Mercurial > repos > blastem
comparison vdp.c @ 477:7fe655d4e2b7
Partial fix for DMA copy
author | Mike Pavone <pavone@retrodev.com> |
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date | Mon, 16 Sep 2013 09:44:22 -0700 |
parents | 5d7bc113653b |
children | 2e4a4188cfb0 |
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476:5d7bc113653b | 477:7fe655d4e2b7 |
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453 return; | 453 return; |
454 } | 454 } |
455 uint16_t read_val; | 455 uint16_t read_val; |
456 uint8_t ran_source = 0, partial = 0; | 456 uint8_t ran_source = 0, partial = 0; |
457 uint16_t dma_len; | 457 uint16_t dma_len; |
458 uint8_t cd = context->cd; | |
458 switch(context->regs[REG_DMASRC_H] & 0xC0) | 459 switch(context->regs[REG_DMASRC_H] & 0xC0) |
459 { | 460 { |
460 //68K -> VDP | 461 //68K -> VDP |
461 case 0: | 462 case 0: |
462 case 0x40: | 463 case 0x40: |
466 } | 467 } |
467 break; | 468 break; |
468 //Copy | 469 //Copy |
469 case 0xC0: | 470 case 0xC0: |
470 if (context->flags & FLAG_UNUSED_SLOT) { | 471 if (context->flags & FLAG_UNUSED_SLOT) { |
471 switch(context->dma_cd & 0xF) | 472 read_val = context->vdpmem[(context->regs[REG_DMASRC_M] << 8) | context->regs[REG_DMASRC_L] ^ 1] | (context->fifo[context->fifo_write].value & 0xFF00); |
472 { | 473 cd = VRAM_WRITE; |
473 case VRAM_WRITE: | 474 partial = 1; |
474 read_val = context->vdpmem[(context->regs[REG_DMASRC_M] << 8) | context->regs[REG_DMASRC_L]]; | |
475 break; | |
476 case CRAM_WRITE: | |
477 read_val = context->cram[context->regs[REG_DMASRC_L] & (CRAM_SIZE-1)]; | |
478 break; | |
479 case VSRAM_WRITE: | |
480 if ((context->regs[REG_DMASRC_L] & 63) < VSRAM_SIZE) { | |
481 read_val = context->vsram[context->regs[REG_DMASRC_L] & 63]; | |
482 } else { | |
483 read_val = 0; | |
484 } | |
485 break; | |
486 } | |
487 ran_source = 1; | 475 ran_source = 1; |
488 context->flags &= ~FLAG_UNUSED_SLOT; | 476 context->flags &= ~FLAG_UNUSED_SLOT; |
489 } | 477 } |
490 break; | 478 break; |
491 case 0x80: | 479 case 0x80: |
498 if (ran_source) { | 486 if (ran_source) { |
499 fifo_entry * cur = context->fifo + context->fifo_write; | 487 fifo_entry * cur = context->fifo + context->fifo_write; |
500 cur->cycle = context->cycles + ((context->latched_mode & BIT_H40) ? 16 : 20)*FIFO_LATENCY; | 488 cur->cycle = context->cycles + ((context->latched_mode & BIT_H40) ? 16 : 20)*FIFO_LATENCY; |
501 cur->address = context->address; | 489 cur->address = context->address; |
502 cur->value = read_val; | 490 cur->value = read_val; |
503 cur->cd = context->cd; | 491 cur->cd = cd; |
504 cur->partial = partial; | 492 cur->partial = partial; |
505 if (context->fifo_read < 0) { | 493 if (context->fifo_read < 0) { |
506 context->fifo_read = context->fifo_write; | 494 context->fifo_read = context->fifo_write; |
507 } | 495 } |
508 context->fifo_write = (context->fifo_write+1) & (FIFO_SIZE-1); | 496 context->fifo_write = (context->fifo_write+1) & (FIFO_SIZE-1); |