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Adjust DMA start delay to not break the FIFO Wait State test in the VDP FIFO Testing ROM
author Michael Pavone <pavone@retrodev.com>
date Sun, 19 Mar 2017 11:17:40 -0700
parents 76e47254596b
children aa1a8eb5bb2b
comparison
equal deleted inserted replaced
1288:94f32d534bed 1289:6ad59a62e656
2484 //DMA copy or 68K -> VDP, transfer starts immediately 2484 //DMA copy or 68K -> VDP, transfer starts immediately
2485 context->dma_cd = context->cd; 2485 context->dma_cd = context->cd;
2486 //printf("DMA start (length: %X) at cycle %d, frame: %d, vcounter: %d, hslot: %d\n", (context->regs[REG_DMALEN_H] << 8) | context->regs[REG_DMALEN_L], context->cycles, context->frame, context->vcounter, context->hslot); 2486 //printf("DMA start (length: %X) at cycle %d, frame: %d, vcounter: %d, hslot: %d\n", (context->regs[REG_DMALEN_H] << 8) | context->regs[REG_DMALEN_L], context->cycles, context->frame, context->vcounter, context->hslot);
2487 if (!(context->regs[REG_DMASRC_H] & 0x80)) { 2487 if (!(context->regs[REG_DMASRC_H] & 0x80)) {
2488 //printf("DMA Address: %X, New CD: %X, Source: %X, Length: %X\n", context->address, context->cd, (context->regs[REG_DMASRC_H] << 17) | (context->regs[REG_DMASRC_M] << 9) | (context->regs[REG_DMASRC_L] << 1), context->regs[REG_DMALEN_H] << 8 | context->regs[REG_DMALEN_L]); 2488 //printf("DMA Address: %X, New CD: %X, Source: %X, Length: %X\n", context->address, context->cd, (context->regs[REG_DMASRC_H] << 17) | (context->regs[REG_DMASRC_M] << 9) | (context->regs[REG_DMASRC_L] << 1), context->regs[REG_DMALEN_H] << 8 | context->regs[REG_DMALEN_L]);
2489 //68K -> VDP DMA takes 4 slots to actually start reading even though it acquires the bus immediately 2489 //68K -> VDP DMA takes a few slots to actually start reading even though it acquires the bus immediately
2490 vdp_run_context(context, context->cycles + 16 * ((context->regs[REG_MODE_2] & BIT_MODE_5) && (context->regs[REG_MODE_4] & BIT_H40) ? 4 : 5)); 2490 //logic analyzer captures made it seem like the proper value is 4 slots, but that seems to cause trouble with the Nemesis' FIFO Wait State test
2491 //only captures are from a direct color DMA demo which will generally start DMA at a very specific point in display so other values are plausible
2492 //sticking with 3 slots for now until I can do some more captures
2493 vdp_run_context(context, context->cycles + 12 * ((context->regs[REG_MODE_2] & BIT_MODE_5) && (context->regs[REG_MODE_4] & BIT_H40) ? 4 : 5));
2491 context->flags |= FLAG_DMA_RUN; 2494 context->flags |= FLAG_DMA_RUN;
2492 return 1; 2495 return 1;
2493 } else { 2496 } else {
2494 context->flags |= FLAG_DMA_RUN; 2497 context->flags |= FLAG_DMA_RUN;
2495 //printf("DMA Copy Address: %X, New CD: %X, Source: %X\n", context->address, context->cd, (context->regs[REG_DMASRC_M] << 8) | context->regs[REG_DMASRC_L]); 2498 //printf("DMA Copy Address: %X, New CD: %X, Source: %X\n", context->address, context->cd, (context->regs[REG_DMASRC_M] << 8) | context->regs[REG_DMASRC_L]);