Mercurial > repos > blastem
comparison vdp.c @ 332:671a5be51522
Update hv counter calculation for clock wonkiness
author | Mike Pavone <pavone@retrodev.com> |
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date | Tue, 14 May 2013 00:28:45 -0700 |
parents | de17e0352f27 |
children | f16136a3835d |
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331:de17e0352f27 | 332:671a5be51522 |
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1149 case 39: | 1149 case 39: |
1150 slot = 2; | 1150 slot = 2; |
1151 inccycles = 20; | 1151 inccycles = 20; |
1152 break; | 1152 break; |
1153 case 59: | 1153 case 59: |
1154 slot = 2; | 1154 slot = 3; |
1155 inccycles = 20; | 1155 inccycles = 20; |
1156 break; | 1156 break; |
1157 case 79: | 1157 case 79: |
1158 slot = 3; | 1158 slot = 4; |
1159 inccycles = 18; | 1159 inccycles = 18; |
1160 break; | 1160 break; |
1161 case 97: | 1161 case 97: |
1162 slot = 4; | |
1163 inccycles = 20; | |
1164 break; | |
1165 case 117: | |
1166 slot = 5; | 1162 slot = 5; |
1167 inccycles = 20; | 1163 inccycles = 20; |
1168 break; | 1164 break; |
1169 case 137: | 1165 case 117: |
1170 slot = 6; | 1166 slot = 6; |
1171 inccycles = 20; | 1167 inccycles = 20; |
1172 break; | 1168 break; |
1169 case 137: | |
1170 slot = 7; | |
1171 inccycles = 20; | |
1172 break; | |
1173 case 157: | 1173 case 157: |
1174 slot = 7; | 1174 slot = 8; |
1175 inccycles = 18; | 1175 inccycles = 18; |
1176 break; | 1176 break; |
1177 case 175: | 1177 case 175: |
1178 slot = 8; | 1178 slot = 9; |
1179 inccycles = 20; | 1179 inccycles = 20; |
1180 break; | 1180 break; |
1181 case 195: | 1181 case 195: |
1182 slot = 9; | 1182 slot = 10; |
1183 inccycles = 20; | 1183 inccycles = 20; |
1184 break; | 1184 break; |
1185 case 215: | 1185 case 215: |
1186 slot = 11; | 1186 slot = 11; |
1187 inccycles = 20; | 1187 inccycles = 20; |
1427 line = (line + 0xFA) & 0xFF; | 1427 line = (line + 0xFA) & 0xFF; |
1428 } | 1428 } |
1429 } | 1429 } |
1430 uint32_t linecyc = context->cycles % MCLKS_LINE; | 1430 uint32_t linecyc = context->cycles % MCLKS_LINE; |
1431 if (context->latched_mode & BIT_H40) { | 1431 if (context->latched_mode & BIT_H40) { |
1432 linecyc /= 8; | 1432 uint32_t slot; |
1433 if (linecyc < MCLKS_SLOT_H40*HSYNC_SLOT_H40) { | |
1434 slot = linecyc/MCLKS_SLOT_H40; | |
1435 } else if(linecyc < MCLK_WEIRD_END) { | |
1436 switch(linecyc-(MCLKS_SLOT_H40*HSYNC_SLOT_H40)) | |
1437 { | |
1438 case 0: | |
1439 slot = 0; | |
1440 break; | |
1441 case 19: | |
1442 slot = 1; | |
1443 break; | |
1444 case 39: | |
1445 slot = 2; | |
1446 break; | |
1447 case 59: | |
1448 slot = 2; | |
1449 break; | |
1450 case 79: | |
1451 slot = 3; | |
1452 break; | |
1453 case 97: | |
1454 slot = 4; | |
1455 break; | |
1456 case 117: | |
1457 slot = 5; | |
1458 break; | |
1459 case 137: | |
1460 slot = 6; | |
1461 break; | |
1462 case 157: | |
1463 slot = 7; | |
1464 break; | |
1465 case 175: | |
1466 slot = 8; | |
1467 break; | |
1468 case 195: | |
1469 slot = 9; | |
1470 break; | |
1471 case 215: | |
1472 slot = 11; | |
1473 break; | |
1474 case 235: | |
1475 slot = 12; | |
1476 break; | |
1477 case 253: | |
1478 slot = 13; | |
1479 break; | |
1480 case 273: | |
1481 slot = 14; | |
1482 break; | |
1483 case 293: | |
1484 slot = 15; | |
1485 break; | |
1486 case 313: | |
1487 slot = 16; | |
1488 break; | |
1489 default: | |
1490 fprintf(stderr, "cycles after weirdness %d\n", linecyc-(MCLKS_SLOT_H40*HSYNC_SLOT_H40)); | |
1491 exit(1); | |
1492 } | |
1493 slot += HSYNC_SLOT_H40; | |
1494 } else { | |
1495 slot = (linecyc-MCLK_WEIRD_END)/MCLKS_SLOT_H40 + SLOT_WEIRD_END; | |
1496 } | |
1497 linecyc = slot * 2; | |
1433 if (linecyc >= 86) { | 1498 if (linecyc >= 86) { |
1434 linecyc -= 86; | 1499 linecyc -= 86; |
1435 } else { | 1500 } else { |
1436 linecyc += 334; | 1501 linecyc += 334; |
1437 } | 1502 } |