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comparison gen_x86.h @ 2053:3414a4423de1 segacd

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Merge from default
author Michael Pavone <pavone@retrodev.com>
date Sat, 15 Jan 2022 13:15:21 -0800
parents e45a317802bd
children 5b308c7b098c
comparison
equal deleted inserted replaced
1692:5dacaef602a7 2053:3414a4423de1
28 R11, 28 R11,
29 R12, 29 R12,
30 R13, 30 R13,
31 R14, 31 R14,
32 R15 32 R15
33 } x86_regs; 33 };
34 34
35 enum { 35 enum {
36 CC_O = 0, 36 CC_O = 0,
37 CC_NO, 37 CC_NO,
38 CC_C, 38 CC_C,
49 CC_NP, 49 CC_NP,
50 CC_L, 50 CC_L,
51 CC_GE, 51 CC_GE,
52 CC_LE, 52 CC_LE,
53 CC_G 53 CC_G
54 } x86_cc; 54 };
55 55
56 enum { 56 enum {
57 SZ_B = 0, 57 SZ_B = 0,
58 SZ_W, 58 SZ_W,
59 SZ_D, 59 SZ_D,
60 SZ_Q 60 SZ_Q
61 } x86_size; 61 };
62 62
63 #ifdef X86_64 63 #ifdef X86_64
64 #define SZ_PTR SZ_Q 64 #define SZ_PTR SZ_Q
65 #define MAX_INST_LEN 14 65 #define MAX_INST_LEN 14
66 #ifdef _WIN32
67 #define FIRST_ARG_REG RCX
68 #define SECOND_ARG_REG RDX
69 #else
70 #define FIRST_ARG_REG RDI
71 #define SECOND_ARG_REG RSI
72 #endif
66 #else 73 #else
67 #define SZ_PTR SZ_D 74 #define SZ_PTR SZ_D
68 #define MAX_INST_LEN 11 75 #define MAX_INST_LEN 11
69 #endif 76 #endif
70 77
76 MODE_REG_DISPLACE32 = 0x80, 83 MODE_REG_DISPLACE32 = 0x80,
77 MODE_REG_INDEXED_DIPSLACE32 = 0x84, 84 MODE_REG_INDEXED_DIPSLACE32 = 0x84,
78 MODE_REG_DIRECT = 0xC0, 85 MODE_REG_DIRECT = 0xC0,
79 //"phony" mode 86 //"phony" mode
80 MODE_IMMED = 0xFF 87 MODE_IMMED = 0xFF
81 } x86_modes; 88 };
82 89
83 void rol_ir(code_info *code, uint8_t val, uint8_t dst, uint8_t size); 90 void rol_ir(code_info *code, uint8_t val, uint8_t dst, uint8_t size);
84 void ror_ir(code_info *code, uint8_t val, uint8_t dst, uint8_t size); 91 void ror_ir(code_info *code, uint8_t val, uint8_t dst, uint8_t size);
85 void rcl_ir(code_info *code, uint8_t val, uint8_t dst, uint8_t size); 92 void rcl_ir(code_info *code, uint8_t val, uint8_t dst, uint8_t size);
86 void rcr_ir(code_info *code, uint8_t val, uint8_t dst, uint8_t size); 93 void rcr_ir(code_info *code, uint8_t val, uint8_t dst, uint8_t size);