Mercurial > repos > blastem
comparison m68k_to_x86.c @ 157:301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
author | Mike Pavone <pavone@retrodev.com> |
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date | Fri, 04 Jan 2013 23:52:20 -0800 |
parents | 3900cfde9dbb |
children | a2ab895d9708 |
comparison
equal
deleted
inserted
replaced
156:3900cfde9dbb | 157:301470eb870b |
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2791 } else { | 2791 } else { |
2792 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_B); | 2792 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_B); |
2793 } | 2793 } |
2794 dst = and_ir(dst, 63, SCRATCH1, SZ_D); | 2794 dst = and_ir(dst, 63, SCRATCH1, SZ_D); |
2795 zero_off = dst+1; | 2795 zero_off = dst+1; |
2796 dst = jcc(dst, CC_NZ, dst+2); | 2796 dst = jcc(dst, CC_Z, dst+2); |
2797 dst = add_rr(dst, SCRATCH1, CYCLES, SZ_D); | 2797 dst = add_rr(dst, SCRATCH1, CYCLES, SZ_D); |
2798 dst = add_rr(dst, SCRATCH1, CYCLES, SZ_D); | 2798 dst = add_rr(dst, SCRATCH1, CYCLES, SZ_D); |
2799 dst = cmp_ir(dst, 32, SCRATCH1, SZ_B); | 2799 dst = cmp_ir(dst, 32, SCRATCH1, SZ_B); |
2800 norm_off = dst+1; | 2800 norm_off = dst+1; |
2801 dst = jcc(dst, CC_L, dst+2); | 2801 dst = jcc(dst, CC_L, dst+2); |
2853 if (inst->src.addr_mode == MODE_UNUSED) { | 2853 if (inst->src.addr_mode == MODE_UNUSED) { |
2854 dst = cycles(dst, BUS); | 2854 dst = cycles(dst, BUS); |
2855 //Memory rotate | 2855 //Memory rotate |
2856 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B); | 2856 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B); |
2857 if (inst->op == M68K_ROXL) { | 2857 if (inst->op == M68K_ROXL) { |
2858 dst = rol_ir(dst, 1, dst_op.base, inst->extra.size); | 2858 dst = rcl_ir(dst, 1, dst_op.base, inst->extra.size); |
2859 } else { | 2859 } else { |
2860 dst = ror_ir(dst, 1, dst_op.base, inst->extra.size); | 2860 dst = rcr_ir(dst, 1, dst_op.base, inst->extra.size); |
2861 } | 2861 } |
2862 dst = setcc_r(dst, CC_C, FLAG_C); | 2862 dst = setcc_r(dst, CC_C, FLAG_C); |
2863 dst = cmp_ir(dst, 0, dst_op.base, inst->extra.size); | 2863 dst = cmp_ir(dst, 0, dst_op.base, inst->extra.size); |
2864 dst = setcc_r(dst, CC_Z, FLAG_Z); | 2864 dst = setcc_r(dst, CC_Z, FLAG_Z); |
2865 dst = setcc_r(dst, CC_S, FLAG_N); | 2865 dst = setcc_r(dst, CC_S, FLAG_N); |
2868 if (src_op.mode == MODE_IMMED) { | 2868 if (src_op.mode == MODE_IMMED) { |
2869 dst = cycles(dst, (inst->extra.size == OPSIZE_LONG ? 8 : 6) + src_op.disp*2); | 2869 dst = cycles(dst, (inst->extra.size == OPSIZE_LONG ? 8 : 6) + src_op.disp*2); |
2870 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B); | 2870 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B); |
2871 if (dst_op.mode == MODE_REG_DIRECT) { | 2871 if (dst_op.mode == MODE_REG_DIRECT) { |
2872 if (inst->op == M68K_ROXL) { | 2872 if (inst->op == M68K_ROXL) { |
2873 dst = rol_ir(dst, src_op.disp, dst_op.base, inst->extra.size); | 2873 dst = rcl_ir(dst, src_op.disp, dst_op.base, inst->extra.size); |
2874 } else { | 2874 } else { |
2875 dst = ror_ir(dst, src_op.disp, dst_op.base, inst->extra.size); | 2875 dst = rcr_ir(dst, src_op.disp, dst_op.base, inst->extra.size); |
2876 } | 2876 } |
2877 } else { | 2877 } else { |
2878 if (inst->op == M68K_ROXL) { | 2878 if (inst->op == M68K_ROXL) { |
2879 dst = rol_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); | 2879 dst = rcl_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); |
2880 } else { | 2880 } else { |
2881 dst = ror_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); | 2881 dst = rcr_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); |
2882 } | 2882 } |
2883 } | 2883 } |
2884 dst = setcc_r(dst, CC_C, FLAG_C); | 2884 dst = setcc_r(dst, CC_C, FLAG_C); |
2885 } else { | 2885 } else { |
2886 if (src_op.mode == MODE_REG_DIRECT) { | 2886 if (src_op.mode == MODE_REG_DIRECT) { |
2890 } else { | 2890 } else { |
2891 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_B); | 2891 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_B); |
2892 } | 2892 } |
2893 dst = and_ir(dst, 63, SCRATCH1, SZ_D); | 2893 dst = and_ir(dst, 63, SCRATCH1, SZ_D); |
2894 zero_off = dst+1; | 2894 zero_off = dst+1; |
2895 dst = jcc(dst, CC_NZ, dst+2); | 2895 dst = jcc(dst, CC_Z, dst+2); |
2896 dst = add_rr(dst, SCRATCH1, CYCLES, SZ_D); | 2896 dst = add_rr(dst, SCRATCH1, CYCLES, SZ_D); |
2897 dst = add_rr(dst, SCRATCH1, CYCLES, SZ_D); | 2897 dst = add_rr(dst, SCRATCH1, CYCLES, SZ_D); |
2898 dst = cmp_ir(dst, 32, SCRATCH1, SZ_B); | 2898 dst = cmp_ir(dst, 32, SCRATCH1, SZ_B); |
2899 norm_off = dst+1; | 2899 norm_off = dst+1; |
2900 dst = jcc(dst, CC_L, dst+2); | 2900 dst = jcc(dst, CC_L, dst+2); |
2901 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B); | 2901 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B); |
2902 if (dst_op.mode == MODE_REG_DIRECT) { | 2902 if (dst_op.mode == MODE_REG_DIRECT) { |
2903 if (inst->op == M68K_ROXL) { | 2903 if (inst->op == M68K_ROXL) { |
2904 dst = rol_ir(dst, 31, dst_op.base, inst->extra.size); | 2904 dst = rcl_ir(dst, 31, dst_op.base, inst->extra.size); |
2905 dst = rol_ir(dst, 1, dst_op.base, inst->extra.size); | 2905 dst = rcl_ir(dst, 1, dst_op.base, inst->extra.size); |
2906 } else { | 2906 } else { |
2907 dst = ror_ir(dst, 31, dst_op.base, inst->extra.size); | 2907 dst = rcr_ir(dst, 31, dst_op.base, inst->extra.size); |
2908 dst = ror_ir(dst, 1, dst_op.base, inst->extra.size); | 2908 dst = rcr_ir(dst, 1, dst_op.base, inst->extra.size); |
2909 } | 2909 } |
2910 } else { | 2910 } else { |
2911 if (inst->op == M68K_ROXL) { | 2911 if (inst->op == M68K_ROXL) { |
2912 dst = rol_irdisp8(dst, 31, dst_op.base, dst_op.disp, inst->extra.size); | 2912 dst = rcl_irdisp8(dst, 31, dst_op.base, dst_op.disp, inst->extra.size); |
2913 dst = rol_irdisp8(dst, 1, dst_op.base, dst_op.disp, inst->extra.size); | 2913 dst = rcl_irdisp8(dst, 1, dst_op.base, dst_op.disp, inst->extra.size); |
2914 } else { | 2914 } else { |
2915 dst = ror_irdisp8(dst, 31, dst_op.base, dst_op.disp, inst->extra.size); | 2915 dst = rcr_irdisp8(dst, 31, dst_op.base, dst_op.disp, inst->extra.size); |
2916 dst = ror_irdisp8(dst, 1, dst_op.base, dst_op.disp, inst->extra.size); | 2916 dst = rcr_irdisp8(dst, 1, dst_op.base, dst_op.disp, inst->extra.size); |
2917 } | 2917 } |
2918 } | 2918 } |
2919 dst = sub_ir(dst, 32, SCRATCH1, SZ_B); | 2919 dst = sub_ir(dst, 32, SCRATCH1, SZ_B); |
2920 *norm_off = dst - (norm_off+1); | 2920 *norm_off = dst - (norm_off+1); |
2921 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B); | 2921 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B); |
2922 if (dst_op.mode == MODE_REG_DIRECT) { | 2922 if (dst_op.mode == MODE_REG_DIRECT) { |
2923 if (inst->op == M68K_ROXL) { | 2923 if (inst->op == M68K_ROXL) { |
2924 dst = rol_clr(dst, dst_op.base, inst->extra.size); | 2924 dst = rcl_clr(dst, dst_op.base, inst->extra.size); |
2925 } else { | 2925 } else { |
2926 dst = ror_clr(dst, dst_op.base, inst->extra.size); | 2926 dst = rcr_clr(dst, dst_op.base, inst->extra.size); |
2927 } | 2927 } |
2928 } else { | 2928 } else { |
2929 if (inst->op == M68K_ROXL) { | 2929 if (inst->op == M68K_ROXL) { |
2930 dst = rol_clrdisp8(dst, dst_op.base, dst_op.disp, inst->extra.size); | 2930 dst = rcl_clrdisp8(dst, dst_op.base, dst_op.disp, inst->extra.size); |
2931 } else { | 2931 } else { |
2932 dst = ror_clrdisp8(dst, dst_op.base, dst_op.disp, inst->extra.size); | 2932 dst = rcr_clrdisp8(dst, dst_op.base, dst_op.disp, inst->extra.size); |
2933 } | 2933 } |
2934 } | 2934 } |
2935 dst = setcc_r(dst, CC_C, FLAG_C); | 2935 dst = setcc_r(dst, CC_C, FLAG_C); |
2936 end_off = dst + 1; | 2936 end_off = dst + 1; |
2937 dst = jmp(dst, dst+2); | 2937 dst = jmp(dst, dst+2); |