Mercurial > repos > blastem
comparison vdp.c @ 884:252dfd29831d
Selecting a second game from the menu now works
author | Michael Pavone <pavone@retrodev.com> |
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date | Fri, 13 Nov 2015 22:56:59 -0800 |
parents | ac65086c031e |
children | e64168bb2b25 |
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883:9f149f0e98b7 | 884:252dfd29831d |
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136 } | 136 } |
137 } | 137 } |
138 if (region_pal) { | 138 if (region_pal) { |
139 context->flags2 |= FLAG2_REGION_PAL; | 139 context->flags2 |= FLAG2_REGION_PAL; |
140 } | 140 } |
141 } | |
142 | |
143 void vdp_free(vdp_context *context) | |
144 { | |
145 free(context->vdpmem); | |
146 free(context->linebuf); | |
147 if (headless) { | |
148 free(context->oddbuf); | |
149 free(context->evenbuf); | |
150 } else { | |
151 render_free_surfaces(context); | |
152 } | |
153 free(context); | |
141 } | 154 } |
142 | 155 |
143 int is_refresh(vdp_context * context, uint32_t slot) | 156 int is_refresh(vdp_context * context, uint32_t slot) |
144 { | 157 { |
145 if (context->regs[REG_MODE_4] & BIT_H40) { | 158 if (context->regs[REG_MODE_4] & BIT_H40) { |
845 colors += CRAM_SIZE; | 858 colors += CRAM_SIZE; |
846 } else if (intensity == BUF_BIT_PRIORITY*2) { | 859 } else if (intensity == BUF_BIT_PRIORITY*2) { |
847 src |= DBG_HILIGHT; | 860 src |= DBG_HILIGHT; |
848 colors += CRAM_SIZE*2; | 861 colors += CRAM_SIZE*2; |
849 } | 862 } |
850 | 863 |
851 uint32_t outpixel; | 864 uint32_t outpixel; |
852 if (context->debug) { | 865 if (context->debug) { |
853 outpixel = context->debugcolors[src]; | 866 outpixel = context->debugcolors[src]; |
854 } else { | 867 } else { |
855 outpixel = colors[pixel & 0x3F]; | 868 outpixel = colors[pixel & 0x3F]; |
947 context->vcounter = 0x1CA; | 960 context->vcounter = 0x1CA; |
948 } | 961 } |
949 } else if (!(context->latched_mode & BIT_PAL) && context->vcounter == 0xEB) { | 962 } else if (!(context->latched_mode & BIT_PAL) && context->vcounter == 0xEB) { |
950 context->vcounter = 0x1E5; | 963 context->vcounter = 0x1E5; |
951 } | 964 } |
952 | 965 |
953 if (context->vcounter > (context->latched_mode & BIT_PAL ? PAL_INACTIVE_START : NTSC_INACTIVE_START)) { | 966 if (context->vcounter > (context->latched_mode & BIT_PAL ? PAL_INACTIVE_START : NTSC_INACTIVE_START)) { |
954 context->hint_counter = context->regs[REG_HINT]; | 967 context->hint_counter = context->regs[REG_HINT]; |
955 } else if (context->hint_counter) { | 968 } else if (context->hint_counter) { |
956 context->hint_counter--; | 969 context->hint_counter--; |
957 } else { | 970 } else { |
1018 render_map_output(context->vcounter, column, context);\ | 1031 render_map_output(context->vcounter, column, context);\ |
1019 if (column == 40 || (column == 32 && startcyc == 124)) {\ | 1032 if (column == 40 || (column == 32 && startcyc == 124)) {\ |
1020 vdp_advance_line(context);\ | 1033 vdp_advance_line(context);\ |
1021 }\ | 1034 }\ |
1022 CHECK_LIMIT | 1035 CHECK_LIMIT |
1023 | 1036 |
1024 #define SPRITE_RENDER_H40(slot) \ | 1037 #define SPRITE_RENDER_H40(slot) \ |
1025 case slot:\ | 1038 case slot:\ |
1026 render_sprite_cells( context);\ | 1039 render_sprite_cells( context);\ |
1027 scan_sprite_table(context->vcounter, context);\ | 1040 scan_sprite_table(context->vcounter, context);\ |
1028 if (context->flags & FLAG_DMA_RUN) { run_dma_src(context, context->hslot); } \ | 1041 if (context->flags & FLAG_DMA_RUN) { run_dma_src(context, context->hslot); } \ |
1036 } else {\ | 1049 } else {\ |
1037 context->cycles += slot_cycles;\ | 1050 context->cycles += slot_cycles;\ |
1038 }\ | 1051 }\ |
1039 }\ | 1052 }\ |
1040 CHECK_ONLY | 1053 CHECK_ONLY |
1041 | 1054 |
1042 #define SPRITE_RENDER_H32(slot) \ | 1055 #define SPRITE_RENDER_H32(slot) \ |
1043 case slot:\ | 1056 case slot:\ |
1044 render_sprite_cells( context);\ | 1057 render_sprite_cells( context);\ |
1045 scan_sprite_table(context->vcounter, context);\ | 1058 scan_sprite_table(context->vcounter, context);\ |
1046 if (context->flags & FLAG_DMA_RUN) { run_dma_src(context, context->hslot); } \ | 1059 if (context->flags & FLAG_DMA_RUN) { run_dma_src(context, context->hslot); } \ |
1049 } else {\ | 1062 } else {\ |
1050 context->hslot++;\ | 1063 context->hslot++;\ |
1051 }\ | 1064 }\ |
1052 context->cycles += slot_cycles;\ | 1065 context->cycles += slot_cycles;\ |
1053 CHECK_ONLY | 1066 CHECK_ONLY |
1054 | 1067 |
1055 | 1068 |
1056 void vdp_h40(vdp_context * context, uint32_t target_cycles) | 1069 void vdp_h40(vdp_context * context, uint32_t target_cycles) |
1057 { | 1070 { |
1058 uint16_t address; | 1071 uint16_t address; |
1059 uint32_t mask; | 1072 uint32_t mask; |
1682 if ( | 1695 if ( |
1683 ( | 1696 ( |
1684 line > inactive_start | 1697 line > inactive_start |
1685 && line < 0x1FF | 1698 && line < 0x1FF |
1686 ) | 1699 ) |
1687 || (line == inactive_start | 1700 || (line == inactive_start |
1688 && ( | 1701 && ( |
1689 slot >= (context->regs[REG_MODE_4] & BIT_H40 ? VBLANK_START_H40 : VBLANK_START_H32) | 1702 slot >= (context->regs[REG_MODE_4] & BIT_H40 ? VBLANK_START_H40 : VBLANK_START_H32) |
1690 || slot < (context->regs[REG_MODE_4] & BIT_H40 ? LINE_CHANGE_H40 : LINE_CHANGE_H32) | 1703 || slot < (context->regs[REG_MODE_4] & BIT_H40 ? LINE_CHANGE_H40 : LINE_CHANGE_H32) |
1691 ) | 1704 ) |
1692 ) | 1705 ) |