Mercurial > repos > blastem
comparison vdp.c @ 924:1b86268a4cb3
Change the sentinel value for the hslot parameter of run_dma_src to something that is not a valid slot number and actually use it for calls during the active display period
author | Michael Pavone <pavone@retrodev.com> |
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date | Tue, 02 Feb 2016 18:33:00 -0800 |
parents | 8e012ece95c1 |
children | 7f4a7f07f325 |
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923:8e012ece95c1 | 924:1b86268a4cb3 |
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512 } else { | 512 } else { |
513 context->flags |= FLAG_UNUSED_SLOT; | 513 context->flags |= FLAG_UNUSED_SLOT; |
514 } | 514 } |
515 } | 515 } |
516 | 516 |
517 void run_dma_src(vdp_context * context, uint32_t slot) | 517 void run_dma_src(vdp_context * context, int32_t slot) |
518 { | 518 { |
519 //TODO: Figure out what happens if CD bit 4 is not set in DMA copy mode | 519 //TODO: Figure out what happens if CD bit 4 is not set in DMA copy mode |
520 //TODO: Figure out what happens when CD:0-3 is not set to a write mode in DMA operations | 520 //TODO: Figure out what happens when CD:0-3 is not set to a write mode in DMA operations |
521 //TODO: Figure out what happens if DMA gets disabled part way through a DMA fill or DMA copy | 521 //TODO: Figure out what happens if DMA gets disabled part way through a DMA fill or DMA copy |
522 if (context->fifo_write == context->fifo_read) { | 522 if (context->fifo_write == context->fifo_read) { |
526 switch(context->regs[REG_DMASRC_H] & 0xC0) | 526 switch(context->regs[REG_DMASRC_H] & 0xC0) |
527 { | 527 { |
528 //68K -> VDP | 528 //68K -> VDP |
529 case 0: | 529 case 0: |
530 case 0x40: | 530 case 0x40: |
531 if (!slot || !is_refresh(context, slot-1)) { | 531 if (slot == -1 || !is_refresh(context, slot-1)) { |
532 cur = context->fifo + context->fifo_write; | 532 cur = context->fifo + context->fifo_write; |
533 cur->cycle = context->cycles + ((context->regs[REG_MODE_4] & BIT_H40) ? 16 : 20)*FIFO_LATENCY; | 533 cur->cycle = context->cycles + ((context->regs[REG_MODE_4] & BIT_H40) ? 16 : 20)*FIFO_LATENCY; |
534 cur->address = context->address; | 534 cur->address = context->address; |
535 cur->value = read_dma_value((context->regs[REG_DMASRC_H] << 16) | (context->regs[REG_DMASRC_M] << 8) | context->regs[REG_DMASRC_L]); | 535 cur->value = read_dma_value((context->regs[REG_DMASRC_H] << 16) | (context->regs[REG_DMASRC_M] << 8) | context->regs[REG_DMASRC_L]); |
536 cur->cd = context->cd; | 536 cur->cd = context->cd; |
973 context->hint_counter = context->regs[REG_HINT]; | 973 context->hint_counter = context->regs[REG_HINT]; |
974 } | 974 } |
975 } | 975 } |
976 | 976 |
977 #define CHECK_ONLY if (context->cycles >= target_cycles) { return; } | 977 #define CHECK_ONLY if (context->cycles >= target_cycles) { return; } |
978 #define CHECK_LIMIT if (context->flags & FLAG_DMA_RUN) { run_dma_src(context, context->hslot); } context->hslot++; context->cycles += slot_cycles; CHECK_ONLY | 978 #define CHECK_LIMIT if (context->flags & FLAG_DMA_RUN) { run_dma_src(context, -1); } context->hslot++; context->cycles += slot_cycles; CHECK_ONLY |
979 | 979 |
980 #define COLUMN_RENDER_BLOCK(column, startcyc) \ | 980 #define COLUMN_RENDER_BLOCK(column, startcyc) \ |
981 case startcyc:\ | 981 case startcyc:\ |
982 read_map_scroll_a(column, context->vcounter, context);\ | 982 read_map_scroll_a(column, context->vcounter, context);\ |
983 CHECK_LIMIT\ | 983 CHECK_LIMIT\ |
1033 | 1033 |
1034 #define SPRITE_RENDER_H40(slot) \ | 1034 #define SPRITE_RENDER_H40(slot) \ |
1035 case slot:\ | 1035 case slot:\ |
1036 render_sprite_cells( context);\ | 1036 render_sprite_cells( context);\ |
1037 scan_sprite_table(context->vcounter, context);\ | 1037 scan_sprite_table(context->vcounter, context);\ |
1038 if (context->flags & FLAG_DMA_RUN) { run_dma_src(context, context->hslot); } \ | 1038 if (context->flags & FLAG_DMA_RUN) { run_dma_src(context, -1); } \ |
1039 if (slot == 182) {\ | 1039 if (slot == 182) {\ |
1040 context->hslot = 229;\ | 1040 context->hslot = 229;\ |
1041 context->cycles += h40_hsync_cycles[0];\ | 1041 context->cycles += h40_hsync_cycles[0];\ |
1042 } else {\ | 1042 } else {\ |
1043 context->hslot++;\ | 1043 context->hslot++;\ |
1051 | 1051 |
1052 #define SPRITE_RENDER_H32(slot) \ | 1052 #define SPRITE_RENDER_H32(slot) \ |
1053 case slot:\ | 1053 case slot:\ |
1054 render_sprite_cells( context);\ | 1054 render_sprite_cells( context);\ |
1055 scan_sprite_table(context->vcounter, context);\ | 1055 scan_sprite_table(context->vcounter, context);\ |
1056 if (context->flags & FLAG_DMA_RUN) { run_dma_src(context, context->hslot); } \ | 1056 if (context->flags & FLAG_DMA_RUN) { run_dma_src(context, -1); } \ |
1057 if (slot == 147) {\ | 1057 if (slot == 147) {\ |
1058 context->hslot = 233;\ | 1058 context->hslot = 233;\ |
1059 } else {\ | 1059 } else {\ |
1060 context->hslot++;\ | 1060 context->hslot++;\ |
1061 }\ | 1061 }\ |
1123 } | 1123 } |
1124 address += (context->vcounter & mask) * 4; | 1124 address += (context->vcounter & mask) * 4; |
1125 context->hscroll_a = context->vdpmem[address] << 8 | context->vdpmem[address+1]; | 1125 context->hscroll_a = context->vdpmem[address] << 8 | context->vdpmem[address+1]; |
1126 context->hscroll_b = context->vdpmem[address+2] << 8 | context->vdpmem[address+3]; | 1126 context->hscroll_b = context->vdpmem[address+2] << 8 | context->vdpmem[address+3]; |
1127 //printf("%d: HScroll A: %d, HScroll B: %d\n", context->vcounter, context->hscroll_a, context->hscroll_b); | 1127 //printf("%d: HScroll A: %d, HScroll B: %d\n", context->vcounter, context->hscroll_a, context->hscroll_b); |
1128 if (context->flags & FLAG_DMA_RUN) { run_dma_src(context, context->hslot); } | 1128 if (context->flags & FLAG_DMA_RUN) { run_dma_src(context, -1); } |
1129 context->hslot++; | 1129 context->hslot++; |
1130 context->cycles += h40_hsync_cycles[14]; | 1130 context->cycles += h40_hsync_cycles[14]; |
1131 CHECK_ONLY | 1131 CHECK_ONLY |
1132 //!HSYNC high | 1132 //!HSYNC high |
1133 SPRITE_RENDER_H40(243) | 1133 SPRITE_RENDER_H40(243) |
1139 CHECK_LIMIT | 1139 CHECK_LIMIT |
1140 SPRITE_RENDER_H40(248) | 1140 SPRITE_RENDER_H40(248) |
1141 case 249: | 1141 case 249: |
1142 render_map_1(context); | 1142 render_map_1(context); |
1143 scan_sprite_table(context->vcounter, context);//Just a guess | 1143 scan_sprite_table(context->vcounter, context);//Just a guess |
1144 if (context->flags & FLAG_DMA_RUN) { run_dma_src(context, context->hslot); } | |
1145 CHECK_LIMIT | 1144 CHECK_LIMIT |
1146 case 250: | 1145 case 250: |
1147 render_map_2(context); | 1146 render_map_2(context); |
1148 scan_sprite_table(context->vcounter, context);//Just a guess | 1147 scan_sprite_table(context->vcounter, context);//Just a guess |
1149 CHECK_LIMIT | 1148 CHECK_LIMIT |