Mercurial > repos > blastem
comparison vdp.c @ 983:14d2f3b0e45d
Fixes to the DMA busy flag and DMA fill. Now up to 120/122 on VDP FIFO Testing.
author | Michael Pavone <pavone@retrodev.com> |
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date | Sun, 24 Apr 2016 11:53:59 -0700 |
parents | 902c53d9c16f |
children | bd4d698d995b |
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982:f7bbbf49db4e | 983:14d2f3b0e45d |
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518 | 518 |
519 break; | 519 break; |
520 } | 520 } |
521 context->fifo_read = (context->fifo_read+1) & (FIFO_SIZE-1); | 521 context->fifo_read = (context->fifo_read+1) & (FIFO_SIZE-1); |
522 if (context->fifo_read == context->fifo_write) { | 522 if (context->fifo_read == context->fifo_write) { |
523 if ((context->cd & 0x20) && (context->regs[REG_DMASRC_H] & 0xC0) == 0x80) { | |
524 context->flags |= FLAG_DMA_RUN; | |
525 } | |
523 context->fifo_read = -1; | 526 context->fifo_read = -1; |
524 } | 527 } |
525 } else if ((context->flags & FLAG_DMA_RUN) && (context->regs[REG_DMASRC_H] & 0xC0) == 0xC0) { | 528 } else if ((context->flags & FLAG_DMA_RUN) && (context->regs[REG_DMASRC_H] & 0xC0) == 0xC0) { |
526 if (context->flags & FLAG_READ_FETCHED) { | 529 if (context->flags & FLAG_READ_FETCHED) { |
527 context->vdpmem[context->address ^ 1] = context->prefetch; | 530 context->vdpmem[context->address ^ 1] = context->prefetch; |
1587 if (context->flags & FLAG_DMA_RUN) { | 1590 if (context->flags & FLAG_DMA_RUN) { |
1588 return -1; | 1591 return -1; |
1589 } | 1592 } |
1590 if (context->flags & FLAG_PENDING) { | 1593 if (context->flags & FLAG_PENDING) { |
1591 context->address = (context->address & 0x3FFF) | (value << 14); | 1594 context->address = (context->address & 0x3FFF) | (value << 14); |
1592 context->cd = (context->cd & 0x3) | ((value >> 2) & 0x3C); | 1595 //It seems like the DMA enable bit doesn't so much enable DMA so much |
1596 //as it enables changing CD5 from control port writes | |
1597 uint8_t preserve = (context->regs[REG_MODE_2] & BIT_DMA_ENABLE) ? 0x3 : 0x23; | |
1598 context->cd = (context->cd & preserve) | ((value >> 2) & ~preserve & 0xFF); | |
1593 context->flags &= ~FLAG_PENDING; | 1599 context->flags &= ~FLAG_PENDING; |
1594 //Should these be taken care of here or after the first write? | 1600 //Should these be taken care of here or after the first write? |
1595 context->flags &= ~FLAG_READ_FETCHED; | 1601 context->flags &= ~FLAG_READ_FETCHED; |
1596 context->flags2 &= ~FLAG2_READ_PENDING; | 1602 context->flags2 &= ~FLAG2_READ_PENDING; |
1597 //printf("New Address: %X, New CD: %X\n", context->address, context->cd); | 1603 //printf("New Address: %X, New CD: %X\n", context->address, context->cd); |
1598 if (context->cd & 0x20 && (context->regs[REG_MODE_2] & BIT_DMA_ENABLE)) { | 1604 if (context->cd & 0x20) { |
1599 // | 1605 // |
1600 if((context->regs[REG_DMASRC_H] & 0xC0) != 0x80) { | 1606 if((context->regs[REG_DMASRC_H] & 0xC0) != 0x80) { |
1601 //DMA copy or 68K -> VDP, transfer starts immediately | 1607 //DMA copy or 68K -> VDP, transfer starts immediately |
1602 context->flags |= FLAG_DMA_RUN; | 1608 context->flags |= FLAG_DMA_RUN; |
1603 context->dma_cd = context->cd; | 1609 context->dma_cd = context->cd; |
1631 if (reg == REG_MODE_4) { | 1637 if (reg == REG_MODE_4) { |
1632 context->double_res = (value & (BIT_INTERLACE | BIT_DOUBLE_RES)) == (BIT_INTERLACE | BIT_DOUBLE_RES); | 1638 context->double_res = (value & (BIT_INTERLACE | BIT_DOUBLE_RES)) == (BIT_INTERLACE | BIT_DOUBLE_RES); |
1633 if (!context->double_res) { | 1639 if (!context->double_res) { |
1634 context->framebuf = context->oddbuf; | 1640 context->framebuf = context->oddbuf; |
1635 } | 1641 } |
1636 } | 1642 } |
1637 context->cd &= 0x3C; | 1643 context->cd &= 0x3C; |
1638 } | 1644 } |
1639 } else { | 1645 } else { |
1640 context->flags |= FLAG_PENDING; | 1646 context->flags |= FLAG_PENDING; |
1641 context->address = (context->address &0xC000) | (value & 0x3FFF); | 1647 context->address = (context->address &0xC000) | (value & 0x3FFF); |
1671 } | 1677 } |
1672 fifo_entry * cur = context->fifo + context->fifo_write; | 1678 fifo_entry * cur = context->fifo + context->fifo_write; |
1673 cur->cycle = context->cycles + ((context->regs[REG_MODE_4] & BIT_H40) ? 16 : 20)*FIFO_LATENCY; | 1679 cur->cycle = context->cycles + ((context->regs[REG_MODE_4] & BIT_H40) ? 16 : 20)*FIFO_LATENCY; |
1674 cur->address = context->address; | 1680 cur->address = context->address; |
1675 cur->value = value; | 1681 cur->value = value; |
1676 if (context->cd & 0x20 && (context->regs[REG_DMASRC_H] & 0xC0) == 0x80 && (context->regs[REG_MODE_2] & BIT_DMA_ENABLE)) { | |
1677 context->flags |= FLAG_DMA_RUN; | |
1678 } | |
1679 cur->cd = context->cd; | 1682 cur->cd = context->cd; |
1680 cur->partial = 0; | 1683 cur->partial = 0; |
1681 if (context->fifo_read < 0) { | 1684 if (context->fifo_read < 0) { |
1682 context->fifo_read = context->fifo_write; | 1685 context->fifo_read = context->fifo_write; |
1683 } | 1686 } |
1729 } else { | 1732 } else { |
1730 if (slot < HBLANK_END_H32 || slot > HBLANK_START_H32) { | 1733 if (slot < HBLANK_END_H32 || slot > HBLANK_START_H32) { |
1731 value |= 0x4; | 1734 value |= 0x4; |
1732 } | 1735 } |
1733 } | 1736 } |
1734 if (context->flags & FLAG_DMA_RUN) { | 1737 if (context->cd & 0x20) { |
1735 value |= 0x2; | 1738 value |= 0x2; |
1736 } | 1739 } |
1737 if (context->flags2 & FLAG2_REGION_PAL) { | 1740 if (context->flags2 & FLAG2_REGION_PAL) { |
1738 value |= 0x1; | 1741 value |= 0x1; |
1739 } | 1742 } |