Mercurial > repos > blastem
comparison vdp.c @ 473:1358045c0bdd
Implement undocumented 8-bit VRAM read
author | Mike Pavone <pavone@retrodev.com> |
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date | Sun, 15 Sep 2013 23:00:17 -0700 |
parents | 93dc0382fd70 |
children | e128e55710bd |
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472:93dc0382fd70 | 473:1358045c0bdd |
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376 context->colors[addr] = color_map[value & 0xEEE]; | 376 context->colors[addr] = color_map[value & 0xEEE]; |
377 context->colors[addr + CRAM_SIZE] = color_map[(value & 0xEEE) | FBUF_SHADOW]; | 377 context->colors[addr + CRAM_SIZE] = color_map[(value & 0xEEE) | FBUF_SHADOW]; |
378 context->colors[addr + CRAM_SIZE*2] = color_map[(value & 0xEEE) | FBUF_HILIGHT]; | 378 context->colors[addr + CRAM_SIZE*2] = color_map[(value & 0xEEE) | FBUF_HILIGHT]; |
379 } | 379 } |
380 | 380 |
381 #define VRAM_READ 0 | 381 #define VRAM_READ 0 //0000 |
382 #define VRAM_WRITE 1 | 382 #define VRAM_WRITE 1 //0001 |
383 #define CRAM_READ 8 | 383 //2 would trigger register write 0010 |
384 #define CRAM_WRITE 3 | 384 #define CRAM_WRITE 3 //0011 |
385 #define VSRAM_READ 4 | 385 #define VSRAM_READ 4 //0100 |
386 #define VSRAM_WRITE 5 | 386 #define VSRAM_WRITE 5//0101 |
387 //6 would trigger regsiter write 0110 | |
388 //7 is a mystery | |
389 #define CRAM_READ 8 //1000 | |
390 //9 is also a mystery //1001 | |
391 //A would trigger register write 1010 | |
392 //B is a mystery 1011 | |
393 #define VRAM_READ8 0xC //1100 | |
394 //D is a mystery 1101 | |
395 //E would trigger register write 1110 | |
396 //F is a mystery 1111 | |
387 #define DMA_START 0x20 | 397 #define DMA_START 0x20 |
388 | 398 |
389 void external_slot(vdp_context * context) | 399 void external_slot(vdp_context * context) |
390 { | 400 { |
391 fifo_entry * start = context->fifo + context->fifo_read; | 401 fifo_entry * start = context->fifo + context->fifo_read; |
1589 while (!(context->flags & FLAG_UNUSED_SLOT)) { | 1599 while (!(context->flags & FLAG_UNUSED_SLOT)) { |
1590 vdp_run_context(context, context->cycles + ((context->latched_mode & BIT_H40) ? 16 : 20)); | 1600 vdp_run_context(context, context->cycles + ((context->latched_mode & BIT_H40) ? 16 : 20)); |
1591 } | 1601 } |
1592 value |= context->vdpmem[context->address | 1]; | 1602 value |= context->vdpmem[context->address | 1]; |
1593 break; | 1603 break; |
1604 case VRAM_READ8: | |
1605 value = context->vdpmem[context->address ^ 1]; | |
1606 value |= context->fifo[context->fifo_write].value & 0xFF00; | |
1607 break; | |
1594 case CRAM_READ: | 1608 case CRAM_READ: |
1595 value = context->cram[(context->address/2) & (CRAM_SIZE-1)] & CRAM_BITS; | 1609 value = context->cram[(context->address/2) & (CRAM_SIZE-1)] & CRAM_BITS; |
1596 value |= context->fifo[context->fifo_write].value & ~CRAM_BITS; | 1610 value |= context->fifo[context->fifo_write].value & ~CRAM_BITS; |
1597 break; | 1611 break; |
1598 case VSRAM_READ: | 1612 case VSRAM_READ: |