Mercurial > repos > blastem

comparison z80_to_x86.c @ 1051:11ff5726fd5e

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
Implement undocumented flag bits for block CP instructions
author Michael Pavone <pavone@retrodev.com>
date Fri, 29 Jul 2016 00:17:40 -0700
parents d06c947a9a77
children 366c28ac6c55
comparison
equal deleted inserted replaced
1050:d06c947a9a77 1051:11ff5726fd5e
699 sub_ir(code, 1, opts->regs[Z80_BC], SZ_W); 699 sub_ir(code, 1, opts->regs[Z80_BC], SZ_W);
700 } else { 700 } else {
701 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_BC), SZ_W); 701 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_BC), SZ_W);
702 } 702 }
703 setcc_rdisp(code, CC_NZ, opts->gen.context_reg, zf_off(ZF_PV)); 703 setcc_rdisp(code, CC_NZ, opts->gen.context_reg, zf_off(ZF_PV));
704 mov_rr(code, opts->regs[Z80_A], opts->gen.scratch2, SZ_B);
705 sub_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B);
706 sub_rdispr(code, opts->gen.context_reg, zf_off(ZF_H), opts->gen.scratch2, SZ_B);
707 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
708 shl_ir(code, 4, opts->gen.scratch2, SZ_B);
709 and_irdisp(code, 0x8, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
710 and_ir(code, 0x20, opts->gen.scratch2, SZ_B);
711 or_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
704 break; 712 break;
705 case Z80_CPIR: { 713 case Z80_CPIR: {
706 cycles(&opts->gen, num_cycles);//T-States 4,4 714 cycles(&opts->gen, num_cycles);//T-States 4,4
707 zreg_to_native(opts, Z80_HL, opts->gen.scratch1); 715 zreg_to_native(opts, Z80_HL, opts->gen.scratch1);
708 call(code, opts->read_8);//T-States 3 716 call(code, opts->read_8);//T-States 3
719 if (opts->regs[Z80_HL] >= 0) { 727 if (opts->regs[Z80_HL] >= 0) {
720 add_ir(code, 1, opts->regs[Z80_HL], SZ_W); 728 add_ir(code, 1, opts->regs[Z80_HL], SZ_W);
721 } else { 729 } else {
722 add_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_W); 730 add_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_W);
723 } 731 }
732 mov_rr(code, opts->regs[Z80_A], opts->gen.scratch2, SZ_B);
733 sub_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B);
734 sub_rdispr(code, opts->gen.context_reg, zf_off(ZF_H), opts->gen.scratch2, SZ_B);
735 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
736 shl_ir(code, 4, opts->gen.scratch2, SZ_B);
737 and_irdisp(code, 0x8, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
738 and_ir(code, 0x20, opts->gen.scratch2, SZ_B);
739 or_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
724 if (opts->regs[Z80_BC] >= 0) { 740 if (opts->regs[Z80_BC] >= 0) {
725 sub_ir(code, 1, opts->regs[Z80_BC], SZ_W); 741 sub_ir(code, 1, opts->regs[Z80_BC], SZ_W);
726 } else { 742 } else {
727 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_BC), SZ_W); 743 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_BC), SZ_W);
728 } 744 }
762 sub_ir(code, 1, opts->regs[Z80_BC], SZ_W); 778 sub_ir(code, 1, opts->regs[Z80_BC], SZ_W);
763 } else { 779 } else {
764 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_BC), SZ_W); 780 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_BC), SZ_W);
765 } 781 }
766 setcc_rdisp(code, CC_NZ, opts->gen.context_reg, zf_off(ZF_PV)); 782 setcc_rdisp(code, CC_NZ, opts->gen.context_reg, zf_off(ZF_PV));
783 mov_rr(code, opts->regs[Z80_A], opts->gen.scratch2, SZ_B);
784 sub_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B);
785 sub_rdispr(code, opts->gen.context_reg, zf_off(ZF_H), opts->gen.scratch2, SZ_B);
786 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
787 shl_ir(code, 4, opts->gen.scratch2, SZ_B);
788 and_irdisp(code, 0x8, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
789 and_ir(code, 0x20, opts->gen.scratch2, SZ_B);
790 or_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
767 break; 791 break;
768 case Z80_CPDR: { 792 case Z80_CPDR: {
769 cycles(&opts->gen, num_cycles);//T-States 4,4 793 cycles(&opts->gen, num_cycles);//T-States 4,4
770 zreg_to_native(opts, Z80_HL, opts->gen.scratch1); 794 zreg_to_native(opts, Z80_HL, opts->gen.scratch1);
771 call(code, opts->read_8);//T-States 3 795 call(code, opts->read_8);//T-States 3
782 if (opts->regs[Z80_HL] >= 0) { 806 if (opts->regs[Z80_HL] >= 0) {
783 sub_ir(code, 1, opts->regs[Z80_HL], SZ_W); 807 sub_ir(code, 1, opts->regs[Z80_HL], SZ_W);
784 } else { 808 } else {
785 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_W); 809 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_W);
786 } 810 }
811 mov_rr(code, opts->regs[Z80_A], opts->gen.scratch2, SZ_B);
812 sub_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B);
813 sub_rdispr(code, opts->gen.context_reg, zf_off(ZF_H), opts->gen.scratch2, SZ_B);
814 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
815 shl_ir(code, 4, opts->gen.scratch2, SZ_B);
816 and_irdisp(code, 0x8, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
817 and_ir(code, 0x20, opts->gen.scratch2, SZ_B);
818 or_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
787 if (opts->regs[Z80_BC] >= 0) { 819 if (opts->regs[Z80_BC] >= 0) {
788 sub_ir(code, 1, opts->regs[Z80_BC], SZ_W); 820 sub_ir(code, 1, opts->regs[Z80_BC], SZ_W);
789 } else { 821 } else {
790 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_BC), SZ_W); 822 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_BC), SZ_W);
791 } 823 }