Mercurial > repos > blastem
comparison blastem.c @ 186:02e25abe2dcd
Cleanup VINT code and fix bug in which VINT cycle would be set incorrectly after a VDP control port write
author | Mike Pavone <pavone@retrodev.com> |
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date | Sun, 13 Jan 2013 16:11:28 -0800 |
parents | b204fbed4efe |
children | c615061f7914 |
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185:b204fbed4efe | 186:02e25abe2dcd |
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101 //TODO: Figure out what happens when you try to DMA from weird adresses like IO or banked Z80 area | 101 //TODO: Figure out what happens when you try to DMA from weird adresses like IO or banked Z80 area |
102 return 0; | 102 return 0; |
103 } | 103 } |
104 | 104 |
105 #define VINT_CYCLE ((MCLKS_LINE * 226)/MCLKS_PER_68K) | 105 #define VINT_CYCLE ((MCLKS_LINE * 226)/MCLKS_PER_68K) |
106 | |
107 void adjust_int_cycle(m68k_context * context, vdp_context * v_context) | |
108 { | |
109 if (!(v_context->regs[REG_MODE_2] & 0x20 && ((context->status & 0x7) < 6)) || context->current_cycle >= VINT_CYCLE) { | |
110 context->int_cycle = CYCLE_NEVER; | |
111 context->target_cycle = context->sync_cycle; | |
112 } else if (context->int_cycle > VINT_CYCLE) { | |
113 context->int_cycle = VINT_CYCLE; | |
114 context->int_num = 6; | |
115 if (context->int_cycle < context->sync_cycle) { | |
116 context->target_cycle = context->int_cycle; | |
117 } | |
118 } | |
119 } | |
106 | 120 |
107 m68k_context * sync_components(m68k_context * context) | 121 m68k_context * sync_components(m68k_context * context) |
108 { | 122 { |
109 //TODO: Handle sync targets smaller than a single frame | 123 //TODO: Handle sync targets smaller than a single frame |
110 vdp_context * v_context = context->next_context; | 124 vdp_context * v_context = context->next_context; |
119 io_adjust_cycles(&gamepad_2, context->current_cycle, MCLKS_PER_FRAME/MCLKS_PER_68K); | 133 io_adjust_cycles(&gamepad_2, context->current_cycle, MCLKS_PER_FRAME/MCLKS_PER_68K); |
120 context->current_cycle -= MCLKS_PER_FRAME/MCLKS_PER_68K; | 134 context->current_cycle -= MCLKS_PER_FRAME/MCLKS_PER_68K; |
121 if (mclks) { | 135 if (mclks) { |
122 vdp_run_context(v_context, mclks); | 136 vdp_run_context(v_context, mclks); |
123 } | 137 } |
124 if (v_context->regs[REG_MODE_2] & 0x20 && ((context->status & 0x7) < 6)) { | |
125 if (context->int_cycle > VINT_CYCLE) { | |
126 context->int_cycle = VINT_CYCLE; | |
127 context->int_num = 6; | |
128 if (context->int_cycle < context->sync_cycle) { | |
129 context->target_cycle = context->int_cycle; | |
130 } | |
131 } | |
132 } else { | |
133 context->int_cycle = 0xFFFFFFFF; | |
134 context->target_cycle = context->sync_cycle; | |
135 } | |
136 } else { | 138 } else { |
137 //printf("running VDP for %d cycles\n", mclks - v_context->cycles); | 139 //printf("running VDP for %d cycles\n", mclks - v_context->cycles); |
138 vdp_run_context(v_context, mclks); | 140 vdp_run_context(v_context, mclks); |
139 if (v_context->regs[REG_MODE_2] & 0x20 && ((context->status & 0x7) < 6)) { | 141 } |
140 if (context->int_cycle > VINT_CYCLE) { | 142 adjust_int_cycle(context, v_context); |
141 context->int_cycle = VINT_CYCLE; | |
142 context->int_num = 6; | |
143 if (context->int_cycle < context->sync_cycle && context->int_cycle < context->current_cycle) { | |
144 context->target_cycle = context->int_cycle; | |
145 } | |
146 } | |
147 if (context->int_cycle <= context->current_cycle) { | |
148 context->int_cycle = CYCLE_NEVER; | |
149 context->target_cycle = context->sync_cycle; | |
150 } | |
151 } else { | |
152 context->int_cycle = CYCLE_NEVER; | |
153 context->target_cycle = context->sync_cycle; | |
154 } | |
155 } | |
156 return context; | 143 return context; |
157 } | 144 } |
158 | 145 |
159 m68k_context * vdp_port_write(uint32_t vdp_port, m68k_context * context, uint16_t value) | 146 m68k_context * vdp_port_write(uint32_t vdp_port, m68k_context * context, uint16_t value) |
160 { | 147 { |
195 blocked = 0; | 182 blocked = 0; |
196 } | 183 } |
197 } | 184 } |
198 context->current_cycle = v_context->cycles / MCLKS_PER_68K; | 185 context->current_cycle = v_context->cycles / MCLKS_PER_68K; |
199 } else { | 186 } else { |
200 if (v_context->regs[REG_MODE_2] & 0x20 && ((context->status & 0x7) < 6)) { | 187 adjust_int_cycle(context, v_context); |
201 if (context->int_cycle > VINT_CYCLE) { | |
202 context->int_cycle = VINT_CYCLE; | |
203 context->int_num = 6; | |
204 if (context->int_cycle < context->sync_cycle) { | |
205 context->target_cycle = context->int_cycle; | |
206 } | |
207 } | |
208 } else { | |
209 context->int_cycle = 0xFFFFFFFF; | |
210 context->target_cycle = context->sync_cycle; | |
211 } | |
212 } | 188 } |
213 } else { | 189 } else { |
214 printf("Illegal write to HV Counter port %X\n", vdp_port); | 190 printf("Illegal write to HV Counter port %X\n", vdp_port); |
215 exit(1); | 191 exit(1); |
216 } | 192 } |