Mercurial > repos > blastem
annotate z80_to_x86.c @ 287:fb840e0a48cd
Implement RRD and implement flags on RLD
author | Mike Pavone <pavone@retrodev.com> |
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date | Sun, 05 May 2013 11:17:37 -0700 |
parents | 872a8911e0f4 |
children | b970ea214ecb |
rev | line source |
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1 #include "z80inst.h" |
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2 #include "z80_to_x86.h" |
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3 #include "gen_x86.h" |
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4 #include "mem.h" |
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5 #include <stdio.h> |
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6 #include <stdlib.h> |
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7 #include <stddef.h> |
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8 #include <string.h> |
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9 |
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10 #define MODE_UNUSED (MODE_IMMED-1) |
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11 |
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12 #define ZCYCLES RBP |
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13 #define ZLIMIT RDI |
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14 #define SCRATCH1 R13 |
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15 #define SCRATCH2 R14 |
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16 #define CONTEXT RSI |
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17 |
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18 //#define DO_DEBUG_PRINT |
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19 |
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20 #ifdef DO_DEBUG_PRINT |
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21 #define dprintf printf |
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22 #else |
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23 #define dprintf |
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24 #endif |
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25 |
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26 void z80_read_byte(); |
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27 void z80_read_word(); |
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28 void z80_write_byte(); |
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29 void z80_write_word_highfirst(); |
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30 void z80_write_word_lowfirst(); |
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31 void z80_save_context(); |
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32 void z80_native_addr(); |
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33 void z80_do_sync(); |
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34 void z80_handle_cycle_limit_int(); |
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35 void z80_retrans_stub(); |
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36 void z80_io_read(); |
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37 void z80_io_write(); |
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38 void z80_halt(); |
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39 |
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40 uint8_t z80_size(z80inst * inst) |
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41 { |
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42 uint8_t reg = (inst->reg & 0x1F); |
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43 if (reg != Z80_UNUSED && reg != Z80_USE_IMMED) { |
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44 return reg < Z80_BC ? SZ_B : SZ_W; |
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45 } |
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46 //TODO: Handle any necessary special cases |
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47 return SZ_B; |
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48 } |
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49 |
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50 uint8_t z80_high_reg(uint8_t reg) |
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51 { |
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52 switch(reg) |
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53 { |
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54 case Z80_C: |
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55 case Z80_BC: |
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56 return Z80_B; |
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57 case Z80_E: |
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58 case Z80_DE: |
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59 return Z80_D; |
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60 case Z80_L: |
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61 case Z80_HL: |
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62 return Z80_H; |
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63 case Z80_IXL: |
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64 case Z80_IX: |
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65 return Z80_IXH; |
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66 case Z80_IYL: |
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67 case Z80_IY: |
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68 return Z80_IYH; |
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69 default: |
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70 return Z80_UNUSED; |
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71 } |
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72 } |
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73 |
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74 uint8_t z80_low_reg(uint8_t reg) |
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75 { |
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76 switch(reg) |
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77 { |
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78 case Z80_B: |
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79 case Z80_BC: |
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80 return Z80_C; |
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81 case Z80_D: |
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82 case Z80_DE: |
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83 return Z80_E; |
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84 case Z80_H: |
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85 case Z80_HL: |
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86 return Z80_L; |
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87 case Z80_IXH: |
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88 case Z80_IX: |
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89 return Z80_IXL; |
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90 case Z80_IYH: |
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91 case Z80_IY: |
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92 return Z80_IYL; |
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93 default: |
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94 return Z80_UNUSED; |
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95 } |
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96 } |
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97 |
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98 uint8_t * zcycles(uint8_t * dst, uint32_t num_cycles) |
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99 { |
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100 return add_ir(dst, num_cycles, ZCYCLES, SZ_D); |
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101 } |
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102 |
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103 uint8_t * z80_check_cycles_int(uint8_t * dst, uint16_t address) |
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104 { |
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105 dst = cmp_rr(dst, ZCYCLES, ZLIMIT, SZ_D); |
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106 uint8_t * jmp_off = dst+1; |
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107 dst = jcc(dst, CC_NC, dst + 7); |
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108 dst = mov_ir(dst, address, SCRATCH1, SZ_W); |
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109 dst = call(dst, (uint8_t *)z80_handle_cycle_limit_int); |
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110 *jmp_off = dst - (jmp_off+1); |
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111 return dst; |
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112 } |
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113 |
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114 uint8_t * translate_z80_reg(z80inst * inst, x86_ea * ea, uint8_t * dst, x86_z80_options * opts) |
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115 { |
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116 if (inst->reg == Z80_USE_IMMED) { |
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117 ea->mode = MODE_IMMED; |
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118 ea->disp = inst->immed; |
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119 } else if ((inst->reg & 0x1F) == Z80_UNUSED) { |
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120 ea->mode = MODE_UNUSED; |
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121 } else { |
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122 ea->mode = MODE_REG_DIRECT; |
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123 if (inst->reg == Z80_IYH) { |
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124 ea->base = opts->regs[Z80_IYL]; |
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125 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W); |
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126 } else if(opts->regs[inst->reg] >= 0) { |
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127 ea->base = opts->regs[inst->reg]; |
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128 if (ea->base >= AH && ea->base <= BH) { |
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129 if ((inst->addr_mode & 0x1F) == Z80_REG) { |
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130 uint8_t other_reg = opts->regs[inst->ea_reg]; |
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131 if (other_reg >= R8 || (other_reg >= RSP && other_reg <= RDI)) { |
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132 //we can't mix an *H reg with a register that requires the REX prefix |
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133 ea->base = opts->regs[z80_low_reg(inst->reg)]; |
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134 dst = ror_ir(dst, 8, ea->base, SZ_W); |
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135 } |
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136 } else if((inst->addr_mode & 0x1F) != Z80_UNUSED && (inst->addr_mode & 0x1F) != Z80_IMMED) { |
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137 //temp regs require REX prefix too |
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138 ea->base = opts->regs[z80_low_reg(inst->reg)]; |
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139 dst = ror_ir(dst, 8, ea->base, SZ_W); |
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140 } |
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141 } |
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142 } else { |
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143 ea->mode = MODE_REG_DISPLACE8; |
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144 ea->base = CONTEXT; |
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145 ea->disp = offsetof(z80_context, regs) + inst->reg; |
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146 } |
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147 } |
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148 return dst; |
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149 } |
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150 |
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151 uint8_t * z80_save_reg(uint8_t * dst, z80inst * inst, x86_z80_options * opts) |
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152 { |
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153 if (inst->reg == Z80_IYH) { |
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154 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W); |
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155 } else if (opts->regs[inst->reg] >= AH && opts->regs[inst->reg] <= BH) { |
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156 if ((inst->addr_mode & 0x1F) == Z80_REG) { |
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157 uint8_t other_reg = opts->regs[inst->ea_reg]; |
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158 if (other_reg >= R8 || (other_reg >= RSP && other_reg <= RDI)) { |
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159 //we can't mix an *H reg with a register that requires the REX prefix |
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160 dst = ror_ir(dst, 8, opts->regs[z80_low_reg(inst->reg)], SZ_W); |
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161 } |
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162 } else if((inst->addr_mode & 0x1F) != Z80_UNUSED && (inst->addr_mode & 0x1F) != Z80_IMMED) { |
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163 //temp regs require REX prefix too |
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164 dst = ror_ir(dst, 8, opts->regs[z80_low_reg(inst->reg)], SZ_W); |
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165 } |
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166 } |
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167 return dst; |
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168 } |
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169 |
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170 uint8_t * translate_z80_ea(z80inst * inst, x86_ea * ea, uint8_t * dst, x86_z80_options * opts, uint8_t read, uint8_t modify) |
213
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171 { |
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172 uint8_t size, reg, areg; |
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173 ea->mode = MODE_REG_DIRECT; |
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174 areg = read ? SCRATCH1 : SCRATCH2; |
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175 switch(inst->addr_mode & 0x1F) |
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176 { |
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177 case Z80_REG: |
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178 if (inst->ea_reg == Z80_IYH) { |
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179 ea->base = opts->regs[Z80_IYL]; |
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180 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W); |
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181 } else { |
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182 ea->base = opts->regs[inst->ea_reg]; |
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183 if (ea->base >= AH && ea->base <= BH && inst->reg != Z80_UNUSED && inst->reg != Z80_USE_IMMED) { |
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184 uint8_t other_reg = opts->regs[inst->reg]; |
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185 if (other_reg >= R8 || (other_reg >= RSP && other_reg <= RDI)) { |
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186 //we can't mix an *H reg with a register that requires the REX prefix |
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187 ea->base = opts->regs[z80_low_reg(inst->ea_reg)]; |
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188 dst = ror_ir(dst, 8, ea->base, SZ_W); |
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189 } |
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190 } |
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191 } |
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192 break; |
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193 case Z80_REG_INDIRECT: |
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194 dst = mov_rr(dst, opts->regs[inst->ea_reg], areg, SZ_W); |
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195 size = z80_size(inst); |
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196 if (read) { |
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197 if (modify) { |
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198 //dst = push_r(dst, SCRATCH1); |
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199 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(z80_context, scratch1), SZ_W); |
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200 } |
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201 if (size == SZ_B) { |
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202 dst = call(dst, (uint8_t *)z80_read_byte); |
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203 } else { |
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204 dst = call(dst, (uint8_t *)z80_read_word); |
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205 } |
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206 if (modify) { |
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207 //dst = pop_r(dst, SCRATCH2); |
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208 dst = mov_rdisp8r(dst, CONTEXT, offsetof(z80_context, scratch1), SCRATCH2, SZ_W); |
213
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209 } |
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210 } |
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211 ea->base = SCRATCH1; |
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212 break; |
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213 case Z80_IMMED: |
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214 ea->mode = MODE_IMMED; |
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215 ea->disp = inst->immed; |
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216 break; |
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217 case Z80_IMMED_INDIRECT: |
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218 dst = mov_ir(dst, inst->immed, areg, SZ_W); |
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219 size = z80_size(inst); |
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220 if (read) { |
277
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221 /*if (modify) { |
213
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222 dst = push_r(dst, SCRATCH1); |
277
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223 }*/ |
213
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224 if (size == SZ_B) { |
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225 dst = call(dst, (uint8_t *)z80_read_byte); |
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226 } else { |
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227 dst = call(dst, (uint8_t *)z80_read_word); |
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228 } |
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229 if (modify) { |
277
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230 //dst = pop_r(dst, SCRATCH2); |
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231 dst = mov_ir(dst, inst->immed, SCRATCH2, SZ_W); |
213
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232 } |
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233 } |
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234 ea->base = SCRATCH1; |
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235 break; |
235
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236 case Z80_IX_DISPLACE: |
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237 case Z80_IY_DISPLACE: |
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238 reg = opts->regs[inst->addr_mode == Z80_IX_DISPLACE ? Z80_IX : Z80_IY]; |
213
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239 dst = mov_rr(dst, reg, areg, SZ_W); |
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240 dst = add_ir(dst, inst->immed, areg, SZ_W); |
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241 size = z80_size(inst); |
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242 if (read) { |
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243 if (modify) { |
277
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244 //dst = push_r(dst, SCRATCH1); |
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245 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(z80_context, scratch1), SZ_W); |
213
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246 } |
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247 if (size == SZ_B) { |
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248 dst = call(dst, (uint8_t *)z80_read_byte); |
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249 } else { |
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250 dst = call(dst, (uint8_t *)z80_read_word); |
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251 } |
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252 if (modify) { |
277
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253 //dst = pop_r(dst, SCRATCH2); |
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254 dst = mov_rdisp8r(dst, CONTEXT, offsetof(z80_context, scratch1), SCRATCH2, SZ_W); |
213
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255 } |
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256 } |
269
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268
diff
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257 ea->base = SCRATCH1; |
213
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258 break; |
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259 case Z80_UNUSED: |
235
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260 ea->mode = MODE_UNUSED; |
213
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261 break; |
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262 default: |
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263 fprintf(stderr, "Unrecognized Z80 addressing mode %d\n", inst->addr_mode); |
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264 exit(1); |
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265 } |
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266 return dst; |
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267 } |
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268 |
235
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|
269 uint8_t * z80_save_ea(uint8_t * dst, z80inst * inst, x86_z80_options * opts) |
213
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270 { |
267
1788e3f29c28
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266
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271 if ((inst->addr_mode & 0x1F) == Z80_REG) { |
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266
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272 if (inst->ea_reg == Z80_IYH) { |
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273 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W); |
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274 } else if (inst->reg != Z80_UNUSED && inst->reg != Z80_USE_IMMED && opts->regs[inst->ea_reg] >= AH && opts->regs[inst->ea_reg] <= BH) { |
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266
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275 uint8_t other_reg = opts->regs[inst->reg]; |
269
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268
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276 if (other_reg >= R8 || (other_reg >= RSP && other_reg <= RDI)) { |
267
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266
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277 //we can't mix an *H reg with a register that requires the REX prefix |
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278 dst = ror_ir(dst, 8, opts->regs[z80_low_reg(inst->ea_reg)], SZ_W); |
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279 } |
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280 } |
213
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281 } |
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282 return dst; |
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283 } |
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284 |
235
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285 uint8_t * z80_save_result(uint8_t * dst, z80inst * inst) |
213
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286 { |
253
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287 switch(inst->addr_mode & 0x1f) |
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288 { |
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289 case Z80_REG_INDIRECT: |
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290 case Z80_IMMED_INDIRECT: |
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291 case Z80_IX_DISPLACE: |
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292 case Z80_IY_DISPLACE: |
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293 if (z80_size(inst) == SZ_B) { |
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294 dst = call(dst, (uint8_t *)z80_write_byte); |
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295 } else { |
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296 dst = call(dst, (uint8_t *)z80_write_word_lowfirst); |
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297 } |
213
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298 } |
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299 return dst; |
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300 } |
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301 |
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|
302 enum { |
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303 DONT_READ=0, |
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|
304 READ |
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305 }; |
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306 |
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|
307 enum { |
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308 DONT_MODIFY=0, |
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309 MODIFY |
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310 }; |
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311 |
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312 uint8_t zf_off(uint8_t flag) |
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313 { |
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314 return offsetof(z80_context, flags) + flag; |
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315 } |
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316 |
241
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317 uint8_t zaf_off(uint8_t flag) |
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318 { |
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319 return offsetof(z80_context, alt_flags) + flag; |
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320 } |
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321 |
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322 uint8_t zar_off(uint8_t reg) |
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323 { |
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324 return offsetof(z80_context, alt_regs) + reg; |
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325 } |
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326 |
235
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327 void z80_print_regs_exit(z80_context * context) |
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328 { |
243
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329 printf("A: %X\nB: %X\nC: %X\nD: %X\nE: %X\nHL: %X\nIX: %X\nIY: %X\nSP: %X\n\nIM: %d, IFF1: %d, IFF2: %d\n", |
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330 context->regs[Z80_A], context->regs[Z80_B], context->regs[Z80_C], |
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331 context->regs[Z80_D], context->regs[Z80_E], |
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332 (context->regs[Z80_H] << 8) | context->regs[Z80_L], |
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333 (context->regs[Z80_IXH] << 8) | context->regs[Z80_IXL], |
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334 (context->regs[Z80_IYH] << 8) | context->regs[Z80_IYL], |
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335 context->sp, context->im, context->iff1, context->iff2); |
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336 puts("--Alternate Regs--"); |
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337 printf("A: %X\nB: %X\nC: %X\nD: %X\nE: %X\nHL: %X\nIX: %X\nIY: %X\n", |
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338 context->alt_regs[Z80_A], context->alt_regs[Z80_B], context->alt_regs[Z80_C], |
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339 context->alt_regs[Z80_D], context->alt_regs[Z80_E], |
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340 (context->alt_regs[Z80_H] << 8) | context->alt_regs[Z80_L], |
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341 (context->alt_regs[Z80_IXH] << 8) | context->alt_regs[Z80_IXL], |
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342 (context->alt_regs[Z80_IYH] << 8) | context->alt_regs[Z80_IYL]); |
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343 exit(0); |
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344 } |
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345 |
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346 uint8_t * translate_z80inst(z80inst * inst, uint8_t * dst, z80_context * context, uint16_t address) |
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347 { |
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348 uint32_t cycles; |
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349 x86_ea src_op, dst_op; |
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350 uint8_t size; |
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351 x86_z80_options *opts = context->options; |
261
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352 uint8_t * start = dst; |
250
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353 dst = z80_check_cycles_int(dst, address); |
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354 switch(inst->op) |
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355 { |
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356 case Z80_LD: |
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357 size = z80_size(inst); |
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358 switch (inst->addr_mode & 0x1F) |
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359 { |
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360 case Z80_REG: |
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361 case Z80_REG_INDIRECT: |
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362 cycles = size == SZ_B ? 4 : 6; |
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363 if (inst->ea_reg == Z80_IX || inst->ea_reg == Z80_IY) { |
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364 cycles += 4; |
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365 } |
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366 break; |
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367 case Z80_IMMED: |
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368 cycles = size == SZ_B ? 7 : 10; |
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369 break; |
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370 case Z80_IMMED_INDIRECT: |
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371 cycles = 10; |
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372 break; |
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373 case Z80_IX_DISPLACE: |
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374 case Z80_IY_DISPLACE: |
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375 cycles = 12; |
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376 break; |
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377 } |
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378 if ((inst->reg >= Z80_IXL && inst->reg <= Z80_IYH) || inst->reg == Z80_IX || inst->reg == Z80_IY) { |
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379 cycles += 4; |
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380 } |
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381 dst = zcycles(dst, cycles); |
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382 if (inst->addr_mode & Z80_DIR) { |
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383 dst = translate_z80_reg(inst, &src_op, dst, opts); |
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384 dst = translate_z80_ea(inst, &dst_op, dst, opts, DONT_READ, MODIFY); |
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385 } else { |
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386 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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387 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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388 } |
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389 if (src_op.mode == MODE_REG_DIRECT) { |
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390 if(dst_op.mode == MODE_REG_DISPLACE8) { |
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391 dst = mov_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, size); |
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392 } else { |
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393 dst = mov_rr(dst, src_op.base, dst_op.base, size); |
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394 } |
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395 } else if(src_op.mode == MODE_IMMED) { |
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396 dst = mov_ir(dst, src_op.disp, dst_op.base, size); |
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397 } else { |
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398 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, size); |
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399 } |
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400 dst = z80_save_reg(dst, inst, opts); |
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401 dst = z80_save_ea(dst, inst, opts); |
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402 if (inst->addr_mode & Z80_DIR) { |
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403 dst = z80_save_result(dst, inst); |
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404 } |
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405 break; |
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406 case Z80_PUSH: |
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407 dst = zcycles(dst, (inst->reg == Z80_IX || inst->reg == Z80_IY) ? 9 : 5); |
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408 dst = sub_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
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409 if (inst->reg == Z80_AF) { |
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410 dst = mov_rdisp8r(dst, CONTEXT, zf_off(ZF_S), SCRATCH1, SZ_B); |
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411 dst = shl_ir(dst, 1, SCRATCH1, SZ_B); |
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412 dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_Z), SCRATCH1, SZ_B); |
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413 dst = shl_ir(dst, 2, SCRATCH1, SZ_B); |
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414 dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_H), SCRATCH1, SZ_B); |
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415 dst = shl_ir(dst, 2, SCRATCH1, SZ_B); |
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416 dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_PV), SCRATCH1, SZ_B); |
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417 dst = shl_ir(dst, 1, SCRATCH1, SZ_B); |
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418 dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_N), SCRATCH1, SZ_B); |
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419 dst = shl_ir(dst, 1, SCRATCH1, SZ_B); |
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420 dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_C), SCRATCH1, SZ_B); |
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421 dst = shl_ir(dst, 8, SCRATCH1, SZ_W); |
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422 dst = mov_rr(dst, opts->regs[Z80_A], SCRATCH1, SZ_B); |
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423 } else { |
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424 dst = translate_z80_reg(inst, &src_op, dst, opts); |
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425 dst = mov_rr(dst, src_op.base, SCRATCH1, SZ_W); |
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426 } |
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427 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W); |
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428 dst = call(dst, (uint8_t *)z80_write_word_highfirst); |
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429 //no call to save_z80_reg needed since there's no chance we'll use the only |
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430 //the upper half of a register pair |
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431 break; |
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432 case Z80_POP: |
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433 dst = zcycles(dst, (inst->reg == Z80_IX || inst->reg == Z80_IY) ? 8 : 4); |
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434 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
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435 dst = call(dst, (uint8_t *)z80_read_word); |
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436 dst = add_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
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437 if (inst->reg == Z80_AF) { |
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438 dst = mov_rr(dst, SCRATCH1, opts->regs[Z80_A], SZ_B); |
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439 dst = bt_ir(dst, 8, SCRATCH1, SZ_W); |
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440 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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441 dst = bt_ir(dst, 9, SCRATCH1, SZ_W); |
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442 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_N)); |
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443 dst = bt_ir(dst, 10, SCRATCH1, SZ_W); |
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444 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_PV)); |
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445 dst = bt_ir(dst, 12, SCRATCH1, SZ_W); |
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446 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_H)); |
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447 dst = bt_ir(dst, 14, SCRATCH1, SZ_W); |
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448 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_Z)); |
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449 dst = bt_ir(dst, 15, SCRATCH1, SZ_W); |
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450 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_S)); |
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451 } else { |
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452 dst = translate_z80_reg(inst, &src_op, dst, opts); |
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453 dst = mov_rr(dst, SCRATCH1, src_op.base, SZ_W); |
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454 } |
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455 //no call to save_z80_reg needed since there's no chance we'll use the only |
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456 //the upper half of a register pair |
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457 break; |
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458 case Z80_EX: |
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459 if (inst->addr_mode == Z80_REG || inst->reg == Z80_HL) { |
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460 cycles = 4; |
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461 } else { |
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462 cycles = 8; |
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463 } |
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464 dst = zcycles(dst, cycles); |
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465 if (inst->addr_mode == Z80_REG) { |
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466 if(inst->reg == Z80_AF) { |
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467 dst = mov_rr(dst, opts->regs[Z80_A], SCRATCH1, SZ_B); |
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468 dst = mov_rdisp8r(dst, CONTEXT, zar_off(Z80_A), opts->regs[Z80_A], SZ_B); |
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469 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, zar_off(Z80_A), SZ_B); |
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470 |
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471 //Flags are currently word aligned, so we can move |
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472 //them efficiently a word at a time |
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473 for (int f = ZF_C; f < ZF_NUM; f+=2) { |
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474 dst = mov_rdisp8r(dst, CONTEXT, zf_off(f), SCRATCH1, SZ_W); |
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475 dst = mov_rdisp8r(dst, CONTEXT, zaf_off(f), SCRATCH2, SZ_W); |
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476 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, zaf_off(f), SZ_W); |
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477 dst = mov_rrdisp8(dst, SCRATCH2, CONTEXT, zf_off(f), SZ_W); |
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478 } |
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479 } else { |
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480 dst = xchg_rr(dst, opts->regs[Z80_DE], opts->regs[Z80_HL], SZ_W); |
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481 } |
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482 } else { |
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483 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
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484 dst = call(dst, (uint8_t *)z80_read_byte); |
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485 dst = xchg_rr(dst, opts->regs[inst->reg], SCRATCH1, SZ_B); |
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486 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W); |
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487 dst = call(dst, (uint8_t *)z80_write_byte); |
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488 dst = zcycles(dst, 1); |
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489 uint8_t high_reg = z80_high_reg(inst->reg); |
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490 uint8_t use_reg; |
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491 //even though some of the upper halves can be used directly |
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492 //the limitations on mixing *H regs with the REX prefix |
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493 //prevent us from taking advantage of it |
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494 use_reg = opts->regs[inst->reg]; |
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495 dst = ror_ir(dst, 8, use_reg, SZ_W); |
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496 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
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497 dst = add_ir(dst, 1, SCRATCH1, SZ_W); |
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498 dst = call(dst, (uint8_t *)z80_read_byte); |
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499 dst = xchg_rr(dst, use_reg, SCRATCH1, SZ_B); |
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500 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W); |
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501 dst = add_ir(dst, 1, SCRATCH2, SZ_W); |
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502 dst = call(dst, (uint8_t *)z80_write_byte); |
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503 //restore reg to normal rotation |
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504 dst = ror_ir(dst, 8, use_reg, SZ_W); |
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505 dst = zcycles(dst, 2); |
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506 } |
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507 break; |
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508 case Z80_EXX: |
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509 dst = zcycles(dst, 4); |
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510 dst = mov_rr(dst, opts->regs[Z80_BC], SCRATCH1, SZ_W); |
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511 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH2, SZ_W); |
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512 dst = mov_rdisp8r(dst, CONTEXT, zar_off(Z80_C), opts->regs[Z80_BC], SZ_W); |
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513 dst = mov_rdisp8r(dst, CONTEXT, zar_off(Z80_L), opts->regs[Z80_HL], SZ_W); |
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514 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, zar_off(Z80_C), SZ_W); |
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515 dst = mov_rrdisp8(dst, SCRATCH2, CONTEXT, zar_off(Z80_L), SZ_W); |
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516 dst = mov_rr(dst, opts->regs[Z80_DE], SCRATCH1, SZ_W); |
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517 dst = mov_rdisp8r(dst, CONTEXT, zar_off(Z80_E), opts->regs[Z80_DE], SZ_W); |
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518 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, zar_off(Z80_E), SZ_W); |
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519 break; |
272 | 520 case Z80_LDI: { |
521 dst = zcycles(dst, 8); | |
522 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH1, SZ_W); | |
523 dst = call(dst, (uint8_t *)z80_read_byte); | |
524 dst = mov_rr(dst, opts->regs[Z80_DE], SCRATCH2, SZ_W); | |
525 dst = call(dst, (uint8_t *)z80_read_byte); | |
526 dst = zcycles(dst, 2); | |
527 dst = add_ir(dst, 1, opts->regs[Z80_DE], SZ_W); | |
528 dst = add_ir(dst, 1, opts->regs[Z80_HL], SZ_W); | |
529 dst = sub_ir(dst, 1, opts->regs[Z80_BC], SZ_W); | |
530 //TODO: Implement half-carry | |
531 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); | |
532 dst = setcc_rdisp8(dst, CC_NZ, CONTEXT, zf_off(ZF_PV)); | |
533 break; | |
534 } | |
261
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535 case Z80_LDIR: { |
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536 dst = zcycles(dst, 8); |
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537 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH1, SZ_W); |
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538 dst = call(dst, (uint8_t *)z80_read_byte); |
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539 dst = mov_rr(dst, opts->regs[Z80_DE], SCRATCH2, SZ_W); |
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540 dst = call(dst, (uint8_t *)z80_read_byte); |
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541 dst = add_ir(dst, 1, opts->regs[Z80_DE], SZ_W); |
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542 dst = add_ir(dst, 1, opts->regs[Z80_HL], SZ_W); |
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543 |
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544 dst = sub_ir(dst, 1, opts->regs[Z80_BC], SZ_W); |
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545 uint8_t * cont = dst+1; |
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546 dst = jcc(dst, CC_Z, dst+2); |
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547 dst = zcycles(dst, 7); |
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548 //TODO: Figure out what the flag state should be here |
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549 //TODO: Figure out whether an interrupt can interrupt this |
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550 dst = jmp(dst, start); |
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551 *cont = dst - (cont + 1); |
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552 dst = zcycles(dst, 2); |
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553 //TODO: Implement half-carry |
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554 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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555 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_PV), SZ_B); |
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556 break; |
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557 } |
273 | 558 case Z80_LDD: { |
559 dst = zcycles(dst, 8); | |
560 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH1, SZ_W); | |
561 dst = call(dst, (uint8_t *)z80_read_byte); | |
562 dst = mov_rr(dst, opts->regs[Z80_DE], SCRATCH2, SZ_W); | |
563 dst = call(dst, (uint8_t *)z80_read_byte); | |
564 dst = zcycles(dst, 2); | |
565 dst = sub_ir(dst, 1, opts->regs[Z80_DE], SZ_W); | |
566 dst = sub_ir(dst, 1, opts->regs[Z80_HL], SZ_W); | |
567 dst = sub_ir(dst, 1, opts->regs[Z80_BC], SZ_W); | |
568 //TODO: Implement half-carry | |
569 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); | |
570 dst = setcc_rdisp8(dst, CC_NZ, CONTEXT, zf_off(ZF_PV)); | |
571 break; | |
572 } | |
573 case Z80_LDDR: { | |
574 dst = zcycles(dst, 8); | |
575 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH1, SZ_W); | |
576 dst = call(dst, (uint8_t *)z80_read_byte); | |
577 dst = mov_rr(dst, opts->regs[Z80_DE], SCRATCH2, SZ_W); | |
578 dst = call(dst, (uint8_t *)z80_read_byte); | |
579 dst = sub_ir(dst, 1, opts->regs[Z80_DE], SZ_W); | |
580 dst = sub_ir(dst, 1, opts->regs[Z80_HL], SZ_W); | |
581 | |
582 dst = sub_ir(dst, 1, opts->regs[Z80_BC], SZ_W); | |
583 uint8_t * cont = dst+1; | |
584 dst = jcc(dst, CC_Z, dst+2); | |
585 dst = zcycles(dst, 7); | |
586 //TODO: Figure out what the flag state should be here | |
587 //TODO: Figure out whether an interrupt can interrupt this | |
588 dst = jmp(dst, start); | |
589 *cont = dst - (cont + 1); | |
590 dst = zcycles(dst, 2); | |
591 //TODO: Implement half-carry | |
592 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); | |
593 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_PV), SZ_B); | |
594 break; | |
595 } | |
596 /*case Z80_CPI: | |
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597 case Z80_CPIR: |
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598 case Z80_CPD: |
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599 case Z80_CPDR: |
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600 break;*/ |
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601 case Z80_ADD: |
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602 cycles = 4; |
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603 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
213
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604 cycles += 12; |
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605 } else if(inst->addr_mode == Z80_IMMED) { |
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606 cycles += 3; |
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607 } else if(z80_size(inst) == SZ_W) { |
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608 cycles += 4; |
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609 } |
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610 dst = zcycles(dst, cycles); |
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611 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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612 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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613 if (src_op.mode == MODE_REG_DIRECT) { |
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614 dst = add_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
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615 } else { |
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616 dst = add_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
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617 } |
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618 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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619 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
213
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620 //TODO: Implement half-carry flag |
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621 if (z80_size(inst) == SZ_B) { |
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622 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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623 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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624 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
213
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625 } |
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626 dst = z80_save_reg(dst, inst, opts); |
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627 dst = z80_save_ea(dst, inst, opts); |
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628 break; |
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629 case Z80_ADC: |
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630 cycles = 4; |
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631 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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632 cycles += 12; |
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633 } else if(inst->addr_mode == Z80_IMMED) { |
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634 cycles += 3; |
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635 } else if(z80_size(inst) == SZ_W) { |
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636 cycles += 4; |
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637 } |
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638 dst = zcycles(dst, cycles); |
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639 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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640 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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641 if (src_op.mode == MODE_REG_DIRECT) { |
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642 dst = adc_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
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643 } else { |
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644 dst = adc_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
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645 } |
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646 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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647 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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648 //TODO: Implement half-carry flag |
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649 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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650 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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651 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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652 dst = z80_save_reg(dst, inst, opts); |
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653 dst = z80_save_ea(dst, inst, opts); |
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654 break; |
213
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655 case Z80_SUB: |
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656 cycles = 4; |
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657 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
213
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|
658 cycles += 12; |
4d4559b04c59
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659 } else if(inst->addr_mode == Z80_IMMED) { |
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660 cycles += 3; |
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661 } |
4d4559b04c59
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662 dst = zcycles(dst, cycles); |
4d4559b04c59
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663 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
4d4559b04c59
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664 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
4d4559b04c59
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665 if (src_op.mode == MODE_REG_DIRECT) { |
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666 dst = sub_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
4d4559b04c59
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667 } else { |
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668 dst = sub_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
4d4559b04c59
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669 } |
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670 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
235
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671 dst = mov_irdisp8(dst, 1, CONTEXT, zf_off(ZF_N), SZ_B); |
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672 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
213
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673 //TODO: Implement half-carry flag |
235
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674 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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675 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
213
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676 dst = z80_save_reg(dst, inst, opts); |
4d4559b04c59
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677 dst = z80_save_ea(dst, inst, opts); |
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678 break; |
248
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679 case Z80_SBC: |
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680 cycles = 4; |
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681 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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682 cycles += 12; |
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683 } else if(inst->addr_mode == Z80_IMMED) { |
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684 cycles += 3; |
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685 } else if(z80_size(inst) == SZ_W) { |
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686 cycles += 4; |
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687 } |
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688 dst = zcycles(dst, cycles); |
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689 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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690 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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691 if (src_op.mode == MODE_REG_DIRECT) { |
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692 dst = sbb_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
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693 } else { |
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694 dst = sbb_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
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695 } |
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696 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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697 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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|
698 //TODO: Implement half-carry flag |
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699 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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700 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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701 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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702 dst = z80_save_reg(dst, inst, opts); |
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703 dst = z80_save_ea(dst, inst, opts); |
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|
704 break; |
213
4d4559b04c59
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|
705 case Z80_AND: |
236
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235
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|
706 cycles = 4; |
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|
707 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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|
708 cycles += 12; |
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|
709 } else if(inst->addr_mode == Z80_IMMED) { |
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|
710 cycles += 3; |
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|
711 } else if(z80_size(inst) == SZ_W) { |
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|
712 cycles += 4; |
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|
713 } |
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|
714 dst = zcycles(dst, cycles); |
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235
diff
changeset
|
715 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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235
diff
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|
716 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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diff
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|
717 if (src_op.mode == MODE_REG_DIRECT) { |
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235
diff
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|
718 dst = and_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
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235
diff
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|
719 } else { |
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235
diff
changeset
|
720 dst = and_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
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235
diff
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|
721 } |
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235
diff
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|
722 //TODO: Cleanup flags |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
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235
diff
changeset
|
723 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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235
diff
changeset
|
724 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
19fb3523a9e5
Implement more Z80 instructions (untested)
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parents:
235
diff
changeset
|
725 //TODO: Implement half-carry flag |
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Implement more Z80 instructions (untested)
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parents:
235
diff
changeset
|
726 if (z80_size(inst) == SZ_B) { |
19fb3523a9e5
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235
diff
changeset
|
727 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
19fb3523a9e5
Implement more Z80 instructions (untested)
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235
diff
changeset
|
728 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
19fb3523a9e5
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235
diff
changeset
|
729 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
19fb3523a9e5
Implement more Z80 instructions (untested)
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235
diff
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|
730 } |
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235
diff
changeset
|
731 dst = z80_save_reg(dst, inst, opts); |
19fb3523a9e5
Implement more Z80 instructions (untested)
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235
diff
changeset
|
732 dst = z80_save_ea(dst, inst, opts); |
19fb3523a9e5
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parents:
235
diff
changeset
|
733 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
734 case Z80_OR: |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
735 cycles = 4; |
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
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235
diff
changeset
|
736 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
19fb3523a9e5
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parents:
235
diff
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|
737 cycles += 12; |
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
738 } else if(inst->addr_mode == Z80_IMMED) { |
19fb3523a9e5
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parents:
235
diff
changeset
|
739 cycles += 3; |
19fb3523a9e5
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235
diff
changeset
|
740 } else if(z80_size(inst) == SZ_W) { |
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235
diff
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|
741 cycles += 4; |
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235
diff
changeset
|
742 } |
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235
diff
changeset
|
743 dst = zcycles(dst, cycles); |
19fb3523a9e5
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235
diff
changeset
|
744 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
19fb3523a9e5
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235
diff
changeset
|
745 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
19fb3523a9e5
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235
diff
changeset
|
746 if (src_op.mode == MODE_REG_DIRECT) { |
19fb3523a9e5
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235
diff
changeset
|
747 dst = or_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
19fb3523a9e5
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parents:
235
diff
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|
748 } else { |
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235
diff
changeset
|
749 dst = or_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
19fb3523a9e5
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235
diff
changeset
|
750 } |
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
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751 //TODO: Cleanup flags |
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752 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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753 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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754 //TODO: Implement half-carry flag |
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755 if (z80_size(inst) == SZ_B) { |
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756 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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757 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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758 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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759 } |
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760 dst = z80_save_reg(dst, inst, opts); |
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761 dst = z80_save_ea(dst, inst, opts); |
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762 break; |
213
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763 case Z80_XOR: |
236
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764 cycles = 4; |
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765 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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766 cycles += 12; |
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767 } else if(inst->addr_mode == Z80_IMMED) { |
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768 cycles += 3; |
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769 } else if(z80_size(inst) == SZ_W) { |
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770 cycles += 4; |
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771 } |
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772 dst = zcycles(dst, cycles); |
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773 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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774 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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775 if (src_op.mode == MODE_REG_DIRECT) { |
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776 dst = add_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
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777 } else { |
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778 dst = add_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
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779 } |
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780 //TODO: Cleanup flags |
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781 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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782 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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783 //TODO: Implement half-carry flag |
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784 if (z80_size(inst) == SZ_B) { |
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785 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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786 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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787 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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788 } |
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789 dst = z80_save_reg(dst, inst, opts); |
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790 dst = z80_save_ea(dst, inst, opts); |
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791 break; |
242 | 792 case Z80_CP: |
793 cycles = 4; | |
794 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { | |
795 cycles += 12; | |
796 } else if(inst->addr_mode == Z80_IMMED) { | |
797 cycles += 3; | |
798 } | |
799 dst = zcycles(dst, cycles); | |
800 dst = translate_z80_reg(inst, &dst_op, dst, opts); | |
801 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); | |
802 if (src_op.mode == MODE_REG_DIRECT) { | |
803 dst = cmp_rr(dst, src_op.base, dst_op.base, z80_size(inst)); | |
804 } else { | |
805 dst = cmp_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); | |
806 } | |
807 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); | |
808 dst = mov_irdisp8(dst, 1, CONTEXT, zf_off(ZF_N), SZ_B); | |
809 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); | |
810 //TODO: Implement half-carry flag | |
811 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); | |
812 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); | |
813 dst = z80_save_reg(dst, inst, opts); | |
814 dst = z80_save_ea(dst, inst, opts); | |
815 break; | |
213
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816 case Z80_INC: |
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|
817 cycles = 4; |
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818 if (inst->reg == Z80_IX || inst->reg == Z80_IY) { |
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|
819 cycles += 6; |
4d4559b04c59
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820 } else if(z80_size(inst) == SZ_W) { |
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changeset
|
821 cycles += 2; |
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822 } else if(inst->reg == Z80_IXH || inst->reg == Z80_IXL || inst->reg == Z80_IYH || inst->reg == Z80_IYL || inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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|
823 cycles += 4; |
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824 } |
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825 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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|
826 if (dst_op.mode == MODE_UNUSED) { |
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827 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
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828 } |
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829 dst = add_ir(dst, 1, dst_op.base, z80_size(inst)); |
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830 if (z80_size(inst) == SZ_B) { |
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831 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
213
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|
832 //TODO: Implement half-carry flag |
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833 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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834 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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835 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
213
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|
836 } |
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|
837 dst = z80_save_reg(dst, inst, opts); |
4d4559b04c59
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diff
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|
838 dst = z80_save_ea(dst, inst, opts); |
4d4559b04c59
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|
839 break; |
236
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840 case Z80_DEC: |
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841 cycles = 4; |
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842 if (inst->reg == Z80_IX || inst->reg == Z80_IY) { |
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843 cycles += 6; |
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844 } else if(z80_size(inst) == SZ_W) { |
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845 cycles += 2; |
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846 } else if(inst->reg == Z80_IXH || inst->reg == Z80_IXL || inst->reg == Z80_IYH || inst->reg == Z80_IYL || inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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847 cycles += 4; |
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|
848 } |
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849 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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850 if (dst_op.mode == MODE_UNUSED) { |
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851 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
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852 } |
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853 dst = sub_ir(dst, 1, dst_op.base, z80_size(inst)); |
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854 if (z80_size(inst) == SZ_B) { |
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855 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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856 //TODO: Implement half-carry flag |
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857 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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858 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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859 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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860 } |
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861 dst = z80_save_reg(dst, inst, opts); |
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862 dst = z80_save_ea(dst, inst, opts); |
213
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|
863 break; |
274
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|
864 //case Z80_DAA: |
213
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|
865 case Z80_CPL: |
274
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|
866 dst = zcycles(dst, 4); |
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867 dst = not_r(dst, opts->regs[Z80_A], SZ_B); |
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|
868 //TODO: Implement half-carry flag |
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869 dst = mov_irdisp8(dst, 1, CONTEXT, zf_off(ZF_N), SZ_B); |
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870 break; |
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871 case Z80_NEG: |
be2b845d3e94
Implement CPL and NEG (untested)
Mike Pavone <pavone@retrodev.com>
parents:
273
diff
changeset
|
872 dst = zcycles(dst, 8); |
be2b845d3e94
Implement CPL and NEG (untested)
Mike Pavone <pavone@retrodev.com>
parents:
273
diff
changeset
|
873 dst = neg_r(dst, opts->regs[Z80_A], SZ_B); |
be2b845d3e94
Implement CPL and NEG (untested)
Mike Pavone <pavone@retrodev.com>
parents:
273
diff
changeset
|
874 //TODO: Implement half-carry flag |
be2b845d3e94
Implement CPL and NEG (untested)
Mike Pavone <pavone@retrodev.com>
parents:
273
diff
changeset
|
875 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
be2b845d3e94
Implement CPL and NEG (untested)
Mike Pavone <pavone@retrodev.com>
parents:
273
diff
changeset
|
876 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
be2b845d3e94
Implement CPL and NEG (untested)
Mike Pavone <pavone@retrodev.com>
parents:
273
diff
changeset
|
877 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
be2b845d3e94
Implement CPL and NEG (untested)
Mike Pavone <pavone@retrodev.com>
parents:
273
diff
changeset
|
878 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
be2b845d3e94
Implement CPL and NEG (untested)
Mike Pavone <pavone@retrodev.com>
parents:
273
diff
changeset
|
879 dst = mov_irdisp8(dst, 1, CONTEXT, zf_off(ZF_N), SZ_B); |
be2b845d3e94
Implement CPL and NEG (untested)
Mike Pavone <pavone@retrodev.com>
parents:
273
diff
changeset
|
880 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
881 case Z80_CCF: |
257 | 882 dst = zcycles(dst, 4); |
883 dst = xor_irdisp8(dst, 1, CONTEXT, zf_off(ZF_C), SZ_B); | |
884 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); | |
885 //TODO: Implement half-carry flag | |
886 break; | |
887 case Z80_SCF: | |
888 dst = zcycles(dst, 4); | |
889 dst = mov_irdisp8(dst, 1, CONTEXT, zf_off(ZF_C), SZ_B); | |
890 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); | |
891 //TODO: Implement half-carry flag | |
892 break; | |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
893 case Z80_NOP: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
894 if (inst->immed == 42) { |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
895 dst = call(dst, (uint8_t *)z80_save_context); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
896 dst = mov_rr(dst, CONTEXT, RDI, SZ_Q); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
897 dst = jmp(dst, (uint8_t *)z80_print_regs_exit); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
898 } else { |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
899 dst = zcycles(dst, 4 * inst->immed); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
900 } |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
901 break; |
285
021aeb6df19b
Implement HALT (sort of tested)
Mike Pavone <pavone@retrodev.com>
parents:
284
diff
changeset
|
902 case Z80_HALT: |
021aeb6df19b
Implement HALT (sort of tested)
Mike Pavone <pavone@retrodev.com>
parents:
284
diff
changeset
|
903 dst = zcycles(dst, 4); |
021aeb6df19b
Implement HALT (sort of tested)
Mike Pavone <pavone@retrodev.com>
parents:
284
diff
changeset
|
904 dst = mov_ir(dst, address, SCRATCH1, SZ_W); |
021aeb6df19b
Implement HALT (sort of tested)
Mike Pavone <pavone@retrodev.com>
parents:
284
diff
changeset
|
905 uint8_t * call_inst = dst; |
021aeb6df19b
Implement HALT (sort of tested)
Mike Pavone <pavone@retrodev.com>
parents:
284
diff
changeset
|
906 dst = call(dst, (uint8_t *)z80_halt); |
021aeb6df19b
Implement HALT (sort of tested)
Mike Pavone <pavone@retrodev.com>
parents:
284
diff
changeset
|
907 dst = jmp(dst, call_inst); |
021aeb6df19b
Implement HALT (sort of tested)
Mike Pavone <pavone@retrodev.com>
parents:
284
diff
changeset
|
908 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
909 case Z80_DI: |
243
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
910 dst = zcycles(dst, 4); |
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
911 dst = mov_irdisp8(dst, 0, CONTEXT, offsetof(z80_context, iff1), SZ_B); |
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
912 dst = mov_irdisp8(dst, 0, CONTEXT, offsetof(z80_context, iff2), SZ_B); |
250
5f1b68cecfc7
Implemented basic interrupt support in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
248
diff
changeset
|
913 dst = mov_rdisp8r(dst, CONTEXT, offsetof(z80_context, sync_cycle), ZLIMIT, SZ_D); |
243
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
914 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
915 case Z80_EI: |
243
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
916 //TODO: Implement interrupt enable latency of 1 instruction afer EI |
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
917 dst = zcycles(dst, 4); |
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
918 dst = mov_irdisp8(dst, 1, CONTEXT, offsetof(z80_context, iff1), SZ_B); |
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
919 dst = mov_irdisp8(dst, 1, CONTEXT, offsetof(z80_context, iff2), SZ_B); |
250
5f1b68cecfc7
Implemented basic interrupt support in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
248
diff
changeset
|
920 dst = call(dst, (uint8_t *)z80_do_sync); |
243
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
921 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
922 case Z80_IM: |
243
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
923 dst = zcycles(dst, 4); |
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
924 dst = mov_irdisp8(dst, inst->immed, CONTEXT, offsetof(z80_context, im), SZ_B); |
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
925 break; |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
926 case Z80_RLC: |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
927 cycles = inst->immed == 0 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8); |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
928 dst = zcycles(dst, cycles); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
929 if (inst->reg == Z80_UNUSED) { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
930 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
931 dst = zcycles(dst, 1); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
932 } else { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
933 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
934 } |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
935 dst = rol_ir(dst, 1, dst_op.base, SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
936 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
937 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
938 //TODO: Implement half-carry flag |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
939 dst = cmp_ir(dst, 0, dst_op.base, SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
940 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
941 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
942 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
943 if (inst->reg == Z80_UNUSED) { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
944 dst = z80_save_result(dst, inst); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
945 } else { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
946 dst = z80_save_reg(dst, inst, opts); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
947 } |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
948 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
949 case Z80_RL: |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
950 cycles = inst->immed == 0 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8); |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
951 dst = zcycles(dst, cycles); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
952 if (inst->reg == Z80_UNUSED) { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
953 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
954 dst = zcycles(dst, 1); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
955 } else { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
956 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
957 } |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
958 dst = bt_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
959 dst = rcl_ir(dst, 1, dst_op.base, SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
960 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
961 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
962 //TODO: Implement half-carry flag |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
963 dst = cmp_ir(dst, 0, dst_op.base, SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
964 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
965 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
966 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
967 if (inst->reg == Z80_UNUSED) { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
968 dst = z80_save_result(dst, inst); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
969 } else { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
970 dst = z80_save_reg(dst, inst, opts); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
971 } |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
972 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
973 case Z80_RRC: |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
974 cycles = inst->immed == 0 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8); |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
975 dst = zcycles(dst, cycles); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
976 if (inst->reg == Z80_UNUSED) { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
977 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
978 dst = zcycles(dst, 1); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
979 } else { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
980 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
981 } |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
982 dst = ror_ir(dst, 1, dst_op.base, SZ_B); |
682e505f5757
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983 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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984 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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985 //TODO: Implement half-carry flag |
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986 dst = cmp_ir(dst, 0, dst_op.base, SZ_B); |
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987 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
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988 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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989 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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990 if (inst->reg == Z80_UNUSED) { |
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991 dst = z80_save_result(dst, inst); |
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992 } else { |
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993 dst = z80_save_reg(dst, inst, opts); |
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|
994 } |
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995 break; |
213
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|
996 case Z80_RR: |
275
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|
997 cycles = inst->immed == 0 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8); |
247
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998 dst = zcycles(dst, cycles); |
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|
999 if (inst->reg == Z80_UNUSED) { |
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1000 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
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1001 dst = zcycles(dst, 1); |
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|
1002 } else { |
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1003 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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1004 } |
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1005 dst = bt_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
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1006 dst = rcr_ir(dst, 1, dst_op.base, SZ_B); |
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1007 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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1008 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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|
1009 //TODO: Implement half-carry flag |
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1010 dst = cmp_ir(dst, 0, dst_op.base, SZ_B); |
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1011 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
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1012 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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1013 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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1014 if (inst->reg == Z80_UNUSED) { |
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1015 dst = z80_save_result(dst, inst); |
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1016 } else { |
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1017 dst = z80_save_reg(dst, inst, opts); |
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1018 } |
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1019 break; |
275
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|
1020 case Z80_SLA: |
213
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|
1021 case Z80_SLL: |
275
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1022 cycles = inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8; |
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|
1023 dst = zcycles(dst, cycles); |
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1024 if (inst->reg == Z80_UNUSED) { |
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1025 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
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1026 dst = zcycles(dst, 1); |
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274
diff
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1027 } else { |
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1028 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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|
1029 } |
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1030 dst = shl_ir(dst, 1, dst_op.base, SZ_B); |
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1031 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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274
diff
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|
1032 //TODO: Implement half-carry flag |
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274
diff
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|
1033 dst = cmp_ir(dst, 0, dst_op.base, SZ_B); |
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diff
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|
1034 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
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diff
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1035 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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diff
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1036 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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274
diff
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|
1037 if (inst->reg == Z80_UNUSED) { |
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274
diff
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|
1038 dst = z80_save_result(dst, inst); |
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274
diff
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|
1039 } else { |
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274
diff
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|
1040 dst = z80_save_reg(dst, inst, opts); |
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274
diff
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|
1041 } |
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274
diff
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|
1042 break; |
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274
diff
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|
1043 case Z80_SRA: |
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274
diff
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|
1044 cycles = inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8; |
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274
diff
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|
1045 dst = zcycles(dst, cycles); |
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274
diff
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|
1046 if (inst->reg == Z80_UNUSED) { |
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274
diff
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|
1047 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
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274
diff
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|
1048 dst = zcycles(dst, 1); |
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274
diff
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|
1049 } else { |
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274
diff
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|
1050 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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274
diff
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|
1051 } |
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274
diff
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|
1052 dst = sar_ir(dst, 1, dst_op.base, SZ_B); |
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274
diff
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|
1053 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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274
diff
changeset
|
1054 //TODO: Implement half-carry flag |
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Mike Pavone <pavone@retrodev.com>
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274
diff
changeset
|
1055 dst = cmp_ir(dst, 0, dst_op.base, SZ_B); |
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274
diff
changeset
|
1056 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
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274
diff
changeset
|
1057 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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274
diff
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|
1058 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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274
diff
changeset
|
1059 if (inst->reg == Z80_UNUSED) { |
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274
diff
changeset
|
1060 dst = z80_save_result(dst, inst); |
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274
diff
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|
1061 } else { |
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274
diff
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|
1062 dst = z80_save_reg(dst, inst, opts); |
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274
diff
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|
1063 } |
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274
diff
changeset
|
1064 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1065 case Z80_SRL: |
275
1a7d0a964ad2
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274
diff
changeset
|
1066 cycles = inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8; |
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274
diff
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|
1067 dst = zcycles(dst, cycles); |
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274
diff
changeset
|
1068 if (inst->reg == Z80_UNUSED) { |
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274
diff
changeset
|
1069 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
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274
diff
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|
1070 dst = zcycles(dst, 1); |
1a7d0a964ad2
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274
diff
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|
1071 } else { |
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274
diff
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|
1072 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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274
diff
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|
1073 } |
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274
diff
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|
1074 dst = shr_ir(dst, 1, dst_op.base, SZ_B); |
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274
diff
changeset
|
1075 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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274
diff
changeset
|
1076 //TODO: Implement half-carry flag |
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274
diff
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|
1077 dst = cmp_ir(dst, 0, dst_op.base, SZ_B); |
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274
diff
changeset
|
1078 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
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274
diff
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|
1079 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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274
diff
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|
1080 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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274
diff
changeset
|
1081 if (inst->reg == Z80_UNUSED) { |
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274
diff
changeset
|
1082 dst = z80_save_result(dst, inst); |
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274
diff
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|
1083 } else { |
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274
diff
changeset
|
1084 dst = z80_save_reg(dst, inst, opts); |
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diff
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|
1085 } |
286 | 1086 case Z80_RLD: |
1087 dst = zcycles(dst, 8); | |
1088 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH1, SZ_W); | |
1089 dst = call(dst, (uint8_t *)z80_read_byte); | |
1090 //Before: (HL) = 0x12, A = 0x34 | |
1091 //After: (HL) = 0x24, A = 0x31 | |
1092 dst = mov_rr(dst, opts->regs[Z80_A], SCRATCH2, SZ_B); | |
1093 dst = shl_ir(dst, 4, SCRATCH1, SZ_W); | |
1094 dst = and_ir(dst, 0xF, SCRATCH2, SZ_W); | |
1095 dst = and_ir(dst, 0xFFF, SCRATCH1, SZ_W); | |
1096 dst = and_ir(dst, 0xF0, opts->regs[Z80_A], SZ_B); | |
1097 dst = or_rr(dst, SCRATCH2, SCRATCH1, SZ_W); | |
1098 //SCRATCH1 = 0x0124 | |
1099 dst = ror_ir(dst, 8, SCRATCH1, SZ_W); | |
1100 dst = zcycles(dst, 4); | |
1101 dst = or_rr(dst, SCRATCH1, opts->regs[Z80_A], SZ_B); | |
287
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286
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|
1102 //set flags |
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286
diff
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|
1103 //TODO: Implement half-carry flag |
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|
1104 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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286
diff
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|
1105 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
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diff
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|
1106 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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diff
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|
1107 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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1108 |
286 | 1109 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH2, SZ_W); |
1110 dst = ror_ir(dst, 8, SCRATCH1, SZ_W); | |
1111 dst = call(dst, (uint8_t *)z80_write_byte); | |
1112 break; | |
287
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286
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|
1113 case Z80_RRD: |
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286
diff
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|
1114 dst = zcycles(dst, 8); |
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1115 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH1, SZ_W); |
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1116 dst = call(dst, (uint8_t *)z80_read_byte); |
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286
diff
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|
1117 //Before: (HL) = 0x12, A = 0x34 |
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286
diff
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|
1118 //After: (HL) = 0x41, A = 0x32 |
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diff
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|
1119 dst = movzx_rr(dst, opts->regs[Z80_A], SCRATCH2, SZ_B, SZ_W); |
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|
1120 dst = ror_ir(dst, 4, SCRATCH1, SZ_W); |
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286
diff
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|
1121 dst = shl_ir(dst, 4, SCRATCH2, SZ_W); |
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286
diff
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|
1122 dst = and_ir(dst, 0xF00F, SCRATCH1, SZ_W); |
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diff
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|
1123 dst = and_ir(dst, 0xF0, opts->regs[Z80_A], SZ_B); |
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286
diff
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|
1124 //SCRATCH1 = 0x2001 |
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286
diff
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|
1125 //SCRATCH2 = 0x0040 |
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1126 dst = or_rr(dst, SCRATCH2, SCRATCH1, SZ_W); |
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286
diff
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|
1127 //SCRATCH1 = 0x2041 |
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286
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1128 dst = ror_ir(dst, 8, SCRATCH1, SZ_W); |
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286
diff
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|
1129 dst = zcycles(dst, 4); |
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|
1130 dst = shr_ir(dst, 4, SCRATCH1, SZ_B); |
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286
diff
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|
1131 dst = or_rr(dst, SCRATCH1, opts->regs[Z80_A], SZ_B); |
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286
diff
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|
1132 //set flags |
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286
diff
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|
1133 //TODO: Implement half-carry flag |
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Mike Pavone <pavone@retrodev.com>
parents:
286
diff
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|
1134 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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286
diff
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|
1135 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
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286
diff
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|
1136 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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Mike Pavone <pavone@retrodev.com>
parents:
286
diff
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|
1137 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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Mike Pavone <pavone@retrodev.com>
parents:
286
diff
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|
1138 |
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diff
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|
1139 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH2, SZ_W); |
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286
diff
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|
1140 dst = ror_ir(dst, 8, SCRATCH1, SZ_W); |
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Mike Pavone <pavone@retrodev.com>
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286
diff
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|
1141 dst = call(dst, (uint8_t *)z80_write_byte); |
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Mike Pavone <pavone@retrodev.com>
parents:
286
diff
changeset
|
1142 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
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|
1143 case Z80_BIT: |
239
a5bea9711a46
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238
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|
1144 cycles = (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) ? 8 : 16; |
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238
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|
1145 dst = zcycles(dst, cycles); |
a5bea9711a46
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238
diff
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|
1146 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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238
diff
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|
1147 if (inst->addr_mode != Z80_REG) { |
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238
diff
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|
1148 //Reads normally take 3 cycles, but the read at the end of a bit instruction takes 4 |
a5bea9711a46
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238
diff
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|
1149 dst = zcycles(dst, 1); |
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238
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|
1150 } |
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|
1151 dst = bt_ir(dst, inst->immed, src_op.base, SZ_B); |
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238
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|
1152 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_Z)); |
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238
diff
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|
1153 break; |
247
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246
diff
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|
1154 case Z80_SET: |
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246
diff
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|
1155 cycles = (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) ? 8 : 16; |
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|
1156 dst = zcycles(dst, cycles); |
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1157 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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diff
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|
1158 if (inst->addr_mode != Z80_REG) { |
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diff
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|
1159 //Reads normally take 3 cycles, but the read in the middle of a set instruction takes 4 |
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246
diff
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|
1160 dst = zcycles(dst, 1); |
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246
diff
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|
1161 } |
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diff
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|
1162 dst = bts_ir(dst, inst->immed, src_op.base, SZ_B); |
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246
diff
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|
1163 if (inst->addr_mode != Z80_REG) { |
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246
diff
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|
1164 dst = z80_save_result(dst, inst); |
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246
diff
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|
1165 } |
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246
diff
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|
1166 break; |
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246
diff
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|
1167 case Z80_RES: |
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246
diff
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|
1168 cycles = (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) ? 8 : 16; |
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246
diff
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|
1169 dst = zcycles(dst, cycles); |
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246
diff
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|
1170 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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246
diff
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|
1171 if (inst->addr_mode != Z80_REG) { |
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246
diff
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|
1172 //Reads normally take 3 cycles, but the read in the middle of a set instruction takes 4 |
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246
diff
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|
1173 dst = zcycles(dst, 1); |
682e505f5757
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246
diff
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|
1174 } |
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246
diff
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|
1175 dst = btr_ir(dst, inst->immed, src_op.base, SZ_B); |
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246
diff
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|
1176 if (inst->addr_mode != Z80_REG) { |
682e505f5757
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246
diff
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|
1177 dst = z80_save_result(dst, inst); |
682e505f5757
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246
diff
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|
1178 } |
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246
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|
1179 break; |
236
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235
diff
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|
1180 case Z80_JP: { |
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235
diff
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|
1181 cycles = 4; |
239
a5bea9711a46
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238
diff
changeset
|
1182 if (inst->addr_mode != Z80_REG) { |
236
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235
diff
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|
1183 cycles += 6; |
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1184 } else if(inst->ea_reg == Z80_IX || inst->ea_reg == Z80_IY) { |
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235
diff
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|
1185 cycles += 4; |
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|
1186 } |
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235
diff
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|
1187 dst = zcycles(dst, cycles); |
239
a5bea9711a46
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238
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|
1188 if (inst->addr_mode != Z80_REG_INDIRECT && inst->immed < 0x4000) { |
236
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235
diff
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|
1189 uint8_t * call_dst = z80_get_native_address(context, inst->immed); |
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|
1190 if (!call_dst) { |
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|
1191 opts->deferred = defer_address(opts->deferred, inst->immed, dst + 1); |
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|
1192 //fake address to force large displacement |
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235
diff
changeset
|
1193 call_dst = dst + 256; |
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235
diff
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|
1194 } |
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|
1195 dst = jmp(dst, call_dst); |
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diff
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|
1196 } else { |
239
a5bea9711a46
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238
diff
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|
1197 if (inst->addr_mode == Z80_REG_INDIRECT) { |
236
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235
diff
changeset
|
1198 dst = mov_rr(dst, opts->regs[inst->ea_reg], SCRATCH1, SZ_W); |
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235
diff
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|
1199 } else { |
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235
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|
1200 dst = mov_ir(dst, inst->immed, SCRATCH1, SZ_W); |
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235
diff
changeset
|
1201 } |
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235
diff
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|
1202 dst = call(dst, (uint8_t *)z80_native_addr); |
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235
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changeset
|
1203 dst = jmp_r(dst, SCRATCH1); |
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235
diff
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|
1204 } |
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235
diff
changeset
|
1205 break; |
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235
diff
changeset
|
1206 } |
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235
diff
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|
1207 case Z80_JPCC: { |
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235
diff
changeset
|
1208 dst = zcycles(dst, 7);//T States: 4,3 |
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235
diff
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|
1209 uint8_t cond = CC_Z; |
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1210 switch (inst->reg) |
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1211 { |
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1212 case Z80_CC_NZ: |
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1213 cond = CC_NZ; |
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1214 case Z80_CC_Z: |
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1215 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_Z), SZ_B); |
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1216 break; |
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1217 case Z80_CC_NC: |
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1218 cond = CC_NZ; |
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1219 case Z80_CC_C: |
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1220 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
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1221 break; |
238
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|
1222 case Z80_CC_PO: |
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|
1223 cond = CC_NZ; |
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|
1224 case Z80_CC_PE: |
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|
1225 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_PV), SZ_B); |
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|
1226 break; |
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|
1227 case Z80_CC_P: |
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|
1228 case Z80_CC_M: |
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|
1229 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_S), SZ_B); |
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|
1230 break; |
236
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|
1231 } |
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|
1232 uint8_t *no_jump_off = dst+1; |
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|
1233 dst = jcc(dst, cond, dst+2); |
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1234 dst = zcycles(dst, 5);//T States: 5 |
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1235 uint16_t dest_addr = inst->immed; |
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1236 if (dest_addr < 0x4000) { |
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|
1237 uint8_t * call_dst = z80_get_native_address(context, dest_addr); |
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1238 if (!call_dst) { |
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|
1239 opts->deferred = defer_address(opts->deferred, dest_addr, dst + 1); |
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|
1240 //fake address to force large displacement |
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1241 call_dst = dst + 256; |
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|
1242 } |
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|
1243 dst = jmp(dst, call_dst); |
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1244 } else { |
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1245 dst = mov_ir(dst, dest_addr, SCRATCH1, SZ_W); |
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1246 dst = call(dst, (uint8_t *)z80_native_addr); |
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|
1247 dst = jmp_r(dst, SCRATCH1); |
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|
1248 } |
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|
1249 *no_jump_off = dst - (no_jump_off+1); |
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|
1250 break; |
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|
1251 } |
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1252 case Z80_JR: { |
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1253 dst = zcycles(dst, 12);//T States: 4,3,5 |
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1254 uint16_t dest_addr = address + inst->immed + 2; |
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1255 if (dest_addr < 0x4000) { |
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|
1256 uint8_t * call_dst = z80_get_native_address(context, dest_addr); |
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1257 if (!call_dst) { |
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1258 opts->deferred = defer_address(opts->deferred, dest_addr, dst + 1); |
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1259 //fake address to force large displacement |
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1260 call_dst = dst + 256; |
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|
1261 } |
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1262 dst = jmp(dst, call_dst); |
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1263 } else { |
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1264 dst = mov_ir(dst, dest_addr, SCRATCH1, SZ_W); |
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1265 dst = call(dst, (uint8_t *)z80_native_addr); |
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1266 dst = jmp_r(dst, SCRATCH1); |
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1267 } |
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|
1268 break; |
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|
1269 } |
235
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1270 case Z80_JRCC: { |
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1271 dst = zcycles(dst, 7);//T States: 4,3 |
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1272 uint8_t cond = CC_Z; |
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1273 switch (inst->reg) |
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|
1274 { |
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|
1275 case Z80_CC_NZ: |
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1276 cond = CC_NZ; |
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1277 case Z80_CC_Z: |
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1278 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_Z), SZ_B); |
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1279 break; |
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|
1280 case Z80_CC_NC: |
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1281 cond = CC_NZ; |
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|
1282 case Z80_CC_C: |
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1283 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
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|
1284 break; |
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|
1285 } |
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|
1286 uint8_t *no_jump_off = dst+1; |
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1287 dst = jcc(dst, cond, dst+2); |
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1288 dst = zcycles(dst, 5);//T States: 5 |
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1289 uint16_t dest_addr = address + inst->immed + 2; |
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1290 if (dest_addr < 0x4000) { |
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|
1291 uint8_t * call_dst = z80_get_native_address(context, dest_addr); |
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1292 if (!call_dst) { |
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1293 opts->deferred = defer_address(opts->deferred, dest_addr, dst + 1); |
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1294 //fake address to force large displacement |
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1295 call_dst = dst + 256; |
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|
1296 } |
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1297 dst = jmp(dst, call_dst); |
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1298 } else { |
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1299 dst = mov_ir(dst, dest_addr, SCRATCH1, SZ_W); |
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1300 dst = call(dst, (uint8_t *)z80_native_addr); |
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1301 dst = jmp_r(dst, SCRATCH1); |
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1302 } |
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1303 *no_jump_off = dst - (no_jump_off+1); |
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|
1304 break; |
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1305 } |
239
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1306 case Z80_DJNZ: |
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1307 dst = zcycles(dst, 8);//T States: 5,3 |
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1308 dst = sub_ir(dst, 1, opts->regs[Z80_B], SZ_B); |
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1309 uint8_t *no_jump_off = dst+1; |
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1310 dst = jcc(dst, CC_Z, dst+2); |
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1311 dst = zcycles(dst, 5);//T States: 5 |
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1312 uint16_t dest_addr = address + inst->immed + 2; |
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1313 if (dest_addr < 0x4000) { |
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1314 uint8_t * call_dst = z80_get_native_address(context, dest_addr); |
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1315 if (!call_dst) { |
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1316 opts->deferred = defer_address(opts->deferred, dest_addr, dst + 1); |
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|
1317 //fake address to force large displacement |
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1318 call_dst = dst + 256; |
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1319 } |
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1320 dst = jmp(dst, call_dst); |
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1321 } else { |
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changeset
|
1322 dst = mov_ir(dst, dest_addr, SCRATCH1, SZ_W); |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
1323 dst = call(dst, (uint8_t *)z80_native_addr); |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
1324 dst = jmp_r(dst, SCRATCH1); |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
1325 } |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
1326 *no_jump_off = dst - (no_jump_off+1); |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
1327 break; |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1328 case Z80_CALL: { |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1329 dst = zcycles(dst, 11);//T States: 4,3,4 |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1330 dst = sub_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
253
3b34deba4ca0
Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents:
252
diff
changeset
|
1331 dst = mov_ir(dst, address + 3, SCRATCH1, SZ_W); |
3b34deba4ca0
Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents:
252
diff
changeset
|
1332 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W); |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1333 dst = call(dst, (uint8_t *)z80_write_word_highfirst);//T States: 3, 3 |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1334 if (inst->immed < 0x4000) { |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1335 uint8_t * call_dst = z80_get_native_address(context, inst->immed); |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1336 if (!call_dst) { |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1337 opts->deferred = defer_address(opts->deferred, inst->immed, dst + 1); |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1338 //fake address to force large displacement |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1339 call_dst = dst + 256; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1340 } |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1341 dst = jmp(dst, call_dst); |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1342 } else { |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1343 dst = mov_ir(dst, inst->immed, SCRATCH1, SZ_W); |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1344 dst = call(dst, (uint8_t *)z80_native_addr); |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1345 dst = jmp_r(dst, SCRATCH1); |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1346 } |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1347 break; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1348 } |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1349 case Z80_CALLCC: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1350 dst = zcycles(dst, 10);//T States: 4,3,3 (false case) |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1351 uint8_t cond = CC_Z; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1352 switch (inst->reg) |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1353 { |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1354 case Z80_CC_NZ: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1355 cond = CC_NZ; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1356 case Z80_CC_Z: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1357 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_Z), SZ_B); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1358 break; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1359 case Z80_CC_NC: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1360 cond = CC_NZ; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1361 case Z80_CC_C: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1362 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1363 break; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1364 case Z80_CC_PO: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1365 cond = CC_NZ; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1366 case Z80_CC_PE: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1367 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_PV), SZ_B); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1368 break; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1369 case Z80_CC_P: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1370 case Z80_CC_M: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1371 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_S), SZ_B); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1372 break; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1373 } |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1374 uint8_t *no_call_off = dst+1; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1375 dst = jcc(dst, cond, dst+2); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1376 dst = zcycles(dst, 1);//Last of the above T states takes an extra cycle in the true case |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1377 dst = sub_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
253
3b34deba4ca0
Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents:
252
diff
changeset
|
1378 dst = mov_ir(dst, address + 3, SCRATCH1, SZ_W); |
3b34deba4ca0
Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents:
252
diff
changeset
|
1379 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W); |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1380 dst = call(dst, (uint8_t *)z80_write_word_highfirst);//T States: 3, 3 |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1381 if (inst->immed < 0x4000) { |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1382 uint8_t * call_dst = z80_get_native_address(context, inst->immed); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1383 if (!call_dst) { |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1384 opts->deferred = defer_address(opts->deferred, inst->immed, dst + 1); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1385 //fake address to force large displacement |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1386 call_dst = dst + 256; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1387 } |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1388 dst = jmp(dst, call_dst); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1389 } else { |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1390 dst = mov_ir(dst, inst->immed, SCRATCH1, SZ_W); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1391 dst = call(dst, (uint8_t *)z80_native_addr); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1392 dst = jmp_r(dst, SCRATCH1); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1393 } |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1394 *no_call_off = dst - (no_call_off+1); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1395 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1396 case Z80_RET: |
235
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1397 dst = zcycles(dst, 4);//T States: 4 |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1398 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1399 dst = call(dst, (uint8_t *)z80_read_word);//T STates: 3, 3 |
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1400 dst = add_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1401 dst = call(dst, (uint8_t *)z80_native_addr); |
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1402 dst = jmp_r(dst, SCRATCH1); |
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1403 break; |
246
ed548c77b598
Implement RETCC in Z80 core.
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parents:
243
diff
changeset
|
1404 case Z80_RETCC: { |
ed548c77b598
Implement RETCC in Z80 core.
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parents:
243
diff
changeset
|
1405 dst = zcycles(dst, 5);//T States: 5 |
ed548c77b598
Implement RETCC in Z80 core.
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243
diff
changeset
|
1406 uint8_t cond = CC_Z; |
ed548c77b598
Implement RETCC in Z80 core.
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243
diff
changeset
|
1407 switch (inst->reg) |
ed548c77b598
Implement RETCC in Z80 core.
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parents:
243
diff
changeset
|
1408 { |
ed548c77b598
Implement RETCC in Z80 core.
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parents:
243
diff
changeset
|
1409 case Z80_CC_NZ: |
ed548c77b598
Implement RETCC in Z80 core.
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243
diff
changeset
|
1410 cond = CC_NZ; |
ed548c77b598
Implement RETCC in Z80 core.
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243
diff
changeset
|
1411 case Z80_CC_Z: |
ed548c77b598
Implement RETCC in Z80 core.
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243
diff
changeset
|
1412 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_Z), SZ_B); |
ed548c77b598
Implement RETCC in Z80 core.
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243
diff
changeset
|
1413 break; |
ed548c77b598
Implement RETCC in Z80 core.
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243
diff
changeset
|
1414 case Z80_CC_NC: |
ed548c77b598
Implement RETCC in Z80 core.
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243
diff
changeset
|
1415 cond = CC_NZ; |
ed548c77b598
Implement RETCC in Z80 core.
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243
diff
changeset
|
1416 case Z80_CC_C: |
ed548c77b598
Implement RETCC in Z80 core.
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243
diff
changeset
|
1417 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
ed548c77b598
Implement RETCC in Z80 core.
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parents:
243
diff
changeset
|
1418 break; |
ed548c77b598
Implement RETCC in Z80 core.
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243
diff
changeset
|
1419 case Z80_CC_PO: |
ed548c77b598
Implement RETCC in Z80 core.
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243
diff
changeset
|
1420 cond = CC_NZ; |
ed548c77b598
Implement RETCC in Z80 core.
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243
diff
changeset
|
1421 case Z80_CC_PE: |
ed548c77b598
Implement RETCC in Z80 core.
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243
diff
changeset
|
1422 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_PV), SZ_B); |
ed548c77b598
Implement RETCC in Z80 core.
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parents:
243
diff
changeset
|
1423 break; |
ed548c77b598
Implement RETCC in Z80 core.
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243
diff
changeset
|
1424 case Z80_CC_P: |
ed548c77b598
Implement RETCC in Z80 core.
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243
diff
changeset
|
1425 case Z80_CC_M: |
ed548c77b598
Implement RETCC in Z80 core.
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243
diff
changeset
|
1426 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_S), SZ_B); |
ed548c77b598
Implement RETCC in Z80 core.
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parents:
243
diff
changeset
|
1427 break; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1428 } |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1429 uint8_t *no_call_off = dst+1; |
ed548c77b598
Implement RETCC in Z80 core.
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parents:
243
diff
changeset
|
1430 dst = jcc(dst, cond, dst+2); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1431 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1432 dst = call(dst, (uint8_t *)z80_read_word);//T STates: 3, 3 |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1433 dst = add_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1434 dst = call(dst, (uint8_t *)z80_native_addr); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1435 dst = jmp_r(dst, SCRATCH1); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1436 *no_call_off = dst - (no_call_off+1); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1437 break; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1438 } |
283
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1439 case Z80_RETI: |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1440 //For some systems, this may need a callback for signalling interrupt routine completion |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1441 dst = zcycles(dst, 8);//T States: 4, 4 |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1442 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1443 dst = call(dst, (uint8_t *)z80_read_word);//T STates: 3, 3 |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1444 dst = add_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1445 dst = call(dst, (uint8_t *)z80_native_addr); |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1446 dst = jmp_r(dst, SCRATCH1); |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1447 break; |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1448 case Z80_RETN: |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1449 dst = zcycles(dst, 8);//T States: 4, 4 |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1450 dst = mov_rdisp8r(dst, CONTEXT, offsetof(z80_context, iff2), SCRATCH2, SZ_B); |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1451 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1452 dst = mov_rrdisp8(dst, SCRATCH2, CONTEXT, offsetof(z80_context, iff1), SZ_B); |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1453 dst = call(dst, (uint8_t *)z80_read_word);//T STates: 3, 3 |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1454 dst = add_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1455 dst = call(dst, (uint8_t *)z80_native_addr); |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1456 dst = jmp_r(dst, SCRATCH1); |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1457 break; |
241
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1458 case Z80_RST: { |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1459 //RST is basically CALL to an address in page 0 |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1460 dst = zcycles(dst, 5);//T States: 5 |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1461 dst = sub_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
253
3b34deba4ca0
Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents:
252
diff
changeset
|
1462 dst = mov_ir(dst, address + 3, SCRATCH1, SZ_W); |
3b34deba4ca0
Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents:
252
diff
changeset
|
1463 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W); |
241
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1464 dst = call(dst, (uint8_t *)z80_write_word_highfirst);//T States: 3, 3 |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1465 uint8_t * call_dst = z80_get_native_address(context, inst->immed); |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1466 if (!call_dst) { |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1467 opts->deferred = defer_address(opts->deferred, inst->immed, dst + 1); |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1468 //fake address to force large displacement |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1469 call_dst = dst + 256; |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1470 } |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1471 dst = jmp(dst, call_dst); |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1472 break; |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1473 } |
284
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1474 case Z80_IN: |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1475 dst = zcycles(dst, inst->reg == Z80_A ? 7 : 8);//T States: 4 3/4 |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1476 if (inst->addr_mode == Z80_IMMED_INDIRECT) { |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1477 dst = mov_ir(dst, inst->immed, SCRATCH1, SZ_B); |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1478 } else { |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1479 dst = mov_rr(dst, opts->regs[Z80_C], SCRATCH1, SZ_B); |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1480 } |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1481 dst = call(dst, (uint8_t *)z80_io_read); |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1482 translate_z80_reg(inst, &dst_op, dst, opts); |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1483 dst = mov_rr(dst, SCRATCH1, dst_op.base, SZ_B); |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1484 dst = z80_save_reg(dst, inst, opts); |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1485 break; |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1486 /*case Z80_INI: |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1487 case Z80_INIR: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1488 case Z80_IND: |
284
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1489 case Z80_INDR:*/ |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1490 case Z80_OUT: |
284
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1491 dst = zcycles(dst, inst->reg == Z80_A ? 7 : 8);//T States: 4 3/4 |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1492 if ((inst->addr_mode & 0x1F) == Z80_IMMED_INDIRECT) { |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1493 dst = mov_ir(dst, inst->immed, SCRATCH2, SZ_B); |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1494 } else { |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1495 dst = mov_rr(dst, opts->regs[Z80_C], SCRATCH2, SZ_B); |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1496 } |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1497 translate_z80_reg(inst, &src_op, dst, opts); |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1498 dst = mov_rr(dst, dst_op.base, SCRATCH1, SZ_B); |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1499 dst = call(dst, (uint8_t *)z80_io_write); |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1500 dst = z80_save_reg(dst, inst, opts); |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1501 break; |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1502 /*case Z80_OUTI: |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1503 case Z80_OTIR: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1504 case Z80_OUTD: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1505 case Z80_OTDR:*/ |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1506 default: { |
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1507 char disbuf[80]; |
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1508 z80_disasm(inst, disbuf); |
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1509 fprintf(stderr, "unimplemented instruction: %s\n", disbuf); |
259
d9417261366f
Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called.
Mike Pavone <pavone@retrodev.com>
parents:
257
diff
changeset
|
1510 FILE * f = fopen("zram.bin", "wb"); |
d9417261366f
Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called.
Mike Pavone <pavone@retrodev.com>
parents:
257
diff
changeset
|
1511 fwrite(context->mem_pointers[0], 1, 8 * 1024, f); |
d9417261366f
Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called.
Mike Pavone <pavone@retrodev.com>
parents:
257
diff
changeset
|
1512 fclose(f); |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1513 exit(1); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1514 } |
235
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1515 } |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1516 return dst; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1517 } |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1518 |
283
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1519 uint8_t z80_is_terminal(z80inst * inst) |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1520 { |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1521 return inst->op == Z80_RET || inst->op == Z80_RETI || inst->op == Z80_RETN || inst->op == Z80_JP |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1522 || inst->op == Z80_JR || inst->op == Z80_HALT || (inst->op == Z80_NOP && inst->immed == 42); |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1523 } |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1524 |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1525 uint8_t * z80_get_native_address(z80_context * context, uint32_t address) |
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1526 { |
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1527 native_map_slot *map; |
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1528 if (address < 0x4000) { |
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1529 address &= 0x1FFF; |
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1530 map = context->static_code_map; |
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1531 } else if (address >= 0x8000) { |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1532 address &= 0x7FFF; |
279
6be6056735a9
Fix native address lookup in bannked memory area
Mike Pavone <pavone@retrodev.com>
parents:
277
diff
changeset
|
1533 map = context->banked_code_map + context->bank_reg; |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1534 } else { |
268
6c2d7e003a55
Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents:
267
diff
changeset
|
1535 dprintf("z80_get_native_address: %X NULL\n", address); |
235
d9bf8e61c33c
Get Z80 core working for simple programs
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|
1536 return NULL; |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1537 } |
268
6c2d7e003a55
Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
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267
diff
changeset
|
1538 if (!map->base || !map->offsets || map->offsets[address] == INVALID_OFFSET || map->offsets[address] == EXTENSION_WORD) { |
6c2d7e003a55
Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
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267
diff
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|
1539 dprintf("z80_get_native_address: %X NULL\n", address); |
235
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Get Z80 core working for simple programs
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213
diff
changeset
|
1540 return NULL; |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1541 } |
268
6c2d7e003a55
Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
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267
diff
changeset
|
1542 dprintf("z80_get_native_address: %X %p\n", address, map->base + map->offsets[address]); |
235
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Get Z80 core working for simple programs
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diff
changeset
|
1543 return map->base + map->offsets[address]; |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1544 } |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1545 |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1546 uint8_t z80_get_native_inst_size(x86_z80_options * opts, uint32_t address) |
235
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Get Z80 core working for simple programs
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213
diff
changeset
|
1547 { |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1548 if (address >= 0x4000) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1549 return 0; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1550 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1551 return opts->ram_inst_sizes[address & 0x1FFF]; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1552 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1553 |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1554 void z80_map_native_address(z80_context * context, uint32_t address, uint8_t * native_address, uint8_t size, uint8_t native_size) |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1555 { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1556 uint32_t orig_address = address; |
235
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Get Z80 core working for simple programs
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diff
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|
1557 native_map_slot *map; |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
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250
diff
changeset
|
1558 x86_z80_options * opts = context->options; |
235
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Get Z80 core working for simple programs
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diff
changeset
|
1559 if (address < 0x4000) { |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1560 address &= 0x1FFF; |
d9bf8e61c33c
Get Z80 core working for simple programs
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diff
changeset
|
1561 map = context->static_code_map; |
252
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Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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250
diff
changeset
|
1562 opts->ram_inst_sizes[address] = native_size; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
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250
diff
changeset
|
1563 context->ram_code_flags[(address & 0x1C00) >> 10] |= 1 << ((address & 0x380) >> 7); |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
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250
diff
changeset
|
1564 context->ram_code_flags[((address + size) & 0x1C00) >> 10] |= 1 << (((address + size) & 0x380) >> 7); |
235
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Get Z80 core working for simple programs
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|
1565 } else if (address >= 0x8000) { |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1566 address &= 0x7FFF; |
279
6be6056735a9
Fix native address lookup in bannked memory area
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diff
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|
1567 map = context->banked_code_map + context->bank_reg; |
235
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|
1568 if (!map->offsets) { |
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Get Z80 core working for simple programs
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diff
changeset
|
1569 map->offsets = malloc(sizeof(int32_t) * 0x8000); |
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Get Z80 core working for simple programs
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|
1570 memset(map->offsets, 0xFF, sizeof(int32_t) * 0x8000); |
d9bf8e61c33c
Get Z80 core working for simple programs
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changeset
|
1571 } |
d9bf8e61c33c
Get Z80 core working for simple programs
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diff
changeset
|
1572 } else { |
d9bf8e61c33c
Get Z80 core working for simple programs
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diff
changeset
|
1573 return; |
d9bf8e61c33c
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changeset
|
1574 } |
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Get Z80 core working for simple programs
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diff
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|
1575 if (!map->base) { |
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|
1576 map->base = native_address; |
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diff
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|
1577 } |
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|
1578 map->offsets[address] = native_address - map->base; |
253
3b34deba4ca0
Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
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|
1579 for(--size, orig_address++; size; --size, orig_address++) { |
252
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Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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|
1580 address = orig_address; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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changeset
|
1581 if (address < 0x4000) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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250
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|
1582 address &= 0x1FFF; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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|
1583 map = context->static_code_map; |
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Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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changeset
|
1584 } else if (address >= 0x8000) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1585 address &= 0x7FFF; |
279
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Fix native address lookup in bannked memory area
Mike Pavone <pavone@retrodev.com>
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|
1586 map = context->banked_code_map + context->bank_reg; |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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changeset
|
1587 } else { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
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250
diff
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|
1588 return; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
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changeset
|
1589 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1590 if (!map->offsets) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
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changeset
|
1591 map->offsets = malloc(sizeof(int32_t) * 0x8000); |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
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|
1592 memset(map->offsets, 0xFF, sizeof(int32_t) * 0x8000); |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
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250
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|
1593 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1594 map->offsets[address] = EXTENSION_WORD; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
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250
diff
changeset
|
1595 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1596 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
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|
1597 |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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|
1598 #define INVALID_INSTRUCTION_START 0xFEEDFEED |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
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250
diff
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|
1599 |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
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|
1600 uint32_t z80_get_instruction_start(native_map_slot * static_code_map, uint32_t address) |
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Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
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250
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changeset
|
1601 { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
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250
diff
changeset
|
1602 if (!static_code_map->base || address >= 0x4000) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1603 return INVALID_INSTRUCTION_START; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1604 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1605 address &= 0x1FFF; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1606 if (static_code_map->offsets[address] == INVALID_OFFSET) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1607 return INVALID_INSTRUCTION_START; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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250
diff
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|
1608 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1609 while (static_code_map->offsets[address] == EXTENSION_WORD) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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|
1610 --address; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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|
1611 address &= 0x1FFF; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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|
1612 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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diff
changeset
|
1613 return address; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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250
diff
changeset
|
1614 } |
63b9a500a00b
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250
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|
1615 |
63b9a500a00b
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|
1616 z80_context * z80_handle_code_write(uint32_t address, z80_context * context) |
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Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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changeset
|
1617 { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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|
1618 uint32_t inst_start = z80_get_instruction_start(context->static_code_map, address); |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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changeset
|
1619 if (inst_start != INVALID_INSTRUCTION_START) { |
63b9a500a00b
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|
1620 uint8_t * dst = z80_get_native_address(context, inst_start); |
268
6c2d7e003a55
Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
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|
1621 dprintf("patching code at %p for Z80 instruction at %X due to write to %X\n", dst, inst_start, address); |
252
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|
1622 dst = mov_ir(dst, inst_start, SCRATCH1, SZ_D); |
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|
1623 dst = jmp(dst, (uint8_t *)z80_retrans_stub); |
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|
1624 } |
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|
1625 return context; |
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|
1626 } |
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changeset
|
1627 |
264
8fd6652e56f8
Fix a crash bug in instruction retranslation
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|
1628 uint8_t * z80_get_native_address_trans(z80_context * context, uint32_t address) |
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Fix a crash bug in instruction retranslation
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262
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changeset
|
1629 { |
8fd6652e56f8
Fix a crash bug in instruction retranslation
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changeset
|
1630 uint8_t * addr = z80_get_native_address(context, address); |
8fd6652e56f8
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262
diff
changeset
|
1631 if (!addr) { |
8fd6652e56f8
Fix a crash bug in instruction retranslation
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diff
changeset
|
1632 translate_z80_stream(context, address); |
8fd6652e56f8
Fix a crash bug in instruction retranslation
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changeset
|
1633 addr = z80_get_native_address(context, address); |
8fd6652e56f8
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diff
changeset
|
1634 if (!addr) { |
8fd6652e56f8
Fix a crash bug in instruction retranslation
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diff
changeset
|
1635 printf("Failed to translate %X to native code\n", address); |
8fd6652e56f8
Fix a crash bug in instruction retranslation
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262
diff
changeset
|
1636 } |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1637 } |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1638 return addr; |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1639 } |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1640 |
266
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1641 void z80_handle_deferred(z80_context * context) |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1642 { |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1643 x86_z80_options * opts = context->options; |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1644 process_deferred(&opts->deferred, context, (native_addr_func)z80_get_native_address); |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1645 if (opts->deferred) { |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1646 translate_z80_stream(context, opts->deferred->address); |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1647 } |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1648 } |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1649 |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1650 void * z80_retranslate_inst(uint32_t address, z80_context * context) |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1651 { |
266
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Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1652 char disbuf[80]; |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1653 x86_z80_options * opts = context->options; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1654 uint8_t orig_size = z80_get_native_inst_size(opts, address); |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1655 uint8_t * orig_start = z80_get_native_address(context, address); |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1656 uint32_t orig = address; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1657 address &= 0x1FFF; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1658 uint8_t * dst = opts->cur_code; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1659 uint8_t * dst_end = opts->code_end; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1660 uint8_t *after, *inst = context->mem_pointers[0] + address; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1661 z80inst instbuf; |
268
6c2d7e003a55
Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents:
267
diff
changeset
|
1662 dprintf("Retranslating code at Z80 address %X, native address %p\n", address, orig_start); |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1663 after = z80_decode(inst, &instbuf); |
268
6c2d7e003a55
Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents:
267
diff
changeset
|
1664 #ifdef DO_DEBUG_PRINT |
267
1788e3f29c28
Don't mix *H regs with the REX prefix
Mike Pavone <pavone@retrodev.com>
parents:
266
diff
changeset
|
1665 z80_disasm(&instbuf, disbuf); |
266
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1666 if (instbuf.op == Z80_NOP) { |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1667 printf("%X\t%s(%d)\n", address, disbuf, instbuf.immed); |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1668 } else { |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1669 printf("%X\t%s\n", address, disbuf); |
267
1788e3f29c28
Don't mix *H regs with the REX prefix
Mike Pavone <pavone@retrodev.com>
parents:
266
diff
changeset
|
1670 } |
268
6c2d7e003a55
Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents:
267
diff
changeset
|
1671 #endif |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1672 if (orig_size != ZMAX_NATIVE_SIZE) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1673 if (dst_end - dst < ZMAX_NATIVE_SIZE) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1674 size_t size = 1024*1024; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1675 dst = alloc_code(&size); |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1676 opts->code_end = dst_end = dst + size; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1677 opts->cur_code = dst; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1678 } |
282
7b8a49220e3b
Remove deferred address entries from abandoned translations inside z80_retrans_inst
Mike Pavone <pavone@retrodev.com>
parents:
279
diff
changeset
|
1679 deferred_addr * orig_deferred = opts->deferred; |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1680 uint8_t * native_end = translate_z80inst(&instbuf, dst, context, address); |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1681 if ((native_end - dst) <= orig_size) { |
264
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1682 uint8_t * native_next = z80_get_native_address(context, address + after-inst); |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1683 if (native_next && ((native_next == orig_start + orig_size) || (orig_size - (native_end - dst)) > 5)) { |
282
7b8a49220e3b
Remove deferred address entries from abandoned translations inside z80_retrans_inst
Mike Pavone <pavone@retrodev.com>
parents:
279
diff
changeset
|
1684 remove_deferred_until(&opts->deferred, orig_deferred); |
264
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1685 native_end = translate_z80inst(&instbuf, orig_start, context, address); |
266
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1686 if (native_next == orig_start + orig_size && (native_next-native_end) < 2) { |
264
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1687 while (native_end < orig_start + orig_size) { |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1688 *(native_end++) = 0x90; //NOP |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1689 } |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1690 } else { |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1691 jmp(native_end, native_next); |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1692 } |
266
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1693 z80_handle_deferred(context); |
264
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1694 return orig_start; |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1695 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1696 } |
264
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1697 z80_map_native_address(context, address, dst, after-inst, ZMAX_NATIVE_SIZE); |
266
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1698 opts->cur_code = dst+ZMAX_NATIVE_SIZE; |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1699 jmp(orig_start, dst); |
283
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1700 if (!z80_is_terminal(&instbuf)) { |
264
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1701 jmp(native_end, z80_get_native_address_trans(context, address + after-inst)); |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1702 } |
266
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1703 z80_handle_deferred(context); |
264
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1704 return dst; |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1705 } else { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1706 dst = translate_z80inst(&instbuf, orig_start, context, address); |
283
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1707 if (!z80_is_terminal(&instbuf)) { |
264
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1708 dst = jmp(dst, z80_get_native_address_trans(context, address + after-inst)); |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1709 } |
266
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1710 z80_handle_deferred(context); |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1711 return orig_start; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1712 } |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1713 } |
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1714 |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1715 void translate_z80_stream(z80_context * context, uint32_t address) |
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1716 { |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1717 char disbuf[80]; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1718 if (z80_get_native_address(context, address)) { |
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1719 return; |
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1720 } |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1721 x86_z80_options * opts = context->options; |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1722 uint8_t * encoded = NULL, *next; |
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1723 if (address < 0x4000) { |
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1724 encoded = context->mem_pointers[0] + (address & 0x1FFF); |
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1725 } else if(address >= 0x8000 && context->mem_pointers[1]) { |
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1726 encoded = context->mem_pointers[1] + (address & 0x7FFF); |
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1727 } |
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1728 while (encoded != NULL) |
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213
diff
changeset
|
1729 { |
d9bf8e61c33c
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parents:
213
diff
changeset
|
1730 z80inst inst; |
268
6c2d7e003a55
Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents:
267
diff
changeset
|
1731 dprintf("translating Z80 code at address %X\n", address); |
235
d9bf8e61c33c
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parents:
213
diff
changeset
|
1732 do { |
252
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Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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parents:
250
diff
changeset
|
1733 if (opts->code_end-opts->cur_code < ZMAX_NATIVE_SIZE) { |
235
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1734 if (opts->code_end-opts->cur_code < 5) { |
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Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1735 puts("out of code memory, not enough space for jmp to next chunk"); |
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parents:
213
diff
changeset
|
1736 exit(1); |
d9bf8e61c33c
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213
diff
changeset
|
1737 } |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1738 size_t size = 1024*1024; |
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213
diff
changeset
|
1739 opts->cur_code = alloc_code(&size); |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1740 opts->code_end = opts->cur_code + size; |
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213
diff
changeset
|
1741 jmp(opts->cur_code, opts->cur_code); |
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213
diff
changeset
|
1742 } |
255
572b935dd030
Properly handle wrapping around to 0 in translate_z80_stream
Mike Pavone <pavone@retrodev.com>
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1743 if (address > 0x4000 && address < 0x8000) { |
235
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1744 opts->cur_code = xor_rr(opts->cur_code, RDI, RDI, SZ_D); |
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1745 opts->cur_code = call(opts->cur_code, (uint8_t *)exit); |
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1746 break; |
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1747 } |
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1748 uint8_t * existing = z80_get_native_address(context, address); |
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1749 if (existing) { |
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1750 opts->cur_code = jmp(opts->cur_code, existing); |
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1751 break; |
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1752 } |
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1753 next = z80_decode(encoded, &inst); |
268
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Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
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1754 #ifdef DO_DEBUG_PRINT |
235
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1755 z80_disasm(&inst, disbuf); |
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1756 if (inst.op == Z80_NOP) { |
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1757 printf("%X\t%s(%d)\n", address, disbuf, inst.immed); |
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1758 } else { |
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1759 printf("%X\t%s\n", address, disbuf); |
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|
1760 } |
268
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1761 #endif |
248
9c7a3db7bcd0
Implement ADC and SBC in Z80 core (untested)
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1762 uint8_t *after = translate_z80inst(&inst, opts->cur_code, context, address); |
252
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Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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1763 z80_map_native_address(context, address, opts->cur_code, next-encoded, after - opts->cur_code); |
248
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1764 opts->cur_code = after; |
235
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1765 address += next-encoded; |
255
572b935dd030
Properly handle wrapping around to 0 in translate_z80_stream
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1766 if (address > 0xFFFF) { |
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Properly handle wrapping around to 0 in translate_z80_stream
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1767 address &= 0xFFFF; |
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1768 |
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|
1769 } else { |
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1770 encoded = next; |
572b935dd030
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|
1771 } |
283
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
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282
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|
1772 } while (!z80_is_terminal(&inst)); |
235
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1773 process_deferred(&opts->deferred, context, (native_addr_func)z80_get_native_address); |
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1774 if (opts->deferred) { |
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1775 address = opts->deferred->address; |
268
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Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
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1776 dprintf("defferred address: %X\n", address); |
235
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1777 if (address < 0x4000) { |
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1778 encoded = context->mem_pointers[0] + (address & 0x1FFF); |
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1779 } else if (address > 0x8000 && context->mem_pointers[1]) { |
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1780 encoded = context->mem_pointers[1] + (address & 0x7FFF); |
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|
1781 } else { |
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|
1782 printf("attempt to translate non-memory address: %X\n", address); |
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diff
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|
1783 exit(1); |
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diff
changeset
|
1784 } |
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diff
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|
1785 } else { |
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diff
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|
1786 encoded = NULL; |
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diff
changeset
|
1787 } |
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diff
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|
1788 } |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
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diff
changeset
|
1789 } |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
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|
1790 |
235
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|
1791 void init_x86_z80_opts(x86_z80_options * options) |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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|
1792 { |
235
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1793 options->flags = 0; |
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1794 options->regs[Z80_B] = BH; |
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1795 options->regs[Z80_C] = RBX; |
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1796 options->regs[Z80_D] = CH; |
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1797 options->regs[Z80_E] = RCX; |
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1798 options->regs[Z80_H] = AH; |
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|
1799 options->regs[Z80_L] = RAX; |
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1800 options->regs[Z80_IXH] = DH; |
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|
1801 options->regs[Z80_IXL] = RDX; |
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diff
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|
1802 options->regs[Z80_IYH] = -1; |
239
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
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diff
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|
1803 options->regs[Z80_IYL] = R8; |
235
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1804 options->regs[Z80_I] = -1; |
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|
1805 options->regs[Z80_R] = -1; |
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1806 options->regs[Z80_A] = R10; |
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|
1807 options->regs[Z80_BC] = RBX; |
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1808 options->regs[Z80_DE] = RCX; |
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1809 options->regs[Z80_HL] = RAX; |
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|
1810 options->regs[Z80_SP] = R9; |
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|
1811 options->regs[Z80_AF] = -1; |
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1812 options->regs[Z80_IX] = RDX; |
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|
1813 options->regs[Z80_IY] = R8; |
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|
1814 size_t size = 1024 * 1024; |
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1815 options->cur_code = alloc_code(&size); |
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1816 options->code_end = options->cur_code + size; |
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1817 options->ram_inst_sizes = malloc(sizeof(uint8_t) * 0x2000); |
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1818 memset(options->ram_inst_sizes, 0, sizeof(uint8_t) * 0x2000); |
235
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1819 options->deferred = NULL; |
213
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|
1820 } |
235
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|
1821 |
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1822 void init_z80_context(z80_context * context, x86_z80_options * options) |
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1823 { |
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1824 memset(context, 0, sizeof(*context)); |
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1825 context->static_code_map = malloc(sizeof(context->static_code_map)); |
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1826 context->static_code_map->base = NULL; |
235
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1827 context->static_code_map->offsets = malloc(sizeof(int32_t) * 0x2000); |
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1828 memset(context->static_code_map->offsets, 0xFF, sizeof(int32_t) * 0x2000); |
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1829 context->banked_code_map = malloc(sizeof(native_map_slot) * (1 << 9)); |
259
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1830 memset(context->banked_code_map, 0, sizeof(native_map_slot) * (1 << 9)); |
235
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1831 context->options = options; |
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1832 } |
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|
1833 |
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1834 void z80_reset(z80_context * context) |
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1835 { |
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1836 context->im = 0; |
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1837 context->iff1 = context->iff2 = 0; |
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1838 context->native_pc = z80_get_native_address_trans(context, 0); |
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|
1839 context->extra_pc = NULL; |
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1840 } |
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|
1841 |
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1842 |