Mercurial > repos > blastem
annotate gentests.py @ 234:f456ee23d372
Add shadow/higlight info to debug renderer
author | Mike Pavone <pavone@retrodev.com> |
---|---|
date | Mon, 22 Apr 2013 23:56:13 -0700 |
parents | 42123feab62d |
children | 8db584faac4b |
rev | line source |
---|---|
214
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1 #!/usr/bin/env python |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2 |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3 def split_fields(line): |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
4 parts = [] |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
5 while line: |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
6 field,_,line = line.partition('\t') |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
7 parts.append(field.strip()) |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
8 while line.startswith('\t'): |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
9 line = line[1:] |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
10 return parts |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
11 |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
12 class Program(object): |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
13 def __init__(self, instruction): |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
14 self.avail_dregs = {0,1,2,3,4,5,6,7} |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
15 self.avail_aregs = {0,1,2,3,4,5,6,7} |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
16 instruction.consume_regs(self) |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
17 self.inst = instruction |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
18 |
224
f7ff02eeec2f
Added testcases for move and roxl/roxr. Made some small improvements to test tools.
Mike Pavone <pavone@retrodev.com>
parents:
220
diff
changeset
|
19 def dirname(self): |
f7ff02eeec2f
Added testcases for move and roxl/roxr. Made some small improvements to test tools.
Mike Pavone <pavone@retrodev.com>
parents:
220
diff
changeset
|
20 return self.inst.name + '_' + self.inst.size |
214
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
21 def name(self): |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
22 return str(self.inst).replace('.', '_').replace('#', '_').replace(',', '_').replace(' ', '_').replace('(', '[').replace(')', ']') |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
23 |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
24 def write_rom_test(self, outfile): |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
25 outfile.write('\tdc.l $0, start\n') |
227
42123feab62d
Added test cases for divs/divu and added divide by zero handler to test generator
Mike Pavone <pavone@retrodev.com>
parents:
224
diff
changeset
|
26 needdivzero = self.inst.name.startswith('div') |
214
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
27 for i in xrange(0x8, 0x100, 0x4): |
227
42123feab62d
Added test cases for divs/divu and added divide by zero handler to test generator
Mike Pavone <pavone@retrodev.com>
parents:
224
diff
changeset
|
28 if needdivzero and i == 0x14: |
42123feab62d
Added test cases for divs/divu and added divide by zero handler to test generator
Mike Pavone <pavone@retrodev.com>
parents:
224
diff
changeset
|
29 outfile.write('\tdc.l div_zero_handler\n') |
42123feab62d
Added test cases for divs/divu and added divide by zero handler to test generator
Mike Pavone <pavone@retrodev.com>
parents:
224
diff
changeset
|
30 else: |
42123feab62d
Added test cases for divs/divu and added divide by zero handler to test generator
Mike Pavone <pavone@retrodev.com>
parents:
224
diff
changeset
|
31 outfile.write('\tdc.l empty_handler\n') |
42123feab62d
Added test cases for divs/divu and added divide by zero handler to test generator
Mike Pavone <pavone@retrodev.com>
parents:
224
diff
changeset
|
32 outfile.write('\tdc.b "SEGA"\nempty_handler:\n\trte\n') |
42123feab62d
Added test cases for divs/divu and added divide by zero handler to test generator
Mike Pavone <pavone@retrodev.com>
parents:
224
diff
changeset
|
33 if needdivzero: |
42123feab62d
Added test cases for divs/divu and added divide by zero handler to test generator
Mike Pavone <pavone@retrodev.com>
parents:
224
diff
changeset
|
34 outfile.write('div_zero_handler:\n') |
42123feab62d
Added test cases for divs/divu and added divide by zero handler to test generator
Mike Pavone <pavone@retrodev.com>
parents:
224
diff
changeset
|
35 div_zero_count = self.get_dreg() |
42123feab62d
Added test cases for divs/divu and added divide by zero handler to test generator
Mike Pavone <pavone@retrodev.com>
parents:
224
diff
changeset
|
36 outfile.write('\taddq #1, ' + str(div_zero_count) + '\n') |
42123feab62d
Added test cases for divs/divu and added divide by zero handler to test generator
Mike Pavone <pavone@retrodev.com>
parents:
224
diff
changeset
|
37 outfile.write('\trte\n') |
42123feab62d
Added test cases for divs/divu and added divide by zero handler to test generator
Mike Pavone <pavone@retrodev.com>
parents:
224
diff
changeset
|
38 outfile.write('start:\n\tmove #0, CCR\n') |
42123feab62d
Added test cases for divs/divu and added divide by zero handler to test generator
Mike Pavone <pavone@retrodev.com>
parents:
224
diff
changeset
|
39 if needdivzero: |
42123feab62d
Added test cases for divs/divu and added divide by zero handler to test generator
Mike Pavone <pavone@retrodev.com>
parents:
224
diff
changeset
|
40 outfile.write('\tmoveq #0, ' + str(div_zero_count) + '\n') |
214
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
41 already = {} |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
42 self.inst.write_init(outfile, already) |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
43 if 'label' in already: |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
44 outfile.write('lbl_' + str(already['label']) + ':\n') |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
45 outfile.write('\t'+str(self.inst)+'\n') |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
46 outfile.write('\t'+self.inst.save_result(self.get_dreg(), True) + '\n') |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
47 save_ccr = self.get_dreg() |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
48 outfile.write('\tmove SR, ' + str(save_ccr) + '\n') |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
49 outfile.write('\tmove #$1F, CCR\n') |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
50 self.inst.invalidate_dest(already) |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
51 self.inst.write_init(outfile, already) |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
52 if 'label' in already: |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
53 outfile.write('lbl_' + str(already['label']) + ':\n') |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
54 outfile.write('\t'+str(self.inst)+'\n') |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
55 outfile.write('\t'+self.inst.save_result(self.get_dreg(), False) + '\n') |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
56 outfile.write('\treset\n') |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
57 |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
58 def consume_dreg(self, num): |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
59 self.avail_dregs.discard(num) |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
60 |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
61 def consume_areg(self, num): |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
62 self.avail_aregs.discard(num) |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
63 |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
64 def get_dreg(self): |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
65 return Register('d', self.avail_dregs.pop()) |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
66 |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
67 class Register(object): |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
68 def __init__(self, kind, num): |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
69 self.kind = kind |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
70 self.num = num |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
71 |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
72 def __str__(self): |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
73 if self.kind == 'd' or self.kind == 'a': |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
74 return self.kind + str(self.num) |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
75 return self.kind |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
76 |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
77 def write_init(self, outfile, size, already): |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
78 if not str(self) in already: |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
79 minv,maxv = get_size_range(size) |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
80 val = randint(minv,maxv) |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
81 already[str(self)] = val |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
82 outfile.write('\tmove.'+size+' #'+str(val)+', ' + str(self) + '\n') |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
83 |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
84 def consume_regs(self, program): |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
85 if self.kind == 'd': |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
86 program.consume_dreg(self.num) |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
87 elif self.kind == 'a': |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
88 program.consume_areg(self.num) |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
89 |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
90 def valid_ram_address(address, size='b'): |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
91 return address >= 0xE00000 and address <= 0xFFFFFFFC and (address & 0xE00000) == 0xE00000 and (size == 'b' or not address & 1) |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
92 |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
93 def random_ram_address(mina=0xE00000, maxa=0xFFFFFFFC): |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
94 return randint(mina, maxa) | 0xE00000 |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
95 |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
96 class Indexed(object): |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
97 def __init__(self, base, index, index_size, disp): |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
98 self.base = base |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
99 self.index = index |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
100 self.index_size = index_size |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
101 self.disp = disp |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
102 |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
103 def write_init(self, outfile, size, already): |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
104 if self.base.kind == 'pc': |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
105 if str(self.index) in already: |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
106 index = already[str(self.index)] |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
107 if self.index_size == 'w': |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
108 index = index & 0xFFFF |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
109 #sign extend index |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
110 if index & 0x8000: |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
111 index -= 65536 |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
112 if index > -1024: |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
113 index = already[str(self.index)] = randint(-32768, -1024) |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
114 outfile.write('\tmove.l #' + str(index) + ', ' + str(self.index) + '\n') |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
115 else: |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
116 index = already[str(self.index)] = randint(-32768, -1024) |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
117 outfile.write('\tmove.l #' + str(index) + ', ' + str(self.index) + '\n') |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
118 num = already.get('label', 0)+1 |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
119 already['label'] = num |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
120 address = 'lbl_' + str(num) + ' + 2 + ' + str(self.disp) + ' + ' + str(index) |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
121 else: |
217
acd29e2664c6
Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents:
214
diff
changeset
|
122 if self.base == self.index: |
acd29e2664c6
Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents:
214
diff
changeset
|
123 if str(self.base) in already: |
acd29e2664c6
Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents:
214
diff
changeset
|
124 if not valid_ram_address(already[str(self.base)]*2): |
acd29e2664c6
Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents:
214
diff
changeset
|
125 del already[str(self.base)] |
acd29e2664c6
Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents:
214
diff
changeset
|
126 self.write_init(outfile, size, already) |
acd29e2664c6
Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents:
214
diff
changeset
|
127 return |
acd29e2664c6
Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents:
214
diff
changeset
|
128 else: |
acd29e2664c6
Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents:
214
diff
changeset
|
129 base = index = already[str(self.base)] |
214
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
130 else: |
217
acd29e2664c6
Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents:
214
diff
changeset
|
131 base = index = already[str(self.base)] = random_ram_address()/2 |
acd29e2664c6
Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents:
214
diff
changeset
|
132 outfile.write('\tmove.l #' + str(base) + ', ' + str(self.base) + '\n') |
214
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
133 else: |
217
acd29e2664c6
Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents:
214
diff
changeset
|
134 if str(self.base) in already: |
acd29e2664c6
Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents:
214
diff
changeset
|
135 if not valid_ram_address(already[str(self.base)]): |
acd29e2664c6
Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents:
214
diff
changeset
|
136 del already[str(self.base)] |
acd29e2664c6
Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents:
214
diff
changeset
|
137 self.write_init(outfile, size, already) |
acd29e2664c6
Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents:
214
diff
changeset
|
138 return |
acd29e2664c6
Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents:
214
diff
changeset
|
139 else: |
acd29e2664c6
Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents:
214
diff
changeset
|
140 base = already[str(self.base)] |
acd29e2664c6
Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents:
214
diff
changeset
|
141 else: |
acd29e2664c6
Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents:
214
diff
changeset
|
142 base = already[str(self.base)] = random_ram_address() |
acd29e2664c6
Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents:
214
diff
changeset
|
143 outfile.write('\tmove.l #' + str(base) + ', ' + str(self.base) + '\n') |
acd29e2664c6
Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents:
214
diff
changeset
|
144 if str(self.index) in already: |
acd29e2664c6
Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents:
214
diff
changeset
|
145 index = already[str(self.index)] |
acd29e2664c6
Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents:
214
diff
changeset
|
146 if self.index_size == 'w': |
acd29e2664c6
Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents:
214
diff
changeset
|
147 index = index & 0xFFFF |
acd29e2664c6
Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents:
214
diff
changeset
|
148 #sign extend index |
acd29e2664c6
Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents:
214
diff
changeset
|
149 if index & 0x8000: |
acd29e2664c6
Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents:
214
diff
changeset
|
150 index -= 65536 |
acd29e2664c6
Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents:
214
diff
changeset
|
151 if not valid_ram_address(base + index): |
acd29e2664c6
Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents:
214
diff
changeset
|
152 index = already[str(self.index)] = randint(-64, 63) |
acd29e2664c6
Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents:
214
diff
changeset
|
153 outfile.write('\tmove.l #' + str(index) + ', ' + str(self.index) + '\n') |
acd29e2664c6
Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents:
214
diff
changeset
|
154 else: |
214
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
155 index = already[str(self.index)] = randint(-64, 63) |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
156 outfile.write('\tmove.l #' + str(index) + ', ' + str(self.index) + '\n') |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
157 address = base + index + self.disp |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
158 if (address & 0xFFFFFF) < 0xE00000: |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
159 if (address & 0xFFFFFF) < 128: |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
160 self.disp -= (address & 0xFFFFFF) |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
161 else: |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
162 self.disp += 0xE00000-(address & 0xFFFFFF) |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
163 address = base + index + self.disp |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
164 elif (address & 0xFFFFFF) > 0xFFFFFC: |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
165 self.disp -= (address & 0xFFFFFF) - 0xFFFFFC |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
166 address = base + index + self.disp |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
167 if size != 'b' and address & 1: |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
168 self.disp = self.disp ^ 1 |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
169 address = base + index + self.disp |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
170 minv,maxv = get_size_range(size) |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
171 outfile.write('\tmove.' + size + ' #' + str(randint(minv, maxv)) + ', (' + str(address) + ').l\n') |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
172 |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
173 def __str__(self): |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
174 return '(' + str(self.disp) + ', ' + str(self.base) + ', ' + str(self.index) + '.' + self.index_size + ')' |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
175 |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
176 def consume_regs(self, program): |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
177 self.base.consume_regs(program) |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
178 self.index.consume_regs(program) |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
179 |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
180 class Displacement(object): |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
181 def __init__(self, base, disp): |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
182 self.base = base |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
183 self.disp = disp |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
184 |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
185 def write_init(self, outfile, size, already): |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
186 if self.base.kind == 'pc': |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
187 num = already.get('label', 0)+1 |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
188 already['label'] = num |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
189 address = 'lbl_' + str(num) + ' + 2 + ' + str(self.disp) |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
190 else: |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
191 if str(self.base) in already: |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
192 if not valid_ram_address(already[str(self.base)]): |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
193 del already[str(self.base)] |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
194 self.write_init(outfile, size, already) |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
195 return |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
196 else: |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
197 base = already[str(self.base)] |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
198 else: |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
199 base = already[str(self.base)] = random_ram_address() |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
200 outfile.write('\tmove.l #' + str(base) + ', ' + str(self.base) + '\n') |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
201 address = base + self.disp |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
202 if (address & 0xFFFFFF) < 0xE00000: |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
203 if (address & 0xFFFFFF) < 0x10000: |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
204 self.disp -= (address & 0xFFFFFF) |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
205 else: |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
206 self.disp += 0xE00000-(address & 0xFFFFFF) |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
207 address = base + self.disp |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
208 elif (address & 0xFFFFFF) > 0xFFFFFC: |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
209 self.disp -= (address & 0xFFFFFF) - 0xFFFFFC |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
210 address = base + self.disp |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
211 if size != 'b' and address & 1: |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
212 self.disp = self.disp ^ 1 |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
213 address = base + self.disp |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
214 minv,maxv = get_size_range(size) |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
215 outfile.write('\tmove.' + size + ' #' + str(randint(minv, maxv)) + ', (' + str(address) + ').l\n') |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
216 |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
217 def __str__(self): |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
218 return '(' + str(self.disp) + ', ' + str(self.base) + ')' |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
219 |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
220 def consume_regs(self, program): |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
221 self.base.consume_regs(program) |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
222 |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
223 class Indirect(object): |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
224 def __init__(self, reg): |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
225 self.reg = reg |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
226 |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
227 def __str__(self): |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
228 return '(' + str(self.reg) + ')' |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
229 |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
230 def write_init(self, outfile, size, already): |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
231 if str(self.reg) in already: |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
232 if not valid_ram_address(already[str(self.reg)], size): |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
233 del already[str(self.reg)] |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
234 self.write_init(outfile, size, already) |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
235 return |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
236 else: |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
237 address = already[str(self.reg)] |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
238 else: |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
239 address = random_ram_address() |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
240 if size != 'b': |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
241 address = address & 0xFFFFFFFE |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
242 outfile.write('\tmove.l #' + str(address) + ', ' + str(self.reg) + '\n') |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
243 already[str(self.reg)] = address |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
244 minv,maxv = get_size_range(size) |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
245 outfile.write('\tmove.' + size + ' #' + str(randint(minv, maxv)) + ', (' + str(address) + ').l\n') |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
246 |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
247 def consume_regs(self, program): |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
248 self.reg.consume_regs(program) |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
249 |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
250 class Increment(object): |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
251 def __init__(self, reg): |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
252 self.reg = reg |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
253 |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
254 def __str__(self): |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
255 return '(' + str(self.reg) + ')+' |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
256 |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
257 def write_init(self, outfile, size, already): |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
258 if str(self.reg) in already: |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
259 if not valid_ram_address(already[str(self.reg)], size): |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
260 del already[str(self.reg)] |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
261 self.write_init(outfile, size, already) |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
262 return |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
263 else: |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
264 address = already[str(self.reg)] |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
265 else: |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
266 address = random_ram_address() |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
267 if size != 'b': |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
268 address = address & 0xFFFFFFFE |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
269 outfile.write('\tmove.l #' + str(address) + ', ' + str(self.reg) + '\n') |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
270 already[str(self.reg)] = address |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
271 minv,maxv = get_size_range(size) |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
272 outfile.write('\tmove.' + size + ' #' + str(randint(minv, maxv)) + ', (' + str(address) + ').l\n') |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
273 |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
274 def consume_regs(self, program): |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
275 self.reg.consume_regs(program) |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
276 |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
277 class Decrement(object): |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
278 def __init__(self, reg): |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
279 self.reg = reg |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
280 |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
281 def __str__(self): |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
282 return '-(' + str(self.reg) + ')' |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
283 |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
284 def write_init(self, outfile, size, already): |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
285 if str(self.reg) in already: |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
286 if not valid_ram_address(already[str(self.reg)]- 4 if size == 'l' else 2 if size == 'w' else 1, size): |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
287 del already[str(self.reg)] |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
288 self.write_init(outfile, size, already) |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
289 return |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
290 else: |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
291 address = already[str(self.reg)] |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
292 else: |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
293 address = random_ram_address(mina=0xE00004) |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
294 if size != 'b': |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
295 address = address & 0xFFFFFFFE |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
296 outfile.write('\tmove.l #' + str(address) + ', ' + str(self.reg) + '\n') |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
297 already[str(self.reg)] = address |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
298 minv,maxv = get_size_range(size) |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
299 outfile.write('\tmove.' + size + ' #' + str(randint(minv, maxv)) + ', (' + str(address) + ').l\n') |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
300 |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
301 def consume_regs(self, program): |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
302 self.reg.consume_regs(program) |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
303 |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
304 class Absolute(object): |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
305 def __init__(self, address, size): |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
306 self.address = address |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
307 self.size = size |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
308 |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
309 def __str__(self): |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
310 return '(' + str(self.address) + ').' + self.size |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
311 |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
312 def write_init(self, outfile, size, already): |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
313 minv,maxv = get_size_range(size) |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
314 outfile.write('\tmove.' + size + ' #' + str(randint(minv, maxv)) + ', '+str(self)+'\n') |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
315 |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
316 def consume_regs(self, program): |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
317 pass |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
318 |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
319 class Immediate(object): |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
320 def __init__(self, value): |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
321 self.value = value |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
322 |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
323 def __str__(self): |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
324 return '#' + str(self.value) |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
325 |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
326 def write_init(self, outfile, size, already): |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
327 pass |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
328 |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
329 def consume_regs(self, program): |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
330 pass |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
331 |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
332 all_dregs = [Register('d', i) for i in range(0, 8)] |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
333 all_aregs = [Register('a', i) for i in range(0, 8)] |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
334 all_indirect = [Indirect(reg) for reg in all_aregs] |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
335 all_predec = [Decrement(reg) for reg in all_aregs] |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
336 all_postinc = [Increment(reg) for reg in all_aregs] |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
337 from random import randint |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
338 def all_indexed(): |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
339 return [Indexed(base, index, index_size, randint(-128, 127)) for base in all_aregs for index in all_dregs + all_aregs for index_size in ('w','l')] |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
340 |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
341 def all_disp(): |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
342 return [Displacement(base, randint(-32768, 32767)) for base in all_aregs] |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
343 |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
344 def rand_pc_disp(): |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
345 return [Displacement(Register('pc', 0), randint(-32768, -1024)) for x in xrange(0, 8)] |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
346 |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
347 def all_pc_indexed(): |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
348 return [Indexed(Register('pc', 0), index, index_size, randint(-128, 127)) for index in all_dregs + all_aregs for index_size in ('w','l')] |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
349 |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
350 def rand_abs_short(): |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
351 return [Absolute(0xFFFF8000 + randint(0, 32767), 'w') for x in xrange(0, 8)] |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
352 |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
353 def rand_abs_long(): |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
354 return [Absolute(0xFF0000 + randint(0, 65535), 'l') for x in xrange(0, 8)] |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
355 |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
356 def get_size_range(size): |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
357 if size == 'b': |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
358 return (-128, 127) |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
359 elif size == 'w': |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
360 return (-32768, 32767) |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
361 else: |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
362 return (-2147483648, 2147483647) |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
363 |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
364 def rand_immediate(size): |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
365 minv,maxv = get_size_range(size) |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
366 |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
367 return [Immediate(randint(minv, maxv)) for x in xrange(0,8)] |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
368 |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
369 def get_variations(mode, size): |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
370 mapping = { |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
371 'd':all_dregs, |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
372 'a':all_aregs, |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
373 '(a)':all_indirect, |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
374 '-(a)':all_predec, |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
375 '(a)+':all_postinc, |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
376 '(n,a)':all_disp, |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
377 '(n,a,x)':all_indexed, |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
378 '(n,pc)':rand_pc_disp, |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
379 '(n,pc,x)':all_pc_indexed, |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
380 '(n).w':rand_abs_short, |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
381 '(n).l':rand_abs_long |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
382 } |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
383 if mode in mapping: |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
384 ret = mapping[mode] |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
385 if type(ret) != list: |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
386 ret = ret() |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
387 return ret |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
388 elif mode == '#n': |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
389 return rand_immediate(size) |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
390 elif mode.startswith('#(') and mode.endswith(')'): |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
391 inner = mode[2:-1] |
224
f7ff02eeec2f
Added testcases for move and roxl/roxr. Made some small improvements to test tools.
Mike Pavone <pavone@retrodev.com>
parents:
220
diff
changeset
|
392 start,sep,end = inner.rpartition('-') |
220
cb72780e17b1
Add support for picking random numbers in a larger range in test generator. Add support for running a subset of tests in runner. Added testcases for bit and rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
217
diff
changeset
|
393 start,end = int(start),int(end) |
cb72780e17b1
Add support for picking random numbers in a larger range in test generator. Add support for running a subset of tests in runner. Added testcases for bit and rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
217
diff
changeset
|
394 if end-start > 16: |
cb72780e17b1
Add support for picking random numbers in a larger range in test generator. Add support for running a subset of tests in runner. Added testcases for bit and rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
217
diff
changeset
|
395 return [Immediate(randint(start, end)) for x in range(0,8)] |
cb72780e17b1
Add support for picking random numbers in a larger range in test generator. Add support for running a subset of tests in runner. Added testcases for bit and rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
217
diff
changeset
|
396 else: |
cb72780e17b1
Add support for picking random numbers in a larger range in test generator. Add support for running a subset of tests in runner. Added testcases for bit and rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
217
diff
changeset
|
397 return [Immediate(num) for num in range(start, end+1)] |
217
acd29e2664c6
Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents:
214
diff
changeset
|
398 else: |
acd29e2664c6
Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents:
214
diff
changeset
|
399 print "Don't know what to do with source type", mode |
acd29e2664c6
Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents:
214
diff
changeset
|
400 return None |
214
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
401 |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
402 class Inst2Op(object): |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
403 def __init__(self, name, size, src, dst): |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
404 self.name = name |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
405 self.size = size |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
406 self.src = src |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
407 self.dst = dst |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
408 |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
409 def __str__(self): |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
410 return self.name + '.' + self.size + ' ' + str(self.src) + ', ' + str(self.dst) |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
411 |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
412 def write_init(self, outfile, already): |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
413 self.src.write_init(outfile, self.size, already) |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
414 self.dst.write_init(outfile, self.size, already) |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
415 |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
416 def invalidate_dest(self, already): |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
417 if type(self.dst) == Register: |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
418 del already[str(self.dst)] |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
419 |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
420 def save_result(self, reg, always): |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
421 if always or type(self.dst) != Register: |
217
acd29e2664c6
Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents:
214
diff
changeset
|
422 if type(self.dst) == Decrement: |
acd29e2664c6
Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents:
214
diff
changeset
|
423 src = Increment(self.dst.reg) |
acd29e2664c6
Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents:
214
diff
changeset
|
424 elif type(self.dst) == Increment: |
acd29e2664c6
Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents:
214
diff
changeset
|
425 src = Decrement(self.dst.reg) |
acd29e2664c6
Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents:
214
diff
changeset
|
426 else: |
acd29e2664c6
Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents:
214
diff
changeset
|
427 src = self.dst |
acd29e2664c6
Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents:
214
diff
changeset
|
428 return 'move.' + self.size + ' ' + str(src) + ', ' + str(reg) |
214
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
429 else: |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
430 return '' |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
431 |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
432 def consume_regs(self, program): |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
433 self.src.consume_regs(program) |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
434 self.dst.consume_regs(program) |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
435 |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
436 class Entry(object): |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
437 def __init__(self, line): |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
438 fields = split_fields(line) |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
439 self.name = fields[0] |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
440 sizes = fields[1] |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
441 sources = fields[2].split(';') |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
442 dests = fields[3].split(';') |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
443 combos = [] |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
444 for size in sizes: |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
445 for source in sources: |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
446 if size != 'b' or source != 'a': |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
447 for dest in dests: |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
448 if size != 'b' or dest != 'a': |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
449 combos.append((size, source, dest)) |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
450 self.cases = combos |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
451 |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
452 def programs(self): |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
453 res = [] |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
454 for (size, src, dst) in self.cases: |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
455 sources = get_variations(src, size) |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
456 dests = get_variations(dst, size) |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
457 for source in sources: |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
458 for dest in dests: |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
459 res.append(Program(Inst2Op(self.name, size, source, dest))) |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
460 return res |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
461 |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
462 def process_entries(f): |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
463 entries = [] |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
464 for line in f: |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
465 if not line.startswith('Name') and not line.startswith('#') and len(line.strip()) > 0: |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
466 entries.append(Entry(line)) |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
467 return entries |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
468 |
224
f7ff02eeec2f
Added testcases for move and roxl/roxr. Made some small improvements to test tools.
Mike Pavone <pavone@retrodev.com>
parents:
220
diff
changeset
|
469 from os import path, mkdir |
214
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
470 def main(args): |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
471 entries = process_entries(open('testcases.txt')) |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
472 for entry in entries: |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
473 programs = entry.programs() |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
474 for program in programs: |
224
f7ff02eeec2f
Added testcases for move and roxl/roxr. Made some small improvements to test tools.
Mike Pavone <pavone@retrodev.com>
parents:
220
diff
changeset
|
475 dname = program.dirname() |
f7ff02eeec2f
Added testcases for move and roxl/roxr. Made some small improvements to test tools.
Mike Pavone <pavone@retrodev.com>
parents:
220
diff
changeset
|
476 if not path.exists('generated_tests/' + dname): |
f7ff02eeec2f
Added testcases for move and roxl/roxr. Made some small improvements to test tools.
Mike Pavone <pavone@retrodev.com>
parents:
220
diff
changeset
|
477 mkdir('generated_tests/' + dname) |
f7ff02eeec2f
Added testcases for move and roxl/roxr. Made some small improvements to test tools.
Mike Pavone <pavone@retrodev.com>
parents:
220
diff
changeset
|
478 f = open('generated_tests/' + dname + '/' + program.name() + '.s68', 'w') |
214
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
479 program.write_rom_test(f) |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
480 f.close() |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
481 |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
482 if __name__ == '__main__': |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
483 import sys |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
484 main(sys.argv) |
9126c33cc33c
Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
485 |