Mercurial > repos > blastem
annotate z80_to_x86.c @ 261:f0c53a4bbfa3
Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write
author | Mike Pavone <pavone@retrodev.com> |
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date | Tue, 30 Apr 2013 01:00:10 -0700 |
parents | d9417261366f |
children | d97c9eca49f4 |
rev | line source |
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1 #include "z80inst.h" |
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2 #include "z80_to_x86.h" |
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3 #include "gen_x86.h" |
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4 #include "mem.h" |
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5 #include <stdio.h> |
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6 #include <stdlib.h> |
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7 #include <stddef.h> |
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8 #include <string.h> |
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9 |
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10 #define MODE_UNUSED (MODE_IMMED-1) |
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11 |
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12 #define ZCYCLES RBP |
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13 #define ZLIMIT RDI |
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14 #define SCRATCH1 R13 |
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15 #define SCRATCH2 R14 |
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16 #define CONTEXT RSI |
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17 |
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18 void z80_read_byte(); |
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19 void z80_read_word(); |
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20 void z80_write_byte(); |
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21 void z80_write_word_highfirst(); |
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22 void z80_write_word_lowfirst(); |
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23 void z80_save_context(); |
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24 void z80_native_addr(); |
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25 void z80_do_sync(); |
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26 void z80_handle_cycle_limit_int(); |
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27 void z80_retrans_stub(); |
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28 |
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29 uint8_t z80_size(z80inst * inst) |
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30 { |
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31 uint8_t reg = (inst->reg & 0x1F); |
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32 if (reg != Z80_UNUSED && reg != Z80_USE_IMMED) { |
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33 return reg < Z80_BC ? SZ_B : SZ_W; |
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34 } |
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35 //TODO: Handle any necessary special cases |
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36 return SZ_B; |
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37 } |
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38 |
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39 uint8_t z80_high_reg(uint8_t reg) |
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40 { |
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41 switch(reg) |
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42 { |
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43 case Z80_C: |
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44 case Z80_BC: |
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45 return Z80_B; |
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46 case Z80_E: |
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47 case Z80_DE: |
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48 return Z80_D; |
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49 case Z80_L: |
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50 case Z80_HL: |
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51 return Z80_H; |
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52 case Z80_IXL: |
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53 case Z80_IX: |
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54 return Z80_IXH; |
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55 case Z80_IYL: |
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56 case Z80_IY: |
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57 return Z80_IYH; |
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58 default: |
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59 return Z80_UNUSED; |
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60 } |
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61 } |
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62 |
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63 uint8_t * zcycles(uint8_t * dst, uint32_t num_cycles) |
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64 { |
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65 return add_ir(dst, num_cycles, ZCYCLES, SZ_D); |
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66 } |
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67 |
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68 uint8_t * z80_check_cycles_int(uint8_t * dst, uint16_t address) |
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69 { |
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70 dst = cmp_rr(dst, ZCYCLES, ZLIMIT, SZ_D); |
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71 uint8_t * jmp_off = dst+1; |
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72 dst = jcc(dst, CC_NC, dst + 7); |
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73 dst = mov_ir(dst, address, SCRATCH1, SZ_W); |
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74 dst = call(dst, (uint8_t *)z80_handle_cycle_limit_int); |
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75 *jmp_off = dst - (jmp_off+1); |
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76 return dst; |
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77 } |
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78 |
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79 uint8_t * translate_z80_reg(z80inst * inst, x86_ea * ea, uint8_t * dst, x86_z80_options * opts) |
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80 { |
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81 if (inst->reg == Z80_USE_IMMED) { |
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82 ea->mode = MODE_IMMED; |
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83 ea->disp = inst->immed; |
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84 } else if ((inst->reg & 0x1F) == Z80_UNUSED) { |
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85 ea->mode = MODE_UNUSED; |
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86 } else { |
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87 ea->mode = MODE_REG_DIRECT; |
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88 if (inst->reg == Z80_IYH) { |
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89 ea->base = opts->regs[Z80_IYL]; |
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90 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W); |
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91 } else { |
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92 ea->base = opts->regs[inst->reg]; |
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93 } |
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94 } |
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95 return dst; |
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96 } |
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97 |
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98 uint8_t * z80_save_reg(uint8_t * dst, z80inst * inst, x86_z80_options * opts) |
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99 { |
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100 if (inst->reg == Z80_IYH) { |
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101 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W); |
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102 } |
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103 return dst; |
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104 } |
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105 |
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106 uint8_t * translate_z80_ea(z80inst * inst, x86_ea * ea, uint8_t * dst, x86_z80_options * opts, uint8_t read, uint8_t modify) |
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107 { |
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108 uint8_t size, reg, areg; |
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109 ea->mode = MODE_REG_DIRECT; |
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110 areg = read ? SCRATCH1 : SCRATCH2; |
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111 switch(inst->addr_mode & 0x1F) |
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112 { |
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113 case Z80_REG: |
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114 if (inst->ea_reg == Z80_IYH) { |
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115 ea->base = opts->regs[Z80_IYL]; |
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116 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W); |
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117 } else { |
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118 ea->base = opts->regs[inst->ea_reg]; |
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119 } |
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120 break; |
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121 case Z80_REG_INDIRECT: |
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122 dst = mov_rr(dst, opts->regs[inst->ea_reg], areg, SZ_W); |
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123 size = z80_size(inst); |
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124 if (read) { |
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125 if (modify) { |
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126 dst = push_r(dst, SCRATCH1); |
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127 } |
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128 if (size == SZ_B) { |
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129 dst = call(dst, (uint8_t *)z80_read_byte); |
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130 } else { |
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131 dst = call(dst, (uint8_t *)z80_read_word); |
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132 } |
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133 if (modify) { |
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134 dst = pop_r(dst, SCRATCH2); |
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135 } |
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136 } |
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137 ea->base = SCRATCH1; |
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138 break; |
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139 case Z80_IMMED: |
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140 ea->mode = MODE_IMMED; |
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141 ea->disp = inst->immed; |
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142 break; |
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143 case Z80_IMMED_INDIRECT: |
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144 dst = mov_ir(dst, inst->immed, areg, SZ_W); |
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145 size = z80_size(inst); |
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146 if (read) { |
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147 if (modify) { |
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148 dst = push_r(dst, SCRATCH1); |
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149 } |
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150 if (size == SZ_B) { |
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151 dst = call(dst, (uint8_t *)z80_read_byte); |
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152 } else { |
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153 dst = call(dst, (uint8_t *)z80_read_word); |
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154 } |
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155 if (modify) { |
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156 dst = pop_r(dst, SCRATCH2); |
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157 } |
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158 } |
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159 ea->base = SCRATCH1; |
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160 break; |
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161 case Z80_IX_DISPLACE: |
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162 case Z80_IY_DISPLACE: |
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163 reg = opts->regs[inst->addr_mode == Z80_IX_DISPLACE ? Z80_IX : Z80_IY]; |
213
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164 dst = mov_rr(dst, reg, areg, SZ_W); |
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165 dst = add_ir(dst, inst->immed, areg, SZ_W); |
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166 size = z80_size(inst); |
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167 if (read) { |
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168 if (modify) { |
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169 dst = push_r(dst, SCRATCH1); |
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170 } |
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171 if (size == SZ_B) { |
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172 dst = call(dst, (uint8_t *)z80_read_byte); |
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173 } else { |
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174 dst = call(dst, (uint8_t *)z80_read_word); |
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175 } |
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176 if (modify) { |
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177 dst = pop_r(dst, SCRATCH2); |
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178 } |
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179 } |
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180 break; |
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181 case Z80_UNUSED: |
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182 ea->mode = MODE_UNUSED; |
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183 break; |
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184 default: |
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185 fprintf(stderr, "Unrecognized Z80 addressing mode %d\n", inst->addr_mode); |
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186 exit(1); |
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187 } |
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188 return dst; |
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189 } |
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190 |
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191 uint8_t * z80_save_ea(uint8_t * dst, z80inst * inst, x86_z80_options * opts) |
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192 { |
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193 if (inst->addr_mode == Z80_REG && inst->ea_reg == Z80_IYH) { |
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194 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W); |
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195 } |
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196 return dst; |
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197 } |
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198 |
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199 uint8_t * z80_save_result(uint8_t * dst, z80inst * inst) |
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200 { |
253
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201 switch(inst->addr_mode & 0x1f) |
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202 { |
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203 case Z80_REG_INDIRECT: |
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204 case Z80_IMMED_INDIRECT: |
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205 case Z80_IX_DISPLACE: |
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206 case Z80_IY_DISPLACE: |
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207 if (z80_size(inst) == SZ_B) { |
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208 dst = call(dst, (uint8_t *)z80_write_byte); |
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209 } else { |
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210 dst = call(dst, (uint8_t *)z80_write_word_lowfirst); |
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211 } |
213
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212 } |
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213 return dst; |
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214 } |
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215 |
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216 enum { |
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217 DONT_READ=0, |
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218 READ |
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219 }; |
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220 |
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221 enum { |
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222 DONT_MODIFY=0, |
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223 MODIFY |
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224 }; |
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225 |
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226 uint8_t zf_off(uint8_t flag) |
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227 { |
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228 return offsetof(z80_context, flags) + flag; |
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229 } |
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230 |
241
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231 uint8_t zaf_off(uint8_t flag) |
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232 { |
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233 return offsetof(z80_context, alt_flags) + flag; |
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234 } |
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235 |
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236 uint8_t zar_off(uint8_t reg) |
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237 { |
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238 return offsetof(z80_context, alt_regs) + reg; |
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239 } |
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240 |
235
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241 void z80_print_regs_exit(z80_context * context) |
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242 { |
243
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243 printf("A: %X\nB: %X\nC: %X\nD: %X\nE: %X\nHL: %X\nIX: %X\nIY: %X\nSP: %X\n\nIM: %d, IFF1: %d, IFF2: %d\n", |
235
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244 context->regs[Z80_A], context->regs[Z80_B], context->regs[Z80_C], |
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245 context->regs[Z80_D], context->regs[Z80_E], |
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246 (context->regs[Z80_H] << 8) | context->regs[Z80_L], |
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247 (context->regs[Z80_IXH] << 8) | context->regs[Z80_IXL], |
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248 (context->regs[Z80_IYH] << 8) | context->regs[Z80_IYL], |
243
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249 context->sp, context->im, context->iff1, context->iff2); |
241
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250 puts("--Alternate Regs--"); |
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251 printf("A: %X\nB: %X\nC: %X\nD: %X\nE: %X\nHL: %X\nIX: %X\nIY: %X\n", |
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252 context->alt_regs[Z80_A], context->alt_regs[Z80_B], context->alt_regs[Z80_C], |
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253 context->alt_regs[Z80_D], context->alt_regs[Z80_E], |
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254 (context->alt_regs[Z80_H] << 8) | context->alt_regs[Z80_L], |
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255 (context->alt_regs[Z80_IXH] << 8) | context->alt_regs[Z80_IXL], |
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256 (context->alt_regs[Z80_IYH] << 8) | context->alt_regs[Z80_IYL]); |
235
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257 exit(0); |
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258 } |
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259 |
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260 uint8_t * translate_z80inst(z80inst * inst, uint8_t * dst, z80_context * context, uint16_t address) |
213
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261 { |
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262 uint32_t cycles; |
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263 x86_ea src_op, dst_op; |
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264 uint8_t size; |
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265 x86_z80_options *opts = context->options; |
261
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266 uint8_t * start = dst; |
250
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267 dst = z80_check_cycles_int(dst, address); |
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268 switch(inst->op) |
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269 { |
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270 case Z80_LD: |
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271 size = z80_size(inst); |
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272 switch (inst->addr_mode & 0x1F) |
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273 { |
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274 case Z80_REG: |
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275 case Z80_REG_INDIRECT: |
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276 cycles = size == SZ_B ? 4 : 6; |
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277 if (inst->ea_reg == Z80_IX || inst->ea_reg == Z80_IY) { |
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278 cycles += 4; |
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279 } |
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280 break; |
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281 case Z80_IMMED: |
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282 cycles = size == SZ_B ? 7 : 10; |
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283 break; |
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284 case Z80_IMMED_INDIRECT: |
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285 cycles = 10; |
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286 break; |
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287 case Z80_IX_DISPLACE: |
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288 case Z80_IY_DISPLACE: |
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289 cycles = 12; |
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290 break; |
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291 } |
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292 if ((inst->reg >= Z80_IXL && inst->reg <= Z80_IYH) || inst->reg == Z80_IX || inst->reg == Z80_IY) { |
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293 cycles += 4; |
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294 } |
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295 dst = zcycles(dst, cycles); |
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296 if (inst->addr_mode & Z80_DIR) { |
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297 dst = translate_z80_reg(inst, &src_op, dst, opts); |
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298 dst = translate_z80_ea(inst, &dst_op, dst, opts, DONT_READ, MODIFY); |
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299 } else { |
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300 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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301 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
213
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302 } |
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303 if (src_op.mode == MODE_REG_DIRECT) { |
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304 dst = mov_rr(dst, src_op.base, dst_op.base, size); |
213
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305 } else { |
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306 dst = mov_ir(dst, src_op.disp, dst_op.base, size); |
213
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307 } |
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308 dst = z80_save_reg(dst, inst, opts); |
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309 dst = z80_save_ea(dst, inst, opts); |
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310 if (inst->addr_mode & Z80_DIR) { |
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311 dst = z80_save_result(dst, inst); |
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312 } |
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313 break; |
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314 case Z80_PUSH: |
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315 dst = zcycles(dst, (inst->reg == Z80_IX || inst->reg == Z80_IY) ? 9 : 5); |
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316 dst = sub_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
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317 if (inst->reg == Z80_AF) { |
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318 dst = mov_rdisp8r(dst, CONTEXT, zf_off(ZF_S), SCRATCH1, SZ_B); |
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319 dst = shl_ir(dst, 1, SCRATCH1, SZ_B); |
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320 dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_Z), SCRATCH1, SZ_B); |
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321 dst = shl_ir(dst, 2, SCRATCH1, SZ_B); |
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322 dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_H), SCRATCH1, SZ_B); |
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323 dst = shl_ir(dst, 2, SCRATCH1, SZ_B); |
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324 dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_PV), SCRATCH1, SZ_B); |
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325 dst = shl_ir(dst, 1, SCRATCH1, SZ_B); |
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326 dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_N), SCRATCH1, SZ_B); |
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327 dst = shl_ir(dst, 1, SCRATCH1, SZ_B); |
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328 dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_C), SCRATCH1, SZ_B); |
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329 dst = shl_ir(dst, 8, SCRATCH1, SZ_W); |
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330 dst = mov_rr(dst, opts->regs[Z80_A], SCRATCH1, SZ_B); |
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331 } else { |
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332 dst = translate_z80_reg(inst, &src_op, dst, opts); |
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333 dst = mov_rr(dst, src_op.base, SCRATCH1, SZ_W); |
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334 } |
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335 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W); |
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336 dst = call(dst, (uint8_t *)z80_write_word_highfirst); |
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337 //no call to save_z80_reg needed since there's no chance we'll use the only |
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338 //the upper half of a register pair |
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339 break; |
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340 case Z80_POP: |
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341 dst = zcycles(dst, (inst->reg == Z80_IX || inst->reg == Z80_IY) ? 8 : 4); |
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342 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
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343 dst = call(dst, (uint8_t *)z80_read_word); |
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344 dst = add_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
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345 if (inst->reg == Z80_AF) { |
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346 dst = mov_rr(dst, SCRATCH1, opts->regs[Z80_A], SZ_B); |
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347 dst = bt_ir(dst, 8, SCRATCH1, SZ_W); |
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348 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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349 dst = bt_ir(dst, 9, SCRATCH1, SZ_W); |
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350 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_N)); |
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351 dst = bt_ir(dst, 10, SCRATCH1, SZ_W); |
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352 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_PV)); |
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353 dst = bt_ir(dst, 12, SCRATCH1, SZ_W); |
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354 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_H)); |
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355 dst = bt_ir(dst, 14, SCRATCH1, SZ_W); |
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356 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_Z)); |
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357 dst = bt_ir(dst, 15, SCRATCH1, SZ_W); |
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358 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_S)); |
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359 } else { |
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360 dst = translate_z80_reg(inst, &src_op, dst, opts); |
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361 dst = mov_rr(dst, SCRATCH1, src_op.base, SZ_W); |
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362 } |
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363 //no call to save_z80_reg needed since there's no chance we'll use the only |
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364 //the upper half of a register pair |
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365 break; |
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366 case Z80_EX: |
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367 if (inst->addr_mode == Z80_REG || inst->reg == Z80_HL) { |
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368 cycles = 4; |
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369 } else { |
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370 cycles = 8; |
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371 } |
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372 dst = zcycles(dst, cycles); |
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373 if (inst->addr_mode == Z80_REG) { |
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374 if(inst->reg == Z80_AF) { |
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375 dst = mov_rr(dst, opts->regs[Z80_A], SCRATCH1, SZ_B); |
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376 dst = mov_rdisp8r(dst, CONTEXT, zar_off(Z80_A), opts->regs[Z80_A], SZ_B); |
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377 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, zar_off(Z80_A), SZ_B); |
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378 |
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379 //Flags are currently word aligned, so we can move |
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380 //them efficiently a word at a time |
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381 for (int f = ZF_C; f < ZF_NUM; f+=2) { |
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382 dst = mov_rdisp8r(dst, CONTEXT, zf_off(f), SCRATCH1, SZ_W); |
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383 dst = mov_rdisp8r(dst, CONTEXT, zaf_off(f), SCRATCH2, SZ_W); |
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384 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, zaf_off(f), SZ_W); |
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385 dst = mov_rrdisp8(dst, SCRATCH2, CONTEXT, zf_off(f), SZ_W); |
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386 } |
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387 } else { |
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388 dst = xchg_rr(dst, opts->regs[Z80_DE], opts->regs[Z80_HL], SZ_W); |
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389 } |
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390 } else { |
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391 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
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392 dst = call(dst, (uint8_t *)z80_read_byte); |
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393 dst = xchg_rr(dst, opts->regs[inst->reg], SCRATCH1, SZ_B); |
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394 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W); |
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395 dst = call(dst, (uint8_t *)z80_write_byte); |
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396 dst = zcycles(dst, 1); |
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397 uint8_t high_reg = z80_high_reg(inst->reg); |
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398 uint8_t use_reg; |
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399 //even though some of the upper halves can be used directly |
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400 //the limitations on mixing *H regs with the REX prefix |
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401 //prevent us from taking advantage of it |
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402 use_reg = opts->regs[inst->reg]; |
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403 dst = ror_ir(dst, 8, use_reg, SZ_W); |
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404 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
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405 dst = add_ir(dst, 1, SCRATCH1, SZ_W); |
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406 dst = call(dst, (uint8_t *)z80_read_byte); |
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407 dst = xchg_rr(dst, use_reg, SCRATCH1, SZ_B); |
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408 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W); |
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409 dst = add_ir(dst, 1, SCRATCH2, SZ_W); |
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410 dst = call(dst, (uint8_t *)z80_write_byte); |
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411 //restore reg to normal rotation |
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412 dst = ror_ir(dst, 8, use_reg, SZ_W); |
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|
413 dst = zcycles(dst, 2); |
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414 } |
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415 break; |
213
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|
416 case Z80_EXX: |
241
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417 dst = zcycles(dst, 4); |
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|
418 dst = mov_rr(dst, opts->regs[Z80_BC], SCRATCH1, SZ_W); |
2586d49ddd46
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419 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH2, SZ_W); |
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changeset
|
420 dst = mov_rdisp8r(dst, CONTEXT, zar_off(Z80_C), opts->regs[Z80_BC], SZ_W); |
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421 dst = mov_rdisp8r(dst, CONTEXT, zar_off(Z80_L), opts->regs[Z80_HL], SZ_W); |
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422 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, zar_off(Z80_C), SZ_W); |
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423 dst = mov_rrdisp8(dst, SCRATCH2, CONTEXT, zar_off(Z80_L), SZ_W); |
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424 dst = mov_rr(dst, opts->regs[Z80_DE], SCRATCH1, SZ_W); |
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425 dst = mov_rdisp8r(dst, CONTEXT, zar_off(Z80_E), opts->regs[Z80_DE], SZ_W); |
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426 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, zar_off(Z80_E), SZ_W); |
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427 break; |
261
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428 //case Z80_LDI: |
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429 case Z80_LDIR: { |
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430 dst = zcycles(dst, 8); |
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431 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH1, SZ_W); |
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432 dst = call(dst, (uint8_t *)z80_read_byte); |
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433 dst = mov_rr(dst, opts->regs[Z80_DE], SCRATCH2, SZ_W); |
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434 dst = call(dst, (uint8_t *)z80_read_byte); |
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435 dst = add_ir(dst, 1, opts->regs[Z80_DE], SZ_W); |
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436 dst = add_ir(dst, 1, opts->regs[Z80_HL], SZ_W); |
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437 |
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438 dst = sub_ir(dst, 1, opts->regs[Z80_BC], SZ_W); |
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439 uint8_t * cont = dst+1; |
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440 dst = jcc(dst, CC_Z, dst+2); |
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441 dst = zcycles(dst, 7); |
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442 //TODO: Figure out what the flag state should be here |
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443 //TODO: Figure out whether an interrupt can interrupt this |
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444 dst = jmp(dst, start); |
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445 *cont = dst - (cont + 1); |
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446 dst = zcycles(dst, 2); |
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447 //TODO: Implement half-carry |
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448 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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449 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_PV), SZ_B); |
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450 break; |
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451 } |
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452 /*case Z80_LDD: |
213
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453 case Z80_LDDR: |
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454 case Z80_CPI: |
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455 case Z80_CPIR: |
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|
456 case Z80_CPD: |
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|
457 case Z80_CPDR: |
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changeset
|
458 break;*/ |
4d4559b04c59
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|
459 case Z80_ADD: |
4d4559b04c59
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changeset
|
460 cycles = 4; |
235
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461 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
213
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462 cycles += 12; |
4d4559b04c59
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|
463 } else if(inst->addr_mode == Z80_IMMED) { |
4d4559b04c59
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464 cycles += 3; |
4d4559b04c59
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465 } else if(z80_size(inst) == SZ_W) { |
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changeset
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466 cycles += 4; |
4d4559b04c59
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changeset
|
467 } |
4d4559b04c59
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changeset
|
468 dst = zcycles(dst, cycles); |
4d4559b04c59
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changeset
|
469 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
4d4559b04c59
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changeset
|
470 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
4d4559b04c59
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changeset
|
471 if (src_op.mode == MODE_REG_DIRECT) { |
4d4559b04c59
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changeset
|
472 dst = add_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
4d4559b04c59
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changeset
|
473 } else { |
4d4559b04c59
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changeset
|
474 dst = add_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
4d4559b04c59
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changeset
|
475 } |
4d4559b04c59
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changeset
|
476 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
235
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|
477 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
213
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changeset
|
478 //TODO: Implement half-carry flag |
4d4559b04c59
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|
479 if (z80_size(inst) == SZ_B) { |
235
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480 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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|
481 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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482 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
213
4d4559b04c59
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diff
changeset
|
483 } |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff
changeset
|
484 dst = z80_save_reg(dst, inst, opts); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff
changeset
|
485 dst = z80_save_ea(dst, inst, opts); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
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changeset
|
486 break; |
248
9c7a3db7bcd0
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|
487 case Z80_ADC: |
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|
488 cycles = 4; |
9c7a3db7bcd0
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|
489 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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|
490 cycles += 12; |
9c7a3db7bcd0
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|
491 } else if(inst->addr_mode == Z80_IMMED) { |
9c7a3db7bcd0
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|
492 cycles += 3; |
9c7a3db7bcd0
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493 } else if(z80_size(inst) == SZ_W) { |
9c7a3db7bcd0
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|
494 cycles += 4; |
9c7a3db7bcd0
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|
495 } |
9c7a3db7bcd0
Implement ADC and SBC in Z80 core (untested)
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changeset
|
496 dst = zcycles(dst, cycles); |
9c7a3db7bcd0
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changeset
|
497 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
9c7a3db7bcd0
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changeset
|
498 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
9c7a3db7bcd0
Implement ADC and SBC in Z80 core (untested)
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|
499 if (src_op.mode == MODE_REG_DIRECT) { |
9c7a3db7bcd0
Implement ADC and SBC in Z80 core (untested)
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|
500 dst = adc_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
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|
501 } else { |
9c7a3db7bcd0
Implement ADC and SBC in Z80 core (untested)
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|
502 dst = adc_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
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|
503 } |
9c7a3db7bcd0
Implement ADC and SBC in Z80 core (untested)
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changeset
|
504 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
9c7a3db7bcd0
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changeset
|
505 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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|
506 //TODO: Implement half-carry flag |
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507 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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508 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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509 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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510 dst = z80_save_reg(dst, inst, opts); |
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511 dst = z80_save_ea(dst, inst, opts); |
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512 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
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changeset
|
513 case Z80_SUB: |
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changeset
|
514 cycles = 4; |
235
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515 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
213
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|
516 cycles += 12; |
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Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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|
517 } else if(inst->addr_mode == Z80_IMMED) { |
4d4559b04c59
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changeset
|
518 cycles += 3; |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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changeset
|
519 } |
4d4559b04c59
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parents:
diff
changeset
|
520 dst = zcycles(dst, cycles); |
4d4559b04c59
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Mike Pavone <pavone@retrodev.com>
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changeset
|
521 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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diff
changeset
|
522 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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changeset
|
523 if (src_op.mode == MODE_REG_DIRECT) { |
4d4559b04c59
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Mike Pavone <pavone@retrodev.com>
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changeset
|
524 dst = sub_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
4d4559b04c59
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diff
changeset
|
525 } else { |
4d4559b04c59
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Mike Pavone <pavone@retrodev.com>
parents:
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changeset
|
526 dst = sub_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
4d4559b04c59
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parents:
diff
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|
527 } |
4d4559b04c59
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Mike Pavone <pavone@retrodev.com>
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diff
changeset
|
528 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
235
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diff
changeset
|
529 dst = mov_irdisp8(dst, 1, CONTEXT, zf_off(ZF_N), SZ_B); |
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Mike Pavone <pavone@retrodev.com>
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diff
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|
530 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
213
4d4559b04c59
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
531 //TODO: Implement half-carry flag |
235
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532 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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diff
changeset
|
533 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
213
4d4559b04c59
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Mike Pavone <pavone@retrodev.com>
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diff
changeset
|
534 dst = z80_save_reg(dst, inst, opts); |
4d4559b04c59
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
535 dst = z80_save_ea(dst, inst, opts); |
4d4559b04c59
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changeset
|
536 break; |
248
9c7a3db7bcd0
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|
537 case Z80_SBC: |
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538 cycles = 4; |
9c7a3db7bcd0
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539 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
9c7a3db7bcd0
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|
540 cycles += 12; |
9c7a3db7bcd0
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|
541 } else if(inst->addr_mode == Z80_IMMED) { |
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parents:
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542 cycles += 3; |
9c7a3db7bcd0
Implement ADC and SBC in Z80 core (untested)
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543 } else if(z80_size(inst) == SZ_W) { |
9c7a3db7bcd0
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544 cycles += 4; |
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247
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545 } |
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|
546 dst = zcycles(dst, cycles); |
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Mike Pavone <pavone@retrodev.com>
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247
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547 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
9c7a3db7bcd0
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changeset
|
548 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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Mike Pavone <pavone@retrodev.com>
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changeset
|
549 if (src_op.mode == MODE_REG_DIRECT) { |
9c7a3db7bcd0
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diff
changeset
|
550 dst = sbb_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
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551 } else { |
9c7a3db7bcd0
Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
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changeset
|
552 dst = sbb_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
9c7a3db7bcd0
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parents:
247
diff
changeset
|
553 } |
9c7a3db7bcd0
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Mike Pavone <pavone@retrodev.com>
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247
diff
changeset
|
554 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
9c7a3db7bcd0
Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
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247
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changeset
|
555 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
9c7a3db7bcd0
Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents:
247
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changeset
|
556 //TODO: Implement half-carry flag |
9c7a3db7bcd0
Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
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247
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changeset
|
557 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
9c7a3db7bcd0
Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
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247
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changeset
|
558 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
9c7a3db7bcd0
Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
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247
diff
changeset
|
559 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
9c7a3db7bcd0
Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents:
247
diff
changeset
|
560 dst = z80_save_reg(dst, inst, opts); |
9c7a3db7bcd0
Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
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247
diff
changeset
|
561 dst = z80_save_ea(dst, inst, opts); |
9c7a3db7bcd0
Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
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247
diff
changeset
|
562 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
563 case Z80_AND: |
236
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
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235
diff
changeset
|
564 cycles = 4; |
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
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235
diff
changeset
|
565 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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parents:
235
diff
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|
566 cycles += 12; |
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235
diff
changeset
|
567 } else if(inst->addr_mode == Z80_IMMED) { |
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
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235
diff
changeset
|
568 cycles += 3; |
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
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235
diff
changeset
|
569 } else if(z80_size(inst) == SZ_W) { |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
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|
570 cycles += 4; |
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
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|
571 } |
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
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235
diff
changeset
|
572 dst = zcycles(dst, cycles); |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
573 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
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235
diff
changeset
|
574 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
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235
diff
changeset
|
575 if (src_op.mode == MODE_REG_DIRECT) { |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
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235
diff
changeset
|
576 dst = and_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
19fb3523a9e5
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235
diff
changeset
|
577 } else { |
19fb3523a9e5
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parents:
235
diff
changeset
|
578 dst = and_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
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235
diff
changeset
|
579 } |
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235
diff
changeset
|
580 //TODO: Cleanup flags |
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
581 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
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235
diff
changeset
|
582 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
19fb3523a9e5
Implement more Z80 instructions (untested)
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parents:
235
diff
changeset
|
583 //TODO: Implement half-carry flag |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
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235
diff
changeset
|
584 if (z80_size(inst) == SZ_B) { |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
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235
diff
changeset
|
585 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
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235
diff
changeset
|
586 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
19fb3523a9e5
Implement more Z80 instructions (untested)
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235
diff
changeset
|
587 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
19fb3523a9e5
Implement more Z80 instructions (untested)
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235
diff
changeset
|
588 } |
19fb3523a9e5
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235
diff
changeset
|
589 dst = z80_save_reg(dst, inst, opts); |
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
590 dst = z80_save_ea(dst, inst, opts); |
19fb3523a9e5
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parents:
235
diff
changeset
|
591 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
592 case Z80_OR: |
236
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
593 cycles = 4; |
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
594 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
595 cycles += 12; |
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
596 } else if(inst->addr_mode == Z80_IMMED) { |
19fb3523a9e5
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parents:
235
diff
changeset
|
597 cycles += 3; |
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
598 } else if(z80_size(inst) == SZ_W) { |
19fb3523a9e5
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235
diff
changeset
|
599 cycles += 4; |
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
600 } |
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235
diff
changeset
|
601 dst = zcycles(dst, cycles); |
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Implement more Z80 instructions (untested)
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235
diff
changeset
|
602 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
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235
diff
changeset
|
603 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
19fb3523a9e5
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235
diff
changeset
|
604 if (src_op.mode == MODE_REG_DIRECT) { |
19fb3523a9e5
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235
diff
changeset
|
605 dst = or_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
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235
diff
changeset
|
606 } else { |
19fb3523a9e5
Implement more Z80 instructions (untested)
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235
diff
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607 dst = or_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
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608 } |
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609 //TODO: Cleanup flags |
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610 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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611 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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612 //TODO: Implement half-carry flag |
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613 if (z80_size(inst) == SZ_B) { |
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614 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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615 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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616 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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617 } |
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618 dst = z80_save_reg(dst, inst, opts); |
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619 dst = z80_save_ea(dst, inst, opts); |
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620 break; |
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621 case Z80_XOR: |
236
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622 cycles = 4; |
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623 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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624 cycles += 12; |
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625 } else if(inst->addr_mode == Z80_IMMED) { |
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626 cycles += 3; |
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627 } else if(z80_size(inst) == SZ_W) { |
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628 cycles += 4; |
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629 } |
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630 dst = zcycles(dst, cycles); |
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631 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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632 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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633 if (src_op.mode == MODE_REG_DIRECT) { |
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634 dst = add_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
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635 } else { |
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636 dst = add_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
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637 } |
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638 //TODO: Cleanup flags |
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639 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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640 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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641 //TODO: Implement half-carry flag |
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642 if (z80_size(inst) == SZ_B) { |
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643 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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644 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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645 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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646 } |
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647 dst = z80_save_reg(dst, inst, opts); |
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648 dst = z80_save_ea(dst, inst, opts); |
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649 break; |
242 | 650 case Z80_CP: |
651 cycles = 4; | |
652 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { | |
653 cycles += 12; | |
654 } else if(inst->addr_mode == Z80_IMMED) { | |
655 cycles += 3; | |
656 } | |
657 dst = zcycles(dst, cycles); | |
658 dst = translate_z80_reg(inst, &dst_op, dst, opts); | |
659 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); | |
660 if (src_op.mode == MODE_REG_DIRECT) { | |
661 dst = cmp_rr(dst, src_op.base, dst_op.base, z80_size(inst)); | |
662 } else { | |
663 dst = cmp_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); | |
664 } | |
665 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); | |
666 dst = mov_irdisp8(dst, 1, CONTEXT, zf_off(ZF_N), SZ_B); | |
667 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); | |
668 //TODO: Implement half-carry flag | |
669 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); | |
670 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); | |
671 dst = z80_save_reg(dst, inst, opts); | |
672 dst = z80_save_ea(dst, inst, opts); | |
673 break; | |
213
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674 case Z80_INC: |
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675 cycles = 4; |
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676 if (inst->reg == Z80_IX || inst->reg == Z80_IY) { |
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677 cycles += 6; |
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678 } else if(z80_size(inst) == SZ_W) { |
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679 cycles += 2; |
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680 } else if(inst->reg == Z80_IXH || inst->reg == Z80_IXL || inst->reg == Z80_IYH || inst->reg == Z80_IYL || inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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681 cycles += 4; |
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682 } |
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683 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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684 if (dst_op.mode == MODE_UNUSED) { |
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685 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
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686 } |
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687 dst = add_ir(dst, 1, dst_op.base, z80_size(inst)); |
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688 if (z80_size(inst) == SZ_B) { |
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689 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
213
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690 //TODO: Implement half-carry flag |
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691 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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692 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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693 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
213
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694 } |
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695 dst = z80_save_reg(dst, inst, opts); |
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696 dst = z80_save_ea(dst, inst, opts); |
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697 break; |
236
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698 case Z80_DEC: |
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699 cycles = 4; |
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700 if (inst->reg == Z80_IX || inst->reg == Z80_IY) { |
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701 cycles += 6; |
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702 } else if(z80_size(inst) == SZ_W) { |
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703 cycles += 2; |
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704 } else if(inst->reg == Z80_IXH || inst->reg == Z80_IXL || inst->reg == Z80_IYH || inst->reg == Z80_IYL || inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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705 cycles += 4; |
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706 } |
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707 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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708 if (dst_op.mode == MODE_UNUSED) { |
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709 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
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710 } |
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711 dst = sub_ir(dst, 1, dst_op.base, z80_size(inst)); |
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712 if (z80_size(inst) == SZ_B) { |
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713 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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714 //TODO: Implement half-carry flag |
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715 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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716 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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717 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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718 } |
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719 dst = z80_save_reg(dst, inst, opts); |
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720 dst = z80_save_ea(dst, inst, opts); |
213
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721 break; |
236
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722 /*case Z80_DAA: |
213
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723 case Z80_CPL: |
257 | 724 case Z80_NEG:*/ |
213
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725 case Z80_CCF: |
257 | 726 dst = zcycles(dst, 4); |
727 dst = xor_irdisp8(dst, 1, CONTEXT, zf_off(ZF_C), SZ_B); | |
728 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); | |
729 //TODO: Implement half-carry flag | |
730 break; | |
731 case Z80_SCF: | |
732 dst = zcycles(dst, 4); | |
733 dst = mov_irdisp8(dst, 1, CONTEXT, zf_off(ZF_C), SZ_B); | |
734 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); | |
735 //TODO: Implement half-carry flag | |
736 break; | |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
737 case Z80_NOP: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
738 if (inst->immed == 42) { |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
739 dst = call(dst, (uint8_t *)z80_save_context); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
740 dst = mov_rr(dst, CONTEXT, RDI, SZ_Q); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
741 dst = jmp(dst, (uint8_t *)z80_print_regs_exit); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
742 } else { |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
743 dst = zcycles(dst, 4 * inst->immed); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
744 } |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
745 break; |
243
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
746 //case Z80_HALT: |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
747 case Z80_DI: |
243
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
748 dst = zcycles(dst, 4); |
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
749 dst = mov_irdisp8(dst, 0, CONTEXT, offsetof(z80_context, iff1), SZ_B); |
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
750 dst = mov_irdisp8(dst, 0, CONTEXT, offsetof(z80_context, iff2), SZ_B); |
250
5f1b68cecfc7
Implemented basic interrupt support in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
248
diff
changeset
|
751 dst = mov_rdisp8r(dst, CONTEXT, offsetof(z80_context, sync_cycle), ZLIMIT, SZ_D); |
243
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
752 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
753 case Z80_EI: |
243
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
754 //TODO: Implement interrupt enable latency of 1 instruction afer EI |
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
755 dst = zcycles(dst, 4); |
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
756 dst = mov_irdisp8(dst, 1, CONTEXT, offsetof(z80_context, iff1), SZ_B); |
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
757 dst = mov_irdisp8(dst, 1, CONTEXT, offsetof(z80_context, iff2), SZ_B); |
250
5f1b68cecfc7
Implemented basic interrupt support in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
248
diff
changeset
|
758 dst = call(dst, (uint8_t *)z80_do_sync); |
243
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
759 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
760 case Z80_IM: |
243
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
761 dst = zcycles(dst, 4); |
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
762 dst = mov_irdisp8(dst, inst->immed, CONTEXT, offsetof(z80_context, im), SZ_B); |
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
763 break; |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
764 case Z80_RLC: |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
765 cycles = inst->immed == 1 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
766 dst = zcycles(dst, cycles); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
767 if (inst->reg == Z80_UNUSED) { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
768 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
769 dst = zcycles(dst, 1); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
770 } else { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
771 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
772 } |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
773 dst = rol_ir(dst, 1, dst_op.base, SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
774 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
775 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
776 //TODO: Implement half-carry flag |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
777 dst = cmp_ir(dst, 0, dst_op.base, SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
778 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
779 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
780 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
781 if (inst->reg == Z80_UNUSED) { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
782 dst = z80_save_result(dst, inst); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
783 } else { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
784 dst = z80_save_reg(dst, inst, opts); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
785 } |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
786 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
787 case Z80_RL: |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
788 cycles = inst->immed == 1 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
789 dst = zcycles(dst, cycles); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
790 if (inst->reg == Z80_UNUSED) { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
791 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
792 dst = zcycles(dst, 1); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
793 } else { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
794 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
795 } |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
796 dst = bt_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
797 dst = rcl_ir(dst, 1, dst_op.base, SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
798 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
799 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
800 //TODO: Implement half-carry flag |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
801 dst = cmp_ir(dst, 0, dst_op.base, SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
802 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
803 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
804 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
805 if (inst->reg == Z80_UNUSED) { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
806 dst = z80_save_result(dst, inst); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
807 } else { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
808 dst = z80_save_reg(dst, inst, opts); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
809 } |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
810 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
811 case Z80_RRC: |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
812 cycles = inst->immed == 1 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
813 dst = zcycles(dst, cycles); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
814 if (inst->reg == Z80_UNUSED) { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
815 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
816 dst = zcycles(dst, 1); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
817 } else { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
818 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
819 } |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
820 dst = ror_ir(dst, 1, dst_op.base, SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
821 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
822 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
823 //TODO: Implement half-carry flag |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
824 dst = cmp_ir(dst, 0, dst_op.base, SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
825 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
826 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
827 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
828 if (inst->reg == Z80_UNUSED) { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
829 dst = z80_save_result(dst, inst); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
830 } else { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
831 dst = z80_save_reg(dst, inst, opts); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
832 } |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
833 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
834 case Z80_RR: |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
835 cycles = inst->immed == 1 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
836 dst = zcycles(dst, cycles); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
837 if (inst->reg == Z80_UNUSED) { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
838 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
839 dst = zcycles(dst, 1); |
682e505f5757
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246
diff
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|
840 } else { |
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diff
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|
841 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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diff
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|
842 } |
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|
843 dst = bt_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
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246
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|
844 dst = rcr_ir(dst, 1, dst_op.base, SZ_B); |
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|
845 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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diff
changeset
|
846 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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diff
changeset
|
847 //TODO: Implement half-carry flag |
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diff
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|
848 dst = cmp_ir(dst, 0, dst_op.base, SZ_B); |
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246
diff
changeset
|
849 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
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|
850 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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diff
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|
851 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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diff
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|
852 if (inst->reg == Z80_UNUSED) { |
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246
diff
changeset
|
853 dst = z80_save_result(dst, inst); |
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246
diff
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|
854 } else { |
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246
diff
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|
855 dst = z80_save_reg(dst, inst, opts); |
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|
856 } |
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|
857 break; |
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|
858 /*case Z80_SLA: |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
859 case Z80_SRA: |
4d4559b04c59
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
860 case Z80_SLL: |
4d4559b04c59
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
861 case Z80_SRL: |
4d4559b04c59
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
862 case Z80_RLD: |
239
a5bea9711a46
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238
diff
changeset
|
863 case Z80_RRD:*/ |
213
4d4559b04c59
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
864 case Z80_BIT: |
239
a5bea9711a46
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changeset
|
865 cycles = (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) ? 8 : 16; |
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238
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|
866 dst = zcycles(dst, cycles); |
a5bea9711a46
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238
diff
changeset
|
867 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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|
868 if (inst->addr_mode != Z80_REG) { |
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238
diff
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|
869 //Reads normally take 3 cycles, but the read at the end of a bit instruction takes 4 |
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|
870 dst = zcycles(dst, 1); |
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238
diff
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|
871 } |
a5bea9711a46
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|
872 dst = bt_ir(dst, inst->immed, src_op.base, SZ_B); |
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|
873 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_Z)); |
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238
diff
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|
874 break; |
247
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246
diff
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|
875 case Z80_SET: |
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246
diff
changeset
|
876 cycles = (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) ? 8 : 16; |
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246
diff
changeset
|
877 dst = zcycles(dst, cycles); |
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246
diff
changeset
|
878 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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|
879 if (inst->addr_mode != Z80_REG) { |
682e505f5757
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diff
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|
880 //Reads normally take 3 cycles, but the read in the middle of a set instruction takes 4 |
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246
diff
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|
881 dst = zcycles(dst, 1); |
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246
diff
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|
882 } |
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246
diff
changeset
|
883 dst = bts_ir(dst, inst->immed, src_op.base, SZ_B); |
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246
diff
changeset
|
884 if (inst->addr_mode != Z80_REG) { |
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246
diff
changeset
|
885 dst = z80_save_result(dst, inst); |
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246
diff
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|
886 } |
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Implement rotation and bit set/reset instructions (untested).
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246
diff
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|
887 break; |
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parents:
246
diff
changeset
|
888 case Z80_RES: |
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246
diff
changeset
|
889 cycles = (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) ? 8 : 16; |
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246
diff
changeset
|
890 dst = zcycles(dst, cycles); |
682e505f5757
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246
diff
changeset
|
891 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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246
diff
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|
892 if (inst->addr_mode != Z80_REG) { |
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246
diff
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|
893 //Reads normally take 3 cycles, but the read in the middle of a set instruction takes 4 |
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246
diff
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|
894 dst = zcycles(dst, 1); |
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246
diff
changeset
|
895 } |
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246
diff
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|
896 dst = btr_ir(dst, inst->immed, src_op.base, SZ_B); |
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246
diff
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|
897 if (inst->addr_mode != Z80_REG) { |
682e505f5757
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246
diff
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|
898 dst = z80_save_result(dst, inst); |
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246
diff
changeset
|
899 } |
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246
diff
changeset
|
900 break; |
236
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235
diff
changeset
|
901 case Z80_JP: { |
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Implement more Z80 instructions (untested)
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parents:
235
diff
changeset
|
902 cycles = 4; |
239
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
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238
diff
changeset
|
903 if (inst->addr_mode != Z80_REG) { |
236
19fb3523a9e5
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235
diff
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|
904 cycles += 6; |
19fb3523a9e5
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235
diff
changeset
|
905 } else if(inst->ea_reg == Z80_IX || inst->ea_reg == Z80_IY) { |
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235
diff
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|
906 cycles += 4; |
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Implement more Z80 instructions (untested)
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parents:
235
diff
changeset
|
907 } |
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Implement more Z80 instructions (untested)
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235
diff
changeset
|
908 dst = zcycles(dst, cycles); |
239
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
909 if (inst->addr_mode != Z80_REG_INDIRECT && inst->immed < 0x4000) { |
236
19fb3523a9e5
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parents:
235
diff
changeset
|
910 uint8_t * call_dst = z80_get_native_address(context, inst->immed); |
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Implement more Z80 instructions (untested)
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235
diff
changeset
|
911 if (!call_dst) { |
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Implement more Z80 instructions (untested)
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235
diff
changeset
|
912 opts->deferred = defer_address(opts->deferred, inst->immed, dst + 1); |
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235
diff
changeset
|
913 //fake address to force large displacement |
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Implement more Z80 instructions (untested)
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235
diff
changeset
|
914 call_dst = dst + 256; |
19fb3523a9e5
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235
diff
changeset
|
915 } |
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235
diff
changeset
|
916 dst = jmp(dst, call_dst); |
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Implement more Z80 instructions (untested)
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235
diff
changeset
|
917 } else { |
239
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
918 if (inst->addr_mode == Z80_REG_INDIRECT) { |
236
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
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235
diff
changeset
|
919 dst = mov_rr(dst, opts->regs[inst->ea_reg], SCRATCH1, SZ_W); |
19fb3523a9e5
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235
diff
changeset
|
920 } else { |
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
921 dst = mov_ir(dst, inst->immed, SCRATCH1, SZ_W); |
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
922 } |
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235
diff
changeset
|
923 dst = call(dst, (uint8_t *)z80_native_addr); |
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235
diff
changeset
|
924 dst = jmp_r(dst, SCRATCH1); |
19fb3523a9e5
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235
diff
changeset
|
925 } |
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parents:
235
diff
changeset
|
926 break; |
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parents:
235
diff
changeset
|
927 } |
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235
diff
changeset
|
928 case Z80_JPCC: { |
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235
diff
changeset
|
929 dst = zcycles(dst, 7);//T States: 4,3 |
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Mike Pavone <pavone@retrodev.com>
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235
diff
changeset
|
930 uint8_t cond = CC_Z; |
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235
diff
changeset
|
931 switch (inst->reg) |
19fb3523a9e5
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parents:
235
diff
changeset
|
932 { |
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parents:
235
diff
changeset
|
933 case Z80_CC_NZ: |
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235
diff
changeset
|
934 cond = CC_NZ; |
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235
diff
changeset
|
935 case Z80_CC_Z: |
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235
diff
changeset
|
936 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_Z), SZ_B); |
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parents:
235
diff
changeset
|
937 break; |
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parents:
235
diff
changeset
|
938 case Z80_CC_NC: |
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235
diff
changeset
|
939 cond = CC_NZ; |
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235
diff
changeset
|
940 case Z80_CC_C: |
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235
diff
changeset
|
941 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
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parents:
235
diff
changeset
|
942 break; |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
943 case Z80_CC_PO: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
944 cond = CC_NZ; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
945 case Z80_CC_PE: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
946 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_PV), SZ_B); |
827ebce557bf
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Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
947 break; |
827ebce557bf
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Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
948 case Z80_CC_P: |
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949 case Z80_CC_M: |
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950 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_S), SZ_B); |
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951 break; |
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952 } |
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953 uint8_t *no_jump_off = dst+1; |
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954 dst = jcc(dst, cond, dst+2); |
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955 dst = zcycles(dst, 5);//T States: 5 |
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956 uint16_t dest_addr = inst->immed; |
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957 if (dest_addr < 0x4000) { |
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958 uint8_t * call_dst = z80_get_native_address(context, dest_addr); |
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959 if (!call_dst) { |
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960 opts->deferred = defer_address(opts->deferred, dest_addr, dst + 1); |
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961 //fake address to force large displacement |
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962 call_dst = dst + 256; |
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963 } |
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964 dst = jmp(dst, call_dst); |
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965 } else { |
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966 dst = mov_ir(dst, dest_addr, SCRATCH1, SZ_W); |
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967 dst = call(dst, (uint8_t *)z80_native_addr); |
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968 dst = jmp_r(dst, SCRATCH1); |
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969 } |
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970 *no_jump_off = dst - (no_jump_off+1); |
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971 break; |
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972 } |
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973 case Z80_JR: { |
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974 dst = zcycles(dst, 12);//T States: 4,3,5 |
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975 uint16_t dest_addr = address + inst->immed + 2; |
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976 if (dest_addr < 0x4000) { |
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977 uint8_t * call_dst = z80_get_native_address(context, dest_addr); |
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978 if (!call_dst) { |
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979 opts->deferred = defer_address(opts->deferred, dest_addr, dst + 1); |
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980 //fake address to force large displacement |
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981 call_dst = dst + 256; |
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982 } |
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983 dst = jmp(dst, call_dst); |
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984 } else { |
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985 dst = mov_ir(dst, dest_addr, SCRATCH1, SZ_W); |
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986 dst = call(dst, (uint8_t *)z80_native_addr); |
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987 dst = jmp_r(dst, SCRATCH1); |
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988 } |
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989 break; |
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990 } |
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991 case Z80_JRCC: { |
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992 dst = zcycles(dst, 7);//T States: 4,3 |
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993 uint8_t cond = CC_Z; |
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994 switch (inst->reg) |
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995 { |
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996 case Z80_CC_NZ: |
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997 cond = CC_NZ; |
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998 case Z80_CC_Z: |
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999 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_Z), SZ_B); |
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1000 break; |
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1001 case Z80_CC_NC: |
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1002 cond = CC_NZ; |
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1003 case Z80_CC_C: |
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1004 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
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1005 break; |
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1006 } |
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1007 uint8_t *no_jump_off = dst+1; |
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1008 dst = jcc(dst, cond, dst+2); |
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1009 dst = zcycles(dst, 5);//T States: 5 |
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1010 uint16_t dest_addr = address + inst->immed + 2; |
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1011 if (dest_addr < 0x4000) { |
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1012 uint8_t * call_dst = z80_get_native_address(context, dest_addr); |
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1013 if (!call_dst) { |
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1014 opts->deferred = defer_address(opts->deferred, dest_addr, dst + 1); |
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1015 //fake address to force large displacement |
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1016 call_dst = dst + 256; |
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1017 } |
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1018 dst = jmp(dst, call_dst); |
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1019 } else { |
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1020 dst = mov_ir(dst, dest_addr, SCRATCH1, SZ_W); |
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1021 dst = call(dst, (uint8_t *)z80_native_addr); |
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1022 dst = jmp_r(dst, SCRATCH1); |
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1023 } |
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1024 *no_jump_off = dst - (no_jump_off+1); |
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1025 break; |
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1026 } |
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1027 case Z80_DJNZ: |
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1028 dst = zcycles(dst, 8);//T States: 5,3 |
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1029 dst = sub_ir(dst, 1, opts->regs[Z80_B], SZ_B); |
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1030 uint8_t *no_jump_off = dst+1; |
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1031 dst = jcc(dst, CC_Z, dst+2); |
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1032 dst = zcycles(dst, 5);//T States: 5 |
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1033 uint16_t dest_addr = address + inst->immed + 2; |
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1034 if (dest_addr < 0x4000) { |
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1035 uint8_t * call_dst = z80_get_native_address(context, dest_addr); |
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1036 if (!call_dst) { |
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1037 opts->deferred = defer_address(opts->deferred, dest_addr, dst + 1); |
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1038 //fake address to force large displacement |
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1039 call_dst = dst + 256; |
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1040 } |
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1041 dst = jmp(dst, call_dst); |
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1042 } else { |
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1043 dst = mov_ir(dst, dest_addr, SCRATCH1, SZ_W); |
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1044 dst = call(dst, (uint8_t *)z80_native_addr); |
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1045 dst = jmp_r(dst, SCRATCH1); |
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1046 } |
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1047 *no_jump_off = dst - (no_jump_off+1); |
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1048 break; |
235
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1049 case Z80_CALL: { |
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1050 dst = zcycles(dst, 11);//T States: 4,3,4 |
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1051 dst = sub_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
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1052 dst = mov_ir(dst, address + 3, SCRATCH1, SZ_W); |
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1053 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W); |
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1054 dst = call(dst, (uint8_t *)z80_write_word_highfirst);//T States: 3, 3 |
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1055 if (inst->immed < 0x4000) { |
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1056 uint8_t * call_dst = z80_get_native_address(context, inst->immed); |
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1057 if (!call_dst) { |
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1058 opts->deferred = defer_address(opts->deferred, inst->immed, dst + 1); |
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1059 //fake address to force large displacement |
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|
1060 call_dst = dst + 256; |
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1061 } |
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213
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|
1062 dst = jmp(dst, call_dst); |
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213
diff
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|
1063 } else { |
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213
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|
1064 dst = mov_ir(dst, inst->immed, SCRATCH1, SZ_W); |
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1065 dst = call(dst, (uint8_t *)z80_native_addr); |
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213
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changeset
|
1066 dst = jmp_r(dst, SCRATCH1); |
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213
diff
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|
1067 } |
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213
diff
changeset
|
1068 break; |
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213
diff
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|
1069 } |
238
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236
diff
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|
1070 case Z80_CALLCC: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
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236
diff
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|
1071 dst = zcycles(dst, 10);//T States: 4,3,3 (false case) |
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236
diff
changeset
|
1072 uint8_t cond = CC_Z; |
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236
diff
changeset
|
1073 switch (inst->reg) |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
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236
diff
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|
1074 { |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
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236
diff
changeset
|
1075 case Z80_CC_NZ: |
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236
diff
changeset
|
1076 cond = CC_NZ; |
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236
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changeset
|
1077 case Z80_CC_Z: |
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Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
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236
diff
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|
1078 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_Z), SZ_B); |
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Added the rest of the conditions to JPCC, implemented CALLCC (untested)
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236
diff
changeset
|
1079 break; |
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236
diff
changeset
|
1080 case Z80_CC_NC: |
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236
diff
changeset
|
1081 cond = CC_NZ; |
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236
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|
1082 case Z80_CC_C: |
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Added the rest of the conditions to JPCC, implemented CALLCC (untested)
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236
diff
changeset
|
1083 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
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236
diff
changeset
|
1084 break; |
827ebce557bf
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236
diff
changeset
|
1085 case Z80_CC_PO: |
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Added the rest of the conditions to JPCC, implemented CALLCC (untested)
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|
1086 cond = CC_NZ; |
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236
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|
1087 case Z80_CC_PE: |
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236
diff
changeset
|
1088 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_PV), SZ_B); |
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236
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|
1089 break; |
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236
diff
changeset
|
1090 case Z80_CC_P: |
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236
diff
changeset
|
1091 case Z80_CC_M: |
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|
1092 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_S), SZ_B); |
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236
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changeset
|
1093 break; |
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236
diff
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|
1094 } |
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236
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|
1095 uint8_t *no_call_off = dst+1; |
827ebce557bf
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|
1096 dst = jcc(dst, cond, dst+2); |
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|
1097 dst = zcycles(dst, 1);//Last of the above T states takes an extra cycle in the true case |
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|
1098 dst = sub_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
253
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Mike Pavone <pavone@retrodev.com>
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252
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|
1099 dst = mov_ir(dst, address + 3, SCRATCH1, SZ_W); |
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|
1100 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W); |
238
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1101 dst = call(dst, (uint8_t *)z80_write_word_highfirst);//T States: 3, 3 |
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236
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|
1102 if (inst->immed < 0x4000) { |
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236
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|
1103 uint8_t * call_dst = z80_get_native_address(context, inst->immed); |
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|
1104 if (!call_dst) { |
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236
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changeset
|
1105 opts->deferred = defer_address(opts->deferred, inst->immed, dst + 1); |
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236
diff
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|
1106 //fake address to force large displacement |
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236
diff
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|
1107 call_dst = dst + 256; |
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diff
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|
1108 } |
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236
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|
1109 dst = jmp(dst, call_dst); |
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236
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|
1110 } else { |
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236
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|
1111 dst = mov_ir(dst, inst->immed, SCRATCH1, SZ_W); |
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236
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|
1112 dst = call(dst, (uint8_t *)z80_native_addr); |
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236
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changeset
|
1113 dst = jmp_r(dst, SCRATCH1); |
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236
diff
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|
1114 } |
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236
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|
1115 *no_call_off = dst - (no_call_off+1); |
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236
diff
changeset
|
1116 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1117 case Z80_RET: |
235
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|
1118 dst = zcycles(dst, 4);//T States: 4 |
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|
1119 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
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213
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1120 dst = call(dst, (uint8_t *)z80_read_word);//T STates: 3, 3 |
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|
1121 dst = add_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
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changeset
|
1122 dst = call(dst, (uint8_t *)z80_native_addr); |
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213
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|
1123 dst = jmp_r(dst, SCRATCH1); |
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213
diff
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|
1124 break; |
246
ed548c77b598
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243
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changeset
|
1125 case Z80_RETCC: { |
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243
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|
1126 dst = zcycles(dst, 5);//T States: 5 |
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243
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|
1127 uint8_t cond = CC_Z; |
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Implement RETCC in Z80 core.
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243
diff
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|
1128 switch (inst->reg) |
ed548c77b598
Implement RETCC in Z80 core.
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243
diff
changeset
|
1129 { |
ed548c77b598
Implement RETCC in Z80 core.
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243
diff
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|
1130 case Z80_CC_NZ: |
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Implement RETCC in Z80 core.
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243
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|
1131 cond = CC_NZ; |
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243
diff
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|
1132 case Z80_CC_Z: |
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Implement RETCC in Z80 core.
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243
diff
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|
1133 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_Z), SZ_B); |
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Implement RETCC in Z80 core.
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243
diff
changeset
|
1134 break; |
ed548c77b598
Implement RETCC in Z80 core.
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243
diff
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|
1135 case Z80_CC_NC: |
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Implement RETCC in Z80 core.
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243
diff
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|
1136 cond = CC_NZ; |
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243
diff
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|
1137 case Z80_CC_C: |
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243
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|
1138 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
ed548c77b598
Implement RETCC in Z80 core.
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243
diff
changeset
|
1139 break; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
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243
diff
changeset
|
1140 case Z80_CC_PO: |
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Implement RETCC in Z80 core.
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243
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|
1141 cond = CC_NZ; |
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|
1142 case Z80_CC_PE: |
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|
1143 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_PV), SZ_B); |
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243
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changeset
|
1144 break; |
ed548c77b598
Implement RETCC in Z80 core.
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243
diff
changeset
|
1145 case Z80_CC_P: |
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Implement RETCC in Z80 core.
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243
diff
changeset
|
1146 case Z80_CC_M: |
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243
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|
1147 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_S), SZ_B); |
ed548c77b598
Implement RETCC in Z80 core.
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243
diff
changeset
|
1148 break; |
ed548c77b598
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243
diff
changeset
|
1149 } |
ed548c77b598
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243
diff
changeset
|
1150 uint8_t *no_call_off = dst+1; |
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Implement RETCC in Z80 core.
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243
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changeset
|
1151 dst = jcc(dst, cond, dst+2); |
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Implement RETCC in Z80 core.
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243
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changeset
|
1152 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
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243
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|
1153 dst = call(dst, (uint8_t *)z80_read_word);//T STates: 3, 3 |
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243
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changeset
|
1154 dst = add_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
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Implement RETCC in Z80 core.
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243
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changeset
|
1155 dst = call(dst, (uint8_t *)z80_native_addr); |
ed548c77b598
Implement RETCC in Z80 core.
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243
diff
changeset
|
1156 dst = jmp_r(dst, SCRATCH1); |
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Implement RETCC in Z80 core.
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243
diff
changeset
|
1157 *no_call_off = dst - (no_call_off+1); |
ed548c77b598
Implement RETCC in Z80 core.
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243
diff
changeset
|
1158 break; |
ed548c77b598
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243
diff
changeset
|
1159 } |
ed548c77b598
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243
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|
1160 /*case Z80_RETI: |
241
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239
diff
changeset
|
1161 case Z80_RETN:*/ |
2586d49ddd46
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239
diff
changeset
|
1162 case Z80_RST: { |
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|
1163 //RST is basically CALL to an address in page 0 |
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239
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changeset
|
1164 dst = zcycles(dst, 5);//T States: 5 |
2586d49ddd46
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239
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changeset
|
1165 dst = sub_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
253
3b34deba4ca0
Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
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252
diff
changeset
|
1166 dst = mov_ir(dst, address + 3, SCRATCH1, SZ_W); |
3b34deba4ca0
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changeset
|
1167 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W); |
241
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changeset
|
1168 dst = call(dst, (uint8_t *)z80_write_word_highfirst);//T States: 3, 3 |
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|
1169 uint8_t * call_dst = z80_get_native_address(context, inst->immed); |
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Implement EX, EXX and RST in Z80 core
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1170 if (!call_dst) { |
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1171 opts->deferred = defer_address(opts->deferred, inst->immed, dst + 1); |
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1172 //fake address to force large displacement |
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1173 call_dst = dst + 256; |
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1174 } |
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1175 dst = jmp(dst, call_dst); |
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1176 break; |
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1177 } |
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1178 /*case Z80_IN: |
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1179 case Z80_INI: |
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1180 case Z80_INIR: |
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1181 case Z80_IND: |
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1182 case Z80_INDR: |
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1183 case Z80_OUT: |
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1184 case Z80_OUTI: |
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1185 case Z80_OTIR: |
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1186 case Z80_OUTD: |
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1187 case Z80_OTDR:*/ |
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1188 default: { |
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1189 char disbuf[80]; |
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1190 z80_disasm(inst, disbuf); |
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1191 fprintf(stderr, "unimplemented instruction: %s\n", disbuf); |
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1192 FILE * f = fopen("zram.bin", "wb"); |
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1193 fwrite(context->mem_pointers[0], 1, 8 * 1024, f); |
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1194 fclose(f); |
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1195 exit(1); |
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1196 } |
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1197 } |
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1198 return dst; |
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1199 } |
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1200 |
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1201 uint8_t * z80_get_native_address(z80_context * context, uint32_t address) |
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1202 { |
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1203 native_map_slot *map; |
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1204 if (address < 0x4000) { |
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1205 address &= 0x1FFF; |
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1206 map = context->static_code_map; |
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1207 } else if (address >= 0x8000) { |
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1208 address &= 0x7FFF; |
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1209 map = context->banked_code_map + (context->bank_reg << 15); |
235
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1210 } else { |
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1211 return NULL; |
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1212 } |
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1213 if (!map->base || !map->offsets || map->offsets[address] == INVALID_OFFSET) { |
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1214 return NULL; |
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1215 } |
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1216 return map->base + map->offsets[address]; |
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1217 } |
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1218 |
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1219 uint8_t z80_get_native_inst_size(x86_z80_options * opts, uint32_t address) |
235
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1220 { |
252
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1221 if (address >= 0x4000) { |
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1222 return 0; |
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1223 } |
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1224 return opts->ram_inst_sizes[address & 0x1FFF]; |
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1225 } |
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1226 |
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Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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1227 void z80_map_native_address(z80_context * context, uint32_t address, uint8_t * native_address, uint8_t size, uint8_t native_size) |
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1228 { |
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1229 uint32_t orig_address = address; |
235
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1230 native_map_slot *map; |
252
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1231 x86_z80_options * opts = context->options; |
235
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1232 if (address < 0x4000) { |
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1233 address &= 0x1FFF; |
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1234 map = context->static_code_map; |
252
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1235 opts->ram_inst_sizes[address] = native_size; |
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1236 context->ram_code_flags[(address & 0x1C00) >> 10] |= 1 << ((address & 0x380) >> 7); |
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1237 context->ram_code_flags[((address + size) & 0x1C00) >> 10] |= 1 << (((address + size) & 0x380) >> 7); |
235
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1238 } else if (address >= 0x8000) { |
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1239 address &= 0x7FFF; |
252
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1240 map = context->banked_code_map + (context->bank_reg << 15); |
235
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1241 if (!map->offsets) { |
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1242 map->offsets = malloc(sizeof(int32_t) * 0x8000); |
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1243 memset(map->offsets, 0xFF, sizeof(int32_t) * 0x8000); |
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1244 } |
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1245 } else { |
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|
1246 return; |
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1247 } |
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1248 if (!map->base) { |
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1249 map->base = native_address; |
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1250 } |
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1251 map->offsets[address] = native_address - map->base; |
253
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1252 for(--size, orig_address++; size; --size, orig_address++) { |
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1253 address = orig_address; |
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1254 if (address < 0x4000) { |
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1255 address &= 0x1FFF; |
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1256 map = context->static_code_map; |
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1257 } else if (address >= 0x8000) { |
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1258 address &= 0x7FFF; |
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1259 map = context->banked_code_map + (context->bank_reg << 15); |
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1260 } else { |
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1261 return; |
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1262 } |
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1263 if (!map->offsets) { |
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1264 map->offsets = malloc(sizeof(int32_t) * 0x8000); |
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1265 memset(map->offsets, 0xFF, sizeof(int32_t) * 0x8000); |
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1266 } |
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1267 map->offsets[address] = EXTENSION_WORD; |
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1268 } |
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1269 } |
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1270 |
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1271 #define INVALID_INSTRUCTION_START 0xFEEDFEED |
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1272 |
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1273 uint32_t z80_get_instruction_start(native_map_slot * static_code_map, uint32_t address) |
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1274 { |
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|
1275 if (!static_code_map->base || address >= 0x4000) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1276 return INVALID_INSTRUCTION_START; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1277 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1278 address &= 0x1FFF; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1279 if (static_code_map->offsets[address] == INVALID_OFFSET) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1280 return INVALID_INSTRUCTION_START; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1281 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1282 while (static_code_map->offsets[address] == EXTENSION_WORD) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1283 --address; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1284 address &= 0x1FFF; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1285 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1286 return address; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1287 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1288 |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1289 z80_context * z80_handle_code_write(uint32_t address, z80_context * context) |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1290 { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
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|
1291 uint32_t inst_start = z80_get_instruction_start(context->static_code_map, address); |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
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|
1292 if (inst_start != INVALID_INSTRUCTION_START) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1293 uint8_t * dst = z80_get_native_address(context, inst_start); |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
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250
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|
1294 dst = mov_ir(dst, inst_start, SCRATCH1, SZ_D); |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
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diff
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|
1295 dst = jmp(dst, (uint8_t *)z80_retrans_stub); |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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250
diff
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|
1296 } |
63b9a500a00b
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Mike Pavone <pavone@retrodev.com>
parents:
250
diff
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|
1297 return context; |
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Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
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250
diff
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|
1298 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1299 |
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Mike Pavone <pavone@retrodev.com>
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|
1300 void * z80_retranslate_inst(uint32_t address, z80_context * context) |
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Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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250
diff
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|
1301 { |
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diff
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|
1302 x86_z80_options * opts = context->options; |
63b9a500a00b
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Mike Pavone <pavone@retrodev.com>
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250
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|
1303 uint8_t orig_size = z80_get_native_inst_size(opts, address); |
63b9a500a00b
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Mike Pavone <pavone@retrodev.com>
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250
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|
1304 uint8_t * orig_start = z80_get_native_address(context, address); |
63b9a500a00b
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250
diff
changeset
|
1305 uint32_t orig = address; |
63b9a500a00b
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250
diff
changeset
|
1306 address &= 0x1FFF; |
63b9a500a00b
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Mike Pavone <pavone@retrodev.com>
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250
diff
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|
1307 uint8_t * dst = opts->cur_code; |
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|
1308 uint8_t * dst_end = opts->code_end; |
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|
1309 uint8_t *after, *inst = context->mem_pointers[0] + address; |
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|
1310 z80inst instbuf; |
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|
1311 after = z80_decode(inst, &instbuf); |
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|
1312 if (orig_size != ZMAX_NATIVE_SIZE) { |
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250
diff
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|
1313 if (dst_end - dst < ZMAX_NATIVE_SIZE) { |
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Mike Pavone <pavone@retrodev.com>
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250
diff
changeset
|
1314 size_t size = 1024*1024; |
63b9a500a00b
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250
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|
1315 dst = alloc_code(&size); |
63b9a500a00b
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|
1316 opts->code_end = dst_end = dst + size; |
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1317 opts->cur_code = dst; |
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1318 } |
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|
1319 uint8_t * native_end = translate_z80inst(&instbuf, dst, context, address); |
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|
1320 if ((native_end - dst) <= orig_size) { |
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|
1321 native_end = translate_z80inst(&instbuf, orig_start, context, address); |
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|
1322 while (native_end < orig_start + orig_size) { |
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|
1323 *(native_end++) = 0x90; //NOP |
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1324 } |
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Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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|
1325 return orig_start; |
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1326 } else { |
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1327 z80_map_native_address(context, address, dst, after-inst, ZMAX_NATIVE_SIZE); |
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|
1328 opts->code_end = dst+ZMAX_NATIVE_SIZE; |
254
64feb6b67244
Fix bug in end condition inside translate_z80_stream.
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1329 if(!(instbuf.op == Z80_RET || instbuf.op == Z80_RETI || instbuf.op == Z80_RETN || instbuf.op == Z80_JP || (instbuf.op == Z80_NOP && instbuf.immed == 42))) { |
252
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Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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|
1330 jmp(native_end, z80_get_native_address(context, address + after-inst)); |
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1331 } |
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|
1332 return dst; |
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1333 } |
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1334 } else { |
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|
1335 dst = translate_z80inst(&instbuf, orig_start, context, address); |
254
64feb6b67244
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|
1336 if(!(instbuf.op == Z80_RET || instbuf.op == Z80_RETI || instbuf.op == Z80_RETN || instbuf.op == Z80_JP || (instbuf.op == Z80_NOP && instbuf.immed == 42))) { |
252
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|
1337 dst = jmp(dst, z80_get_native_address(context, address + after-inst)); |
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1338 } |
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|
1339 return orig_start; |
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1340 } |
235
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|
1341 } |
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|
1342 |
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1343 uint8_t * z80_get_native_address_trans(z80_context * context, uint32_t address) |
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1344 { |
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1345 uint8_t * addr = z80_get_native_address(context, address); |
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1346 if (!addr) { |
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|
1347 translate_z80_stream(context, address); |
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1348 addr = z80_get_native_address(context, address); |
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5f1b68cecfc7
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|
1349 if (!addr) { |
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1350 printf("Failed to translate %X to native code\n", address); |
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1351 } |
235
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|
1352 } |
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|
1353 return addr; |
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1354 } |
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|
1355 |
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1356 void translate_z80_stream(z80_context * context, uint32_t address) |
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1357 { |
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|
1358 char disbuf[80]; |
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1359 if (z80_get_native_address(context, address)) { |
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|
1360 return; |
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1361 } |
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|
1362 x86_z80_options * opts = context->options; |
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1363 uint8_t * encoded = NULL, *next; |
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1364 if (address < 0x4000) { |
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1365 encoded = context->mem_pointers[0] + (address & 0x1FFF); |
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1366 } else if(address >= 0x8000 && context->mem_pointers[1]) { |
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|
1367 encoded = context->mem_pointers[1] + (address & 0x7FFF); |
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1368 } |
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|
1369 while (encoded != NULL) |
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|
1370 { |
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|
1371 z80inst inst; |
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|
1372 printf("translating Z80 code at address %X\n", address); |
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|
1373 do { |
252
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|
1374 if (opts->code_end-opts->cur_code < ZMAX_NATIVE_SIZE) { |
235
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1375 if (opts->code_end-opts->cur_code < 5) { |
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1376 puts("out of code memory, not enough space for jmp to next chunk"); |
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1377 exit(1); |
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1378 } |
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1379 size_t size = 1024*1024; |
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1380 opts->cur_code = alloc_code(&size); |
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1381 opts->code_end = opts->cur_code + size; |
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1382 jmp(opts->cur_code, opts->cur_code); |
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1383 } |
255
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1384 if (address > 0x4000 && address < 0x8000) { |
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1385 opts->cur_code = xor_rr(opts->cur_code, RDI, RDI, SZ_D); |
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1386 opts->cur_code = call(opts->cur_code, (uint8_t *)exit); |
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1387 break; |
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1388 } |
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1389 uint8_t * existing = z80_get_native_address(context, address); |
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1390 if (existing) { |
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1391 opts->cur_code = jmp(opts->cur_code, existing); |
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1392 break; |
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1393 } |
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1394 next = z80_decode(encoded, &inst); |
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1395 z80_disasm(&inst, disbuf); |
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1396 if (inst.op == Z80_NOP) { |
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1397 printf("%X\t%s(%d)\n", address, disbuf, inst.immed); |
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1398 } else { |
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1399 printf("%X\t%s\n", address, disbuf); |
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1400 } |
248
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1401 uint8_t *after = translate_z80inst(&inst, opts->cur_code, context, address); |
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1402 z80_map_native_address(context, address, opts->cur_code, next-encoded, after - opts->cur_code); |
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1403 opts->cur_code = after; |
235
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1404 address += next-encoded; |
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1405 if (address > 0xFFFF) { |
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1406 address &= 0xFFFF; |
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1407 |
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1408 } else { |
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1409 encoded = next; |
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1410 } |
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1411 } while (!(inst.op == Z80_RET || inst.op == Z80_RETI || inst.op == Z80_RETN || inst.op == Z80_JP || (inst.op == Z80_NOP && inst.immed == 42))); |
235
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1412 process_deferred(&opts->deferred, context, (native_addr_func)z80_get_native_address); |
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1413 if (opts->deferred) { |
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1414 address = opts->deferred->address; |
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1415 printf("defferred address: %X\n", address); |
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1416 if (address < 0x4000) { |
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1417 encoded = context->mem_pointers[0] + (address & 0x1FFF); |
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1418 } else if (address > 0x8000 && context->mem_pointers[1]) { |
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1419 encoded = context->mem_pointers[1] + (address & 0x7FFF); |
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1420 } else { |
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1421 printf("attempt to translate non-memory address: %X\n", address); |
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1422 exit(1); |
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1423 } |
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1424 } else { |
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1425 encoded = NULL; |
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1426 } |
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1427 } |
213
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1428 } |
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1429 |
235
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1430 void init_x86_z80_opts(x86_z80_options * options) |
213
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1431 { |
235
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1432 options->flags = 0; |
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1433 options->regs[Z80_B] = BH; |
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1434 options->regs[Z80_C] = RBX; |
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1435 options->regs[Z80_D] = CH; |
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1436 options->regs[Z80_E] = RCX; |
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1437 options->regs[Z80_H] = AH; |
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1438 options->regs[Z80_L] = RAX; |
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1439 options->regs[Z80_IXH] = DH; |
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1440 options->regs[Z80_IXL] = RDX; |
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1441 options->regs[Z80_IYH] = -1; |
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1442 options->regs[Z80_IYL] = R8; |
235
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1443 options->regs[Z80_I] = -1; |
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1444 options->regs[Z80_R] = -1; |
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1445 options->regs[Z80_A] = R10; |
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1446 options->regs[Z80_BC] = RBX; |
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1447 options->regs[Z80_DE] = RCX; |
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1448 options->regs[Z80_HL] = RAX; |
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1449 options->regs[Z80_SP] = R9; |
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1450 options->regs[Z80_AF] = -1; |
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1451 options->regs[Z80_IX] = RDX; |
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1452 options->regs[Z80_IY] = R8; |
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1453 size_t size = 1024 * 1024; |
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1454 options->cur_code = alloc_code(&size); |
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1455 options->code_end = options->cur_code + size; |
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1456 options->ram_inst_sizes = malloc(sizeof(uint8_t) * 0x2000); |
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1457 memset(options->ram_inst_sizes, 0, sizeof(uint8_t) * 0x2000); |
235
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1458 options->deferred = NULL; |
213
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1459 } |
235
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1460 |
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1461 void init_z80_context(z80_context * context, x86_z80_options * options) |
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1462 { |
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1463 memset(context, 0, sizeof(*context)); |
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1464 context->static_code_map = malloc(sizeof(context->static_code_map)); |
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1465 context->static_code_map->base = NULL; |
235
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1466 context->static_code_map->offsets = malloc(sizeof(int32_t) * 0x2000); |
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1467 memset(context->static_code_map->offsets, 0xFF, sizeof(int32_t) * 0x2000); |
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1468 context->banked_code_map = malloc(sizeof(native_map_slot) * (1 << 9)); |
259
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1469 memset(context->banked_code_map, 0, sizeof(native_map_slot) * (1 << 9)); |
235
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1470 context->options = options; |
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1471 } |
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1472 |
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1473 void z80_reset(z80_context * context) |
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1474 { |
259
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1475 context->im = 0; |
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1476 context->iff1 = context->iff2 = 0; |
235
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1477 context->native_pc = z80_get_native_address_trans(context, 0); |
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1478 } |
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1479 |
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1480 |