Mercurial > repos > blastem
annotate vdp.c @ 474:e128e55710bd
Remove read pending stuff, that had been added in an attempt to fix CRAM/VSRAM undefined bit results. Set number of bits actually saved in VSRAM to 11
author | Mike Pavone <pavone@retrodev.com> |
---|---|
date | Sun, 15 Sep 2013 23:33:24 -0700 |
parents | 1358045c0bdd |
children | 50e0cb475294 |
rev | line source |
---|---|
467
140af5509ce7
Added copyright notice to source files and added GPL license text in COPYING
Mike Pavone <pavone@retrodev.com>
parents:
462
diff
changeset
|
1 /* |
140af5509ce7
Added copyright notice to source files and added GPL license text in COPYING
Mike Pavone <pavone@retrodev.com>
parents:
462
diff
changeset
|
2 Copyright 2013 Michael Pavone |
470
541c1ae8abf3
Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
3 This file is part of BlastEm. |
467
140af5509ce7
Added copyright notice to source files and added GPL license text in COPYING
Mike Pavone <pavone@retrodev.com>
parents:
462
diff
changeset
|
4 BlastEm is free software distributed under the terms of the GNU General Public License version 3 or greater. See COPYING for full license text. |
140af5509ce7
Added copyright notice to source files and added GPL license text in COPYING
Mike Pavone <pavone@retrodev.com>
parents:
462
diff
changeset
|
5 */ |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
6 #include "vdp.h" |
75 | 7 #include "blastem.h" |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
8 #include <stdlib.h> |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
9 #include <string.h> |
426
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
10 #include "render.h" |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
11 |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
12 #define NTSC_ACTIVE 225 |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
13 #define PAL_ACTIVE 241 |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
14 #define BUF_BIT_PRIORITY 0x40 |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
15 #define MAP_BIT_PRIORITY 0x8000 |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
16 #define MAP_BIT_H_FLIP 0x800 |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
17 #define MAP_BIT_V_FLIP 0x1000 |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
18 |
39
3c69319269ef
Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should
Mike Pavone <pavone@retrodev.com>
parents:
38
diff
changeset
|
19 #define SCROLL_BUFFER_SIZE 32 |
436
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
20 #define SCROLL_BUFFER_MASK (SCROLL_BUFFER_SIZE-1) |
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
21 #define SCROLL_BUFFER_DRAW (SCROLL_BUFFER_SIZE/2) |
39
3c69319269ef
Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should
Mike Pavone <pavone@retrodev.com>
parents:
38
diff
changeset
|
22 |
328
bf7ed23efa40
Fewer magic numbers in the VDP core for the win
Mike Pavone <pavone@retrodev.com>
parents:
327
diff
changeset
|
23 #define MCLKS_SLOT_H40 16 |
bf7ed23efa40
Fewer magic numbers in the VDP core for the win
Mike Pavone <pavone@retrodev.com>
parents:
327
diff
changeset
|
24 #define MCLKS_SLOT_H32 20 |
331
de17e0352f27
Fixup VINT cycle and HBLANK flag for the previous timing fixes
Mike Pavone <pavone@retrodev.com>
parents:
330
diff
changeset
|
25 #define VINT_CYCLE_H40 (21*MCLKS_SLOT_H40+332+9*MCLKS_SLOT_H40) //21 slots before HSYNC, 16 during, 10 after |
de17e0352f27
Fixup VINT cycle and HBLANK flag for the previous timing fixes
Mike Pavone <pavone@retrodev.com>
parents:
330
diff
changeset
|
26 #define VINT_CYCLE_H32 ((33+20+7)*MCLKS_SLOT_H32) //33 slots before HSYNC, 20 during, 7 after TODO: confirm final number |
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
27 #define HSYNC_SLOT_H40 21 |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
28 #define MCLK_WEIRD_END (HSYNC_SLOT_H40*MCLKS_SLOT_H40 + 332) |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
29 #define SLOT_WEIRD_END (HSYNC_SLOT_H40+17) |
331
de17e0352f27
Fixup VINT cycle and HBLANK flag for the previous timing fixes
Mike Pavone <pavone@retrodev.com>
parents:
330
diff
changeset
|
30 #define HSYNC_END_H32 (33 * MCLKS_SLOT_H32) |
de17e0352f27
Fixup VINT cycle and HBLANK flag for the previous timing fixes
Mike Pavone <pavone@retrodev.com>
parents:
330
diff
changeset
|
31 #define HBLANK_CLEAR_H40 (MCLK_WEIRD_END+61*4) |
de17e0352f27
Fixup VINT cycle and HBLANK flag for the previous timing fixes
Mike Pavone <pavone@retrodev.com>
parents:
330
diff
changeset
|
32 #define HBLANK_CLEAR_H32 (HSYNC_END_H32 + 46*5) |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
33 #define FIFO_LATENCY 3 |
328
bf7ed23efa40
Fewer magic numbers in the VDP core for the win
Mike Pavone <pavone@retrodev.com>
parents:
327
diff
changeset
|
34 |
426
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
35 int32_t color_map[1 << 12]; |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
36 uint8_t levels[] = {0, 27, 49, 71, 87, 103, 119, 130, 146, 157, 174, 190, 206, 228, 255}; |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
37 |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
38 uint8_t debug_base[][3] = { |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
39 {127, 127, 127}, //BG |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
40 {0, 0, 127}, //A |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
41 {127, 0, 0}, //Window |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
42 {0, 127, 0}, //B |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
43 {127, 0, 127} //Sprites |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
44 }; |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
45 |
426
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
46 uint8_t color_map_init_done; |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
47 |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
48 void init_vdp_context(vdp_context * context) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
49 { |
58
a6a19c45d358
Properly zero-init all VDP buffers. Comment out some debug printfs.
Mike Pavone <pavone@retrodev.com>
parents:
56
diff
changeset
|
50 memset(context, 0, sizeof(*context)); |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
51 context->vdpmem = malloc(VRAM_SIZE); |
58
a6a19c45d358
Properly zero-init all VDP buffers. Comment out some debug printfs.
Mike Pavone <pavone@retrodev.com>
parents:
56
diff
changeset
|
52 memset(context->vdpmem, 0, VRAM_SIZE); |
426
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
53 context->oddbuf = context->framebuf = malloc(FRAMEBUF_ENTRIES * (render_depth() / 8)); |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
54 memset(context->framebuf, 0, FRAMEBUF_ENTRIES * (render_depth() / 8)); |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
55 context->evenbuf = malloc(FRAMEBUF_ENTRIES * (render_depth() / 8)); |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
56 memset(context->evenbuf, 0, FRAMEBUF_ENTRIES * (render_depth() / 8)); |
39
3c69319269ef
Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should
Mike Pavone <pavone@retrodev.com>
parents:
38
diff
changeset
|
57 context->linebuf = malloc(LINEBUF_SIZE + SCROLL_BUFFER_SIZE*2); |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
58 memset(context->linebuf, 0, LINEBUF_SIZE + SCROLL_BUFFER_SIZE*2); |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
59 context->tmp_buf_a = context->linebuf + LINEBUF_SIZE; |
39
3c69319269ef
Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should
Mike Pavone <pavone@retrodev.com>
parents:
38
diff
changeset
|
60 context->tmp_buf_b = context->tmp_buf_a + SCROLL_BUFFER_SIZE; |
26
a7c2b92d8056
Fix management of context->sprite_draws so the sprite layer only draws when it should
Mike Pavone <pavone@retrodev.com>
parents:
25
diff
changeset
|
61 context->sprite_draws = MAX_DRAWS; |
471
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
62 context->fifo_write = 0; |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
63 context->fifo_read = -1; |
426
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
64 context->b32 = render_depth() == 32; |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
65 if (!color_map_init_done) { |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
66 uint8_t b,g,r; |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
67 for (uint16_t color = 0; color < (1 << 12); color++) { |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
68 if (color & FBUF_SHADOW) { |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
69 b = levels[(color >> 9) & 0x7]; |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
70 g = levels[(color >> 5) & 0x7]; |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
71 r = levels[(color >> 1) & 0x7]; |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
72 } else if(color & FBUF_HILIGHT) { |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
73 b = levels[((color >> 9) & 0x7) + 7]; |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
74 g = levels[((color >> 5) & 0x7) + 7]; |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
75 r = levels[((color >> 1) & 0x7) + 7]; |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
76 } else { |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
77 b = levels[(color >> 8) & 0xE]; |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
78 g = levels[(color >> 4) & 0xE]; |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
79 r = levels[color & 0xE]; |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
80 } |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
81 color_map[color] = render_map_color(r, g, b); |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
82 } |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
83 color_map_init_done = 1; |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
84 } |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
85 for (uint8_t color = 0; color < (1 << (3 + 1 + 1 + 1)); color++) |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
86 { |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
87 uint8_t src = color & DBG_SRC_MASK; |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
88 if (src > DBG_SRC_S) { |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
89 context->debugcolors[color] = 0; |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
90 } else { |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
91 uint8_t r,g,b; |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
92 b = debug_base[src][0]; |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
93 g = debug_base[src][1]; |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
94 r = debug_base[src][2]; |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
95 if (color & DBG_PRIORITY) |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
96 { |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
97 if (b) { |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
98 b += 48; |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
99 } |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
100 if (g) { |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
101 g += 48; |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
102 } |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
103 if (r) { |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
104 r += 48; |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
105 } |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
106 } |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
107 if (color & DBG_SHADOW) { |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
108 b /= 2; |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
109 g /= 2; |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
110 r /=2 ; |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
111 } |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
112 if (color & DBG_HILIGHT) { |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
113 if (b) { |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
114 b += 72; |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
115 } |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
116 if (g) { |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
117 g += 72; |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
118 } |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
119 if (r) { |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
120 r += 72; |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
121 } |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
122 } |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
123 context->debugcolors[color] = render_map_color(r, g, b); |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
124 } |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
125 } |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
126 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
127 |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
128 int is_refresh(vdp_context * context, uint32_t slot) |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
129 { |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
130 if (context->latched_mode & BIT_H40) { |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
131 return (slot == 37 || slot == 69 || slot == 102 || slot == 133 || slot == 165 || slot == 197 || slot >= 210); |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
132 } else { |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
133 //TODO: Figure out which slots are refresh when display is off in 32-cell mode |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
134 //These numbers are guesses based on H40 numbers |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
135 return (slot == 24 || slot == 56 || slot == 88 || slot == 120 || slot == 152); |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
136 //The numbers below are the refresh slots during active display |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
137 //return (slot == 66 || slot == 98 || slot == 130 || slot == 162); |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
138 } |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
139 } |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
140 |
21
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
141 void render_sprite_cells(vdp_context * context) |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
142 { |
21
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
143 if (context->cur_slot >= context->sprite_draws) { |
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
144 sprite_draw * d = context->sprite_draw_list + context->cur_slot; |
450
3758bcdae5de
Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty
Mike Pavone <pavone@retrodev.com>
parents:
438
diff
changeset
|
145 |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
146 uint16_t dir; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
147 int16_t x; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
148 if (d->h_flip) { |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
149 x = d->x_pos + 7; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
150 dir = -1; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
151 } else { |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
152 x = d->x_pos; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
153 dir = 1; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
154 } |
27
aa1c47fab3f1
Fix sprite transparency for overlapping sprites
Mike Pavone <pavone@retrodev.com>
parents:
26
diff
changeset
|
155 //printf("Draw Slot %d of %d, Rendering sprite cell from %X to x: %d\n", context->cur_slot, context->sprite_draws, d->address, x); |
26
a7c2b92d8056
Fix management of context->sprite_draws so the sprite layer only draws when it should
Mike Pavone <pavone@retrodev.com>
parents:
25
diff
changeset
|
156 context->cur_slot--; |
143
e5487ef04619
Fix infinite loop bug in sprite rendering
Mike Pavone <pavone@retrodev.com>
parents:
142
diff
changeset
|
157 for (uint16_t address = d->address; address != ((d->address+4) & 0xFFFF); address++) { |
27
aa1c47fab3f1
Fix sprite transparency for overlapping sprites
Mike Pavone <pavone@retrodev.com>
parents:
26
diff
changeset
|
158 if (x >= 0 && x < 320 && !(context->linebuf[x] & 0xF)) { |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
159 context->linebuf[x] = (context->vdpmem[address] >> 4) | d->pal_priority; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
160 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
161 x += dir; |
27
aa1c47fab3f1
Fix sprite transparency for overlapping sprites
Mike Pavone <pavone@retrodev.com>
parents:
26
diff
changeset
|
162 if (x >= 0 && x < 320 && !(context->linebuf[x] & 0xF)) { |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
163 context->linebuf[x] = (context->vdpmem[address] & 0xF) | d->pal_priority; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
164 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
165 x += dir; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
166 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
167 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
168 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
169 |
322
8e2fa485c0f2
Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview.
Mike Pavone <pavone@retrodev.com>
parents:
318
diff
changeset
|
170 void vdp_print_sprite_table(vdp_context * context) |
8e2fa485c0f2
Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview.
Mike Pavone <pavone@retrodev.com>
parents:
318
diff
changeset
|
171 { |
8e2fa485c0f2
Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview.
Mike Pavone <pavone@retrodev.com>
parents:
318
diff
changeset
|
172 uint16_t sat_address = (context->regs[REG_SAT] & 0x7F) << 9; |
8e2fa485c0f2
Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview.
Mike Pavone <pavone@retrodev.com>
parents:
318
diff
changeset
|
173 uint16_t current_index = 0; |
8e2fa485c0f2
Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview.
Mike Pavone <pavone@retrodev.com>
parents:
318
diff
changeset
|
174 uint8_t count = 0; |
8e2fa485c0f2
Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview.
Mike Pavone <pavone@retrodev.com>
parents:
318
diff
changeset
|
175 do { |
8e2fa485c0f2
Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview.
Mike Pavone <pavone@retrodev.com>
parents:
318
diff
changeset
|
176 uint16_t address = current_index * 8 + sat_address; |
8e2fa485c0f2
Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview.
Mike Pavone <pavone@retrodev.com>
parents:
318
diff
changeset
|
177 uint8_t height = ((context->vdpmem[address+2] & 0x3) + 1) * 8; |
8e2fa485c0f2
Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview.
Mike Pavone <pavone@retrodev.com>
parents:
318
diff
changeset
|
178 uint8_t width = (((context->vdpmem[address+2] >> 2) & 0x3) + 1) * 8; |
8e2fa485c0f2
Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview.
Mike Pavone <pavone@retrodev.com>
parents:
318
diff
changeset
|
179 int16_t y = ((context->vdpmem[address] & 0x3) << 8 | context->vdpmem[address+1]) & 0x1FF; |
323
8c01b4154480
Properly mask sprite X and Y coordinates
Mike Pavone <pavone@retrodev.com>
parents:
322
diff
changeset
|
180 int16_t x = ((context->vdpmem[address+ 6] & 0x3) << 8 | context->vdpmem[address + 7]) & 0x1FF; |
322
8e2fa485c0f2
Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview.
Mike Pavone <pavone@retrodev.com>
parents:
318
diff
changeset
|
181 uint16_t link = context->vdpmem[address+3] & 0x7F; |
323
8c01b4154480
Properly mask sprite X and Y coordinates
Mike Pavone <pavone@retrodev.com>
parents:
322
diff
changeset
|
182 uint8_t pal = context->vdpmem[address + 4] >> 5 & 0x3; |
8c01b4154480
Properly mask sprite X and Y coordinates
Mike Pavone <pavone@retrodev.com>
parents:
322
diff
changeset
|
183 uint8_t pri = context->vdpmem[address + 4] >> 7; |
450
3758bcdae5de
Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty
Mike Pavone <pavone@retrodev.com>
parents:
438
diff
changeset
|
184 uint16_t pattern = ((context->vdpmem[address + 4] << 8 | context->vdpmem[address + 5]) & 0x7FF) << 5; |
323
8c01b4154480
Properly mask sprite X and Y coordinates
Mike Pavone <pavone@retrodev.com>
parents:
322
diff
changeset
|
185 //printf("Sprite %d: X=%d(%d), Y=%d(%d), Width=%u, Height=%u, Link=%u, Pal=%u, Pri=%u, Pat=%X\n", current_index, x, x-128, y, y-128, width, height, link, pal, pri, pattern); |
322
8e2fa485c0f2
Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview.
Mike Pavone <pavone@retrodev.com>
parents:
318
diff
changeset
|
186 current_index = link; |
8e2fa485c0f2
Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview.
Mike Pavone <pavone@retrodev.com>
parents:
318
diff
changeset
|
187 count++; |
8e2fa485c0f2
Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview.
Mike Pavone <pavone@retrodev.com>
parents:
318
diff
changeset
|
188 } while (current_index != 0 && count < 80); |
8e2fa485c0f2
Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview.
Mike Pavone <pavone@retrodev.com>
parents:
318
diff
changeset
|
189 } |
8e2fa485c0f2
Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview.
Mike Pavone <pavone@retrodev.com>
parents:
318
diff
changeset
|
190 |
327
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
191 void vdp_print_reg_explain(vdp_context * context) |
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
192 { |
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
193 char * hscroll[] = {"full", "7-line", "cell", "line"}; |
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
194 printf("**Mode Group**\n" |
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
195 "00: %.2X | H-ints %s, Pal Select %d, HVC latch %s, Display gen %s\n" |
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
196 "01: %.2X | Display %s, V-ints %s, Height: %d, Mode %d\n" |
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
197 "0B: %.2X | E-ints %s, V-Scroll: %s, H-Scroll: %s\n" |
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
198 "0C: %.2X | Width: %d, Shadow/Highlight: %s\n", |
450
3758bcdae5de
Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty
Mike Pavone <pavone@retrodev.com>
parents:
438
diff
changeset
|
199 context->regs[REG_MODE_1], context->regs[REG_MODE_1] & BIT_HINT_EN ? "enabled" : "disabled", context->regs[REG_MODE_1] & BIT_PAL_SEL != 0, |
327
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
200 context->regs[REG_MODE_1] & BIT_HVC_LATCH ? "enabled" : "disabled", context->regs[REG_MODE_1] & BIT_DISP_DIS ? "disabled" : "enabled", |
450
3758bcdae5de
Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty
Mike Pavone <pavone@retrodev.com>
parents:
438
diff
changeset
|
201 context->regs[REG_MODE_2], context->regs[REG_MODE_2] & BIT_DISP_EN ? "enabled" : "disabled", context->regs[REG_MODE_2] & BIT_VINT_EN ? "enabled" : "disabled", |
327
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
202 context->regs[REG_MODE_2] & BIT_PAL ? 30 : 28, context->regs[REG_MODE_2] & BIT_MODE_5 ? 5 : 4, |
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
203 context->regs[REG_MODE_3], context->regs[REG_MODE_3] & BIT_EINT_EN ? "enabled" : "disabled", context->regs[REG_MODE_3] & BIT_VSCROLL ? "2 cell" : "full", |
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
204 hscroll[context->regs[REG_MODE_3] & 0x3], |
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
205 context->regs[REG_MODE_4], context->regs[REG_MODE_4] & BIT_H40 ? 40 : 32, context->regs[REG_MODE_4] & BIT_HILIGHT ? "enabled" : "disabled"); |
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
206 printf("\n**Table Group**\n" |
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
207 "02: %.2X | Scroll A Name Table: $%.4X\n" |
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
208 "03: %.2X | Window Name Table: $%.4X\n" |
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
209 "04: %.2X | Scroll B Name Table: $%.4X\n" |
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
210 "05: %.2X | Sprite Attribute Table: $%.4X\n" |
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
211 "0D: %.2X | HScroll Data Table: $%.4X\n", |
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
212 context->regs[REG_SCROLL_A], (context->regs[REG_SCROLL_A] & 0x38) << 10, |
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
213 context->regs[REG_WINDOW], (context->regs[REG_WINDOW] & (context->regs[REG_MODE_4] & BIT_H40 ? 0x3C : 0x3E)) << 10, |
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
214 context->regs[REG_SCROLL_B], (context->regs[REG_SCROLL_B] & 0x7) << 13, |
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
215 context->regs[REG_SAT], (context->regs[REG_SAT] & (context->regs[REG_MODE_4] & BIT_H40 ? 0x3E : 0x3F)) << 9, |
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
216 context->regs[REG_HSCROLL], (context->regs[REG_HSCROLL] & 0x1F) << 10); |
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
217 char * sizes[] = {"32", "64", "invalid", "128"}; |
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
218 printf("\n**Misc Group**\n" |
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
219 "07: %.2X | Backdrop Color: $%X\n" |
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
220 "0A: %.2X | H-Int Counter: %u\n" |
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
221 "0F: %.2X | Auto-increment: $%X\n" |
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
222 "10: %.2X | Scroll A/B Size: %sx%s\n", |
450
3758bcdae5de
Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty
Mike Pavone <pavone@retrodev.com>
parents:
438
diff
changeset
|
223 context->regs[REG_BG_COLOR], context->regs[REG_BG_COLOR] & 0x3F, |
3758bcdae5de
Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty
Mike Pavone <pavone@retrodev.com>
parents:
438
diff
changeset
|
224 context->regs[REG_HINT], context->regs[REG_HINT], |
327
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
225 context->regs[REG_AUTOINC], context->regs[REG_AUTOINC], |
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
226 context->regs[REG_SCROLL], sizes[context->regs[REG_SCROLL] & 0x3], sizes[context->regs[REG_SCROLL] >> 4 & 0x3]); |
438
b3cee2fe690b
Add address/cd registers to VDP debug message
Mike Pavone <pavone@retrodev.com>
parents:
437
diff
changeset
|
227 printf("\n**Internal Group**\n" |
b3cee2fe690b
Add address/cd registers to VDP debug message
Mike Pavone <pavone@retrodev.com>
parents:
437
diff
changeset
|
228 "Address: %X\n" |
b3cee2fe690b
Add address/cd registers to VDP debug message
Mike Pavone <pavone@retrodev.com>
parents:
437
diff
changeset
|
229 "CD: %X\n" |
b3cee2fe690b
Add address/cd registers to VDP debug message
Mike Pavone <pavone@retrodev.com>
parents:
437
diff
changeset
|
230 "Pending: %s\n", |
b3cee2fe690b
Add address/cd registers to VDP debug message
Mike Pavone <pavone@retrodev.com>
parents:
437
diff
changeset
|
231 context->address, context->cd, (context->flags & FLAG_PENDING) ? "true" : "false"); |
450
3758bcdae5de
Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty
Mike Pavone <pavone@retrodev.com>
parents:
438
diff
changeset
|
232 |
3758bcdae5de
Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty
Mike Pavone <pavone@retrodev.com>
parents:
438
diff
changeset
|
233 //TODO: Window Group, DMA Group |
327
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
234 } |
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
235 |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
236 void scan_sprite_table(uint32_t line, vdp_context * context) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
237 { |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
238 if (context->sprite_index && context->slot_counter) { |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
239 line += 1; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
240 line &= 0xFF; |
413
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
241 uint16_t ymask, ymin; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
242 uint8_t height_mult; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
243 if (context->double_res) { |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
244 line *= 2; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
245 if (context->framebuf != context->oddbuf) { |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
246 line++; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
247 } |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
248 ymask = 0x3FF; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
249 ymin = 256; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
250 height_mult = 16; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
251 } else { |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
252 ymask = 0x1FF; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
253 ymin = 128; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
254 height_mult = 8; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
255 } |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
256 context->sprite_index &= 0x7F; |
38
898e3d035f42
Implement sprite index >= sprite limit triggers sprite limit behavior
Mike Pavone <pavone@retrodev.com>
parents:
37
diff
changeset
|
257 if (context->latched_mode & BIT_H40) { |
898e3d035f42
Implement sprite index >= sprite limit triggers sprite limit behavior
Mike Pavone <pavone@retrodev.com>
parents:
37
diff
changeset
|
258 if (context->sprite_index >= MAX_SPRITES_FRAME) { |
898e3d035f42
Implement sprite index >= sprite limit triggers sprite limit behavior
Mike Pavone <pavone@retrodev.com>
parents:
37
diff
changeset
|
259 context->sprite_index = 0; |
898e3d035f42
Implement sprite index >= sprite limit triggers sprite limit behavior
Mike Pavone <pavone@retrodev.com>
parents:
37
diff
changeset
|
260 return; |
898e3d035f42
Implement sprite index >= sprite limit triggers sprite limit behavior
Mike Pavone <pavone@retrodev.com>
parents:
37
diff
changeset
|
261 } |
898e3d035f42
Implement sprite index >= sprite limit triggers sprite limit behavior
Mike Pavone <pavone@retrodev.com>
parents:
37
diff
changeset
|
262 } else if(context->sprite_index >= MAX_SPRITES_FRAME_H32) { |
898e3d035f42
Implement sprite index >= sprite limit triggers sprite limit behavior
Mike Pavone <pavone@retrodev.com>
parents:
37
diff
changeset
|
263 context->sprite_index = 0; |
898e3d035f42
Implement sprite index >= sprite limit triggers sprite limit behavior
Mike Pavone <pavone@retrodev.com>
parents:
37
diff
changeset
|
264 return; |
898e3d035f42
Implement sprite index >= sprite limit triggers sprite limit behavior
Mike Pavone <pavone@retrodev.com>
parents:
37
diff
changeset
|
265 } |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
266 //TODO: Read from SAT cache rather than from VRAM |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
267 uint16_t sat_address = (context->regs[REG_SAT] & 0x7F) << 9; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
268 uint16_t address = context->sprite_index * 8 + sat_address; |
413
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
269 line += ymin; |
415
8c60c8c09a0f
Fix sprite y mask in interlace mode. Fix framebuffer selection when switching out of interlace mode.
Mike Pavone <pavone@retrodev.com>
parents:
414
diff
changeset
|
270 uint16_t y = ((context->vdpmem[address] & 0x3) << 8 | context->vdpmem[address+1]) & ymask; |
413
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
271 uint8_t height = ((context->vdpmem[address+2] & 0x3) + 1) * height_mult; |
21
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
272 //printf("Sprite %d | y: %d, height: %d\n", context->sprite_index, y, height); |
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
273 if (y <= line && line < (y + height)) { |
27
aa1c47fab3f1
Fix sprite transparency for overlapping sprites
Mike Pavone <pavone@retrodev.com>
parents:
26
diff
changeset
|
274 //printf("Sprite %d at y: %d with height %d is on line %d\n", context->sprite_index, y, height, line); |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
275 context->sprite_info_list[--(context->slot_counter)].size = context->vdpmem[address+2]; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
276 context->sprite_info_list[context->slot_counter].index = context->sprite_index; |
413
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
277 context->sprite_info_list[context->slot_counter].y = y-ymin; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
278 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
279 context->sprite_index = context->vdpmem[address+3] & 0x7F; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
280 if (context->sprite_index && context->slot_counter) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
281 { |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
282 address = context->sprite_index * 8 + sat_address; |
415
8c60c8c09a0f
Fix sprite y mask in interlace mode. Fix framebuffer selection when switching out of interlace mode.
Mike Pavone <pavone@retrodev.com>
parents:
414
diff
changeset
|
283 y = ((context->vdpmem[address] & 0x3) << 8 | context->vdpmem[address+1]) & ymask; |
413
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
284 height = ((context->vdpmem[address+2] & 0x3) + 1) * height_mult; |
323
8c01b4154480
Properly mask sprite X and Y coordinates
Mike Pavone <pavone@retrodev.com>
parents:
322
diff
changeset
|
285 //printf("Sprite %d | y: %d, height: %d\n", context->sprite_index, y, height); |
21
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
286 if (y <= line && line < (y + height)) { |
27
aa1c47fab3f1
Fix sprite transparency for overlapping sprites
Mike Pavone <pavone@retrodev.com>
parents:
26
diff
changeset
|
287 //printf("Sprite %d at y: %d with height %d is on line %d\n", context->sprite_index, y, height, line); |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
288 context->sprite_info_list[--(context->slot_counter)].size = context->vdpmem[address+2]; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
289 context->sprite_info_list[context->slot_counter].index = context->sprite_index; |
413
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
290 context->sprite_info_list[context->slot_counter].y = y-ymin; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
291 } |
21
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
292 context->sprite_index = context->vdpmem[address+3] & 0x7F; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
293 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
294 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
295 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
296 |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
297 void read_sprite_x(uint32_t line, vdp_context * context) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
298 { |
34
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
299 if (context->cur_slot >= context->slot_counter) { |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
300 if (context->sprite_draws) { |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
301 line += 1; |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
302 line &= 0xFF; |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
303 //in tiles |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
304 uint8_t width = ((context->sprite_info_list[context->cur_slot].size >> 2) & 0x3) + 1; |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
305 //in pixels |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
306 uint8_t height = ((context->sprite_info_list[context->cur_slot].size & 0x3) + 1) * 8; |
413
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
307 if (context->double_res) { |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
308 line *= 2; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
309 if (context->framebuf != context->oddbuf) { |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
310 line++; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
311 } |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
312 height *= 2; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
313 } |
34
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
314 uint16_t att_addr = ((context->regs[REG_SAT] & 0x7F) << 9) + context->sprite_info_list[context->cur_slot].index * 8 + 4; |
450
3758bcdae5de
Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty
Mike Pavone <pavone@retrodev.com>
parents:
438
diff
changeset
|
315 uint16_t tileinfo = (context->vdpmem[att_addr] << 8) | context->vdpmem[att_addr+1]; |
34
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
316 uint8_t pal_priority = (tileinfo >> 9) & 0x70; |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
317 uint8_t row; |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
318 if (tileinfo & MAP_BIT_V_FLIP) { |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
319 row = (context->sprite_info_list[context->cur_slot].y + height - 1) - line; |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
320 } else { |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
321 row = line-context->sprite_info_list[context->cur_slot].y; |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
322 } |
413
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
323 uint16_t address; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
324 if (context->double_res) { |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
325 address = ((tileinfo & 0x3FF) << 6) + row * 4; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
326 } else { |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
327 address = ((tileinfo & 0x7FF) << 5) + row * 4; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
328 } |
323
8c01b4154480
Properly mask sprite X and Y coordinates
Mike Pavone <pavone@retrodev.com>
parents:
322
diff
changeset
|
329 int16_t x = ((context->vdpmem[att_addr+ 2] & 0x3) << 8 | context->vdpmem[att_addr + 3]) & 0x1FF; |
36
04672c060062
Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents:
35
diff
changeset
|
330 if (x) { |
04672c060062
Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents:
35
diff
changeset
|
331 context->flags |= FLAG_CAN_MASK; |
04672c060062
Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents:
35
diff
changeset
|
332 } else if(context->flags & (FLAG_CAN_MASK | FLAG_DOT_OFLOW)) { |
04672c060062
Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents:
35
diff
changeset
|
333 context->flags |= FLAG_MASKED; |
04672c060062
Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents:
35
diff
changeset
|
334 } |
450
3758bcdae5de
Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty
Mike Pavone <pavone@retrodev.com>
parents:
438
diff
changeset
|
335 |
36
04672c060062
Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents:
35
diff
changeset
|
336 context->flags &= ~FLAG_DOT_OFLOW; |
04672c060062
Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents:
35
diff
changeset
|
337 int16_t i; |
04672c060062
Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents:
35
diff
changeset
|
338 if (context->flags & FLAG_MASKED) { |
04672c060062
Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents:
35
diff
changeset
|
339 for (i=0; i < width && context->sprite_draws; i++) { |
04672c060062
Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents:
35
diff
changeset
|
340 --context->sprite_draws; |
04672c060062
Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents:
35
diff
changeset
|
341 context->sprite_draw_list[context->sprite_draws].x_pos = -128; |
34
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
342 } |
36
04672c060062
Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents:
35
diff
changeset
|
343 } else { |
34
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
344 x -= 128; |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
345 int16_t base_x = x; |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
346 int16_t dir; |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
347 if (tileinfo & MAP_BIT_H_FLIP) { |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
348 x += (width-1) * 8; |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
349 dir = -8; |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
350 } else { |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
351 dir = 8; |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
352 } |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
353 //printf("Sprite %d | x: %d, y: %d, width: %d, height: %d, pal_priority: %X, row: %d, tile addr: %X\n", context->sprite_info_list[context->cur_slot].index, x, context->sprite_info_list[context->cur_slot].y, width, height, pal_priority, row, address); |
35
233c7737c152
Small fix to overflow flag
Mike Pavone <pavone@retrodev.com>
parents:
34
diff
changeset
|
354 for (i=0; i < width && context->sprite_draws; i++, x += dir) { |
34
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
355 --context->sprite_draws; |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
356 context->sprite_draw_list[context->sprite_draws].address = address + i * height * 4; |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
357 context->sprite_draw_list[context->sprite_draws].x_pos = x; |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
358 context->sprite_draw_list[context->sprite_draws].pal_priority = pal_priority; |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
359 context->sprite_draw_list[context->sprite_draws].h_flip = (tileinfo & MAP_BIT_H_FLIP) ? 1 : 0; |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
360 } |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
361 } |
36
04672c060062
Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents:
35
diff
changeset
|
362 if (i < width) { |
04672c060062
Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents:
35
diff
changeset
|
363 context->flags |= FLAG_DOT_OFLOW; |
04672c060062
Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents:
35
diff
changeset
|
364 } |
04672c060062
Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents:
35
diff
changeset
|
365 context->cur_slot--; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
366 } else { |
34
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
367 context->flags |= FLAG_DOT_OFLOW; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
368 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
369 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
370 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
371 |
427
2802318c14e1
Refactor duplicated CRAM writing code and fix a bug in the process
Mike Pavone <pavone@retrodev.com>
parents:
426
diff
changeset
|
372 void write_cram(vdp_context * context, uint16_t address, uint16_t value) |
2802318c14e1
Refactor duplicated CRAM writing code and fix a bug in the process
Mike Pavone <pavone@retrodev.com>
parents:
426
diff
changeset
|
373 { |
2802318c14e1
Refactor duplicated CRAM writing code and fix a bug in the process
Mike Pavone <pavone@retrodev.com>
parents:
426
diff
changeset
|
374 uint16_t addr = (address/2) & (CRAM_SIZE-1); |
2802318c14e1
Refactor duplicated CRAM writing code and fix a bug in the process
Mike Pavone <pavone@retrodev.com>
parents:
426
diff
changeset
|
375 context->cram[addr] = value; |
2802318c14e1
Refactor duplicated CRAM writing code and fix a bug in the process
Mike Pavone <pavone@retrodev.com>
parents:
426
diff
changeset
|
376 context->colors[addr] = color_map[value & 0xEEE]; |
2802318c14e1
Refactor duplicated CRAM writing code and fix a bug in the process
Mike Pavone <pavone@retrodev.com>
parents:
426
diff
changeset
|
377 context->colors[addr + CRAM_SIZE] = color_map[(value & 0xEEE) | FBUF_SHADOW]; |
2802318c14e1
Refactor duplicated CRAM writing code and fix a bug in the process
Mike Pavone <pavone@retrodev.com>
parents:
426
diff
changeset
|
378 context->colors[addr + CRAM_SIZE*2] = color_map[(value & 0xEEE) | FBUF_HILIGHT]; |
2802318c14e1
Refactor duplicated CRAM writing code and fix a bug in the process
Mike Pavone <pavone@retrodev.com>
parents:
426
diff
changeset
|
379 } |
2802318c14e1
Refactor duplicated CRAM writing code and fix a bug in the process
Mike Pavone <pavone@retrodev.com>
parents:
426
diff
changeset
|
380 |
473
1358045c0bdd
Implement undocumented 8-bit VRAM read
Mike Pavone <pavone@retrodev.com>
parents:
472
diff
changeset
|
381 #define VRAM_READ 0 //0000 |
1358045c0bdd
Implement undocumented 8-bit VRAM read
Mike Pavone <pavone@retrodev.com>
parents:
472
diff
changeset
|
382 #define VRAM_WRITE 1 //0001 |
1358045c0bdd
Implement undocumented 8-bit VRAM read
Mike Pavone <pavone@retrodev.com>
parents:
472
diff
changeset
|
383 //2 would trigger register write 0010 |
1358045c0bdd
Implement undocumented 8-bit VRAM read
Mike Pavone <pavone@retrodev.com>
parents:
472
diff
changeset
|
384 #define CRAM_WRITE 3 //0011 |
1358045c0bdd
Implement undocumented 8-bit VRAM read
Mike Pavone <pavone@retrodev.com>
parents:
472
diff
changeset
|
385 #define VSRAM_READ 4 //0100 |
1358045c0bdd
Implement undocumented 8-bit VRAM read
Mike Pavone <pavone@retrodev.com>
parents:
472
diff
changeset
|
386 #define VSRAM_WRITE 5//0101 |
1358045c0bdd
Implement undocumented 8-bit VRAM read
Mike Pavone <pavone@retrodev.com>
parents:
472
diff
changeset
|
387 //6 would trigger regsiter write 0110 |
1358045c0bdd
Implement undocumented 8-bit VRAM read
Mike Pavone <pavone@retrodev.com>
parents:
472
diff
changeset
|
388 //7 is a mystery |
1358045c0bdd
Implement undocumented 8-bit VRAM read
Mike Pavone <pavone@retrodev.com>
parents:
472
diff
changeset
|
389 #define CRAM_READ 8 //1000 |
1358045c0bdd
Implement undocumented 8-bit VRAM read
Mike Pavone <pavone@retrodev.com>
parents:
472
diff
changeset
|
390 //9 is also a mystery //1001 |
1358045c0bdd
Implement undocumented 8-bit VRAM read
Mike Pavone <pavone@retrodev.com>
parents:
472
diff
changeset
|
391 //A would trigger register write 1010 |
1358045c0bdd
Implement undocumented 8-bit VRAM read
Mike Pavone <pavone@retrodev.com>
parents:
472
diff
changeset
|
392 //B is a mystery 1011 |
1358045c0bdd
Implement undocumented 8-bit VRAM read
Mike Pavone <pavone@retrodev.com>
parents:
472
diff
changeset
|
393 #define VRAM_READ8 0xC //1100 |
1358045c0bdd
Implement undocumented 8-bit VRAM read
Mike Pavone <pavone@retrodev.com>
parents:
472
diff
changeset
|
394 //D is a mystery 1101 |
1358045c0bdd
Implement undocumented 8-bit VRAM read
Mike Pavone <pavone@retrodev.com>
parents:
472
diff
changeset
|
395 //E would trigger register write 1110 |
1358045c0bdd
Implement undocumented 8-bit VRAM read
Mike Pavone <pavone@retrodev.com>
parents:
472
diff
changeset
|
396 //F is a mystery 1111 |
75 | 397 #define DMA_START 0x20 |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
398 |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
399 void external_slot(vdp_context * context) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
400 { |
471
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
401 fifo_entry * start = context->fifo + context->fifo_read; |
474
e128e55710bd
Remove read pending stuff, that had been added in an attempt to fix CRAM/VSRAM undefined bit results. Set number of bits actually saved in VSRAM to 11
Mike Pavone <pavone@retrodev.com>
parents:
473
diff
changeset
|
402 /*if (context->flags2 & FLAG2_READ_PENDING) { |
470
541c1ae8abf3
Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
403 context->flags2 &= ~FLAG2_READ_PENDING; |
541c1ae8abf3
Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
404 context->flags |= FLAG_UNUSED_SLOT; |
541c1ae8abf3
Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
405 return; |
474
e128e55710bd
Remove read pending stuff, that had been added in an attempt to fix CRAM/VSRAM undefined bit results. Set number of bits actually saved in VSRAM to 11
Mike Pavone <pavone@retrodev.com>
parents:
473
diff
changeset
|
406 }*/ |
471
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
407 if (context->fifo_read >= 0 && start->cycle <= context->cycles) { |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
408 switch (start->cd & 0xF) |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
409 { |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
410 case VRAM_WRITE: |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
411 if (start->partial) { |
471
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
412 //printf("VRAM Write: %X to %X at %d (line %d, slot %d)\n", start->value, start->address ^ 1, context->cycles, context->cycles/MCLKS_LINE, (context->cycles%MCLKS_LINE)/16); |
470
541c1ae8abf3
Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
413 context->last_fifo_val = start->value; |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
414 context->vdpmem[start->address ^ 1] = start->value; |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
415 } else { |
471
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
416 //printf("VRAM Write High: %X to %X at %d (line %d, slot %d)\n", start->value >> 8, start->address, context->cycles, context->cycles/MCLKS_LINE, (context->cycles%MCLKS_LINE)/16); |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
417 context->vdpmem[start->address] = start->value >> 8; |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
418 start->partial = 1; |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
419 //skip auto-increment and removal of entry from fifo |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
420 return; |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
421 } |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
422 break; |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
423 case CRAM_WRITE: { |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
424 //printf("CRAM Write | %X to %X\n", start->value, (start->address/2) & (CRAM_SIZE-1)); |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
425 write_cram(context, start->address, start->value); |
470
541c1ae8abf3
Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
426 context->last_fifo_val = start->value; |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
427 break; |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
428 } |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
429 case VSRAM_WRITE: |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
430 if (((start->address/2) & 63) < VSRAM_SIZE) { |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
431 //printf("VSRAM Write: %X to %X\n", start->value, context->address); |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
432 context->vsram[(start->address/2) & 63] = start->value; |
470
541c1ae8abf3
Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
433 context->last_fifo_val = start->value; |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
434 } |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
435 |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
436 break; |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
437 } |
471
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
438 context->fifo_read = (context->fifo_read+1) & (FIFO_SIZE-1); |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
439 if (context->fifo_read == context->fifo_write) { |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
440 context->fifo_read = -1; |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
441 } |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
442 } else { |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
443 context->flags |= FLAG_UNUSED_SLOT; |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
444 } |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
445 } |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
446 |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
447 void run_dma_src(vdp_context * context, uint32_t slot) |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
448 { |
75 | 449 //TODO: Figure out what happens if CD bit 4 is not set in DMA copy mode |
450 //TODO: Figure out what happens when CD:0-3 is not set to a write mode in DMA operations | |
451 //TODO: Figure out what happens if DMA gets disabled part way through a DMA fill or DMA copy | |
471
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
452 if (context->fifo_write == context->fifo_read) { |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
453 return; |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
454 } |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
455 uint16_t read_val; |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
456 uint8_t ran_source = 0, partial = 0; |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
457 uint16_t dma_len; |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
458 switch(context->regs[REG_DMASRC_H] & 0xC0) |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
459 { |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
460 //68K -> VDP |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
461 case 0: |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
462 case 0x40: |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
463 if (!slot || !is_refresh(context, slot-1)) { |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
464 read_val = read_dma_value((context->regs[REG_DMASRC_H] << 16) | (context->regs[REG_DMASRC_M] << 8) | context->regs[REG_DMASRC_L]); |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
465 ran_source = 1; |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
466 } |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
467 break; |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
468 //Copy |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
469 case 0xC0: |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
470 if (context->flags & FLAG_UNUSED_SLOT) { |
131
8fc8e46be691
Fix bug that was causing DMA fills to lock up under certain circumstances
Mike Pavone <pavone@retrodev.com>
parents:
109
diff
changeset
|
471 switch(context->dma_cd & 0xF) |
75 | 472 { |
473 case VRAM_WRITE: | |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
474 read_val = context->vdpmem[(context->regs[REG_DMASRC_M] << 8) | context->regs[REG_DMASRC_L]]; |
75 | 475 break; |
427
2802318c14e1
Refactor duplicated CRAM writing code and fix a bug in the process
Mike Pavone <pavone@retrodev.com>
parents:
426
diff
changeset
|
476 case CRAM_WRITE: |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
477 read_val = context->cram[context->regs[REG_DMASRC_L] & (CRAM_SIZE-1)]; |
75 | 478 break; |
479 case VSRAM_WRITE: | |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
480 if ((context->regs[REG_DMASRC_L] & 63) < VSRAM_SIZE) { |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
481 read_val = context->vsram[context->regs[REG_DMASRC_L] & 63]; |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
482 } else { |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
483 read_val = 0; |
75 | 484 } |
485 break; | |
486 } | |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
487 ran_source = 1; |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
488 context->flags &= ~FLAG_UNUSED_SLOT; |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
489 } |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
490 break; |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
491 case 0x80: |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
492 read_val = (context->cd & 0xF) == VRAM_WRITE ? context->last_write_val >> 8 : context->last_write_val; |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
493 partial = 1; |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
494 ran_source = 1; |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
495 break; |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
496 } |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
497 |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
498 if (ran_source) { |
471
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
499 fifo_entry * cur = context->fifo + context->fifo_write; |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
500 cur->cycle = context->cycles + ((context->latched_mode & BIT_H40) ? 16 : 20)*FIFO_LATENCY; |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
501 cur->address = context->address; |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
502 cur->value = read_val; |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
503 cur->cd = context->cd; |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
504 cur->partial = partial; |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
505 if (context->fifo_read < 0) { |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
506 context->fifo_read = context->fifo_write; |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
507 } |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
508 context->fifo_write = (context->fifo_write+1) & (FIFO_SIZE-1); |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
509 context->regs[REG_DMASRC_L] += 1; |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
510 if (!context->regs[REG_DMASRC_L]) { |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
511 context->regs[REG_DMASRC_M] += 1; |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
512 } |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
513 context->address += context->regs[REG_AUTOINC]; |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
514 dma_len = ((context->regs[REG_DMALEN_H] << 8) | context->regs[REG_DMALEN_L]) - 1; |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
515 context->regs[REG_DMALEN_H] = dma_len >> 8; |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
516 context->regs[REG_DMALEN_L] = dma_len; |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
517 if (!dma_len) { |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
518 //printf("DMA end at cycle %d\n", context->cycles); |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
519 context->flags &= ~FLAG_DMA_RUN; |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
520 context->cd &= 0xF; |
75 | 521 } |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
522 } |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
523 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
524 |
40 | 525 #define WINDOW_RIGHT 0x80 |
526 #define WINDOW_DOWN 0x80 | |
527 | |
25
4d0c20ad815a
Fix vertical scroll value for plane B
Mike Pavone <pavone@retrodev.com>
parents:
24
diff
changeset
|
528 void read_map_scroll(uint16_t column, uint16_t vsram_off, uint32_t line, uint16_t address, uint16_t hscroll_val, vdp_context * context) |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
529 { |
417
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
415
diff
changeset
|
530 uint16_t window_line_shift, v_offset_mask, vscroll_shift; |
414
51ee0f117365
Fix vscroll calculation in double resultion interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
413
diff
changeset
|
531 if (context->double_res) { |
413
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
532 line *= 2; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
533 if (context->framebuf != context->oddbuf) { |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
534 line++; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
535 } |
417
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
415
diff
changeset
|
536 window_line_shift = 4; |
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
415
diff
changeset
|
537 v_offset_mask = 0xF; |
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
415
diff
changeset
|
538 vscroll_shift = 4; |
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
415
diff
changeset
|
539 } else { |
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
415
diff
changeset
|
540 window_line_shift = 3; |
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
415
diff
changeset
|
541 v_offset_mask = 0x7; |
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
415
diff
changeset
|
542 vscroll_shift = 3; |
414
51ee0f117365
Fix vscroll calculation in double resultion interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
413
diff
changeset
|
543 } |
40 | 544 if (!vsram_off) { |
545 uint16_t left_col, right_col; | |
546 if (context->regs[REG_WINDOW_H] & WINDOW_RIGHT) { | |
41
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
547 left_col = (context->regs[REG_WINDOW_H] & 0x1F) * 2; |
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
548 right_col = 42; |
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
549 } else { |
40 | 550 left_col = 0; |
551 right_col = (context->regs[REG_WINDOW_H] & 0x1F) * 2; | |
552 if (right_col) { | |
553 right_col += 2; | |
554 } | |
555 } | |
41
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
556 uint16_t top_line, bottom_line; |
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
557 if (context->regs[REG_WINDOW_V] & WINDOW_DOWN) { |
417
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
415
diff
changeset
|
558 top_line = (context->regs[REG_WINDOW_V] & 0x1F) << window_line_shift; |
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
415
diff
changeset
|
559 bottom_line = context->double_res ? 481 : 241; |
41
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
560 } else { |
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
561 top_line = 0; |
417
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
415
diff
changeset
|
562 bottom_line = (context->regs[REG_WINDOW_V] & 0x1F) << window_line_shift; |
41
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
563 } |
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
564 if ((column >= left_col && column < right_col) || (line >= top_line && line < bottom_line)) { |
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
565 uint16_t address = context->regs[REG_WINDOW] << 10; |
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
566 uint16_t line_offset, offset, mask; |
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
567 if (context->latched_mode & BIT_H40) { |
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
568 address &= 0xF000; |
417
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
415
diff
changeset
|
569 line_offset = (((line) >> vscroll_shift) * 64 * 2) & 0xFFF; |
41
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
570 mask = 0x7F; |
450
3758bcdae5de
Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty
Mike Pavone <pavone@retrodev.com>
parents:
438
diff
changeset
|
571 |
41
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
572 } else { |
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
573 address &= 0xF800; |
417
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
415
diff
changeset
|
574 line_offset = (((line) >> vscroll_shift) * 32 * 2) & 0xFFF; |
41
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
575 mask = 0x3F; |
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
576 } |
417
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
415
diff
changeset
|
577 if (context->double_res) { |
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
415
diff
changeset
|
578 mask <<= 1; |
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
415
diff
changeset
|
579 mask |= 1; |
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
415
diff
changeset
|
580 } |
42
6653e67a6811
Fix bug in tile address masking. Remove some debug code from window plane.
Mike Pavone <pavone@retrodev.com>
parents:
41
diff
changeset
|
581 offset = address + line_offset + (((column - 2) * 2) & mask); |
41
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
582 context->col_1 = (context->vdpmem[offset] << 8) | context->vdpmem[offset+1]; |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
583 //printf("Window | top: %d, bot: %d, left: %d, right: %d, base: %X, line: %X offset: %X, tile: %X, reg: %X\n", top_line, bottom_line, left_col, right_col, address, line_offset, offset, ((context->col_1 & 0x3FF) << 5), context->regs[REG_WINDOW]); |
42
6653e67a6811
Fix bug in tile address masking. Remove some debug code from window plane.
Mike Pavone <pavone@retrodev.com>
parents:
41
diff
changeset
|
584 offset = address + line_offset + (((column - 1) * 2) & mask); |
41
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
585 context->col_2 = (context->vdpmem[offset] << 8) | context->vdpmem[offset+1]; |
417
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
415
diff
changeset
|
586 context->v_offset = (line) & v_offset_mask; |
41
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
587 context->flags |= FLAG_WINDOW; |
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
588 return; |
40 | 589 } |
590 context->flags &= ~FLAG_WINDOW; | |
591 } | |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
592 uint16_t vscroll; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
593 switch(context->regs[REG_SCROLL] & 0x30) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
594 { |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
595 case 0: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
596 vscroll = 0xFF; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
597 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
598 case 0x10: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
599 vscroll = 0x1FF; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
600 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
601 case 0x20: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
602 //TODO: Verify this behavior |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
603 vscroll = 0; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
604 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
605 case 0x30: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
606 vscroll = 0x3FF; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
607 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
608 } |
414
51ee0f117365
Fix vscroll calculation in double resultion interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
413
diff
changeset
|
609 if (context->double_res) { |
413
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
610 vscroll <<= 1; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
611 vscroll |= 1; |
414
51ee0f117365
Fix vscroll calculation in double resultion interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
413
diff
changeset
|
612 } |
454
e9b6fe443bf2
Fix per-column scrolling bug
Mike Pavone <pavone@retrodev.com>
parents:
453
diff
changeset
|
613 vscroll &= (context->vsram[(context->regs[REG_MODE_3] & BIT_VSCROLL ? (column-2)&63 : 0) + vsram_off] + line); |
414
51ee0f117365
Fix vscroll calculation in double resultion interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
413
diff
changeset
|
614 context->v_offset = vscroll & v_offset_mask; |
26
a7c2b92d8056
Fix management of context->sprite_draws so the sprite layer only draws when it should
Mike Pavone <pavone@retrodev.com>
parents:
25
diff
changeset
|
615 //printf("%s | line %d, vsram: %d, vscroll: %d, v_offset: %d\n",(vsram_off ? "B" : "A"), line, context->vsram[context->regs[REG_MODE_3] & 0x4 ? column : 0], vscroll, context->v_offset); |
414
51ee0f117365
Fix vscroll calculation in double resultion interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
413
diff
changeset
|
616 vscroll >>= vscroll_shift; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
617 uint16_t hscroll_mask; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
618 uint16_t v_mul; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
619 switch(context->regs[REG_SCROLL] & 0x3) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
620 { |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
621 case 0: |
108
1a551a85cb06
Fix horizontal mask values for scroll plane map address calculation
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
622 hscroll_mask = 0x1F; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
623 v_mul = 64; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
624 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
625 case 0x1: |
39
3c69319269ef
Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should
Mike Pavone <pavone@retrodev.com>
parents:
38
diff
changeset
|
626 hscroll_mask = 0x3F; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
627 v_mul = 128; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
628 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
629 case 0x2: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
630 //TODO: Verify this behavior |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
631 hscroll_mask = 0; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
632 v_mul = 0; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
633 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
634 case 0x3: |
108
1a551a85cb06
Fix horizontal mask values for scroll plane map address calculation
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
635 hscroll_mask = 0x7F; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
636 v_mul = 256; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
637 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
638 } |
28 | 639 uint16_t hscroll, offset; |
640 for (int i = 0; i < 2; i++) { | |
39
3c69319269ef
Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should
Mike Pavone <pavone@retrodev.com>
parents:
38
diff
changeset
|
641 hscroll = (column - 2 + i - ((hscroll_val/8) & 0xFFFE)) & hscroll_mask; |
3c69319269ef
Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should
Mike Pavone <pavone@retrodev.com>
parents:
38
diff
changeset
|
642 offset = address + ((vscroll * v_mul + hscroll*2) & 0x1FFF); |
3c69319269ef
Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should
Mike Pavone <pavone@retrodev.com>
parents:
38
diff
changeset
|
643 //printf("%s | line: %d, col: %d, x: %d, hs_mask %X, scr reg: %X, tbl addr: %X\n", (vsram_off ? "B" : "A"), line, (column-2+i), hscroll, hscroll_mask, context->regs[REG_SCROLL], offset); |
28 | 644 uint16_t col_val = (context->vdpmem[offset] << 8) | context->vdpmem[offset+1]; |
645 if (i) { | |
646 context->col_2 = col_val; | |
647 } else { | |
648 context->col_1 = col_val; | |
649 } | |
650 } | |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
651 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
652 |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
653 void read_map_scroll_a(uint16_t column, uint32_t line, vdp_context * context) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
654 { |
25
4d0c20ad815a
Fix vertical scroll value for plane B
Mike Pavone <pavone@retrodev.com>
parents:
24
diff
changeset
|
655 read_map_scroll(column, 0, line, (context->regs[REG_SCROLL_A] & 0x38) << 10, context->hscroll_a, context); |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
656 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
657 |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
658 void read_map_scroll_b(uint16_t column, uint32_t line, vdp_context * context) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
659 { |
25
4d0c20ad815a
Fix vertical scroll value for plane B
Mike Pavone <pavone@retrodev.com>
parents:
24
diff
changeset
|
660 read_map_scroll(column, 1, line, (context->regs[REG_SCROLL_B] & 0x7) << 13, context->hscroll_b, context); |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
661 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
662 |
436
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
663 void render_map(uint16_t col, uint8_t * tmp_buf, uint8_t offset, vdp_context * context) |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
664 { |
413
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
665 uint16_t address; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
666 uint8_t shift, add; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
667 if (context->double_res) { |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
668 address = ((col & 0x3FF) << 6); |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
669 shift = 1; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
670 add = context->framebuf != context->oddbuf ? 1 : 0; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
671 } else { |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
672 address = ((col & 0x7FF) << 5); |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
673 shift = 0; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
674 add = 0; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
675 } |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
676 if (col & MAP_BIT_V_FLIP) { |
414
51ee0f117365
Fix vscroll calculation in double resultion interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
413
diff
changeset
|
677 address += 28 - 4 * context->v_offset/*((context->v_offset << shift) + add)*/; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
678 } else { |
414
51ee0f117365
Fix vscroll calculation in double resultion interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
413
diff
changeset
|
679 address += 4 * context->v_offset/*((context->v_offset << shift) + add)*/; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
680 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
681 uint16_t pal_priority = (col >> 9) & 0x70; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
682 int32_t dir; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
683 if (col & MAP_BIT_H_FLIP) { |
436
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
684 offset += 7; |
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
685 offset &= SCROLL_BUFFER_MASK; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
686 dir = -1; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
687 } else { |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
688 dir = 1; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
689 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
690 for (uint32_t i=0; i < 4; i++, address++) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
691 { |
436
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
692 tmp_buf[offset] = pal_priority | (context->vdpmem[address] >> 4); |
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
693 offset += dir; |
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
694 offset &= SCROLL_BUFFER_MASK; |
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
695 tmp_buf[offset] = pal_priority | (context->vdpmem[address] & 0xF); |
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
696 offset += dir; |
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
697 offset &= SCROLL_BUFFER_MASK; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
698 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
699 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
700 |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
701 void render_map_1(vdp_context * context) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
702 { |
436
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
703 render_map(context->col_1, context->tmp_buf_a, context->buf_a_off, context); |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
704 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
705 |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
706 void render_map_2(vdp_context * context) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
707 { |
436
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
708 render_map(context->col_2, context->tmp_buf_a, context->buf_a_off+8, context); |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
709 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
710 |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
711 void render_map_3(vdp_context * context) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
712 { |
436
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
713 render_map(context->col_1, context->tmp_buf_b, context->buf_b_off, context); |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
714 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
715 |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
716 void render_map_output(uint32_t line, int32_t col, vdp_context * context) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
717 { |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
718 if (line >= 240) { |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
719 return; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
720 } |
436
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
721 render_map(context->col_2, context->tmp_buf_b, context->buf_b_off+8, context); |
426
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
722 uint16_t *dst; |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
723 uint32_t *dst32; |
436
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
724 uint8_t *sprite_buf, *plane_a, *plane_b; |
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
725 int plane_a_off, plane_b_off; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
726 if (col) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
727 { |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
728 col-=2; |
426
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
729 if (context->b32) { |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
730 dst32 = context->framebuf; |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
731 dst32 += line * 320 + col * 8; |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
732 } else { |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
733 dst = context->framebuf; |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
734 dst += line * 320 + col * 8; |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
735 } |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
736 sprite_buf = context->linebuf + col * 8; |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
737 uint8_t a_src, src; |
40 | 738 if (context->flags & FLAG_WINDOW) { |
436
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
739 plane_a_off = context->buf_a_off; |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
740 a_src = DBG_SRC_W; |
40 | 741 } else { |
436
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
742 plane_a_off = context->buf_a_off - (context->hscroll_a & 0xF); |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
743 a_src = DBG_SRC_A; |
40 | 744 } |
436
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
745 plane_b_off = context->buf_b_off - (context->hscroll_b & 0xF); |
30 | 746 //printf("A | tmp_buf offset: %d\n", 8 - (context->hscroll_a & 0x7)); |
450
3758bcdae5de
Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty
Mike Pavone <pavone@retrodev.com>
parents:
438
diff
changeset
|
747 |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
748 if (context->regs[REG_MODE_4] & BIT_HILIGHT) { |
436
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
749 for (int i = 0; i < 16; ++plane_a_off, ++plane_b_off, ++sprite_buf, ++i) { |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
750 uint8_t pixel; |
436
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
751 plane_a = context->tmp_buf_a + (plane_a_off & SCROLL_BUFFER_MASK); |
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
752 plane_b = context->tmp_buf_b + (plane_b_off & SCROLL_BUFFER_MASK); |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
753 uint32_t * colors = context->colors; |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
754 src = 0; |
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
755 uint8_t sprite_color = *sprite_buf & 0x3F; |
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
756 if (sprite_color == 0x3E || sprite_color == 0x3F) { |
232
54873acb982e
Shadow and higlight operators were switched
Mike Pavone <pavone@retrodev.com>
parents:
230
diff
changeset
|
757 if (sprite_color == 0x3F) { |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
758 colors += CRAM_SIZE; |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
759 src = DBG_SHADOW; |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
760 } else { |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
761 colors += CRAM_SIZE*2; |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
762 src = DBG_HILIGHT; |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
763 } |
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
764 if (*plane_a & BUF_BIT_PRIORITY && *plane_a & 0xF) { |
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
765 pixel = *plane_a; |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
766 src |= a_src; |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
767 } else if (*plane_b & BUF_BIT_PRIORITY && *plane_b & 0xF) { |
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
768 pixel = *plane_b; |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
769 src |= DBG_SRC_B; |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
770 } else if (*plane_a & 0xF) { |
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
771 pixel = *plane_a; |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
772 src |= a_src; |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
773 } else if (*plane_b & 0xF){ |
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
774 pixel = *plane_b; |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
775 src |= DBG_SRC_B; |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
776 } else { |
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
777 pixel = context->regs[REG_BG_COLOR] & 0x3F; |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
778 src |= DBG_SRC_BG; |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
779 } |
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
780 } else { |
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
781 if (*sprite_buf & BUF_BIT_PRIORITY && *sprite_buf & 0xF) { |
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
782 pixel = *sprite_buf; |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
783 src = DBG_SRC_S; |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
784 } else if (*plane_a & BUF_BIT_PRIORITY && *plane_a & 0xF) { |
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
785 pixel = *plane_a; |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
786 src = a_src; |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
787 } else if (*plane_b & BUF_BIT_PRIORITY && *plane_b & 0xF) { |
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
788 pixel = *plane_b; |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
789 src = DBG_SRC_B; |
233
9d10669f2579
Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
parents:
232
diff
changeset
|
790 } else { |
9d10669f2579
Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
parents:
232
diff
changeset
|
791 if (!(*plane_a & BUF_BIT_PRIORITY || *plane_a & BUF_BIT_PRIORITY)) { |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
792 colors += CRAM_SIZE; |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
793 src = DBG_SHADOW; |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
794 } |
233
9d10669f2579
Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
parents:
232
diff
changeset
|
795 if (*sprite_buf & 0xF) { |
9d10669f2579
Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
parents:
232
diff
changeset
|
796 pixel = *sprite_buf; |
9d10669f2579
Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
parents:
232
diff
changeset
|
797 if (*sprite_buf & 0xF == 0xE) { |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
798 colors = context->colors; |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
799 src = DBG_SRC_S; |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
800 } else { |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
801 src |= DBG_SRC_S; |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
802 } |
233
9d10669f2579
Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
parents:
232
diff
changeset
|
803 } else if (*plane_a & 0xF) { |
9d10669f2579
Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
parents:
232
diff
changeset
|
804 pixel = *plane_a; |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
805 src |= a_src; |
233
9d10669f2579
Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
parents:
232
diff
changeset
|
806 } else if (*plane_b & 0xF){ |
9d10669f2579
Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
parents:
232
diff
changeset
|
807 pixel = *plane_b; |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
808 src |= DBG_SRC_B; |
233
9d10669f2579
Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
parents:
232
diff
changeset
|
809 } else { |
9d10669f2579
Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
parents:
232
diff
changeset
|
810 pixel = context->regs[REG_BG_COLOR] & 0x3F; |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
811 src |= DBG_SRC_BG; |
233
9d10669f2579
Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
parents:
232
diff
changeset
|
812 } |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
813 } |
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
814 } |
426
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
815 pixel &= 0x3F; |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
816 uint32_t outpixel; |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
817 if (context->debug) { |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
818 outpixel = context->debugcolors[src]; |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
819 } else { |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
820 outpixel = colors[pixel]; |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
821 } |
426
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
822 if (context->b32) { |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
823 *(dst32++) = outpixel; |
426
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
824 } else { |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
825 *(dst++) = outpixel; |
426
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
826 } |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
827 //*dst = (context->cram[pixel & 0x3F] & 0xEEE) | ((pixel & BUF_BIT_PRIORITY) ? FBUF_BIT_PRIORITY : 0) | src; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
828 } |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
829 } else { |
436
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
830 for (int i = 0; i < 16; ++plane_a_off, ++plane_b_off, ++sprite_buf, ++i) { |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
831 uint8_t pixel; |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
832 src = 0; |
436
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
833 plane_a = context->tmp_buf_a + (plane_a_off & SCROLL_BUFFER_MASK); |
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
834 plane_b = context->tmp_buf_b + (plane_b_off & SCROLL_BUFFER_MASK); |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
835 if (*sprite_buf & BUF_BIT_PRIORITY && *sprite_buf & 0xF) { |
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
836 pixel = *sprite_buf; |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
837 src = DBG_SRC_S; |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
838 } else if (*plane_a & BUF_BIT_PRIORITY && *plane_a & 0xF) { |
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
839 pixel = *plane_a; |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
840 src = a_src; |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
841 } else if (*plane_b & BUF_BIT_PRIORITY && *plane_b & 0xF) { |
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
842 pixel = *plane_b; |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
843 src = DBG_SRC_B; |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
844 } else if (*sprite_buf & 0xF) { |
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
845 pixel = *sprite_buf; |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
846 src = DBG_SRC_S; |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
847 } else if (*plane_a & 0xF) { |
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
848 pixel = *plane_a; |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
849 src = a_src; |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
850 } else if (*plane_b & 0xF){ |
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
851 pixel = *plane_b; |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
852 src = DBG_SRC_B; |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
853 } else { |
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
854 pixel = context->regs[REG_BG_COLOR] & 0x3F; |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
855 src = DBG_SRC_BG; |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
856 } |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
857 uint32_t outpixel; |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
858 if (context->debug) { |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
859 outpixel = context->debugcolors[src]; |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
860 } else { |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
861 outpixel = context->colors[pixel & 0x3F]; |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
862 } |
426
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
863 if (context->b32) { |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
864 *(dst32++) = outpixel; |
426
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
865 } else { |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
866 *(dst++) = outpixel; |
426
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
867 } |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
868 //*dst = (context->cram[pixel & 0x3F] & 0xEEE) | ((pixel & BUF_BIT_PRIORITY) ? FBUF_BIT_PRIORITY : 0) | src; |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
869 } |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
870 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
871 } else { |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
872 //dst = context->framebuf + line * 320; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
873 //sprite_buf = context->linebuf + col * 8; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
874 //plane_a = context->tmp_buf_a + 16 - (context->hscroll_a & 0x7); |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
875 //plane_b = context->tmp_buf_b + 16 - (context->hscroll_b & 0x7); |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
876 //end = dst + 8; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
877 } |
436
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
878 context->buf_a_off = (context->buf_a_off + SCROLL_BUFFER_DRAW) & SCROLL_BUFFER_MASK; |
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
879 context->buf_b_off = (context->buf_b_off + SCROLL_BUFFER_DRAW) & SCROLL_BUFFER_MASK; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
880 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
881 |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
882 #define COLUMN_RENDER_BLOCK(column, startcyc) \ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
883 case startcyc:\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
884 read_map_scroll_a(column, line, context);\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
885 break;\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
886 case (startcyc+1):\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
887 external_slot(context);\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
888 break;\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
889 case (startcyc+2):\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
890 render_map_1(context);\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
891 break;\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
892 case (startcyc+3):\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
893 render_map_2(context);\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
894 break;\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
895 case (startcyc+4):\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
896 read_map_scroll_b(column, line, context);\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
897 break;\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
898 case (startcyc+5):\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
899 read_sprite_x(line, context);\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
900 break;\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
901 case (startcyc+6):\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
902 render_map_3(context);\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
903 break;\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
904 case (startcyc+7):\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
905 render_map_output(line, column, context);\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
906 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
907 |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
908 #define COLUMN_RENDER_BLOCK_REFRESH(column, startcyc) \ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
909 case startcyc:\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
910 read_map_scroll_a(column, line, context);\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
911 break;\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
912 case (startcyc+1):\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
913 break;\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
914 case (startcyc+2):\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
915 render_map_1(context);\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
916 break;\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
917 case (startcyc+3):\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
918 render_map_2(context);\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
919 break;\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
920 case (startcyc+4):\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
921 read_map_scroll_b(column, line, context);\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
922 break;\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
923 case (startcyc+5):\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
924 read_sprite_x(line, context);\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
925 break;\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
926 case (startcyc+6):\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
927 render_map_3(context);\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
928 break;\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
929 case (startcyc+7):\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
930 render_map_output(line, column, context);\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
931 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
932 |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
933 void vdp_h40(uint32_t line, uint32_t linecyc, vdp_context * context) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
934 { |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
935 uint16_t address; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
936 uint32_t mask; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
937 switch(linecyc) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
938 { |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
939 //sprite render to line buffer starts |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
940 case 0: |
26
a7c2b92d8056
Fix management of context->sprite_draws so the sprite layer only draws when it should
Mike Pavone <pavone@retrodev.com>
parents:
25
diff
changeset
|
941 context->cur_slot = MAX_DRAWS-1; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
942 memset(context->linebuf, 0, LINEBUF_SIZE); |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
943 case 1: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
944 case 2: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
945 case 3: |
329
fd5f6577db9b
Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents:
328
diff
changeset
|
946 if (line == 0xFF) { |
fd5f6577db9b
Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents:
328
diff
changeset
|
947 external_slot(context); |
fd5f6577db9b
Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents:
328
diff
changeset
|
948 } else { |
fd5f6577db9b
Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents:
328
diff
changeset
|
949 render_sprite_cells(context); |
fd5f6577db9b
Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents:
328
diff
changeset
|
950 } |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
951 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
952 //sprite attribute table scan starts |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
953 case 4: |
21
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
954 render_sprite_cells( context); |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
955 context->sprite_index = 0x80; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
956 context->slot_counter = MAX_SPRITES_LINE; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
957 scan_sprite_table(line, context); |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
958 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
959 case 5: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
960 case 6: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
961 case 7: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
962 case 8: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
963 case 9: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
964 case 10: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
965 case 11: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
966 case 12: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
967 case 13: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
968 case 14: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
969 case 15: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
970 case 16: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
971 case 17: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
972 case 18: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
973 case 19: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
974 case 20: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
975 //!HSYNC asserted |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
976 case 21: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
977 case 22: |
21
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
978 render_sprite_cells(context); |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
979 scan_sprite_table(line, context); |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
980 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
981 case 23: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
982 external_slot(context); |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
983 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
984 case 24: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
985 case 25: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
986 case 26: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
987 case 27: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
988 case 28: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
989 case 29: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
990 case 30: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
991 case 31: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
992 case 32: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
993 case 33: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
994 case 34: |
21
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
995 render_sprite_cells(context); |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
996 scan_sprite_table(line, context); |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
997 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
998 case 35: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
999 address = (context->regs[REG_HSCROLL] & 0x3F) << 10; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1000 mask = 0; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1001 if (context->regs[REG_MODE_3] & 0x2) { |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1002 mask |= 0xF8; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1003 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1004 if (context->regs[REG_MODE_3] & 0x1) { |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1005 mask |= 0x7; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1006 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1007 line &= mask; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1008 address += line * 4; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1009 context->hscroll_a = context->vdpmem[address] << 8 | context->vdpmem[address+1]; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1010 context->hscroll_b = context->vdpmem[address+2] << 8 | context->vdpmem[address+3]; |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1011 //printf("%d: HScroll A: %d, HScroll B: %d\n", line, context->hscroll_a, context->hscroll_b); |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1012 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1013 case 36: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1014 //!HSYNC high |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1015 case 37: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1016 case 38: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1017 case 39: |
21
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
1018 render_sprite_cells(context); |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1019 scan_sprite_table(line, context); |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1020 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1021 case 40: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1022 read_map_scroll_a(0, line, context); |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1023 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1024 case 41: |
21
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
1025 render_sprite_cells(context); |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1026 scan_sprite_table(line, context); |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1027 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1028 case 42: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1029 render_map_1(context); |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1030 scan_sprite_table(line, context);//Just a guess |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1031 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1032 case 43: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1033 render_map_2(context); |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1034 scan_sprite_table(line, context);//Just a guess |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1035 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1036 case 44: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1037 read_map_scroll_b(0, line, context); |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1038 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1039 case 45: |
21
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
1040 render_sprite_cells(context); |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1041 scan_sprite_table(line, context); |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1042 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1043 case 46: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1044 render_map_3(context); |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1045 scan_sprite_table(line, context);//Just a guess |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1046 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1047 case 47: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1048 render_map_output(line, 0, context); |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1049 scan_sprite_table(line, context);//Just a guess |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1050 //reverse context slot counter so it counts the number of sprite slots |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1051 //filled rather than the number of available slots |
21
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
1052 //context->slot_counter = MAX_SPRITES_LINE - context->slot_counter; |
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
1053 context->cur_slot = MAX_SPRITES_LINE-1; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1054 context->sprite_draws = MAX_DRAWS; |
36
04672c060062
Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents:
35
diff
changeset
|
1055 context->flags &= (~FLAG_CAN_MASK & ~FLAG_MASKED); |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1056 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1057 COLUMN_RENDER_BLOCK(2, 48) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1058 COLUMN_RENDER_BLOCK(4, 56) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1059 COLUMN_RENDER_BLOCK(6, 64) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1060 COLUMN_RENDER_BLOCK_REFRESH(8, 72) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1061 COLUMN_RENDER_BLOCK(10, 80) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1062 COLUMN_RENDER_BLOCK(12, 88) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1063 COLUMN_RENDER_BLOCK(14, 96) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1064 COLUMN_RENDER_BLOCK_REFRESH(16, 104) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1065 COLUMN_RENDER_BLOCK(18, 112) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1066 COLUMN_RENDER_BLOCK(20, 120) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1067 COLUMN_RENDER_BLOCK(22, 128) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1068 COLUMN_RENDER_BLOCK_REFRESH(24, 136) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1069 COLUMN_RENDER_BLOCK(26, 144) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1070 COLUMN_RENDER_BLOCK(28, 152) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1071 COLUMN_RENDER_BLOCK(30, 160) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1072 COLUMN_RENDER_BLOCK_REFRESH(32, 168) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1073 COLUMN_RENDER_BLOCK(34, 176) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1074 COLUMN_RENDER_BLOCK(36, 184) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1075 COLUMN_RENDER_BLOCK(38, 192) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1076 COLUMN_RENDER_BLOCK_REFRESH(40, 200) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1077 case 208: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1078 case 209: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1079 external_slot(context); |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1080 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1081 default: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1082 //leftovers from HSYNC clock change nonsense |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1083 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1084 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1085 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1086 |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1087 void vdp_h32(uint32_t line, uint32_t linecyc, vdp_context * context) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1088 { |
37 | 1089 uint16_t address; |
1090 uint32_t mask; | |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1091 switch(linecyc) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1092 { |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1093 //sprite render to line buffer starts |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1094 case 0: |
37 | 1095 context->cur_slot = MAX_DRAWS_H32-1; |
1096 memset(context->linebuf, 0, LINEBUF_SIZE); | |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1097 case 1: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1098 case 2: |
37 | 1099 case 3: |
329
fd5f6577db9b
Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents:
328
diff
changeset
|
1100 if (line == 0xFF) { |
fd5f6577db9b
Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents:
328
diff
changeset
|
1101 external_slot(context); |
fd5f6577db9b
Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents:
328
diff
changeset
|
1102 } else { |
fd5f6577db9b
Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents:
328
diff
changeset
|
1103 render_sprite_cells(context); |
fd5f6577db9b
Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents:
328
diff
changeset
|
1104 } |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1105 break; |
37 | 1106 //sprite attribute table scan starts |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1107 case 4: |
37 | 1108 render_sprite_cells( context); |
1109 context->sprite_index = 0x80; | |
1110 context->slot_counter = MAX_SPRITES_LINE_H32; | |
1111 scan_sprite_table(line, context); | |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1112 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1113 case 5: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1114 case 6: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1115 case 7: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1116 case 8: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1117 case 9: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1118 case 10: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1119 case 11: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1120 case 12: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1121 case 13: |
37 | 1122 render_sprite_cells(context); |
1123 scan_sprite_table(line, context); | |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1124 case 14: |
37 | 1125 external_slot(context); |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1126 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1127 case 15: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1128 case 16: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1129 case 17: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1130 case 18: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1131 case 19: |
37 | 1132 //HSYNC start |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1133 case 20: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1134 case 21: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1135 case 22: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1136 case 23: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1137 case 24: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1138 case 25: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1139 case 26: |
37 | 1140 render_sprite_cells(context); |
1141 scan_sprite_table(line, context); | |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1142 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1143 case 27: |
37 | 1144 external_slot(context); |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1145 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1146 case 28: |
37 | 1147 address = (context->regs[REG_HSCROLL] & 0x3F) << 10; |
1148 mask = 0; | |
1149 if (context->regs[REG_MODE_3] & 0x2) { | |
1150 mask |= 0xF8; | |
1151 } | |
1152 if (context->regs[REG_MODE_3] & 0x1) { | |
1153 mask |= 0x7; | |
1154 } | |
1155 line &= mask; | |
1156 address += line * 4; | |
1157 context->hscroll_a = context->vdpmem[address] << 8 | context->vdpmem[address+1]; | |
1158 context->hscroll_b = context->vdpmem[address+2] << 8 | context->vdpmem[address+3]; | |
1159 //printf("%d: HScroll A: %d, HScroll B: %d\n", line, context->hscroll_a, context->hscroll_b); | |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1160 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1161 case 29: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1162 case 30: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1163 case 31: |
37 | 1164 case 32: |
1165 render_sprite_cells(context); | |
1166 scan_sprite_table(line, context); | |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1167 break; |
37 | 1168 //!HSYNC high |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1169 case 33: |
37 | 1170 read_map_scroll_a(0, line, context); |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1171 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1172 case 34: |
37 | 1173 render_sprite_cells(context); |
1174 scan_sprite_table(line, context); | |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1175 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1176 case 35: |
37 | 1177 render_map_1(context); |
1178 scan_sprite_table(line, context);//Just a guess | |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1179 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1180 case 36: |
37 | 1181 render_map_2(context); |
1182 scan_sprite_table(line, context);//Just a guess | |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1183 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1184 case 37: |
37 | 1185 read_map_scroll_b(0, line, context); |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1186 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1187 case 38: |
37 | 1188 render_sprite_cells(context); |
1189 scan_sprite_table(line, context); | |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1190 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1191 case 39: |
37 | 1192 render_map_3(context); |
1193 scan_sprite_table(line, context);//Just a guess | |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1194 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1195 case 40: |
37 | 1196 render_map_output(line, 0, context); |
1197 scan_sprite_table(line, context);//Just a guess | |
1198 //reverse context slot counter so it counts the number of sprite slots | |
1199 //filled rather than the number of available slots | |
1200 //context->slot_counter = MAX_SPRITES_LINE - context->slot_counter; | |
1201 context->cur_slot = MAX_SPRITES_LINE_H32-1; | |
1202 context->sprite_draws = MAX_DRAWS_H32; | |
1203 context->flags &= (~FLAG_CAN_MASK & ~FLAG_MASKED); | |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1204 break; |
37 | 1205 COLUMN_RENDER_BLOCK(2, 41) |
1206 COLUMN_RENDER_BLOCK(4, 49) | |
1207 COLUMN_RENDER_BLOCK(6, 57) | |
1208 COLUMN_RENDER_BLOCK_REFRESH(8, 65) | |
1209 COLUMN_RENDER_BLOCK(10, 73) | |
1210 COLUMN_RENDER_BLOCK(12, 81) | |
1211 COLUMN_RENDER_BLOCK(14, 89) | |
1212 COLUMN_RENDER_BLOCK_REFRESH(16, 97) | |
1213 COLUMN_RENDER_BLOCK(18, 105) | |
1214 COLUMN_RENDER_BLOCK(20, 113) | |
1215 COLUMN_RENDER_BLOCK(22, 121) | |
1216 COLUMN_RENDER_BLOCK_REFRESH(24, 129) | |
1217 COLUMN_RENDER_BLOCK(26, 137) | |
1218 COLUMN_RENDER_BLOCK(28, 145) | |
1219 COLUMN_RENDER_BLOCK(30, 153) | |
1220 COLUMN_RENDER_BLOCK_REFRESH(32, 161) | |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1221 case 169: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1222 case 170: |
37 | 1223 external_slot(context); |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1224 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1225 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1226 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1227 void latch_mode(vdp_context * context) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1228 { |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1229 context->latched_mode = (context->regs[REG_MODE_4] & 0x81) | (context->regs[REG_MODE_2] & BIT_PAL); |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1230 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1231 |
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1232 void check_render_bg(vdp_context * context, int32_t line, uint32_t slot) |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1233 { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1234 if (line > 0) { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1235 line -= 1; |
426
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
1236 int starti = -1; |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1237 if (context->latched_mode & BIT_H40) { |
462
5677c053edd6
Fix timing of backdrop rendering when the display is turned off
Mike Pavone <pavone@retrodev.com>
parents:
461
diff
changeset
|
1238 if (slot >= 55 && slot < 210) { |
5677c053edd6
Fix timing of backdrop rendering when the display is turned off
Mike Pavone <pavone@retrodev.com>
parents:
461
diff
changeset
|
1239 uint32_t x = (slot-55)*2; |
426
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
1240 starti = line * 320 + x; |
462
5677c053edd6
Fix timing of backdrop rendering when the display is turned off
Mike Pavone <pavone@retrodev.com>
parents:
461
diff
changeset
|
1241 } else if (slot < 5) { |
5677c053edd6
Fix timing of backdrop rendering when the display is turned off
Mike Pavone <pavone@retrodev.com>
parents:
461
diff
changeset
|
1242 uint32_t x = (slot + 155)*2; |
5677c053edd6
Fix timing of backdrop rendering when the display is turned off
Mike Pavone <pavone@retrodev.com>
parents:
461
diff
changeset
|
1243 starti = (line-1)*320 + x; |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1244 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1245 } else { |
462
5677c053edd6
Fix timing of backdrop rendering when the display is turned off
Mike Pavone <pavone@retrodev.com>
parents:
461
diff
changeset
|
1246 if (slot >= 48 && slot < 171) { |
5677c053edd6
Fix timing of backdrop rendering when the display is turned off
Mike Pavone <pavone@retrodev.com>
parents:
461
diff
changeset
|
1247 uint32_t x = (slot-48)*2; |
426
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
1248 starti = line * 320 + x; |
462
5677c053edd6
Fix timing of backdrop rendering when the display is turned off
Mike Pavone <pavone@retrodev.com>
parents:
461
diff
changeset
|
1249 } else if (slot < 5) { |
5677c053edd6
Fix timing of backdrop rendering when the display is turned off
Mike Pavone <pavone@retrodev.com>
parents:
461
diff
changeset
|
1250 uint32_t x = (slot + 123)*2; |
5677c053edd6
Fix timing of backdrop rendering when the display is turned off
Mike Pavone <pavone@retrodev.com>
parents:
461
diff
changeset
|
1251 starti = (line-1)*320 + x; |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1252 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1253 } |
426
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
1254 if (starti >= 0) { |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
1255 if (context->b32) { |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
1256 uint32_t color = context->colors[context->regs[REG_BG_COLOR] & 0x3F]; |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
1257 uint32_t * start = context->framebuf; |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
1258 start += starti; |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
1259 for (int i = 0; i < 2; i++) { |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
1260 *(start++) = color; |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
1261 } |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
1262 } else { |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
1263 uint16_t color = context->colors[context->regs[REG_BG_COLOR] & 0x3F]; |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
1264 uint16_t * start = context->framebuf; |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
1265 start += starti; |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
1266 for (int i = 0; i < 2; i++) { |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
1267 *(start++) = color; |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
1268 } |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
1269 } |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1270 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1271 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1272 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1273 |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1274 void vdp_run_context(vdp_context * context, uint32_t target_cycles) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1275 { |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1276 while(context->cycles < target_cycles) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1277 { |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
1278 context->flags &= ~FLAG_UNUSED_SLOT; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1279 uint32_t line = context->cycles / MCLKS_LINE; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1280 uint32_t active_lines = context->latched_mode & BIT_PAL ? PAL_ACTIVE : NTSC_ACTIVE; |
334
4c91470e1a53
Only latch video mode at the very beginning of the frame to avoid problems with the cycle count getting out of sync with what I expect
Mike Pavone <pavone@retrodev.com>
parents:
333
diff
changeset
|
1281 if (!context->cycles) { |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1282 latch_mode(context); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1283 } |
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1284 uint32_t linecyc = context->cycles % MCLKS_LINE; |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1285 if (linecyc == 0) { |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1286 if (line <= 1 || line >= active_lines) { |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1287 context->hint_counter = context->regs[REG_HINT]; |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1288 } else if (context->hint_counter) { |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1289 context->hint_counter--; |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1290 } else { |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1291 context->flags2 |= FLAG2_HINT_PENDING; |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1292 context->hint_counter = context->regs[REG_HINT]; |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1293 } |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1294 } else if(line == active_lines) { |
331
de17e0352f27
Fixup VINT cycle and HBLANK flag for the previous timing fixes
Mike Pavone <pavone@retrodev.com>
parents:
330
diff
changeset
|
1295 uint32_t intcyc = context->latched_mode & BIT_H40 ? VINT_CYCLE_H40 : VINT_CYCLE_H32; |
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1296 if (linecyc == intcyc) { |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1297 context->flags2 |= FLAG2_VINT_PENDING; |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1298 } |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1299 } |
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1300 uint32_t inccycles, slot; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1301 if (context->latched_mode & BIT_H40){ |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1302 if (linecyc < MCLKS_SLOT_H40*HSYNC_SLOT_H40) { |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1303 slot = linecyc/MCLKS_SLOT_H40; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1304 inccycles = MCLKS_SLOT_H40; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1305 } else if(linecyc < MCLK_WEIRD_END) { |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1306 switch(linecyc-(MCLKS_SLOT_H40*HSYNC_SLOT_H40)) |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1307 { |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1308 case 0: |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1309 inccycles = 19; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1310 slot = 0; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1311 break; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1312 case 19: |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1313 slot = 1; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1314 inccycles = 20; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1315 break; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1316 case 39: |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1317 slot = 2; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1318 inccycles = 20; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1319 break; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1320 case 59: |
332
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1321 slot = 3; |
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1322 inccycles = 20; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1323 break; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1324 case 79: |
332
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1325 slot = 4; |
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1326 inccycles = 18; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1327 break; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1328 case 97: |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1329 slot = 5; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1330 inccycles = 20; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1331 break; |
332
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1332 case 117: |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1333 slot = 6; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1334 inccycles = 20; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1335 break; |
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1336 case 137: |
332
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1337 slot = 7; |
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1338 inccycles = 20; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1339 break; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1340 case 157: |
332
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1341 slot = 8; |
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1342 inccycles = 18; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1343 break; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1344 case 175: |
332
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1345 slot = 9; |
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1346 inccycles = 20; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1347 break; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1348 case 195: |
332
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1349 slot = 10; |
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1350 inccycles = 20; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1351 break; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1352 case 215: |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1353 slot = 11; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1354 inccycles = 20; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1355 break; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1356 case 235: |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1357 slot = 12; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1358 inccycles = 18; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1359 break; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1360 case 253: |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1361 slot = 13; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1362 inccycles = 20; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1363 break; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1364 case 273: |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1365 slot = 14; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1366 inccycles = 20; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1367 break; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1368 case 293: |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1369 slot = 15; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1370 inccycles = 20; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1371 break; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1372 case 313: |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1373 slot = 16; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1374 inccycles = 19; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1375 break; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1376 default: |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1377 fprintf(stderr, "cycles after weirdness %d\n", linecyc-(MCLKS_SLOT_H40*HSYNC_SLOT_H40)); |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1378 exit(1); |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1379 } |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1380 slot += HSYNC_SLOT_H40; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1381 } else { |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1382 slot = (linecyc-MCLK_WEIRD_END)/MCLKS_SLOT_H40 + SLOT_WEIRD_END; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1383 inccycles = MCLKS_SLOT_H40; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1384 } |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1385 } else { |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1386 inccycles = MCLKS_SLOT_H32; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1387 slot = linecyc/MCLKS_SLOT_H32; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1388 } |
329
fd5f6577db9b
Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents:
328
diff
changeset
|
1389 if ((line < active_lines || (line == active_lines && linecyc < (context->latched_mode & BIT_H40 ? 64 : 80))) && context->regs[REG_MODE_2] & DISPLAY_ENABLE) { |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1390 //first sort-of active line is treated as 255 internally |
450
3758bcdae5de
Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty
Mike Pavone <pavone@retrodev.com>
parents:
438
diff
changeset
|
1391 //it's used for gathering sprite info for line |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1392 line = (line - 1) & 0xFF; |
450
3758bcdae5de
Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty
Mike Pavone <pavone@retrodev.com>
parents:
438
diff
changeset
|
1393 |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1394 //Convert to slot number |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1395 if (context->latched_mode & BIT_H40){ |
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1396 vdp_h40(line, slot, context); |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1397 } else { |
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1398 vdp_h32(line, slot, context); |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1399 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1400 } else { |
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1401 if (!is_refresh(context, slot)) { |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1402 external_slot(context); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1403 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1404 if (line < active_lines) { |
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1405 check_render_bg(context, line, slot); |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1406 } |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1407 } |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
1408 if (context->flags & FLAG_DMA_RUN && !is_refresh(context, slot)) { |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
1409 run_dma_src(context, slot); |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
1410 } |
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1411 context->cycles += inccycles; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1412 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1413 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1414 |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1415 uint32_t vdp_run_to_vblank(vdp_context * context) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1416 { |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1417 uint32_t target_cycles = ((context->latched_mode & BIT_PAL) ? PAL_ACTIVE : NTSC_ACTIVE) * MCLKS_LINE; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1418 vdp_run_context(context, target_cycles); |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1419 return context->cycles; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1420 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1421 |
75 | 1422 void vdp_run_dma_done(vdp_context * context, uint32_t target_cycles) |
1423 { | |
1424 for(;;) { | |
1425 uint32_t dmalen = (context->regs[REG_DMALEN_H] << 8) | context->regs[REG_DMALEN_L]; | |
1426 if (!dmalen) { | |
1427 dmalen = 0x10000; | |
1428 } | |
1429 uint32_t min_dma_complete = dmalen * (context->latched_mode & BIT_H40 ? 16 : 20); | |
1430 if ((context->regs[REG_DMASRC_H] & 0xC0) == 0xC0 || (context->cd & 0xF) == VRAM_WRITE) { | |
1431 //DMA copies take twice as long to complete since they require a read and a write | |
1432 //DMA Fills and transfers to VRAM also take twice as long as it requires 2 writes for a single word | |
1433 min_dma_complete *= 2; | |
1434 } | |
1435 min_dma_complete += context->cycles; | |
1436 if (target_cycles < min_dma_complete) { | |
1437 vdp_run_context(context, target_cycles); | |
1438 return; | |
1439 } else { | |
1440 vdp_run_context(context, min_dma_complete); | |
1441 if (!(context->flags & FLAG_DMA_RUN)) { | |
1442 return; | |
1443 } | |
1444 } | |
1445 } | |
1446 } | |
1447 | |
1448 int vdp_control_port_write(vdp_context * context, uint16_t value) | |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1449 { |
471
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1450 //printf("control port write: %X at %d\n", value, context->cycles); |
149
139e5dcd6aa3
Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents:
143
diff
changeset
|
1451 if (context->flags & FLAG_DMA_RUN) { |
139e5dcd6aa3
Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents:
143
diff
changeset
|
1452 return -1; |
139e5dcd6aa3
Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents:
143
diff
changeset
|
1453 } |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1454 if (context->flags & FLAG_PENDING) { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1455 context->address = (context->address & 0x3FFF) | (value << 14); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1456 context->cd = (context->cd & 0x3) | ((value >> 2) & 0x3C); |
75 | 1457 context->flags &= ~FLAG_PENDING; |
453
b491df8bdbc0
Adjust VBLANK flag and refresh timing to be in line with logic analyzer and visual observations of direct color DMA demos. Remove debug print statements.
Mike Pavone <pavone@retrodev.com>
parents:
452
diff
changeset
|
1458 //printf("New Address: %X, New CD: %X\n", context->address, context->cd); |
327
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
1459 if (context->cd & 0x20 && (context->regs[REG_MODE_2] & BIT_DMA_ENABLE)) { |
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
1460 // |
75 | 1461 if((context->regs[REG_DMASRC_H] & 0xC0) != 0x80) { |
1462 //DMA copy or 68K -> VDP, transfer starts immediately | |
1463 context->flags |= FLAG_DMA_RUN; | |
131
8fc8e46be691
Fix bug that was causing DMA fills to lock up under certain circumstances
Mike Pavone <pavone@retrodev.com>
parents:
109
diff
changeset
|
1464 context->dma_cd = context->cd; |
453
b491df8bdbc0
Adjust VBLANK flag and refresh timing to be in line with logic analyzer and visual observations of direct color DMA demos. Remove debug print statements.
Mike Pavone <pavone@retrodev.com>
parents:
452
diff
changeset
|
1465 //printf("DMA start at cycle %d\n", context->cycles); |
75 | 1466 if (!(context->regs[REG_DMASRC_H] & 0x80)) { |
327
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
1467 //printf("DMA Address: %X, New CD: %X, Source: %X, Length: %X\n", context->address, context->cd, (context->regs[REG_DMASRC_H] << 17) | (context->regs[REG_DMASRC_M] << 9) | (context->regs[REG_DMASRC_L] << 1), context->regs[REG_DMALEN_H] << 8 | context->regs[REG_DMALEN_L]); |
75 | 1468 return 1; |
327
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
1469 } else { |
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
1470 //printf("DMA Copy Address: %X, New CD: %X, Source: %X\n", context->address, context->cd, (context->regs[REG_DMASRC_M] << 8) | context->regs[REG_DMASRC_L]); |
75 | 1471 } |
327
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
1472 } else { |
453
b491df8bdbc0
Adjust VBLANK flag and refresh timing to be in line with logic analyzer and visual observations of direct color DMA demos. Remove debug print statements.
Mike Pavone <pavone@retrodev.com>
parents:
452
diff
changeset
|
1473 //printf("DMA Fill Address: %X, New CD: %X\n", context->address, context->cd); |
75 | 1474 } |
63
a6dd5b7a971b
Add FPS counter to console output
Mike Pavone <pavone@retrodev.com>
parents:
58
diff
changeset
|
1475 } |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1476 } else { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1477 if ((value & 0xC000) == 0x8000) { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1478 //Register write |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1479 uint8_t reg = (value >> 8) & 0x1F; |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1480 if (reg < VDP_REGS) { |
453
b491df8bdbc0
Adjust VBLANK flag and refresh timing to be in line with logic analyzer and visual observations of direct color DMA demos. Remove debug print statements.
Mike Pavone <pavone@retrodev.com>
parents:
452
diff
changeset
|
1481 //printf("register %d set to %X\n", reg, value & 0xFF); |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1482 context->regs[reg] = value; |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
149
diff
changeset
|
1483 if (reg == REG_MODE_2) { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
149
diff
changeset
|
1484 //printf("Display is now %s\n", (context->regs[REG_MODE_2] & DISPLAY_ENABLE) ? "enabled" : "disabled"); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
149
diff
changeset
|
1485 } |
413
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1486 if (reg == REG_MODE_4) { |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1487 context->double_res = (value & (BIT_INTERLACE | BIT_DOUBLE_RES)) == (BIT_INTERLACE | BIT_DOUBLE_RES); |
415
8c60c8c09a0f
Fix sprite y mask in interlace mode. Fix framebuffer selection when switching out of interlace mode.
Mike Pavone <pavone@retrodev.com>
parents:
414
diff
changeset
|
1488 if (!context->double_res) { |
8c60c8c09a0f
Fix sprite y mask in interlace mode. Fix framebuffer selection when switching out of interlace mode.
Mike Pavone <pavone@retrodev.com>
parents:
414
diff
changeset
|
1489 context->framebuf = context->oddbuf; |
8c60c8c09a0f
Fix sprite y mask in interlace mode. Fix framebuffer selection when switching out of interlace mode.
Mike Pavone <pavone@retrodev.com>
parents:
414
diff
changeset
|
1490 } |
413
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1491 } |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1492 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1493 } else { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1494 context->flags |= FLAG_PENDING; |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1495 context->address = (context->address &0xC000) | (value & 0x3FFF); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1496 context->cd = (context->cd &0x3C) | (value >> 14); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1497 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1498 } |
75 | 1499 return 0; |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1500 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1501 |
149
139e5dcd6aa3
Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents:
143
diff
changeset
|
1502 int vdp_data_port_write(vdp_context * context, uint16_t value) |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1503 { |
471
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1504 //printf("data port write: %X at %d\n", value, context->cycles); |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
1505 if (context->flags & FLAG_DMA_RUN && (context->regs[REG_DMASRC_H] & 0xC0) != 0x80) { |
149
139e5dcd6aa3
Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents:
143
diff
changeset
|
1506 return -1; |
139e5dcd6aa3
Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents:
143
diff
changeset
|
1507 } |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1508 context->flags &= ~FLAG_PENDING; |
109
004dd46e0a97
COmment out fifo full debug printf
Mike Pavone <pavone@retrodev.com>
parents:
108
diff
changeset
|
1509 /*if (context->fifo_cur == context->fifo_end) { |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1510 printf("FIFO full, waiting for space before next write at cycle %X\n", context->cycles); |
109
004dd46e0a97
COmment out fifo full debug printf
Mike Pavone <pavone@retrodev.com>
parents:
108
diff
changeset
|
1511 }*/ |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
1512 if (context->cd & 0x20 && (context->regs[REG_DMASRC_H] & 0xC0) == 0x80) { |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
1513 context->flags &= ~FLAG_DMA_RUN; |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
1514 } |
471
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1515 while (context->fifo_write == context->fifo_read) { |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1516 vdp_run_context(context, context->cycles + ((context->latched_mode & BIT_H40) ? 16 : 20)); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1517 } |
471
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1518 fifo_entry * cur = context->fifo + context->fifo_write; |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1519 cur->cycle = context->cycles + ((context->latched_mode & BIT_H40) ? 16 : 20)*FIFO_LATENCY; |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1520 cur->address = context->address; |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1521 cur->value = value; |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
1522 context->last_write_val = value; |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
1523 if (context->cd & 0x20 && (context->regs[REG_DMASRC_H] & 0xC0) == 0x80) { |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
1524 context->flags |= FLAG_DMA_RUN; |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
1525 } |
471
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1526 cur->cd = context->cd; |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1527 cur->partial = 0; |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1528 if (context->fifo_read < 0) { |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1529 context->fifo_read = context->fifo_write; |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1530 } |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1531 context->fifo_write = (context->fifo_write + 1) & (FIFO_SIZE-1); |
138 | 1532 context->address += context->regs[REG_AUTOINC]; |
149
139e5dcd6aa3
Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents:
143
diff
changeset
|
1533 return 0; |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1534 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1535 |
470
541c1ae8abf3
Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1536 void vdp_test_port_write(vdp_context * context, uint16_t value) |
541c1ae8abf3
Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1537 { |
541c1ae8abf3
Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1538 //TODO: implement test register |
541c1ae8abf3
Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1539 } |
541c1ae8abf3
Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1540 |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1541 uint16_t vdp_control_port_read(vdp_context * context) |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1542 { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1543 context->flags &= ~FLAG_PENDING; |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1544 uint16_t value = 0x3400; |
471
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1545 if (context->fifo_read < 0) { |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1546 value |= 0x200; |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1547 } |
471
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1548 if (context->fifo_read == context->fifo_write) { |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1549 value |= 0x100; |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1550 } |
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1551 if (context->flags2 & FLAG2_VINT_PENDING) { |
413
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1552 value |= 0x80; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1553 } |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1554 if ((context->regs[REG_MODE_4] & BIT_INTERLACE) && context->framebuf == context->oddbuf) { |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1555 value |= 0x10; |
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1556 } |
318
789f2f5f2277
Implement hblank flag in status register
Mike Pavone <pavone@retrodev.com>
parents:
317
diff
changeset
|
1557 uint32_t line= context->cycles / MCLKS_LINE; |
789f2f5f2277
Implement hblank flag in status register
Mike Pavone <pavone@retrodev.com>
parents:
317
diff
changeset
|
1558 uint32_t linecyc = context->cycles % MCLKS_LINE; |
459
c49ecf575784
Revert change to VBLANK flag timing based on new direct color DMA test
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
1559 if (line >= (context->latched_mode & BIT_PAL ? PAL_ACTIVE : NTSC_ACTIVE)) { |
318
789f2f5f2277
Implement hblank flag in status register
Mike Pavone <pavone@retrodev.com>
parents:
317
diff
changeset
|
1560 value |= 0x8; |
789f2f5f2277
Implement hblank flag in status register
Mike Pavone <pavone@retrodev.com>
parents:
317
diff
changeset
|
1561 } |
331
de17e0352f27
Fixup VINT cycle and HBLANK flag for the previous timing fixes
Mike Pavone <pavone@retrodev.com>
parents:
330
diff
changeset
|
1562 if (linecyc < (context->latched_mode & BIT_H40 ? HBLANK_CLEAR_H40 : HBLANK_CLEAR_H32)) { |
318
789f2f5f2277
Implement hblank flag in status register
Mike Pavone <pavone@retrodev.com>
parents:
317
diff
changeset
|
1563 value |= 0x4; |
789f2f5f2277
Implement hblank flag in status register
Mike Pavone <pavone@retrodev.com>
parents:
317
diff
changeset
|
1564 } |
149
139e5dcd6aa3
Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents:
143
diff
changeset
|
1565 if (context->flags & FLAG_DMA_RUN) { |
141
576f55711d8d
Fix DMA in progress flag in VDP status register
Mike Pavone <pavone@retrodev.com>
parents:
138
diff
changeset
|
1566 value |= 0x2; |
75 | 1567 } |
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1568 if (context->latched_mode & BIT_PAL) {//Not sure about this, need to verify |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1569 value |= 0x1; |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1570 } |
459
c49ecf575784
Revert change to VBLANK flag timing based on new direct color DMA test
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
1571 //printf("status read at cycle %d returned %X\n", context->cycles, value); |
318
789f2f5f2277
Implement hblank flag in status register
Mike Pavone <pavone@retrodev.com>
parents:
317
diff
changeset
|
1572 //TODO: Sprite overflow, sprite collision, odd frame flag |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1573 return value; |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1574 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1575 |
470
541c1ae8abf3
Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1576 #define CRAM_BITS 0xEEE |
474
e128e55710bd
Remove read pending stuff, that had been added in an attempt to fix CRAM/VSRAM undefined bit results. Set number of bits actually saved in VSRAM to 11
Mike Pavone <pavone@retrodev.com>
parents:
473
diff
changeset
|
1577 #define VSRAM_BITS 0x7FF |
471
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1578 #define VSRAM_DIRTY_BITS 0xF800 |
470
541c1ae8abf3
Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1579 |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1580 uint16_t vdp_data_port_read(vdp_context * context) |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1581 { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1582 context->flags &= ~FLAG_PENDING; |
138 | 1583 if (context->cd & 1) { |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1584 return 0; |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1585 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1586 //Not sure if the FIFO should be drained before processing a read or not, but it would make sense |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1587 context->flags &= ~FLAG_UNUSED_SLOT; |
474
e128e55710bd
Remove read pending stuff, that had been added in an attempt to fix CRAM/VSRAM undefined bit results. Set number of bits actually saved in VSRAM to 11
Mike Pavone <pavone@retrodev.com>
parents:
473
diff
changeset
|
1588 //context->flags2 |= FLAG2_READ_PENDING; |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1589 while (!(context->flags & FLAG_UNUSED_SLOT)) { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1590 vdp_run_context(context, context->cycles + ((context->latched_mode & BIT_H40) ? 16 : 20)); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1591 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1592 uint16_t value = 0; |
138 | 1593 switch (context->cd & 0xF) |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1594 { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1595 case VRAM_READ: |
472 | 1596 value = context->vdpmem[context->address & 0xFFFE] << 8; |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1597 context->flags &= ~FLAG_UNUSED_SLOT; |
470
541c1ae8abf3
Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1598 context->flags2 |= FLAG2_READ_PENDING; |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1599 while (!(context->flags & FLAG_UNUSED_SLOT)) { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1600 vdp_run_context(context, context->cycles + ((context->latched_mode & BIT_H40) ? 16 : 20)); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1601 } |
472 | 1602 value |= context->vdpmem[context->address | 1]; |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1603 break; |
473
1358045c0bdd
Implement undocumented 8-bit VRAM read
Mike Pavone <pavone@retrodev.com>
parents:
472
diff
changeset
|
1604 case VRAM_READ8: |
1358045c0bdd
Implement undocumented 8-bit VRAM read
Mike Pavone <pavone@retrodev.com>
parents:
472
diff
changeset
|
1605 value = context->vdpmem[context->address ^ 1]; |
1358045c0bdd
Implement undocumented 8-bit VRAM read
Mike Pavone <pavone@retrodev.com>
parents:
472
diff
changeset
|
1606 value |= context->fifo[context->fifo_write].value & 0xFF00; |
1358045c0bdd
Implement undocumented 8-bit VRAM read
Mike Pavone <pavone@retrodev.com>
parents:
472
diff
changeset
|
1607 break; |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1608 case CRAM_READ: |
470
541c1ae8abf3
Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1609 value = context->cram[(context->address/2) & (CRAM_SIZE-1)] & CRAM_BITS; |
471
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1610 value |= context->fifo[context->fifo_write].value & ~CRAM_BITS; |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1611 break; |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1612 case VSRAM_READ: |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1613 if (((context->address / 2) & 63) < VSRAM_SIZE) { |
472 | 1614 value = context->vsram[(context->address / 2) & 63] & VSRAM_BITS; |
471
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1615 value |= context->fifo[context->fifo_write].value & VSRAM_DIRTY_BITS; |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1616 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1617 break; |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1618 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1619 context->address += context->regs[REG_AUTOINC]; |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1620 return value; |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1621 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1622 |
137 | 1623 uint16_t vdp_hv_counter_read(vdp_context * context) |
1624 { | |
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1625 //TODO: deal with clock adjustemnts handled in vdp_run_context |
137 | 1626 uint32_t line= context->cycles / MCLKS_LINE; |
1627 if (!line) { | |
1628 line = 0xFF; | |
1629 } else { | |
1630 line--; | |
1631 if (line > 0xEA) { | |
1632 line = (line + 0xFA) & 0xFF; | |
1633 } | |
1634 } | |
1635 uint32_t linecyc = context->cycles % MCLKS_LINE; | |
1636 if (context->latched_mode & BIT_H40) { | |
332
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1637 uint32_t slot; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1638 if (linecyc < MCLKS_SLOT_H40*HSYNC_SLOT_H40) { |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1639 slot = linecyc/MCLKS_SLOT_H40; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1640 } else if(linecyc < MCLK_WEIRD_END) { |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1641 switch(linecyc-(MCLKS_SLOT_H40*HSYNC_SLOT_H40)) |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1642 { |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1643 case 0: |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1644 slot = 0; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1645 break; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1646 case 19: |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1647 slot = 1; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1648 break; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1649 case 39: |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1650 slot = 2; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1651 break; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1652 case 59: |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1653 slot = 2; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1654 break; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1655 case 79: |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1656 slot = 3; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1657 break; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1658 case 97: |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1659 slot = 4; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1660 break; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1661 case 117: |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1662 slot = 5; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1663 break; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1664 case 137: |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1665 slot = 6; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1666 break; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1667 case 157: |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1668 slot = 7; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1669 break; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1670 case 175: |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1671 slot = 8; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1672 break; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1673 case 195: |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1674 slot = 9; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1675 break; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1676 case 215: |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1677 slot = 11; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1678 break; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1679 case 235: |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1680 slot = 12; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1681 break; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1682 case 253: |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1683 slot = 13; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1684 break; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1685 case 273: |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1686 slot = 14; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1687 break; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1688 case 293: |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1689 slot = 15; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1690 break; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1691 case 313: |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1692 slot = 16; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1693 break; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1694 default: |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1695 fprintf(stderr, "cycles after weirdness %d\n", linecyc-(MCLKS_SLOT_H40*HSYNC_SLOT_H40)); |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1696 exit(1); |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1697 } |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1698 slot += HSYNC_SLOT_H40; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1699 } else { |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1700 slot = (linecyc-MCLK_WEIRD_END)/MCLKS_SLOT_H40 + SLOT_WEIRD_END; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1701 } |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1702 linecyc = slot * 2; |
137 | 1703 if (linecyc >= 86) { |
1704 linecyc -= 86; | |
1705 } else { | |
1706 linecyc += 334; | |
1707 } | |
1708 if (linecyc > 0x16C) { | |
1709 linecyc += 92; | |
1710 } | |
1711 } else { | |
1712 linecyc /= 10; | |
1713 if (linecyc >= 74) { | |
1714 linecyc -= 74; | |
1715 } else { | |
1716 linecyc += 268; | |
1717 } | |
1718 if (linecyc > 0x127) { | |
1719 linecyc += 170; | |
1720 } | |
1721 } | |
1722 linecyc &= 0xFF; | |
413
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1723 if (context->double_res) { |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1724 line <<= 1; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1725 if (line & 0x100) { |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1726 line |= 1; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1727 } |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1728 } |
137 | 1729 return (line << 8) | linecyc; |
1730 } | |
1731 | |
470
541c1ae8abf3
Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1732 uint16_t vdp_test_port_read(vdp_context * context) |
541c1ae8abf3
Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1733 { |
541c1ae8abf3
Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1734 //TODO: Find out what actually gets returned here |
541c1ae8abf3
Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1735 return 0xFFFF; |
541c1ae8abf3
Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1736 } |
541c1ae8abf3
Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1737 |
65
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1738 void vdp_adjust_cycles(vdp_context * context, uint32_t deduction) |
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1739 { |
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1740 context->cycles -= deduction; |
471
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1741 if (context->fifo_read >= 0) { |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1742 int32_t idx = context->fifo_read; |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1743 do { |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1744 if (context->fifo[idx].cycle >= deduction) { |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1745 context->fifo[idx].cycle -= deduction; |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1746 } else { |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1747 context->fifo[idx].cycle = 0; |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1748 } |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1749 idx = (idx+1) & (FIFO_SIZE-1); |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1750 } while(idx != context->fifo_write); |
65
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1751 } |
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1752 } |
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1753 |
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1754 uint32_t vdp_next_hint(vdp_context * context) |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1755 { |
327
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
1756 if (!(context->regs[REG_MODE_1] & BIT_HINT_EN)) { |
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1757 return 0xFFFFFFFF; |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1758 } |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1759 if (context->flags2 & FLAG2_HINT_PENDING) { |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1760 return context->cycles; |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1761 } |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1762 uint32_t active_lines = context->latched_mode & BIT_PAL ? PAL_ACTIVE : NTSC_ACTIVE; |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1763 uint32_t line = context->cycles / MCLKS_LINE; |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1764 if (line >= active_lines) { |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1765 return 0xFFFFFFFF; |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1766 } |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1767 uint32_t linecyc = context->cycles % MCLKS_LINE; |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1768 uint32_t hcycle = context->cycles + context->hint_counter * MCLKS_LINE + MCLKS_LINE - linecyc; |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1769 if (!line) { |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1770 hcycle += MCLKS_LINE; |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1771 } |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1772 return hcycle; |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1773 } |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1774 |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1775 uint32_t vdp_next_vint(vdp_context * context) |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1776 { |
327
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
1777 if (!(context->regs[REG_MODE_2] & BIT_VINT_EN)) { |
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1778 return 0xFFFFFFFF; |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1779 } |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1780 if (context->flags2 & FLAG2_VINT_PENDING) { |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1781 return context->cycles; |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1782 } |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1783 uint32_t active_lines = context->latched_mode & BIT_PAL ? PAL_ACTIVE : NTSC_ACTIVE; |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1784 uint32_t vcycle = MCLKS_LINE * active_lines; |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1785 if (context->latched_mode & BIT_H40) { |
331
de17e0352f27
Fixup VINT cycle and HBLANK flag for the previous timing fixes
Mike Pavone <pavone@retrodev.com>
parents:
330
diff
changeset
|
1786 vcycle += VINT_CYCLE_H40; |
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1787 } else { |
331
de17e0352f27
Fixup VINT cycle and HBLANK flag for the previous timing fixes
Mike Pavone <pavone@retrodev.com>
parents:
330
diff
changeset
|
1788 vcycle += VINT_CYCLE_H32; |
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1789 } |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1790 if (vcycle < context->cycles) { |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1791 return 0xFFFFFFFF; |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1792 } |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1793 return vcycle; |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1794 } |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1795 |
333 | 1796 uint32_t vdp_next_vint_z80(vdp_context * context) |
1797 { | |
1798 uint32_t active_lines = context->latched_mode & BIT_PAL ? PAL_ACTIVE : NTSC_ACTIVE; | |
1799 uint32_t vcycle = MCLKS_LINE * active_lines; | |
1800 if (context->latched_mode & BIT_H40) { | |
1801 vcycle += VINT_CYCLE_H40; | |
1802 } else { | |
1803 vcycle += VINT_CYCLE_H32; | |
1804 } | |
1805 return vcycle; | |
1806 } | |
1807 | |
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1808 void vdp_int_ack(vdp_context * context, uint16_t int_num) |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1809 { |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1810 if (int_num == 6) { |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1811 context->flags2 &= ~FLAG2_VINT_PENDING; |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1812 } else if(int_num ==4) { |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1813 context->flags2 &= ~FLAG2_HINT_PENDING; |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1814 } |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1815 } |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1816 |