Mercurial > repos > blastem
annotate 68kinst.c @ 637:d8d58eced22f
Tiny bit of work towards supporting 68020 addressing modes in decoder/disassembler
author | Michael Pavone <pavone@retrodev.com> |
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date | Sun, 12 Oct 2014 23:55:25 -0700 |
parents | 22e357678fad |
children | 8a3198c17207 |
rev | line source |
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1 /* |
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2 Copyright 2013 Michael Pavone |
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3 This file is part of BlastEm. |
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4 BlastEm is free software distributed under the terms of the GNU General Public License version 3 or greater. See COPYING for full license text. |
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5 */ |
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6 #include "68kinst.h" |
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7 #include <string.h> |
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8 #include <stdio.h> |
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9 |
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10 uint32_t sign_extend16(uint32_t val) |
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11 { |
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12 return (val & 0x8000) ? val | 0xFFFF0000 : val; |
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13 } |
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14 |
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15 uint32_t sign_extend8(uint32_t val) |
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16 { |
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17 return (val & 0x80) ? val | 0xFFFFFF00 : val; |
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18 } |
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19 |
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20 uint16_t *m68k_decode_op_ex(uint16_t *cur, uint8_t mode, uint8_t reg, uint8_t size, m68k_op_info *dst) |
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21 { |
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22 uint16_t ext; |
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23 dst->addr_mode = mode; |
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24 switch(mode) |
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25 { |
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26 case MODE_REG: |
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27 case MODE_AREG: |
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28 case MODE_AREG_INDIRECT: |
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29 case MODE_AREG_POSTINC: |
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30 case MODE_AREG_PREDEC: |
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31 dst->params.regs.pri = reg; |
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32 break; |
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33 case MODE_AREG_DISPLACE: |
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34 ext = *(++cur); |
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35 dst->params.regs.pri = reg; |
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36 dst->params.regs.displacement = sign_extend16(ext); |
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37 break; |
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38 case MODE_AREG_INDEX_MEM: |
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39 #ifdef M68020 |
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40 //TODO: implement me for M68020+ support |
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41 #else |
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42 dst->addr_mode = MODE_AREG_INDEX_DISP8; |
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43 dst->params.regs.pri = reg; |
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44 ext = *(++cur); |
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45 dst->params.regs.sec = ext >> 11;//includes areg/dreg bit, reg num and word/long bit |
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46 dst->params.regs.displacement = sign_extend8(ext&0xFF); |
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47 #endif |
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48 break; |
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49 case MODE_PC_INDIRECT_ABS_IMMED: |
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50 switch(reg) |
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51 { |
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52 case 0: |
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53 dst->addr_mode = MODE_ABSOLUTE_SHORT; |
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54 ext = *(++cur); |
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55 dst->params.immed = sign_extend16(ext); |
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56 break; |
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57 case 1: |
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58 dst->addr_mode = MODE_ABSOLUTE; |
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59 ext = *(++cur); |
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60 dst->params.immed = ext << 16 | *(++cur); |
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61 break; |
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62 case 3: |
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63 #ifdef M68020 |
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64 //TODO: Implement me for M68020+ support; |
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65 #else |
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66 dst->addr_mode = MODE_PC_INDEX_DISP8; |
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67 ext = *(++cur); |
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68 dst->params.regs.sec = ext >> 11;//includes areg/dreg bit, reg num and word/long bit |
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69 dst->params.regs.displacement = sign_extend8(ext&0xFF); |
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70 #endif |
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71 break; |
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72 case 2: |
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73 dst->addr_mode = MODE_PC_DISPLACE; |
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74 ext = *(++cur); |
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75 dst->params.regs.displacement = sign_extend16(ext); |
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76 break; |
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77 case 4: |
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78 dst->addr_mode = MODE_IMMEDIATE; |
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79 ext = *(++cur); |
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80 switch (size) |
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81 { |
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82 case OPSIZE_BYTE: |
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83 dst->params.immed = ext & 0xFF; |
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84 break; |
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85 case OPSIZE_WORD: |
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86 dst->params.immed = ext; |
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87 break; |
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88 case OPSIZE_LONG: |
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89 dst->params.immed = ext << 16 | *(++cur); |
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90 break; |
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91 } |
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92 break; |
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93 default: |
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94 return NULL; |
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95 } |
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96 break; |
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97 } |
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98 return cur; |
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99 } |
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100 |
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101 uint16_t *m68k_decode_op(uint16_t *cur, uint8_t size, m68k_op_info *dst) |
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102 { |
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103 uint8_t mode = (*cur >> 3) & 0x7; |
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104 uint8_t reg = *cur & 0x7; |
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105 return m68k_decode_op_ex(cur, mode, reg, size, dst); |
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106 } |
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107 |
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108 void m68k_decode_cond(uint16_t op, m68kinst * decoded) |
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109 { |
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110 decoded->extra.cond = (op >> 0x8) & 0xF; |
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111 } |
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112 |
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113 uint8_t m68k_reg_quick_field(uint16_t op) |
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114 { |
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115 return (op >> 9) & 0x7; |
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116 } |
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117 |
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118 uint16_t * m68k_decode(uint16_t * istream, m68kinst * decoded, uint32_t address) |
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119 { |
176
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120 uint16_t *start = istream; |
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121 uint8_t optype = *istream >> 12; |
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122 uint8_t size; |
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123 uint8_t reg; |
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124 uint8_t opmode; |
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125 uint32_t immed; |
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126 decoded->op = M68K_INVALID; |
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127 decoded->src.addr_mode = decoded->dst.addr_mode = MODE_UNUSED; |
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128 decoded->variant = VAR_NORMAL; |
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129 decoded->address = address; |
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130 switch(optype) |
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131 { |
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132 case BIT_MOVEP_IMMED: |
163 | 133 if ((*istream & 0x138) == 0x108) { |
134 //MOVEP | |
135 decoded->op = M68K_MOVEP; | |
136 decoded->extra.size = *istream & 0x40 ? OPSIZE_LONG : OPSIZE_WORD; | |
137 if (*istream & 0x80) { | |
138 //memory dest | |
139 decoded->src.addr_mode = MODE_REG; | |
140 decoded->src.params.regs.pri = m68k_reg_quick_field(*istream); | |
141 decoded->dst.addr_mode = MODE_AREG_DISPLACE; | |
142 decoded->dst.params.regs.pri = *istream & 0x7; | |
143 decoded->dst.params.regs.displacement = *(++istream); | |
144 } else { | |
145 //memory source | |
146 decoded->dst.addr_mode = MODE_REG; | |
147 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream); | |
148 decoded->src.addr_mode = MODE_AREG_DISPLACE; | |
149 decoded->src.params.regs.pri = *istream & 0x7; | |
150 decoded->src.params.regs.displacement = *(++istream); | |
151 } | |
152 } else if (*istream & 0x100) { | |
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153 //BTST, BCHG, BCLR, BSET |
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154 switch ((*istream >> 6) & 0x3) |
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155 { |
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156 case 0: |
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157 decoded->op = M68K_BTST; |
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158 break; |
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159 case 1: |
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160 decoded->op = M68K_BCHG; |
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161 break; |
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162 case 2: |
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163 decoded->op = M68K_BCLR; |
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164 break; |
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165 case 3: |
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166 decoded->op = M68K_BSET; |
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167 break; |
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168 } |
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169 decoded->src.addr_mode = MODE_REG; |
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170 decoded->src.params.regs.pri = m68k_reg_quick_field(*istream); |
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171 decoded->extra.size = OPSIZE_BYTE; |
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172 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->dst)); |
176
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173 if (!istream) { |
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174 decoded->op = M68K_INVALID; |
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175 break; |
176
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176 } |
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177 if (decoded->dst.addr_mode == MODE_REG) { |
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178 decoded->extra.size = OPSIZE_LONG; |
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179 } |
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180 } else if ((*istream & 0xF00) == 0x800) { |
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181 //BTST, BCHG, BCLR, BSET |
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182 switch ((*istream >> 6) & 0x3) |
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183 { |
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184 case 0: |
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185 decoded->op = M68K_BTST; |
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186 break; |
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187 case 1: |
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188 decoded->op = M68K_BCHG; |
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189 break; |
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190 case 2: |
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191 decoded->op = M68K_BCLR; |
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192 break; |
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193 case 3: |
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194 decoded->op = M68K_BSET; |
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195 break; |
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196 } |
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197 opmode = (*istream >> 3) & 0x7; |
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198 reg = *istream & 0x7; |
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199 decoded->src.addr_mode = MODE_IMMEDIATE_WORD; |
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200 decoded->src.params.immed = *(++istream) & 0xFF; |
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201 decoded->extra.size = OPSIZE_BYTE; |
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202 istream = m68k_decode_op_ex(istream, opmode, reg, decoded->extra.size, &(decoded->dst)); |
176
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203 if (!istream) { |
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204 decoded->op = M68K_INVALID; |
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205 break; |
176
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206 } |
61
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207 if (decoded->dst.addr_mode == MODE_REG) { |
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208 decoded->extra.size = OPSIZE_LONG; |
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209 } |
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210 } else if ((*istream & 0xC0) == 0xC0) { |
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211 #ifdef M68020 |
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212 //CMP2, CHK2, CAS, CAS2, RTM, CALLM |
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213 #endif |
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214 } else { |
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215 switch ((*istream >> 9) & 0x7) |
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216 { |
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217 case 0: |
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218 if ((*istream & 0xFF) == 0x3C) { |
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219 decoded->op = M68K_ORI_CCR; |
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220 decoded->extra.size = OPSIZE_BYTE; |
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221 decoded->src.addr_mode = MODE_IMMEDIATE; |
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222 decoded->src.params.immed = *(++istream) & 0xFF; |
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223 } else if((*istream & 0xFF) == 0x7C) { |
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224 decoded->op = M68K_ORI_SR; |
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225 decoded->extra.size = OPSIZE_WORD; |
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226 decoded->src.addr_mode = MODE_IMMEDIATE; |
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227 decoded->src.params.immed = *(++istream); |
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228 } else { |
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229 decoded->op = M68K_OR; |
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230 decoded->variant = VAR_IMMEDIATE; |
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231 decoded->src.addr_mode = MODE_IMMEDIATE; |
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232 decoded->extra.size = size = (*istream >> 6) & 3; |
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233 reg = *istream & 0x7; |
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234 opmode = (*istream >> 3) & 0x7; |
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235 switch (size) |
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236 { |
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237 case OPSIZE_BYTE: |
15
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parents:
13
diff
changeset
|
238 decoded->src.params.immed = *(++istream) & 0xFF; |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
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5
diff
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|
239 break; |
23b83d94c633
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Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
240 case OPSIZE_WORD: |
15
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Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
241 decoded->src.params.immed = *(++istream); |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
242 break; |
23b83d94c633
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Mike Pavone <pavone@retrodev.com>
parents:
5
diff
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|
243 case OPSIZE_LONG: |
23b83d94c633
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diff
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|
244 immed = *(++istream); |
15
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parents:
13
diff
changeset
|
245 decoded->src.params.immed = immed << 16 | *(++istream); |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
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parents:
5
diff
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|
246 break; |
4
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3
diff
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|
247 } |
8
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5
diff
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|
248 istream = m68k_decode_op_ex(istream, opmode, reg, size, &(decoded->dst)); |
176
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163
diff
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|
249 if (!istream) { |
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163
diff
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|
250 decoded->op = M68K_INVALID; |
630
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Michael Pavone <pavone@retrodev.com>
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518
diff
changeset
|
251 break; |
176
e2918b5208eb
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Mike Pavone <pavone@retrodev.com>
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163
diff
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|
252 } |
4
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
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3
diff
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|
253 } |
6f6a2d7cc889
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parents:
3
diff
changeset
|
254 break; |
6f6a2d7cc889
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parents:
3
diff
changeset
|
255 case 1: |
8
23b83d94c633
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Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
256 //ANDI, ANDI to CCR, ANDI to SR |
5
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diff
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|
257 if ((*istream & 0xFF) == 0x3C) { |
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diff
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|
258 decoded->op = M68K_ANDI_CCR; |
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diff
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|
259 decoded->extra.size = OPSIZE_BYTE; |
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4
diff
changeset
|
260 decoded->src.addr_mode = MODE_IMMEDIATE; |
15
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Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
261 decoded->src.params.immed = *(++istream) & 0xFF; |
5
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diff
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|
262 } else if((*istream & 0xFF) == 0x7C) { |
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4
diff
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|
263 decoded->op = M68K_ANDI_SR; |
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4
diff
changeset
|
264 decoded->extra.size = OPSIZE_WORD; |
85699517043f
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4
diff
changeset
|
265 decoded->src.addr_mode = MODE_IMMEDIATE; |
15
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Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
266 decoded->src.params.immed = *(++istream); |
5
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diff
changeset
|
267 } else { |
8
23b83d94c633
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5
diff
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|
268 decoded->op = M68K_AND; |
23b83d94c633
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5
diff
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|
269 decoded->variant = VAR_IMMEDIATE; |
5
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4
diff
changeset
|
270 decoded->src.addr_mode = MODE_IMMEDIATE; |
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diff
changeset
|
271 decoded->extra.size = size = (*istream >> 6) & 3; |
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4
diff
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|
272 reg = *istream & 0x7; |
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diff
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|
273 opmode = (*istream >> 3) & 0x7; |
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diff
changeset
|
274 switch (size) |
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4
diff
changeset
|
275 { |
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4
diff
changeset
|
276 case OPSIZE_BYTE: |
15
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Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
277 decoded->src.params.immed = *(++istream) & 0xFF; |
5
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4
diff
changeset
|
278 break; |
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4
diff
changeset
|
279 case OPSIZE_WORD: |
15
c0f339564819
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Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
280 decoded->src.params.immed = *(++istream); |
5
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4
diff
changeset
|
281 break; |
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4
diff
changeset
|
282 case OPSIZE_LONG: |
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diff
changeset
|
283 immed = *(++istream); |
15
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Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
284 decoded->src.params.immed = immed << 16 | *(++istream); |
5
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4
diff
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|
285 break; |
85699517043f
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4
diff
changeset
|
286 } |
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4
diff
changeset
|
287 istream = m68k_decode_op_ex(istream, opmode, reg, size, &(decoded->dst)); |
176
e2918b5208eb
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Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
288 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
289 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
290 break; |
176
e2918b5208eb
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parents:
163
diff
changeset
|
291 } |
5
85699517043f
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4
diff
changeset
|
292 } |
4
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
293 break; |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
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5
diff
changeset
|
294 case 2: |
23b83d94c633
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diff
changeset
|
295 decoded->op = M68K_SUB; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
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5
diff
changeset
|
296 decoded->variant = VAR_IMMEDIATE; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
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5
diff
changeset
|
297 decoded->src.addr_mode = MODE_IMMEDIATE; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
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5
diff
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|
298 decoded->extra.size = size = (*istream >> 6) & 3; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
299 reg = *istream & 0x7; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
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5
diff
changeset
|
300 opmode = (*istream >> 3) & 0x7; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
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5
diff
changeset
|
301 switch (size) |
23b83d94c633
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Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
302 { |
23b83d94c633
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Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
303 case OPSIZE_BYTE: |
15
c0f339564819
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Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
304 decoded->src.params.immed = *(++istream) & 0xFF; |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
305 break; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
306 case OPSIZE_WORD: |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
307 decoded->src.params.immed = *(++istream); |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
308 break; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
309 case OPSIZE_LONG: |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
310 immed = *(++istream); |
15
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Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
311 decoded->src.params.immed = immed << 16 | *(++istream); |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
312 break; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
313 } |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
314 istream = m68k_decode_op_ex(istream, opmode, reg, size, &(decoded->dst)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
315 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
316 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
317 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
318 } |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
319 break; |
4
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
320 case 3: |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
321 decoded->op = M68K_ADD; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
322 decoded->variant = VAR_IMMEDIATE; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
323 decoded->src.addr_mode = MODE_IMMEDIATE; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
324 decoded->extra.size = size = (*istream >> 6) & 3; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
325 reg = *istream & 0x7; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
326 opmode = (*istream >> 3) & 0x7; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
327 switch (size) |
23b83d94c633
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Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
328 { |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
329 case OPSIZE_BYTE: |
15
c0f339564819
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Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
330 decoded->src.params.immed = *(++istream) & 0xFF; |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
331 break; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
332 case OPSIZE_WORD: |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
333 decoded->src.params.immed = *(++istream); |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
334 break; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
335 case OPSIZE_LONG: |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
336 immed = *(++istream); |
15
c0f339564819
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Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
337 decoded->src.params.immed = immed << 16 | *(++istream); |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
338 break; |
5
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4
diff
changeset
|
339 } |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
340 istream = m68k_decode_op_ex(istream, opmode, reg, size, &(decoded->dst)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
341 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
342 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
343 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
344 } |
4
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
345 break; |
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
346 case 4: |
5
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4
diff
changeset
|
347 //BTST, BCHG, BCLR, BSET |
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4
diff
changeset
|
348 switch ((*istream >> 6) & 0x3) |
85699517043f
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4
diff
changeset
|
349 { |
85699517043f
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Mike Pavone <pavone@retrodev.com>
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4
diff
changeset
|
350 case 0: |
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4
diff
changeset
|
351 decoded->op = M68K_BTST; |
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Mike Pavone <pavone@retrodev.com>
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4
diff
changeset
|
352 break; |
85699517043f
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Mike Pavone <pavone@retrodev.com>
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4
diff
changeset
|
353 case 1: |
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4
diff
changeset
|
354 decoded->op = M68K_BCHG; |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
355 break; |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
356 case 2: |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
357 decoded->op = M68K_BCLR; |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
358 break; |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
359 case 3: |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
360 decoded->op = M68K_BSET; |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
361 break; |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
362 } |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
363 decoded->src.addr_mode = MODE_IMMEDIATE; |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
364 decoded->src.params.immed = *(++istream) & 0xFF; |
5
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
365 istream = m68k_decode_op(istream, OPSIZE_BYTE, &(decoded->dst)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
366 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
367 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
368 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
369 } |
4
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
370 break; |
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
371 case 5: |
5
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
372 //EORI, EORI to CCR, EORI to SR |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
373 if ((*istream & 0xFF) == 0x3C) { |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
374 decoded->op = M68K_EORI_CCR; |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
375 decoded->extra.size = OPSIZE_BYTE; |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
376 decoded->src.addr_mode = MODE_IMMEDIATE; |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
377 decoded->src.params.immed = *(++istream) & 0xFF; |
5
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
378 } else if((*istream & 0xFF) == 0x7C) { |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
379 decoded->op = M68K_EORI_SR; |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
380 decoded->extra.size = OPSIZE_WORD; |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
381 decoded->src.addr_mode = MODE_IMMEDIATE; |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
382 decoded->src.params.immed = *(++istream); |
5
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
383 } else { |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
384 decoded->op = M68K_EOR; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
385 decoded->variant = VAR_IMMEDIATE; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
386 decoded->src.addr_mode = MODE_IMMEDIATE; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
387 decoded->extra.size = size = (*istream >> 6) & 3; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
388 reg = *istream & 0x7; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
389 opmode = (*istream >> 3) & 0x7; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
390 switch (size) |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
391 { |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
392 case OPSIZE_BYTE: |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
393 decoded->src.params.immed = *(++istream) & 0xFF; |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
394 break; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
395 case OPSIZE_WORD: |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
396 decoded->src.params.immed = *(++istream); |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
397 break; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
398 case OPSIZE_LONG: |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
399 immed = *(++istream); |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
400 decoded->src.params.immed = immed << 16 | *(++istream); |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
401 break; |
5
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
402 } |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
403 istream = m68k_decode_op_ex(istream, opmode, reg, size, &(decoded->dst)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
404 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
405 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
406 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
407 } |
5
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
408 } |
4
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
409 break; |
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
410 case 6: |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
411 decoded->op = M68K_CMP; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
412 decoded->variant = VAR_IMMEDIATE; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
413 decoded->extra.size = (*istream >> 6) & 0x3; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
414 decoded->src.addr_mode = MODE_IMMEDIATE; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
415 reg = *istream & 0x7; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
416 opmode = (*istream >> 3) & 0x7; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
417 switch (decoded->extra.size) |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
418 { |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
419 case OPSIZE_BYTE: |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
420 decoded->src.params.immed = *(++istream) & 0xFF; |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
421 break; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
422 case OPSIZE_WORD: |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
423 decoded->src.params.immed = *(++istream); |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
424 break; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
425 case OPSIZE_LONG: |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
426 immed = *(++istream); |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
427 decoded->src.params.immed = (immed << 16) | *(++istream); |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
428 break; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
429 } |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
430 istream = m68k_decode_op_ex(istream, opmode, reg, decoded->extra.size, &(decoded->dst)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
431 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
432 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
433 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
434 } |
4
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
435 break; |
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
436 case 7: |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
437 #ifdef M68010 |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
438 decoded->op = M68K_MOVES; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
439 decoded->extra.size = *istream >> 6 & 0x3; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
440 immed = *(++istream); |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
441 reg = immed >> 12 & 0x7; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
442 opmode = immed & 0x8000 ? MODE_AREG : MODE_REG; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
443 if (immed & 0x800) { |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
444 m68k_decode_op_ex(istream, *start >> 3 & 0x7, *start & 0x7, decoded->extra.size, &(decoded->src)); |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
445 decoded->dst.addr_mode = opmode; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
446 decoded->dst.params.regs.pri = reg; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
447 } else { |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
448 decoded->src.addr_mode = opmode; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
449 decoded->src.params.regs.pri = reg; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
450 m68k_decode_op_ex(istream, *start >> 3 & 0x7, *start & 0x7, decoded->extra.size, &(decoded->dst)); |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
451 } |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
452 #endif |
4
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
453 break; |
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
454 } |
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
455 } |
0
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
456 break; |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
457 case MOVE_BYTE: |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
458 case MOVE_LONG: |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
459 case MOVE_WORD: |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
460 decoded->op = M68K_MOVE; |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
461 decoded->extra.size = optype == MOVE_BYTE ? OPSIZE_BYTE : (optype == MOVE_WORD ? OPSIZE_WORD : OPSIZE_LONG); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
462 opmode = (*istream >> 6) & 0x7; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
463 reg = m68k_reg_quick_field(*istream); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
464 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
465 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
466 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
467 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
468 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
469 istream = m68k_decode_op_ex(istream, opmode, reg, decoded->extra.size, &(decoded->dst)); |
197
7c227a8ec53d
Add instruction address logging to translator and support for reading an address log to the disassembler
Mike Pavone <pavone@retrodev.com>
parents:
184
diff
changeset
|
470 if (!istream || decoded->dst.addr_mode == MODE_IMMEDIATE) { |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
471 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
472 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
473 } |
0
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
474 break; |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
475 case MISC: |
518
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
476 |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
477 if ((*istream & 0x1C0) == 0x1C0) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
478 decoded->op = M68K_LEA; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
479 decoded->extra.size = OPSIZE_LONG; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
480 decoded->dst.addr_mode = MODE_AREG; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
481 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
482 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
483 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
484 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
485 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
486 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
487 } else { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
488 if (*istream & 0x100) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
489 decoded->op = M68K_CHK; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
490 if ((*istream & 0x180) == 0x180) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
491 decoded->extra.size = OPSIZE_WORD; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
492 } else { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
493 //only on M68020+ |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
494 #ifdef M68020 |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
495 decoded->extra.size = OPSIZE_LONG; |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
496 #else |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
497 decoded->op = M68K_INVALID; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
498 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
499 #endif |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
500 } |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
501 decoded->dst.addr_mode = MODE_REG; |
325
8db584faac4b
Fixed decoding of CHK destination
Mike Pavone <pavone@retrodev.com>
parents:
208
diff
changeset
|
502 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
503 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
504 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
505 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
506 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
507 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
508 } else { |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
509 opmode = (*istream >> 3) & 0x7; |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
60
diff
changeset
|
510 if ((*istream & 0xB80) == 0x880 && opmode != MODE_REG && opmode != MODE_AREG) { |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
60
diff
changeset
|
511 //TODO: Check for invalid modes that are dependent on direction |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
512 decoded->op = M68K_MOVEM; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
513 decoded->extra.size = *istream & 0x40 ? OPSIZE_LONG : OPSIZE_WORD; |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
514 reg = *istream & 0x7; |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
515 if(*istream & 0x400) { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
516 decoded->dst.addr_mode = MODE_REG; |
68
1c9a4052a2c0
Fix decoding and disassembly of MOVEM
Mike Pavone <pavone@retrodev.com>
parents:
62
diff
changeset
|
517 decoded->dst.params.immed = *(++istream); |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
518 istream = m68k_decode_op_ex(istream, opmode, reg, decoded->extra.size, &(decoded->src)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
519 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
520 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
521 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
522 } |
412
00d5a2b532f4
Fix movem with pc displacement or pc indexed source
Mike Pavone <pavone@retrodev.com>
parents:
325
diff
changeset
|
523 if (decoded->src.addr_mode == MODE_PC_DISPLACE || decoded->src.addr_mode == MODE_PC_INDEX_DISP8) { |
00d5a2b532f4
Fix movem with pc displacement or pc indexed source
Mike Pavone <pavone@retrodev.com>
parents:
325
diff
changeset
|
524 //adjust displacement to account for extra instruction word |
00d5a2b532f4
Fix movem with pc displacement or pc indexed source
Mike Pavone <pavone@retrodev.com>
parents:
325
diff
changeset
|
525 decoded->src.params.regs.displacement += 2; |
00d5a2b532f4
Fix movem with pc displacement or pc indexed source
Mike Pavone <pavone@retrodev.com>
parents:
325
diff
changeset
|
526 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
527 } else { |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
528 decoded->src.addr_mode = MODE_REG; |
68
1c9a4052a2c0
Fix decoding and disassembly of MOVEM
Mike Pavone <pavone@retrodev.com>
parents:
62
diff
changeset
|
529 decoded->src.params.immed = *(++istream); |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
530 istream = m68k_decode_op_ex(istream, opmode, reg, decoded->extra.size, &(decoded->dst)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
531 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
532 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
533 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
534 } |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
535 } |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
536 } else { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
537 optype = (*istream >> 9) & 0x7; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
538 size = (*istream >> 6) & 0x3; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
539 switch(optype) |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
540 { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
541 case 0: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
542 //Move from SR or NEGX |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
543 if (size == OPSIZE_INVALID) { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
544 decoded->op = M68K_MOVE_FROM_SR; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
545 size = OPSIZE_WORD; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
546 } else { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
547 decoded->op = M68K_NEGX; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
548 } |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
549 decoded->extra.size = size; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
550 istream= m68k_decode_op(istream, size, &(decoded->dst)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
551 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
552 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
553 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
554 } |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
555 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
556 case 1: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
557 //MOVE from CCR or CLR |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
558 if (size == OPSIZE_INVALID) { |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
559 #ifdef M68010 |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
560 decoded->op = M68K_MOVE_FROM_CCR; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
561 size = OPSIZE_WORD; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
562 #else |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
563 break; |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
564 #endif |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
565 } else { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
566 decoded->op = M68K_CLR; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
567 } |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
568 decoded->extra.size = size; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
569 istream= m68k_decode_op(istream, size, &(decoded->dst)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
570 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
571 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
572 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
573 } |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
574 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
575 case 2: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
576 //MOVE to CCR or NEG |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
577 if (size == OPSIZE_INVALID) { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
578 decoded->op = M68K_MOVE_CCR; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
579 size = OPSIZE_WORD; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
580 istream= m68k_decode_op(istream, size, &(decoded->src)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
581 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
582 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
583 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
584 } |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
585 } else { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
586 decoded->op = M68K_NEG; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
587 istream= m68k_decode_op(istream, size, &(decoded->dst)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
588 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
589 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
590 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
591 } |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
592 } |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
593 decoded->extra.size = size; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
594 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
595 case 3: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
596 //MOVE to SR or NOT |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
597 if (size == OPSIZE_INVALID) { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
598 decoded->op = M68K_MOVE_SR; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
599 size = OPSIZE_WORD; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
600 istream= m68k_decode_op(istream, size, &(decoded->src)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
601 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
602 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
603 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
604 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
605 } else { |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
606 decoded->op = M68K_NOT; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
607 istream= m68k_decode_op(istream, size, &(decoded->dst)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
608 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
609 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
610 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
611 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
612 } |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
613 decoded->extra.size = size; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
614 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
615 case 4: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
616 //EXT, EXTB, LINK.l, NBCD, SWAP, BKPT, PEA |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
617 switch((*istream >> 3) & 0x3F) |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
618 { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
619 case 1: |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
620 #ifdef M68020 |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
621 decoded->op = M68K_LINK; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
622 decoded->extra.size = OPSIZE_LONG; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
623 reg = *istream & 0x7; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
624 immed = *(++istream) << 16; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
625 immed |= *(++istream); |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
626 #endif |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
627 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
628 case 8: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
629 decoded->op = M68K_SWAP; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
630 decoded->src.addr_mode = MODE_REG; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
631 decoded->src.params.regs.pri = *istream & 0x7; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
632 decoded->extra.size = OPSIZE_WORD; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
633 break; |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
634 case 9: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
635 #ifdef M68010 |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
636 decoded->op = M68K_BKPT; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
637 decoded->src.addr_mode = MODE_IMMEDIATE; |
10
4553fc97b15e
Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special cases
Mike Pavone <pavone@retrodev.com>
parents:
9
diff
changeset
|
638 decoded->extra.size = OPSIZE_UNSIZED; |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
639 decoded->src.params.immed = *istream & 0x7; |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
640 #endif |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
641 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
642 case 0x10: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
643 decoded->op = M68K_EXT; |
93
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
91
diff
changeset
|
644 decoded->dst.addr_mode = MODE_REG; |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
91
diff
changeset
|
645 decoded->dst.params.regs.pri = *istream & 0x7; |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
646 decoded->extra.size = OPSIZE_WORD; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
647 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
648 case 0x18: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
649 decoded->op = M68K_EXT; |
93
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
91
diff
changeset
|
650 decoded->dst.addr_mode = MODE_REG; |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
91
diff
changeset
|
651 decoded->dst.params.regs.pri = *istream & 0x7; |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
652 decoded->extra.size = OPSIZE_LONG; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
653 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
654 case 0x38: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
655 #ifdef M68020 |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
656 #endif |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
657 break; |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
658 default: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
659 if (!(*istream & 0x1C0)) { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
660 decoded->op = M68K_NBCD; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
661 decoded->extra.size = OPSIZE_BYTE; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
662 istream = m68k_decode_op(istream, OPSIZE_BYTE, &(decoded->dst)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
663 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
664 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
665 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
666 } |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
667 } else if((*istream & 0x1C0) == 0x40) { |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
668 decoded->op = M68K_PEA; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
669 decoded->extra.size = OPSIZE_LONG; |
116
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
111
diff
changeset
|
670 istream = m68k_decode_op(istream, OPSIZE_LONG, &(decoded->src)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
671 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
672 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
673 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
674 } |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
675 } |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
676 } |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
677 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
678 case 5: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
679 //BGND, ILLEGAL, TAS, TST |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
680 optype = *istream & 0xFF; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
681 if (optype == 0xFA) { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
682 //BGND - CPU32 only |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
683 } else if (optype == 0xFC) { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
684 decoded->op = M68K_ILLEGAL; |
10
4553fc97b15e
Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special cases
Mike Pavone <pavone@retrodev.com>
parents:
9
diff
changeset
|
685 decoded->extra.size = OPSIZE_UNSIZED; |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
686 } else { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
687 if (size == OPSIZE_INVALID) { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
688 decoded->op = M68K_TAS; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
689 } else { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
690 decoded->op = M68K_TST; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
691 decoded->extra.size = size; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
692 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
693 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
694 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
695 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
696 } |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
697 } |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
698 } |
518
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
699 break; |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
700 case 6: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
701 //MULU, MULS, DIVU, DIVUL, DIVS, DIVSL |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
702 #ifdef M68020 |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
703 //TODO: Implement these for 68020+ support |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
704 #endif |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
705 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
706 case 7: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
707 //TRAP, LINK.w, UNLNK, MOVE USP, RESET, NOP, STOP, RTE, RTD, RTS, TRAPV, RTR, MOVEC, JSR, JMP |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
708 if (*istream & 0x80) { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
709 //JSR, JMP |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
710 if (*istream & 0x40) { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
711 decoded->op = M68K_JMP; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
712 } else { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
713 decoded->op = M68K_JSR; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
714 } |
10
4553fc97b15e
Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special cases
Mike Pavone <pavone@retrodev.com>
parents:
9
diff
changeset
|
715 decoded->extra.size = OPSIZE_UNSIZED; |
4553fc97b15e
Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special cases
Mike Pavone <pavone@retrodev.com>
parents:
9
diff
changeset
|
716 istream = m68k_decode_op(istream, OPSIZE_UNSIZED, &(decoded->src)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
717 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
718 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
719 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
720 } |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
721 } else { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
722 //it would appear bit 6 needs to be set for it to be a valid instruction here |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
723 switch((*istream >> 3) & 0x7) |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
724 { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
725 case 0: |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
726 case 1: |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
727 //TRAP |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
728 decoded->op = M68K_TRAP; |
10
4553fc97b15e
Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special cases
Mike Pavone <pavone@retrodev.com>
parents:
9
diff
changeset
|
729 decoded->extra.size = OPSIZE_UNSIZED; |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
730 decoded->src.addr_mode = MODE_IMMEDIATE; |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
731 decoded->src.params.immed = *istream & 0xF; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
732 break; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
733 case 2: |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
734 //LINK.w |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
735 decoded->op = M68K_LINK; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
736 decoded->extra.size = OPSIZE_WORD; |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
737 decoded->src.addr_mode = MODE_AREG; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
738 decoded->src.params.regs.pri = *istream & 0x7; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
739 decoded->dst.addr_mode = MODE_IMMEDIATE; |
93
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
91
diff
changeset
|
740 decoded->dst.params.immed = sign_extend16(*(++istream)); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
741 break; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
742 case 3: |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
743 //UNLK |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
744 decoded->op = M68K_UNLK; |
10
4553fc97b15e
Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special cases
Mike Pavone <pavone@retrodev.com>
parents:
9
diff
changeset
|
745 decoded->extra.size = OPSIZE_UNSIZED; |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
746 decoded->dst.addr_mode = MODE_AREG; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
747 decoded->dst.params.regs.pri = *istream & 0x7; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
748 break; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
749 case 4: |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
750 case 5: |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
751 //MOVE USP |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
752 decoded->op = M68K_MOVE_USP; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
753 if (*istream & 0x8) { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
754 decoded->dst.addr_mode = MODE_AREG; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
755 decoded->dst.params.regs.pri = *istream & 0x7; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
756 } else { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
757 decoded->src.addr_mode = MODE_AREG; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
758 decoded->src.params.regs.pri = *istream & 0x7; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
759 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
760 break; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
761 case 6: |
10
4553fc97b15e
Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special cases
Mike Pavone <pavone@retrodev.com>
parents:
9
diff
changeset
|
762 decoded->extra.size = OPSIZE_UNSIZED; |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
763 switch(*istream & 0x7) |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
764 { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
765 case 0: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
766 decoded->op = M68K_RESET; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
767 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
768 case 1: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
769 decoded->op = M68K_NOP; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
770 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
771 case 2: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
772 decoded->op = M68K_STOP; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
773 decoded->src.addr_mode = MODE_IMMEDIATE; |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
774 decoded->src.params.immed =*(++istream); |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
775 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
776 case 3: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
777 decoded->op = M68K_RTE; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
778 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
779 case 4: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
780 #ifdef M68010 |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
781 decoded->op = M68K_RTD; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
782 decoded->src.addr_mode = MODE_IMMEDIATE; |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
783 decoded->src.params.immed =*(++istream); |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
784 #endif |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
785 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
786 case 5: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
787 decoded->op = M68K_RTS; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
788 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
789 case 6: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
790 decoded->op = M68K_TRAPV; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
791 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
792 case 7: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
793 decoded->op = M68K_RTR; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
794 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
795 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
796 break; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
797 case 7: |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
798 //MOVEC |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
799 #ifdef M68010 |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
800 decoded->op = M68K_MOVEC; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
801 immed = *(++istream); |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
802 reg = immed >> 12 & 0x7; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
803 opmode = immed & 0x8000 ? MODE_AREG : MODE_REG; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
804 if (immed & 0x800) { |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
805 if (immed > MAX_HIGH_CR) { |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
806 decoded->op = M68K_INVALID; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
807 break; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
808 } else { |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
809 immed = immed - 0x800 + CR_USP; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
810 } |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
811 } else { |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
812 if (immed > MAX_LOW_CR) { |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
813 decoded->op = M68K_INVALID; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
814 break; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
815 } |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
816 } |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
817 if (*start & 1) { |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
818 decoded->src.addr_mode = opmode; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
819 decoded->src.params.regs.pri = reg; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
820 decoded->dst.params.immed = immed; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
821 } else { |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
822 decoded->dst.addr_mode = opmode; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
823 decoded->dst.params.regs.pri = reg; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
824 decoded->src.params.immed = immed; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
825 } |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
826 #endif |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
827 break; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
828 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
829 } |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
830 break; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
831 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
832 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
833 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
834 } |
0
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
835 break; |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
836 case QUICK_ARITH_LOOP: |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
837 size = (*istream >> 6) & 3; |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
838 if (size == 0x3) { |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
839 //DBcc, TRAPcc or Scc |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
840 m68k_decode_cond(*istream, decoded); |
111 | 841 if (((*istream >> 3) & 0x7) == 1) { |
0
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
842 decoded->op = M68K_DBCC; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
843 decoded->src.addr_mode = MODE_IMMEDIATE; |
0
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
844 decoded->dst.addr_mode = MODE_REG; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
845 decoded->dst.params.regs.pri = *istream & 0x7; |
46
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
18
diff
changeset
|
846 decoded->src.params.immed = sign_extend16(*(++istream)); |
111 | 847 } else if(((*istream >> 3) & 0x7) == 1 && (*istream & 0x7) > 1 && (*istream & 0x7) < 5) { |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
848 #ifdef M68020 |
0
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
849 decoded->op = M68K_TRAPCC; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
850 decoded->src.addr_mode = MODE_IMMEDIATE; |
0
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
851 //TODO: Figure out what to do with OPMODE and optional extention words |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
852 #endif |
111 | 853 } else { |
0
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
854 decoded->op = M68K_SCC; |
111 | 855 decoded->extra.cond = (*istream >> 8) & 0xF; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
856 istream = m68k_decode_op(istream, OPSIZE_BYTE, &(decoded->dst)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
857 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
858 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
859 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
860 } |
0
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
861 } |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
862 } else { |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
863 //ADDQ, SUBQ |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
864 decoded->variant = VAR_QUICK; |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
865 decoded->extra.size = size; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
866 decoded->src.addr_mode = MODE_IMMEDIATE; |
91
8c446fc19cc0
Fix decoding bug in addq/subq
Mike Pavone <pavone@retrodev.com>
parents:
90
diff
changeset
|
867 immed = m68k_reg_quick_field(*istream); |
0
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
868 if (!immed) { |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
869 immed = 8; |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
870 } |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
871 decoded->src.params.immed = immed; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
872 if (*istream & 0x100) { |
0
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
873 decoded->op = M68K_SUB; |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
874 } else { |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
875 decoded->op = M68K_ADD; |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
876 } |
94
a668a35a3463
Fix decoding bug for addq/subq
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
877 istream = m68k_decode_op(istream, size, &(decoded->dst)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
878 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
879 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
880 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
881 } |
0
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
882 } |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
883 break; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
884 case BRANCH: |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
885 m68k_decode_cond(*istream, decoded); |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
886 decoded->op = decoded->extra.cond == COND_FALSE ? M68K_BSR : M68K_BCC; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
887 decoded->src.addr_mode = MODE_IMMEDIATE; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
888 immed = *istream & 0xFF; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
889 if (immed == 0) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
890 decoded->variant = VAR_WORD; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
891 immed = *(++istream); |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
892 immed = sign_extend16(immed); |
154
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
140
diff
changeset
|
893 #ifdef M68020 |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
894 } else if (immed == 0xFF) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
895 decoded->variant = VAR_LONG; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
896 immed = *(++istream) << 16; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
897 immed |= *(++istream); |
154
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
140
diff
changeset
|
898 #endif |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
899 } else { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
900 decoded->variant = VAR_BYTE; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
901 immed = sign_extend8(immed); |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
902 } |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
903 decoded->src.params.immed = immed; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
904 break; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
905 case MOVEQ: |
208
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
197
diff
changeset
|
906 if (*istream & 0x100) { |
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
197
diff
changeset
|
907 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
908 break; |
208
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
197
diff
changeset
|
909 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
910 decoded->op = M68K_MOVE; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
911 decoded->variant = VAR_QUICK; |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
912 decoded->extra.size = OPSIZE_LONG; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
913 decoded->src.addr_mode = MODE_IMMEDIATE; |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
914 decoded->src.params.immed = sign_extend8(*istream & 0xFF); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
915 decoded->dst.addr_mode = MODE_REG; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
916 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
917 immed = *istream & 0xFF; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
918 break; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
919 case OR_DIV_SBCD: |
11
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
920 //for OR, if opmode bit 2 is 1, then src = Dn, dst = <ea> |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
921 opmode = (*istream >> 6) & 0x7; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
922 size = opmode & 0x3; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
923 if (size == OPSIZE_INVALID || (opmode & 0x4 && !(*istream & 0x30))) { |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
924 switch(opmode) |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
925 { |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
926 case 3: |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
927 decoded->op = M68K_DIVU; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
928 decoded->extra.size = OPSIZE_WORD; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
929 decoded->dst.addr_mode = MODE_REG; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
930 decoded->dst.params.regs.pri = (*istream >> 9) & 0x7; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
931 istream = m68k_decode_op(istream, OPSIZE_WORD, &(decoded->src)); |
183
2f08d9e90a4c
Fix (a7)+ src when size is byte, fix trap return address, make div with areg src decoded to invalid
Mike Pavone <pavone@retrodev.com>
parents:
181
diff
changeset
|
932 if (!istream || decoded->src.addr_mode == MODE_AREG) { |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
933 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
934 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
935 } |
11
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
936 break; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
937 case 4: |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
938 decoded->op = M68K_SBCD; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
939 decoded->dst.addr_mode = decoded->src.addr_mode = *istream & 0x8 ? MODE_AREG_PREDEC : MODE_REG; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
940 decoded->src.params.regs.pri = *istream & 0x7; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
941 decoded->dst.params.regs.pri = (*istream >> 9) & 0x7; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
942 break; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
943 case 5: |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
944 #ifdef M68020 |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
945 #endif |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
946 break; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
947 case 6: |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
948 #ifdef M68020 |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
949 #endif |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
950 break; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
951 case 7: |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
952 decoded->op = M68K_DIVS; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
953 decoded->extra.size = OPSIZE_WORD; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
954 decoded->dst.addr_mode = MODE_REG; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
955 decoded->dst.params.regs.pri = (*istream >> 9) & 0x7; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
956 istream = m68k_decode_op(istream, OPSIZE_WORD, &(decoded->src)); |
183
2f08d9e90a4c
Fix (a7)+ src when size is byte, fix trap return address, make div with areg src decoded to invalid
Mike Pavone <pavone@retrodev.com>
parents:
181
diff
changeset
|
957 if (!istream || decoded->src.addr_mode == MODE_AREG) { |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
958 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
959 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
960 } |
518
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
961 break; |
11
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
962 } |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
963 } else { |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
964 decoded->op = M68K_OR; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
965 decoded->extra.size = size; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
966 if (opmode & 0x4) { |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
967 decoded->src.addr_mode = MODE_REG; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
968 decoded->src.params.regs.pri = (*istream >> 9) & 0x7; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
969 istream = m68k_decode_op(istream, size, &(decoded->dst)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
970 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
971 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
972 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
973 } |
11
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
974 } else { |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
975 decoded->dst.addr_mode = MODE_REG; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
976 decoded->dst.params.regs.pri = (*istream >> 9) & 0x7; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
977 istream = m68k_decode_op(istream, size, &(decoded->src)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
978 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
979 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
980 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
981 } |
11
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
982 } |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
983 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
984 break; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
985 case SUB_SUBX: |
101
d7789186ba5e
Some fixes to add/addx sub/subx decoding
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
986 size = (*istream >> 6) & 0x3; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
987 decoded->op = M68K_SUB; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
988 if (*istream & 0x100) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
989 //<ea> destination, SUBA.l or SUBX |
101
d7789186ba5e
Some fixes to add/addx sub/subx decoding
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
990 if (*istream & 0x30 || size == OPSIZE_INVALID) { |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
991 if (size == OPSIZE_INVALID) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
992 //SUBA.l |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
993 decoded->extra.size = OPSIZE_LONG; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
994 decoded->dst.addr_mode = MODE_AREG; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
995 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
996 istream = m68k_decode_op(istream, OPSIZE_LONG, &(decoded->src)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
997 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
998 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
999 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1000 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1001 } else { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1002 decoded->extra.size = size; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1003 decoded->src.addr_mode = MODE_REG; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
1004 decoded->src.params.regs.pri = m68k_reg_quick_field(*istream); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1005 istream = m68k_decode_op(istream, size, &(decoded->dst)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1006 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1007 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1008 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1009 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1010 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1011 } else { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1012 //SUBX |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1013 decoded->op = M68K_SUBX; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1014 decoded->extra.size = size; |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1015 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1016 decoded->src.params.regs.pri = *istream & 0x7; |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1017 if (*istream & 0x8) { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1018 decoded->dst.addr_mode = decoded->src.addr_mode = MODE_AREG_PREDEC; |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1019 } else { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1020 decoded->dst.addr_mode = decoded->src.addr_mode = MODE_REG; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1021 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1022 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1023 } else { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1024 if (size == OPSIZE_INVALID) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1025 //SUBA.w |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1026 decoded->extra.size = OPSIZE_WORD; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1027 decoded->dst.addr_mode = MODE_AREG; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1028 } else { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1029 decoded->extra.size = size; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1030 decoded->dst.addr_mode = MODE_REG; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1031 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
1032 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1033 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1034 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1035 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1036 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1037 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1038 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1039 break; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1040 case RESERVED: |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1041 break; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1042 case CMP_XOR: |
120 | 1043 size = (*istream >> 6) & 0x3; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1044 decoded->op = M68K_CMP; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1045 if (*istream & 0x100) { |
120 | 1046 //CMPM or CMPA.l or EOR |
1047 if (size == OPSIZE_INVALID) { | |
1048 decoded->extra.size = OPSIZE_LONG; | |
1049 decoded->dst.addr_mode = MODE_AREG; | |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
1050 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream); |
136
e64554246d11
Fix some bugs in decoding cmp
Mike Pavone <pavone@retrodev.com>
parents:
134
diff
changeset
|
1051 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1052 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1053 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1054 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1055 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1056 } else { |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1057 reg = m68k_reg_quick_field(*istream); |
120 | 1058 istream = m68k_decode_op(istream, size, &(decoded->dst)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1059 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1060 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1061 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1062 } |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
176
diff
changeset
|
1063 decoded->extra.size = size; |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
176
diff
changeset
|
1064 if (decoded->dst.addr_mode == MODE_AREG) { |
120 | 1065 //CMPM |
1066 decoded->src.addr_mode = decoded->dst.addr_mode = MODE_AREG_POSTINC; | |
1067 decoded->src.params.regs.pri = decoded->dst.params.regs.pri; | |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1068 decoded->dst.params.regs.pri = reg; |
120 | 1069 } else { |
1070 //EOR | |
1071 decoded->op = M68K_EOR; | |
1072 decoded->src.addr_mode = MODE_REG; | |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1073 decoded->src.params.regs.pri = reg; |
120 | 1074 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1075 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1076 } else { |
120 | 1077 //CMP or CMPA.w |
1078 if (size == OPSIZE_INVALID) { | |
1079 decoded->extra.size = OPSIZE_WORD; | |
1080 decoded->dst.addr_mode = MODE_AREG; | |
1081 } else { | |
1082 decoded->extra.size = size; | |
1083 decoded->dst.addr_mode = MODE_REG; | |
1084 } | |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
1085 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream); |
136
e64554246d11
Fix some bugs in decoding cmp
Mike Pavone <pavone@retrodev.com>
parents:
134
diff
changeset
|
1086 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1087 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1088 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1089 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1090 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1091 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1092 break; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1093 case AND_MUL_ABCD_EXG: |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1094 //page 575 for summary |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1095 //EXG opmodes: |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1096 //01000 -data regs |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1097 //01001 -addr regs |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1098 //10001 -one of each |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1099 //AND opmodes: |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1100 //operand order bit + 2 size bits (00 - 10) |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1101 //no address register direct addressing |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1102 //data register direct not allowed when <ea> is the source (operand order bit of 1) |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1103 if (*istream & 0x100) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1104 if ((*istream & 0xC0) == 0xC0) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1105 decoded->op = M68K_MULS; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1106 decoded->extra.size = OPSIZE_WORD; |
3
a4ad0e3e3e0e
Finish mulu.w, muls.w and abcd parameter decoding
Mike Pavone <pavone@retrodev.com>
parents:
2
diff
changeset
|
1107 decoded->dst.addr_mode = MODE_REG; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
1108 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1109 istream = m68k_decode_op(istream, OPSIZE_WORD, &(decoded->src)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1110 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1111 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1112 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1113 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1114 } else if(!(*istream & 0xF0)) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1115 decoded->op = M68K_ABCD; |
3
a4ad0e3e3e0e
Finish mulu.w, muls.w and abcd parameter decoding
Mike Pavone <pavone@retrodev.com>
parents:
2
diff
changeset
|
1116 decoded->extra.size = OPSIZE_BYTE; |
a4ad0e3e3e0e
Finish mulu.w, muls.w and abcd parameter decoding
Mike Pavone <pavone@retrodev.com>
parents:
2
diff
changeset
|
1117 decoded->src.params.regs.pri = *istream & 0x7; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
1118 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream); |
3
a4ad0e3e3e0e
Finish mulu.w, muls.w and abcd parameter decoding
Mike Pavone <pavone@retrodev.com>
parents:
2
diff
changeset
|
1119 decoded->dst.addr_mode = decoded->src.addr_mode = (*istream & 8) ? MODE_AREG_PREDEC : MODE_REG; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1120 } else if(!(*istream & 0x30)) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1121 decoded->op = M68K_EXG; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1122 decoded->extra.size = OPSIZE_LONG; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
1123 decoded->src.params.regs.pri = m68k_reg_quick_field(*istream); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1124 decoded->dst.params.regs.pri = *istream & 0x7; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1125 if (*istream & 0x8) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1126 if (*istream & 0x80) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1127 decoded->src.addr_mode = MODE_REG; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1128 decoded->dst.addr_mode = MODE_AREG; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1129 } else { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1130 decoded->src.addr_mode = decoded->dst.addr_mode = MODE_AREG; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1131 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1132 } else { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1133 decoded->src.addr_mode = decoded->dst.addr_mode = MODE_REG; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1134 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1135 } else { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1136 decoded->op = M68K_AND; |
90 | 1137 decoded->extra.size = (*istream >> 6) & 0x3; |
60
6ffea8607730
Fix operand order for AND instructions
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1138 decoded->src.addr_mode = MODE_REG; |
6ffea8607730
Fix operand order for AND instructions
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1139 decoded->src.params.regs.pri = m68k_reg_quick_field(*istream); |
6ffea8607730
Fix operand order for AND instructions
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1140 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->dst)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1141 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1142 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1143 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1144 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1145 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1146 } else { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1147 if ((*istream & 0xC0) == 0xC0) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1148 decoded->op = M68K_MULU; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1149 decoded->extra.size = OPSIZE_WORD; |
3
a4ad0e3e3e0e
Finish mulu.w, muls.w and abcd parameter decoding
Mike Pavone <pavone@retrodev.com>
parents:
2
diff
changeset
|
1150 decoded->dst.addr_mode = MODE_REG; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
1151 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1152 istream = m68k_decode_op(istream, OPSIZE_WORD, &(decoded->src)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1153 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1154 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1155 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1156 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1157 } else { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1158 decoded->op = M68K_AND; |
90 | 1159 decoded->extra.size = (*istream >> 6) & 0x3; |
60
6ffea8607730
Fix operand order for AND instructions
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1160 decoded->dst.addr_mode = MODE_REG; |
6ffea8607730
Fix operand order for AND instructions
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1161 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream); |
6ffea8607730
Fix operand order for AND instructions
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1162 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1163 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1164 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1165 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1166 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1167 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1168 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1169 break; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1170 case ADD_ADDX: |
101
d7789186ba5e
Some fixes to add/addx sub/subx decoding
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
1171 size = (*istream >> 6) & 0x3; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1172 decoded->op = M68K_ADD; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1173 if (*istream & 0x100) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1174 //<ea> destination, ADDA.l or ADDX |
101
d7789186ba5e
Some fixes to add/addx sub/subx decoding
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
1175 if (*istream & 0x30 || size == OPSIZE_INVALID) { |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1176 if (size == OPSIZE_INVALID) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1177 //ADDA.l |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1178 decoded->extra.size = OPSIZE_LONG; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1179 decoded->dst.addr_mode = MODE_AREG; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
1180 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1181 istream = m68k_decode_op(istream, OPSIZE_LONG, &(decoded->src)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1182 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1183 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1184 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1185 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1186 } else { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1187 decoded->extra.size = size; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1188 decoded->src.addr_mode = MODE_REG; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
1189 decoded->src.params.regs.pri = m68k_reg_quick_field(*istream); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1190 istream = m68k_decode_op(istream, size, &(decoded->dst)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1191 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1192 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1193 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1194 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1195 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1196 } else { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1197 //ADDX |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1198 decoded->op = M68K_ADDX; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1199 decoded->extra.size = size; |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1200 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1201 decoded->src.params.regs.pri = *istream & 0x7; |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1202 if (*istream & 0x8) { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1203 decoded->dst.addr_mode = decoded->src.addr_mode = MODE_AREG_PREDEC; |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1204 } else { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1205 decoded->dst.addr_mode = decoded->src.addr_mode = MODE_REG; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1206 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1207 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1208 } else { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1209 if (size == OPSIZE_INVALID) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1210 //ADDA.w |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1211 decoded->extra.size = OPSIZE_WORD; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1212 decoded->dst.addr_mode = MODE_AREG; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1213 } else { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1214 decoded->extra.size = size; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1215 decoded->dst.addr_mode = MODE_REG; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1216 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
1217 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1218 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1219 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1220 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1221 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1222 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1223 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1224 break; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1225 case SHIFT_ROTATE: |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1226 if ((*istream & 0x8C0) == 0xC0) { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1227 switch((*istream >> 8) & 0x7) |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1228 { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1229 case 0: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1230 decoded->op = M68K_ASR; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1231 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1232 case 1: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1233 decoded->op = M68K_ASL; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1234 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1235 case 2: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1236 decoded->op = M68K_LSR; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1237 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1238 case 3: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1239 decoded->op = M68K_LSL; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1240 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1241 case 4: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1242 decoded->op = M68K_ROXR; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1243 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1244 case 5: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1245 decoded->op = M68K_ROXL; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1246 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1247 case 6: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1248 decoded->op = M68K_ROR; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1249 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1250 case 7: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1251 decoded->op = M68K_ROL; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1252 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1253 } |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1254 decoded->extra.size = OPSIZE_WORD; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1255 istream = m68k_decode_op(istream, OPSIZE_WORD, &(decoded->dst)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1256 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1257 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1258 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1259 } |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1260 } else if((*istream & 0xC0) != 0xC0) { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1261 switch(((*istream >> 2) & 0x6) | ((*istream >> 8) & 1)) |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1262 { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1263 case 0: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1264 decoded->op = M68K_ASR; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1265 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1266 case 1: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1267 decoded->op = M68K_ASL; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1268 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1269 case 2: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1270 decoded->op = M68K_LSR; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1271 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1272 case 3: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1273 decoded->op = M68K_LSL; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1274 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1275 case 4: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1276 decoded->op = M68K_ROXR; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1277 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1278 case 5: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1279 decoded->op = M68K_ROXL; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1280 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1281 case 6: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1282 decoded->op = M68K_ROR; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1283 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1284 case 7: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1285 decoded->op = M68K_ROL; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1286 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1287 } |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1288 decoded->extra.size = (*istream >> 6) & 0x3; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1289 immed = (*istream >> 9) & 0x7; |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
50
diff
changeset
|
1290 if (*istream & 0x20) { |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1291 decoded->src.addr_mode = MODE_REG; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1292 decoded->src.params.regs.pri = immed; |
50
4836d1f3841a
Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1293 } else { |
4836d1f3841a
Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1294 decoded->src.addr_mode = MODE_IMMEDIATE; |
4836d1f3841a
Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1295 if (!immed) { |
4836d1f3841a
Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1296 immed = 8; |
4836d1f3841a
Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1297 } |
4836d1f3841a
Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1298 decoded->src.params.immed = immed; |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1299 } |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1300 decoded->dst.addr_mode = MODE_REG; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1301 decoded->dst.params.regs.pri = *istream & 0x7; |
518
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1302 |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1303 } else { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1304 #ifdef M68020 |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1305 //TODO: Implement bitfield instructions for M68020+ support |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1306 switch (*istream >> 8 & 7) |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1307 { |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1308 case 0: |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1309 decoded->op = M68K_BFTST; //<ea> |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1310 break; |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1311 case 1: |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1312 decoded->op = M68K_BFEXTU; //<ea>, Dn |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1313 break; |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1314 case 2: |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1315 decoded->op = M68K_BFCHG; //<ea> |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1316 break; |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1317 case 3: |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1318 decoded->op = M68K_BFEXTS; //<ea>, Dn |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1319 break; |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1320 case 4: |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1321 decoded->op = M68K_BFCLR; //<ea> |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1322 break; |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1323 case 5: |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1324 decoded->op = M68K_BFFFO; //<ea>, Dn |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1325 break; |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1326 case 6: |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1327 decoded->op = M68K_BFSET; //<ea> |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1328 break; |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1329 case 7: |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1330 decoded->op = M68K_BFINS; //Dn, <ea> |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1331 break; |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1332 } |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1333 opmode = *istream >> 3 & 0x7; |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1334 reg = *istream & 0x7; |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1335 m68k_op_info *ea, *other; |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1336 if (decoded->op == M68K_BFEXTU || decoded->op == M68K_BFEXTS || decoded->op == M68K_BFFFO) |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1337 { |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1338 ea = &(decoded->src); |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1339 other = &(decoded->dst); |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1340 } else { |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1341 ea = &(decoded->dst); |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1342 other = &(decoded->dst); |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1343 } |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1344 if (*istream & 0x100) |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1345 { |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1346 immed = *(istream++); |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1347 other->addr_mode = MODE_REG; |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1348 other->params.regs.pri = immed >> 12 & 0x7; |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1349 } else { |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1350 immed = *(istream++); |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1351 } |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1352 decoded->extra.size = OPSIZE_UNSIZED; |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1353 istream = m68k_decode_op_ex(istream, opmode, reg, decoded->extra.size, ea); |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1354 ea->addr_mode |= M68K_FLAG_BITFIELD; |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1355 ea->bitfield = immed & 0xFFF; |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1356 #endif |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1357 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1358 break; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1359 case COPROC: |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1360 //TODO: Implement me |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1361 break; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1362 } |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1363 if (decoded->op == M68K_INVALID) { |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1364 decoded->src.params.immed = *start; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1365 return start + 1; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1366 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1367 return istream+1; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1368 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1369 |
518
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1370 uint32_t m68k_branch_target(m68kinst * inst, uint32_t *dregs, uint32_t *aregs) |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1371 { |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1372 if(inst->op == M68K_BCC || inst->op == M68K_BSR || inst->op == M68K_DBCC) { |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1373 return inst->address + 2 + inst->src.params.immed; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1374 } else if(inst->op == M68K_JMP || inst->op == M68K_JSR) { |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1375 uint32_t ret = 0; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1376 switch(inst->src.addr_mode) |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1377 { |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1378 case MODE_AREG_INDIRECT: |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1379 ret = aregs[inst->src.params.regs.pri]; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1380 break; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1381 case MODE_AREG_INDEX_DISP8: { |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1382 uint8_t sec_reg = inst->src.params.regs.sec >> 1 & 0x7; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1383 ret = aregs[inst->src.params.regs.pri]; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1384 uint32_t * regfile = inst->src.params.regs.sec & 0x10 ? aregs : dregs; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1385 if (inst->src.params.regs.sec & 1) { |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1386 //32-bit index register |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1387 ret += regfile[sec_reg]; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1388 } else { |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1389 //16-bit index register |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1390 if (regfile[sec_reg] & 0x8000) { |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1391 ret += (0xFFFF0000 | regfile[sec_reg]); |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1392 } else { |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1393 ret += regfile[sec_reg]; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1394 } |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1395 } |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1396 ret += inst->src.params.regs.displacement; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1397 break; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1398 } |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1399 case MODE_PC_DISPLACE: |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1400 ret = inst->src.params.regs.displacement + inst->address + 2; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1401 break; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1402 case MODE_PC_INDEX_DISP8: { |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1403 uint8_t sec_reg = inst->src.params.regs.sec >> 1 & 0x7; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1404 ret = inst->address + 2; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1405 uint32_t * regfile = inst->src.params.regs.sec & 0x10 ? aregs : dregs; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1406 if (inst->src.params.regs.sec & 1) { |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1407 //32-bit index register |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1408 ret += regfile[sec_reg]; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1409 } else { |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1410 //16-bit index register |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1411 if (regfile[sec_reg] & 0x8000) { |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1412 ret += (0xFFFF0000 | regfile[sec_reg]); |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1413 } else { |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1414 ret += regfile[sec_reg]; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1415 } |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1416 } |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1417 ret += inst->src.params.regs.displacement; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1418 break; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1419 } |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1420 case MODE_ABSOLUTE: |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1421 case MODE_ABSOLUTE_SHORT: |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1422 ret = inst->src.params.immed; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1423 break; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1424 } |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1425 return ret; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1426 } |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1427 return 0; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1428 } |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1429 |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1430 uint8_t m68k_is_branch(m68kinst * inst) |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1431 { |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1432 return (inst->op == M68K_BCC && inst->extra.cond != COND_FALSE) |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1433 || (inst->op == M68K_DBCC && inst->extra.cond != COND_TRUE) |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1434 || inst->op == M68K_BSR || inst->op == M68K_JMP || inst->op == M68K_JSR; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1435 } |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1436 |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1437 uint8_t m68k_is_noncall_branch(m68kinst * inst) |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1438 { |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1439 return m68k_is_branch(inst) && inst->op != M68K_BSR && inst->op != M68K_JSR; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1440 } |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1441 |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1442 |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1443 char * mnemonics[] = { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1444 "abcd", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1445 "add", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1446 "addx", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1447 "and", |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1448 "andi",//ccr |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1449 "andi",//sr |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1450 "asl", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1451 "asr", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1452 "bcc", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1453 "bchg", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1454 "bclr", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1455 "bset", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1456 "bsr", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1457 "btst", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1458 "chk", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1459 "clr", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1460 "cmp", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1461 "dbcc", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1462 "divs", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1463 "divu", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1464 "eor", |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1465 "eori",//ccr |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1466 "eori",//sr |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1467 "exg", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1468 "ext", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1469 "illegal", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1470 "jmp", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1471 "jsr", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1472 "lea", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1473 "link", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1474 "lsl", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1475 "lsr", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1476 "move", |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1477 "move",//ccr |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1478 "move",//from_sr |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1479 "move",//sr |
50
4836d1f3841a
Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1480 "move",//usp |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1481 "movem", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1482 "movep", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1483 "muls", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1484 "mulu", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1485 "nbcd", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1486 "neg", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1487 "negx", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1488 "nop", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1489 "not", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1490 "or", |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1491 "ori",//ccr |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1492 "ori",//sr |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1493 "pea", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1494 "reset", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1495 "rol", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1496 "ror", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1497 "roxl", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1498 "roxr", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1499 "rte", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1500 "rtr", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1501 "rts", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1502 "sbcd", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1503 "scc", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1504 "stop", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1505 "sub", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1506 "subx", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1507 "swap", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1508 "tas", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1509 "trap", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1510 "trapv", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1511 "tst", |
12
db60ed283d8d
Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents:
11
diff
changeset
|
1512 "unlk", |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1513 "invalid", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1514 #ifdef M68010 |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1515 "bkpt", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1516 "move", //from ccr |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1517 "movec", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1518 "moves", |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1519 "rtd", |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1520 #endif |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1521 #ifdef M68020 |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1522 "bfchg", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1523 "bfclr", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1524 "bfexts", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1525 "bfextu", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1526 "bfffo", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1527 "bfins", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1528 "bfset", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1529 "bftst", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1530 "callm", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1531 "cas", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1532 "cas2", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1533 "chk2", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1534 "cmp2", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1535 "cpbcc", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1536 "cpdbcc", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1537 "cpgen", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1538 "cprestore", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1539 "cpsave", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1540 "cpscc", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1541 "cptrapcc", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1542 "divsl", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1543 "divul", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1544 "extb", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1545 "pack", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1546 "rtm", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1547 "trapcc", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1548 "unpk" |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1549 #endif |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1550 }; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1551 |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1552 char * cond_mnem[] = { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1553 "ra", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1554 "f", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1555 "hi", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1556 "ls", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1557 "cc", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1558 "cs", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1559 "ne", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1560 "eq", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1561 "vc", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1562 "vs", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1563 "pl", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1564 "mi", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1565 "ge", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1566 "lt", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1567 "gt", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1568 "le" |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1569 }; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1570 #ifdef M68010 |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1571 char * cr_mnem[] = { |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1572 "SFC", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1573 "DFC", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1574 #ifdef M68020 |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1575 "CACR", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1576 #endif |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1577 "USP", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1578 "VBR", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1579 #ifdef M68020 |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1580 "CAAR", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1581 "MSP", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1582 "ISP" |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1583 #endif |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1584 }; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1585 #endif |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1586 |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
1587 int m68k_disasm_op(m68k_op_info *decoded, char *dst, int need_comma, uint8_t labels, uint32_t address, format_label_fun label_fun, void * data) |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1588 { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1589 char * c = need_comma ? "," : ""; |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1590 int ret = 0; |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1591 #ifdef M68020 |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1592 uint8_t addr_mode = decoded->addr_mode & (~M68K_FLAG_BITFIELD); |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1593 #else |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1594 uint8_t addr_mode = decoded->addr_mode; |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1595 #endif |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1596 switch(addr_mode) |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1597 { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1598 case MODE_REG: |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1599 ret = sprintf(dst, "%s d%d", c, decoded->params.regs.pri); |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1600 break; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1601 case MODE_AREG: |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1602 ret = sprintf(dst, "%s a%d", c, decoded->params.regs.pri); |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1603 break; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1604 case MODE_AREG_INDIRECT: |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1605 ret = sprintf(dst, "%s (a%d)", c, decoded->params.regs.pri); |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1606 break; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1607 case MODE_AREG_POSTINC: |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1608 ret = sprintf(dst, "%s (a%d)+", c, decoded->params.regs.pri); |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1609 break; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1610 case MODE_AREG_PREDEC: |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1611 ret = sprintf(dst, "%s -(a%d)", c, decoded->params.regs.pri); |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1612 break; |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1613 case MODE_AREG_DISPLACE: |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1614 ret = sprintf(dst, "%s (%d, a%d)", c, decoded->params.regs.displacement, decoded->params.regs.pri); |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1615 break; |
79
d212e0cd0b7e
Implement indexed with 8-bit displacement addressing modes in decoder and disassembler
Mike Pavone <pavone@retrodev.com>
parents:
69
diff
changeset
|
1616 case MODE_AREG_INDEX_DISP8: |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1617 ret = sprintf(dst, "%s (%d, a%d, %c%d.%c)", c, decoded->params.regs.displacement, decoded->params.regs.pri, (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w'); |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1618 break; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1619 case MODE_IMMEDIATE: |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
60
diff
changeset
|
1620 case MODE_IMMEDIATE_WORD: |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1621 ret = sprintf(dst, (decoded->params.immed <= 128 ? "%s #%d" : "%s #$%X"), c, decoded->params.immed); |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1622 break; |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1623 case MODE_ABSOLUTE_SHORT: |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
1624 if (labels) { |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1625 ret = sprintf(dst, "%s ", c); |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
1626 ret += label_fun(dst+ret, decoded->params.immed, data); |
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
1627 strcat(dst+ret, ".w"); |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1628 ret = ret + 2; |
134 | 1629 } else { |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1630 ret = sprintf(dst, "%s $%X.w", c, decoded->params.immed); |
134 | 1631 } |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1632 break; |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1633 case MODE_ABSOLUTE: |
134 | 1634 if (labels) { |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1635 ret = sprintf(dst, "%s ", c); |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
1636 ret += label_fun(dst+ret, decoded->params.immed, data); |
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
1637 strcat(dst+ret, ".l"); |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1638 ret = ret + 2; |
134 | 1639 } else { |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1640 ret = sprintf(dst, "%s $%X", c, decoded->params.immed); |
134 | 1641 } |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1642 break; |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1643 case MODE_PC_DISPLACE: |
134 | 1644 if (labels) { |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1645 ret = sprintf(dst, "%s ", c); |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
1646 ret += label_fun(dst+ret, address + 2 + decoded->params.regs.displacement, data); |
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
1647 strcat(dst+ret, "(pc)"); |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1648 ret = ret + 4; |
134 | 1649 } else { |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1650 ret = sprintf(dst, "%s (%d, pc)", c, decoded->params.regs.displacement); |
134 | 1651 } |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1652 break; |
79
d212e0cd0b7e
Implement indexed with 8-bit displacement addressing modes in decoder and disassembler
Mike Pavone <pavone@retrodev.com>
parents:
69
diff
changeset
|
1653 case MODE_PC_INDEX_DISP8: |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1654 ret = sprintf(dst, "%s (%d, pc, %c%d.%c)", c, decoded->params.regs.displacement, (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w'); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1655 default: |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1656 ret = 0; |
0
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1657 } |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1658 #ifdef M68020 |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1659 if (decoded->addr_mode & M68K_FLAG_BITFIELD) |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1660 { |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1661 switch (decoded->bitfield & 0x820) |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1662 { |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1663 case 0: |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1664 return ret + sprintf(dst+ret, " {$%X:%d}", decoded->bitfield >> 6 & 0x1F, decoded->bitfield & 0x1F ? decoded->bitfield & 0x1F : 32); |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1665 case 0x20: |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1666 return ret + sprintf(dst+ret, " {$%X:d%d}", decoded->bitfield >> 6 & 0x1F, decoded->bitfield & 0x7); |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1667 case 0x800: |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1668 return ret + sprintf(dst+ret, " {d%d:%d}", decoded->bitfield >> 6 & 0x7, decoded->bitfield & 0x1F ? decoded->bitfield & 0x1F : 32); |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1669 case 0x820: |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1670 return ret + sprintf(dst+ret, " {d%d:d%d}", decoded->bitfield >> 6 & 0x7, decoded->bitfield & 0x7); |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1671 } |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1672 } |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1673 #endif |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1674 return ret; |
0
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1675 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1676 |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
1677 int m68k_disasm_movem_op(m68k_op_info *decoded, m68k_op_info *other, char *dst, int need_comma, uint8_t labels, uint32_t address, format_label_fun label_fun, void * data) |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1678 { |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1679 int8_t dir, reg, bit, regnum, last=-1, lastreg, first=-1; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1680 char *rtype, *last_rtype; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1681 int oplen; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1682 if (decoded->addr_mode == MODE_REG) { |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1683 if (other->addr_mode == MODE_AREG_PREDEC) { |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1684 bit = 15; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1685 dir = -1; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1686 } else { |
69
36f1133837d0
Fix disassembly of reg list in MOVEM when the reg list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
68
diff
changeset
|
1687 dir = 1; |
36f1133837d0
Fix disassembly of reg list in MOVEM when the reg list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
68
diff
changeset
|
1688 bit = 0; |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1689 } |
68
1c9a4052a2c0
Fix decoding and disassembly of MOVEM
Mike Pavone <pavone@retrodev.com>
parents:
62
diff
changeset
|
1690 if (need_comma) { |
1c9a4052a2c0
Fix decoding and disassembly of MOVEM
Mike Pavone <pavone@retrodev.com>
parents:
62
diff
changeset
|
1691 strcat(dst, ", "); |
1c9a4052a2c0
Fix decoding and disassembly of MOVEM
Mike Pavone <pavone@retrodev.com>
parents:
62
diff
changeset
|
1692 oplen = 2; |
1c9a4052a2c0
Fix decoding and disassembly of MOVEM
Mike Pavone <pavone@retrodev.com>
parents:
62
diff
changeset
|
1693 } else { |
1c9a4052a2c0
Fix decoding and disassembly of MOVEM
Mike Pavone <pavone@retrodev.com>
parents:
62
diff
changeset
|
1694 strcat(dst, " "); |
1c9a4052a2c0
Fix decoding and disassembly of MOVEM
Mike Pavone <pavone@retrodev.com>
parents:
62
diff
changeset
|
1695 oplen = 1; |
1c9a4052a2c0
Fix decoding and disassembly of MOVEM
Mike Pavone <pavone@retrodev.com>
parents:
62
diff
changeset
|
1696 } |
1c9a4052a2c0
Fix decoding and disassembly of MOVEM
Mike Pavone <pavone@retrodev.com>
parents:
62
diff
changeset
|
1697 for (reg=0; bit < 16 && bit > -1; bit += dir, reg++) { |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
1698 if (decoded->params.immed & (1 << bit)) { |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1699 if (reg > 7) { |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1700 rtype = "a"; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1701 regnum = reg - 8; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1702 } else { |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1703 rtype = "d"; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1704 regnum = reg; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1705 } |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1706 if (last >= 0 && last == regnum - 1 && lastreg == reg - 1) { |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1707 last = regnum; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1708 lastreg = reg; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1709 } else if(last >= 0) { |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1710 if (first != last) { |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1711 oplen += sprintf(dst + oplen, "-%s%d/%s%d",last_rtype, last, rtype, regnum); |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1712 } else { |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1713 oplen += sprintf(dst + oplen, "/%s%d", rtype, regnum); |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1714 } |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1715 first = last = regnum; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1716 last_rtype = rtype; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1717 lastreg = reg; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1718 } else { |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1719 oplen += sprintf(dst + oplen, "%s%d", rtype, regnum); |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1720 first = last = regnum; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1721 last_rtype = rtype; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1722 lastreg = reg; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1723 } |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1724 } |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1725 } |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1726 if (last >= 0 && last != first) { |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1727 oplen += sprintf(dst + oplen, "-%s%d", last_rtype, last); |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1728 } |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1729 return oplen; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1730 } else { |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
1731 return m68k_disasm_op(decoded, dst, need_comma, labels, address, label_fun, data); |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1732 } |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1733 } |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1734 |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
1735 int m68k_default_label_fun(char * dst, uint32_t address, void * data) |
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
1736 { |
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
1737 return sprintf(dst, "ADR_%X", address); |
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
1738 } |
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
1739 |
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
1740 int m68k_disasm_ex(m68kinst * decoded, char * dst, uint8_t labels, format_label_fun label_fun, void * data) |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1741 { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1742 int ret,op1len; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1743 uint8_t size; |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1744 char * special_op = "CCR"; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1745 switch (decoded->op) |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1746 { |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1747 case M68K_BCC: |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1748 case M68K_DBCC: |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1749 case M68K_SCC: |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1750 ret = strlen(mnemonics[decoded->op]) - 2; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1751 memcpy(dst, mnemonics[decoded->op], ret); |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1752 dst[ret] = 0; |
50
4836d1f3841a
Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1753 strcpy(dst+ret, cond_mnem[decoded->extra.cond]); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1754 ret = strlen(dst); |
50
4836d1f3841a
Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1755 if (decoded->op != M68K_SCC) { |
134 | 1756 if (labels) { |
1757 if (decoded->op == M68K_DBCC) { | |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
1758 ret += sprintf(dst+ret, " d%d, ", decoded->dst.params.regs.pri); |
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
1759 ret += label_fun(dst+ret, decoded->address + 2 + decoded->src.params.immed, data); |
134 | 1760 } else { |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
1761 dst[ret++] = ' '; |
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
1762 ret += label_fun(dst+ret, decoded->address + 2 + decoded->src.params.immed, data); |
134 | 1763 } |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
1764 } else { |
134 | 1765 if (decoded->op == M68K_DBCC) { |
1766 ret += sprintf(dst+ret, " d%d, #%d <%X>", decoded->dst.params.regs.pri, decoded->src.params.immed, decoded->address + 2 + decoded->src.params.immed); | |
1767 } else { | |
1768 ret += sprintf(dst+ret, " #%d <%X>", decoded->src.params.immed, decoded->address + 2 + decoded->src.params.immed); | |
1769 } | |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
1770 } |
50
4836d1f3841a
Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1771 return ret; |
4836d1f3841a
Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1772 } |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1773 break; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1774 case M68K_BSR: |
134 | 1775 if (labels) { |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
1776 ret = sprintf(dst, "bsr%s ", decoded->variant == VAR_BYTE ? ".s" : ""); |
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
1777 ret += label_fun(dst+ret, decoded->address + 2 + decoded->src.params.immed, data); |
134 | 1778 } else { |
1779 ret = sprintf(dst, "bsr%s #%d <%X>", decoded->variant == VAR_BYTE ? ".s" : "", decoded->src.params.immed, decoded->address + 2 + decoded->src.params.immed); | |
1780 } | |
50
4836d1f3841a
Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1781 return ret; |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1782 case M68K_MOVE_FROM_SR: |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1783 ret = sprintf(dst, "%s", mnemonics[decoded->op]); |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1784 ret += sprintf(dst + ret, " SR"); |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
1785 ret += m68k_disasm_op(&(decoded->dst), dst + ret, 1, labels, decoded->address, label_fun, data); |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1786 return ret; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1787 case M68K_ANDI_SR: |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1788 case M68K_EORI_SR: |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1789 case M68K_MOVE_SR: |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1790 case M68K_ORI_SR: |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1791 special_op = "SR"; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1792 case M68K_ANDI_CCR: |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1793 case M68K_EORI_CCR: |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1794 case M68K_MOVE_CCR: |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1795 case M68K_ORI_CCR: |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1796 ret = sprintf(dst, "%s", mnemonics[decoded->op]); |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
1797 ret += m68k_disasm_op(&(decoded->src), dst + ret, 0, labels, decoded->address, label_fun, data); |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1798 ret += sprintf(dst + ret, ", %s", special_op); |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1799 return ret; |
50
4836d1f3841a
Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1800 case M68K_MOVE_USP: |
4836d1f3841a
Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1801 ret = sprintf(dst, "%s", mnemonics[decoded->op]); |
4836d1f3841a
Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1802 if (decoded->src.addr_mode != MODE_UNUSED) { |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
1803 ret += m68k_disasm_op(&(decoded->src), dst + ret, 0, labels, decoded->address, label_fun, data); |
50
4836d1f3841a
Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1804 ret += sprintf(dst + ret, ", USP"); |
4836d1f3841a
Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1805 } else { |
4836d1f3841a
Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1806 ret += sprintf(dst + ret, "USP, "); |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
1807 ret += m68k_disasm_op(&(decoded->dst), dst + ret, 0, labels, decoded->address, label_fun, data); |
50
4836d1f3841a
Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1808 } |
4836d1f3841a
Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1809 return ret; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1810 case M68K_INVALID: |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1811 ret = sprintf(dst, "dc.w $%X", decoded->src.params.immed); |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1812 return ret; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1813 #ifdef M68010 |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1814 case M68K_MOVEC: |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1815 ret = sprintf(dst, "%s ", mnemonics[decoded->op]); |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1816 if (decoded->src.addr_mode == MODE_UNUSED) { |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1817 ret += sprintf(dst + ret, "%s, ", cr_mnem[decoded->src.params.immed]); |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
1818 ret += m68k_disasm_op(&(decoded->dst), dst + ret, 0, labels, decoded->address, label_fun, data); |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1819 } else { |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
1820 ret += m68k_disasm_op(&(decoded->src), dst + ret, 0, labels, decoded->address, label_fun, data); |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1821 ret += sprintf(dst + ret, ", %s", cr_mnem[decoded->dst.params.immed]); |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1822 } |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1823 return ret; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1824 #endif |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1825 default: |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1826 size = decoded->extra.size; |
518
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1827 ret = sprintf(dst, "%s%s%s", |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1828 mnemonics[decoded->op], |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1829 decoded->variant == VAR_QUICK ? "q" : (decoded->variant == VAR_IMMEDIATE ? "i" : ""), |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1830 size == OPSIZE_BYTE ? ".b" : (size == OPSIZE_WORD ? ".w" : (size == OPSIZE_LONG ? ".l" : ""))); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1831 } |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1832 if (decoded->op == M68K_MOVEM) { |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
1833 op1len = m68k_disasm_movem_op(&(decoded->src), &(decoded->dst), dst + ret, 0, labels, decoded->address, label_fun, data); |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1834 ret += op1len; |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
1835 ret += m68k_disasm_movem_op(&(decoded->dst), &(decoded->src), dst + ret, op1len, labels, decoded->address, label_fun, data); |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1836 } else { |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
1837 op1len = m68k_disasm_op(&(decoded->src), dst + ret, 0, labels, decoded->address, label_fun, data); |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1838 ret += op1len; |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
1839 ret += m68k_disasm_op(&(decoded->dst), dst + ret, op1len, labels, decoded->address, label_fun, data); |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1840 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1841 return ret; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1842 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1843 |
134 | 1844 int m68k_disasm(m68kinst * decoded, char * dst) |
1845 { | |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
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1846 return m68k_disasm_ex(decoded, dst, 0, NULL, NULL); |
134 | 1847 } |
1848 | |
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Better support for labels sourced from VOS program module header
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1849 int m68k_disasm_labels(m68kinst * decoded, char * dst, format_label_fun label_fun, void * data) |
134 | 1850 { |
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1851 if (!label_fun) |
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Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
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1852 { |
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Better support for labels sourced from VOS program module header
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1853 label_fun = m68k_default_label_fun; |
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Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
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1854 } |
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Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
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1855 return m68k_disasm_ex(decoded, dst, 1, label_fun, data); |
134 | 1856 } |