Mercurial > repos > blastem
annotate m68k_to_x86.c @ 229:d60837a7d18a
Improve color rendering accuracy and optimize SDL renderer a bit
author | Mike Pavone <pavone@retrodev.com> |
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date | Sun, 21 Apr 2013 19:12:48 -0700 |
parents | 1ed81ef2a3a2 |
children | d9bf8e61c33c |
rev | line source |
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1 #include "gen_x86.h" |
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2 #include "m68k_to_x86.h" |
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3 #include "68kinst.h" |
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4 #include "mem.h" |
211 | 5 #include "x86_backend.h" |
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6 #include <stdio.h> |
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7 #include <stddef.h> |
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8 #include <stdlib.h> |
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9 #include <string.h> |
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10 |
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11 #define BUS 4 |
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12 #define PREDEC_PENALTY 2 |
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13 #define CYCLES RAX |
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14 #define LIMIT RBP |
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15 #define SCRATCH1 RCX |
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16 #define SCRATCH2 RDI |
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17 #define CONTEXT RSI |
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18 |
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19 #define FLAG_N RBX |
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20 #define FLAG_V BH |
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21 #define FLAG_Z RDX |
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22 #define FLAG_C DH |
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23 |
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24 char disasm_buf[1024]; |
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25 |
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26 void handle_cycle_limit_int(); |
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27 void m68k_read_word_scratch1(); |
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28 void m68k_read_long_scratch1(); |
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29 void m68k_read_byte_scratch1(); |
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30 void m68k_write_word(); |
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31 void m68k_write_long_lowfirst(); |
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32 void m68k_write_long_highfirst(); |
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33 void m68k_write_byte(); |
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34 void m68k_save_context(); |
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35 void m68k_load_context(); |
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36 void m68k_modified_ret_addr(); |
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37 void m68k_native_addr(); |
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38 void m68k_native_addr_and_sync(); |
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39 void m68k_trap(); |
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40 void m68k_invalid(); |
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41 void m68k_retrans_stub(); |
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42 void set_sr(); |
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43 void set_ccr(); |
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44 void get_sr(); |
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45 void do_sync(); |
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46 void bcd_add(); |
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47 void bcd_sub(); |
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48 void m68k_start_context(uint8_t * addr, m68k_context * context); |
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49 |
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50 uint8_t * cycles(uint8_t * dst, uint32_t num) |
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51 { |
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52 dst = add_ir(dst, num, CYCLES, SZ_D); |
118 | 53 return dst; |
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54 } |
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55 |
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56 uint8_t * check_cycles_int(uint8_t * dst, uint32_t address) |
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57 { |
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58 dst = cmp_rr(dst, CYCLES, LIMIT, SZ_D); |
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59 uint8_t * jmp_off = dst+1; |
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60 dst = jcc(dst, CC_NC, dst + 7); |
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61 dst = mov_ir(dst, address, SCRATCH1, SZ_D); |
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62 dst = call(dst, (uint8_t *)handle_cycle_limit_int); |
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63 *jmp_off = dst - (jmp_off+1); |
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64 return dst; |
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65 } |
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66 |
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67 int8_t native_reg(m68k_op_info * op, x86_68k_options * opts) |
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68 { |
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69 if (op->addr_mode == MODE_REG) { |
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70 return opts->dregs[op->params.regs.pri]; |
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71 } |
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72 if (op->addr_mode == MODE_AREG) { |
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73 return opts->aregs[op->params.regs.pri]; |
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74 } |
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75 return -1; |
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76 } |
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77 |
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78 //must be called with an m68k_op_info that uses a register |
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79 size_t reg_offset(m68k_op_info *op) |
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80 { |
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81 if (op->addr_mode == MODE_REG) { |
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82 return offsetof(m68k_context, dregs) + sizeof(uint32_t) * op->params.regs.pri; |
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83 } |
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84 return offsetof(m68k_context, aregs) + sizeof(uint32_t) * op->params.regs.pri; |
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85 } |
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86 |
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87 void print_regs_exit(m68k_context * context) |
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88 { |
207 | 89 printf("XNZVC\n%d%d%d%d%d\n", context->flags[0], context->flags[1], context->flags[2], context->flags[3], context->flags[4]); |
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90 for (int i = 0; i < 8; i++) { |
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91 printf("d%d: %X\n", i, context->dregs[i]); |
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92 } |
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93 for (int i = 0; i < 8; i++) { |
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94 printf("a%d: %X\n", i, context->aregs[i]); |
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95 } |
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96 exit(0); |
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97 } |
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98 |
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99 uint8_t * translate_m68k_src(m68kinst * inst, x86_ea * ea, uint8_t * out, x86_68k_options * opts) |
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100 { |
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101 int8_t reg = native_reg(&(inst->src), opts); |
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102 uint8_t sec_reg; |
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103 int32_t dec_amount,inc_amount; |
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104 if (reg >= 0) { |
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105 ea->mode = MODE_REG_DIRECT; |
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106 if (inst->dst.addr_mode == MODE_AREG && inst->extra.size == OPSIZE_WORD) { |
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107 out = movsx_rr(out, reg, SCRATCH1, SZ_W, SZ_D); |
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108 ea->base = SCRATCH1; |
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109 } else { |
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110 ea->base = reg; |
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111 } |
18
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|
112 return out; |
14
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|
113 } |
18
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114 switch (inst->src.addr_mode) |
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115 { |
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116 case MODE_REG: |
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117 case MODE_AREG: |
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118 //We only get one memory parameter, so if the dst operand is a register in memory, |
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119 //we need to copy this to a temp register first |
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120 reg = native_reg(&(inst->dst), opts); |
128
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Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
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126
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121 if (reg >= 0 || inst->dst.addr_mode == MODE_UNUSED || !(inst->dst.addr_mode == MODE_REG || inst->dst.addr_mode == MODE_AREG) |
18
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122 || inst->op == M68K_EXG) { |
71
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123 |
18
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124 ea->mode = MODE_REG_DISPLACE8; |
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125 ea->base = CONTEXT; |
52
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126 ea->disp = reg_offset(&(inst->src)); |
18
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127 } else { |
181
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128 if (inst->dst.addr_mode == MODE_AREG && inst->extra.size == OPSIZE_WORD) { |
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129 out = movsx_rdisp8r(out, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_W, SZ_D); |
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130 } else { |
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131 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, inst->extra.size); |
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132 } |
18
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133 ea->mode = MODE_REG_DIRECT; |
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134 ea->base = SCRATCH1; |
181
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135 //we're explicitly handling the areg dest here, so we exit immediately |
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136 return out; |
18
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137 } |
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138 break; |
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139 case MODE_AREG_PREDEC: |
216
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213
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140 dec_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : (inst->src.params.regs.pri == 7 ? 2 :1)); |
18
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141 out = cycles(out, PREDEC_PENALTY); |
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142 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
158
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143 out = sub_ir(out, dec_amount, opts->aregs[inst->src.params.regs.pri], SZ_D); |
18
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144 } else { |
158
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157
diff
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145 out = sub_irdisp8(out, dec_amount, CONTEXT, reg_offset(&(inst->src)), SZ_D); |
18
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146 } |
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147 case MODE_AREG_INDIRECT: |
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148 case MODE_AREG_POSTINC: |
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149 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
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150 out = mov_rr(out, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
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151 } else { |
52
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|
152 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); |
18
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153 } |
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154 switch (inst->extra.size) |
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155 { |
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156 case OPSIZE_BYTE: |
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157 out = call(out, (char *)m68k_read_byte_scratch1); |
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158 break; |
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159 case OPSIZE_WORD: |
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160 out = call(out, (char *)m68k_read_word_scratch1); |
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161 break; |
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162 case OPSIZE_LONG: |
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163 out = call(out, (char *)m68k_read_long_scratch1); |
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164 break; |
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165 } |
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166 |
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167 if (inst->src.addr_mode == MODE_AREG_POSTINC) { |
183
2f08d9e90a4c
Fix (a7)+ src when size is byte, fix trap return address, make div with areg src decoded to invalid
Mike Pavone <pavone@retrodev.com>
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182
diff
changeset
|
168 inc_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : (inst->src.params.regs.pri == 7 ? 2 : 1)); |
18
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169 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
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|
170 out = add_ir(out, inc_amount, opts->aregs[inst->src.params.regs.pri], SZ_D); |
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|
171 } else { |
52
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|
172 out = add_irdisp8(out, inc_amount, CONTEXT, reg_offset(&(inst->src)), SZ_D); |
18
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|
173 } |
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174 } |
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|
175 ea->mode = MODE_REG_DIRECT; |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
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183
diff
changeset
|
176 ea->base = (inst->dst.addr_mode == MODE_AREG_PREDEC && inst->op != M68K_MOVE) ? SCRATCH2 : SCRATCH1; |
18
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|
177 break; |
71
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178 case MODE_AREG_DISPLACE: |
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179 out = cycles(out, BUS); |
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180 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
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181 out = mov_rr(out, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
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182 } else { |
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183 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); |
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184 } |
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185 out = add_ir(out, inst->src.params.regs.displacement, SCRATCH1, SZ_D); |
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186 switch (inst->extra.size) |
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187 { |
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188 case OPSIZE_BYTE: |
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189 out = call(out, (char *)m68k_read_byte_scratch1); |
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190 break; |
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191 case OPSIZE_WORD: |
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192 out = call(out, (char *)m68k_read_word_scratch1); |
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193 break; |
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194 case OPSIZE_LONG: |
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195 out = call(out, (char *)m68k_read_long_scratch1); |
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196 break; |
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197 } |
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198 ea->mode = MODE_REG_DIRECT; |
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199 ea->base = SCRATCH1; |
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|
200 break; |
81
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78
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changeset
|
201 case MODE_AREG_INDEX_DISP8: |
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202 out = cycles(out, 6); |
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203 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
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|
204 out = mov_rr(out, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
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205 } else { |
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206 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); |
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207 } |
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|
208 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7; |
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|
209 if (inst->src.params.regs.sec & 1) { |
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|
210 if (inst->src.params.regs.sec & 0x10) { |
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|
211 if (opts->aregs[sec_reg] >= 0) { |
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parents:
78
diff
changeset
|
212 out = add_rr(out, opts->aregs[sec_reg], SCRATCH1, SZ_D); |
6d231dbe75ab
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Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
213 } else { |
6d231dbe75ab
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Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
214 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
215 } |
6d231dbe75ab
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Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
216 } else { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
217 if (opts->dregs[sec_reg] >= 0) { |
6d231dbe75ab
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Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
218 out = add_rr(out, opts->dregs[sec_reg], SCRATCH1, SZ_D); |
6d231dbe75ab
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Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
219 } else { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
220 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
221 } |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
222 } |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
223 } else { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
224 if (inst->src.params.regs.sec & 0x10) { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
225 if (opts->aregs[sec_reg] >= 0) { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
226 out = movsx_rr(out, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
227 } else { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
228 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
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78
diff
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|
229 } |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
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78
diff
changeset
|
230 } else { |
6d231dbe75ab
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Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
231 if (opts->dregs[sec_reg] >= 0) { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
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78
diff
changeset
|
232 out = movsx_rr(out, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
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78
diff
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|
233 } else { |
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Mike Pavone <pavone@retrodev.com>
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78
diff
changeset
|
234 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
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78
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|
235 } |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
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78
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|
236 } |
6d231dbe75ab
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diff
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|
237 out = add_rr(out, SCRATCH2, SCRATCH1, SZ_D); |
6d231dbe75ab
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78
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|
238 } |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
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78
diff
changeset
|
239 if (inst->src.params.regs.displacement) { |
6d231dbe75ab
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78
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|
240 out = add_ir(out, inst->src.params.regs.displacement, SCRATCH1, SZ_D); |
6d231dbe75ab
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78
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|
241 } |
97
c7185fd840fc
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96
diff
changeset
|
242 switch (inst->extra.size) |
c7185fd840fc
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Mike Pavone <pavone@retrodev.com>
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96
diff
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|
243 { |
c7185fd840fc
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96
diff
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|
244 case OPSIZE_BYTE: |
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96
diff
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|
245 out = call(out, (char *)m68k_read_byte_scratch1); |
c7185fd840fc
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96
diff
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|
246 break; |
c7185fd840fc
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96
diff
changeset
|
247 case OPSIZE_WORD: |
c7185fd840fc
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96
diff
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|
248 out = call(out, (char *)m68k_read_word_scratch1); |
c7185fd840fc
Fix address register indexed addressing (probably)
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96
diff
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|
249 break; |
c7185fd840fc
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96
diff
changeset
|
250 case OPSIZE_LONG: |
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96
diff
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|
251 out = call(out, (char *)m68k_read_long_scratch1); |
c7185fd840fc
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96
diff
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|
252 break; |
c7185fd840fc
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96
diff
changeset
|
253 } |
c7185fd840fc
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96
diff
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|
254 ea->mode = MODE_REG_DIRECT; |
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96
diff
changeset
|
255 ea->base = SCRATCH1; |
81
6d231dbe75ab
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|
256 break; |
71
f80fa1776507
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70
diff
changeset
|
257 case MODE_PC_DISPLACE: |
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70
diff
changeset
|
258 out = cycles(out, BUS); |
74
6396dc91f61e
Fix some bugs in movem with a register list destination
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73
diff
changeset
|
259 out = mov_ir(out, inst->src.params.regs.displacement + inst->address+2, SCRATCH1, SZ_D); |
71
f80fa1776507
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70
diff
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|
260 switch (inst->extra.size) |
f80fa1776507
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parents:
70
diff
changeset
|
261 { |
f80fa1776507
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Mike Pavone <pavone@retrodev.com>
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70
diff
changeset
|
262 case OPSIZE_BYTE: |
f80fa1776507
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70
diff
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|
263 out = call(out, (char *)m68k_read_byte_scratch1); |
f80fa1776507
Implement more instructions and address modes
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parents:
70
diff
changeset
|
264 break; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
265 case OPSIZE_WORD: |
f80fa1776507
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70
diff
changeset
|
266 out = call(out, (char *)m68k_read_word_scratch1); |
f80fa1776507
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Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
267 break; |
f80fa1776507
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parents:
70
diff
changeset
|
268 case OPSIZE_LONG: |
f80fa1776507
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Mike Pavone <pavone@retrodev.com>
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70
diff
changeset
|
269 out = call(out, (char *)m68k_read_long_scratch1); |
f80fa1776507
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Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
270 break; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
271 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
272 ea->mode = MODE_REG_DIRECT; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
273 ea->base = SCRATCH1; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
274 break; |
81
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
275 case MODE_PC_INDEX_DISP8: |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
276 out = cycles(out, 6); |
96
f894f85cf39d
Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
277 out = mov_ir(out, inst->address+2, SCRATCH1, SZ_D); |
81
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
278 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7; |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
279 if (inst->src.params.regs.sec & 1) { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
280 if (inst->src.params.regs.sec & 0x10) { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
281 if (opts->aregs[sec_reg] >= 0) { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
282 out = add_rr(out, opts->aregs[sec_reg], SCRATCH1, SZ_D); |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
283 } else { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
284 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
285 } |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
286 } else { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
287 if (opts->dregs[sec_reg] >= 0) { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
288 out = add_rr(out, opts->dregs[sec_reg], SCRATCH1, SZ_D); |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
289 } else { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
290 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
291 } |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
292 } |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
293 } else { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
294 if (inst->src.params.regs.sec & 0x10) { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
295 if (opts->aregs[sec_reg] >= 0) { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
296 out = movsx_rr(out, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
297 } else { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
298 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
299 } |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
300 } else { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
301 if (opts->dregs[sec_reg] >= 0) { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
302 out = movsx_rr(out, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
303 } else { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
304 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
305 } |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
306 } |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
307 out = add_rr(out, SCRATCH2, SCRATCH1, SZ_D); |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
308 } |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
309 if (inst->src.params.regs.displacement) { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
310 out = add_ir(out, inst->src.params.regs.displacement, SCRATCH1, SZ_D); |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
311 } |
96
f894f85cf39d
Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
312 switch (inst->extra.size) |
f894f85cf39d
Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
313 { |
f894f85cf39d
Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
314 case OPSIZE_BYTE: |
f894f85cf39d
Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
315 out = call(out, (char *)m68k_read_byte_scratch1); |
f894f85cf39d
Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
316 break; |
f894f85cf39d
Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
317 case OPSIZE_WORD: |
f894f85cf39d
Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
318 out = call(out, (char *)m68k_read_word_scratch1); |
f894f85cf39d
Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
319 break; |
f894f85cf39d
Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
320 case OPSIZE_LONG: |
f894f85cf39d
Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
321 out = call(out, (char *)m68k_read_long_scratch1); |
f894f85cf39d
Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
322 break; |
f894f85cf39d
Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
323 } |
f894f85cf39d
Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
324 ea->mode = MODE_REG_DIRECT; |
f894f85cf39d
Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
325 ea->base = SCRATCH1; |
81
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
326 break; |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
327 case MODE_ABSOLUTE: |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
328 case MODE_ABSOLUTE_SHORT: |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
329 if (inst->src.addr_mode == MODE_ABSOLUTE) { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
330 out = cycles(out, BUS*2); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
331 } else { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
332 out = cycles(out, BUS); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
333 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
334 out = mov_ir(out, inst->src.params.immed, SCRATCH1, SZ_D); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
335 switch (inst->extra.size) |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
336 { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
337 case OPSIZE_BYTE: |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
338 out = call(out, (char *)m68k_read_byte_scratch1); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
339 break; |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
340 case OPSIZE_WORD: |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
341 out = call(out, (char *)m68k_read_word_scratch1); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
342 break; |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
343 case OPSIZE_LONG: |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
344 out = call(out, (char *)m68k_read_long_scratch1); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
345 break; |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
346 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
347 ea->mode = MODE_REG_DIRECT; |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
348 ea->base = SCRATCH1; |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
349 break; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
350 case MODE_IMMEDIATE: |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
351 case MODE_IMMEDIATE_WORD: |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
352 if (inst->variant != VAR_QUICK) { |
64
2b1a65f4b85d
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents:
61
diff
changeset
|
353 out = cycles(out, (inst->extra.size == OPSIZE_LONG && inst->src.addr_mode == MODE_IMMEDIATE) ? BUS*2 : BUS); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
354 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
355 ea->mode = MODE_IMMED; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
356 ea->disp = inst->src.params.immed; |
216
0b5ec22dcda2
Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source.
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
357 if (inst->dst.addr_mode == MODE_AREG && inst->extra.size == OPSIZE_WORD && ea->disp & 0x8000) { |
0b5ec22dcda2
Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source.
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
358 ea->disp |= 0xFFFF0000; |
0b5ec22dcda2
Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source.
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
359 } |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
360 return out; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
361 default: |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
362 m68k_disasm(inst, disasm_buf); |
154
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
363 printf("%X: %s\naddress mode %d not implemented (src)\n", inst->address, disasm_buf, inst->src.addr_mode); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
364 exit(1); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
365 } |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
366 if (inst->dst.addr_mode == MODE_AREG && inst->extra.size == OPSIZE_WORD) { |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
367 if (ea->mode == MODE_REG_DIRECT) { |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
368 out = movsx_rr(out, ea->base, SCRATCH1, SZ_W, SZ_D); |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
369 } else { |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
370 out = movsx_rdisp8r(out, ea->base, ea->disp, SCRATCH1, SZ_W, SZ_D); |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
371 ea->mode = MODE_REG_DIRECT; |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
372 } |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
373 ea->base = SCRATCH1; |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
374 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
375 return out; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
376 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
377 |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
378 uint8_t * translate_m68k_dst(m68kinst * inst, x86_ea * ea, uint8_t * out, x86_68k_options * opts, uint8_t fake_read) |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
379 { |
98
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
380 int8_t reg = native_reg(&(inst->dst), opts), sec_reg; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
381 int32_t dec_amount, inc_amount; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
382 if (reg >= 0) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
383 ea->mode = MODE_REG_DIRECT; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
384 ea->base = reg; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
385 return out; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
386 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
387 switch (inst->dst.addr_mode) |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
388 { |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
389 case MODE_REG: |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
390 case MODE_AREG: |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
391 ea->mode = MODE_REG_DISPLACE8; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
392 ea->base = CONTEXT; |
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
393 ea->disp = reg_offset(&(inst->dst)); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
394 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
395 case MODE_AREG_PREDEC: |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
396 if (inst->src.addr_mode == MODE_AREG_PREDEC) { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
397 out = push_r(out, SCRATCH1); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
398 } |
182
924af8b2f7a0
Fix -(a7) dest when size is byte
Mike Pavone <pavone@retrodev.com>
parents:
181
diff
changeset
|
399 dec_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : (inst->dst.params.regs.pri == 7 ? 2 : 1)); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
400 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
401 out = sub_ir(out, dec_amount, opts->aregs[inst->dst.params.regs.pri], SZ_D); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
402 } else { |
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
403 out = sub_irdisp8(out, dec_amount, CONTEXT, reg_offset(&(inst->dst)), SZ_D); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
404 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
405 case MODE_AREG_INDIRECT: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
406 case MODE_AREG_POSTINC: |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
407 if (fake_read) { |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
408 out = cycles(out, inst->extra.size == OPSIZE_LONG ? 8 : 4); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
409 } else { |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
410 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
411 out = mov_rr(out, opts->aregs[inst->dst.params.regs.pri], SCRATCH1, SZ_D); |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
412 } else { |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
413 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->dst)), SCRATCH1, SZ_D); |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
414 } |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
415 switch (inst->extra.size) |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
416 { |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
417 case OPSIZE_BYTE: |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
418 out = call(out, (char *)m68k_read_byte_scratch1); |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
419 break; |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
420 case OPSIZE_WORD: |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
421 out = call(out, (char *)m68k_read_word_scratch1); |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
422 break; |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
423 case OPSIZE_LONG: |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
424 out = call(out, (char *)m68k_read_long_scratch1); |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
425 break; |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
426 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
427 } |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
428 if (inst->src.addr_mode == MODE_AREG_PREDEC) { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
429 //restore src operand to SCRATCH2 |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
430 out =pop_r(out, SCRATCH2); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
431 } else { |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
432 //save reg value in SCRATCH2 so we can use it to save the result in memory later |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
433 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
434 out = mov_rr(out, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
435 } else { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
436 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
437 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
438 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
439 |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
440 if (inst->dst.addr_mode == MODE_AREG_POSTINC) { |
218
1abf8e967b33
Fix autoincrement on a7 when used as a destination in a byte sized instruction
Mike Pavone <pavone@retrodev.com>
parents:
216
diff
changeset
|
441 inc_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : (inst->dst.params.regs.pri == 7 ? 2 : 1)); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
442 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
443 out = add_ir(out, inc_amount, opts->aregs[inst->dst.params.regs.pri], SZ_D); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
444 } else { |
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
445 out = add_irdisp8(out, inc_amount, CONTEXT, reg_offset(&(inst->dst)), SZ_D); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
446 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
447 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
448 ea->mode = MODE_REG_DIRECT; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
449 ea->base = SCRATCH1; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
450 break; |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
451 case MODE_AREG_DISPLACE: |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
452 out = cycles(out, fake_read ? BUS+(inst->extra.size == OPSIZE_LONG ? BUS*2 : BUS) : BUS); |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
453 reg = fake_read ? SCRATCH2 : SCRATCH1; |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
454 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
455 out = mov_rr(out, opts->aregs[inst->dst.params.regs.pri], reg, SZ_D); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
456 } else { |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
457 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->dst)), reg, SZ_D); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
458 } |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
459 out = add_ir(out, inst->dst.params.regs.displacement, reg, SZ_D); |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
460 if (!fake_read) { |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
461 out = push_r(out, SCRATCH1); |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
462 switch (inst->extra.size) |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
463 { |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
464 case OPSIZE_BYTE: |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
465 out = call(out, (char *)m68k_read_byte_scratch1); |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
466 break; |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
467 case OPSIZE_WORD: |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
468 out = call(out, (char *)m68k_read_word_scratch1); |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
469 break; |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
470 case OPSIZE_LONG: |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
471 out = call(out, (char *)m68k_read_long_scratch1); |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
472 break; |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
473 } |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
474 out = pop_r(out, SCRATCH2); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
475 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
476 ea->mode = MODE_REG_DIRECT; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
477 ea->base = SCRATCH1; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
478 break; |
98
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
479 case MODE_AREG_INDEX_DISP8: |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
480 out = cycles(out, fake_read ? (6 + inst->extra.size == OPSIZE_LONG ? 8 : 4) : 6); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
481 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
482 out = mov_rr(out, opts->aregs[inst->dst.params.regs.pri], SCRATCH1, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
483 } else { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
484 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->dst)), SCRATCH1, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
485 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
486 sec_reg = (inst->dst.params.regs.sec >> 1) & 0x7; |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
487 if (inst->dst.params.regs.sec & 1) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
488 if (inst->dst.params.regs.sec & 0x10) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
489 if (opts->aregs[sec_reg] >= 0) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
490 out = add_rr(out, opts->aregs[sec_reg], SCRATCH1, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
491 } else { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
492 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
493 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
494 } else { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
495 if (opts->dregs[sec_reg] >= 0) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
496 out = add_rr(out, opts->dregs[sec_reg], SCRATCH1, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
497 } else { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
498 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
499 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
500 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
501 } else { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
502 if (inst->dst.params.regs.sec & 0x10) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
503 if (opts->aregs[sec_reg] >= 0) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
504 out = movsx_rr(out, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
505 } else { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
506 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
507 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
508 } else { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
509 if (opts->dregs[sec_reg] >= 0) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
510 out = movsx_rr(out, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
511 } else { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
512 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
513 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
514 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
515 out = add_rr(out, SCRATCH2, SCRATCH1, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
516 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
517 if (inst->dst.params.regs.displacement) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
518 out = add_ir(out, inst->dst.params.regs.displacement, SCRATCH1, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
519 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
520 if (fake_read) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
521 out = mov_rr(out, SCRATCH1, SCRATCH2, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
522 } else { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
523 out = push_r(out, SCRATCH1); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
524 switch (inst->extra.size) |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
525 { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
526 case OPSIZE_BYTE: |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
527 out = call(out, (char *)m68k_read_byte_scratch1); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
528 break; |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
529 case OPSIZE_WORD: |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
530 out = call(out, (char *)m68k_read_word_scratch1); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
531 break; |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
532 case OPSIZE_LONG: |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
533 out = call(out, (char *)m68k_read_long_scratch1); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
534 break; |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
535 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
536 out = pop_r(out, SCRATCH2); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
537 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
538 ea->mode = MODE_REG_DIRECT; |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
539 ea->base = SCRATCH1; |
161
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
540 break; |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
541 case MODE_PC_DISPLACE: |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
542 out = cycles(out, fake_read ? BUS+(inst->extra.size == OPSIZE_LONG ? BUS*2 : BUS) : BUS); |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
543 out = mov_ir(out, inst->dst.params.regs.displacement + inst->address+2, fake_read ? SCRATCH2 : SCRATCH1, SZ_D); |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
544 if (!fake_read) { |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
545 out = push_r(out, SCRATCH1); |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
546 switch (inst->extra.size) |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
547 { |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
548 case OPSIZE_BYTE: |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
549 out = call(out, (char *)m68k_read_byte_scratch1); |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
550 break; |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
551 case OPSIZE_WORD: |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
552 out = call(out, (char *)m68k_read_word_scratch1); |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
553 break; |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
554 case OPSIZE_LONG: |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
555 out = call(out, (char *)m68k_read_long_scratch1); |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
556 break; |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
557 } |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
558 out = pop_r(out, SCRATCH2); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
559 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
560 ea->mode = MODE_REG_DIRECT; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
561 ea->base = SCRATCH1; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
562 break; |
98
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
563 case MODE_PC_INDEX_DISP8: |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
564 out = cycles(out, fake_read ? (6 + inst->extra.size == OPSIZE_LONG ? 8 : 4) : 6); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
565 out = mov_ir(out, inst->address+2, SCRATCH1, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
566 sec_reg = (inst->dst.params.regs.sec >> 1) & 0x7; |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
567 if (inst->dst.params.regs.sec & 1) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
568 if (inst->dst.params.regs.sec & 0x10) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
569 if (opts->aregs[sec_reg] >= 0) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
570 out = add_rr(out, opts->aregs[sec_reg], SCRATCH1, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
571 } else { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
572 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
573 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
574 } else { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
575 if (opts->dregs[sec_reg] >= 0) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
576 out = add_rr(out, opts->dregs[sec_reg], SCRATCH1, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
577 } else { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
578 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
579 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
580 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
581 } else { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
582 if (inst->dst.params.regs.sec & 0x10) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
583 if (opts->aregs[sec_reg] >= 0) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
584 out = movsx_rr(out, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
585 } else { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
586 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
587 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
588 } else { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
589 if (opts->dregs[sec_reg] >= 0) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
590 out = movsx_rr(out, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
591 } else { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
592 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
593 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
594 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
595 out = add_rr(out, SCRATCH2, SCRATCH1, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
596 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
597 if (inst->dst.params.regs.displacement) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
598 out = add_ir(out, inst->dst.params.regs.displacement, SCRATCH1, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
599 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
600 if (fake_read) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
601 out = mov_rr(out, SCRATCH1, SCRATCH2, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
602 } else { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
603 out = push_r(out, SCRATCH1); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
604 switch (inst->extra.size) |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
605 { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
606 case OPSIZE_BYTE: |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
607 out = call(out, (char *)m68k_read_byte_scratch1); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
608 break; |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
609 case OPSIZE_WORD: |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
610 out = call(out, (char *)m68k_read_word_scratch1); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
611 break; |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
612 case OPSIZE_LONG: |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
613 out = call(out, (char *)m68k_read_long_scratch1); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
614 break; |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
615 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
616 out = pop_r(out, SCRATCH2); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
617 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
618 ea->mode = MODE_REG_DIRECT; |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
619 ea->base = SCRATCH1; |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
620 break; |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
621 case MODE_ABSOLUTE: |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
622 case MODE_ABSOLUTE_SHORT: |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
623 //Add cycles for reading address from instruction stream |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
624 out = cycles(out, (inst->dst.addr_mode == MODE_ABSOLUTE ? BUS*2 : BUS) + (fake_read ? (inst->extra.size == OPSIZE_LONG ? BUS*2 : BUS) : 0)); |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
625 out = mov_ir(out, inst->dst.params.immed, fake_read ? SCRATCH2 : SCRATCH1, SZ_D); |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
626 if (!fake_read) { |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
627 out = push_r(out, SCRATCH1); |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
628 switch (inst->extra.size) |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
629 { |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
630 case OPSIZE_BYTE: |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
631 out = call(out, (char *)m68k_read_byte_scratch1); |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
632 break; |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
633 case OPSIZE_WORD: |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
634 out = call(out, (char *)m68k_read_word_scratch1); |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
635 break; |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
636 case OPSIZE_LONG: |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
637 out = call(out, (char *)m68k_read_long_scratch1); |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
638 break; |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
639 } |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
640 out = pop_r(out, SCRATCH2); |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
641 } |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
642 ea->mode = MODE_REG_DIRECT; |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
643 ea->base = SCRATCH1; |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
644 break; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
645 default: |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
646 m68k_disasm(inst, disasm_buf); |
154
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
647 printf("%X: %s\naddress mode %d not implemented (dst)\n", inst->address, disasm_buf, inst->dst.addr_mode); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
648 exit(1); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
649 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
650 return out; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
651 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
652 |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
653 uint8_t * m68k_save_result(m68kinst * inst, uint8_t * out, x86_68k_options * opts) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
654 { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
655 if (inst->dst.addr_mode != MODE_REG && inst->dst.addr_mode != MODE_AREG) { |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
656 if (inst->dst.addr_mode == MODE_AREG_PREDEC && inst->src.addr_mode == MODE_AREG_PREDEC && inst->op != M68K_MOVE) { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
657 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
658 out = mov_rr(out, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
659 } else { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
660 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
661 } |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
662 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
663 switch (inst->extra.size) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
664 { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
665 case OPSIZE_BYTE: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
666 out = call(out, (char *)m68k_write_byte); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
667 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
668 case OPSIZE_WORD: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
669 out = call(out, (char *)m68k_write_word); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
670 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
671 case OPSIZE_LONG: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
672 out = call(out, (char *)m68k_write_long_lowfirst); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
673 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
674 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
675 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
676 return out; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
diff
changeset
|
677 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
678 |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
679 uint8_t * get_native_address(native_map_slot * native_code_map, uint32_t address) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
680 { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
681 address &= 0xFFFFFF; |
95
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
682 address /= 2; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
683 uint32_t chunk = address / NATIVE_CHUNK_SIZE; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
684 if (!native_code_map[chunk].base) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
685 return NULL; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
686 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
687 uint32_t offset = address % NATIVE_CHUNK_SIZE; |
193
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
688 if (native_code_map[chunk].offsets[offset] == INVALID_OFFSET || native_code_map[chunk].offsets[offset] == EXTENSION_WORD) { |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
diff
changeset
|
689 return NULL; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
690 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
diff
changeset
|
691 return native_code_map[chunk].base + native_code_map[chunk].offsets[offset]; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
692 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
693 |
193
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
694 uint32_t get_instruction_start(native_map_slot * native_code_map, uint32_t address) |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
695 { |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
696 address &= 0xFFFFFF; |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
697 address /= 2; |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
698 uint32_t chunk = address / NATIVE_CHUNK_SIZE; |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
699 if (!native_code_map[chunk].base) { |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
700 return 0; |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
701 } |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
702 uint32_t offset = address % NATIVE_CHUNK_SIZE; |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
703 if (native_code_map[chunk].offsets[offset] == INVALID_OFFSET) { |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
704 return 0; |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
705 } |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
706 while (native_code_map[chunk].offsets[offset] == EXTENSION_WORD) { |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
707 --address; |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
708 chunk = address / NATIVE_CHUNK_SIZE; |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
709 offset = address % NATIVE_CHUNK_SIZE; |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
710 } |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
711 return address*2; |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
712 } |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
713 |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
714 deferred_addr * defer_address(deferred_addr * old_head, uint32_t address, uint8_t *dest) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
715 { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
716 deferred_addr * new_head = malloc(sizeof(deferred_addr)); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
717 new_head->next = old_head; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
718 new_head->address = address & 0xFFFFFF; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
719 new_head->dest = dest; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
720 return new_head; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
721 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
722 |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
723 void process_deferred(x86_68k_options * opts) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
724 { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
725 deferred_addr * cur = opts->deferred; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
726 deferred_addr **last_next = &(opts->deferred); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
727 while(cur) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
728 { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
729 uint8_t * native = get_native_address(opts->native_code_map, cur->address); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
730 if (native) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
731 int32_t disp = native - (cur->dest + 4); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
732 uint8_t * out = cur->dest; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
733 *(out++) = disp; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
734 disp >>= 8; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
735 *(out++) = disp; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
736 disp >>= 8; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
737 *(out++) = disp; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
738 disp >>= 8; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
739 *out = disp; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
740 *last_next = cur->next; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
741 free(cur); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
742 cur = *last_next; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
743 } else { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
744 last_next = &(cur->next); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
745 cur = cur->next; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
746 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
747 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
748 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
749 |
192
1db07e112bf7
Prep work for handling games that modify code in RAM
Mike Pavone <pavone@retrodev.com>
parents:
188
diff
changeset
|
750 void map_native_address(m68k_context * context, uint32_t address, uint8_t * native_addr, uint8_t size, uint8_t native_size) |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
751 { |
192
1db07e112bf7
Prep work for handling games that modify code in RAM
Mike Pavone <pavone@retrodev.com>
parents:
188
diff
changeset
|
752 native_map_slot * native_code_map = context->native_code_map; |
1db07e112bf7
Prep work for handling games that modify code in RAM
Mike Pavone <pavone@retrodev.com>
parents:
188
diff
changeset
|
753 x86_68k_options * opts = context->options; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
754 address &= 0xFFFFFF; |
192
1db07e112bf7
Prep work for handling games that modify code in RAM
Mike Pavone <pavone@retrodev.com>
parents:
188
diff
changeset
|
755 if (address > 0xE00000) { |
1db07e112bf7
Prep work for handling games that modify code in RAM
Mike Pavone <pavone@retrodev.com>
parents:
188
diff
changeset
|
756 context->ram_code_flags[(address & 0xC000) >> 14] |= 1 << ((address & 0x3800) >> 11); |
1db07e112bf7
Prep work for handling games that modify code in RAM
Mike Pavone <pavone@retrodev.com>
parents:
188
diff
changeset
|
757 if (((address & 0x3FFF) + size) & 0xC000) { |
1db07e112bf7
Prep work for handling games that modify code in RAM
Mike Pavone <pavone@retrodev.com>
parents:
188
diff
changeset
|
758 context->ram_code_flags[((address+size) & 0xC000) >> 14] |= 1 << (((address+size) & 0x3800) >> 11); |
1db07e112bf7
Prep work for handling games that modify code in RAM
Mike Pavone <pavone@retrodev.com>
parents:
188
diff
changeset
|
759 } |
1db07e112bf7
Prep work for handling games that modify code in RAM
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|
760 uint32_t slot = (address & 0xFFFF)/1024; |
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761 if (!opts->ram_inst_sizes[slot]) { |
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diff
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|
762 opts->ram_inst_sizes[slot] = malloc(sizeof(uint8_t) * 512); |
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|
763 } |
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diff
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|
764 opts->ram_inst_sizes[slot][((address & 0xFFFF)/2)%512] = native_size; |
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diff
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|
765 } |
95
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
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parents:
93
diff
changeset
|
766 address/= 2; |
18
3e7bfde7606e
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diff
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|
767 uint32_t chunk = address / NATIVE_CHUNK_SIZE; |
3e7bfde7606e
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diff
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768 if (!native_code_map[chunk].base) { |
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diff
changeset
|
769 native_code_map[chunk].base = native_addr; |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
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81
diff
changeset
|
770 native_code_map[chunk].offsets = malloc(sizeof(int32_t) * NATIVE_CHUNK_SIZE); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
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diff
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|
771 memset(native_code_map[chunk].offsets, 0xFF, sizeof(int32_t) * NATIVE_CHUNK_SIZE); |
18
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diff
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|
772 } |
3e7bfde7606e
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diff
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|
773 uint32_t offset = address % NATIVE_CHUNK_SIZE; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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diff
changeset
|
774 native_code_map[chunk].offsets[offset] = native_addr-native_code_map[chunk].base; |
193
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parents:
192
diff
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|
775 for(address++,size-=2; size; address++,size-=2) { |
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192
diff
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|
776 chunk = address / NATIVE_CHUNK_SIZE; |
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Implement support for self-modifying code
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diff
changeset
|
777 offset = address % NATIVE_CHUNK_SIZE; |
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192
diff
changeset
|
778 if (!native_code_map[chunk].base) { |
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192
diff
changeset
|
779 native_code_map[chunk].base = native_addr; |
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diff
changeset
|
780 native_code_map[chunk].offsets = malloc(sizeof(int32_t) * NATIVE_CHUNK_SIZE); |
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diff
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|
781 memset(native_code_map[chunk].offsets, 0xFF, sizeof(int32_t) * NATIVE_CHUNK_SIZE); |
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diff
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|
782 } |
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|
783 native_code_map[chunk].offsets[offset] = EXTENSION_WORD; |
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|
784 } |
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diff
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|
785 } |
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|
786 |
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diff
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|
787 uint8_t get_native_inst_size(x86_68k_options * opts, uint32_t address) |
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|
788 { |
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diff
changeset
|
789 if (address < 0xE00000) { |
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diff
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|
790 return 0; |
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diff
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|
791 } |
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diff
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|
792 uint32_t slot = (address & 0xFFFF)/1024; |
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diff
changeset
|
793 return opts->ram_inst_sizes[slot][((address & 0xFFFF)/2)%512]; |
18
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diff
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|
794 } |
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diff
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|
795 |
3e7bfde7606e
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diff
changeset
|
796 uint8_t * translate_m68k_move(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
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diff
changeset
|
797 { |
99
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
798 int8_t reg, flags_reg, sec_reg; |
18
3e7bfde7606e
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diff
changeset
|
799 uint8_t dir = 0; |
3e7bfde7606e
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diff
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800 int32_t offset; |
3e7bfde7606e
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diff
changeset
|
801 int32_t inc_amount, dec_amount; |
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diff
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|
802 x86_ea src; |
3e7bfde7606e
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Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
803 dst = translate_m68k_src(inst, &src, dst, opts); |
3e7bfde7606e
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parents:
14
diff
changeset
|
804 reg = native_reg(&(inst->dst), opts); |
184
ebcbdd1c4cc8
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183
diff
changeset
|
805 if (inst->dst.addr_mode != MODE_AREG) { |
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parents:
183
diff
changeset
|
806 //update statically set flags |
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diff
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|
807 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
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Fix a bunch of bugs in the CPU core, add a 68K debugger
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183
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|
808 dst = mov_ir(dst, 0, FLAG_C, SZ_B); |
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Fix a bunch of bugs in the CPU core, add a 68K debugger
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parents:
183
diff
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|
809 } |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
810 |
216
0b5ec22dcda2
Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source.
Mike Pavone <pavone@retrodev.com>
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213
diff
changeset
|
811 if (inst->dst.addr_mode != MODE_AREG) { |
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Mike Pavone <pavone@retrodev.com>
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diff
changeset
|
812 if (src.mode == MODE_REG_DIRECT) { |
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213
diff
changeset
|
813 flags_reg = src.base; |
18
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parents:
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diff
changeset
|
814 } else { |
216
0b5ec22dcda2
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Mike Pavone <pavone@retrodev.com>
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diff
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|
815 if (reg >= 0) { |
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Mike Pavone <pavone@retrodev.com>
parents:
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diff
changeset
|
816 flags_reg = reg; |
128
fe598ffd85ce
Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents:
126
diff
changeset
|
817 } else { |
216
0b5ec22dcda2
Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source.
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213
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changeset
|
818 if(src.mode == MODE_REG_DISPLACE8) { |
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diff
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|
819 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size); |
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213
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|
820 } else { |
0b5ec22dcda2
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Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
821 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size); |
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Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source.
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diff
changeset
|
822 } |
0b5ec22dcda2
Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source.
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parents:
213
diff
changeset
|
823 src.mode = MODE_REG_DIRECT; |
0b5ec22dcda2
Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source.
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
824 flags_reg = src.base = SCRATCH1; |
128
fe598ffd85ce
Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents:
126
diff
changeset
|
825 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
diff
changeset
|
826 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
827 } |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
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179
diff
changeset
|
828 uint8_t size = inst->extra.size; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
829 switch(inst->dst.addr_mode) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
830 { |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
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diff
changeset
|
831 case MODE_AREG: |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
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179
diff
changeset
|
832 size = OPSIZE_LONG; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
833 case MODE_REG: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
diff
changeset
|
834 if (reg >= 0) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
diff
changeset
|
835 if (src.mode == MODE_REG_DIRECT) { |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
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parents:
179
diff
changeset
|
836 dst = mov_rr(dst, src.base, reg, size); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
837 } else if (src.mode == MODE_REG_DISPLACE8) { |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
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179
diff
changeset
|
838 dst = mov_rdisp8r(dst, src.base, src.disp, reg, size); |
18
3e7bfde7606e
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Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
839 } else { |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
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179
diff
changeset
|
840 dst = mov_ir(dst, src.disp, reg, size); |
18
3e7bfde7606e
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Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
841 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
842 } else if(src.mode == MODE_REG_DIRECT) { |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
843 dst = mov_rrdisp8(dst, src.base, CONTEXT, reg_offset(&(inst->dst)), size); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
844 } else { |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
845 dst = mov_irdisp8(dst, src.disp, CONTEXT, reg_offset(&(inst->dst)), size); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
846 } |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
847 if (inst->dst.addr_mode != MODE_AREG) { |
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parents:
183
diff
changeset
|
848 dst = cmp_ir(dst, 0, flags_reg, size); |
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183
diff
changeset
|
849 dst = setcc_r(dst, CC_Z, FLAG_Z); |
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183
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|
850 dst = setcc_r(dst, CC_S, FLAG_N); |
ebcbdd1c4cc8
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183
diff
changeset
|
851 } |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
852 break; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
853 case MODE_AREG_PREDEC: |
182
924af8b2f7a0
Fix -(a7) dest when size is byte
Mike Pavone <pavone@retrodev.com>
parents:
181
diff
changeset
|
854 dec_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : (inst->dst.params.regs.pri == 7 ? 2 : 1)); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
855 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
856 dst = sub_ir(dst, dec_amount, opts->aregs[inst->dst.params.regs.pri], SZ_D); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
857 } else { |
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
858 dst = sub_irdisp8(dst, dec_amount, CONTEXT, reg_offset(&(inst->dst)), SZ_D); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
859 } |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
860 case MODE_AREG_INDIRECT: |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
861 case MODE_AREG_POSTINC: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
862 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
863 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
864 } else { |
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
865 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
866 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
867 if (src.mode == MODE_REG_DIRECT) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
868 if (src.base != SCRATCH1) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
869 dst = mov_rr(dst, src.base, SCRATCH1, inst->extra.size); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
870 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
871 } else if (src.mode == MODE_REG_DISPLACE8) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
872 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
873 } else { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
874 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
875 } |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
876 if (inst->dst.addr_mode != MODE_AREG) { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
877 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
878 dst = setcc_r(dst, CC_Z, FLAG_Z); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
879 dst = setcc_r(dst, CC_S, FLAG_N); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
880 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
881 switch (inst->extra.size) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
882 { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
883 case OPSIZE_BYTE: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
884 dst = call(dst, (char *)m68k_write_byte); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
885 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
886 case OPSIZE_WORD: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
887 dst = call(dst, (char *)m68k_write_word); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
888 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
889 case OPSIZE_LONG: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
890 dst = call(dst, (char *)m68k_write_long_highfirst); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
891 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
892 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
893 if (inst->dst.addr_mode == MODE_AREG_POSTINC) { |
218
1abf8e967b33
Fix autoincrement on a7 when used as a destination in a byte sized instruction
Mike Pavone <pavone@retrodev.com>
parents:
216
diff
changeset
|
894 inc_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : (inst->dst.params.regs.pri == 7 ? 2 : 1)); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
895 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
896 dst = add_ir(dst, inc_amount, opts->aregs[inst->dst.params.regs.pri], SZ_D); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
897 } else { |
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
898 dst = add_irdisp8(dst, inc_amount, CONTEXT, reg_offset(&(inst->dst)), SZ_D); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
899 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
900 } |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
901 break; |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
902 case MODE_AREG_DISPLACE: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
903 dst = cycles(dst, BUS); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
904 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
905 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
906 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
907 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
908 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
909 dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH2, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
910 if (src.mode == MODE_REG_DIRECT) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
911 if (src.base != SCRATCH1) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
912 dst = mov_rr(dst, src.base, SCRATCH1, inst->extra.size); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
913 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
914 } else if (src.mode == MODE_REG_DISPLACE8) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
915 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
916 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
917 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
918 } |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
919 if (inst->dst.addr_mode != MODE_AREG) { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
920 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
921 dst = setcc_r(dst, CC_Z, FLAG_Z); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
922 dst = setcc_r(dst, CC_S, FLAG_N); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
923 } |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
924 switch (inst->extra.size) |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
925 { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
926 case OPSIZE_BYTE: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
927 dst = call(dst, (char *)m68k_write_byte); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
928 break; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
929 case OPSIZE_WORD: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
930 dst = call(dst, (char *)m68k_write_word); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
931 break; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
932 case OPSIZE_LONG: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
933 dst = call(dst, (char *)m68k_write_long_highfirst); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
934 break; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
935 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
936 break; |
99
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
937 case MODE_AREG_INDEX_DISP8: |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
938 dst = cycles(dst, 6);//TODO: Check to make sure this is correct |
107
9705075fcf36
Fix areg indexed mode for move dst
Mike Pavone <pavone@retrodev.com>
parents:
106
diff
changeset
|
939 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
9705075fcf36
Fix areg indexed mode for move dst
Mike Pavone <pavone@retrodev.com>
parents:
106
diff
changeset
|
940 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D); |
99
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
941 } else { |
107
9705075fcf36
Fix areg indexed mode for move dst
Mike Pavone <pavone@retrodev.com>
parents:
106
diff
changeset
|
942 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D); |
99
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
943 } |
107
9705075fcf36
Fix areg indexed mode for move dst
Mike Pavone <pavone@retrodev.com>
parents:
106
diff
changeset
|
944 sec_reg = (inst->dst.params.regs.sec >> 1) & 0x7; |
9705075fcf36
Fix areg indexed mode for move dst
Mike Pavone <pavone@retrodev.com>
parents:
106
diff
changeset
|
945 if (inst->dst.params.regs.sec & 1) { |
9705075fcf36
Fix areg indexed mode for move dst
Mike Pavone <pavone@retrodev.com>
parents:
106
diff
changeset
|
946 if (inst->dst.params.regs.sec & 0x10) { |
99
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
947 if (opts->aregs[sec_reg] >= 0) { |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
948 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_D); |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
949 } else { |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
950 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D); |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
951 } |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
952 } else { |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
953 if (opts->dregs[sec_reg] >= 0) { |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
954 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_D); |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
955 } else { |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
956 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D); |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
957 } |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
958 } |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
959 } else { |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
960 if (src.base == SCRATCH1) { |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
961 dst = push_r(dst, SCRATCH1); |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
962 } |
107
9705075fcf36
Fix areg indexed mode for move dst
Mike Pavone <pavone@retrodev.com>
parents:
106
diff
changeset
|
963 if (inst->dst.params.regs.sec & 0x10) { |
99
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
964 if (opts->aregs[sec_reg] >= 0) { |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
965 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_W, SZ_D); |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
966 } else { |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
967 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D); |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
968 } |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
969 } else { |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
970 if (opts->dregs[sec_reg] >= 0) { |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
971 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_W, SZ_D); |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
972 } else { |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
973 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D); |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
974 } |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
975 } |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
976 dst = add_rr(dst, SCRATCH1, SCRATCH2, SZ_D); |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
977 if (src.base == SCRATCH1) { |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
978 dst = pop_r(dst, SCRATCH1); |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
979 } |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
980 } |
107
9705075fcf36
Fix areg indexed mode for move dst
Mike Pavone <pavone@retrodev.com>
parents:
106
diff
changeset
|
981 if (inst->dst.params.regs.displacement) { |
9705075fcf36
Fix areg indexed mode for move dst
Mike Pavone <pavone@retrodev.com>
parents:
106
diff
changeset
|
982 dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH2, SZ_D); |
99
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
983 } |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
984 if (src.mode == MODE_REG_DIRECT) { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
985 if (src.base != SCRATCH1) { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
986 dst = mov_rr(dst, src.base, SCRATCH1, inst->extra.size); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
987 } |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
988 } else if (src.mode == MODE_REG_DISPLACE8) { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
989 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
990 } else { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
991 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
992 } |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
993 if (inst->dst.addr_mode != MODE_AREG) { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
994 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
995 dst = setcc_r(dst, CC_Z, FLAG_Z); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
996 dst = setcc_r(dst, CC_S, FLAG_N); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
997 } |
99
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
998 switch (inst->extra.size) |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
999 { |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
1000 case OPSIZE_BYTE: |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
1001 dst = call(dst, (char *)m68k_write_byte); |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
1002 break; |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
1003 case OPSIZE_WORD: |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
1004 dst = call(dst, (char *)m68k_write_word); |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
1005 break; |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
1006 case OPSIZE_LONG: |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
1007 dst = call(dst, (char *)m68k_write_long_highfirst); |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
1008 break; |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
1009 } |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
1010 break; |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1011 case MODE_PC_DISPLACE: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1012 dst = cycles(dst, BUS); |
74
6396dc91f61e
Fix some bugs in movem with a register list destination
Mike Pavone <pavone@retrodev.com>
parents:
73
diff
changeset
|
1013 dst = mov_ir(dst, inst->dst.params.regs.displacement + inst->address+2, SCRATCH2, SZ_D); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1014 if (src.mode == MODE_REG_DIRECT) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1015 if (src.base != SCRATCH1) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1016 dst = mov_rr(dst, src.base, SCRATCH1, inst->extra.size); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1017 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1018 } else if (src.mode == MODE_REG_DISPLACE8) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1019 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1020 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1021 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1022 } |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1023 if (inst->dst.addr_mode != MODE_AREG) { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1024 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1025 dst = setcc_r(dst, CC_Z, FLAG_Z); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1026 dst = setcc_r(dst, CC_S, FLAG_N); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1027 } |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1028 switch (inst->extra.size) |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1029 { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1030 case OPSIZE_BYTE: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1031 dst = call(dst, (char *)m68k_write_byte); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1032 break; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1033 case OPSIZE_WORD: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1034 dst = call(dst, (char *)m68k_write_word); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1035 break; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1036 case OPSIZE_LONG: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1037 dst = call(dst, (char *)m68k_write_long_highfirst); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1038 break; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1039 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1040 break; |
196
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1041 case MODE_PC_INDEX_DISP8: |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1042 dst = cycles(dst, 6);//TODO: Check to make sure this is correct |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1043 dst = mov_ir(dst, inst->address, SCRATCH2, SZ_D); |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1044 sec_reg = (inst->dst.params.regs.sec >> 1) & 0x7; |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1045 if (inst->dst.params.regs.sec & 1) { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1046 if (inst->dst.params.regs.sec & 0x10) { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1047 if (opts->aregs[sec_reg] >= 0) { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1048 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_D); |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1049 } else { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1050 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D); |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1051 } |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1052 } else { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1053 if (opts->dregs[sec_reg] >= 0) { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1054 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_D); |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1055 } else { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1056 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D); |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1057 } |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1058 } |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1059 } else { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1060 if (src.base == SCRATCH1) { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1061 dst = push_r(dst, SCRATCH1); |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1062 } |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1063 if (inst->dst.params.regs.sec & 0x10) { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1064 if (opts->aregs[sec_reg] >= 0) { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1065 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_W, SZ_D); |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1066 } else { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1067 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D); |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1068 } |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1069 } else { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1070 if (opts->dregs[sec_reg] >= 0) { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1071 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_W, SZ_D); |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1072 } else { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1073 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D); |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1074 } |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1075 } |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1076 dst = add_rr(dst, SCRATCH1, SCRATCH2, SZ_D); |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1077 if (src.base == SCRATCH1) { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1078 dst = pop_r(dst, SCRATCH1); |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1079 } |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1080 } |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1081 if (inst->dst.params.regs.displacement) { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1082 dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH2, SZ_D); |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1083 } |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1084 if (src.mode == MODE_REG_DIRECT) { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1085 if (src.base != SCRATCH1) { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1086 dst = mov_rr(dst, src.base, SCRATCH1, inst->extra.size); |
f8955d33486d
Implement pc indexed mode as move dst
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parents:
194
diff
changeset
|
1087 } |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1088 } else if (src.mode == MODE_REG_DISPLACE8) { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1089 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size); |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1090 } else { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1091 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size); |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1092 } |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1093 if (inst->dst.addr_mode != MODE_AREG) { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1094 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size); |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1095 dst = setcc_r(dst, CC_Z, FLAG_Z); |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1096 dst = setcc_r(dst, CC_S, FLAG_N); |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1097 } |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1098 switch (inst->extra.size) |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1099 { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1100 case OPSIZE_BYTE: |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1101 dst = call(dst, (char *)m68k_write_byte); |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1102 break; |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1103 case OPSIZE_WORD: |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1104 dst = call(dst, (char *)m68k_write_word); |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1105 break; |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1106 case OPSIZE_LONG: |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1107 dst = call(dst, (char *)m68k_write_long_highfirst); |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1108 break; |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1109 } |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1110 break; |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1111 case MODE_ABSOLUTE: |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1112 case MODE_ABSOLUTE_SHORT: |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1113 if (src.mode == MODE_REG_DIRECT) { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1114 if (src.base != SCRATCH1) { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1115 dst = mov_rr(dst, src.base, SCRATCH1, inst->extra.size); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1116 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1117 } else if (src.mode == MODE_REG_DISPLACE8) { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1118 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1119 } else { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1120 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1121 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1122 if (inst->dst.addr_mode == MODE_ABSOLUTE) { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1123 dst = cycles(dst, BUS*2); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1124 } else { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1125 dst = cycles(dst, BUS); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1126 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1127 dst = mov_ir(dst, inst->dst.params.immed, SCRATCH2, SZ_D); |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1128 if (inst->dst.addr_mode != MODE_AREG) { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1129 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1130 dst = setcc_r(dst, CC_Z, FLAG_Z); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1131 dst = setcc_r(dst, CC_S, FLAG_N); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1132 } |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1133 switch (inst->extra.size) |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1134 { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1135 case OPSIZE_BYTE: |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1136 dst = call(dst, (char *)m68k_write_byte); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1137 break; |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1138 case OPSIZE_WORD: |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1139 dst = call(dst, (char *)m68k_write_word); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1140 break; |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1141 case OPSIZE_LONG: |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1142 dst = call(dst, (char *)m68k_write_long_highfirst); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1143 break; |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1144 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1145 break; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1146 default: |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
1147 m68k_disasm(inst, disasm_buf); |
154
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
1148 printf("%X: %s\naddress mode %d not implemented (move dst)\n", inst->address, disasm_buf, inst->dst.addr_mode); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1149 exit(1); |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1150 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1151 |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1152 //add cycles for prefetch |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1153 dst = cycles(dst, BUS); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1154 return dst; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1155 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1156 |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1157 uint8_t * translate_m68k_movem(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1158 { |
161
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1159 int8_t bit,reg,sec_reg; |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1160 uint8_t early_cycles; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1161 if(inst->src.addr_mode == MODE_REG) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1162 //reg to mem |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1163 early_cycles = 8; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1164 int8_t dir; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1165 switch (inst->dst.addr_mode) |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1166 { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1167 case MODE_AREG_INDIRECT: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1168 case MODE_AREG_PREDEC: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1169 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1170 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1171 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1172 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1173 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1174 break; |
161
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1175 case MODE_AREG_DISPLACE: |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1176 early_cycles += BUS; |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1177 reg = SCRATCH2; |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1178 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1179 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1180 } else { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1181 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1182 } |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1183 dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH2, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1184 break; |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1185 case MODE_AREG_INDEX_DISP8: |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1186 early_cycles += 6; |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1187 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1188 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1189 } else { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1190 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1191 } |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1192 sec_reg = (inst->dst.params.regs.sec >> 1) & 0x7; |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1193 if (inst->dst.params.regs.sec & 1) { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1194 if (inst->dst.params.regs.sec & 0x10) { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1195 if (opts->aregs[sec_reg] >= 0) { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1196 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1197 } else { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1198 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1199 } |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1200 } else { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1201 if (opts->dregs[sec_reg] >= 0) { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1202 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1203 } else { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1204 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1205 } |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1206 } |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1207 } else { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1208 if (inst->dst.params.regs.sec & 0x10) { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1209 if (opts->aregs[sec_reg] >= 0) { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1210 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_W, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1211 } else { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1212 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1213 } |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1214 } else { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1215 if (opts->dregs[sec_reg] >= 0) { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1216 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_W, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1217 } else { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1218 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1219 } |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1220 } |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1221 dst = add_rr(dst, SCRATCH1, SCRATCH2, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1222 } |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1223 if (inst->dst.params.regs.displacement) { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1224 dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH2, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1225 } |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1226 break; |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1227 case MODE_PC_DISPLACE: |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1228 early_cycles += BUS; |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1229 dst = mov_ir(dst, inst->dst.params.regs.displacement + inst->address+2, SCRATCH2, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1230 break; |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1231 case MODE_PC_INDEX_DISP8: |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1232 early_cycles += 6; |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1233 dst = mov_ir(dst, inst->address+2, SCRATCH2, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1234 sec_reg = (inst->dst.params.regs.sec >> 1) & 0x7; |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1235 if (inst->dst.params.regs.sec & 1) { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1236 if (inst->dst.params.regs.sec & 0x10) { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1237 if (opts->aregs[sec_reg] >= 0) { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1238 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1239 } else { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1240 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1241 } |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1242 } else { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1243 if (opts->dregs[sec_reg] >= 0) { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1244 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1245 } else { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1246 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1247 } |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1248 } |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1249 } else { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1250 if (inst->dst.params.regs.sec & 0x10) { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1251 if (opts->aregs[sec_reg] >= 0) { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1252 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_W, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1253 } else { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1254 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1255 } |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1256 } else { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1257 if (opts->dregs[sec_reg] >= 0) { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1258 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_W, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1259 } else { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1260 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1261 } |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1262 } |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1263 dst = add_rr(dst, SCRATCH1, SCRATCH2, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1264 } |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1265 if (inst->dst.params.regs.displacement) { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1266 dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH2, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1267 } |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1268 break; |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1269 case MODE_ABSOLUTE: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1270 early_cycles += 4; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1271 case MODE_ABSOLUTE_SHORT: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1272 early_cycles += 4; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1273 dst = mov_ir(dst, inst->dst.params.immed, SCRATCH2, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1274 break; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1275 default: |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
1276 m68k_disasm(inst, disasm_buf); |
154
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
1277 printf("%X: %s\naddress mode %d not implemented (movem dst)\n", inst->address, disasm_buf, inst->dst.addr_mode); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1278 exit(1); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1279 } |
210
4beaad3a9a50
Fix movem reg to mem for certain addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
209
diff
changeset
|
1280 if (inst->dst.addr_mode == MODE_AREG_PREDEC) { |
4beaad3a9a50
Fix movem reg to mem for certain addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
209
diff
changeset
|
1281 reg = 15; |
4beaad3a9a50
Fix movem reg to mem for certain addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
209
diff
changeset
|
1282 dir = -1; |
4beaad3a9a50
Fix movem reg to mem for certain addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
209
diff
changeset
|
1283 } else { |
4beaad3a9a50
Fix movem reg to mem for certain addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
209
diff
changeset
|
1284 reg = 0; |
4beaad3a9a50
Fix movem reg to mem for certain addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
209
diff
changeset
|
1285 dir = 1; |
4beaad3a9a50
Fix movem reg to mem for certain addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
209
diff
changeset
|
1286 } |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1287 dst = cycles(dst, early_cycles); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1288 for(bit=0; reg < 16 && reg >= 0; reg += dir, bit++) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1289 if (inst->src.params.immed & (1 << bit)) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1290 if (inst->dst.addr_mode == MODE_AREG_PREDEC) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1291 dst = sub_ir(dst, (inst->extra.size == OPSIZE_LONG) ? 4 : 2, SCRATCH2, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1292 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1293 dst = push_r(dst, SCRATCH2); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1294 if (reg > 7) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1295 if (opts->aregs[reg-8] >= 0) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1296 dst = mov_rr(dst, opts->aregs[reg-8], SCRATCH1, inst->extra.size); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1297 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1298 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * (reg-8), SCRATCH1, inst->extra.size); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1299 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1300 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1301 if (opts->dregs[reg] >= 0) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1302 dst = mov_rr(dst, opts->dregs[reg], SCRATCH1, inst->extra.size); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1303 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1304 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t) * (reg), SCRATCH1, inst->extra.size); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1305 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1306 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1307 if (inst->extra.size == OPSIZE_LONG) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1308 dst = call(dst, (uint8_t *)m68k_write_long_lowfirst); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1309 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1310 dst = call(dst, (uint8_t *)m68k_write_word); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1311 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1312 dst = pop_r(dst, SCRATCH2); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1313 if (inst->dst.addr_mode != MODE_AREG_PREDEC) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1314 dst = add_ir(dst, (inst->extra.size == OPSIZE_LONG) ? 4 : 2, SCRATCH2, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1315 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1316 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1317 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1318 if (inst->dst.addr_mode == MODE_AREG_PREDEC) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1319 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1320 dst = mov_rr(dst, SCRATCH2, opts->aregs[inst->dst.params.regs.pri], SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1321 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1322 dst = mov_rrdisp8(dst, SCRATCH2, CONTEXT, reg_offset(&(inst->dst)), SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1323 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1324 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1325 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1326 //mem to reg |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1327 early_cycles = 4; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1328 switch (inst->src.addr_mode) |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1329 { |
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Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1330 case MODE_AREG_INDIRECT: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1331 case MODE_AREG_POSTINC: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1332 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1333 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
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Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1334 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1335 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1336 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1337 break; |
162
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1338 case MODE_AREG_DISPLACE: |
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Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1339 early_cycles += BUS; |
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Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1340 reg = SCRATCH2; |
169
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1341 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1342 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
162
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Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1343 } else { |
169
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1344 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); |
162
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1345 } |
169
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1346 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D); |
162
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1347 break; |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1348 case MODE_AREG_INDEX_DISP8: |
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Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1349 early_cycles += 6; |
169
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1350 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1351 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
162
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1352 } else { |
169
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1353 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); |
162
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1354 } |
169
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1355 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7; |
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1356 if (inst->src.params.regs.sec & 1) { |
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1357 if (inst->src.params.regs.sec & 0x10) { |
162
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1358 if (opts->aregs[sec_reg] >= 0) { |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1359 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D); |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1360 } else { |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1361 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1362 } |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1363 } else { |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1364 if (opts->dregs[sec_reg] >= 0) { |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1365 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_D); |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1366 } else { |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1367 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1368 } |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1369 } |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1370 } else { |
169
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1371 if (inst->src.params.regs.sec & 0x10) { |
162
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1372 if (opts->aregs[sec_reg] >= 0) { |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1373 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1374 } else { |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1375 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1376 } |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1377 } else { |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1378 if (opts->dregs[sec_reg] >= 0) { |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1379 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1380 } else { |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1381 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1382 } |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1383 } |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1384 dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D); |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1385 } |
169
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1386 if (inst->src.params.regs.displacement) { |
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1387 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D); |
162
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1388 } |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1389 break; |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1390 case MODE_PC_DISPLACE: |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1391 early_cycles += BUS; |
169
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1392 dst = mov_ir(dst, inst->src.params.regs.displacement + inst->address+2, SCRATCH1, SZ_D); |
162
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1393 break; |
eba78ad49a11
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Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1394 case MODE_PC_INDEX_DISP8: |
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Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1395 early_cycles += 6; |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1396 dst = mov_ir(dst, inst->address+2, SCRATCH1, SZ_D); |
169
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1397 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7; |
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1398 if (inst->src.params.regs.sec & 1) { |
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1399 if (inst->src.params.regs.sec & 0x10) { |
162
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1400 if (opts->aregs[sec_reg] >= 0) { |
eba78ad49a11
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Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1401 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D); |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1402 } else { |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1403 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1404 } |
eba78ad49a11
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Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1405 } else { |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1406 if (opts->dregs[sec_reg] >= 0) { |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1407 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_D); |
eba78ad49a11
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Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1408 } else { |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1409 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1410 } |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1411 } |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1412 } else { |
169
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1413 if (inst->src.params.regs.sec & 0x10) { |
162
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1414 if (opts->aregs[sec_reg] >= 0) { |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1415 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1416 } else { |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1417 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1418 } |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1419 } else { |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1420 if (opts->dregs[sec_reg] >= 0) { |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1421 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1422 } else { |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1423 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1424 } |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1425 } |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1426 dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D); |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1427 } |
169
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1428 if (inst->src.params.regs.displacement) { |
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1429 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D); |
162
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1430 } |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1431 break; |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1432 case MODE_ABSOLUTE: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1433 early_cycles += 4; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1434 case MODE_ABSOLUTE_SHORT: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1435 early_cycles += 4; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1436 dst = mov_ir(dst, inst->src.params.immed, SCRATCH1, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1437 break; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1438 default: |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
1439 m68k_disasm(inst, disasm_buf); |
154
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
1440 printf("%X: %s\naddress mode %d not implemented (movem src)\n", inst->address, disasm_buf, inst->src.addr_mode); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1441 exit(1); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1442 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1443 dst = cycles(dst, early_cycles); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1444 for(reg = 0; reg < 16; reg ++) { |
74
6396dc91f61e
Fix some bugs in movem with a register list destination
Mike Pavone <pavone@retrodev.com>
parents:
73
diff
changeset
|
1445 if (inst->dst.params.immed & (1 << reg)) { |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1446 dst = push_r(dst, SCRATCH1); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1447 if (inst->extra.size == OPSIZE_LONG) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1448 dst = call(dst, (uint8_t *)m68k_read_long_scratch1); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1449 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1450 dst = call(dst, (uint8_t *)m68k_read_word_scratch1); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1451 } |
188
062e3aa549eb
Fix movem.w when dest is register list
Mike Pavone <pavone@retrodev.com>
parents:
187
diff
changeset
|
1452 if (inst->extra.size == OPSIZE_WORD) { |
062e3aa549eb
Fix movem.w when dest is register list
Mike Pavone <pavone@retrodev.com>
parents:
187
diff
changeset
|
1453 dst = movsx_rr(dst, SCRATCH1, SCRATCH1, SZ_W, SZ_D); |
062e3aa549eb
Fix movem.w when dest is register list
Mike Pavone <pavone@retrodev.com>
parents:
187
diff
changeset
|
1454 } |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1455 if (reg > 7) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1456 if (opts->aregs[reg-8] >= 0) { |
188
062e3aa549eb
Fix movem.w when dest is register list
Mike Pavone <pavone@retrodev.com>
parents:
187
diff
changeset
|
1457 dst = mov_rr(dst, SCRATCH1, opts->aregs[reg-8], SZ_D); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1458 } else { |
188
062e3aa549eb
Fix movem.w when dest is register list
Mike Pavone <pavone@retrodev.com>
parents:
187
diff
changeset
|
1459 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * (reg-8), SZ_D); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1460 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1461 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1462 if (opts->dregs[reg] >= 0) { |
188
062e3aa549eb
Fix movem.w when dest is register list
Mike Pavone <pavone@retrodev.com>
parents:
187
diff
changeset
|
1463 dst = mov_rr(dst, SCRATCH1, opts->dregs[reg], SZ_D); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1464 } else { |
188
062e3aa549eb
Fix movem.w when dest is register list
Mike Pavone <pavone@retrodev.com>
parents:
187
diff
changeset
|
1465 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t) * (reg), SZ_D); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1466 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1467 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1468 dst = pop_r(dst, SCRATCH1); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1469 dst = add_ir(dst, (inst->extra.size == OPSIZE_LONG) ? 4 : 2, SCRATCH1, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1470 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1471 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1472 if (inst->src.addr_mode == MODE_AREG_POSTINC) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1473 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
74
6396dc91f61e
Fix some bugs in movem with a register list destination
Mike Pavone <pavone@retrodev.com>
parents:
73
diff
changeset
|
1474 dst = mov_rr(dst, SCRATCH1, opts->aregs[inst->src.params.regs.pri], SZ_D); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1475 } else { |
74
6396dc91f61e
Fix some bugs in movem with a register list destination
Mike Pavone <pavone@retrodev.com>
parents:
73
diff
changeset
|
1476 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, reg_offset(&(inst->src)), SZ_D); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1477 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1478 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1479 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1480 //prefetch |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1481 dst = cycles(dst, 4); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1482 return dst; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1483 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1484 |
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
1485 uint8_t * translate_m68k_clr(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
1486 { |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
1487 dst = mov_ir(dst, 0, FLAG_N, SZ_B); |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
1488 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
1489 dst = mov_ir(dst, 0, FLAG_C, SZ_B); |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
1490 dst = mov_ir(dst, 1, FLAG_Z, SZ_B); |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
1491 int8_t reg = native_reg(&(inst->dst), opts); |
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
1492 if (reg >= 0) { |
64
2b1a65f4b85d
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents:
61
diff
changeset
|
1493 dst = cycles(dst, (inst->extra.size == OPSIZE_LONG ? 6 : 4)); |
2b1a65f4b85d
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents:
61
diff
changeset
|
1494 return xor_rr(dst, reg, reg, inst->extra.size); |
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
1495 } |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
1496 x86_ea dst_op; |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
1497 dst = translate_m68k_dst(inst, &dst_op, dst, opts, 1); |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
1498 if (dst_op.mode == MODE_REG_DIRECT) { |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
1499 dst = xor_rr(dst, dst_op.base, dst_op.base, inst->extra.size); |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
1500 } else { |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
1501 dst = mov_irdisp8(dst, 0, dst_op.base, dst_op.disp, inst->extra.size); |
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
1502 } |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
1503 dst = m68k_save_result(inst, dst, opts); |
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
1504 return dst; |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
1505 } |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
1506 |
93
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1507 uint8_t * translate_m68k_ext(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1508 { |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1509 x86_ea dst_op; |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1510 uint8_t dst_size = inst->extra.size; |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1511 inst->extra.size--; |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1512 dst = translate_m68k_dst(inst, &dst_op, dst, opts, 0); |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1513 if (dst_op.mode == MODE_REG_DIRECT) { |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1514 dst = movsx_rr(dst, dst_op.base, dst_op.base, inst->extra.size, dst_size); |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1515 dst = cmp_ir(dst, 0, dst_op.base, dst_size); |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1516 } else { |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1517 dst = movsx_rdisp8r(dst, dst_op.base, dst_op.disp, SCRATCH1, inst->extra.size, dst_size); |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1518 dst = cmp_ir(dst, 0, SCRATCH1, dst_size); |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1519 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, dst_size); |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1520 } |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1521 inst->extra.size = dst_size; |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1522 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1523 dst = mov_ir(dst, 0, FLAG_C, SZ_B); |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1524 dst = setcc_r(dst, CC_Z, FLAG_Z); |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1525 dst = setcc_r(dst, CC_S, FLAG_N); |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1526 //M68K EXT only operates on registers so no need for a call to save result here |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1527 return dst; |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1528 } |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1529 |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1530 uint8_t * translate_m68k_lea(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1531 { |
100
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1532 int8_t dst_reg = native_reg(&(inst->dst), opts), sec_reg; |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1533 switch(inst->src.addr_mode) |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1534 { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1535 case MODE_AREG_INDIRECT: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1536 dst = cycles(dst, BUS); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1537 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1538 if (dst_reg >= 0) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1539 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], dst_reg, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1540 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1541 dst = mov_rrdisp8(dst, opts->aregs[inst->src.params.regs.pri], CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->dst.params.regs.pri, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1542 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1543 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1544 if (dst_reg >= 0) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1545 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, dst_reg, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1546 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1547 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, SCRATCH1, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1548 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->dst.params.regs.pri, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1549 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1550 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1551 break; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1552 case MODE_AREG_DISPLACE: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1553 dst = cycles(dst, 8); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1554 if (dst_reg >= 0) { |
168
7b099f2b382b
Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents:
167
diff
changeset
|
1555 if (inst->src.params.regs.pri != inst->dst.params.regs.pri) { |
7b099f2b382b
Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents:
167
diff
changeset
|
1556 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
7b099f2b382b
Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents:
167
diff
changeset
|
1557 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], dst_reg, SZ_D); |
7b099f2b382b
Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents:
167
diff
changeset
|
1558 } else { |
7b099f2b382b
Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents:
167
diff
changeset
|
1559 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), dst_reg, SZ_D); |
7b099f2b382b
Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents:
167
diff
changeset
|
1560 } |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1561 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1562 dst = add_ir(dst, inst->src.params.regs.displacement, dst_reg, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1563 } else { |
168
7b099f2b382b
Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents:
167
diff
changeset
|
1564 if (inst->src.params.regs.pri != inst->dst.params.regs.pri) { |
7b099f2b382b
Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents:
167
diff
changeset
|
1565 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
7b099f2b382b
Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents:
167
diff
changeset
|
1566 dst = mov_rrdisp8(dst, opts->aregs[inst->src.params.regs.pri], CONTEXT, reg_offset(&(inst->dst)), SZ_D); |
7b099f2b382b
Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents:
167
diff
changeset
|
1567 } else { |
7b099f2b382b
Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents:
167
diff
changeset
|
1568 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); |
7b099f2b382b
Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents:
167
diff
changeset
|
1569 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, reg_offset(&(inst->dst)), SZ_D); |
7b099f2b382b
Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents:
167
diff
changeset
|
1570 } |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1571 } |
165
62b152811bae
Fix certain address modes with lea when the destination is not a native register
Mike Pavone <pavone@retrodev.com>
parents:
162
diff
changeset
|
1572 dst = add_irdisp8(dst, inst->src.params.regs.displacement, CONTEXT, reg_offset(&(inst->dst)), SZ_D); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1573 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1574 break; |
100
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1575 case MODE_AREG_INDEX_DISP8: |
168
7b099f2b382b
Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents:
167
diff
changeset
|
1576 dst = cycles(dst, 12); |
100
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1577 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1578 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH2, SZ_D); |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1579 } else { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1580 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH2, SZ_D); |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1581 } |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1582 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7; |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1583 if (inst->src.params.regs.sec & 1) { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1584 if (inst->src.params.regs.sec & 0x10) { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1585 if (opts->aregs[sec_reg] >= 0) { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1586 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_D); |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1587 } else { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1588 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D); |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1589 } |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1590 } else { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1591 if (opts->dregs[sec_reg] >= 0) { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1592 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_D); |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1593 } else { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1594 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D); |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1595 } |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1596 } |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1597 } else { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1598 if (inst->src.params.regs.sec & 0x10) { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1599 if (opts->aregs[sec_reg] >= 0) { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1600 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_W, SZ_D); |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1601 } else { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1602 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D); |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1603 } |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1604 } else { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1605 if (opts->dregs[sec_reg] >= 0) { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1606 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_W, SZ_D); |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1607 } else { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1608 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D); |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1609 } |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1610 } |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1611 dst = add_rr(dst, SCRATCH1, SCRATCH2, SZ_D); |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1612 } |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1613 if (inst->src.params.regs.displacement) { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1614 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH2, SZ_D); |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1615 } |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1616 if (dst_reg >= 0) { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1617 dst = mov_rr(dst, SCRATCH2, dst_reg, SZ_D); |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1618 } else { |
165
62b152811bae
Fix certain address modes with lea when the destination is not a native register
Mike Pavone <pavone@retrodev.com>
parents:
162
diff
changeset
|
1619 dst = mov_rrdisp8(dst, SCRATCH2, CONTEXT, reg_offset(&(inst->dst)), SZ_D); |
100
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1620 } |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1621 break; |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1622 case MODE_PC_DISPLACE: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1623 dst = cycles(dst, 8); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1624 if (dst_reg >= 0) { |
74
6396dc91f61e
Fix some bugs in movem with a register list destination
Mike Pavone <pavone@retrodev.com>
parents:
73
diff
changeset
|
1625 dst = mov_ir(dst, inst->src.params.regs.displacement + inst->address+2, dst_reg, SZ_D); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1626 } else { |
74
6396dc91f61e
Fix some bugs in movem with a register list destination
Mike Pavone <pavone@retrodev.com>
parents:
73
diff
changeset
|
1627 dst = mov_irdisp8(dst, inst->src.params.regs.displacement + inst->address+2, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->dst.params.regs.pri, SZ_D); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1628 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1629 break; |
133
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1630 case MODE_PC_INDEX_DISP8: |
168
7b099f2b382b
Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents:
167
diff
changeset
|
1631 dst = cycles(dst, BUS*3); |
133
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1632 dst = mov_ir(dst, inst->address+2, SCRATCH1, SZ_D); |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1633 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7; |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1634 if (inst->src.params.regs.sec & 1) { |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1635 if (inst->src.params.regs.sec & 0x10) { |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1636 if (opts->aregs[sec_reg] >= 0) { |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1637 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D); |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1638 } else { |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1639 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1640 } |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1641 } else { |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1642 if (opts->dregs[sec_reg] >= 0) { |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1643 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_D); |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1644 } else { |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1645 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1646 } |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1647 } |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1648 } else { |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1649 if (inst->src.params.regs.sec & 0x10) { |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1650 if (opts->aregs[sec_reg] >= 0) { |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1651 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1652 } else { |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1653 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1654 } |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1655 } else { |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1656 if (opts->dregs[sec_reg] >= 0) { |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1657 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1658 } else { |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1659 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1660 } |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1661 } |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1662 dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D); |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1663 } |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1664 if (inst->src.params.regs.displacement) { |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1665 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D); |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1666 } |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1667 if (dst_reg >= 0) { |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1668 dst = mov_rr(dst, SCRATCH1, dst_reg, SZ_D); |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1669 } else { |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1670 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, reg_offset(&(inst->dst)), SZ_D); |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1671 } |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1672 break; |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1673 case MODE_ABSOLUTE: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1674 case MODE_ABSOLUTE_SHORT: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1675 dst = cycles(dst, (inst->src.addr_mode == MODE_ABSOLUTE) ? BUS * 3 : BUS * 2); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1676 if (dst_reg >= 0) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1677 dst = mov_ir(dst, inst->src.params.immed, dst_reg, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1678 } else { |
133
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1679 dst = mov_irdisp8(dst, inst->src.params.immed, CONTEXT, reg_offset(&(inst->dst)), SZ_D); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1680 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1681 break; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1682 default: |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
1683 m68k_disasm(inst, disasm_buf); |
154
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
1684 printf("%X: %s\naddress mode %d not implemented (lea src)\n", inst->address, disasm_buf, inst->src.addr_mode); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1685 exit(1); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1686 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1687 return dst; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1688 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1689 |
116
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1690 uint8_t * translate_m68k_pea(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1691 { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1692 uint8_t sec_reg; |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1693 switch(inst->src.addr_mode) |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1694 { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1695 case MODE_AREG_INDIRECT: |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1696 dst = cycles(dst, BUS); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1697 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1698 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1699 } else { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1700 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, SCRATCH1, SZ_D); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1701 } |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1702 break; |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1703 case MODE_AREG_DISPLACE: |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1704 dst = cycles(dst, 8); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1705 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1706 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1707 } else { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1708 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1709 } |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1710 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1711 break; |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1712 case MODE_AREG_INDEX_DISP8: |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1713 dst = cycles(dst, 6);//TODO: Check to make sure this is correct |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1714 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1715 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1716 } else { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1717 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1718 } |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1719 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7; |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1720 if (inst->src.params.regs.sec & 1) { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1721 if (inst->src.params.regs.sec & 0x10) { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1722 if (opts->aregs[sec_reg] >= 0) { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1723 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1724 } else { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1725 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1726 } |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1727 } else { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1728 if (opts->dregs[sec_reg] >= 0) { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1729 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_D); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1730 } else { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1731 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1732 } |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1733 } |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1734 } else { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1735 if (inst->src.params.regs.sec & 0x10) { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1736 if (opts->aregs[sec_reg] >= 0) { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1737 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1738 } else { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1739 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1740 } |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1741 } else { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1742 if (opts->dregs[sec_reg] >= 0) { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1743 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1744 } else { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1745 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1746 } |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1747 } |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1748 dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1749 } |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1750 if (inst->src.params.regs.displacement) { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1751 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1752 } |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1753 break; |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1754 case MODE_PC_DISPLACE: |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1755 dst = cycles(dst, 8); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1756 dst = mov_ir(dst, inst->src.params.regs.displacement + inst->address+2, SCRATCH1, SZ_D); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1757 break; |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1758 case MODE_ABSOLUTE: |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1759 case MODE_ABSOLUTE_SHORT: |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1760 dst = cycles(dst, (inst->src.addr_mode == MODE_ABSOLUTE) ? BUS * 3 : BUS * 2); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1761 dst = mov_ir(dst, inst->src.params.immed, SCRATCH1, SZ_D); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1762 break; |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1763 default: |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
1764 m68k_disasm(inst, disasm_buf); |
154
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
1765 printf("%X: %s\naddress mode %d not implemented (lea src)\n", inst->address, disasm_buf, inst->src.addr_mode); |
116
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1766 exit(1); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1767 } |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1768 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1769 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1770 dst = call(dst, (uint8_t *)m68k_write_long_lowfirst); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1771 return dst; |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1772 } |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1773 |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1774 uint8_t * translate_m68k_bsr(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1775 { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1776 int32_t disp = inst->src.params.immed; |
154
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
1777 uint32_t after = inst->address + (inst->variant == VAR_BYTE ? 2 : 4); |
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1778 //TODO: Add cycles in the right place relative to pushing the return address on the stack |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1779 dst = cycles(dst, 10); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1780 dst = mov_ir(dst, after, SCRATCH1, SZ_D); |
155
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
1781 if (opts->flags & OPT_NATIVE_CALL_STACK) { |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
1782 dst = push_r(dst, SCRATCH1); |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
1783 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1784 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1785 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1786 dst = call(dst, (char *)m68k_write_long_highfirst); |
154
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
1787 uint8_t * dest_addr = get_native_address(opts->native_code_map, (inst->address+2) + disp); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1788 if (!dest_addr) { |
154
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
1789 opts->deferred = defer_address(opts->deferred, (inst->address+2) + disp, dst + 1); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1790 //dummy address to be replaced later |
155
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
1791 dest_addr = dst + 256; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1792 } |
155
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
1793 if (opts->flags & OPT_NATIVE_CALL_STACK) { |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
1794 dst = call(dst, (char *)dest_addr); |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
1795 //would add_ir(dst, 8, RSP, SZ_Q) be faster here? |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
1796 dst = pop_r(dst, SCRATCH1); |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
1797 } else { |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
1798 dst = jmp(dst, (char *)dest_addr); |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
1799 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1800 return dst; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1801 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1802 |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1803 uint8_t * translate_m68k_bcc(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1804 { |
156
3900cfde9dbb
Add cycles for Bcc (needs work, but this changes keeps some ROMs from making the emulator unresponsive)
Mike Pavone <pavone@retrodev.com>
parents:
155
diff
changeset
|
1805 dst = cycles(dst, 10);//TODO: Adjust this for branch not taken case |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1806 int32_t disp = inst->src.params.immed; |
46
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1807 uint32_t after = inst->address + 2; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1808 uint8_t * dest_addr = get_native_address(opts->native_code_map, after + disp); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1809 if (inst->extra.cond == COND_TRUE) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1810 if (!dest_addr) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1811 opts->deferred = defer_address(opts->deferred, after + disp, dst + 1); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1812 //dummy address to be replaced later, make sure it generates a 4-byte displacement |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1813 dest_addr = dst + 256; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1814 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1815 dst = jmp(dst, dest_addr); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1816 } else { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1817 uint8_t cond = CC_NZ; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1818 switch (inst->extra.cond) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1819 { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1820 case COND_HIGH: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1821 cond = CC_Z; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1822 case COND_LOW_SAME: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1823 dst = mov_rr(dst, FLAG_Z, SCRATCH1, SZ_B); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1824 dst = or_rr(dst, FLAG_C, SCRATCH1, SZ_B); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1825 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1826 case COND_CARRY_CLR: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1827 cond = CC_Z; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1828 case COND_CARRY_SET: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1829 dst = cmp_ir(dst, 0, FLAG_C, SZ_B); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1830 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1831 case COND_NOT_EQ: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1832 cond = CC_Z; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1833 case COND_EQ: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1834 dst = cmp_ir(dst, 0, FLAG_Z, SZ_B); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1835 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1836 case COND_OVERF_CLR: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1837 cond = CC_Z; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1838 case COND_OVERF_SET: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1839 dst = cmp_ir(dst, 0, FLAG_V, SZ_B); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1840 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1841 case COND_PLUS: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1842 cond = CC_Z; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1843 case COND_MINUS: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1844 dst = cmp_ir(dst, 0, FLAG_N, SZ_B); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1845 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1846 case COND_GREATER_EQ: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1847 cond = CC_Z; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
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1848 case COND_LESS: |
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1849 dst = cmp_rr(dst, FLAG_N, FLAG_V, SZ_B); |
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1850 break; |
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1851 case COND_GREATER: |
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1852 cond = CC_Z; |
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1853 case COND_LESS_EQ: |
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1854 dst = mov_rr(dst, FLAG_V, SCRATCH1, SZ_B); |
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1855 dst = xor_rr(dst, FLAG_N, SCRATCH1, SZ_B); |
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1856 dst = or_rr(dst, FLAG_Z, SCRATCH1, SZ_B); |
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1857 break; |
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1858 } |
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1859 if (!dest_addr) { |
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1860 opts->deferred = defer_address(opts->deferred, after + disp, dst + 2); |
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1861 //dummy address to be replaced later, make sure it generates a 4-byte displacement |
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1862 dest_addr = dst + 256; |
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1863 } |
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1864 dst = jcc(dst, cond, dest_addr); |
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1865 } |
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1866 return dst; |
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1867 } |
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1868 |
112 | 1869 uint8_t * translate_m68k_scc(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
1870 { | |
1871 uint8_t cond = inst->extra.cond; | |
1872 x86_ea dst_op; | |
1873 inst->extra.size = OPSIZE_BYTE; | |
1874 dst = translate_m68k_dst(inst, &dst_op, dst, opts, 1); | |
1875 if (cond == COND_TRUE || cond == COND_FALSE) { | |
1876 if ((inst->dst.addr_mode == MODE_REG || inst->dst.addr_mode == MODE_AREG) && inst->extra.cond == COND_TRUE) { | |
1877 dst = cycles(dst, 6); | |
1878 } else { | |
1879 dst = cycles(dst, BUS); | |
1880 } | |
1881 if (dst_op.mode == MODE_REG_DIRECT) { | |
179
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1882 dst = mov_ir(dst, cond == COND_TRUE ? 0xFF : 0, dst_op.base, SZ_B); |
112 | 1883 } else { |
179
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1884 dst = mov_irdisp8(dst, cond == COND_TRUE ? 0xFF : 0, dst_op.base, dst_op.disp, SZ_B); |
112 | 1885 } |
1886 } else { | |
1887 uint8_t cc = CC_NZ; | |
1888 switch (cond) | |
1889 { | |
1890 case COND_HIGH: | |
1891 cc = CC_Z; | |
1892 case COND_LOW_SAME: | |
1893 dst = mov_rr(dst, FLAG_Z, SCRATCH1, SZ_B); | |
1894 dst = or_rr(dst, FLAG_C, SCRATCH1, SZ_B); | |
1895 break; | |
1896 case COND_CARRY_CLR: | |
1897 cc = CC_Z; | |
1898 case COND_CARRY_SET: | |
1899 dst = cmp_ir(dst, 0, FLAG_C, SZ_B); | |
1900 break; | |
1901 case COND_NOT_EQ: | |
1902 cc = CC_Z; | |
1903 case COND_EQ: | |
1904 dst = cmp_ir(dst, 0, FLAG_Z, SZ_B); | |
1905 break; | |
1906 case COND_OVERF_CLR: | |
1907 cc = CC_Z; | |
1908 case COND_OVERF_SET: | |
1909 dst = cmp_ir(dst, 0, FLAG_V, SZ_B); | |
1910 break; | |
1911 case COND_PLUS: | |
1912 cc = CC_Z; | |
1913 case COND_MINUS: | |
1914 dst = cmp_ir(dst, 0, FLAG_N, SZ_B); | |
1915 break; | |
1916 case COND_GREATER_EQ: | |
1917 cc = CC_Z; | |
1918 case COND_LESS: | |
1919 dst = cmp_rr(dst, FLAG_N, FLAG_V, SZ_B); | |
1920 break; | |
1921 case COND_GREATER: | |
1922 cc = CC_Z; | |
1923 case COND_LESS_EQ: | |
1924 dst = mov_rr(dst, FLAG_V, SCRATCH1, SZ_B); | |
1925 dst = xor_rr(dst, FLAG_N, SCRATCH1, SZ_B); | |
1926 dst = or_rr(dst, FLAG_Z, SCRATCH1, SZ_B); | |
1927 break; | |
1928 } | |
179
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1929 uint8_t *true_off = dst + 1; |
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1930 dst = jcc(dst, cc, dst+2); |
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1931 dst = cycles(dst, BUS); |
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1932 if (dst_op.mode == MODE_REG_DIRECT) { |
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1933 dst = mov_ir(dst, 0, dst_op.base, SZ_B); |
112 | 1934 } else { |
179
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1935 dst = mov_irdisp8(dst, 0, dst_op.base, dst_op.disp, SZ_B); |
112 | 1936 } |
179
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1937 uint8_t *end_off = dst+1; |
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1938 dst = jmp(dst, dst+2); |
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1939 *true_off = dst - (true_off+1); |
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1940 dst = cycles(dst, 6); |
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1941 if (dst_op.mode == MODE_REG_DIRECT) { |
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1942 dst = mov_ir(dst, 0xFF, dst_op.base, SZ_B); |
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1943 } else { |
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1944 dst = mov_irdisp8(dst, 0xFF, dst_op.base, dst_op.disp, SZ_B); |
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1945 } |
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1946 *end_off = dst - (end_off+1); |
112 | 1947 } |
1948 dst = m68k_save_result(inst, dst, opts); | |
1949 return dst; | |
1950 } | |
1951 | |
53
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1952 uint8_t * translate_m68k_jmp(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
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1953 { |
132
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1954 uint8_t * dest_addr, sec_reg; |
124
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1955 uint32_t m68k_addr; |
71
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1956 switch(inst->src.addr_mode) |
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1957 { |
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1958 case MODE_AREG_INDIRECT: |
76
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1959 dst = cycles(dst, BUS*2); |
71
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1960 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
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1961 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
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1962 } else { |
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1963 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, SCRATCH1, SZ_D); |
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1964 } |
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1965 dst = call(dst, (uint8_t *)m68k_native_addr); |
81
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1966 dst = jmp_r(dst, SCRATCH1); |
76
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1967 break; |
132
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1968 case MODE_AREG_INDEX_DISP8: |
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1969 dst = cycles(dst, BUS*3);//TODO: CHeck that this is correct |
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1970 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
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1971 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
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1972 } else { |
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1973 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); |
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1974 } |
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1975 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7; |
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1976 if (inst->src.params.regs.sec & 1) { |
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1977 if (inst->src.params.regs.sec & 0x10) { |
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1978 if (opts->aregs[sec_reg] >= 0) { |
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1979 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D); |
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1980 } else { |
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1981 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
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1982 } |
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1983 } else { |
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1984 if (opts->dregs[sec_reg] >= 0) { |
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1985 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_D); |
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1986 } else { |
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1987 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
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1988 } |
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1989 } |
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1990 } else { |
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1991 if (inst->src.params.regs.sec & 0x10) { |
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1992 if (opts->aregs[sec_reg] >= 0) { |
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1993 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
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1994 } else { |
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1995 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
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1996 } |
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1997 } else { |
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1998 if (opts->dregs[sec_reg] >= 0) { |
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1999 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
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2000 } else { |
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2001 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
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2002 } |
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2003 } |
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2004 dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D); |
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2005 } |
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2006 if (inst->src.params.regs.displacement) { |
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2007 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D); |
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2008 } |
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|
2009 dst = call(dst, (uint8_t *)m68k_native_addr); |
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|
2010 dst = jmp_r(dst, SCRATCH1); |
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129
diff
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|
2011 break; |
76
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74
diff
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|
2012 case MODE_PC_DISPLACE: |
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Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
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74
diff
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|
2013 dst = cycles(dst, 10); |
124
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123
diff
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|
2014 m68k_addr = inst->src.params.regs.displacement + inst->address + 2; |
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123
diff
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|
2015 if ((m68k_addr & 0xFFFFFF) < 0x400000) { |
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123
diff
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|
2016 dest_addr = get_native_address(opts->native_code_map, m68k_addr); |
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123
diff
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|
2017 if (!dest_addr) { |
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123
diff
changeset
|
2018 opts->deferred = defer_address(opts->deferred, m68k_addr, dst + 1); |
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Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
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123
diff
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|
2019 //dummy address to be replaced later, make sure it generates a 4-byte displacement |
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123
diff
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|
2020 dest_addr = dst + 256; |
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123
diff
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|
2021 } |
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123
diff
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|
2022 dst = jmp(dst, dest_addr); |
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123
diff
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|
2023 } else { |
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123
diff
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|
2024 dst = mov_ir(dst, m68k_addr, SCRATCH1, SZ_D); |
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diff
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|
2025 dst = call(dst, (uint8_t *)m68k_native_addr); |
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123
diff
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|
2026 dst = jmp_r(dst, SCRATCH1); |
76
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Implement JSR for some addressing modes
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74
diff
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|
2027 } |
71
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70
diff
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|
2028 break; |
132
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129
diff
changeset
|
2029 case MODE_PC_INDEX_DISP8: |
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129
diff
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|
2030 dst = cycles(dst, BUS*3);//TODO: CHeck that this is correct |
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129
diff
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|
2031 dst = mov_ir(dst, inst->address+2, SCRATCH1, SZ_D); |
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129
diff
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|
2032 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7; |
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129
diff
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|
2033 if (inst->src.params.regs.sec & 1) { |
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129
diff
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|
2034 if (inst->src.params.regs.sec & 0x10) { |
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129
diff
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|
2035 if (opts->aregs[sec_reg] >= 0) { |
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129
diff
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|
2036 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D); |
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129
diff
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|
2037 } else { |
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129
diff
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|
2038 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
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129
diff
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|
2039 } |
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129
diff
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|
2040 } else { |
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129
diff
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|
2041 if (opts->dregs[sec_reg] >= 0) { |
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129
diff
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|
2042 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_D); |
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129
diff
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|
2043 } else { |
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129
diff
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|
2044 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
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129
diff
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|
2045 } |
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129
diff
changeset
|
2046 } |
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129
diff
changeset
|
2047 } else { |
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129
diff
changeset
|
2048 if (inst->src.params.regs.sec & 0x10) { |
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129
diff
changeset
|
2049 if (opts->aregs[sec_reg] >= 0) { |
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129
diff
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|
2050 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
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Mike Pavone <pavone@retrodev.com>
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129
diff
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|
2051 } else { |
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129
diff
changeset
|
2052 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
0969d8363a20
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129
diff
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|
2053 } |
0969d8363a20
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parents:
129
diff
changeset
|
2054 } else { |
0969d8363a20
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129
diff
changeset
|
2055 if (opts->dregs[sec_reg] >= 0) { |
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129
diff
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|
2056 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
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Mike Pavone <pavone@retrodev.com>
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129
diff
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|
2057 } else { |
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129
diff
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|
2058 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
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129
diff
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|
2059 } |
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129
diff
changeset
|
2060 } |
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129
diff
changeset
|
2061 dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D); |
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129
diff
changeset
|
2062 } |
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Mike Pavone <pavone@retrodev.com>
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129
diff
changeset
|
2063 if (inst->src.params.regs.displacement) { |
0969d8363a20
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Mike Pavone <pavone@retrodev.com>
parents:
129
diff
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|
2064 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D); |
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Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2065 } |
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Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2066 dst = call(dst, (uint8_t *)m68k_native_addr); |
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Mike Pavone <pavone@retrodev.com>
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129
diff
changeset
|
2067 dst = jmp_r(dst, SCRATCH1); |
0969d8363a20
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Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2068 break; |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
2069 case MODE_ABSOLUTE: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
2070 case MODE_ABSOLUTE_SHORT: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
2071 dst = cycles(dst, inst->src.addr_mode == MODE_ABSOLUTE ? 12 : 10); |
124
da95566514f3
Some fixes for translating code in located in RAM
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parents:
123
diff
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|
2072 m68k_addr = inst->src.params.immed; |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2073 if ((m68k_addr & 0xFFFFFF) < 0x400000) { |
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Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2074 dest_addr = get_native_address(opts->native_code_map, m68k_addr); |
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Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2075 if (!dest_addr) { |
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Some fixes for translating code in located in RAM
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parents:
123
diff
changeset
|
2076 opts->deferred = defer_address(opts->deferred, m68k_addr, dst + 1); |
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Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2077 //dummy address to be replaced later, make sure it generates a 4-byte displacement |
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Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2078 dest_addr = dst + 256; |
da95566514f3
Some fixes for translating code in located in RAM
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parents:
123
diff
changeset
|
2079 } |
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Some fixes for translating code in located in RAM
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123
diff
changeset
|
2080 dst = jmp(dst, dest_addr); |
da95566514f3
Some fixes for translating code in located in RAM
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parents:
123
diff
changeset
|
2081 } else { |
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123
diff
changeset
|
2082 dst = mov_ir(dst, m68k_addr, SCRATCH1, SZ_D); |
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Some fixes for translating code in located in RAM
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123
diff
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|
2083 dst = call(dst, (uint8_t *)m68k_native_addr); |
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123
diff
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|
2084 dst = jmp_r(dst, SCRATCH1); |
71
f80fa1776507
Implement more instructions and address modes
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parents:
70
diff
changeset
|
2085 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
2086 break; |
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2087 default: |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
2088 m68k_disasm(inst, disasm_buf); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
2089 printf("%s\naddress mode %d not yet supported (jmp)\n", disasm_buf, inst->src.addr_mode); |
104
a0fdaa134964
Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp
Mike Pavone <pavone@retrodev.com>
parents:
102
diff
changeset
|
2090 exit(1); |
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2091 } |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2092 return dst; |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2093 } |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2094 |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2095 uint8_t * translate_m68k_jsr(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2096 { |
110
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2097 uint8_t * dest_addr, sec_reg; |
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
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74
diff
changeset
|
2098 uint32_t after; |
124
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123
diff
changeset
|
2099 uint32_t m68k_addr; |
76
187c65f40a64
Implement JSR for some addressing modes
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74
diff
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|
2100 switch(inst->src.addr_mode) |
187c65f40a64
Implement JSR for some addressing modes
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parents:
74
diff
changeset
|
2101 { |
187c65f40a64
Implement JSR for some addressing modes
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parents:
74
diff
changeset
|
2102 case MODE_AREG_INDIRECT: |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2103 dst = cycles(dst, BUS*2); |
119
ee19ddadb398
Fix return address pushed to stack for jsr
Mike Pavone <pavone@retrodev.com>
parents:
118
diff
changeset
|
2104 dst = mov_ir(dst, inst->address + 2, SCRATCH1, SZ_D); |
155
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2105 if (opts->flags & OPT_NATIVE_CALL_STACK) { |
94a65fb4e1c7
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154
diff
changeset
|
2106 dst = push_r(dst, SCRATCH1); |
94a65fb4e1c7
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154
diff
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|
2107 } |
81
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
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parents:
78
diff
changeset
|
2108 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D); |
6d231dbe75ab
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Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
2109 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D); |
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Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
2110 dst = call(dst, (char *)m68k_write_long_highfirst); |
76
187c65f40a64
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74
diff
changeset
|
2111 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
187c65f40a64
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74
diff
changeset
|
2112 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
187c65f40a64
Implement JSR for some addressing modes
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74
diff
changeset
|
2113 } else { |
187c65f40a64
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74
diff
changeset
|
2114 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, SCRATCH1, SZ_D); |
187c65f40a64
Implement JSR for some addressing modes
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74
diff
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|
2115 } |
187c65f40a64
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74
diff
changeset
|
2116 dst = call(dst, (uint8_t *)m68k_native_addr); |
155
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154
diff
changeset
|
2117 if (opts->flags & OPT_NATIVE_CALL_STACK) { |
94a65fb4e1c7
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154
diff
changeset
|
2118 dst = call_r(dst, SCRATCH1); |
94a65fb4e1c7
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154
diff
changeset
|
2119 //would add_ir(dst, 8, RSP, SZ_Q) be faster here? |
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154
diff
changeset
|
2120 dst = pop_r(dst, SCRATCH1); |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
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154
diff
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|
2121 } else { |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2122 dst = jmp_r(dst, SCRATCH1); |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2123 } |
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2124 break; |
174
a1c3ecb4823f
Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents:
173
diff
changeset
|
2125 case MODE_AREG_DISPLACE: |
a1c3ecb4823f
Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents:
173
diff
changeset
|
2126 dst = cycles(dst, BUS*2); |
187
8e138da572ab
Fix return address for areg displacement mode JSR
Mike Pavone <pavone@retrodev.com>
parents:
184
diff
changeset
|
2127 dst = mov_ir(dst, inst->address + 4, SCRATCH1, SZ_D); |
174
a1c3ecb4823f
Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents:
173
diff
changeset
|
2128 if (opts->flags & OPT_NATIVE_CALL_STACK) { |
a1c3ecb4823f
Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents:
173
diff
changeset
|
2129 dst = push_r(dst, SCRATCH1); |
a1c3ecb4823f
Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents:
173
diff
changeset
|
2130 } |
a1c3ecb4823f
Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents:
173
diff
changeset
|
2131 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D); |
a1c3ecb4823f
Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents:
173
diff
changeset
|
2132 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D); |
a1c3ecb4823f
Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents:
173
diff
changeset
|
2133 dst = call(dst, (char *)m68k_write_long_highfirst); |
a1c3ecb4823f
Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents:
173
diff
changeset
|
2134 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
a1c3ecb4823f
Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents:
173
diff
changeset
|
2135 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
a1c3ecb4823f
Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents:
173
diff
changeset
|
2136 } else { |
a1c3ecb4823f
Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents:
173
diff
changeset
|
2137 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, SCRATCH1, SZ_D); |
a1c3ecb4823f
Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents:
173
diff
changeset
|
2138 } |
a1c3ecb4823f
Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents:
173
diff
changeset
|
2139 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D); |
a1c3ecb4823f
Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents:
173
diff
changeset
|
2140 dst = call(dst, (uint8_t *)m68k_native_addr); |
a1c3ecb4823f
Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents:
173
diff
changeset
|
2141 if (opts->flags & OPT_NATIVE_CALL_STACK) { |
a1c3ecb4823f
Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents:
173
diff
changeset
|
2142 dst = call_r(dst, SCRATCH1); |
a1c3ecb4823f
Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents:
173
diff
changeset
|
2143 //would add_ir(dst, 8, RSP, SZ_Q) be faster here? |
a1c3ecb4823f
Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents:
173
diff
changeset
|
2144 dst = pop_r(dst, SCRATCH1); |
a1c3ecb4823f
Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents:
173
diff
changeset
|
2145 } else { |
a1c3ecb4823f
Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents:
173
diff
changeset
|
2146 dst = jmp_r(dst, SCRATCH1); |
a1c3ecb4823f
Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents:
173
diff
changeset
|
2147 } |
a1c3ecb4823f
Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents:
173
diff
changeset
|
2148 break; |
110
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2149 case MODE_AREG_INDEX_DISP8: |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2150 dst = cycles(dst, BUS*3);//TODO: CHeck that this is correct |
119
ee19ddadb398
Fix return address pushed to stack for jsr
Mike Pavone <pavone@retrodev.com>
parents:
118
diff
changeset
|
2151 dst = mov_ir(dst, inst->address + 4, SCRATCH1, SZ_D); |
155
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2152 if (opts->flags & OPT_NATIVE_CALL_STACK) { |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2153 dst = push_r(dst, SCRATCH1); |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2154 } |
110
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2155 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2156 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2157 dst = call(dst, (char *)m68k_write_long_highfirst); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2158 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2159 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2160 } else { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2161 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2162 } |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2163 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7; |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2164 if (inst->src.params.regs.sec & 1) { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2165 if (inst->src.params.regs.sec & 0x10) { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2166 if (opts->aregs[sec_reg] >= 0) { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2167 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2168 } else { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2169 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2170 } |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2171 } else { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2172 if (opts->dregs[sec_reg] >= 0) { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2173 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2174 } else { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2175 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2176 } |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2177 } |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2178 } else { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2179 if (inst->src.params.regs.sec & 0x10) { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2180 if (opts->aregs[sec_reg] >= 0) { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2181 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2182 } else { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2183 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2184 } |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2185 } else { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2186 if (opts->dregs[sec_reg] >= 0) { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2187 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2188 } else { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2189 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2190 } |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2191 } |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2192 dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2193 } |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2194 if (inst->src.params.regs.displacement) { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2195 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2196 } |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2197 dst = call(dst, (uint8_t *)m68k_native_addr); |
155
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2198 if (opts->flags & OPT_NATIVE_CALL_STACK) { |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2199 dst = call_r(dst, SCRATCH1); |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2200 //would add_ir(dst, 8, RSP, SZ_Q) be faster here? |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2201 dst = pop_r(dst, SCRATCH1); |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2202 } else { |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2203 dst = jmp_r(dst, SCRATCH1); |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2204 } |
110
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2205 break; |
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2206 case MODE_PC_DISPLACE: |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2207 //TODO: Add cycles in the right place relative to pushing the return address on the stack |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2208 dst = cycles(dst, 10); |
119
ee19ddadb398
Fix return address pushed to stack for jsr
Mike Pavone <pavone@retrodev.com>
parents:
118
diff
changeset
|
2209 dst = mov_ir(dst, inst->address + 4, SCRATCH1, SZ_D); |
155
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2210 if (opts->flags & OPT_NATIVE_CALL_STACK) { |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2211 dst = push_r(dst, SCRATCH1); |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2212 } |
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2213 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D); |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2214 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D); |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2215 dst = call(dst, (char *)m68k_write_long_highfirst); |
124
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2216 m68k_addr = inst->src.params.regs.displacement + inst->address + 2; |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2217 if ((m68k_addr & 0xFFFFFF) < 0x400000) { |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2218 dest_addr = get_native_address(opts->native_code_map, m68k_addr); |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2219 if (!dest_addr) { |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2220 opts->deferred = defer_address(opts->deferred, m68k_addr, dst + 1); |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2221 //dummy address to be replaced later, make sure it generates a 4-byte displacement |
155
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2222 dest_addr = dst + 256; |
124
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2223 } |
155
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2224 if (opts->flags & OPT_NATIVE_CALL_STACK) { |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2225 dst = call(dst, (char *)dest_addr); |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2226 } else { |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2227 dst = jmp(dst, dest_addr); |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2228 } |
124
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2229 } else { |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2230 dst = mov_ir(dst, m68k_addr, SCRATCH1, SZ_D); |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2231 dst = call(dst, (uint8_t *)m68k_native_addr); |
155
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2232 if (opts->flags & OPT_NATIVE_CALL_STACK) { |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2233 dst = call_r(dst, SCRATCH1); |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2234 } else { |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2235 dst = jmp_r(dst, SCRATCH1); |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2236 } |
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2237 } |
155
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2238 if (opts->flags & OPT_NATIVE_CALL_STACK) { |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2239 //would add_ir(dst, 8, RSP, SZ_Q) be faster here? |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2240 dst = pop_r(dst, SCRATCH1); |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2241 } |
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2242 break; |
110
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2243 case MODE_PC_INDEX_DISP8: |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2244 dst = cycles(dst, BUS*3);//TODO: CHeck that this is correct |
119
ee19ddadb398
Fix return address pushed to stack for jsr
Mike Pavone <pavone@retrodev.com>
parents:
118
diff
changeset
|
2245 dst = mov_ir(dst, inst->address + 4, SCRATCH1, SZ_D); |
155
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2246 if (opts->flags & OPT_NATIVE_CALL_STACK) { |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2247 dst = push_r(dst, SCRATCH1); |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2248 } |
110
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2249 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2250 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2251 dst = call(dst, (char *)m68k_write_long_highfirst); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2252 dst = mov_ir(dst, inst->address+2, SCRATCH1, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2253 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7; |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2254 if (inst->src.params.regs.sec & 1) { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2255 if (inst->src.params.regs.sec & 0x10) { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2256 if (opts->aregs[sec_reg] >= 0) { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2257 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2258 } else { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2259 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2260 } |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2261 } else { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2262 if (opts->dregs[sec_reg] >= 0) { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2263 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2264 } else { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2265 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2266 } |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2267 } |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2268 } else { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2269 if (inst->src.params.regs.sec & 0x10) { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2270 if (opts->aregs[sec_reg] >= 0) { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2271 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2272 } else { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2273 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2274 } |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2275 } else { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2276 if (opts->dregs[sec_reg] >= 0) { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2277 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2278 } else { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2279 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2280 } |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2281 } |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2282 dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2283 } |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2284 if (inst->src.params.regs.displacement) { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2285 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2286 } |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2287 dst = call(dst, (uint8_t *)m68k_native_addr); |
155
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2288 if (opts->flags & OPT_NATIVE_CALL_STACK) { |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2289 dst = call_r(dst, SCRATCH1); |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2290 //would add_ir(dst, 8, RSP, SZ_Q) be faster here? |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2291 dst = pop_r(dst, SCRATCH1); |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2292 } else { |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2293 dst = jmp_r(dst, SCRATCH1); |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2294 } |
110
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2295 break; |
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2296 case MODE_ABSOLUTE: |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2297 case MODE_ABSOLUTE_SHORT: |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2298 //TODO: Add cycles in the right place relative to pushing the return address on the stack |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2299 dst = cycles(dst, inst->src.addr_mode == MODE_ABSOLUTE ? 12 : 10); |
119
ee19ddadb398
Fix return address pushed to stack for jsr
Mike Pavone <pavone@retrodev.com>
parents:
118
diff
changeset
|
2300 dst = mov_ir(dst, inst->address + (inst->src.addr_mode == MODE_ABSOLUTE ? 6 : 4), SCRATCH1, SZ_D); |
155
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2301 if (opts->flags & OPT_NATIVE_CALL_STACK) { |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2302 dst = push_r(dst, SCRATCH1); |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2303 } |
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2304 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D); |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2305 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D); |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2306 dst = call(dst, (char *)m68k_write_long_highfirst); |
124
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2307 m68k_addr = inst->src.params.immed; |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2308 if ((m68k_addr & 0xFFFFFF) < 0x400000) { |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2309 dest_addr = get_native_address(opts->native_code_map, m68k_addr); |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2310 if (!dest_addr) { |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2311 opts->deferred = defer_address(opts->deferred, m68k_addr, dst + 1); |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2312 //dummy address to be replaced later, make sure it generates a 4-byte displacement |
155
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2313 dest_addr = dst + 256; |
124
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2314 } |
155
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2315 if (opts->flags & OPT_NATIVE_CALL_STACK) { |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2316 dst = call(dst, (char *)dest_addr); |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2317 } else { |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2318 dst = jmp(dst, dest_addr); |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2319 } |
124
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2320 } else { |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2321 dst = mov_ir(dst, m68k_addr, SCRATCH1, SZ_D); |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2322 dst = call(dst, (uint8_t *)m68k_native_addr); |
155
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2323 if (opts->flags & OPT_NATIVE_CALL_STACK) { |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2324 dst = call_r(dst, SCRATCH1); |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2325 } else { |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2326 dst = jmp_r(dst, SCRATCH1); |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2327 } |
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2328 } |
155
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2329 if (opts->flags & OPT_NATIVE_CALL_STACK) { |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2330 //would add_ir(dst, 8, RSP, SZ_Q) be faster here? |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2331 dst = pop_r(dst, SCRATCH1); |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2332 } |
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2333 break; |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2334 default: |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
2335 m68k_disasm(inst, disasm_buf); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
2336 printf("%s\naddress mode %d not yet supported (jsr)\n", disasm_buf, inst->src.addr_mode); |
105 | 2337 exit(1); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
2338 } |
53
44e661913a51
Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents:
52
diff
changeset
|
2339 return dst; |
44e661913a51
Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents:
52
diff
changeset
|
2340 } |
44e661913a51
Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents:
52
diff
changeset
|
2341 |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2342 uint8_t * translate_m68k_rts(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2343 { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2344 //TODO: Add cycles |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2345 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2346 dst = add_ir(dst, 4, opts->aregs[7], SZ_D); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2347 dst = call(dst, (char *)m68k_read_long_scratch1); |
155
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2348 if (opts->flags & OPT_NATIVE_CALL_STACK) { |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2349 dst = cmp_rdisp8r(dst, RSP, 8, SCRATCH1, SZ_D); |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2350 dst = jcc(dst, CC_NZ, dst+3); |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2351 dst = retn(dst); |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2352 dst = jmp(dst, (char *)m68k_modified_ret_addr); |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2353 } else { |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2354 dst = call(dst, (uint8_t *)m68k_native_addr); |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2355 dst = jmp_r(dst, SCRATCH1); |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2356 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2357 return dst; |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2358 } |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2359 |
46
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2360 uint8_t * translate_m68k_dbcc(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2361 { |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2362 //best case duration |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2363 dst = cycles(dst, 10); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2364 uint8_t * skip_loc = NULL; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2365 //TODO: Check if COND_TRUE technically valid here even though |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2366 //it's basically a slow NOP |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2367 if (inst->extra.cond != COND_FALSE) { |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2368 uint8_t cond = CC_NZ; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2369 switch (inst->extra.cond) |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2370 { |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2371 case COND_HIGH: |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2372 cond = CC_Z; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2373 case COND_LOW_SAME: |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2374 dst = mov_rr(dst, FLAG_Z, SCRATCH1, SZ_B); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2375 dst = or_rr(dst, FLAG_C, SCRATCH1, SZ_B); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2376 break; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2377 case COND_CARRY_CLR: |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2378 cond = CC_Z; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2379 case COND_CARRY_SET: |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2380 dst = cmp_ir(dst, 0, FLAG_C, SZ_B); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2381 break; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2382 case COND_NOT_EQ: |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2383 cond = CC_Z; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2384 case COND_EQ: |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2385 dst = cmp_ir(dst, 0, FLAG_Z, SZ_B); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2386 break; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2387 case COND_OVERF_CLR: |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2388 cond = CC_Z; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2389 case COND_OVERF_SET: |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2390 dst = cmp_ir(dst, 0, FLAG_V, SZ_B); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2391 break; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2392 case COND_PLUS: |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2393 cond = CC_Z; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2394 case COND_MINUS: |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2395 dst = cmp_ir(dst, 0, FLAG_N, SZ_B); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2396 break; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2397 case COND_GREATER_EQ: |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2398 cond = CC_Z; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2399 case COND_LESS: |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2400 dst = cmp_rr(dst, FLAG_N, FLAG_V, SZ_B); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2401 break; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2402 case COND_GREATER: |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2403 cond = CC_Z; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2404 case COND_LESS_EQ: |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2405 dst = mov_rr(dst, FLAG_V, SCRATCH1, SZ_B); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2406 dst = xor_rr(dst, FLAG_N, SCRATCH1, SZ_B); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2407 dst = or_rr(dst, FLAG_Z, SCRATCH1, SZ_B); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2408 break; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2409 } |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2410 skip_loc = dst + 1; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2411 dst = jcc(dst, cond, dst + 2); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2412 } |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2413 if (opts->dregs[inst->dst.params.regs.pri] >= 0) { |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2414 dst = sub_ir(dst, 1, opts->dregs[inst->dst.params.regs.pri], SZ_W); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2415 dst = cmp_ir(dst, -1, opts->dregs[inst->dst.params.regs.pri], SZ_W); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2416 } else { |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2417 dst = sub_irdisp8(dst, 1, CONTEXT, offsetof(m68k_context, dregs) + 4 * inst->dst.params.regs.pri, SZ_W); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2418 dst = cmp_irdisp8(dst, -1, CONTEXT, offsetof(m68k_context, dregs) + 4 * inst->dst.params.regs.pri, SZ_W); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2419 } |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2420 uint8_t *loop_end_loc = dst+1; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2421 dst = jcc(dst, CC_Z, dst+2); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2422 uint32_t after = inst->address + 2; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2423 uint8_t * dest_addr = get_native_address(opts->native_code_map, after + inst->src.params.immed); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2424 if (!dest_addr) { |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2425 opts->deferred = defer_address(opts->deferred, after + inst->src.params.immed, dst + 1); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2426 //dummy address to be replaced later, make sure it generates a 4-byte displacement |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2427 dest_addr = dst + 256; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2428 } |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2429 dst = jmp(dst, dest_addr); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2430 *loop_end_loc = dst - (loop_end_loc+1); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2431 if (skip_loc) { |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2432 dst = cycles(dst, 2); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2433 *skip_loc = dst - (skip_loc+1); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2434 dst = cycles(dst, 2); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2435 } else { |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2436 dst = cycles(dst, 4); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2437 } |
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
2438 return dst; |
46
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2439 } |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2440 |
78
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2441 uint8_t * translate_m68k_link(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2442 { |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2443 int8_t reg = native_reg(&(inst->src), opts); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2444 //compensate for displacement word |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2445 dst = cycles(dst, BUS); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2446 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2447 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2448 if (reg >= 0) { |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2449 dst = mov_rr(dst, reg, SCRATCH1, SZ_D); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2450 } else { |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2451 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2452 } |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2453 dst = call(dst, (char *)m68k_write_long_highfirst); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2454 if (reg >= 0) { |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2455 dst = mov_rr(dst, opts->aregs[7], reg, SZ_D); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2456 } else { |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2457 dst = mov_rrdisp8(dst, opts->aregs[7], CONTEXT, reg_offset(&(inst->src)), SZ_D); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2458 } |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2459 dst = add_ir(dst, inst->dst.params.immed, opts->aregs[7], SZ_D); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2460 //prefetch |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2461 dst = cycles(dst, BUS); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2462 return dst; |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2463 } |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2464 |
172 | 2465 uint8_t * translate_m68k_movep(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
2466 { | |
2467 int8_t reg; | |
2468 dst = cycles(dst, BUS*2); | |
2469 if (inst->src.addr_mode == MODE_REG) { | |
2470 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { | |
2471 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D); | |
2472 } else { | |
2473 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D); | |
2474 } | |
2475 if (inst->dst.params.regs.displacement) { | |
2476 dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH2, SZ_D); | |
2477 } | |
2478 reg = native_reg(&(inst->src), opts); | |
2479 if (inst->extra.size == OPSIZE_LONG) { | |
2480 if (reg >= 0) { | |
2481 dst = mov_rr(dst, reg, SCRATCH1, SZ_D); | |
2482 dst = shr_ir(dst, 24, SCRATCH1, SZ_D); | |
2483 dst = push_r(dst, SCRATCH2); | |
2484 dst = call(dst, (uint8_t *)m68k_write_byte); | |
2485 dst = pop_r(dst, SCRATCH2); | |
2486 dst = mov_rr(dst, reg, SCRATCH1, SZ_D); | |
2487 dst = shr_ir(dst, 16, SCRATCH1, SZ_D); | |
2488 | |
2489 } else { | |
2490 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src))+3, SCRATCH1, SZ_B); | |
2491 dst = push_r(dst, SCRATCH2); | |
2492 dst = call(dst, (uint8_t *)m68k_write_byte); | |
2493 dst = pop_r(dst, SCRATCH2); | |
2494 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src))+2, SCRATCH1, SZ_B); | |
2495 } | |
2496 dst = add_ir(dst, 2, SCRATCH2, SZ_D); | |
2497 dst = push_r(dst, SCRATCH2); | |
2498 dst = call(dst, (uint8_t *)m68k_write_byte); | |
2499 dst = pop_r(dst, SCRATCH2); | |
2500 dst = add_ir(dst, 2, SCRATCH2, SZ_D); | |
2501 } | |
2502 if (reg >= 0) { | |
2503 dst = mov_rr(dst, reg, SCRATCH1, SZ_W); | |
2504 dst = shr_ir(dst, 8, SCRATCH1, SZ_W); | |
2505 dst = push_r(dst, SCRATCH2); | |
2506 dst = call(dst, (uint8_t *)m68k_write_byte); | |
2507 dst = pop_r(dst, SCRATCH2); | |
2508 dst = mov_rr(dst, reg, SCRATCH1, SZ_W); | |
2509 } else { | |
2510 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src))+1, SCRATCH1, SZ_B); | |
2511 dst = push_r(dst, SCRATCH2); | |
2512 dst = call(dst, (uint8_t *)m68k_write_byte); | |
2513 dst = pop_r(dst, SCRATCH2); | |
2514 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_B); | |
2515 } | |
2516 dst = add_ir(dst, 2, SCRATCH2, SZ_D); | |
2517 dst = call(dst, (uint8_t *)m68k_write_byte); | |
2518 } else { | |
2519 if (opts->aregs[inst->src.params.regs.pri] >= 0) { | |
2520 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); | |
2521 } else { | |
2522 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); | |
2523 } | |
2524 if (inst->src.params.regs.displacement) { | |
2525 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D); | |
2526 } | |
2527 reg = native_reg(&(inst->dst), opts); | |
2528 if (inst->extra.size == OPSIZE_LONG) { | |
2529 if (reg >= 0) { | |
2530 dst = push_r(dst, SCRATCH1); | |
2531 dst = call(dst, (uint8_t *)m68k_read_byte_scratch1); | |
2532 dst = shl_ir(dst, 24, SCRATCH1, SZ_D); | |
2533 dst = mov_rr(dst, SCRATCH1, reg, SZ_D); | |
2534 dst = pop_r(dst, SCRATCH1); | |
2535 dst = add_ir(dst, 2, SCRATCH1, SZ_D); | |
2536 dst = push_r(dst, SCRATCH1); | |
2537 dst = call(dst, (uint8_t *)m68k_read_byte_scratch1); | |
2538 dst = shl_ir(dst, 16, SCRATCH1, SZ_D); | |
2539 dst = or_rr(dst, SCRATCH1, reg, SZ_D); | |
2540 } else { | |
2541 dst = push_r(dst, SCRATCH1); | |
2542 dst = call(dst, (uint8_t *)m68k_read_byte_scratch1); | |
2543 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, reg_offset(&(inst->dst))+3, SZ_B); | |
2544 dst = pop_r(dst, SCRATCH1); | |
2545 dst = add_ir(dst, 2, SCRATCH1, SZ_D); | |
2546 dst = push_r(dst, SCRATCH1); | |
2547 dst = call(dst, (uint8_t *)m68k_read_byte_scratch1); | |
2548 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, reg_offset(&(inst->dst))+2, SZ_B); | |
2549 } | |
2550 dst = pop_r(dst, SCRATCH1); | |
2551 dst = add_ir(dst, 2, SCRATCH1, SZ_D); | |
2552 } | |
2553 dst = push_r(dst, SCRATCH1); | |
2554 dst = call(dst, (uint8_t *)m68k_read_byte_scratch1); | |
2555 if (reg >= 0) { | |
2556 | |
2557 dst = shl_ir(dst, 8, SCRATCH1, SZ_W); | |
2558 dst = mov_rr(dst, SCRATCH1, reg, SZ_W); | |
2559 dst = pop_r(dst, SCRATCH1); | |
2560 dst = add_ir(dst, 2, SCRATCH1, SZ_D); | |
2561 dst = call(dst, (uint8_t *)m68k_read_byte_scratch1); | |
2562 dst = mov_rr(dst, SCRATCH1, reg, SZ_B); | |
2563 } else { | |
2564 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, reg_offset(&(inst->dst))+1, SZ_B); | |
2565 dst = pop_r(dst, SCRATCH1); | |
2566 dst = add_ir(dst, 2, SCRATCH1, SZ_D); | |
2567 dst = call(dst, (uint8_t *)m68k_read_byte_scratch1); | |
2568 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, reg_offset(&(inst->dst)), SZ_B); | |
2569 } | |
2570 } | |
2571 return dst; | |
2572 } | |
2573 | |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2574 uint8_t * translate_m68k_cmp(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2575 { |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2576 uint8_t size = inst->extra.size; |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2577 x86_ea src_op, dst_op; |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2578 dst = translate_m68k_src(inst, &src_op, dst, opts); |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2579 if (inst->dst.addr_mode == MODE_AREG_POSTINC) { |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2580 dst = push_r(dst, SCRATCH1); |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2581 dst = translate_m68k_dst(inst, &dst_op, dst, opts, 0); |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2582 dst = pop_r(dst, SCRATCH2); |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2583 src_op.base = SCRATCH2; |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2584 } else { |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2585 dst = translate_m68k_dst(inst, &dst_op, dst, opts, 0); |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2586 if (inst->dst.addr_mode == MODE_AREG && size == OPSIZE_WORD) { |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2587 size = OPSIZE_LONG; |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2588 } |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2589 } |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2590 dst = cycles(dst, BUS); |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2591 if (src_op.mode == MODE_REG_DIRECT) { |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2592 if (dst_op.mode == MODE_REG_DIRECT) { |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2593 dst = cmp_rr(dst, src_op.base, dst_op.base, size); |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2594 } else { |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2595 dst = cmp_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, size); |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2596 } |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2597 } else if (src_op.mode == MODE_REG_DISPLACE8) { |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2598 dst = cmp_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, size); |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2599 } else { |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2600 if (dst_op.mode == MODE_REG_DIRECT) { |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2601 dst = cmp_ir(dst, src_op.disp, dst_op.base, size); |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2602 } else { |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2603 dst = cmp_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, size); |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2604 } |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2605 } |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2606 dst = setcc_r(dst, CC_C, FLAG_C); |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2607 dst = setcc_r(dst, CC_Z, FLAG_Z); |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2608 dst = setcc_r(dst, CC_S, FLAG_N); |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2609 dst = setcc_r(dst, CC_O, FLAG_V); |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2610 return dst; |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2611 } |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2612 |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2613 typedef uint8_t * (*shift_ir_t)(uint8_t * out, uint8_t val, uint8_t dst, uint8_t size); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2614 typedef uint8_t * (*shift_irdisp8_t)(uint8_t * out, uint8_t val, uint8_t dst_base, int8_t disp, uint8_t size); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2615 typedef uint8_t * (*shift_clr_t)(uint8_t * out, uint8_t dst, uint8_t size); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2616 typedef uint8_t * (*shift_clrdisp8_t)(uint8_t * out, uint8_t dst_base, int8_t disp, uint8_t size); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2617 |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2618 uint8_t * translate_shift(uint8_t * dst, m68kinst * inst, x86_ea *src_op, x86_ea * dst_op, x86_68k_options * opts, shift_ir_t shift_ir, shift_irdisp8_t shift_irdisp8, shift_clr_t shift_clr, shift_clrdisp8_t shift_clrdisp8, shift_ir_t special, shift_irdisp8_t special_disp8) |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2619 { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2620 uint8_t * end_off = NULL; |
207 | 2621 uint8_t * nz_off = NULL; |
2622 uint8_t * z_off = NULL; | |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2623 if (inst->src.addr_mode == MODE_UNUSED) { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2624 dst = cycles(dst, BUS); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2625 //Memory shift |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2626 dst = shift_ir(dst, 1, dst_op->base, SZ_W); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2627 } else { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2628 dst = cycles(dst, inst->extra.size == OPSIZE_LONG ? 8 : 6); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2629 if (src_op->mode == MODE_IMMED) { |
207 | 2630 if (src_op->disp != 1 && inst->op == M68K_ASL) { |
2631 dst = mov_ir(dst, 0, FLAG_V, SZ_B); | |
2632 for (int i = 0; i < src_op->disp; i++) { | |
2633 if (dst_op->mode == MODE_REG_DIRECT) { | |
2634 dst = shift_ir(dst, 1, dst_op->base, inst->extra.size); | |
2635 } else { | |
2636 dst = shift_irdisp8(dst, 1, dst_op->base, dst_op->disp, inst->extra.size); | |
2637 } | |
2638 //dst = setcc_r(dst, CC_O, FLAG_V); | |
2639 dst = jcc(dst, CC_NO, dst+4); | |
2640 dst = mov_ir(dst, 1, FLAG_V, SZ_B); | |
2641 } | |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2642 } else { |
207 | 2643 if (dst_op->mode == MODE_REG_DIRECT) { |
2644 dst = shift_ir(dst, src_op->disp, dst_op->base, inst->extra.size); | |
2645 } else { | |
2646 dst = shift_irdisp8(dst, src_op->disp, dst_op->base, dst_op->disp, inst->extra.size); | |
2647 } | |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
211
diff
changeset
|
2648 dst = setcc_r(dst, CC_O, FLAG_V); |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2649 } |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2650 } else { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2651 if (src_op->base != RCX) { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2652 if (src_op->mode == MODE_REG_DIRECT) { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2653 dst = mov_rr(dst, src_op->base, RCX, SZ_B); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2654 } else { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2655 dst = mov_rdisp8r(dst, src_op->base, src_op->disp, RCX, SZ_B); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2656 } |
207 | 2657 |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2658 } |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2659 dst = and_ir(dst, 63, RCX, SZ_D); |
207 | 2660 nz_off = dst+1; |
2661 dst = jcc(dst, CC_NZ, dst+2); | |
2662 //Flag behavior for shift count of 0 is different for x86 than 68K | |
2663 if (dst_op->mode == MODE_REG_DIRECT) { | |
2664 dst = cmp_ir(dst, 0, dst_op->base, inst->extra.size); | |
2665 } else { | |
2666 dst = cmp_irdisp8(dst, 0, dst_op->base, dst_op->disp, inst->extra.size); | |
2667 } | |
2668 dst = setcc_r(dst, CC_Z, FLAG_Z); | |
2669 dst = setcc_r(dst, CC_S, FLAG_N); | |
2670 dst = mov_ir(dst, 0, FLAG_C, SZ_B); | |
2671 //For other instructions, this flag will be set below | |
2672 if (inst->op == M68K_ASL) { | |
2673 dst = mov_ir(dst, 0, FLAG_V, SZ_B); | |
2674 } | |
2675 z_off = dst+1; | |
2676 dst = jmp(dst, dst+2); | |
2677 *nz_off = dst - (nz_off + 1); | |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2678 //add 2 cycles for every bit shifted |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2679 dst = add_rr(dst, RCX, CYCLES, SZ_D); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2680 dst = add_rr(dst, RCX, CYCLES, SZ_D); |
207 | 2681 if (inst->op == M68K_ASL) { |
2682 //ASL has Overflow flag behavior that depends on all of the bits shifted through the MSB | |
2683 //Easiest way to deal with this is to shift one bit at a time | |
2684 dst = mov_ir(dst, 0, FLAG_V, SZ_B); | |
2685 uint8_t * loop_start = dst; | |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2686 if (dst_op->mode == MODE_REG_DIRECT) { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2687 dst = shift_ir(dst, 1, dst_op->base, inst->extra.size); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2688 } else { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2689 dst = shift_irdisp8(dst, 1, dst_op->base, dst_op->disp, inst->extra.size); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2690 } |
207 | 2691 //dst = setcc_r(dst, CC_O, FLAG_V); |
2692 dst = jcc(dst, CC_NO, dst+4); | |
2693 dst = mov_ir(dst, 1, FLAG_V, SZ_B); | |
2694 dst = loop(dst, loop_start); | |
2695 } else { | |
2696 //x86 shifts modulo 32 for operand sizes less than 64-bits | |
2697 //but M68K shifts modulo 64, so we need to check for large shifts here | |
2698 dst = cmp_ir(dst, 32, RCX, SZ_B); | |
2699 uint8_t * norm_shift_off = dst + 1; | |
2700 dst = jcc(dst, CC_L, dst+2); | |
2701 if (special) { | |
2702 if (inst->extra.size == OPSIZE_LONG) { | |
2703 uint8_t * neq_32_off = dst + 1; | |
2704 dst = jcc(dst, CC_NZ, dst+2); | |
2705 | |
2706 //set the carry bit to the lsb | |
2707 if (dst_op->mode == MODE_REG_DIRECT) { | |
2708 dst = special(dst, 1, dst_op->base, SZ_D); | |
2709 } else { | |
2710 dst = special_disp8(dst, 1, dst_op->base, dst_op->disp, SZ_D); | |
2711 } | |
2712 dst = setcc_r(dst, CC_C, FLAG_C); | |
2713 dst = jmp(dst, dst+4); | |
2714 *neq_32_off = dst - (neq_32_off+1); | |
2715 } | |
2716 dst = mov_ir(dst, 0, FLAG_C, SZ_B); | |
2717 dst = mov_ir(dst, 1, FLAG_Z, SZ_B); | |
2718 dst = mov_ir(dst, 0, FLAG_N, SZ_B); | |
2719 if (dst_op->mode == MODE_REG_DIRECT) { | |
2720 dst = xor_rr(dst, dst_op->base, dst_op->base, inst->extra.size); | |
2721 } else { | |
2722 dst = mov_irdisp8(dst, 0, dst_op->base, dst_op->disp, inst->extra.size); | |
2723 } | |
2724 } else { | |
2725 if (dst_op->mode == MODE_REG_DIRECT) { | |
2726 dst = shift_ir(dst, 31, dst_op->base, inst->extra.size); | |
2727 dst = shift_ir(dst, 1, dst_op->base, inst->extra.size); | |
2728 } else { | |
2729 dst = shift_irdisp8(dst, 31, dst_op->base, dst_op->disp, inst->extra.size); | |
2730 dst = shift_irdisp8(dst, 1, dst_op->base, dst_op->disp, inst->extra.size); | |
2731 } | |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2732 |
207 | 2733 } |
2734 end_off = dst+1; | |
2735 dst = jmp(dst, dst+2); | |
2736 *norm_shift_off = dst - (norm_shift_off+1); | |
2737 if (dst_op->mode == MODE_REG_DIRECT) { | |
2738 dst = shift_clr(dst, dst_op->base, inst->extra.size); | |
2739 } else { | |
2740 dst = shift_clrdisp8(dst, dst_op->base, dst_op->disp, inst->extra.size); | |
2741 } | |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2742 } |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2743 } |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2744 |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2745 } |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2746 if (!special && end_off) { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2747 *end_off = dst - (end_off + 1); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2748 } |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2749 dst = setcc_r(dst, CC_C, FLAG_C); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2750 dst = setcc_r(dst, CC_Z, FLAG_Z); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2751 dst = setcc_r(dst, CC_S, FLAG_N); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2752 if (special && end_off) { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2753 *end_off = dst - (end_off + 1); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2754 } |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2755 //set X flag to same as C flag |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2756 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B); |
207 | 2757 if (z_off) { |
2758 *z_off = dst - (z_off + 1); | |
2759 } | |
219
8d3c16071559
Fix overflow flag behavior for lsl/lsr/asr
Mike Pavone <pavone@retrodev.com>
parents:
218
diff
changeset
|
2760 if (inst->op != M68K_ASL) { |
207 | 2761 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
2762 } | |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2763 if (inst->src.addr_mode == MODE_UNUSED) { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2764 dst = m68k_save_result(inst, dst, opts); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2765 } |
66 | 2766 return dst; |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2767 } |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2768 |
73
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2769 #define BIT_SUPERVISOR 5 |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2770 |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2771 uint8_t * translate_m68k(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2772 { |
122 | 2773 uint8_t * end_off, *zero_off, *norm_off; |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
2774 uint8_t dst_reg; |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
2775 dst = check_cycles_int(dst, inst->address); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2776 if (inst->op == M68K_MOVE) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2777 return translate_m68k_move(dst, inst, opts); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2778 } else if(inst->op == M68K_LEA) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2779 return translate_m68k_lea(dst, inst, opts); |
116
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
2780 } else if(inst->op == M68K_PEA) { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
2781 return translate_m68k_pea(dst, inst, opts); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2782 } else if(inst->op == M68K_BSR) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2783 return translate_m68k_bsr(dst, inst, opts); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2784 } else if(inst->op == M68K_BCC) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2785 return translate_m68k_bcc(dst, inst, opts); |
53
44e661913a51
Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents:
52
diff
changeset
|
2786 } else if(inst->op == M68K_JMP) { |
44e661913a51
Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents:
52
diff
changeset
|
2787 return translate_m68k_jmp(dst, inst, opts); |
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2788 } else if(inst->op == M68K_JSR) { |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2789 return translate_m68k_jsr(dst, inst, opts); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2790 } else if(inst->op == M68K_RTS) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2791 return translate_m68k_rts(dst, inst, opts); |
46
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2792 } else if(inst->op == M68K_DBCC) { |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2793 return translate_m68k_dbcc(dst, inst, opts); |
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
2794 } else if(inst->op == M68K_CLR) { |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
2795 return translate_m68k_clr(dst, inst, opts); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
2796 } else if(inst->op == M68K_MOVEM) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
2797 return translate_m68k_movem(dst, inst, opts); |
78
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2798 } else if(inst->op == M68K_LINK) { |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2799 return translate_m68k_link(dst, inst, opts); |
93
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
2800 } else if(inst->op == M68K_EXT) { |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
2801 return translate_m68k_ext(dst, inst, opts); |
112 | 2802 } else if(inst->op == M68K_SCC) { |
2803 return translate_m68k_scc(dst, inst, opts); | |
172 | 2804 } else if(inst->op == M68K_MOVEP) { |
2805 return translate_m68k_movep(dst, inst, opts); | |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
175
diff
changeset
|
2806 } else if(inst->op == M68K_INVALID) { |
208
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
207
diff
changeset
|
2807 if (inst->src.params.immed == 0x7100) { |
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
207
diff
changeset
|
2808 return retn(dst); |
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
207
diff
changeset
|
2809 } |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
175
diff
changeset
|
2810 dst = mov_ir(dst, inst->address, SCRATCH1, SZ_D); |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
175
diff
changeset
|
2811 return call(dst, (uint8_t *)m68k_invalid); |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2812 } else if(inst->op == M68K_CMP) { |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2813 return translate_m68k_cmp(dst, inst, opts); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2814 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2815 x86_ea src_op, dst_op; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2816 if (inst->src.addr_mode != MODE_UNUSED) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2817 dst = translate_m68k_src(inst, &src_op, dst, opts); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2818 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2819 if (inst->dst.addr_mode != MODE_UNUSED) { |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
2820 dst = translate_m68k_dst(inst, &dst_op, dst, opts, 0); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2821 } |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2822 uint8_t size; |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2823 switch(inst->op) |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2824 { |
194
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2825 case M68K_ABCD: |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2826 if (src_op.base != SCRATCH2) { |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2827 if (src_op.mode == MODE_REG_DIRECT) { |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2828 dst = mov_rr(dst, src_op.base, SCRATCH2, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2829 } else { |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2830 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH2, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2831 } |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2832 } |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2833 if (dst_op.base != SCRATCH1) { |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2834 if (dst_op.mode == MODE_REG_DIRECT) { |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2835 dst = mov_rr(dst, dst_op.base, SCRATCH1, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2836 } else { |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2837 dst = mov_rdisp8r(dst, dst_op.base, dst_op.disp, SCRATCH1, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2838 } |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2839 } |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2840 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2841 dst = jcc(dst, CC_NC, dst+5); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2842 dst = add_ir(dst, 1, SCRATCH1, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2843 dst = call(dst, (uint8_t *)bcd_add); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2844 dst = mov_rr(dst, CH, FLAG_C, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2845 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2846 dst = cmp_ir(dst, 0, SCRATCH1, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2847 dst = jcc(dst, CC_Z, dst+4); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2848 dst = mov_ir(dst, 0, FLAG_Z, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2849 if (dst_op.base != SCRATCH1) { |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2850 if (dst_op.mode == MODE_REG_DIRECT) { |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2851 dst = mov_rr(dst, SCRATCH1, dst_op.base, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2852 } else { |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2853 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2854 } |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2855 } |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2856 dst = m68k_save_result(inst, dst, opts); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2857 break; |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2858 case M68K_ADD: |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2859 dst = cycles(dst, BUS); |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2860 size = inst->dst.addr_mode == MODE_AREG ? OPSIZE_LONG : inst->extra.size; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2861 if (src_op.mode == MODE_REG_DIRECT) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2862 if (dst_op.mode == MODE_REG_DIRECT) { |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2863 dst = add_rr(dst, src_op.base, dst_op.base, size); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2864 } else { |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2865 dst = add_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, size); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2866 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2867 } else if (src_op.mode == MODE_REG_DISPLACE8) { |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2868 dst = add_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, size); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2869 } else { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2870 if (dst_op.mode == MODE_REG_DIRECT) { |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2871 dst = add_ir(dst, src_op.disp, dst_op.base, size); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2872 } else { |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2873 dst = add_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, size); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2874 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2875 } |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
2876 if (inst->dst.addr_mode != MODE_AREG) { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
2877 dst = setcc_r(dst, CC_C, FLAG_C); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
2878 dst = setcc_r(dst, CC_Z, FLAG_Z); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
2879 dst = setcc_r(dst, CC_S, FLAG_N); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
2880 dst = setcc_r(dst, CC_O, FLAG_V); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
2881 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
2882 } |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2883 dst = m68k_save_result(inst, dst, opts); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2884 break; |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2885 case M68K_ADDX: |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2886 dst = cycles(dst, BUS); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2887 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2888 if (src_op.mode == MODE_REG_DIRECT) { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2889 if (dst_op.mode == MODE_REG_DIRECT) { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2890 dst = adc_rr(dst, src_op.base, dst_op.base, inst->extra.size); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2891 } else { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2892 dst = adc_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2893 } |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2894 } else if (src_op.mode == MODE_REG_DISPLACE8) { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2895 dst = adc_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2896 } else { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2897 if (dst_op.mode == MODE_REG_DIRECT) { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2898 dst = adc_ir(dst, src_op.disp, dst_op.base, inst->extra.size); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2899 } else { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2900 dst = adc_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2901 } |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2902 } |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2903 dst = setcc_r(dst, CC_C, FLAG_C); |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
2904 dst = jcc(dst, CC_Z, dst+4); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
2905 dst = mov_ir(dst, 0, FLAG_Z, SZ_B); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2906 dst = setcc_r(dst, CC_S, FLAG_N); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2907 dst = setcc_r(dst, CC_O, FLAG_V); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2908 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2909 dst = m68k_save_result(inst, dst, opts); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2910 break; |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2911 case M68K_AND: |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2912 dst = cycles(dst, BUS); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2913 if (src_op.mode == MODE_REG_DIRECT) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2914 if (dst_op.mode == MODE_REG_DIRECT) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2915 dst = and_rr(dst, src_op.base, dst_op.base, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2916 } else { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2917 dst = and_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2918 } |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2919 } else if (src_op.mode == MODE_REG_DISPLACE8) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2920 dst = and_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2921 } else { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2922 if (dst_op.mode == MODE_REG_DIRECT) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2923 dst = and_ir(dst, src_op.disp, dst_op.base, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2924 } else { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2925 dst = and_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2926 } |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2927 } |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2928 dst = mov_ir(dst, 0, FLAG_C, SZ_B); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2929 dst = setcc_r(dst, CC_Z, FLAG_Z); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2930 dst = setcc_r(dst, CC_S, FLAG_N); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2931 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2932 dst = m68k_save_result(inst, dst, opts); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2933 break; |
73
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2934 case M68K_ANDI_CCR: |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2935 case M68K_ANDI_SR: |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2936 dst = cycles(dst, 20); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2937 //TODO: If ANDI to SR, trap if not in supervisor mode |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2938 if (!(inst->src.params.immed & 0x1)) { |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2939 dst = mov_ir(dst, 0, FLAG_C, SZ_B); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2940 } |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2941 if (!(inst->src.params.immed & 0x2)) { |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2942 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2943 } |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2944 if (!(inst->src.params.immed & 0x4)) { |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2945 dst = mov_ir(dst, 0, FLAG_Z, SZ_B); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2946 } |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2947 if (!(inst->src.params.immed & 0x8)) { |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2948 dst = mov_ir(dst, 0, FLAG_N, SZ_B); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2949 } |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2950 if (!(inst->src.params.immed & 0x10)) { |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2951 dst = mov_irind(dst, 0, CONTEXT, SZ_B); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2952 } |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2953 if (inst->op == M68K_ANDI_SR) { |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2954 dst = and_irdisp8(dst, inst->src.params.immed >> 8, CONTEXT, offsetof(m68k_context, status), SZ_B); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2955 if (!((inst->src.params.immed >> 8) & (1 << BIT_SUPERVISOR))) { |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2956 //leave supervisor mode |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2957 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_B); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2958 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, opts->aregs[7], SZ_B); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2959 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_B); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2960 } |
150
3e68e517cc01
Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed.
Mike Pavone <pavone@retrodev.com>
parents:
146
diff
changeset
|
2961 if (inst->src.params.immed & 0x700) { |
3e68e517cc01
Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed.
Mike Pavone <pavone@retrodev.com>
parents:
146
diff
changeset
|
2962 dst = call(dst, (uint8_t *)do_sync); |
3e68e517cc01
Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed.
Mike Pavone <pavone@retrodev.com>
parents:
146
diff
changeset
|
2963 } |
73
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2964 } |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2965 break; |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2966 case M68K_ASL: |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2967 case M68K_LSL: |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2968 dst = translate_shift(dst, inst, &src_op, &dst_op, opts, shl_ir, shl_irdisp8, shl_clr, shl_clrdisp8, shr_ir, shr_irdisp8); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2969 break; |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2970 case M68K_ASR: |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2971 dst = translate_shift(dst, inst, &src_op, &dst_op, opts, sar_ir, sar_irdisp8, sar_clr, sar_clrdisp8, NULL, NULL); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2972 break; |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2973 case M68K_LSR: |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2974 dst = translate_shift(dst, inst, &src_op, &dst_op, opts, shr_ir, shr_irdisp8, shr_clr, shr_clrdisp8, shl_ir, shl_irdisp8); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2975 break; |
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2976 case M68K_BCHG: |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2977 case M68K_BCLR: |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2978 case M68K_BSET: |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2979 case M68K_BTST: |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
2980 dst = cycles(dst, inst->extra.size == OPSIZE_BYTE ? 4 : 6); |
67 | 2981 if (src_op.mode == MODE_IMMED) { |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
2982 if (inst->extra.size == OPSIZE_BYTE) { |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
2983 src_op.disp &= 0x7; |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
2984 } |
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2985 if (inst->op == M68K_BTST) { |
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2986 if (dst_op.mode == MODE_REG_DIRECT) { |
128
fe598ffd85ce
Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents:
126
diff
changeset
|
2987 dst = bt_ir(dst, src_op.disp, dst_op.base, inst->extra.size); |
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2988 } else { |
128
fe598ffd85ce
Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents:
126
diff
changeset
|
2989 dst = bt_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); |
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2990 } |
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2991 } else if (inst->op == M68K_BSET) { |
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2992 if (dst_op.mode == MODE_REG_DIRECT) { |
128
fe598ffd85ce
Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents:
126
diff
changeset
|
2993 dst = bts_ir(dst, src_op.disp, dst_op.base, inst->extra.size); |
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2994 } else { |
128
fe598ffd85ce
Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents:
126
diff
changeset
|
2995 dst = bts_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); |
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2996 } |
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2997 } else if (inst->op == M68K_BCLR) { |
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2998 if (dst_op.mode == MODE_REG_DIRECT) { |
128
fe598ffd85ce
Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents:
126
diff
changeset
|
2999 dst = btr_ir(dst, src_op.disp, dst_op.base, inst->extra.size); |
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
3000 } else { |
128
fe598ffd85ce
Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents:
126
diff
changeset
|
3001 dst = btr_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); |
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
3002 } |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
3003 } else { |
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
3004 if (dst_op.mode == MODE_REG_DIRECT) { |
128
fe598ffd85ce
Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents:
126
diff
changeset
|
3005 dst = btc_ir(dst, src_op.disp, dst_op.base, inst->extra.size); |
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
3006 } else { |
128
fe598ffd85ce
Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents:
126
diff
changeset
|
3007 dst = btc_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); |
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
3008 } |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
3009 } |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
3010 } else { |
221
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
3011 if (src_op.mode == MODE_REG_DISPLACE8 || (inst->dst.addr_mode != MODE_REG && src_op.base != SCRATCH1 && src_op.base != SCRATCH2)) { |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
3012 if (dst_op.base == SCRATCH1) { |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
3013 dst = push_r(dst, SCRATCH2); |
221
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
3014 if (src_op.mode == MODE_REG_DIRECT) { |
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
3015 dst = mov_rr(dst, src_op.base, SCRATCH2, SZ_B); |
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
3016 } else { |
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
3017 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH2, SZ_B); |
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
3018 } |
128
fe598ffd85ce
Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents:
126
diff
changeset
|
3019 src_op.base = SCRATCH2; |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
3020 } else { |
221
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
3021 if (src_op.mode == MODE_REG_DIRECT) { |
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
3022 dst = mov_rr(dst, src_op.base, SCRATCH1, SZ_B); |
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
3023 } else { |
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
3024 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_B); |
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
3025 } |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
3026 src_op.base = SCRATCH1; |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
3027 } |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
3028 } |
221
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
3029 uint8_t size = inst->extra.size; |
154
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
3030 if (dst_op.mode == MODE_REG_DISPLACE8) { |
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
3031 if (src_op.base != SCRATCH1 && src_op.base != SCRATCH2) { |
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
3032 if (src_op.mode == MODE_REG_DIRECT) { |
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
3033 dst = mov_rr(dst, src_op.base, SCRATCH1, SZ_D); |
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
3034 } else { |
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
3035 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_D); |
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
3036 src_op.mode = MODE_REG_DIRECT; |
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
3037 } |
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
3038 src_op.base = SCRATCH1; |
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
3039 } |
221
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
3040 //b### with register destination is modulo 32 |
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
3041 //x86 with a memory destination isn't modulo anything |
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
3042 //so use an and here to force the value to be modulo 32 |
154
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
3043 dst = and_ir(dst, 31, SCRATCH1, SZ_D); |
221
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
3044 } else if(inst->dst.addr_mode != MODE_REG) { |
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
3045 //b### with memory destination is modulo 8 |
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
3046 //x86-64 doesn't support 8-bit bit operations |
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
3047 //so we fake it by forcing the bit number to be modulo 8 |
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
3048 dst = and_ir(dst, 7, src_op.base, SZ_D); |
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
3049 size = SZ_D; |
154
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
3050 } |
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
3051 if (inst->op == M68K_BTST) { |
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
3052 if (dst_op.mode == MODE_REG_DIRECT) { |
221
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
3053 dst = bt_rr(dst, src_op.base, dst_op.base, size); |
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
3054 } else { |
221
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
3055 dst = bt_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, size); |
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
3056 } |
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
3057 } else if (inst->op == M68K_BSET) { |
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
3058 if (dst_op.mode == MODE_REG_DIRECT) { |
221
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
3059 dst = bts_rr(dst, src_op.base, dst_op.base, size); |
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
3060 } else { |
221
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
3061 dst = bts_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, size); |
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
3062 } |
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
3063 } else if (inst->op == M68K_BCLR) { |
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
3064 if (dst_op.mode == MODE_REG_DIRECT) { |
221
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
3065 dst = btr_rr(dst, src_op.base, dst_op.base, size); |
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
3066 } else { |
221
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
3067 dst = btr_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, size); |
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
3068 } |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
3069 } else { |
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
3070 if (dst_op.mode == MODE_REG_DIRECT) { |
221
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
3071 dst = btc_rr(dst, src_op.base, dst_op.base, size); |
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
3072 } else { |
221
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
3073 dst = btc_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, size); |
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
3074 } |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
3075 } |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
3076 if (src_op.base == SCRATCH2) { |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
3077 dst = pop_r(dst, SCRATCH2); |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
3078 } |
128
fe598ffd85ce
Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents:
126
diff
changeset
|
3079 } |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
3080 //x86 sets the carry flag to the value of the bit tested |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
3081 //68K sets the zero flag to the complement of the bit tested |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
3082 dst = setcc_r(dst, CC_NC, FLAG_Z); |
128
fe598ffd85ce
Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents:
126
diff
changeset
|
3083 if (inst->op != M68K_BTST) { |
fe598ffd85ce
Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents:
126
diff
changeset
|
3084 dst = m68k_save_result(inst, dst, opts); |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
3085 } |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
3086 break; |
226
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3087 case M68K_CHK: |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3088 { |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3089 dst = cycles(dst, 6); |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3090 if (dst_op.mode == MODE_REG_DIRECT) { |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3091 dst = cmp_ir(dst, 0, dst_op.base, inst->extra.size); |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3092 } else { |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3093 dst = cmp_irdisp8(dst, 0, dst_op.base, dst_op.disp, inst->extra.size); |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3094 } |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3095 uint8_t * passed = dst+1; |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3096 dst = jcc(dst, CC_GE, dst+2); |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3097 dst = mov_ir(dst, 1, FLAG_N, SZ_B); |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3098 dst = mov_ir(dst, VECTOR_CHK, SCRATCH2, SZ_D); |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3099 dst = mov_ir(dst, inst->address+2, SCRATCH1, SZ_D); |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3100 dst = jmp(dst, (uint8_t *)m68k_trap); |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3101 *passed = dst - (passed+1); |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3102 if (dst_op.mode == MODE_REG_DIRECT) { |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3103 if (src_op.mode == MODE_REG_DIRECT) { |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3104 dst = cmp_rr(dst, src_op.base, dst_op.base, inst->extra.size); |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3105 } else if(src_op.mode == MODE_REG_DISPLACE8) { |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3106 dst = cmp_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size); |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3107 } else { |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3108 dst = cmp_ir(dst, src_op.disp, dst_op.base, inst->extra.size); |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3109 } |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3110 } else if(dst_op.mode == MODE_REG_DISPLACE8) { |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3111 if (src_op.mode == MODE_REG_DIRECT) { |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3112 dst = cmp_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size); |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3113 } else { |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3114 dst = cmp_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3115 } |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3116 } |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3117 passed = dst+1; |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3118 dst = jcc(dst, CC_LE, dst+2); |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3119 dst = mov_ir(dst, 0, FLAG_N, SZ_B); |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3120 dst = mov_ir(dst, VECTOR_CHK, SCRATCH2, SZ_D); |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3121 dst = mov_ir(dst, inst->address+2, SCRATCH1, SZ_D); |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3122 dst = jmp(dst, (uint8_t *)m68k_trap); |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3123 *passed = dst - (passed+1); |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3124 dst = cycles(dst, 4); |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3125 break; |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3126 } |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3127 case M68K_DIVS: |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3128 case M68K_DIVU: |
228
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3129 { |
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3130 //TODO: cycle exact division |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3131 dst = cycles(dst, inst->op == M68K_DIVS ? 158 : 140); |
228
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3132 dst = mov_ir(dst, 0, FLAG_C, SZ_B); |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3133 dst = push_r(dst, RDX); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3134 dst = push_r(dst, RAX); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3135 if (dst_op.mode == MODE_REG_DIRECT) { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3136 dst = mov_rr(dst, dst_op.base, RAX, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3137 } else { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3138 dst = mov_rdisp8r(dst, dst_op.base, dst_op.disp, RAX, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3139 } |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3140 if (src_op.mode == MODE_IMMED) { |
228
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3141 dst = mov_ir(dst, (src_op.disp & 0x8000) && inst->op == M68K_DIVS ? src_op.disp | 0xFFFF0000 : src_op.disp, SCRATCH2, SZ_D); |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3142 } else if (src_op.mode == MODE_REG_DIRECT) { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3143 if (inst->op == M68K_DIVS) { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3144 dst = movsx_rr(dst, src_op.base, SCRATCH2, SZ_W, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3145 } else { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3146 dst = movzx_rr(dst, src_op.base, SCRATCH2, SZ_W, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3147 } |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3148 } else if (src_op.mode == MODE_REG_DISPLACE8) { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3149 if (inst->op == M68K_DIVS) { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3150 dst = movsx_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH2, SZ_W, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3151 } else { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3152 dst = movzx_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH2, SZ_W, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3153 } |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3154 } |
228
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3155 dst = cmp_ir(dst, 0, SCRATCH2, SZ_D); |
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3156 uint8_t * not_zero = dst+1; |
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3157 dst = jcc(dst, CC_NZ, dst+2); |
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3158 dst = pop_r(dst, RAX); |
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3159 dst = pop_r(dst, RDX); |
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3160 dst = mov_ir(dst, VECTOR_INT_DIV_ZERO, SCRATCH2, SZ_D); |
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3161 dst = mov_ir(dst, inst->address+2, SCRATCH1, SZ_D); |
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3162 dst = jmp(dst, (uint8_t *)m68k_trap); |
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3163 *not_zero = dst - (not_zero+1); |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3164 if (inst->op == M68K_DIVS) { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3165 dst = cdq(dst); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3166 } else { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3167 dst = xor_rr(dst, RDX, RDX, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3168 } |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3169 if (inst->op == M68K_DIVS) { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3170 dst = idiv_r(dst, SCRATCH2, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3171 } else { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3172 dst = div_r(dst, SCRATCH2, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3173 } |
228
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3174 uint8_t * skip_sec_check; |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
3175 if (inst->op == M68K_DIVS) { |
228
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3176 dst = cmp_ir(dst, 0x8000, RAX, SZ_D); |
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3177 skip_sec_check = dst + 1; |
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3178 dst = jcc(dst, CC_GE, dst+2); |
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3179 dst = cmp_ir(dst, -0x8000, RAX, SZ_D); |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
3180 norm_off = dst+1; |
228
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3181 dst = jcc(dst, CC_L, dst+2); |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
3182 } else { |
228
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3183 dst = cmp_ir(dst, 0x10000, RAX, SZ_D); |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
3184 norm_off = dst+1; |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
3185 dst = jcc(dst, CC_NC, dst+2); |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
3186 } |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3187 if (dst_op.mode == MODE_REG_DIRECT) { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3188 dst = mov_rr(dst, RDX, dst_op.base, SZ_W); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3189 dst = shl_ir(dst, 16, dst_op.base, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3190 dst = mov_rr(dst, RAX, dst_op.base, SZ_W); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3191 } else { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3192 dst = mov_rrdisp8(dst, RDX, dst_op.base, dst_op.disp, SZ_W); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3193 dst = shl_irdisp8(dst, 16, dst_op.base, dst_op.disp, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3194 dst = mov_rrdisp8(dst, RAX, dst_op.base, dst_op.disp, SZ_W); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3195 } |
209
922b59c09259
Flag fixes for div, negx and not
Mike Pavone <pavone@retrodev.com>
parents:
208
diff
changeset
|
3196 dst = cmp_ir(dst, 0, RAX, SZ_W); |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3197 dst = pop_r(dst, RAX); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3198 dst = pop_r(dst, RDX); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3199 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3200 dst = setcc_r(dst, CC_Z, FLAG_Z); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3201 dst = setcc_r(dst, CC_S, FLAG_N); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3202 end_off = dst+1; |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3203 dst = jmp(dst, dst+2); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3204 *norm_off = dst - (norm_off + 1); |
228
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3205 if (inst->op == M68K_DIVS) { |
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3206 *skip_sec_check = dst - (skip_sec_check+1); |
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3207 } |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3208 dst = pop_r(dst, RAX); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3209 dst = pop_r(dst, RDX); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3210 dst = mov_ir(dst, 1, FLAG_V, SZ_B); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3211 *end_off = dst - (end_off + 1); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3212 break; |
228
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3213 } |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3214 case M68K_EOR: |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3215 dst = cycles(dst, BUS); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3216 if (src_op.mode == MODE_REG_DIRECT) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3217 if (dst_op.mode == MODE_REG_DIRECT) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3218 dst = xor_rr(dst, src_op.base, dst_op.base, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3219 } else { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3220 dst = xor_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3221 } |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3222 } else if (src_op.mode == MODE_REG_DISPLACE8) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3223 dst = xor_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3224 } else { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3225 if (dst_op.mode == MODE_REG_DIRECT) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3226 dst = xor_ir(dst, src_op.disp, dst_op.base, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3227 } else { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3228 dst = xor_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3229 } |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3230 } |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3231 dst = mov_ir(dst, 0, FLAG_C, SZ_B); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3232 dst = setcc_r(dst, CC_Z, FLAG_Z); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3233 dst = setcc_r(dst, CC_S, FLAG_N); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3234 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3235 dst = m68k_save_result(inst, dst, opts); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3236 break; |
171 | 3237 case M68K_EORI_CCR: |
3238 case M68K_EORI_SR: | |
3239 dst = cycles(dst, 20); | |
3240 //TODO: If ANDI to SR, trap if not in supervisor mode | |
3241 if (inst->src.params.immed & 0x1) { | |
3242 dst = xor_ir(dst, 1, FLAG_C, SZ_B); | |
3243 } | |
3244 if (inst->src.params.immed & 0x2) { | |
3245 dst = xor_ir(dst, 1, FLAG_V, SZ_B); | |
3246 } | |
3247 if (inst->src.params.immed & 0x4) { | |
3248 dst = xor_ir(dst, 1, FLAG_Z, SZ_B); | |
3249 } | |
3250 if (inst->src.params.immed & 0x8) { | |
3251 dst = xor_ir(dst, 1, FLAG_N, SZ_B); | |
3252 } | |
3253 if (inst->src.params.immed & 0x10) { | |
3254 dst = xor_irdisp8(dst, 1, CONTEXT, 0, SZ_B); | |
3255 } | |
3256 if (inst->op == M68K_ORI_SR) { | |
3257 dst = xor_irdisp8(dst, inst->src.params.immed >> 8, CONTEXT, offsetof(m68k_context, status), SZ_B); | |
3258 if (inst->src.params.immed & 0x700) { | |
3259 dst = call(dst, (uint8_t *)do_sync); | |
3260 } | |
3261 } | |
3262 break; | |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3263 case M68K_EXG: |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3264 dst = cycles(dst, 6); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3265 if (dst_op.mode == MODE_REG_DIRECT) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3266 dst = mov_rr(dst, dst_op.base, SCRATCH2, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3267 if (src_op.mode == MODE_REG_DIRECT) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3268 dst = mov_rr(dst, src_op.base, dst_op.base, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3269 dst = mov_rr(dst, SCRATCH2, src_op.base, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3270 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3271 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3272 dst = mov_rrdisp8(dst, SCRATCH2, src_op.base, src_op.disp, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3273 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3274 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3275 dst = mov_rdisp8r(dst, dst_op.base, dst_op.disp, SCRATCH2, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3276 if (src_op.mode == MODE_REG_DIRECT) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3277 dst = mov_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3278 dst = mov_rr(dst, SCRATCH2, src_op.base, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3279 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3280 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3281 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3282 dst = mov_rrdisp8(dst, SCRATCH2, src_op.base, src_op.disp, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3283 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3284 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3285 break; |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3286 case M68K_ILLEGAL: |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3287 dst = call(dst, (uint8_t *)m68k_save_context); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3288 dst = mov_rr(dst, CONTEXT, RDI, SZ_Q); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3289 dst = call(dst, (uint8_t *)print_regs_exit); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3290 break; |
105 | 3291 case M68K_MOVE_FROM_SR: |
3292 //TODO: Trap if not in system mode | |
3293 dst = call(dst, (uint8_t *)get_sr); | |
3294 if (dst_op.mode == MODE_REG_DIRECT) { | |
3295 dst = mov_rr(dst, SCRATCH1, dst_op.base, SZ_W); | |
3296 } else { | |
3297 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, SZ_W); | |
3298 } | |
3299 dst = m68k_save_result(inst, dst, opts); | |
3300 break; | |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3301 case M68K_MOVE_CCR: |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3302 case M68K_MOVE_SR: |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3303 //TODO: Privilege check for MOVE to SR |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3304 if (src_op.mode == MODE_IMMED) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3305 dst = mov_ir(dst, src_op.disp & 0x1, FLAG_C, SZ_B); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3306 dst = mov_ir(dst, (src_op.disp >> 1) & 0x1, FLAG_V, SZ_B); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3307 dst = mov_ir(dst, (src_op.disp >> 2) & 0x1, FLAG_Z, SZ_B); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3308 dst = mov_ir(dst, (src_op.disp >> 3) & 0x1, FLAG_N, SZ_B); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3309 dst = mov_irind(dst, (src_op.disp >> 4) & 0x1, CONTEXT, SZ_B); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3310 if (inst->op == M68K_MOVE_SR) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3311 dst = mov_irdisp8(dst, (src_op.disp >> 8), CONTEXT, offsetof(m68k_context, status), SZ_B); |
73
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3312 if (!((inst->src.params.immed >> 8) & (1 << BIT_SUPERVISOR))) { |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3313 //leave supervisor mode |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3314 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3315 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, opts->aregs[7], SZ_D); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3316 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_D); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3317 } |
150
3e68e517cc01
Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed.
Mike Pavone <pavone@retrodev.com>
parents:
146
diff
changeset
|
3318 dst = call(dst, (uint8_t *)do_sync); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3319 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3320 dst = cycles(dst, 12); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3321 } else { |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3322 if (src_op.base != SCRATCH1) { |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3323 if (src_op.mode == MODE_REG_DIRECT) { |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3324 dst = mov_rr(dst, src_op.base, SCRATCH1, SZ_W); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3325 } else { |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3326 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_W); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3327 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3328 } |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3329 dst = call(dst, (uint8_t *)(inst->op == M68K_MOVE_SR ? set_sr : set_ccr)); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3330 dst = cycles(dst, 12); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3331 |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3332 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3333 break; |
73
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3334 case M68K_MOVE_USP: |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3335 dst = cycles(dst, BUS); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3336 //TODO: Trap if not in supervisor mode |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3337 //dst = bt_irdisp8(dst, BIT_SUPERVISOR, CONTEXT, offsetof(m68k_context, status), SZ_B); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3338 if (inst->src.addr_mode == MODE_UNUSED) { |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3339 if (dst_op.mode == MODE_REG_DIRECT) { |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3340 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, dst_op.base, SZ_D); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3341 } else { |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3342 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SCRATCH1, SZ_D); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3343 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, SZ_D); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3344 } |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3345 } else { |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3346 if (src_op.mode == MODE_REG_DIRECT) { |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3347 dst = mov_rrdisp8(dst, src_op.base, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_D); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3348 } else { |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3349 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_D); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3350 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_D); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3351 } |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3352 } |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3353 break; |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3354 //case M68K_MOVEP: |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3355 case M68K_MULS: |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3356 case M68K_MULU: |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3357 dst = cycles(dst, 70); //TODO: Calculate the actual value based on the value of the <ea> parameter |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3358 if (src_op.mode == MODE_IMMED) { |
223
17534fb7c4f5
Fix muls with a negative immediate source.
Mike Pavone <pavone@retrodev.com>
parents:
221
diff
changeset
|
3359 dst = mov_ir(dst, inst->op == M68K_MULU ? (src_op.disp & 0xFFFF) : ((src_op.disp & 0x8000) ? src_op.disp | 0xFFFF0000 : src_op.disp), SCRATCH1, SZ_D); |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3360 } else if (src_op.mode == MODE_REG_DIRECT) { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3361 if (inst->op == M68K_MULS) { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3362 dst = movsx_rr(dst, src_op.base, SCRATCH1, SZ_W, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3363 } else { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3364 dst = movzx_rr(dst, src_op.base, SCRATCH1, SZ_W, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3365 } |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3366 } else { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3367 if (inst->op == M68K_MULS) { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3368 dst = movsx_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_W, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3369 } else { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3370 dst = movzx_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_W, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3371 } |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3372 } |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3373 if (dst_op.mode == MODE_REG_DIRECT) { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3374 dst_reg = dst_op.base; |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3375 if (inst->op == M68K_MULS) { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3376 dst = movsx_rr(dst, dst_reg, dst_reg, SZ_W, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3377 } else { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3378 dst = movzx_rr(dst, dst_reg, dst_reg, SZ_W, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3379 } |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3380 } else { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3381 dst_reg = SCRATCH2; |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3382 if (inst->op == M68K_MULS) { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3383 dst = movsx_rdisp8r(dst, dst_op.base, dst_op.disp, SCRATCH2, SZ_W, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3384 } else { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3385 dst = movzx_rdisp8r(dst, dst_op.base, dst_op.disp, SCRATCH2, SZ_W, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3386 } |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3387 } |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3388 dst = imul_rr(dst, SCRATCH1, dst_reg, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3389 if (dst_op.mode == MODE_REG_DISPLACE8) { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3390 dst = mov_rrdisp8(dst, dst_reg, dst_op.base, dst_op.disp, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3391 } |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3392 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3393 dst = mov_ir(dst, 0, FLAG_C, SZ_B); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3394 dst = cmp_ir(dst, 0, dst_reg, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3395 dst = setcc_r(dst, CC_Z, FLAG_Z); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3396 dst = setcc_r(dst, CC_S, FLAG_N); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3397 break; |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3398 //case M68K_NBCD: |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3399 case M68K_NEG: |
173 | 3400 dst = cycles(dst, BUS); |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3401 if (dst_op.mode == MODE_REG_DIRECT) { |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3402 dst = neg_r(dst, dst_op.base, inst->extra.size); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3403 } else { |
165
62b152811bae
Fix certain address modes with lea when the destination is not a native register
Mike Pavone <pavone@retrodev.com>
parents:
162
diff
changeset
|
3404 dst = neg_rdisp8(dst, dst_op.base, dst_op.disp, inst->extra.size); |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3405 } |
173 | 3406 dst = setcc_r(dst, CC_C, FLAG_C); |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3407 dst = setcc_r(dst, CC_Z, FLAG_Z); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3408 dst = setcc_r(dst, CC_S, FLAG_N); |
173 | 3409 dst = setcc_r(dst, CC_O, FLAG_V); |
3410 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B); | |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3411 dst = m68k_save_result(inst, dst, opts); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3412 break; |
173 | 3413 case M68K_NEGX: |
3414 dst = cycles(dst, BUS); | |
3415 if (dst_op.mode == MODE_REG_DIRECT) { | |
3416 if (dst_op.base == SCRATCH1) { | |
3417 dst = push_r(dst, SCRATCH2); | |
3418 dst = xor_rr(dst, SCRATCH2, SCRATCH2, inst->extra.size); | |
3419 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B); | |
3420 dst = sbb_rr(dst, dst_op.base, SCRATCH2, inst->extra.size); | |
3421 dst = mov_rr(dst, SCRATCH2, dst_op.base, inst->extra.size); | |
3422 dst = pop_r(dst, SCRATCH2); | |
3423 } else { | |
3424 dst = xor_rr(dst, SCRATCH1, SCRATCH1, inst->extra.size); | |
3425 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B); | |
3426 dst = sbb_rr(dst, dst_op.base, SCRATCH1, inst->extra.size); | |
3427 dst = mov_rr(dst, SCRATCH1, dst_op.base, inst->extra.size); | |
3428 } | |
3429 } else { | |
3430 dst = xor_rr(dst, SCRATCH1, SCRATCH1, inst->extra.size); | |
3431 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B); | |
3432 dst = sbb_rdisp8r(dst, dst_op.base, dst_op.disp, SCRATCH1, inst->extra.size); | |
3433 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, inst->extra.size); | |
3434 } | |
3435 dst = setcc_r(dst, CC_C, FLAG_C); | |
209
922b59c09259
Flag fixes for div, negx and not
Mike Pavone <pavone@retrodev.com>
parents:
208
diff
changeset
|
3436 dst = jcc(dst, CC_Z, dst+4); |
922b59c09259
Flag fixes for div, negx and not
Mike Pavone <pavone@retrodev.com>
parents:
208
diff
changeset
|
3437 dst = mov_ir(dst, 0, FLAG_Z, SZ_B); |
173 | 3438 dst = setcc_r(dst, CC_S, FLAG_N); |
3439 dst = setcc_r(dst, CC_O, FLAG_V); | |
3440 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B); | |
3441 dst = m68k_save_result(inst, dst, opts); | |
3442 break; | |
3443 break; | |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3444 case M68K_NOP: |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3445 dst = cycles(dst, BUS); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3446 break; |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3447 case M68K_NOT: |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3448 if (dst_op.mode == MODE_REG_DIRECT) { |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3449 dst = not_r(dst, dst_op.base, inst->extra.size); |
209
922b59c09259
Flag fixes for div, negx and not
Mike Pavone <pavone@retrodev.com>
parents:
208
diff
changeset
|
3450 dst = cmp_ir(dst, 0, dst_op.base, inst->extra.size); |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3451 } else { |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3452 dst = not_rdisp8(dst, dst_op.base, dst_op.disp, inst->extra.size); |
209
922b59c09259
Flag fixes for div, negx and not
Mike Pavone <pavone@retrodev.com>
parents:
208
diff
changeset
|
3453 dst = cmp_irdisp8(dst, 0, dst_op.base, dst_op.disp, inst->extra.size); |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3454 } |
209
922b59c09259
Flag fixes for div, negx and not
Mike Pavone <pavone@retrodev.com>
parents:
208
diff
changeset
|
3455 |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3456 dst = mov_ir(dst, 0, FLAG_C, SZ_B); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3457 dst = setcc_r(dst, CC_Z, FLAG_Z); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3458 dst = setcc_r(dst, CC_S, FLAG_N); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3459 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3460 dst = m68k_save_result(inst, dst, opts); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3461 break; |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3462 case M68K_OR: |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3463 dst = cycles(dst, BUS); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3464 if (src_op.mode == MODE_REG_DIRECT) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3465 if (dst_op.mode == MODE_REG_DIRECT) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3466 dst = or_rr(dst, src_op.base, dst_op.base, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3467 } else { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3468 dst = or_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3469 } |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3470 } else if (src_op.mode == MODE_REG_DISPLACE8) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3471 dst = or_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3472 } else { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3473 if (dst_op.mode == MODE_REG_DIRECT) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3474 dst = or_ir(dst, src_op.disp, dst_op.base, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3475 } else { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3476 dst = or_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3477 } |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3478 } |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3479 dst = mov_ir(dst, 0, FLAG_C, SZ_B); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3480 dst = setcc_r(dst, CC_Z, FLAG_Z); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3481 dst = setcc_r(dst, CC_S, FLAG_N); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3482 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3483 dst = m68k_save_result(inst, dst, opts); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3484 break; |
106 | 3485 case M68K_ORI_CCR: |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3486 case M68K_ORI_SR: |
106 | 3487 dst = cycles(dst, 20); |
3488 //TODO: If ANDI to SR, trap if not in supervisor mode | |
3489 if (inst->src.params.immed & 0x1) { | |
3490 dst = mov_ir(dst, 1, FLAG_C, SZ_B); | |
3491 } | |
3492 if (inst->src.params.immed & 0x2) { | |
3493 dst = mov_ir(dst, 1, FLAG_V, SZ_B); | |
3494 } | |
3495 if (inst->src.params.immed & 0x4) { | |
3496 dst = mov_ir(dst, 1, FLAG_Z, SZ_B); | |
3497 } | |
3498 if (inst->src.params.immed & 0x8) { | |
3499 dst = mov_ir(dst, 1, FLAG_N, SZ_B); | |
3500 } | |
3501 if (inst->src.params.immed & 0x10) { | |
3502 dst = mov_irind(dst, 1, CONTEXT, SZ_B); | |
3503 } | |
150
3e68e517cc01
Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed.
Mike Pavone <pavone@retrodev.com>
parents:
146
diff
changeset
|
3504 if (inst->op == M68K_ORI_SR) { |
106 | 3505 dst = or_irdisp8(dst, inst->src.params.immed >> 8, CONTEXT, offsetof(m68k_context, status), SZ_B); |
150
3e68e517cc01
Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed.
Mike Pavone <pavone@retrodev.com>
parents:
146
diff
changeset
|
3506 if (inst->src.params.immed & 0x700) { |
3e68e517cc01
Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed.
Mike Pavone <pavone@retrodev.com>
parents:
146
diff
changeset
|
3507 dst = call(dst, (uint8_t *)do_sync); |
3e68e517cc01
Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed.
Mike Pavone <pavone@retrodev.com>
parents:
146
diff
changeset
|
3508 } |
106 | 3509 } |
3510 break; | |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
211
diff
changeset
|
3511 case M68K_RESET: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
211
diff
changeset
|
3512 dst = call(dst, (uint8_t *)m68k_save_context); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
211
diff
changeset
|
3513 dst = mov_rr(dst, CONTEXT, RDI, SZ_Q); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
211
diff
changeset
|
3514 dst = call(dst, (uint8_t *)print_regs_exit); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
211
diff
changeset
|
3515 break; |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3516 case M68K_ROL: |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3517 case M68K_ROR: |
122 | 3518 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
3519 if (inst->src.addr_mode == MODE_UNUSED) { | |
3520 dst = cycles(dst, BUS); | |
3521 //Memory rotate | |
3522 if (inst->op == M68K_ROL) { | |
3523 dst = rol_ir(dst, 1, dst_op.base, inst->extra.size); | |
3524 } else { | |
3525 dst = ror_ir(dst, 1, dst_op.base, inst->extra.size); | |
3526 } | |
3527 dst = setcc_r(dst, CC_C, FLAG_C); | |
3528 dst = cmp_ir(dst, 0, dst_op.base, inst->extra.size); | |
3529 dst = setcc_r(dst, CC_Z, FLAG_Z); | |
3530 dst = setcc_r(dst, CC_S, FLAG_N); | |
3531 dst = m68k_save_result(inst, dst, opts); | |
3532 } else { | |
3533 if (src_op.mode == MODE_IMMED) { | |
3534 dst = cycles(dst, (inst->extra.size == OPSIZE_LONG ? 8 : 6) + src_op.disp*2); | |
3535 if (dst_op.mode == MODE_REG_DIRECT) { | |
3536 if (inst->op == M68K_ROL) { | |
3537 dst = rol_ir(dst, src_op.disp, dst_op.base, inst->extra.size); | |
3538 } else { | |
3539 dst = ror_ir(dst, src_op.disp, dst_op.base, inst->extra.size); | |
3540 } | |
3541 } else { | |
3542 if (inst->op == M68K_ROL) { | |
3543 dst = rol_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); | |
3544 } else { | |
3545 dst = ror_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); | |
3546 } | |
3547 } | |
3548 dst = setcc_r(dst, CC_C, FLAG_C); | |
3549 } else { | |
3550 if (src_op.mode == MODE_REG_DIRECT) { | |
3551 if (src_op.base != SCRATCH1) { | |
3552 dst = mov_rr(dst, src_op.base, SCRATCH1, SZ_B); | |
3553 } | |
3554 } else { | |
3555 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_B); | |
3556 } | |
3557 dst = and_ir(dst, 63, SCRATCH1, SZ_D); | |
3558 zero_off = dst+1; | |
157
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3559 dst = jcc(dst, CC_Z, dst+2); |
122 | 3560 dst = add_rr(dst, SCRATCH1, CYCLES, SZ_D); |
3561 dst = add_rr(dst, SCRATCH1, CYCLES, SZ_D); | |
3562 dst = cmp_ir(dst, 32, SCRATCH1, SZ_B); | |
3563 norm_off = dst+1; | |
3564 dst = jcc(dst, CC_L, dst+2); | |
3565 if (dst_op.mode == MODE_REG_DIRECT) { | |
3566 if (inst->op == M68K_ROL) { | |
3567 dst = rol_ir(dst, 31, dst_op.base, inst->extra.size); | |
3568 dst = rol_ir(dst, 1, dst_op.base, inst->extra.size); | |
3569 } else { | |
3570 dst = ror_ir(dst, 31, dst_op.base, inst->extra.size); | |
3571 dst = ror_ir(dst, 1, dst_op.base, inst->extra.size); | |
3572 } | |
3573 } else { | |
3574 if (inst->op == M68K_ROL) { | |
3575 dst = rol_irdisp8(dst, 31, dst_op.base, dst_op.disp, inst->extra.size); | |
3576 dst = rol_irdisp8(dst, 1, dst_op.base, dst_op.disp, inst->extra.size); | |
3577 } else { | |
3578 dst = ror_irdisp8(dst, 31, dst_op.base, dst_op.disp, inst->extra.size); | |
3579 dst = ror_irdisp8(dst, 1, dst_op.base, dst_op.disp, inst->extra.size); | |
3580 } | |
3581 } | |
3582 dst = sub_ir(dst, 32, SCRATCH1, SZ_B); | |
3583 *norm_off = dst - (norm_off+1); | |
3584 if (dst_op.mode == MODE_REG_DIRECT) { | |
3585 if (inst->op == M68K_ROL) { | |
3586 dst = rol_clr(dst, dst_op.base, inst->extra.size); | |
3587 } else { | |
3588 dst = ror_clr(dst, dst_op.base, inst->extra.size); | |
3589 } | |
3590 } else { | |
3591 if (inst->op == M68K_ROL) { | |
3592 dst = rol_clrdisp8(dst, dst_op.base, dst_op.disp, inst->extra.size); | |
3593 } else { | |
3594 dst = ror_clrdisp8(dst, dst_op.base, dst_op.disp, inst->extra.size); | |
3595 } | |
3596 } | |
3597 dst = setcc_r(dst, CC_C, FLAG_C); | |
3598 end_off = dst + 1; | |
3599 dst = jmp(dst, dst+2); | |
3600 *zero_off = dst - (zero_off+1); | |
3601 dst = mov_ir(dst, 0, FLAG_C, SZ_B); | |
3602 *end_off = dst - (end_off+1); | |
3603 } | |
3604 if (dst_op.mode == MODE_REG_DIRECT) { | |
3605 dst = cmp_ir(dst, 0, dst_op.base, inst->extra.size); | |
3606 } else { | |
3607 dst = cmp_irdisp8(dst, 0, dst_op.base, dst_op.disp, inst->extra.size); | |
3608 } | |
3609 dst = setcc_r(dst, CC_Z, FLAG_Z); | |
3610 dst = setcc_r(dst, CC_S, FLAG_N); | |
3611 } | |
3612 break; | |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3613 case M68K_ROXL: |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3614 case M68K_ROXR: |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3615 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3616 if (inst->src.addr_mode == MODE_UNUSED) { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3617 dst = cycles(dst, BUS); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3618 //Memory rotate |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3619 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3620 if (inst->op == M68K_ROXL) { |
157
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3621 dst = rcl_ir(dst, 1, dst_op.base, inst->extra.size); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3622 } else { |
157
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3623 dst = rcr_ir(dst, 1, dst_op.base, inst->extra.size); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3624 } |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3625 dst = setcc_r(dst, CC_C, FLAG_C); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3626 dst = cmp_ir(dst, 0, dst_op.base, inst->extra.size); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3627 dst = setcc_r(dst, CC_Z, FLAG_Z); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3628 dst = setcc_r(dst, CC_S, FLAG_N); |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
3629 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3630 dst = m68k_save_result(inst, dst, opts); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3631 } else { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3632 if (src_op.mode == MODE_IMMED) { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3633 dst = cycles(dst, (inst->extra.size == OPSIZE_LONG ? 8 : 6) + src_op.disp*2); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3634 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3635 if (dst_op.mode == MODE_REG_DIRECT) { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3636 if (inst->op == M68K_ROXL) { |
157
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3637 dst = rcl_ir(dst, src_op.disp, dst_op.base, inst->extra.size); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3638 } else { |
157
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3639 dst = rcr_ir(dst, src_op.disp, dst_op.base, inst->extra.size); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3640 } |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3641 } else { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3642 if (inst->op == M68K_ROXL) { |
157
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3643 dst = rcl_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3644 } else { |
157
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3645 dst = rcr_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3646 } |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3647 } |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3648 dst = setcc_r(dst, CC_C, FLAG_C); |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
3649 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3650 } else { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3651 if (src_op.mode == MODE_REG_DIRECT) { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3652 if (src_op.base != SCRATCH1) { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3653 dst = mov_rr(dst, src_op.base, SCRATCH1, SZ_B); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3654 } |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3655 } else { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3656 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_B); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3657 } |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3658 dst = and_ir(dst, 63, SCRATCH1, SZ_D); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3659 zero_off = dst+1; |
157
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3660 dst = jcc(dst, CC_Z, dst+2); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3661 dst = add_rr(dst, SCRATCH1, CYCLES, SZ_D); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3662 dst = add_rr(dst, SCRATCH1, CYCLES, SZ_D); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3663 dst = cmp_ir(dst, 32, SCRATCH1, SZ_B); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3664 norm_off = dst+1; |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3665 dst = jcc(dst, CC_L, dst+2); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3666 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3667 if (dst_op.mode == MODE_REG_DIRECT) { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3668 if (inst->op == M68K_ROXL) { |
157
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3669 dst = rcl_ir(dst, 31, dst_op.base, inst->extra.size); |
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3670 dst = rcl_ir(dst, 1, dst_op.base, inst->extra.size); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3671 } else { |
157
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3672 dst = rcr_ir(dst, 31, dst_op.base, inst->extra.size); |
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3673 dst = rcr_ir(dst, 1, dst_op.base, inst->extra.size); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3674 } |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3675 } else { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3676 if (inst->op == M68K_ROXL) { |
157
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3677 dst = rcl_irdisp8(dst, 31, dst_op.base, dst_op.disp, inst->extra.size); |
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3678 dst = rcl_irdisp8(dst, 1, dst_op.base, dst_op.disp, inst->extra.size); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3679 } else { |
157
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3680 dst = rcr_irdisp8(dst, 31, dst_op.base, dst_op.disp, inst->extra.size); |
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3681 dst = rcr_irdisp8(dst, 1, dst_op.base, dst_op.disp, inst->extra.size); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3682 } |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3683 } |
225
7348057e7a8c
Fixed a couple bugs in roxl/roxr. X flag wasn't being saved properly and rotates of more than 31 bits were messed up as the X flag was being thrown away between the first 31 bits of rotate and the rest.
Mike Pavone <pavone@retrodev.com>
parents:
223
diff
changeset
|
3684 dst = setcc_rind(dst, CC_C, CONTEXT); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3685 dst = sub_ir(dst, 32, SCRATCH1, SZ_B); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3686 *norm_off = dst - (norm_off+1); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3687 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3688 if (dst_op.mode == MODE_REG_DIRECT) { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3689 if (inst->op == M68K_ROXL) { |
157
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3690 dst = rcl_clr(dst, dst_op.base, inst->extra.size); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3691 } else { |
157
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3692 dst = rcr_clr(dst, dst_op.base, inst->extra.size); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3693 } |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3694 } else { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3695 if (inst->op == M68K_ROXL) { |
157
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3696 dst = rcl_clrdisp8(dst, dst_op.base, dst_op.disp, inst->extra.size); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3697 } else { |
157
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3698 dst = rcr_clrdisp8(dst, dst_op.base, dst_op.disp, inst->extra.size); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3699 } |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3700 } |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3701 dst = setcc_r(dst, CC_C, FLAG_C); |
225
7348057e7a8c
Fixed a couple bugs in roxl/roxr. X flag wasn't being saved properly and rotates of more than 31 bits were messed up as the X flag was being thrown away between the first 31 bits of rotate and the rest.
Mike Pavone <pavone@retrodev.com>
parents:
223
diff
changeset
|
3702 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3703 end_off = dst + 1; |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3704 dst = jmp(dst, dst+2); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3705 *zero_off = dst - (zero_off+1); |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
3706 //Carry flag is set to X flag when count is 0, this is different from ROR/ROL |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
3707 dst = mov_rindr(dst, CONTEXT, FLAG_C, SZ_B); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3708 *end_off = dst - (end_off+1); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3709 } |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3710 if (dst_op.mode == MODE_REG_DIRECT) { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3711 dst = cmp_ir(dst, 0, dst_op.base, inst->extra.size); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3712 } else { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3713 dst = cmp_irdisp8(dst, 0, dst_op.base, dst_op.disp, inst->extra.size); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3714 } |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3715 dst = setcc_r(dst, CC_Z, FLAG_Z); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3716 dst = setcc_r(dst, CC_S, FLAG_N); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3717 } |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3718 break; |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3719 case M68K_RTE: |
170 | 3720 //TODO: Trap if not in system mode |
175
7504200cac86
Fix order of SR and PC saved in an exception stack frame
Mike Pavone <pavone@retrodev.com>
parents:
174
diff
changeset
|
3721 //Read saved SR |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3722 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3723 dst = call(dst, (uint8_t *)m68k_read_word_scratch1); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3724 dst = add_ir(dst, 2, opts->aregs[7], SZ_D); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3725 dst = call(dst, (uint8_t *)set_sr); |
178
48eb62ba63bc
Fix order of reading saved pc and swapping user and system stack pointers
Mike Pavone <pavone@retrodev.com>
parents:
177
diff
changeset
|
3726 //Read saved PC |
48eb62ba63bc
Fix order of reading saved pc and swapping user and system stack pointers
Mike Pavone <pavone@retrodev.com>
parents:
177
diff
changeset
|
3727 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D); |
48eb62ba63bc
Fix order of reading saved pc and swapping user and system stack pointers
Mike Pavone <pavone@retrodev.com>
parents:
177
diff
changeset
|
3728 dst = call(dst, (uint8_t *)m68k_read_long_scratch1); |
48eb62ba63bc
Fix order of reading saved pc and swapping user and system stack pointers
Mike Pavone <pavone@retrodev.com>
parents:
177
diff
changeset
|
3729 dst = add_ir(dst, 4, opts->aregs[7], SZ_D); |
175
7504200cac86
Fix order of SR and PC saved in an exception stack frame
Mike Pavone <pavone@retrodev.com>
parents:
174
diff
changeset
|
3730 //Check if we've switched to user mode and swap stack pointers if needed |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3731 dst = bt_irdisp8(dst, 5, CONTEXT, offsetof(m68k_context, status), SZ_B); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3732 end_off = dst+1; |
121
f848aad2abef
Fix logic for switching between USP and SSP
Mike Pavone <pavone@retrodev.com>
parents:
119
diff
changeset
|
3733 dst = jcc(dst, CC_C, dst+2); |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3734 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3735 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, opts->aregs[7], SZ_D); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3736 dst = mov_rrdisp8(dst, SCRATCH2, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_D); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3737 *end_off = dst - (end_off+1); |
175
7504200cac86
Fix order of SR and PC saved in an exception stack frame
Mike Pavone <pavone@retrodev.com>
parents:
174
diff
changeset
|
3738 //Get native address, sync components, recalculate integer points and jump to returned address |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3739 dst = call(dst, (uint8_t *)m68k_native_addr_and_sync); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3740 dst = jmp_r(dst, SCRATCH1); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3741 break; |
170 | 3742 case M68K_RTR: |
175
7504200cac86
Fix order of SR and PC saved in an exception stack frame
Mike Pavone <pavone@retrodev.com>
parents:
174
diff
changeset
|
3743 //Read saved CCR |
170 | 3744 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D); |
3745 dst = call(dst, (uint8_t *)m68k_read_word_scratch1); | |
3746 dst = add_ir(dst, 2, opts->aregs[7], SZ_D); | |
3747 dst = call(dst, (uint8_t *)set_ccr); | |
175
7504200cac86
Fix order of SR and PC saved in an exception stack frame
Mike Pavone <pavone@retrodev.com>
parents:
174
diff
changeset
|
3748 //Read saved PC |
7504200cac86
Fix order of SR and PC saved in an exception stack frame
Mike Pavone <pavone@retrodev.com>
parents:
174
diff
changeset
|
3749 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D); |
7504200cac86
Fix order of SR and PC saved in an exception stack frame
Mike Pavone <pavone@retrodev.com>
parents:
174
diff
changeset
|
3750 dst = call(dst, (uint8_t *)m68k_read_long_scratch1); |
7504200cac86
Fix order of SR and PC saved in an exception stack frame
Mike Pavone <pavone@retrodev.com>
parents:
174
diff
changeset
|
3751 dst = add_ir(dst, 4, opts->aregs[7], SZ_D); |
7504200cac86
Fix order of SR and PC saved in an exception stack frame
Mike Pavone <pavone@retrodev.com>
parents:
174
diff
changeset
|
3752 //Get native address and jump to it |
7504200cac86
Fix order of SR and PC saved in an exception stack frame
Mike Pavone <pavone@retrodev.com>
parents:
174
diff
changeset
|
3753 dst = call(dst, (uint8_t *)m68k_native_addr); |
170 | 3754 dst = jmp_r(dst, SCRATCH1); |
3755 break; | |
194
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3756 case M68K_SBCD: |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3757 if (src_op.base != SCRATCH2) { |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3758 if (src_op.mode == MODE_REG_DIRECT) { |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3759 dst = mov_rr(dst, src_op.base, SCRATCH2, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3760 } else { |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3761 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH2, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3762 } |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3763 } |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3764 if (dst_op.base != SCRATCH1) { |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3765 if (dst_op.mode == MODE_REG_DIRECT) { |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3766 dst = mov_rr(dst, dst_op.base, SCRATCH1, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3767 } else { |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3768 dst = mov_rdisp8r(dst, dst_op.base, dst_op.disp, SCRATCH1, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3769 } |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3770 } |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3771 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3772 dst = jcc(dst, CC_NC, dst+5); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3773 dst = sub_ir(dst, 1, SCRATCH1, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3774 dst = call(dst, (uint8_t *)bcd_sub); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3775 dst = mov_rr(dst, CH, FLAG_C, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3776 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3777 dst = cmp_ir(dst, 0, SCRATCH1, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3778 dst = jcc(dst, CC_Z, dst+4); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3779 dst = mov_ir(dst, 0, FLAG_Z, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3780 if (dst_op.base != SCRATCH1) { |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3781 if (dst_op.mode == MODE_REG_DIRECT) { |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3782 dst = mov_rr(dst, SCRATCH1, dst_op.base, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3783 } else { |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3784 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3785 } |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3786 } |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3787 dst = m68k_save_result(inst, dst, opts); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3788 break; |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3789 /*case M68K_STOP: |
70
cebd0b5ac7f0
Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents:
67
diff
changeset
|
3790 break;*/ |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3791 case M68K_SUB: |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
3792 size = inst->dst.addr_mode == MODE_AREG ? OPSIZE_LONG : inst->extra.size; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3793 dst = cycles(dst, BUS); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3794 if (src_op.mode == MODE_REG_DIRECT) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3795 if (dst_op.mode == MODE_REG_DIRECT) { |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
3796 dst = sub_rr(dst, src_op.base, dst_op.base, size); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3797 } else { |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
3798 dst = sub_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, size); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3799 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3800 } else if (src_op.mode == MODE_REG_DISPLACE8) { |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
3801 dst = sub_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, size); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3802 } else { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3803 if (dst_op.mode == MODE_REG_DIRECT) { |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
3804 dst = sub_ir(dst, src_op.disp, dst_op.base, size); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3805 } else { |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
3806 dst = sub_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, size); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3807 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3808 } |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
3809 if (inst->dst.addr_mode != MODE_AREG) { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
3810 dst = setcc_r(dst, CC_C, FLAG_C); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
3811 dst = setcc_r(dst, CC_Z, FLAG_Z); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
3812 dst = setcc_r(dst, CC_S, FLAG_N); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
3813 dst = setcc_r(dst, CC_O, FLAG_V); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
3814 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
3815 } |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3816 dst = m68k_save_result(inst, dst, opts); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3817 break; |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3818 case M68K_SUBX: |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3819 dst = cycles(dst, BUS); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3820 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3821 if (src_op.mode == MODE_REG_DIRECT) { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3822 if (dst_op.mode == MODE_REG_DIRECT) { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3823 dst = sbb_rr(dst, src_op.base, dst_op.base, inst->extra.size); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3824 } else { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3825 dst = sbb_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3826 } |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3827 } else if (src_op.mode == MODE_REG_DISPLACE8) { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3828 dst = sbb_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3829 } else { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3830 if (dst_op.mode == MODE_REG_DIRECT) { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3831 dst = sbb_ir(dst, src_op.disp, dst_op.base, inst->extra.size); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3832 } else { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3833 dst = sbb_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3834 } |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3835 } |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3836 dst = setcc_r(dst, CC_C, FLAG_C); |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
3837 dst = jcc(dst, CC_Z, dst+4); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
3838 dst = mov_ir(dst, 0, FLAG_Z, SZ_B); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3839 dst = setcc_r(dst, CC_S, FLAG_N); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3840 dst = setcc_r(dst, CC_O, FLAG_V); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3841 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3842 dst = m68k_save_result(inst, dst, opts); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3843 break; |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3844 case M68K_SWAP: |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3845 dst = cycles(dst, BUS); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3846 if (src_op.mode == MODE_REG_DIRECT) { |
129 | 3847 dst = rol_ir(dst, 16, src_op.base, SZ_D); |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3848 } else{ |
129 | 3849 dst = rol_irdisp8(dst, 16, src_op.base, src_op.disp, SZ_D); |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3850 } |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3851 dst = mov_ir(dst, 0, FLAG_C, SZ_B); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3852 dst = setcc_r(dst, CC_Z, FLAG_Z); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3853 dst = setcc_r(dst, CC_S, FLAG_N); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3854 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3855 break; |
152
79958b95526f
Implement TRAP (untested)
Mike Pavone <pavone@retrodev.com>
parents:
151
diff
changeset
|
3856 //case M68K_TAS: |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3857 case M68K_TRAP: |
226
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3858 dst = mov_ir(dst, src_op.disp + VECTOR_TRAP_0, SCRATCH2, SZ_D); |
183
2f08d9e90a4c
Fix (a7)+ src when size is byte, fix trap return address, make div with areg src decoded to invalid
Mike Pavone <pavone@retrodev.com>
parents:
182
diff
changeset
|
3859 dst = mov_ir(dst, inst->address+2, SCRATCH1, SZ_D); |
152
79958b95526f
Implement TRAP (untested)
Mike Pavone <pavone@retrodev.com>
parents:
151
diff
changeset
|
3860 dst = jmp(dst, (uint8_t *)m68k_trap); |
79958b95526f
Implement TRAP (untested)
Mike Pavone <pavone@retrodev.com>
parents:
151
diff
changeset
|
3861 break; |
79958b95526f
Implement TRAP (untested)
Mike Pavone <pavone@retrodev.com>
parents:
151
diff
changeset
|
3862 //case M68K_TRAPV: |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3863 case M68K_TST: |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3864 dst = cycles(dst, BUS); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3865 if (src_op.mode == MODE_REG_DIRECT) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3866 dst = cmp_ir(dst, 0, src_op.base, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3867 } else { //M68000 doesn't support immedate operand for tst, so this must be MODE_REG_DISPLACE8 |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3868 dst = cmp_irdisp8(dst, 0, src_op.base, src_op.disp, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3869 } |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
3870 dst = mov_ir(dst, 0, FLAG_C, SZ_B); |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3871 dst = setcc_r(dst, CC_Z, FLAG_Z); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3872 dst = setcc_r(dst, CC_S, FLAG_N); |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
3873 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3874 break; |
78
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
3875 case M68K_UNLK: |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
3876 dst = cycles(dst, BUS); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
3877 if (dst_op.mode == MODE_REG_DIRECT) { |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
3878 dst = mov_rr(dst, dst_op.base, opts->aregs[7], SZ_D); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
3879 } else { |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
3880 dst = mov_rdisp8r(dst, dst_op.base, dst_op.disp, opts->aregs[7], SZ_D); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
3881 } |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
3882 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
3883 dst = call(dst, (uint8_t *)m68k_read_long_scratch1); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
3884 if (dst_op.mode == MODE_REG_DIRECT) { |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
3885 dst = mov_rr(dst, SCRATCH1, dst_op.base, SZ_D); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
3886 } else { |
93
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
3887 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, SZ_D); |
78
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
3888 } |
93
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
3889 dst = add_ir(dst, 4, opts->aregs[7], SZ_D); |
78
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
3890 break; |
70
cebd0b5ac7f0
Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents:
67
diff
changeset
|
3891 default: |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3892 m68k_disasm(inst, disasm_buf); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3893 printf("%X: %s\ninstruction %d not yet implemented\n", inst->address, disasm_buf, inst->op); |
70
cebd0b5ac7f0
Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents:
67
diff
changeset
|
3894 exit(1); |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3895 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3896 return dst; |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3897 } |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3898 |
95
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
3899 uint8_t * translate_m68k_stream(uint32_t address, m68k_context * context) |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3900 { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3901 m68kinst instbuf; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3902 x86_68k_options * opts = context->options; |
95
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
3903 uint8_t * dst = opts->cur_code; |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
3904 uint8_t * dst_end = opts->code_end; |
188
062e3aa549eb
Fix movem.w when dest is register list
Mike Pavone <pavone@retrodev.com>
parents:
187
diff
changeset
|
3905 address &= 0xFFFFFF; |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3906 if(get_native_address(opts->native_code_map, address)) { |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3907 return dst; |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3908 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3909 char disbuf[1024]; |
95
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
3910 uint16_t *encoded, *next; |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
3911 if ((address & 0xFFFFFF) < 0x400000) { |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
3912 encoded = context->mem_pointers[0] + (address & 0xFFFFFF)/2; |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
3913 } else if ((address & 0xFFFFFF) > 0xE00000) { |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
3914 encoded = context->mem_pointers[1] + (address & 0xFFFF)/2; |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
3915 } else { |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
3916 printf("attempt to translate non-memory address: %X\n", address); |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
3917 exit(1); |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
3918 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3919 do { |
197
7c227a8ec53d
Add instruction address logging to translator and support for reading an address log to the disassembler
Mike Pavone <pavone@retrodev.com>
parents:
196
diff
changeset
|
3920 if (opts->address_log) { |
7c227a8ec53d
Add instruction address logging to translator and support for reading an address log to the disassembler
Mike Pavone <pavone@retrodev.com>
parents:
196
diff
changeset
|
3921 fprintf(opts->address_log, "%X\n", address); |
7c227a8ec53d
Add instruction address logging to translator and support for reading an address log to the disassembler
Mike Pavone <pavone@retrodev.com>
parents:
196
diff
changeset
|
3922 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3923 do { |
193
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
3924 if (dst_end-dst < MAX_NATIVE_SIZE) { |
102
bfaca67eeb78
allocate a new native code chunk when we run out of space
Mike Pavone <pavone@retrodev.com>
parents:
100
diff
changeset
|
3925 if (dst_end-dst < 5) { |
bfaca67eeb78
allocate a new native code chunk when we run out of space
Mike Pavone <pavone@retrodev.com>
parents:
100
diff
changeset
|
3926 puts("out of code memory, not enough space for jmp to next chunk"); |
bfaca67eeb78
allocate a new native code chunk when we run out of space
Mike Pavone <pavone@retrodev.com>
parents:
100
diff
changeset
|
3927 exit(1); |
bfaca67eeb78
allocate a new native code chunk when we run out of space
Mike Pavone <pavone@retrodev.com>
parents:
100
diff
changeset
|
3928 } |
bfaca67eeb78
allocate a new native code chunk when we run out of space
Mike Pavone <pavone@retrodev.com>
parents:
100
diff
changeset
|
3929 size_t size = 1024*1024; |
bfaca67eeb78
allocate a new native code chunk when we run out of space
Mike Pavone <pavone@retrodev.com>
parents:
100
diff
changeset
|
3930 opts->cur_code = alloc_code(&size); |
bfaca67eeb78
allocate a new native code chunk when we run out of space
Mike Pavone <pavone@retrodev.com>
parents:
100
diff
changeset
|
3931 opts->code_end = opts->cur_code + size; |
bfaca67eeb78
allocate a new native code chunk when we run out of space
Mike Pavone <pavone@retrodev.com>
parents:
100
diff
changeset
|
3932 jmp(dst, opts->cur_code); |
bfaca67eeb78
allocate a new native code chunk when we run out of space
Mike Pavone <pavone@retrodev.com>
parents:
100
diff
changeset
|
3933 dst = opts->cur_code; |
bfaca67eeb78
allocate a new native code chunk when we run out of space
Mike Pavone <pavone@retrodev.com>
parents:
100
diff
changeset
|
3934 dst_end = opts->code_end; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3935 } |
159
c1530501c215
FIx movem when src is reg list and dst is not a areg predec mode
Mike Pavone <pavone@retrodev.com>
parents:
158
diff
changeset
|
3936 if (address >= 0x400000 && address < 0xE00000) { |
c1530501c215
FIx movem when src is reg list and dst is not a areg predec mode
Mike Pavone <pavone@retrodev.com>
parents:
158
diff
changeset
|
3937 dst = xor_rr(dst, RDI, RDI, SZ_D); |
c1530501c215
FIx movem when src is reg list and dst is not a areg predec mode
Mike Pavone <pavone@retrodev.com>
parents:
158
diff
changeset
|
3938 dst = call(dst, (uint8_t *)exit); |
c1530501c215
FIx movem when src is reg list and dst is not a areg predec mode
Mike Pavone <pavone@retrodev.com>
parents:
158
diff
changeset
|
3939 break; |
c1530501c215
FIx movem when src is reg list and dst is not a areg predec mode
Mike Pavone <pavone@retrodev.com>
parents:
158
diff
changeset
|
3940 } |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
3941 uint8_t * existing = get_native_address(opts->native_code_map, address); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
3942 if (existing) { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
3943 dst = jmp(dst, existing); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
3944 break; |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
3945 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3946 next = m68k_decode(encoded, &instbuf, address); |
208
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
207
diff
changeset
|
3947 if (instbuf.op == M68K_INVALID) { |
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
207
diff
changeset
|
3948 instbuf.src.params.immed = *encoded; |
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
207
diff
changeset
|
3949 } |
192
1db07e112bf7
Prep work for handling games that modify code in RAM
Mike Pavone <pavone@retrodev.com>
parents:
188
diff
changeset
|
3950 uint16_t m68k_size = (next-encoded)*2; |
1db07e112bf7
Prep work for handling games that modify code in RAM
Mike Pavone <pavone@retrodev.com>
parents:
188
diff
changeset
|
3951 address += m68k_size; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3952 encoded = next; |
150
3e68e517cc01
Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed.
Mike Pavone <pavone@retrodev.com>
parents:
146
diff
changeset
|
3953 //m68k_disasm(&instbuf, disbuf); |
3e68e517cc01
Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed.
Mike Pavone <pavone@retrodev.com>
parents:
146
diff
changeset
|
3954 //printf("%X: %s\n", instbuf.address, disbuf); |
192
1db07e112bf7
Prep work for handling games that modify code in RAM
Mike Pavone <pavone@retrodev.com>
parents:
188
diff
changeset
|
3955 uint8_t * after = translate_m68k(dst, &instbuf, opts); |
1db07e112bf7
Prep work for handling games that modify code in RAM
Mike Pavone <pavone@retrodev.com>
parents:
188
diff
changeset
|
3956 map_native_address(context, instbuf.address, dst, m68k_size, after-dst); |
1db07e112bf7
Prep work for handling games that modify code in RAM
Mike Pavone <pavone@retrodev.com>
parents:
188
diff
changeset
|
3957 dst = after; |
216
0b5ec22dcda2
Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source.
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
3958 } while(instbuf.op != M68K_ILLEGAL && instbuf.op != M68K_RESET && instbuf.op != M68K_INVALID && instbuf.op != M68K_TRAP && instbuf.op != M68K_RTS && instbuf.op != M68K_RTR && instbuf.op != M68K_RTE && !(instbuf.op == M68K_BCC && instbuf.extra.cond == COND_TRUE) && instbuf.op != M68K_JMP); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3959 process_deferred(opts); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3960 if (opts->deferred) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3961 address = opts->deferred->address; |
124
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
3962 if ((address & 0xFFFFFF) < 0x400000) { |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
3963 encoded = context->mem_pointers[0] + (address & 0xFFFFFF)/2; |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
3964 } else if ((address & 0xFFFFFF) > 0xE00000) { |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
3965 encoded = context->mem_pointers[1] + (address & 0xFFFF)/2; |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
3966 } else { |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
3967 printf("attempt to translate non-memory address: %X\n", address); |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
3968 exit(1); |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
3969 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3970 } else { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3971 encoded = NULL; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3972 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3973 } while(encoded != NULL); |
95
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
3974 opts->cur_code = dst; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3975 return dst; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3976 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3977 |
95
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
3978 uint8_t * get_native_address_trans(m68k_context * context, uint32_t address) |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
3979 { |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
3980 address &= 0xFFFFFF; |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
3981 uint8_t * ret = get_native_address(context->native_code_map, address); |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
3982 if (!ret) { |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
3983 translate_m68k_stream(address, context); |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
3984 ret = get_native_address(context->native_code_map, address); |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
3985 } |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
3986 return ret; |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
3987 } |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
3988 |
193
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
3989 void * m68k_retranslate_inst(uint32_t address, m68k_context * context) |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
3990 { |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
3991 x86_68k_options * opts = context->options; |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
3992 uint8_t orig_size = get_native_inst_size(opts, address); |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
3993 uint8_t * orig_start = get_native_address(context->native_code_map, address); |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
3994 uint32_t orig = address; |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
3995 address &= 0xFFFF; |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
3996 uint8_t * dst = opts->cur_code; |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
3997 uint8_t * dst_end = opts->code_end; |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
3998 uint16_t *after, *inst = context->mem_pointers[1] + address/2; |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
3999 m68kinst instbuf; |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4000 after = m68k_decode(inst, &instbuf, orig); |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4001 if (orig_size != MAX_NATIVE_SIZE) { |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4002 if (dst_end - dst < 128) { |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4003 size_t size = 1024*1024; |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4004 dst = alloc_code(&size); |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4005 opts->code_end = dst_end = dst + size; |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4006 opts->cur_code = dst; |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4007 } |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4008 uint8_t * native_end = translate_m68k(dst, &instbuf, opts); |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4009 if ((native_end - dst) <= orig_size) { |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4010 native_end = translate_m68k(orig_start, &instbuf, opts); |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4011 while (native_end < orig_start + orig_size) { |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4012 *(native_end++) = 0x90; //NOP |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4013 } |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4014 return orig_start; |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4015 } else { |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4016 map_native_address(context, instbuf.address, dst, (after-inst)*2, MAX_NATIVE_SIZE); |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4017 opts->code_end = dst+MAX_NATIVE_SIZE; |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4018 if (instbuf.op != M68K_RTS && instbuf.op != M68K_RTE && instbuf.op != M68K_RTR && instbuf.op != M68K_JMP && (instbuf.op != M68K_BCC || instbuf.extra.cond != COND_TRUE)) { |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4019 jmp(native_end, get_native_address(context->native_code_map, address + (after-inst)*2)); |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4020 } |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4021 return dst; |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4022 } |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4023 } else { |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4024 dst = translate_m68k(orig_start, &instbuf, opts); |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4025 if (instbuf.op != M68K_RTS && instbuf.op != M68K_RTE && instbuf.op != M68K_RTR && instbuf.op != M68K_JMP && (instbuf.op != M68K_BCC || instbuf.extra.cond != COND_TRUE)) { |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4026 dst = jmp(dst, get_native_address(context->native_code_map, address + (after-inst)*2)); |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4027 } |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4028 return orig_start; |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4029 } |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4030 } |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4031 |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4032 m68k_context * m68k_handle_code_write(uint32_t address, m68k_context * context) |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4033 { |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4034 uint32_t inst_start = get_instruction_start(context->native_code_map, address | 0xFF0000); |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4035 if (inst_start) { |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4036 uint8_t * dst = get_native_address(context->native_code_map, inst_start); |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4037 dst = mov_ir(dst, inst_start, SCRATCH2, SZ_D); |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4038 dst = jmp(dst, (uint8_t *)m68k_retrans_stub); |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4039 } |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4040 return context; |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4041 } |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4042 |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4043 void insert_breakpoint(m68k_context * context, uint32_t address, uint8_t * bp_handler) |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4044 { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4045 static uint8_t * bp_stub = NULL; |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4046 uint8_t * native = get_native_address_trans(context, address); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4047 uint8_t * start_native = native; |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4048 native = mov_ir(native, address, SCRATCH1, SZ_D); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4049 if (!bp_stub) { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4050 x86_68k_options * opts = context->options; |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4051 uint8_t * dst = opts->cur_code; |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4052 uint8_t * dst_end = opts->code_end; |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4053 if (dst_end - dst < 128) { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4054 size_t size = 1024*1024; |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4055 dst = alloc_code(&size); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4056 opts->code_end = dst_end = dst + size; |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4057 } |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4058 bp_stub = dst; |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4059 native = call(native, bp_stub); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4060 |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4061 //Calculate length of prologue |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4062 dst = check_cycles_int(dst, address); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4063 int check_int_size = dst-bp_stub; |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4064 dst = bp_stub; |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4065 |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4066 //Save context and call breakpoint handler |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4067 dst = call(dst, (uint8_t *)m68k_save_context); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4068 dst = push_r(dst, SCRATCH1); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4069 dst = mov_rr(dst, CONTEXT, RDI, SZ_Q); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4070 dst = mov_rr(dst, SCRATCH1, RSI, SZ_D); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4071 dst = call(dst, bp_handler); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4072 dst = mov_rr(dst, RAX, CONTEXT, SZ_Q); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4073 //Restore context |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4074 dst = call(dst, (uint8_t *)m68k_load_context); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4075 dst = pop_r(dst, SCRATCH1); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4076 //do prologue stuff |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4077 dst = cmp_rr(dst, CYCLES, LIMIT, SZ_D); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4078 uint8_t * jmp_off = dst+1; |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4079 dst = jcc(dst, CC_NC, dst + 7); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4080 dst = call(dst, (uint8_t *)handle_cycle_limit_int); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4081 *jmp_off = dst - (jmp_off+1); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4082 //jump back to body of translated instruction |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4083 dst = pop_r(dst, SCRATCH1); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4084 dst = add_ir(dst, check_int_size - (native-start_native), SCRATCH1, SZ_Q); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4085 dst = jmp_r(dst, SCRATCH1); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4086 opts->cur_code = dst; |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4087 } else { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4088 native = call(native, bp_stub); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4089 } |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4090 } |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4091 |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4092 void remove_breakpoint(m68k_context * context, uint32_t address) |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4093 { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4094 uint8_t * native = get_native_address(context->native_code_map, address); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4095 check_cycles_int(native, address); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4096 } |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4097 |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4098 void start_68k_context(m68k_context * context, uint32_t address) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4099 { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4100 uint8_t * addr = get_native_address(context->native_code_map, address); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4101 m68k_start_context(addr, context); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4102 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4103 |
19
4717146a7606
Initial support for M68k reset vector, rather than starting at an arbitrary address
Mike Pavone <pavone@retrodev.com>
parents:
18
diff
changeset
|
4104 void m68k_reset(m68k_context * context) |
4717146a7606
Initial support for M68k reset vector, rather than starting at an arbitrary address
Mike Pavone <pavone@retrodev.com>
parents:
18
diff
changeset
|
4105 { |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
4106 //TODO: Make this actually use the normal read functions |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
4107 context->aregs[7] = context->mem_pointers[0][0] << 16 | context->mem_pointers[0][1]; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
4108 uint32_t address = context->mem_pointers[0][2] << 16 | context->mem_pointers[0][3]; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
4109 start_68k_context(context, address); |
19
4717146a7606
Initial support for M68k reset vector, rather than starting at an arbitrary address
Mike Pavone <pavone@retrodev.com>
parents:
18
diff
changeset
|
4110 } |
4717146a7606
Initial support for M68k reset vector, rather than starting at an arbitrary address
Mike Pavone <pavone@retrodev.com>
parents:
18
diff
changeset
|
4111 |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4112 void init_x86_68k_opts(x86_68k_options * opts) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4113 { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4114 opts->flags = 0; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4115 for (int i = 0; i < 8; i++) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4116 opts->dregs[i] = opts->aregs[i] = -1; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4117 opts->dregs[0] = R10; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4118 opts->dregs[1] = R11; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4119 opts->dregs[2] = R12; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4120 opts->aregs[0] = R13; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4121 opts->aregs[1] = R14; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4122 opts->aregs[7] = R15; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4123 opts->native_code_map = malloc(sizeof(native_map_slot) * NATIVE_MAP_CHUNKS); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4124 memset(opts->native_code_map, 0, sizeof(native_map_slot) * NATIVE_MAP_CHUNKS); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4125 opts->deferred = NULL; |
95
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
4126 size_t size = 1024 * 1024; |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
4127 opts->cur_code = alloc_code(&size); |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
4128 opts->code_end = opts->cur_code + size; |
192
1db07e112bf7
Prep work for handling games that modify code in RAM
Mike Pavone <pavone@retrodev.com>
parents:
188
diff
changeset
|
4129 opts->ram_inst_sizes = malloc(sizeof(uint8_t *) * 64); |
193
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4130 memset(opts->ram_inst_sizes, 0, sizeof(uint8_t *) * 64); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4131 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4132 |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4133 void init_68k_context(m68k_context * context, native_map_slot * native_code_map, void * opts) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4134 { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4135 memset(context, 0, sizeof(m68k_context)); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4136 context->native_code_map = native_code_map; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4137 context->options = opts; |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
4138 context->int_cycle = 0xFFFFFFFF; |
167
f6c7fea1ecf7
Initialize status register to proper value on startup
Mike Pavone <pavone@retrodev.com>
parents:
165
diff
changeset
|
4139 context->status = 0x27; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4140 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4141 |