Mercurial > repos > blastem
annotate segacd.h @ 2055:c4d066d798c4 segacd
Fix prog RAM banking and Genesis to SCD cycle conversion. Arkagis Escape demo now works
author | Michael Pavone <pavone@retrodev.com> |
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date | Tue, 18 Jan 2022 23:54:02 -0800 |
parents | 8ee7ecbf3f21 |
children | 70260f6051dd |
rev | line source |
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Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
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1 #ifndef SEGACD_H_ |
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Michael Pavone <pavone@retrodev.com>
parents:
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2 #define SEGACD_H_ |
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parents:
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3 #include <stdint.h> |
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8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1503
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4 #include "genesis.h" |
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Michael Pavone <pavone@retrodev.com>
parents:
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5 |
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Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
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6 typedef struct { |
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Michael Pavone <pavone@retrodev.com>
parents:
1503
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7 m68k_context *m68k; |
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Michael Pavone <pavone@retrodev.com>
parents:
1503
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8 system_media *media; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1503
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9 genesis_context *genesis; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1503
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10 uint16_t gate_array[0x100]; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1503
diff
changeset
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11 uint16_t *rom; //unaltered ROM, needed for mirrored locations |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1503
diff
changeset
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12 uint16_t *rom_mut; //ROM with low 16-bit of HINT vector modified by register write |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1503
diff
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13 uint16_t *prog_ram; |
8ee7ecbf3f21
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Michael Pavone <pavone@retrodev.com>
parents:
1503
diff
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14 uint16_t *word_ram; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1503
diff
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15 uint8_t *pcm_ram; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1503
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16 uint8_t *bram; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1503
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changeset
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17 uint32_t stopwatch_cycle; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1503
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18 uint32_t int2_cycle; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1503
diff
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19 uint32_t periph_reset_cycle; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1503
diff
changeset
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20 uint32_t base; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1503
diff
changeset
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21 uint8_t timer_pending; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1503
diff
changeset
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22 uint8_t timer_value; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1503
diff
changeset
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23 uint8_t busreq; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1503
diff
changeset
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24 uint8_t busack; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1503
diff
changeset
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25 uint8_t reset; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1503
diff
changeset
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26 uint8_t need_reset; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1503
diff
changeset
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27 uint8_t memptr_start_index; |
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2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
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28 } segacd_context; |
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Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
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29 |
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Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
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diff
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30 segacd_context *alloc_configure_segacd(system_media *media, uint32_t opts, uint8_t force_region, rom_info *info); |
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Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1503
diff
changeset
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31 memmap_chunk *segacd_main_cpu_map(segacd_context *cd, uint8_t cart_boot, uint32_t *num_chunks); |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1503
diff
changeset
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32 uint32_t gen_cycle_to_scd(uint32_t cycle, genesis_context *gen); |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1503
diff
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33 void scd_run(segacd_context *cd, uint32_t cycle); |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1503
diff
changeset
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34 void scd_adjust_cycle(segacd_context *cd, uint32_t deduction); |
1502
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
35 |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
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36 #endif //SEGACD_H_ |