Mercurial > repos > blastem
annotate z80_to_x86.c @ 274:be2b845d3e94
Implement CPL and NEG (untested)
author | Mike Pavone <pavone@retrodev.com> |
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date | Thu, 02 May 2013 22:39:39 -0700 |
parents | 719b9fea2fe9 |
children | 1a7d0a964ad2 |
rev | line source |
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1 #include "z80inst.h" |
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2 #include "z80_to_x86.h" |
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3 #include "gen_x86.h" |
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4 #include "mem.h" |
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5 #include <stdio.h> |
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6 #include <stdlib.h> |
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7 #include <stddef.h> |
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8 #include <string.h> |
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9 |
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10 #define MODE_UNUSED (MODE_IMMED-1) |
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11 |
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12 #define ZCYCLES RBP |
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13 #define ZLIMIT RDI |
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14 #define SCRATCH1 R13 |
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15 #define SCRATCH2 R14 |
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16 #define CONTEXT RSI |
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17 |
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18 #ifdef DO_DEBUG_PRINT |
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19 #define dprintf printf |
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20 #else |
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21 #define dprintf |
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22 #endif |
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23 |
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24 void z80_read_byte(); |
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25 void z80_read_word(); |
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26 void z80_write_byte(); |
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27 void z80_write_word_highfirst(); |
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28 void z80_write_word_lowfirst(); |
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29 void z80_save_context(); |
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30 void z80_native_addr(); |
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31 void z80_do_sync(); |
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32 void z80_handle_cycle_limit_int(); |
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33 void z80_retrans_stub(); |
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34 |
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35 uint8_t z80_size(z80inst * inst) |
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36 { |
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37 uint8_t reg = (inst->reg & 0x1F); |
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38 if (reg != Z80_UNUSED && reg != Z80_USE_IMMED) { |
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39 return reg < Z80_BC ? SZ_B : SZ_W; |
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40 } |
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41 //TODO: Handle any necessary special cases |
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42 return SZ_B; |
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43 } |
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44 |
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45 uint8_t z80_high_reg(uint8_t reg) |
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46 { |
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47 switch(reg) |
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48 { |
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49 case Z80_C: |
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50 case Z80_BC: |
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51 return Z80_B; |
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52 case Z80_E: |
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53 case Z80_DE: |
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54 return Z80_D; |
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55 case Z80_L: |
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56 case Z80_HL: |
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57 return Z80_H; |
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58 case Z80_IXL: |
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59 case Z80_IX: |
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60 return Z80_IXH; |
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61 case Z80_IYL: |
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62 case Z80_IY: |
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63 return Z80_IYH; |
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64 default: |
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65 return Z80_UNUSED; |
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66 } |
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67 } |
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68 |
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69 uint8_t z80_low_reg(uint8_t reg) |
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70 { |
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71 switch(reg) |
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72 { |
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73 case Z80_B: |
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74 case Z80_BC: |
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75 return Z80_C; |
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76 case Z80_D: |
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77 case Z80_DE: |
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78 return Z80_E; |
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79 case Z80_H: |
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80 case Z80_HL: |
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81 return Z80_L; |
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82 case Z80_IXH: |
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83 case Z80_IX: |
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84 return Z80_IXL; |
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85 case Z80_IYH: |
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86 case Z80_IY: |
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87 return Z80_IYL; |
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88 default: |
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89 return Z80_UNUSED; |
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90 } |
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91 } |
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92 |
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93 uint8_t * zcycles(uint8_t * dst, uint32_t num_cycles) |
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94 { |
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95 return add_ir(dst, num_cycles, ZCYCLES, SZ_D); |
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96 } |
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97 |
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98 uint8_t * z80_check_cycles_int(uint8_t * dst, uint16_t address) |
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99 { |
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100 dst = cmp_rr(dst, ZCYCLES, ZLIMIT, SZ_D); |
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101 uint8_t * jmp_off = dst+1; |
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102 dst = jcc(dst, CC_NC, dst + 7); |
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103 dst = mov_ir(dst, address, SCRATCH1, SZ_W); |
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104 dst = call(dst, (uint8_t *)z80_handle_cycle_limit_int); |
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105 *jmp_off = dst - (jmp_off+1); |
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106 return dst; |
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107 } |
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108 |
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109 uint8_t * translate_z80_reg(z80inst * inst, x86_ea * ea, uint8_t * dst, x86_z80_options * opts) |
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110 { |
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111 if (inst->reg == Z80_USE_IMMED) { |
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112 ea->mode = MODE_IMMED; |
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113 ea->disp = inst->immed; |
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114 } else if ((inst->reg & 0x1F) == Z80_UNUSED) { |
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115 ea->mode = MODE_UNUSED; |
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116 } else { |
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117 ea->mode = MODE_REG_DIRECT; |
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118 if (inst->reg == Z80_IYH) { |
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119 ea->base = opts->regs[Z80_IYL]; |
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120 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W); |
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121 } else if(opts->regs[inst->reg] >= 0) { |
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122 ea->base = opts->regs[inst->reg]; |
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123 if (ea->base >= AH && ea->base <= BH) { |
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124 if ((inst->addr_mode & 0x1F) == Z80_REG) { |
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125 uint8_t other_reg = opts->regs[inst->ea_reg]; |
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126 if (other_reg >= R8 || (other_reg >= RSP && other_reg <= RDI)) { |
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127 //we can't mix an *H reg with a register that requires the REX prefix |
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128 ea->base = opts->regs[z80_low_reg(inst->reg)]; |
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129 dst = ror_ir(dst, 8, ea->base, SZ_W); |
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130 } |
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131 } else if((inst->addr_mode & 0x1F) != Z80_UNUSED && (inst->addr_mode & 0x1F) != Z80_IMMED) { |
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132 //temp regs require REX prefix too |
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133 ea->base = opts->regs[z80_low_reg(inst->reg)]; |
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134 dst = ror_ir(dst, 8, ea->base, SZ_W); |
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135 } |
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136 } |
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137 } else { |
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138 ea->mode = MODE_REG_DISPLACE8; |
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139 ea->base = CONTEXT; |
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140 ea->disp = offsetof(z80_context, regs) + inst->reg; |
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141 } |
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142 } |
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143 return dst; |
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144 } |
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145 |
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146 uint8_t * z80_save_reg(uint8_t * dst, z80inst * inst, x86_z80_options * opts) |
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147 { |
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148 if (inst->reg == Z80_IYH) { |
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149 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W); |
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150 } else if (opts->regs[inst->reg] >= AH && opts->regs[inst->reg] <= BH) { |
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151 if ((inst->addr_mode & 0x1F) == Z80_REG) { |
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152 uint8_t other_reg = opts->regs[inst->ea_reg]; |
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153 if (other_reg >= R8 || (other_reg >= RSP && other_reg <= RDI)) { |
268
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154 //we can't mix an *H reg with a register that requires the REX prefix |
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155 dst = ror_ir(dst, 8, opts->regs[z80_low_reg(inst->reg)], SZ_W); |
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156 } |
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157 } else if((inst->addr_mode & 0x1F) != Z80_UNUSED && (inst->addr_mode & 0x1F) != Z80_IMMED) { |
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158 //temp regs require REX prefix too |
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159 dst = ror_ir(dst, 8, opts->regs[z80_low_reg(inst->reg)], SZ_W); |
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160 } |
213
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161 } |
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162 return dst; |
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163 } |
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164 |
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165 uint8_t * translate_z80_ea(z80inst * inst, x86_ea * ea, uint8_t * dst, x86_z80_options * opts, uint8_t read, uint8_t modify) |
213
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166 { |
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167 uint8_t size, reg, areg; |
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168 ea->mode = MODE_REG_DIRECT; |
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169 areg = read ? SCRATCH1 : SCRATCH2; |
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170 switch(inst->addr_mode & 0x1F) |
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171 { |
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172 case Z80_REG: |
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173 if (inst->ea_reg == Z80_IYH) { |
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174 ea->base = opts->regs[Z80_IYL]; |
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175 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W); |
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176 } else { |
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177 ea->base = opts->regs[inst->ea_reg]; |
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178 if (ea->base >= AH && ea->base <= BH && inst->reg != Z80_UNUSED && inst->reg != Z80_USE_IMMED) { |
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179 uint8_t other_reg = opts->regs[inst->reg]; |
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180 if (other_reg >= R8 || (other_reg >= RSP && other_reg <= RDI)) { |
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181 //we can't mix an *H reg with a register that requires the REX prefix |
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182 ea->base = opts->regs[z80_low_reg(inst->ea_reg)]; |
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183 dst = ror_ir(dst, 8, ea->base, SZ_W); |
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184 } |
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185 } |
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186 } |
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187 break; |
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188 case Z80_REG_INDIRECT: |
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189 dst = mov_rr(dst, opts->regs[inst->ea_reg], areg, SZ_W); |
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190 size = z80_size(inst); |
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191 if (read) { |
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192 if (modify) { |
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193 dst = push_r(dst, SCRATCH1); |
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194 } |
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195 if (size == SZ_B) { |
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196 dst = call(dst, (uint8_t *)z80_read_byte); |
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197 } else { |
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198 dst = call(dst, (uint8_t *)z80_read_word); |
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199 } |
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200 if (modify) { |
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201 dst = pop_r(dst, SCRATCH2); |
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202 } |
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203 } |
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204 ea->base = SCRATCH1; |
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205 break; |
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206 case Z80_IMMED: |
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207 ea->mode = MODE_IMMED; |
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208 ea->disp = inst->immed; |
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209 break; |
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210 case Z80_IMMED_INDIRECT: |
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211 dst = mov_ir(dst, inst->immed, areg, SZ_W); |
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212 size = z80_size(inst); |
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213 if (read) { |
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214 if (modify) { |
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215 dst = push_r(dst, SCRATCH1); |
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216 } |
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217 if (size == SZ_B) { |
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218 dst = call(dst, (uint8_t *)z80_read_byte); |
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219 } else { |
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220 dst = call(dst, (uint8_t *)z80_read_word); |
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221 } |
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222 if (modify) { |
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223 dst = pop_r(dst, SCRATCH2); |
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224 } |
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225 } |
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226 ea->base = SCRATCH1; |
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227 break; |
235
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228 case Z80_IX_DISPLACE: |
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229 case Z80_IY_DISPLACE: |
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230 reg = opts->regs[inst->addr_mode == Z80_IX_DISPLACE ? Z80_IX : Z80_IY]; |
213
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231 dst = mov_rr(dst, reg, areg, SZ_W); |
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232 dst = add_ir(dst, inst->immed, areg, SZ_W); |
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233 size = z80_size(inst); |
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234 if (read) { |
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235 if (modify) { |
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236 dst = push_r(dst, SCRATCH1); |
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237 } |
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238 if (size == SZ_B) { |
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239 dst = call(dst, (uint8_t *)z80_read_byte); |
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240 } else { |
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241 dst = call(dst, (uint8_t *)z80_read_word); |
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242 } |
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243 if (modify) { |
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244 dst = pop_r(dst, SCRATCH2); |
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245 } |
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246 } |
269
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247 ea->base = SCRATCH1; |
213
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248 break; |
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249 case Z80_UNUSED: |
235
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250 ea->mode = MODE_UNUSED; |
213
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251 break; |
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252 default: |
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253 fprintf(stderr, "Unrecognized Z80 addressing mode %d\n", inst->addr_mode); |
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254 exit(1); |
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255 } |
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256 return dst; |
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257 } |
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258 |
235
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259 uint8_t * z80_save_ea(uint8_t * dst, z80inst * inst, x86_z80_options * opts) |
213
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260 { |
267
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261 if ((inst->addr_mode & 0x1F) == Z80_REG) { |
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262 if (inst->ea_reg == Z80_IYH) { |
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263 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W); |
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264 } else if (inst->reg != Z80_UNUSED && inst->reg != Z80_USE_IMMED && opts->regs[inst->ea_reg] >= AH && opts->regs[inst->ea_reg] <= BH) { |
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265 uint8_t other_reg = opts->regs[inst->reg]; |
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266 if (other_reg >= R8 || (other_reg >= RSP && other_reg <= RDI)) { |
267
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267 //we can't mix an *H reg with a register that requires the REX prefix |
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268 dst = ror_ir(dst, 8, opts->regs[z80_low_reg(inst->ea_reg)], SZ_W); |
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269 } |
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270 } |
213
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271 } |
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272 return dst; |
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273 } |
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274 |
235
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275 uint8_t * z80_save_result(uint8_t * dst, z80inst * inst) |
213
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276 { |
253
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277 switch(inst->addr_mode & 0x1f) |
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278 { |
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279 case Z80_REG_INDIRECT: |
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280 case Z80_IMMED_INDIRECT: |
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281 case Z80_IX_DISPLACE: |
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282 case Z80_IY_DISPLACE: |
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283 if (z80_size(inst) == SZ_B) { |
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284 dst = call(dst, (uint8_t *)z80_write_byte); |
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285 } else { |
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286 dst = call(dst, (uint8_t *)z80_write_word_lowfirst); |
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287 } |
213
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288 } |
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289 return dst; |
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290 } |
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291 |
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292 enum { |
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293 DONT_READ=0, |
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294 READ |
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295 }; |
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296 |
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297 enum { |
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298 DONT_MODIFY=0, |
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299 MODIFY |
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300 }; |
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301 |
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302 uint8_t zf_off(uint8_t flag) |
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303 { |
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304 return offsetof(z80_context, flags) + flag; |
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305 } |
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306 |
241
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307 uint8_t zaf_off(uint8_t flag) |
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308 { |
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309 return offsetof(z80_context, alt_flags) + flag; |
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310 } |
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311 |
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312 uint8_t zar_off(uint8_t reg) |
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313 { |
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314 return offsetof(z80_context, alt_regs) + reg; |
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315 } |
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316 |
235
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317 void z80_print_regs_exit(z80_context * context) |
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318 { |
243
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319 printf("A: %X\nB: %X\nC: %X\nD: %X\nE: %X\nHL: %X\nIX: %X\nIY: %X\nSP: %X\n\nIM: %d, IFF1: %d, IFF2: %d\n", |
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320 context->regs[Z80_A], context->regs[Z80_B], context->regs[Z80_C], |
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321 context->regs[Z80_D], context->regs[Z80_E], |
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322 (context->regs[Z80_H] << 8) | context->regs[Z80_L], |
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323 (context->regs[Z80_IXH] << 8) | context->regs[Z80_IXL], |
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324 (context->regs[Z80_IYH] << 8) | context->regs[Z80_IYL], |
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325 context->sp, context->im, context->iff1, context->iff2); |
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326 puts("--Alternate Regs--"); |
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327 printf("A: %X\nB: %X\nC: %X\nD: %X\nE: %X\nHL: %X\nIX: %X\nIY: %X\n", |
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328 context->alt_regs[Z80_A], context->alt_regs[Z80_B], context->alt_regs[Z80_C], |
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329 context->alt_regs[Z80_D], context->alt_regs[Z80_E], |
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330 (context->alt_regs[Z80_H] << 8) | context->alt_regs[Z80_L], |
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331 (context->alt_regs[Z80_IXH] << 8) | context->alt_regs[Z80_IXL], |
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332 (context->alt_regs[Z80_IYH] << 8) | context->alt_regs[Z80_IYL]); |
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333 exit(0); |
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334 } |
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335 |
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336 uint8_t * translate_z80inst(z80inst * inst, uint8_t * dst, z80_context * context, uint16_t address) |
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337 { |
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338 uint32_t cycles; |
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339 x86_ea src_op, dst_op; |
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340 uint8_t size; |
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341 x86_z80_options *opts = context->options; |
261
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342 uint8_t * start = dst; |
250
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343 dst = z80_check_cycles_int(dst, address); |
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344 switch(inst->op) |
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345 { |
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346 case Z80_LD: |
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347 size = z80_size(inst); |
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348 switch (inst->addr_mode & 0x1F) |
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349 { |
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350 case Z80_REG: |
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351 case Z80_REG_INDIRECT: |
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352 cycles = size == SZ_B ? 4 : 6; |
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353 if (inst->ea_reg == Z80_IX || inst->ea_reg == Z80_IY) { |
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354 cycles += 4; |
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355 } |
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356 break; |
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357 case Z80_IMMED: |
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358 cycles = size == SZ_B ? 7 : 10; |
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359 break; |
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360 case Z80_IMMED_INDIRECT: |
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361 cycles = 10; |
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362 break; |
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363 case Z80_IX_DISPLACE: |
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364 case Z80_IY_DISPLACE: |
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365 cycles = 12; |
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366 break; |
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367 } |
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368 if ((inst->reg >= Z80_IXL && inst->reg <= Z80_IYH) || inst->reg == Z80_IX || inst->reg == Z80_IY) { |
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369 cycles += 4; |
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370 } |
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371 dst = zcycles(dst, cycles); |
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372 if (inst->addr_mode & Z80_DIR) { |
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373 dst = translate_z80_reg(inst, &src_op, dst, opts); |
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374 dst = translate_z80_ea(inst, &dst_op, dst, opts, DONT_READ, MODIFY); |
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375 } else { |
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376 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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377 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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378 } |
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379 if (src_op.mode == MODE_REG_DIRECT) { |
262
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380 if(dst_op.mode == MODE_REG_DISPLACE8) { |
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381 dst = mov_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, size); |
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382 } else { |
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383 dst = mov_rr(dst, src_op.base, dst_op.base, size); |
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384 } |
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385 } else if(src_op.mode == MODE_IMMED) { |
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386 dst = mov_ir(dst, src_op.disp, dst_op.base, size); |
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387 } else { |
262
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388 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, size); |
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389 } |
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390 dst = z80_save_reg(dst, inst, opts); |
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391 dst = z80_save_ea(dst, inst, opts); |
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392 if (inst->addr_mode & Z80_DIR) { |
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393 dst = z80_save_result(dst, inst); |
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394 } |
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395 break; |
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396 case Z80_PUSH: |
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397 dst = zcycles(dst, (inst->reg == Z80_IX || inst->reg == Z80_IY) ? 9 : 5); |
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398 dst = sub_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
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399 if (inst->reg == Z80_AF) { |
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400 dst = mov_rdisp8r(dst, CONTEXT, zf_off(ZF_S), SCRATCH1, SZ_B); |
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401 dst = shl_ir(dst, 1, SCRATCH1, SZ_B); |
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402 dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_Z), SCRATCH1, SZ_B); |
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403 dst = shl_ir(dst, 2, SCRATCH1, SZ_B); |
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404 dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_H), SCRATCH1, SZ_B); |
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405 dst = shl_ir(dst, 2, SCRATCH1, SZ_B); |
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406 dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_PV), SCRATCH1, SZ_B); |
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407 dst = shl_ir(dst, 1, SCRATCH1, SZ_B); |
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408 dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_N), SCRATCH1, SZ_B); |
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409 dst = shl_ir(dst, 1, SCRATCH1, SZ_B); |
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410 dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_C), SCRATCH1, SZ_B); |
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411 dst = shl_ir(dst, 8, SCRATCH1, SZ_W); |
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412 dst = mov_rr(dst, opts->regs[Z80_A], SCRATCH1, SZ_B); |
235
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413 } else { |
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414 dst = translate_z80_reg(inst, &src_op, dst, opts); |
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415 dst = mov_rr(dst, src_op.base, SCRATCH1, SZ_W); |
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416 } |
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417 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W); |
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418 dst = call(dst, (uint8_t *)z80_write_word_highfirst); |
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419 //no call to save_z80_reg needed since there's no chance we'll use the only |
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420 //the upper half of a register pair |
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421 break; |
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422 case Z80_POP: |
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423 dst = zcycles(dst, (inst->reg == Z80_IX || inst->reg == Z80_IY) ? 8 : 4); |
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424 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
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425 dst = call(dst, (uint8_t *)z80_read_word); |
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426 dst = add_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
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427 if (inst->reg == Z80_AF) { |
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428 dst = mov_rr(dst, SCRATCH1, opts->regs[Z80_A], SZ_B); |
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429 dst = bt_ir(dst, 8, SCRATCH1, SZ_W); |
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430 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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431 dst = bt_ir(dst, 9, SCRATCH1, SZ_W); |
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432 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_N)); |
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433 dst = bt_ir(dst, 10, SCRATCH1, SZ_W); |
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434 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_PV)); |
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435 dst = bt_ir(dst, 12, SCRATCH1, SZ_W); |
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436 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_H)); |
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437 dst = bt_ir(dst, 14, SCRATCH1, SZ_W); |
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438 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_Z)); |
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439 dst = bt_ir(dst, 15, SCRATCH1, SZ_W); |
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440 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_S)); |
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441 } else { |
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442 dst = translate_z80_reg(inst, &src_op, dst, opts); |
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443 dst = mov_rr(dst, SCRATCH1, src_op.base, SZ_W); |
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444 } |
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445 //no call to save_z80_reg needed since there's no chance we'll use the only |
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446 //the upper half of a register pair |
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447 break; |
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448 case Z80_EX: |
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449 if (inst->addr_mode == Z80_REG || inst->reg == Z80_HL) { |
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450 cycles = 4; |
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451 } else { |
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452 cycles = 8; |
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453 } |
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454 dst = zcycles(dst, cycles); |
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455 if (inst->addr_mode == Z80_REG) { |
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456 if(inst->reg == Z80_AF) { |
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457 dst = mov_rr(dst, opts->regs[Z80_A], SCRATCH1, SZ_B); |
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458 dst = mov_rdisp8r(dst, CONTEXT, zar_off(Z80_A), opts->regs[Z80_A], SZ_B); |
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459 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, zar_off(Z80_A), SZ_B); |
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460 |
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461 //Flags are currently word aligned, so we can move |
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462 //them efficiently a word at a time |
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463 for (int f = ZF_C; f < ZF_NUM; f+=2) { |
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464 dst = mov_rdisp8r(dst, CONTEXT, zf_off(f), SCRATCH1, SZ_W); |
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465 dst = mov_rdisp8r(dst, CONTEXT, zaf_off(f), SCRATCH2, SZ_W); |
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466 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, zaf_off(f), SZ_W); |
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467 dst = mov_rrdisp8(dst, SCRATCH2, CONTEXT, zf_off(f), SZ_W); |
241
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468 } |
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469 } else { |
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470 dst = xchg_rr(dst, opts->regs[Z80_DE], opts->regs[Z80_HL], SZ_W); |
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471 } |
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472 } else { |
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473 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
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474 dst = call(dst, (uint8_t *)z80_read_byte); |
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475 dst = xchg_rr(dst, opts->regs[inst->reg], SCRATCH1, SZ_B); |
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476 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W); |
241
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477 dst = call(dst, (uint8_t *)z80_write_byte); |
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478 dst = zcycles(dst, 1); |
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479 uint8_t high_reg = z80_high_reg(inst->reg); |
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480 uint8_t use_reg; |
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481 //even though some of the upper halves can be used directly |
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482 //the limitations on mixing *H regs with the REX prefix |
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483 //prevent us from taking advantage of it |
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484 use_reg = opts->regs[inst->reg]; |
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485 dst = ror_ir(dst, 8, use_reg, SZ_W); |
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486 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
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487 dst = add_ir(dst, 1, SCRATCH1, SZ_W); |
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488 dst = call(dst, (uint8_t *)z80_read_byte); |
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489 dst = xchg_rr(dst, use_reg, SCRATCH1, SZ_B); |
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490 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W); |
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491 dst = add_ir(dst, 1, SCRATCH2, SZ_W); |
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492 dst = call(dst, (uint8_t *)z80_write_byte); |
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493 //restore reg to normal rotation |
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494 dst = ror_ir(dst, 8, use_reg, SZ_W); |
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495 dst = zcycles(dst, 2); |
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496 } |
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497 break; |
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498 case Z80_EXX: |
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499 dst = zcycles(dst, 4); |
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500 dst = mov_rr(dst, opts->regs[Z80_BC], SCRATCH1, SZ_W); |
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501 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH2, SZ_W); |
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502 dst = mov_rdisp8r(dst, CONTEXT, zar_off(Z80_C), opts->regs[Z80_BC], SZ_W); |
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503 dst = mov_rdisp8r(dst, CONTEXT, zar_off(Z80_L), opts->regs[Z80_HL], SZ_W); |
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504 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, zar_off(Z80_C), SZ_W); |
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505 dst = mov_rrdisp8(dst, SCRATCH2, CONTEXT, zar_off(Z80_L), SZ_W); |
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506 dst = mov_rr(dst, opts->regs[Z80_DE], SCRATCH1, SZ_W); |
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507 dst = mov_rdisp8r(dst, CONTEXT, zar_off(Z80_E), opts->regs[Z80_DE], SZ_W); |
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508 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, zar_off(Z80_E), SZ_W); |
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509 break; |
272 | 510 case Z80_LDI: { |
511 dst = zcycles(dst, 8); | |
512 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH1, SZ_W); | |
513 dst = call(dst, (uint8_t *)z80_read_byte); | |
514 dst = mov_rr(dst, opts->regs[Z80_DE], SCRATCH2, SZ_W); | |
515 dst = call(dst, (uint8_t *)z80_read_byte); | |
516 dst = zcycles(dst, 2); | |
517 dst = add_ir(dst, 1, opts->regs[Z80_DE], SZ_W); | |
518 dst = add_ir(dst, 1, opts->regs[Z80_HL], SZ_W); | |
519 dst = sub_ir(dst, 1, opts->regs[Z80_BC], SZ_W); | |
520 //TODO: Implement half-carry | |
521 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); | |
522 dst = setcc_rdisp8(dst, CC_NZ, CONTEXT, zf_off(ZF_PV)); | |
523 break; | |
524 } | |
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525 case Z80_LDIR: { |
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526 dst = zcycles(dst, 8); |
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527 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH1, SZ_W); |
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528 dst = call(dst, (uint8_t *)z80_read_byte); |
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529 dst = mov_rr(dst, opts->regs[Z80_DE], SCRATCH2, SZ_W); |
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530 dst = call(dst, (uint8_t *)z80_read_byte); |
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531 dst = add_ir(dst, 1, opts->regs[Z80_DE], SZ_W); |
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532 dst = add_ir(dst, 1, opts->regs[Z80_HL], SZ_W); |
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533 |
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534 dst = sub_ir(dst, 1, opts->regs[Z80_BC], SZ_W); |
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535 uint8_t * cont = dst+1; |
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536 dst = jcc(dst, CC_Z, dst+2); |
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537 dst = zcycles(dst, 7); |
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538 //TODO: Figure out what the flag state should be here |
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539 //TODO: Figure out whether an interrupt can interrupt this |
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540 dst = jmp(dst, start); |
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541 *cont = dst - (cont + 1); |
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542 dst = zcycles(dst, 2); |
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543 //TODO: Implement half-carry |
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544 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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545 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_PV), SZ_B); |
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546 break; |
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547 } |
273 | 548 case Z80_LDD: { |
549 dst = zcycles(dst, 8); | |
550 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH1, SZ_W); | |
551 dst = call(dst, (uint8_t *)z80_read_byte); | |
552 dst = mov_rr(dst, opts->regs[Z80_DE], SCRATCH2, SZ_W); | |
553 dst = call(dst, (uint8_t *)z80_read_byte); | |
554 dst = zcycles(dst, 2); | |
555 dst = sub_ir(dst, 1, opts->regs[Z80_DE], SZ_W); | |
556 dst = sub_ir(dst, 1, opts->regs[Z80_HL], SZ_W); | |
557 dst = sub_ir(dst, 1, opts->regs[Z80_BC], SZ_W); | |
558 //TODO: Implement half-carry | |
559 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); | |
560 dst = setcc_rdisp8(dst, CC_NZ, CONTEXT, zf_off(ZF_PV)); | |
561 break; | |
562 } | |
563 case Z80_LDDR: { | |
564 dst = zcycles(dst, 8); | |
565 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH1, SZ_W); | |
566 dst = call(dst, (uint8_t *)z80_read_byte); | |
567 dst = mov_rr(dst, opts->regs[Z80_DE], SCRATCH2, SZ_W); | |
568 dst = call(dst, (uint8_t *)z80_read_byte); | |
569 dst = sub_ir(dst, 1, opts->regs[Z80_DE], SZ_W); | |
570 dst = sub_ir(dst, 1, opts->regs[Z80_HL], SZ_W); | |
571 | |
572 dst = sub_ir(dst, 1, opts->regs[Z80_BC], SZ_W); | |
573 uint8_t * cont = dst+1; | |
574 dst = jcc(dst, CC_Z, dst+2); | |
575 dst = zcycles(dst, 7); | |
576 //TODO: Figure out what the flag state should be here | |
577 //TODO: Figure out whether an interrupt can interrupt this | |
578 dst = jmp(dst, start); | |
579 *cont = dst - (cont + 1); | |
580 dst = zcycles(dst, 2); | |
581 //TODO: Implement half-carry | |
582 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); | |
583 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_PV), SZ_B); | |
584 break; | |
585 } | |
586 /*case Z80_CPI: | |
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587 case Z80_CPIR: |
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588 case Z80_CPD: |
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589 case Z80_CPDR: |
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590 break;*/ |
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591 case Z80_ADD: |
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592 cycles = 4; |
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593 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
213
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594 cycles += 12; |
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595 } else if(inst->addr_mode == Z80_IMMED) { |
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596 cycles += 3; |
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597 } else if(z80_size(inst) == SZ_W) { |
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598 cycles += 4; |
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599 } |
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600 dst = zcycles(dst, cycles); |
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601 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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602 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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603 if (src_op.mode == MODE_REG_DIRECT) { |
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604 dst = add_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
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605 } else { |
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606 dst = add_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
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607 } |
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608 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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609 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
213
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610 //TODO: Implement half-carry flag |
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611 if (z80_size(inst) == SZ_B) { |
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612 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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613 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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614 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
213
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615 } |
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616 dst = z80_save_reg(dst, inst, opts); |
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617 dst = z80_save_ea(dst, inst, opts); |
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618 break; |
248
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619 case Z80_ADC: |
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620 cycles = 4; |
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621 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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622 cycles += 12; |
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623 } else if(inst->addr_mode == Z80_IMMED) { |
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624 cycles += 3; |
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625 } else if(z80_size(inst) == SZ_W) { |
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626 cycles += 4; |
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627 } |
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628 dst = zcycles(dst, cycles); |
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629 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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630 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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631 if (src_op.mode == MODE_REG_DIRECT) { |
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632 dst = adc_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
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633 } else { |
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634 dst = adc_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
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635 } |
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636 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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637 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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638 //TODO: Implement half-carry flag |
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639 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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640 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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641 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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642 dst = z80_save_reg(dst, inst, opts); |
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643 dst = z80_save_ea(dst, inst, opts); |
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644 break; |
213
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645 case Z80_SUB: |
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646 cycles = 4; |
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647 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
213
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648 cycles += 12; |
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649 } else if(inst->addr_mode == Z80_IMMED) { |
4d4559b04c59
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650 cycles += 3; |
4d4559b04c59
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651 } |
4d4559b04c59
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|
652 dst = zcycles(dst, cycles); |
4d4559b04c59
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653 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
4d4559b04c59
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654 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
4d4559b04c59
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655 if (src_op.mode == MODE_REG_DIRECT) { |
4d4559b04c59
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656 dst = sub_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
4d4559b04c59
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657 } else { |
4d4559b04c59
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658 dst = sub_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
4d4559b04c59
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659 } |
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|
660 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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661 dst = mov_irdisp8(dst, 1, CONTEXT, zf_off(ZF_N), SZ_B); |
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662 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
213
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663 //TODO: Implement half-carry flag |
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664 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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665 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
213
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666 dst = z80_save_reg(dst, inst, opts); |
4d4559b04c59
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|
667 dst = z80_save_ea(dst, inst, opts); |
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668 break; |
248
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669 case Z80_SBC: |
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670 cycles = 4; |
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671 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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672 cycles += 12; |
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673 } else if(inst->addr_mode == Z80_IMMED) { |
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674 cycles += 3; |
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675 } else if(z80_size(inst) == SZ_W) { |
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676 cycles += 4; |
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677 } |
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678 dst = zcycles(dst, cycles); |
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679 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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680 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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681 if (src_op.mode == MODE_REG_DIRECT) { |
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682 dst = sbb_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
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683 } else { |
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684 dst = sbb_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
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685 } |
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686 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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687 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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688 //TODO: Implement half-carry flag |
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689 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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690 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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691 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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692 dst = z80_save_reg(dst, inst, opts); |
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693 dst = z80_save_ea(dst, inst, opts); |
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694 break; |
213
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Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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|
695 case Z80_AND: |
236
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696 cycles = 4; |
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697 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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698 cycles += 12; |
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699 } else if(inst->addr_mode == Z80_IMMED) { |
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|
700 cycles += 3; |
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701 } else if(z80_size(inst) == SZ_W) { |
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702 cycles += 4; |
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|
703 } |
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704 dst = zcycles(dst, cycles); |
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705 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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706 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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707 if (src_op.mode == MODE_REG_DIRECT) { |
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708 dst = and_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
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709 } else { |
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235
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710 dst = and_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
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|
711 } |
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|
712 //TODO: Cleanup flags |
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|
713 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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|
714 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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diff
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|
715 //TODO: Implement half-carry flag |
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|
716 if (z80_size(inst) == SZ_B) { |
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235
diff
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|
717 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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|
718 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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235
diff
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|
719 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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235
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|
720 } |
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diff
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|
721 dst = z80_save_reg(dst, inst, opts); |
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235
diff
changeset
|
722 dst = z80_save_ea(dst, inst, opts); |
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parents:
235
diff
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|
723 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
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diff
changeset
|
724 case Z80_OR: |
236
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235
diff
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|
725 cycles = 4; |
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235
diff
changeset
|
726 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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235
diff
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|
727 cycles += 12; |
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Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
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235
diff
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|
728 } else if(inst->addr_mode == Z80_IMMED) { |
19fb3523a9e5
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235
diff
changeset
|
729 cycles += 3; |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
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235
diff
changeset
|
730 } else if(z80_size(inst) == SZ_W) { |
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235
diff
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|
731 cycles += 4; |
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
732 } |
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235
diff
changeset
|
733 dst = zcycles(dst, cycles); |
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235
diff
changeset
|
734 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
19fb3523a9e5
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235
diff
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|
735 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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235
diff
changeset
|
736 if (src_op.mode == MODE_REG_DIRECT) { |
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235
diff
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|
737 dst = or_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
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235
diff
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|
738 } else { |
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235
diff
changeset
|
739 dst = or_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
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235
diff
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|
740 } |
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235
diff
changeset
|
741 //TODO: Cleanup flags |
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235
diff
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|
742 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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235
diff
changeset
|
743 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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235
diff
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|
744 //TODO: Implement half-carry flag |
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235
diff
changeset
|
745 if (z80_size(inst) == SZ_B) { |
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235
diff
changeset
|
746 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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235
diff
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|
747 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
19fb3523a9e5
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235
diff
changeset
|
748 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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235
diff
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|
749 } |
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235
diff
changeset
|
750 dst = z80_save_reg(dst, inst, opts); |
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235
diff
changeset
|
751 dst = z80_save_ea(dst, inst, opts); |
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752 break; |
213
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753 case Z80_XOR: |
236
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754 cycles = 4; |
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755 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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756 cycles += 12; |
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757 } else if(inst->addr_mode == Z80_IMMED) { |
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758 cycles += 3; |
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759 } else if(z80_size(inst) == SZ_W) { |
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760 cycles += 4; |
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761 } |
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762 dst = zcycles(dst, cycles); |
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763 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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764 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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765 if (src_op.mode == MODE_REG_DIRECT) { |
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766 dst = add_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
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767 } else { |
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768 dst = add_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
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769 } |
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770 //TODO: Cleanup flags |
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771 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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772 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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773 //TODO: Implement half-carry flag |
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774 if (z80_size(inst) == SZ_B) { |
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775 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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776 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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777 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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778 } |
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779 dst = z80_save_reg(dst, inst, opts); |
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780 dst = z80_save_ea(dst, inst, opts); |
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781 break; |
242 | 782 case Z80_CP: |
783 cycles = 4; | |
784 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { | |
785 cycles += 12; | |
786 } else if(inst->addr_mode == Z80_IMMED) { | |
787 cycles += 3; | |
788 } | |
789 dst = zcycles(dst, cycles); | |
790 dst = translate_z80_reg(inst, &dst_op, dst, opts); | |
791 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); | |
792 if (src_op.mode == MODE_REG_DIRECT) { | |
793 dst = cmp_rr(dst, src_op.base, dst_op.base, z80_size(inst)); | |
794 } else { | |
795 dst = cmp_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); | |
796 } | |
797 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); | |
798 dst = mov_irdisp8(dst, 1, CONTEXT, zf_off(ZF_N), SZ_B); | |
799 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); | |
800 //TODO: Implement half-carry flag | |
801 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); | |
802 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); | |
803 dst = z80_save_reg(dst, inst, opts); | |
804 dst = z80_save_ea(dst, inst, opts); | |
805 break; | |
213
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806 case Z80_INC: |
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807 cycles = 4; |
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808 if (inst->reg == Z80_IX || inst->reg == Z80_IY) { |
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809 cycles += 6; |
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810 } else if(z80_size(inst) == SZ_W) { |
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811 cycles += 2; |
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812 } else if(inst->reg == Z80_IXH || inst->reg == Z80_IXL || inst->reg == Z80_IYH || inst->reg == Z80_IYL || inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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813 cycles += 4; |
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814 } |
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815 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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816 if (dst_op.mode == MODE_UNUSED) { |
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817 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
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818 } |
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819 dst = add_ir(dst, 1, dst_op.base, z80_size(inst)); |
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820 if (z80_size(inst) == SZ_B) { |
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821 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
213
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|
822 //TODO: Implement half-carry flag |
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823 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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824 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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825 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
213
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826 } |
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827 dst = z80_save_reg(dst, inst, opts); |
4d4559b04c59
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diff
changeset
|
828 dst = z80_save_ea(dst, inst, opts); |
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829 break; |
236
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830 case Z80_DEC: |
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831 cycles = 4; |
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832 if (inst->reg == Z80_IX || inst->reg == Z80_IY) { |
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833 cycles += 6; |
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834 } else if(z80_size(inst) == SZ_W) { |
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835 cycles += 2; |
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836 } else if(inst->reg == Z80_IXH || inst->reg == Z80_IXL || inst->reg == Z80_IYH || inst->reg == Z80_IYL || inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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837 cycles += 4; |
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838 } |
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839 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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840 if (dst_op.mode == MODE_UNUSED) { |
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841 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
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842 } |
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843 dst = sub_ir(dst, 1, dst_op.base, z80_size(inst)); |
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844 if (z80_size(inst) == SZ_B) { |
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845 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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846 //TODO: Implement half-carry flag |
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847 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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848 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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849 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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850 } |
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851 dst = z80_save_reg(dst, inst, opts); |
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852 dst = z80_save_ea(dst, inst, opts); |
213
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|
853 break; |
274
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273
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|
854 //case Z80_DAA: |
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|
855 case Z80_CPL: |
274
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856 dst = zcycles(dst, 4); |
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857 dst = not_r(dst, opts->regs[Z80_A], SZ_B); |
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858 //TODO: Implement half-carry flag |
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859 dst = mov_irdisp8(dst, 1, CONTEXT, zf_off(ZF_N), SZ_B); |
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860 break; |
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861 case Z80_NEG: |
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862 dst = zcycles(dst, 8); |
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863 dst = neg_r(dst, opts->regs[Z80_A], SZ_B); |
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864 //TODO: Implement half-carry flag |
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865 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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866 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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867 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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868 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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869 dst = mov_irdisp8(dst, 1, CONTEXT, zf_off(ZF_N), SZ_B); |
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870 break; |
213
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diff
changeset
|
871 case Z80_CCF: |
257 | 872 dst = zcycles(dst, 4); |
873 dst = xor_irdisp8(dst, 1, CONTEXT, zf_off(ZF_C), SZ_B); | |
874 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); | |
875 //TODO: Implement half-carry flag | |
876 break; | |
877 case Z80_SCF: | |
878 dst = zcycles(dst, 4); | |
879 dst = mov_irdisp8(dst, 1, CONTEXT, zf_off(ZF_C), SZ_B); | |
880 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); | |
881 //TODO: Implement half-carry flag | |
882 break; | |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
883 case Z80_NOP: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
884 if (inst->immed == 42) { |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
885 dst = call(dst, (uint8_t *)z80_save_context); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
886 dst = mov_rr(dst, CONTEXT, RDI, SZ_Q); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
887 dst = jmp(dst, (uint8_t *)z80_print_regs_exit); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
888 } else { |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
889 dst = zcycles(dst, 4 * inst->immed); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
890 } |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
891 break; |
243
2f069a0b487e
Implement EI, DI and IM in the Z80 core
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242
diff
changeset
|
892 //case Z80_HALT: |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
893 case Z80_DI: |
243
2f069a0b487e
Implement EI, DI and IM in the Z80 core
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242
diff
changeset
|
894 dst = zcycles(dst, 4); |
2f069a0b487e
Implement EI, DI and IM in the Z80 core
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242
diff
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|
895 dst = mov_irdisp8(dst, 0, CONTEXT, offsetof(z80_context, iff1), SZ_B); |
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242
diff
changeset
|
896 dst = mov_irdisp8(dst, 0, CONTEXT, offsetof(z80_context, iff2), SZ_B); |
250
5f1b68cecfc7
Implemented basic interrupt support in Z80 core.
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parents:
248
diff
changeset
|
897 dst = mov_rdisp8r(dst, CONTEXT, offsetof(z80_context, sync_cycle), ZLIMIT, SZ_D); |
243
2f069a0b487e
Implement EI, DI and IM in the Z80 core
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242
diff
changeset
|
898 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
899 case Z80_EI: |
243
2f069a0b487e
Implement EI, DI and IM in the Z80 core
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242
diff
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|
900 //TODO: Implement interrupt enable latency of 1 instruction afer EI |
2f069a0b487e
Implement EI, DI and IM in the Z80 core
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242
diff
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|
901 dst = zcycles(dst, 4); |
2f069a0b487e
Implement EI, DI and IM in the Z80 core
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242
diff
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|
902 dst = mov_irdisp8(dst, 1, CONTEXT, offsetof(z80_context, iff1), SZ_B); |
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Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
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242
diff
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|
903 dst = mov_irdisp8(dst, 1, CONTEXT, offsetof(z80_context, iff2), SZ_B); |
250
5f1b68cecfc7
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parents:
248
diff
changeset
|
904 dst = call(dst, (uint8_t *)z80_do_sync); |
243
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
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242
diff
changeset
|
905 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
906 case Z80_IM: |
243
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
907 dst = zcycles(dst, 4); |
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
908 dst = mov_irdisp8(dst, inst->immed, CONTEXT, offsetof(z80_context, im), SZ_B); |
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242
diff
changeset
|
909 break; |
247
682e505f5757
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parents:
246
diff
changeset
|
910 case Z80_RLC: |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
911 cycles = inst->immed == 1 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8); |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
912 dst = zcycles(dst, cycles); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
913 if (inst->reg == Z80_UNUSED) { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
914 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
915 dst = zcycles(dst, 1); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
916 } else { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
917 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
918 } |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
919 dst = rol_ir(dst, 1, dst_op.base, SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
920 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
921 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
922 //TODO: Implement half-carry flag |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
923 dst = cmp_ir(dst, 0, dst_op.base, SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
924 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
925 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
926 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
927 if (inst->reg == Z80_UNUSED) { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
928 dst = z80_save_result(dst, inst); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
929 } else { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
930 dst = z80_save_reg(dst, inst, opts); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
931 } |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
932 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
933 case Z80_RL: |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
934 cycles = inst->immed == 1 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
935 dst = zcycles(dst, cycles); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
936 if (inst->reg == Z80_UNUSED) { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
937 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
938 dst = zcycles(dst, 1); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
939 } else { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
940 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
941 } |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
942 dst = bt_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
943 dst = rcl_ir(dst, 1, dst_op.base, SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
944 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
945 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
946 //TODO: Implement half-carry flag |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
947 dst = cmp_ir(dst, 0, dst_op.base, SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
948 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
949 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
950 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
951 if (inst->reg == Z80_UNUSED) { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
952 dst = z80_save_result(dst, inst); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
953 } else { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
954 dst = z80_save_reg(dst, inst, opts); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
955 } |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
956 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
957 case Z80_RRC: |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
958 cycles = inst->immed == 1 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
959 dst = zcycles(dst, cycles); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
960 if (inst->reg == Z80_UNUSED) { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
961 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
962 dst = zcycles(dst, 1); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
963 } else { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
964 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
965 } |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
966 dst = ror_ir(dst, 1, dst_op.base, SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
967 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
968 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
969 //TODO: Implement half-carry flag |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
970 dst = cmp_ir(dst, 0, dst_op.base, SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
971 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
972 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
973 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
974 if (inst->reg == Z80_UNUSED) { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
975 dst = z80_save_result(dst, inst); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
976 } else { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
977 dst = z80_save_reg(dst, inst, opts); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
978 } |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
979 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
980 case Z80_RR: |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
981 cycles = inst->immed == 1 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
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|
982 dst = zcycles(dst, cycles); |
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|
983 if (inst->reg == Z80_UNUSED) { |
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984 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
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|
985 dst = zcycles(dst, 1); |
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diff
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|
986 } else { |
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|
987 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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|
988 } |
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|
989 dst = bt_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
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990 dst = rcr_ir(dst, 1, dst_op.base, SZ_B); |
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|
991 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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|
992 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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diff
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|
993 //TODO: Implement half-carry flag |
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994 dst = cmp_ir(dst, 0, dst_op.base, SZ_B); |
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|
995 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
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diff
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|
996 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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|
997 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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|
998 if (inst->reg == Z80_UNUSED) { |
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|
999 dst = z80_save_result(dst, inst); |
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diff
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|
1000 } else { |
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diff
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|
1001 dst = z80_save_reg(dst, inst, opts); |
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diff
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|
1002 } |
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diff
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|
1003 break; |
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|
1004 /*case Z80_SLA: |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff
changeset
|
1005 case Z80_SRA: |
4d4559b04c59
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parents:
diff
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|
1006 case Z80_SLL: |
4d4559b04c59
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1007 case Z80_SRL: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
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|
1008 case Z80_RLD: |
239
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
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238
diff
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|
1009 case Z80_RRD:*/ |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
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diff
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|
1010 case Z80_BIT: |
239
a5bea9711a46
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diff
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|
1011 cycles = (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) ? 8 : 16; |
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238
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|
1012 dst = zcycles(dst, cycles); |
a5bea9711a46
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238
diff
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|
1013 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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238
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|
1014 if (inst->addr_mode != Z80_REG) { |
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238
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|
1015 //Reads normally take 3 cycles, but the read at the end of a bit instruction takes 4 |
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238
diff
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|
1016 dst = zcycles(dst, 1); |
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238
diff
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|
1017 } |
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238
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|
1018 dst = bt_ir(dst, inst->immed, src_op.base, SZ_B); |
a5bea9711a46
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diff
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|
1019 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_Z)); |
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238
diff
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|
1020 break; |
247
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diff
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|
1021 case Z80_SET: |
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246
diff
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|
1022 cycles = (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) ? 8 : 16; |
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246
diff
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|
1023 dst = zcycles(dst, cycles); |
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|
1024 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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246
diff
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|
1025 if (inst->addr_mode != Z80_REG) { |
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246
diff
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|
1026 //Reads normally take 3 cycles, but the read in the middle of a set instruction takes 4 |
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246
diff
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|
1027 dst = zcycles(dst, 1); |
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246
diff
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|
1028 } |
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diff
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|
1029 dst = bts_ir(dst, inst->immed, src_op.base, SZ_B); |
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246
diff
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|
1030 if (inst->addr_mode != Z80_REG) { |
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Mike Pavone <pavone@retrodev.com>
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246
diff
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|
1031 dst = z80_save_result(dst, inst); |
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246
diff
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|
1032 } |
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246
diff
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|
1033 break; |
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246
diff
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|
1034 case Z80_RES: |
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246
diff
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|
1035 cycles = (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) ? 8 : 16; |
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246
diff
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|
1036 dst = zcycles(dst, cycles); |
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246
diff
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|
1037 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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246
diff
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|
1038 if (inst->addr_mode != Z80_REG) { |
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246
diff
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|
1039 //Reads normally take 3 cycles, but the read in the middle of a set instruction takes 4 |
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246
diff
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|
1040 dst = zcycles(dst, 1); |
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246
diff
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|
1041 } |
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246
diff
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|
1042 dst = btr_ir(dst, inst->immed, src_op.base, SZ_B); |
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246
diff
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|
1043 if (inst->addr_mode != Z80_REG) { |
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246
diff
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|
1044 dst = z80_save_result(dst, inst); |
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246
diff
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|
1045 } |
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246
diff
changeset
|
1046 break; |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
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235
diff
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|
1047 case Z80_JP: { |
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Implement more Z80 instructions (untested)
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235
diff
changeset
|
1048 cycles = 4; |
239
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
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238
diff
changeset
|
1049 if (inst->addr_mode != Z80_REG) { |
236
19fb3523a9e5
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parents:
235
diff
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|
1050 cycles += 6; |
19fb3523a9e5
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235
diff
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|
1051 } else if(inst->ea_reg == Z80_IX || inst->ea_reg == Z80_IY) { |
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235
diff
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|
1052 cycles += 4; |
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235
diff
changeset
|
1053 } |
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235
diff
changeset
|
1054 dst = zcycles(dst, cycles); |
239
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
1055 if (inst->addr_mode != Z80_REG_INDIRECT && inst->immed < 0x4000) { |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
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235
diff
changeset
|
1056 uint8_t * call_dst = z80_get_native_address(context, inst->immed); |
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235
diff
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|
1057 if (!call_dst) { |
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235
diff
changeset
|
1058 opts->deferred = defer_address(opts->deferred, inst->immed, dst + 1); |
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Implement more Z80 instructions (untested)
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235
diff
changeset
|
1059 //fake address to force large displacement |
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235
diff
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|
1060 call_dst = dst + 256; |
19fb3523a9e5
Implement more Z80 instructions (untested)
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235
diff
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|
1061 } |
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235
diff
changeset
|
1062 dst = jmp(dst, call_dst); |
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235
diff
changeset
|
1063 } else { |
239
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
1064 if (inst->addr_mode == Z80_REG_INDIRECT) { |
236
19fb3523a9e5
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235
diff
changeset
|
1065 dst = mov_rr(dst, opts->regs[inst->ea_reg], SCRATCH1, SZ_W); |
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235
diff
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|
1066 } else { |
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235
diff
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|
1067 dst = mov_ir(dst, inst->immed, SCRATCH1, SZ_W); |
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235
diff
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|
1068 } |
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235
diff
changeset
|
1069 dst = call(dst, (uint8_t *)z80_native_addr); |
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235
diff
changeset
|
1070 dst = jmp_r(dst, SCRATCH1); |
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235
diff
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|
1071 } |
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235
diff
changeset
|
1072 break; |
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235
diff
changeset
|
1073 } |
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235
diff
changeset
|
1074 case Z80_JPCC: { |
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235
diff
changeset
|
1075 dst = zcycles(dst, 7);//T States: 4,3 |
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235
diff
changeset
|
1076 uint8_t cond = CC_Z; |
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235
diff
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|
1077 switch (inst->reg) |
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235
diff
changeset
|
1078 { |
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parents:
235
diff
changeset
|
1079 case Z80_CC_NZ: |
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235
diff
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|
1080 cond = CC_NZ; |
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235
diff
changeset
|
1081 case Z80_CC_Z: |
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235
diff
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|
1082 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_Z), SZ_B); |
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parents:
235
diff
changeset
|
1083 break; |
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parents:
235
diff
changeset
|
1084 case Z80_CC_NC: |
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235
diff
changeset
|
1085 cond = CC_NZ; |
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235
diff
changeset
|
1086 case Z80_CC_C: |
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235
diff
changeset
|
1087 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
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parents:
235
diff
changeset
|
1088 break; |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1089 case Z80_CC_PO: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1090 cond = CC_NZ; |
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1091 case Z80_CC_PE: |
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1092 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_PV), SZ_B); |
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1093 break; |
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1094 case Z80_CC_P: |
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1095 case Z80_CC_M: |
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1096 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_S), SZ_B); |
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1097 break; |
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1098 } |
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1099 uint8_t *no_jump_off = dst+1; |
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1100 dst = jcc(dst, cond, dst+2); |
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1101 dst = zcycles(dst, 5);//T States: 5 |
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1102 uint16_t dest_addr = inst->immed; |
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1103 if (dest_addr < 0x4000) { |
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1104 uint8_t * call_dst = z80_get_native_address(context, dest_addr); |
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1105 if (!call_dst) { |
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1106 opts->deferred = defer_address(opts->deferred, dest_addr, dst + 1); |
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1107 //fake address to force large displacement |
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1108 call_dst = dst + 256; |
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1109 } |
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1110 dst = jmp(dst, call_dst); |
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1111 } else { |
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1112 dst = mov_ir(dst, dest_addr, SCRATCH1, SZ_W); |
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1113 dst = call(dst, (uint8_t *)z80_native_addr); |
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1114 dst = jmp_r(dst, SCRATCH1); |
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1115 } |
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1116 *no_jump_off = dst - (no_jump_off+1); |
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1117 break; |
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1118 } |
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1119 case Z80_JR: { |
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1120 dst = zcycles(dst, 12);//T States: 4,3,5 |
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1121 uint16_t dest_addr = address + inst->immed + 2; |
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1122 if (dest_addr < 0x4000) { |
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1123 uint8_t * call_dst = z80_get_native_address(context, dest_addr); |
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1124 if (!call_dst) { |
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1125 opts->deferred = defer_address(opts->deferred, dest_addr, dst + 1); |
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1126 //fake address to force large displacement |
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1127 call_dst = dst + 256; |
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1128 } |
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1129 dst = jmp(dst, call_dst); |
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1130 } else { |
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1131 dst = mov_ir(dst, dest_addr, SCRATCH1, SZ_W); |
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1132 dst = call(dst, (uint8_t *)z80_native_addr); |
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1133 dst = jmp_r(dst, SCRATCH1); |
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1134 } |
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1135 break; |
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1136 } |
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1137 case Z80_JRCC: { |
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1138 dst = zcycles(dst, 7);//T States: 4,3 |
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1139 uint8_t cond = CC_Z; |
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1140 switch (inst->reg) |
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1141 { |
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1142 case Z80_CC_NZ: |
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1143 cond = CC_NZ; |
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1144 case Z80_CC_Z: |
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1145 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_Z), SZ_B); |
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1146 break; |
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1147 case Z80_CC_NC: |
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1148 cond = CC_NZ; |
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1149 case Z80_CC_C: |
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1150 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
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1151 break; |
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1152 } |
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1153 uint8_t *no_jump_off = dst+1; |
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1154 dst = jcc(dst, cond, dst+2); |
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1155 dst = zcycles(dst, 5);//T States: 5 |
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1156 uint16_t dest_addr = address + inst->immed + 2; |
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1157 if (dest_addr < 0x4000) { |
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1158 uint8_t * call_dst = z80_get_native_address(context, dest_addr); |
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1159 if (!call_dst) { |
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1160 opts->deferred = defer_address(opts->deferred, dest_addr, dst + 1); |
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1161 //fake address to force large displacement |
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1162 call_dst = dst + 256; |
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1163 } |
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1164 dst = jmp(dst, call_dst); |
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1165 } else { |
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1166 dst = mov_ir(dst, dest_addr, SCRATCH1, SZ_W); |
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1167 dst = call(dst, (uint8_t *)z80_native_addr); |
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1168 dst = jmp_r(dst, SCRATCH1); |
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1169 } |
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1170 *no_jump_off = dst - (no_jump_off+1); |
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1171 break; |
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1172 } |
239
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1173 case Z80_DJNZ: |
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1174 dst = zcycles(dst, 8);//T States: 5,3 |
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1175 dst = sub_ir(dst, 1, opts->regs[Z80_B], SZ_B); |
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1176 uint8_t *no_jump_off = dst+1; |
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1177 dst = jcc(dst, CC_Z, dst+2); |
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1178 dst = zcycles(dst, 5);//T States: 5 |
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1179 uint16_t dest_addr = address + inst->immed + 2; |
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1180 if (dest_addr < 0x4000) { |
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1181 uint8_t * call_dst = z80_get_native_address(context, dest_addr); |
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1182 if (!call_dst) { |
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1183 opts->deferred = defer_address(opts->deferred, dest_addr, dst + 1); |
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1184 //fake address to force large displacement |
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1185 call_dst = dst + 256; |
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1186 } |
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1187 dst = jmp(dst, call_dst); |
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1188 } else { |
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1189 dst = mov_ir(dst, dest_addr, SCRATCH1, SZ_W); |
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1190 dst = call(dst, (uint8_t *)z80_native_addr); |
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1191 dst = jmp_r(dst, SCRATCH1); |
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1192 } |
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1193 *no_jump_off = dst - (no_jump_off+1); |
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|
1194 break; |
235
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1195 case Z80_CALL: { |
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1196 dst = zcycles(dst, 11);//T States: 4,3,4 |
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1197 dst = sub_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
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1198 dst = mov_ir(dst, address + 3, SCRATCH1, SZ_W); |
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1199 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W); |
235
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1200 dst = call(dst, (uint8_t *)z80_write_word_highfirst);//T States: 3, 3 |
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1201 if (inst->immed < 0x4000) { |
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Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1202 uint8_t * call_dst = z80_get_native_address(context, inst->immed); |
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Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1203 if (!call_dst) { |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1204 opts->deferred = defer_address(opts->deferred, inst->immed, dst + 1); |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1205 //fake address to force large displacement |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1206 call_dst = dst + 256; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1207 } |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1208 dst = jmp(dst, call_dst); |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1209 } else { |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1210 dst = mov_ir(dst, inst->immed, SCRATCH1, SZ_W); |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1211 dst = call(dst, (uint8_t *)z80_native_addr); |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1212 dst = jmp_r(dst, SCRATCH1); |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1213 } |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1214 break; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1215 } |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1216 case Z80_CALLCC: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1217 dst = zcycles(dst, 10);//T States: 4,3,3 (false case) |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1218 uint8_t cond = CC_Z; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1219 switch (inst->reg) |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1220 { |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1221 case Z80_CC_NZ: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1222 cond = CC_NZ; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1223 case Z80_CC_Z: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1224 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_Z), SZ_B); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1225 break; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1226 case Z80_CC_NC: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1227 cond = CC_NZ; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1228 case Z80_CC_C: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1229 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1230 break; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1231 case Z80_CC_PO: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1232 cond = CC_NZ; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1233 case Z80_CC_PE: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1234 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_PV), SZ_B); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1235 break; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1236 case Z80_CC_P: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1237 case Z80_CC_M: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1238 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_S), SZ_B); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1239 break; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1240 } |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1241 uint8_t *no_call_off = dst+1; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1242 dst = jcc(dst, cond, dst+2); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1243 dst = zcycles(dst, 1);//Last of the above T states takes an extra cycle in the true case |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1244 dst = sub_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
253
3b34deba4ca0
Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents:
252
diff
changeset
|
1245 dst = mov_ir(dst, address + 3, SCRATCH1, SZ_W); |
3b34deba4ca0
Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents:
252
diff
changeset
|
1246 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W); |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1247 dst = call(dst, (uint8_t *)z80_write_word_highfirst);//T States: 3, 3 |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1248 if (inst->immed < 0x4000) { |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1249 uint8_t * call_dst = z80_get_native_address(context, inst->immed); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1250 if (!call_dst) { |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1251 opts->deferred = defer_address(opts->deferred, inst->immed, dst + 1); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1252 //fake address to force large displacement |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1253 call_dst = dst + 256; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1254 } |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1255 dst = jmp(dst, call_dst); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1256 } else { |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1257 dst = mov_ir(dst, inst->immed, SCRATCH1, SZ_W); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1258 dst = call(dst, (uint8_t *)z80_native_addr); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1259 dst = jmp_r(dst, SCRATCH1); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1260 } |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1261 *no_call_off = dst - (no_call_off+1); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1262 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1263 case Z80_RET: |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1264 dst = zcycles(dst, 4);//T States: 4 |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1265 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1266 dst = call(dst, (uint8_t *)z80_read_word);//T STates: 3, 3 |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1267 dst = add_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1268 dst = call(dst, (uint8_t *)z80_native_addr); |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1269 dst = jmp_r(dst, SCRATCH1); |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1270 break; |
246
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1271 case Z80_RETCC: { |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1272 dst = zcycles(dst, 5);//T States: 5 |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1273 uint8_t cond = CC_Z; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1274 switch (inst->reg) |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1275 { |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1276 case Z80_CC_NZ: |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1277 cond = CC_NZ; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1278 case Z80_CC_Z: |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1279 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_Z), SZ_B); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1280 break; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1281 case Z80_CC_NC: |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1282 cond = CC_NZ; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1283 case Z80_CC_C: |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1284 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1285 break; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1286 case Z80_CC_PO: |
ed548c77b598
Implement RETCC in Z80 core.
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parents:
243
diff
changeset
|
1287 cond = CC_NZ; |
ed548c77b598
Implement RETCC in Z80 core.
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parents:
243
diff
changeset
|
1288 case Z80_CC_PE: |
ed548c77b598
Implement RETCC in Z80 core.
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parents:
243
diff
changeset
|
1289 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_PV), SZ_B); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1290 break; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1291 case Z80_CC_P: |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1292 case Z80_CC_M: |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1293 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_S), SZ_B); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1294 break; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1295 } |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1296 uint8_t *no_call_off = dst+1; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1297 dst = jcc(dst, cond, dst+2); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1298 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1299 dst = call(dst, (uint8_t *)z80_read_word);//T STates: 3, 3 |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1300 dst = add_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
ed548c77b598
Implement RETCC in Z80 core.
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parents:
243
diff
changeset
|
1301 dst = call(dst, (uint8_t *)z80_native_addr); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1302 dst = jmp_r(dst, SCRATCH1); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1303 *no_call_off = dst - (no_call_off+1); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1304 break; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1305 } |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1306 /*case Z80_RETI: |
241
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1307 case Z80_RETN:*/ |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1308 case Z80_RST: { |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
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parents:
239
diff
changeset
|
1309 //RST is basically CALL to an address in page 0 |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1310 dst = zcycles(dst, 5);//T States: 5 |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1311 dst = sub_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
253
3b34deba4ca0
Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
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|
1312 dst = mov_ir(dst, address + 3, SCRATCH1, SZ_W); |
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1313 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W); |
241
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Implement EX, EXX and RST in Z80 core
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|
1314 dst = call(dst, (uint8_t *)z80_write_word_highfirst);//T States: 3, 3 |
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|
1315 uint8_t * call_dst = z80_get_native_address(context, inst->immed); |
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|
1316 if (!call_dst) { |
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|
1317 opts->deferred = defer_address(opts->deferred, inst->immed, dst + 1); |
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|
1318 //fake address to force large displacement |
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|
1319 call_dst = dst + 256; |
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|
1320 } |
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|
1321 dst = jmp(dst, call_dst); |
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|
1322 break; |
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|
1323 } |
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|
1324 /*case Z80_IN: |
213
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Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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|
1325 case Z80_INI: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff
changeset
|
1326 case Z80_INIR: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
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|
1327 case Z80_IND: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
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diff
changeset
|
1328 case Z80_INDR: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
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changeset
|
1329 case Z80_OUT: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
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|
1330 case Z80_OUTI: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
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diff
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|
1331 case Z80_OTIR: |
4d4559b04c59
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Mike Pavone <pavone@retrodev.com>
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diff
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|
1332 case Z80_OUTD: |
4d4559b04c59
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|
1333 case Z80_OTDR:*/ |
235
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|
1334 default: { |
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|
1335 char disbuf[80]; |
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|
1336 z80_disasm(inst, disbuf); |
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|
1337 fprintf(stderr, "unimplemented instruction: %s\n", disbuf); |
259
d9417261366f
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257
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|
1338 FILE * f = fopen("zram.bin", "wb"); |
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|
1339 fwrite(context->mem_pointers[0], 1, 8 * 1024, f); |
d9417261366f
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257
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|
1340 fclose(f); |
213
4d4559b04c59
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|
1341 exit(1); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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|
1342 } |
235
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|
1343 } |
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|
1344 return dst; |
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|
1345 } |
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|
1346 |
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1347 uint8_t * z80_get_native_address(z80_context * context, uint32_t address) |
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Get Z80 core working for simple programs
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|
1348 { |
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|
1349 native_map_slot *map; |
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|
1350 if (address < 0x4000) { |
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1351 address &= 0x1FFF; |
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|
1352 map = context->static_code_map; |
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|
1353 } else if (address >= 0x8000) { |
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Get Z80 core working for simple programs
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|
1354 address &= 0x7FFF; |
252
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|
1355 map = context->banked_code_map + (context->bank_reg << 15); |
235
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|
1356 } else { |
268
6c2d7e003a55
Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
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267
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|
1357 dprintf("z80_get_native_address: %X NULL\n", address); |
235
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|
1358 return NULL; |
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|
1359 } |
268
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Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
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|
1360 if (!map->base || !map->offsets || map->offsets[address] == INVALID_OFFSET || map->offsets[address] == EXTENSION_WORD) { |
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Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
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|
1361 dprintf("z80_get_native_address: %X NULL\n", address); |
235
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|
1362 return NULL; |
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|
1363 } |
268
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|
1364 dprintf("z80_get_native_address: %X %p\n", address, map->base + map->offsets[address]); |
235
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1365 return map->base + map->offsets[address]; |
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213
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|
1366 } |
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|
1367 |
252
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Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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|
1368 uint8_t z80_get_native_inst_size(x86_z80_options * opts, uint32_t address) |
235
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|
1369 { |
252
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Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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|
1370 if (address >= 0x4000) { |
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Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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|
1371 return 0; |
63b9a500a00b
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|
1372 } |
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Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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|
1373 return opts->ram_inst_sizes[address & 0x1FFF]; |
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|
1374 } |
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Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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1375 |
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Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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|
1376 void z80_map_native_address(z80_context * context, uint32_t address, uint8_t * native_address, uint8_t size, uint8_t native_size) |
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Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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|
1377 { |
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Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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|
1378 uint32_t orig_address = address; |
235
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|
1379 native_map_slot *map; |
252
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|
1380 x86_z80_options * opts = context->options; |
235
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|
1381 if (address < 0x4000) { |
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|
1382 address &= 0x1FFF; |
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|
1383 map = context->static_code_map; |
252
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|
1384 opts->ram_inst_sizes[address] = native_size; |
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|
1385 context->ram_code_flags[(address & 0x1C00) >> 10] |= 1 << ((address & 0x380) >> 7); |
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|
1386 context->ram_code_flags[((address + size) & 0x1C00) >> 10] |= 1 << (((address + size) & 0x380) >> 7); |
235
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|
1387 } else if (address >= 0x8000) { |
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|
1388 address &= 0x7FFF; |
252
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|
1389 map = context->banked_code_map + (context->bank_reg << 15); |
235
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1390 if (!map->offsets) { |
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1391 map->offsets = malloc(sizeof(int32_t) * 0x8000); |
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1392 memset(map->offsets, 0xFF, sizeof(int32_t) * 0x8000); |
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|
1393 } |
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|
1394 } else { |
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|
1395 return; |
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|
1396 } |
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1397 if (!map->base) { |
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1398 map->base = native_address; |
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1399 } |
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|
1400 map->offsets[address] = native_address - map->base; |
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1401 for(--size, orig_address++; size; --size, orig_address++) { |
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1402 address = orig_address; |
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1403 if (address < 0x4000) { |
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1404 address &= 0x1FFF; |
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1405 map = context->static_code_map; |
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1406 } else if (address >= 0x8000) { |
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1407 address &= 0x7FFF; |
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1408 map = context->banked_code_map + (context->bank_reg << 15); |
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1409 } else { |
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1410 return; |
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1411 } |
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1412 if (!map->offsets) { |
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1413 map->offsets = malloc(sizeof(int32_t) * 0x8000); |
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1414 memset(map->offsets, 0xFF, sizeof(int32_t) * 0x8000); |
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1415 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1416 map->offsets[address] = EXTENSION_WORD; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1417 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1418 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1419 |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1420 #define INVALID_INSTRUCTION_START 0xFEEDFEED |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1421 |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1422 uint32_t z80_get_instruction_start(native_map_slot * static_code_map, uint32_t address) |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1423 { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1424 if (!static_code_map->base || address >= 0x4000) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1425 return INVALID_INSTRUCTION_START; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1426 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1427 address &= 0x1FFF; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1428 if (static_code_map->offsets[address] == INVALID_OFFSET) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1429 return INVALID_INSTRUCTION_START; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1430 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1431 while (static_code_map->offsets[address] == EXTENSION_WORD) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1432 --address; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1433 address &= 0x1FFF; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1434 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1435 return address; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1436 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1437 |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1438 z80_context * z80_handle_code_write(uint32_t address, z80_context * context) |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1439 { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1440 uint32_t inst_start = z80_get_instruction_start(context->static_code_map, address); |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1441 if (inst_start != INVALID_INSTRUCTION_START) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1442 uint8_t * dst = z80_get_native_address(context, inst_start); |
268
6c2d7e003a55
Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents:
267
diff
changeset
|
1443 dprintf("patching code at %p for Z80 instruction at %X due to write to %X\n", dst, inst_start, address); |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1444 dst = mov_ir(dst, inst_start, SCRATCH1, SZ_D); |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1445 dst = jmp(dst, (uint8_t *)z80_retrans_stub); |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1446 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1447 return context; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1448 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1449 |
264
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1450 uint8_t * z80_get_native_address_trans(z80_context * context, uint32_t address) |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1451 { |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1452 uint8_t * addr = z80_get_native_address(context, address); |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1453 if (!addr) { |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1454 translate_z80_stream(context, address); |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1455 addr = z80_get_native_address(context, address); |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1456 if (!addr) { |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1457 printf("Failed to translate %X to native code\n", address); |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1458 } |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1459 } |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1460 return addr; |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1461 } |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1462 |
266
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1463 void z80_handle_deferred(z80_context * context) |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1464 { |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1465 x86_z80_options * opts = context->options; |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1466 process_deferred(&opts->deferred, context, (native_addr_func)z80_get_native_address); |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1467 if (opts->deferred) { |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1468 translate_z80_stream(context, opts->deferred->address); |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1469 } |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1470 } |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1471 |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1472 void * z80_retranslate_inst(uint32_t address, z80_context * context) |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1473 { |
266
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1474 char disbuf[80]; |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1475 x86_z80_options * opts = context->options; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1476 uint8_t orig_size = z80_get_native_inst_size(opts, address); |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1477 uint8_t * orig_start = z80_get_native_address(context, address); |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1478 uint32_t orig = address; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1479 address &= 0x1FFF; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1480 uint8_t * dst = opts->cur_code; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1481 uint8_t * dst_end = opts->code_end; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1482 uint8_t *after, *inst = context->mem_pointers[0] + address; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1483 z80inst instbuf; |
268
6c2d7e003a55
Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents:
267
diff
changeset
|
1484 dprintf("Retranslating code at Z80 address %X, native address %p\n", address, orig_start); |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1485 after = z80_decode(inst, &instbuf); |
268
6c2d7e003a55
Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents:
267
diff
changeset
|
1486 #ifdef DO_DEBUG_PRINT |
267
1788e3f29c28
Don't mix *H regs with the REX prefix
Mike Pavone <pavone@retrodev.com>
parents:
266
diff
changeset
|
1487 z80_disasm(&instbuf, disbuf); |
266
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1488 if (instbuf.op == Z80_NOP) { |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1489 printf("%X\t%s(%d)\n", address, disbuf, instbuf.immed); |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1490 } else { |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1491 printf("%X\t%s\n", address, disbuf); |
267
1788e3f29c28
Don't mix *H regs with the REX prefix
Mike Pavone <pavone@retrodev.com>
parents:
266
diff
changeset
|
1492 } |
268
6c2d7e003a55
Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents:
267
diff
changeset
|
1493 #endif |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1494 if (orig_size != ZMAX_NATIVE_SIZE) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1495 if (dst_end - dst < ZMAX_NATIVE_SIZE) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1496 size_t size = 1024*1024; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1497 dst = alloc_code(&size); |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1498 opts->code_end = dst_end = dst + size; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1499 opts->cur_code = dst; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1500 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1501 uint8_t * native_end = translate_z80inst(&instbuf, dst, context, address); |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1502 if ((native_end - dst) <= orig_size) { |
264
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1503 uint8_t * native_next = z80_get_native_address(context, address + after-inst); |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1504 if (native_next && ((native_next == orig_start + orig_size) || (orig_size - (native_end - dst)) > 5)) { |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1505 native_end = translate_z80inst(&instbuf, orig_start, context, address); |
266
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1506 if (native_next == orig_start + orig_size && (native_next-native_end) < 2) { |
264
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1507 while (native_end < orig_start + orig_size) { |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1508 *(native_end++) = 0x90; //NOP |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1509 } |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1510 } else { |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1511 jmp(native_end, native_next); |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1512 } |
266
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1513 z80_handle_deferred(context); |
264
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1514 return orig_start; |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1515 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1516 } |
264
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
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1517 z80_map_native_address(context, address, dst, after-inst, ZMAX_NATIVE_SIZE); |
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|
1518 opts->cur_code = dst+ZMAX_NATIVE_SIZE; |
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Fix some more retranslation bugs in the Z80 core
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diff
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|
1519 jmp(orig_start, dst); |
264
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|
1520 if(!(instbuf.op == Z80_RET || instbuf.op == Z80_RETI || instbuf.op == Z80_RETN || instbuf.op == Z80_JP || (instbuf.op == Z80_NOP && instbuf.immed == 42))) { |
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|
1521 jmp(native_end, z80_get_native_address_trans(context, address + after-inst)); |
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|
1522 } |
266
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diff
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|
1523 z80_handle_deferred(context); |
264
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|
1524 return dst; |
252
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Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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|
1525 } else { |
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Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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|
1526 dst = translate_z80inst(&instbuf, orig_start, context, address); |
254
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Fix bug in end condition inside translate_z80_stream.
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|
1527 if(!(instbuf.op == Z80_RET || instbuf.op == Z80_RETI || instbuf.op == Z80_RETN || instbuf.op == Z80_JP || (instbuf.op == Z80_NOP && instbuf.immed == 42))) { |
264
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|
1528 dst = jmp(dst, z80_get_native_address_trans(context, address + after-inst)); |
252
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|
1529 } |
266
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|
1530 z80_handle_deferred(context); |
252
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Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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|
1531 return orig_start; |
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Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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|
1532 } |
235
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|
1533 } |
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|
1534 |
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|
1535 void translate_z80_stream(z80_context * context, uint32_t address) |
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|
1536 { |
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|
1537 char disbuf[80]; |
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Get Z80 core working for simple programs
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|
1538 if (z80_get_native_address(context, address)) { |
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|
1539 return; |
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|
1540 } |
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|
1541 x86_z80_options * opts = context->options; |
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|
1542 uint8_t * encoded = NULL, *next; |
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|
1543 if (address < 0x4000) { |
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|
1544 encoded = context->mem_pointers[0] + (address & 0x1FFF); |
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|
1545 } else if(address >= 0x8000 && context->mem_pointers[1]) { |
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|
1546 encoded = context->mem_pointers[1] + (address & 0x7FFF); |
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|
1547 } |
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|
1548 while (encoded != NULL) |
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diff
changeset
|
1549 { |
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diff
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|
1550 z80inst inst; |
268
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|
1551 dprintf("translating Z80 code at address %X\n", address); |
235
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|
1552 do { |
252
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|
1553 if (opts->code_end-opts->cur_code < ZMAX_NATIVE_SIZE) { |
235
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|
1554 if (opts->code_end-opts->cur_code < 5) { |
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diff
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|
1555 puts("out of code memory, not enough space for jmp to next chunk"); |
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diff
changeset
|
1556 exit(1); |
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diff
changeset
|
1557 } |
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|
1558 size_t size = 1024*1024; |
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|
1559 opts->cur_code = alloc_code(&size); |
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|
1560 opts->code_end = opts->cur_code + size; |
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|
1561 jmp(opts->cur_code, opts->cur_code); |
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diff
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|
1562 } |
255
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|
1563 if (address > 0x4000 && address < 0x8000) { |
235
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|
1564 opts->cur_code = xor_rr(opts->cur_code, RDI, RDI, SZ_D); |
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|
1565 opts->cur_code = call(opts->cur_code, (uint8_t *)exit); |
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diff
changeset
|
1566 break; |
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changeset
|
1567 } |
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|
1568 uint8_t * existing = z80_get_native_address(context, address); |
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diff
changeset
|
1569 if (existing) { |
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diff
changeset
|
1570 opts->cur_code = jmp(opts->cur_code, existing); |
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changeset
|
1571 break; |
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diff
changeset
|
1572 } |
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|
1573 next = z80_decode(encoded, &inst); |
268
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|
1574 #ifdef DO_DEBUG_PRINT |
235
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|
1575 z80_disasm(&inst, disbuf); |
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|
1576 if (inst.op == Z80_NOP) { |
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diff
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|
1577 printf("%X\t%s(%d)\n", address, disbuf, inst.immed); |
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|
1578 } else { |
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|
1579 printf("%X\t%s\n", address, disbuf); |
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diff
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|
1580 } |
268
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|
1581 #endif |
248
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Implement ADC and SBC in Z80 core (untested)
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|
1582 uint8_t *after = translate_z80inst(&inst, opts->cur_code, context, address); |
252
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|
1583 z80_map_native_address(context, address, opts->cur_code, next-encoded, after - opts->cur_code); |
248
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1584 opts->cur_code = after; |
235
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1585 address += next-encoded; |
255
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|
1586 if (address > 0xFFFF) { |
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|
1587 address &= 0xFFFF; |
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|
1588 |
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|
1589 } else { |
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|
1590 encoded = next; |
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|
1591 } |
254
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|
1592 } while (!(inst.op == Z80_RET || inst.op == Z80_RETI || inst.op == Z80_RETN || inst.op == Z80_JP || (inst.op == Z80_NOP && inst.immed == 42))); |
235
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|
1593 process_deferred(&opts->deferred, context, (native_addr_func)z80_get_native_address); |
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|
1594 if (opts->deferred) { |
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|
1595 address = opts->deferred->address; |
268
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|
1596 dprintf("defferred address: %X\n", address); |
235
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|
1597 if (address < 0x4000) { |
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|
1598 encoded = context->mem_pointers[0] + (address & 0x1FFF); |
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|
1599 } else if (address > 0x8000 && context->mem_pointers[1]) { |
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|
1600 encoded = context->mem_pointers[1] + (address & 0x7FFF); |
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|
1601 } else { |
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|
1602 printf("attempt to translate non-memory address: %X\n", address); |
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|
1603 exit(1); |
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|
1604 } |
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|
1605 } else { |
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|
1606 encoded = NULL; |
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|
1607 } |
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|
1608 } |
213
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changeset
|
1609 } |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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|
1610 |
235
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|
1611 void init_x86_z80_opts(x86_z80_options * options) |
213
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|
1612 { |
235
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1613 options->flags = 0; |
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1614 options->regs[Z80_B] = BH; |
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1615 options->regs[Z80_C] = RBX; |
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1616 options->regs[Z80_D] = CH; |
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1617 options->regs[Z80_E] = RCX; |
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1618 options->regs[Z80_H] = AH; |
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1619 options->regs[Z80_L] = RAX; |
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1620 options->regs[Z80_IXH] = DH; |
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1621 options->regs[Z80_IXL] = RDX; |
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|
1622 options->regs[Z80_IYH] = -1; |
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1623 options->regs[Z80_IYL] = R8; |
235
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1624 options->regs[Z80_I] = -1; |
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1625 options->regs[Z80_R] = -1; |
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1626 options->regs[Z80_A] = R10; |
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1627 options->regs[Z80_BC] = RBX; |
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1628 options->regs[Z80_DE] = RCX; |
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1629 options->regs[Z80_HL] = RAX; |
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1630 options->regs[Z80_SP] = R9; |
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1631 options->regs[Z80_AF] = -1; |
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1632 options->regs[Z80_IX] = RDX; |
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1633 options->regs[Z80_IY] = R8; |
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1634 size_t size = 1024 * 1024; |
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1635 options->cur_code = alloc_code(&size); |
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1636 options->code_end = options->cur_code + size; |
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1637 options->ram_inst_sizes = malloc(sizeof(uint8_t) * 0x2000); |
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1638 memset(options->ram_inst_sizes, 0, sizeof(uint8_t) * 0x2000); |
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1639 options->deferred = NULL; |
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1640 } |
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1641 |
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1642 void init_z80_context(z80_context * context, x86_z80_options * options) |
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1643 { |
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1644 memset(context, 0, sizeof(*context)); |
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1645 context->static_code_map = malloc(sizeof(context->static_code_map)); |
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1646 context->static_code_map->base = NULL; |
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1647 context->static_code_map->offsets = malloc(sizeof(int32_t) * 0x2000); |
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1648 memset(context->static_code_map->offsets, 0xFF, sizeof(int32_t) * 0x2000); |
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1649 context->banked_code_map = malloc(sizeof(native_map_slot) * (1 << 9)); |
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1650 memset(context->banked_code_map, 0, sizeof(native_map_slot) * (1 << 9)); |
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1651 context->options = options; |
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1652 } |
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1653 |
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1654 void z80_reset(z80_context * context) |
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1655 { |
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1656 context->im = 0; |
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1657 context->iff1 = context->iff2 = 0; |
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1658 context->native_pc = z80_get_native_address_trans(context, 0); |
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1659 context->extra_pc = NULL; |
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1660 } |
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1661 |
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1662 |