Mercurial > repos > blastem
annotate vdp.c @ 1053:b86c3ce007d9
Implemented undocumented flag bits for rotate instructions
author | Michael Pavone <pavone@retrodev.com> |
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date | Fri, 29 Jul 2016 09:23:59 -0700 |
parents | 679137a0e78e |
children | fa6fe03f218a |
rev | line source |
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467
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Added copyright notice to source files and added GPL license text in COPYING
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1 /* |
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2 Copyright 2013 Michael Pavone |
470
541c1ae8abf3
Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
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3 This file is part of BlastEm. |
467
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4 BlastEm is free software distributed under the terms of the GNU General Public License version 3 or greater. See COPYING for full license text. |
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5 */ |
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6 #include "vdp.h" |
75 | 7 #include "blastem.h" |
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8 #include <stdlib.h> |
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9 #include <string.h> |
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10 #include "render.h" |
991
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Properly emulate machine freeze when reading from VDP while configured for writes
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11 #include "util.h" |
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12 |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
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13 #define NTSC_INACTIVE_START 224 |
b76d2a628ab9
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14 #define PAL_INACTIVE_START 240 |
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15 #define BUF_BIT_PRIORITY 0x40 |
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16 #define MAP_BIT_PRIORITY 0x8000 |
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17 #define MAP_BIT_H_FLIP 0x800 |
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18 #define MAP_BIT_V_FLIP 0x1000 |
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19 |
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20 #define SCROLL_BUFFER_SIZE 32 |
436
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Implement the scroll ring buffer properly without memcpy
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21 #define SCROLL_BUFFER_MASK (SCROLL_BUFFER_SIZE-1) |
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22 #define SCROLL_BUFFER_DRAW (SCROLL_BUFFER_SIZE/2) |
39
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23 |
328
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24 #define MCLKS_SLOT_H40 16 |
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25 #define MCLKS_SLOT_H32 20 |
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Fix some stuff with interrupt timing. The change in adjust_int_cycle gets Overdrive working again (vint was not being preferred over hint in some cases). One of the changes seems to have broken Fatal Rewind again, but no other regressions that I can see.
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26 #define VINT_SLOT_H40 255 //21 slots before HSYNC, 16 during, 10 after |
2bc27415565b
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27 #define VINT_SLOT_H32 255 //old value was 23, but recent tests suggest the actual value is close to the H40 one |
922
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Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
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28 #define HSYNC_SLOT_H40 228 |
697
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Sync fixes and logging to fix more sync issues
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29 #define HSYNC_END_H40 (HSYNC_SLOT_H40+17) |
331
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Fixup VINT cycle and HBLANK flag for the previous timing fixes
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30 #define HSYNC_END_H32 (33 * MCLKS_SLOT_H32) |
647
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Fix the HV counter and adjust the slots of certain VDP events
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31 #define HBLANK_START_H40 178 //should be 179 according to Nemesis, but 178 seems to fit slightly better with my test ROM results |
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32 #define HBLANK_END_H40 0 //should be 5.5 according to Nemesis, but 0 seems to fit better with my test ROM results |
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33 #define HBLANK_START_H32 233 //should be 147 according to Nemesis which is very different from my test ROM result |
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34 #define HBLANK_END_H32 0 //should be 5 according to Nemesis, but 0 seems to fit better with my test ROM results |
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35 #define LINE_CHANGE_H40 165 |
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36 #define LINE_CHANGE_H32 132 |
717
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
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37 #define VBLANK_START_H40 (LINE_CHANGE_H40+2) |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
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38 #define VBLANK_START_H32 (LINE_CHANGE_H32+2) |
460
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Implement FIFO latency and improve DMA accuracy
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39 #define FIFO_LATENCY 3 |
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40 |
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41 int32_t color_map[1 << 12]; |
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42 uint8_t levels[] = {0, 27, 49, 71, 87, 103, 119, 130, 146, 157, 174, 190, 206, 228, 255}; |
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43 |
437
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44 uint8_t debug_base[][3] = { |
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45 {127, 127, 127}, //BG |
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46 {0, 0, 127}, //A |
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47 {127, 0, 0}, //Window |
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48 {0, 127, 0}, //B |
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49 {127, 0, 127} //Sprites |
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50 }; |
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51 |
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52 uint8_t color_map_init_done; |
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53 |
623
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Fix most of the breakage caused by the vcounter/hcounter changes
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54 void init_vdp_context(vdp_context * context, uint8_t region_pal) |
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55 { |
58
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Properly zero-init all VDP buffers. Comment out some debug printfs.
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56 memset(context, 0, sizeof(*context)); |
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57 context->vdpmem = malloc(VRAM_SIZE); |
58
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58 memset(context->vdpmem, 0, VRAM_SIZE); |
505
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The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
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59 /* |
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60 */ |
505
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The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
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61 if (headless) { |
b7b7a1cab44a
The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
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62 context->oddbuf = context->framebuf = malloc(FRAMEBUF_ENTRIES * (32 / 8)); |
b7b7a1cab44a
The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
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63 memset(context->framebuf, 0, FRAMEBUF_ENTRIES * (32 / 8)); |
b7b7a1cab44a
The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
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64 context->evenbuf = malloc(FRAMEBUF_ENTRIES * (32 / 8)); |
b7b7a1cab44a
The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
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65 memset(context->evenbuf, 0, FRAMEBUF_ENTRIES * (32 / 8)); |
b7b7a1cab44a
The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
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66 } else { |
b7b7a1cab44a
The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
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67 render_alloc_surfaces(context); |
b7b7a1cab44a
The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
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68 } |
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69 context->framebuf = context->oddbuf; |
39
3c69319269ef
Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should
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70 context->linebuf = malloc(LINEBUF_SIZE + SCROLL_BUFFER_SIZE*2); |
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3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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71 memset(context->linebuf, 0, LINEBUF_SIZE + SCROLL_BUFFER_SIZE*2); |
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72 context->tmp_buf_a = context->linebuf + LINEBUF_SIZE; |
39
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73 context->tmp_buf_b = context->tmp_buf_a + SCROLL_BUFFER_SIZE; |
26
a7c2b92d8056
Fix management of context->sprite_draws so the sprite layer only draws when it should
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74 context->sprite_draws = MAX_DRAWS; |
471
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75 context->fifo_write = 0; |
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76 context->fifo_read = -1; |
995
2bc27415565b
Fix some stuff with interrupt timing. The change in adjust_int_cycle gets Overdrive working again (vint was not being preferred over hint in some cases). One of the changes seems to have broken Fatal Rewind again, but no other regressions that I can see.
Michael Pavone <pavone@retrodev.com>
parents:
991
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77 context->regs[REG_HINT] = context->hint_counter = 0xFF; |
505
b7b7a1cab44a
The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents:
503
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78 |
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79 if (!color_map_init_done) { |
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80 uint8_t b,g,r; |
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81 for (uint16_t color = 0; color < (1 << 12); color++) { |
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82 if (color & FBUF_SHADOW) { |
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83 b = levels[(color >> 9) & 0x7]; |
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84 g = levels[(color >> 5) & 0x7]; |
add9e2f5c0e3
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85 r = levels[(color >> 1) & 0x7]; |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
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86 } else if(color & FBUF_HILIGHT) { |
add9e2f5c0e3
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87 b = levels[((color >> 9) & 0x7) + 7]; |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
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88 g = levels[((color >> 5) & 0x7) + 7]; |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
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89 r = levels[((color >> 1) & 0x7) + 7]; |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
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90 } else { |
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91 b = levels[(color >> 8) & 0xE]; |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
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92 g = levels[(color >> 4) & 0xE]; |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
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93 r = levels[color & 0xE]; |
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94 } |
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95 color_map[color] = render_map_color(r, g, b); |
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96 } |
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97 color_map_init_done = 1; |
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98 } |
437
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99 for (uint8_t color = 0; color < (1 << (3 + 1 + 1 + 1)); color++) |
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100 { |
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101 uint8_t src = color & DBG_SRC_MASK; |
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102 if (src > DBG_SRC_S) { |
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103 context->debugcolors[color] = 0; |
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104 } else { |
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105 uint8_t r,g,b; |
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106 b = debug_base[src][0]; |
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107 g = debug_base[src][1]; |
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108 r = debug_base[src][2]; |
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109 if (color & DBG_PRIORITY) |
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110 { |
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111 if (b) { |
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112 b += 48; |
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113 } |
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114 if (g) { |
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115 g += 48; |
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116 } |
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117 if (r) { |
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118 r += 48; |
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119 } |
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120 } |
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121 if (color & DBG_SHADOW) { |
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122 b /= 2; |
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123 g /= 2; |
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124 r /=2 ; |
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125 } |
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126 if (color & DBG_HILIGHT) { |
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127 if (b) { |
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128 b += 72; |
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129 } |
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130 if (g) { |
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131 g += 72; |
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132 } |
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133 if (r) { |
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134 r += 72; |
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135 } |
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136 } |
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137 context->debugcolors[color] = render_map_color(r, g, b); |
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138 } |
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139 } |
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140 if (region_pal) { |
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141 context->flags2 |= FLAG2_REGION_PAL; |
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142 } |
20
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143 } |
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144 |
884
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145 void vdp_free(vdp_context *context) |
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146 { |
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147 free(context->vdpmem); |
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148 free(context->linebuf); |
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149 if (headless) { |
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150 free(context->oddbuf); |
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151 free(context->evenbuf); |
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152 } else { |
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153 render_free_surfaces(context); |
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154 } |
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155 free(context); |
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156 } |
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157 |
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158 int is_refresh(vdp_context * context, uint32_t slot) |
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159 { |
622
b76d2a628ab9
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160 if (context->regs[REG_MODE_4] & BIT_H40) { |
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161 return slot == 250 || slot == 26 || slot == 59 || slot == 90 || slot == 122 || slot == 154; |
460
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162 } else { |
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163 //TODO: Figure out which slots are refresh when display is off in 32-cell mode |
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164 //These numbers are guesses based on H40 numbers |
622
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Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
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|
165 return slot == 243 || slot == 19 || slot == 51 || slot == 83 || slot == 115; |
460
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166 //The numbers below are the refresh slots during active display |
622
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Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
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621
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|
167 //return (slot == 29 || slot == 61 || slot == 93 || slot == 125); |
460
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|
168 } |
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|
169 } |
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|
170 |
21
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20
diff
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|
171 void render_sprite_cells(vdp_context * context) |
20
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|
172 { |
21
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20
diff
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|
173 if (context->cur_slot >= context->sprite_draws) { |
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20
diff
changeset
|
174 sprite_draw * d = context->sprite_draw_list + context->cur_slot; |
450
3758bcdae5de
Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty
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parents:
438
diff
changeset
|
175 |
20
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diff
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|
176 uint16_t dir; |
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|
177 int16_t x; |
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|
178 if (d->h_flip) { |
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|
179 x = d->x_pos + 7; |
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diff
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|
180 dir = -1; |
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|
181 } else { |
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|
182 x = d->x_pos; |
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|
183 dir = 1; |
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diff
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|
184 } |
27
aa1c47fab3f1
Fix sprite transparency for overlapping sprites
Mike Pavone <pavone@retrodev.com>
parents:
26
diff
changeset
|
185 //printf("Draw Slot %d of %d, Rendering sprite cell from %X to x: %d\n", context->cur_slot, context->sprite_draws, d->address, x); |
26
a7c2b92d8056
Fix management of context->sprite_draws so the sprite layer only draws when it should
Mike Pavone <pavone@retrodev.com>
parents:
25
diff
changeset
|
186 context->cur_slot--; |
143
e5487ef04619
Fix infinite loop bug in sprite rendering
Mike Pavone <pavone@retrodev.com>
parents:
142
diff
changeset
|
187 for (uint16_t address = d->address; address != ((d->address+4) & 0xFFFF); address++) { |
1029
4263dc9cf86d
Fix implementation of sprite collision flag. Old implementation did not make sense.
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1019
diff
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|
188 if (x >= 0 && x < 320) { |
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|
189 if (!(context->linebuf[x] & 0xF)) { |
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|
190 context->linebuf[x] = (context->vdpmem[address] >> 4) | d->pal_priority; |
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|
191 } else if (context->vdpmem[address] >> 4) { |
494
8ac0eb05642c
Initial implementation of sprite overflow and sprite collision status register flags
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481
diff
changeset
|
192 context->flags2 |= FLAG2_SPRITE_COLLIDE; |
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481
diff
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|
193 } |
20
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|
194 } |
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|
195 x += dir; |
1029
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|
196 if (x >= 0 && x < 320) { |
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|
197 if (!(context->linebuf[x] & 0xF)) { |
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|
198 context->linebuf[x] = (context->vdpmem[address] & 0xF) | d->pal_priority; |
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|
199 } else if (context->vdpmem[address] & 0xF) { |
494
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481
diff
changeset
|
200 context->flags2 |= FLAG2_SPRITE_COLLIDE; |
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481
diff
changeset
|
201 } |
20
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diff
changeset
|
202 } |
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diff
changeset
|
203 x += dir; |
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diff
changeset
|
204 } |
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diff
changeset
|
205 } |
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diff
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|
206 } |
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diff
changeset
|
207 |
322
8e2fa485c0f2
Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview.
Mike Pavone <pavone@retrodev.com>
parents:
318
diff
changeset
|
208 void vdp_print_sprite_table(vdp_context * context) |
8e2fa485c0f2
Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview.
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parents:
318
diff
changeset
|
209 { |
8e2fa485c0f2
Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview.
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parents:
318
diff
changeset
|
210 uint16_t sat_address = (context->regs[REG_SAT] & 0x7F) << 9; |
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211 uint16_t current_index = 0; |
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212 uint8_t count = 0; |
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213 do { |
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214 uint16_t address = current_index * 8 + sat_address; |
998
bf63cbf1d7bb
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215 uint16_t cache_address = current_index * 4; |
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216 uint8_t height = ((context->sat_cache[cache_address+2] & 0x3) + 1) * 8; |
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217 uint8_t width = (((context->sat_cache[cache_address+2] >> 2) & 0x3) + 1) * 8; |
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218 int16_t y = ((context->sat_cache[cache_address] & 0x3) << 8 | context->sat_cache[cache_address+1]) & 0x1FF; |
323
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219 int16_t x = ((context->vdpmem[address+ 6] & 0x3) << 8 | context->vdpmem[address + 7]) & 0x1FF; |
998
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220 uint16_t link = context->sat_cache[cache_address+3] & 0x7F; |
323
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221 uint8_t pal = context->vdpmem[address + 4] >> 5 & 0x3; |
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222 uint8_t pri = context->vdpmem[address + 4] >> 7; |
450
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223 uint16_t pattern = ((context->vdpmem[address + 4] << 8 | context->vdpmem[address + 5]) & 0x7FF) << 5; |
515
1495179d6737
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224 printf("Sprite %d: X=%d(%d), Y=%d(%d), Width=%u, Height=%u, Link=%u, Pal=%u, Pri=%u, Pat=%X\n", current_index, x, x-128, y, y-128, width, height, link, pal, pri, pattern); |
322
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225 current_index = link; |
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226 count++; |
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227 } while (current_index != 0 && count < 80); |
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228 } |
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229 |
705
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230 #define VRAM_READ 0 //0000 |
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231 #define VRAM_WRITE 1 //0001 |
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232 //2 would trigger register write 0010 |
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233 #define CRAM_WRITE 3 //0011 |
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234 #define VSRAM_READ 4 //0100 |
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235 #define VSRAM_WRITE 5//0101 |
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236 //6 would trigger regsiter write 0110 |
980
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237 //7 is a mystery //0111 |
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238 #define CRAM_READ 8 //1000 |
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239 //9 is also a mystery //1001 |
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240 //A would trigger register write 1010 |
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241 //B is a mystery 1011 |
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242 #define VRAM_READ8 0xC //1100 |
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243 //D is a mystery 1101 |
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244 //E would trigger register write 1110 |
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245 //F is a mystery 1111 |
980
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246 |
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247 //Possible theory on how bits work |
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248 //CD0 = Read/Write flag |
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249 //CD2,(CD1|CD3) = RAM type |
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250 // 00 = VRAM |
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251 // 01 = CRAM |
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252 // 10 = VSRAM |
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253 // 11 = VRAM8 |
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254 //Would result in |
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255 // 7 = VRAM8 write |
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256 // 9 = CRAM write alias |
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257 // B = CRAM write alias |
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258 // D = VRAM8 write alias |
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259 // F = VRAM8 write alais |
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260 |
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261 #define DMA_START 0x20 |
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262 |
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263 const char * cd_name(uint8_t cd) |
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264 { |
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265 switch (cd & 0xF) |
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266 { |
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267 case VRAM_READ: |
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268 return "VRAM read"; |
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269 case VRAM_WRITE: |
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270 return "VRAM write"; |
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271 case CRAM_WRITE: |
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272 return "CRAM write"; |
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273 case VSRAM_READ: |
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274 return "VSRAM read"; |
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275 case VSRAM_WRITE: |
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276 return "VSRAM write"; |
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277 case VRAM_READ8: |
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278 return "VRAM read (undocumented 8-bit mode)"; |
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279 default: |
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280 return "invalid"; |
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281 } |
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282 } |
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283 |
327
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284 void vdp_print_reg_explain(vdp_context * context) |
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285 { |
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286 char * hscroll[] = {"full", "7-line", "cell", "line"}; |
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287 printf("**Mode Group**\n" |
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288 "00: %.2X | H-ints %s, Pal Select %d, HVC latch %s, Display gen %s\n" |
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289 "01: %.2X | Display %s, V-ints %s, Height: %d, Mode %d\n" |
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290 "0B: %.2X | E-ints %s, V-Scroll: %s, H-Scroll: %s\n" |
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291 "0C: %.2X | Width: %d, Shadow/Highlight: %s\n", |
757
483f7e7926a6
More clang warning cleanup
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748
diff
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292 context->regs[REG_MODE_1], context->regs[REG_MODE_1] & BIT_HINT_EN ? "enabled" : "disabled", (context->regs[REG_MODE_1] & BIT_PAL_SEL) != 0, |
327
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293 context->regs[REG_MODE_1] & BIT_HVC_LATCH ? "enabled" : "disabled", context->regs[REG_MODE_1] & BIT_DISP_DIS ? "disabled" : "enabled", |
450
3758bcdae5de
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294 context->regs[REG_MODE_2], context->regs[REG_MODE_2] & BIT_DISP_EN ? "enabled" : "disabled", context->regs[REG_MODE_2] & BIT_VINT_EN ? "enabled" : "disabled", |
327
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295 context->regs[REG_MODE_2] & BIT_PAL ? 30 : 28, context->regs[REG_MODE_2] & BIT_MODE_5 ? 5 : 4, |
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296 context->regs[REG_MODE_3], context->regs[REG_MODE_3] & BIT_EINT_EN ? "enabled" : "disabled", context->regs[REG_MODE_3] & BIT_VSCROLL ? "2 cell" : "full", |
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297 hscroll[context->regs[REG_MODE_3] & 0x3], |
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298 context->regs[REG_MODE_4], context->regs[REG_MODE_4] & BIT_H40 ? 40 : 32, context->regs[REG_MODE_4] & BIT_HILIGHT ? "enabled" : "disabled"); |
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299 printf("\n**Table Group**\n" |
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323
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300 "02: %.2X | Scroll A Name Table: $%.4X\n" |
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301 "03: %.2X | Window Name Table: $%.4X\n" |
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302 "04: %.2X | Scroll B Name Table: $%.4X\n" |
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303 "05: %.2X | Sprite Attribute Table: $%.4X\n" |
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304 "0D: %.2X | HScroll Data Table: $%.4X\n", |
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305 context->regs[REG_SCROLL_A], (context->regs[REG_SCROLL_A] & 0x38) << 10, |
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|
306 context->regs[REG_WINDOW], (context->regs[REG_WINDOW] & (context->regs[REG_MODE_4] & BIT_H40 ? 0x3C : 0x3E)) << 10, |
1b00258b1f29
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307 context->regs[REG_SCROLL_B], (context->regs[REG_SCROLL_B] & 0x7) << 13, |
621
5196333b37a6
Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents:
515
diff
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|
308 context->regs[REG_SAT], (context->regs[REG_SAT] & (context->regs[REG_MODE_4] & BIT_H40 ? 0x7E : 0x7F)) << 9, |
5196333b37a6
Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents:
515
diff
changeset
|
309 context->regs[REG_HSCROLL], (context->regs[REG_HSCROLL] & 0x3F) << 10); |
327
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
310 char * sizes[] = {"32", "64", "invalid", "128"}; |
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
311 printf("\n**Misc Group**\n" |
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
312 "07: %.2X | Backdrop Color: $%X\n" |
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
313 "0A: %.2X | H-Int Counter: %u\n" |
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
314 "0F: %.2X | Auto-increment: $%X\n" |
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
315 "10: %.2X | Scroll A/B Size: %sx%s\n", |
505
b7b7a1cab44a
The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents:
503
diff
changeset
|
316 context->regs[REG_BG_COLOR], context->regs[REG_BG_COLOR], |
450
3758bcdae5de
Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty
Mike Pavone <pavone@retrodev.com>
parents:
438
diff
changeset
|
317 context->regs[REG_HINT], context->regs[REG_HINT], |
327
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
318 context->regs[REG_AUTOINC], context->regs[REG_AUTOINC], |
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
319 context->regs[REG_SCROLL], sizes[context->regs[REG_SCROLL] & 0x3], sizes[context->regs[REG_SCROLL] >> 4 & 0x3]); |
621
5196333b37a6
Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents:
515
diff
changeset
|
320 char * src_types[] = {"68K", "68K", "Copy", "Fill"}; |
5196333b37a6
Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents:
515
diff
changeset
|
321 printf("\n**DMA Group**\n" |
5196333b37a6
Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents:
515
diff
changeset
|
322 "13: %.2X |\n" |
5196333b37a6
Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents:
515
diff
changeset
|
323 "14: %.2X | DMA Length: $%.4X words\n" |
5196333b37a6
Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents:
515
diff
changeset
|
324 "15: %.2X |\n" |
5196333b37a6
Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents:
515
diff
changeset
|
325 "16: %.2X |\n" |
5196333b37a6
Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents:
515
diff
changeset
|
326 "17: %.2X | DMA Source Address: $%.6X, Type: %s\n", |
5196333b37a6
Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents:
515
diff
changeset
|
327 context->regs[REG_DMALEN_L], |
5196333b37a6
Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents:
515
diff
changeset
|
328 context->regs[REG_DMALEN_H], context->regs[REG_DMALEN_H] << 8 | context->regs[REG_DMALEN_L], |
5196333b37a6
Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents:
515
diff
changeset
|
329 context->regs[REG_DMASRC_L], |
5196333b37a6
Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents:
515
diff
changeset
|
330 context->regs[REG_DMASRC_M], |
5196333b37a6
Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents:
515
diff
changeset
|
331 context->regs[REG_DMASRC_H], |
629
9089951a1994
Small fix to display of DMA source address in vr debug command
Michael Pavone <pavone@retrodev.com>
parents:
624
diff
changeset
|
332 context->regs[REG_DMASRC_H] << 17 | context->regs[REG_DMASRC_M] << 9 | context->regs[REG_DMASRC_L] << 1, |
621
5196333b37a6
Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents:
515
diff
changeset
|
333 src_types[context->regs[REG_DMASRC_H] >> 6 & 3]); |
438
b3cee2fe690b
Add address/cd registers to VDP debug message
Mike Pavone <pavone@retrodev.com>
parents:
437
diff
changeset
|
334 printf("\n**Internal Group**\n" |
b3cee2fe690b
Add address/cd registers to VDP debug message
Mike Pavone <pavone@retrodev.com>
parents:
437
diff
changeset
|
335 "Address: %X\n" |
705
ce4046476abc
Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents:
699
diff
changeset
|
336 "CD: %X - %s\n" |
647
5d58dcd94733
Fix the HV counter and adjust the slots of certain VDP events
Michael Pavone <pavone@retrodev.com>
parents:
629
diff
changeset
|
337 "Pending: %s\n" |
5d58dcd94733
Fix the HV counter and adjust the slots of certain VDP events
Michael Pavone <pavone@retrodev.com>
parents:
629
diff
changeset
|
338 "VCounter: %d\n" |
995
2bc27415565b
Fix some stuff with interrupt timing. The change in adjust_int_cycle gets Overdrive working again (vint was not being preferred over hint in some cases). One of the changes seems to have broken Fatal Rewind again, but no other regressions that I can see.
Michael Pavone <pavone@retrodev.com>
parents:
991
diff
changeset
|
339 "HCounter: %d\n" |
2bc27415565b
Fix some stuff with interrupt timing. The change in adjust_int_cycle gets Overdrive working again (vint was not being preferred over hint in some cases). One of the changes seems to have broken Fatal Rewind again, but no other regressions that I can see.
Michael Pavone <pavone@retrodev.com>
parents:
991
diff
changeset
|
340 "VINT Pending: %s\n" |
2bc27415565b
Fix some stuff with interrupt timing. The change in adjust_int_cycle gets Overdrive working again (vint was not being preferred over hint in some cases). One of the changes seems to have broken Fatal Rewind again, but no other regressions that I can see.
Michael Pavone <pavone@retrodev.com>
parents:
991
diff
changeset
|
341 "HINT Pending: %s\n" |
2bc27415565b
Fix some stuff with interrupt timing. The change in adjust_int_cycle gets Overdrive working again (vint was not being preferred over hint in some cases). One of the changes seems to have broken Fatal Rewind again, but no other regressions that I can see.
Michael Pavone <pavone@retrodev.com>
parents:
991
diff
changeset
|
342 "Status: %X\n", |
705
ce4046476abc
Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents:
699
diff
changeset
|
343 context->address, context->cd, cd_name(context->cd), (context->flags & FLAG_PENDING) ? "true" : "false", |
995
2bc27415565b
Fix some stuff with interrupt timing. The change in adjust_int_cycle gets Overdrive working again (vint was not being preferred over hint in some cases). One of the changes seems to have broken Fatal Rewind again, but no other regressions that I can see.
Michael Pavone <pavone@retrodev.com>
parents:
991
diff
changeset
|
344 context->vcounter, context->hslot*2, (context->flags2 & FLAG2_VINT_PENDING) ? "true" : "false", |
2bc27415565b
Fix some stuff with interrupt timing. The change in adjust_int_cycle gets Overdrive working again (vint was not being preferred over hint in some cases). One of the changes seems to have broken Fatal Rewind again, but no other regressions that I can see.
Michael Pavone <pavone@retrodev.com>
parents:
991
diff
changeset
|
345 (context->flags2 & FLAG2_HINT_PENDING) ? "true" : "false", vdp_control_port_read(context)); |
450
3758bcdae5de
Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty
Mike Pavone <pavone@retrodev.com>
parents:
438
diff
changeset
|
346 |
3758bcdae5de
Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty
Mike Pavone <pavone@retrodev.com>
parents:
438
diff
changeset
|
347 //TODO: Window Group, DMA Group |
327
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
348 } |
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
349 |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
350 void scan_sprite_table(uint32_t line, vdp_context * context) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
351 { |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
352 if (context->sprite_index && context->slot_counter) { |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
353 line += 1; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
354 line &= 0xFF; |
413
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
355 uint16_t ymask, ymin; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
356 uint8_t height_mult; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
357 if (context->double_res) { |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
358 line *= 2; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
359 if (context->framebuf != context->oddbuf) { |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
360 line++; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
361 } |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
362 ymask = 0x3FF; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
363 ymin = 256; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
364 height_mult = 16; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
365 } else { |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
366 ymask = 0x1FF; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
367 ymin = 128; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
368 height_mult = 8; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
369 } |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
370 context->sprite_index &= 0x7F; |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
371 if (context->regs[REG_MODE_4] & BIT_H40) { |
38
898e3d035f42
Implement sprite index >= sprite limit triggers sprite limit behavior
Mike Pavone <pavone@retrodev.com>
parents:
37
diff
changeset
|
372 if (context->sprite_index >= MAX_SPRITES_FRAME) { |
898e3d035f42
Implement sprite index >= sprite limit triggers sprite limit behavior
Mike Pavone <pavone@retrodev.com>
parents:
37
diff
changeset
|
373 context->sprite_index = 0; |
898e3d035f42
Implement sprite index >= sprite limit triggers sprite limit behavior
Mike Pavone <pavone@retrodev.com>
parents:
37
diff
changeset
|
374 return; |
898e3d035f42
Implement sprite index >= sprite limit triggers sprite limit behavior
Mike Pavone <pavone@retrodev.com>
parents:
37
diff
changeset
|
375 } |
898e3d035f42
Implement sprite index >= sprite limit triggers sprite limit behavior
Mike Pavone <pavone@retrodev.com>
parents:
37
diff
changeset
|
376 } else if(context->sprite_index >= MAX_SPRITES_FRAME_H32) { |
898e3d035f42
Implement sprite index >= sprite limit triggers sprite limit behavior
Mike Pavone <pavone@retrodev.com>
parents:
37
diff
changeset
|
377 context->sprite_index = 0; |
898e3d035f42
Implement sprite index >= sprite limit triggers sprite limit behavior
Mike Pavone <pavone@retrodev.com>
parents:
37
diff
changeset
|
378 return; |
898e3d035f42
Implement sprite index >= sprite limit triggers sprite limit behavior
Mike Pavone <pavone@retrodev.com>
parents:
37
diff
changeset
|
379 } |
998
bf63cbf1d7bb
Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents:
995
diff
changeset
|
380 uint16_t address = context->sprite_index * 4; |
413
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
381 line += ymin; |
998
bf63cbf1d7bb
Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents:
995
diff
changeset
|
382 uint16_t y = ((context->sat_cache[address] & 0x3) << 8 | context->sat_cache[address+1]) & ymask; |
bf63cbf1d7bb
Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents:
995
diff
changeset
|
383 uint8_t height = ((context->sat_cache[address+2] & 0x3) + 1) * height_mult; |
21
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
384 //printf("Sprite %d | y: %d, height: %d\n", context->sprite_index, y, height); |
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
385 if (y <= line && line < (y + height)) { |
27
aa1c47fab3f1
Fix sprite transparency for overlapping sprites
Mike Pavone <pavone@retrodev.com>
parents:
26
diff
changeset
|
386 //printf("Sprite %d at y: %d with height %d is on line %d\n", context->sprite_index, y, height, line); |
998
bf63cbf1d7bb
Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents:
995
diff
changeset
|
387 context->sprite_info_list[--(context->slot_counter)].size = context->sat_cache[address+2]; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
388 context->sprite_info_list[context->slot_counter].index = context->sprite_index; |
413
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
389 context->sprite_info_list[context->slot_counter].y = y-ymin; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
390 } |
998
bf63cbf1d7bb
Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents:
995
diff
changeset
|
391 context->sprite_index = context->sat_cache[address+3] & 0x7F; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
392 if (context->sprite_index && context->slot_counter) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
393 { |
998
bf63cbf1d7bb
Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents:
995
diff
changeset
|
394 if (context->regs[REG_MODE_4] & BIT_H40) { |
bf63cbf1d7bb
Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents:
995
diff
changeset
|
395 if (context->sprite_index >= MAX_SPRITES_FRAME) { |
bf63cbf1d7bb
Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents:
995
diff
changeset
|
396 context->sprite_index = 0; |
bf63cbf1d7bb
Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents:
995
diff
changeset
|
397 return; |
bf63cbf1d7bb
Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents:
995
diff
changeset
|
398 } |
bf63cbf1d7bb
Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents:
995
diff
changeset
|
399 } else if(context->sprite_index >= MAX_SPRITES_FRAME_H32) { |
bf63cbf1d7bb
Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents:
995
diff
changeset
|
400 context->sprite_index = 0; |
bf63cbf1d7bb
Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents:
995
diff
changeset
|
401 return; |
bf63cbf1d7bb
Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents:
995
diff
changeset
|
402 } |
bf63cbf1d7bb
Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents:
995
diff
changeset
|
403 address = context->sprite_index * 4; |
bf63cbf1d7bb
Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents:
995
diff
changeset
|
404 y = ((context->sat_cache[address] & 0x3) << 8 | context->sat_cache[address+1]) & ymask; |
bf63cbf1d7bb
Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents:
995
diff
changeset
|
405 height = ((context->sat_cache[address+2] & 0x3) + 1) * height_mult; |
323
8c01b4154480
Properly mask sprite X and Y coordinates
Mike Pavone <pavone@retrodev.com>
parents:
322
diff
changeset
|
406 //printf("Sprite %d | y: %d, height: %d\n", context->sprite_index, y, height); |
21
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
407 if (y <= line && line < (y + height)) { |
27
aa1c47fab3f1
Fix sprite transparency for overlapping sprites
Mike Pavone <pavone@retrodev.com>
parents:
26
diff
changeset
|
408 //printf("Sprite %d at y: %d with height %d is on line %d\n", context->sprite_index, y, height, line); |
998
bf63cbf1d7bb
Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents:
995
diff
changeset
|
409 context->sprite_info_list[--(context->slot_counter)].size = context->sat_cache[address+2]; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
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parents:
diff
changeset
|
410 context->sprite_info_list[context->slot_counter].index = context->sprite_index; |
413
36fbbced25c2
Initial work on interlace
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parents:
337
diff
changeset
|
411 context->sprite_info_list[context->slot_counter].y = y-ymin; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
412 } |
998
bf63cbf1d7bb
Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents:
995
diff
changeset
|
413 context->sprite_index = context->sat_cache[address+3] & 0x7F; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
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parents:
diff
changeset
|
414 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
415 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
416 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
417 |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
418 void read_sprite_x(uint32_t line, vdp_context * context) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
419 { |
34
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
420 if (context->cur_slot >= context->slot_counter) { |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
421 if (context->sprite_draws) { |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
422 line += 1; |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
423 line &= 0xFF; |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
424 //in tiles |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
425 uint8_t width = ((context->sprite_info_list[context->cur_slot].size >> 2) & 0x3) + 1; |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
426 //in pixels |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
427 uint8_t height = ((context->sprite_info_list[context->cur_slot].size & 0x3) + 1) * 8; |
413
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
428 if (context->double_res) { |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
429 line *= 2; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
430 if (context->framebuf != context->oddbuf) { |
36fbbced25c2
Initial work on interlace
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parents:
337
diff
changeset
|
431 line++; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
432 } |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
433 height *= 2; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
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337
diff
changeset
|
434 } |
34
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
435 uint16_t att_addr = ((context->regs[REG_SAT] & 0x7F) << 9) + context->sprite_info_list[context->cur_slot].index * 8 + 4; |
450
3758bcdae5de
Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty
Mike Pavone <pavone@retrodev.com>
parents:
438
diff
changeset
|
436 uint16_t tileinfo = (context->vdpmem[att_addr] << 8) | context->vdpmem[att_addr+1]; |
34
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
437 uint8_t pal_priority = (tileinfo >> 9) & 0x70; |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
438 uint8_t row; |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
439 if (tileinfo & MAP_BIT_V_FLIP) { |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
440 row = (context->sprite_info_list[context->cur_slot].y + height - 1) - line; |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
441 } else { |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
442 row = line-context->sprite_info_list[context->cur_slot].y; |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
443 } |
413
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
444 uint16_t address; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
445 if (context->double_res) { |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
446 address = ((tileinfo & 0x3FF) << 6) + row * 4; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
447 } else { |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
448 address = ((tileinfo & 0x7FF) << 5) + row * 4; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
449 } |
323
8c01b4154480
Properly mask sprite X and Y coordinates
Mike Pavone <pavone@retrodev.com>
parents:
322
diff
changeset
|
450 int16_t x = ((context->vdpmem[att_addr+ 2] & 0x3) << 8 | context->vdpmem[att_addr + 3]) & 0x1FF; |
36
04672c060062
Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents:
35
diff
changeset
|
451 if (x) { |
04672c060062
Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents:
35
diff
changeset
|
452 context->flags |= FLAG_CAN_MASK; |
04672c060062
Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents:
35
diff
changeset
|
453 } else if(context->flags & (FLAG_CAN_MASK | FLAG_DOT_OFLOW)) { |
04672c060062
Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents:
35
diff
changeset
|
454 context->flags |= FLAG_MASKED; |
04672c060062
Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents:
35
diff
changeset
|
455 } |
450
3758bcdae5de
Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty
Mike Pavone <pavone@retrodev.com>
parents:
438
diff
changeset
|
456 |
36
04672c060062
Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents:
35
diff
changeset
|
457 context->flags &= ~FLAG_DOT_OFLOW; |
04672c060062
Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents:
35
diff
changeset
|
458 int16_t i; |
04672c060062
Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents:
35
diff
changeset
|
459 if (context->flags & FLAG_MASKED) { |
04672c060062
Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents:
35
diff
changeset
|
460 for (i=0; i < width && context->sprite_draws; i++) { |
04672c060062
Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents:
35
diff
changeset
|
461 --context->sprite_draws; |
04672c060062
Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents:
35
diff
changeset
|
462 context->sprite_draw_list[context->sprite_draws].x_pos = -128; |
34
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
463 } |
36
04672c060062
Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents:
35
diff
changeset
|
464 } else { |
34
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
465 x -= 128; |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
466 int16_t base_x = x; |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
467 int16_t dir; |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
468 if (tileinfo & MAP_BIT_H_FLIP) { |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
469 x += (width-1) * 8; |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
470 dir = -8; |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
471 } else { |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
472 dir = 8; |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
473 } |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
474 //printf("Sprite %d | x: %d, y: %d, width: %d, height: %d, pal_priority: %X, row: %d, tile addr: %X\n", context->sprite_info_list[context->cur_slot].index, x, context->sprite_info_list[context->cur_slot].y, width, height, pal_priority, row, address); |
35
233c7737c152
Small fix to overflow flag
Mike Pavone <pavone@retrodev.com>
parents:
34
diff
changeset
|
475 for (i=0; i < width && context->sprite_draws; i++, x += dir) { |
34
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
476 --context->sprite_draws; |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
477 context->sprite_draw_list[context->sprite_draws].address = address + i * height * 4; |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
478 context->sprite_draw_list[context->sprite_draws].x_pos = x; |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
479 context->sprite_draw_list[context->sprite_draws].pal_priority = pal_priority; |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
480 context->sprite_draw_list[context->sprite_draws].h_flip = (tileinfo & MAP_BIT_H_FLIP) ? 1 : 0; |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
481 } |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
482 } |
1000
1a797fcbb35f
Added TODO for hardware checking
Michael Pavone <pavone@retrodev.com>
parents:
999
diff
changeset
|
483 //Used to be i < width |
1a797fcbb35f
Added TODO for hardware checking
Michael Pavone <pavone@retrodev.com>
parents:
999
diff
changeset
|
484 //TODO: Confirm this is the right condition on hardware |
1a797fcbb35f
Added TODO for hardware checking
Michael Pavone <pavone@retrodev.com>
parents:
999
diff
changeset
|
485 if (!context->sprite_draws) { |
36
04672c060062
Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents:
35
diff
changeset
|
486 context->flags |= FLAG_DOT_OFLOW; |
04672c060062
Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents:
35
diff
changeset
|
487 } |
04672c060062
Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents:
35
diff
changeset
|
488 context->cur_slot--; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
489 } else { |
34
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
490 context->flags |= FLAG_DOT_OFLOW; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
491 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
492 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
493 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
494 |
427
2802318c14e1
Refactor duplicated CRAM writing code and fix a bug in the process
Mike Pavone <pavone@retrodev.com>
parents:
426
diff
changeset
|
495 void write_cram(vdp_context * context, uint16_t address, uint16_t value) |
2802318c14e1
Refactor duplicated CRAM writing code and fix a bug in the process
Mike Pavone <pavone@retrodev.com>
parents:
426
diff
changeset
|
496 { |
2802318c14e1
Refactor duplicated CRAM writing code and fix a bug in the process
Mike Pavone <pavone@retrodev.com>
parents:
426
diff
changeset
|
497 uint16_t addr = (address/2) & (CRAM_SIZE-1); |
2802318c14e1
Refactor duplicated CRAM writing code and fix a bug in the process
Mike Pavone <pavone@retrodev.com>
parents:
426
diff
changeset
|
498 context->cram[addr] = value; |
2802318c14e1
Refactor duplicated CRAM writing code and fix a bug in the process
Mike Pavone <pavone@retrodev.com>
parents:
426
diff
changeset
|
499 context->colors[addr] = color_map[value & 0xEEE]; |
2802318c14e1
Refactor duplicated CRAM writing code and fix a bug in the process
Mike Pavone <pavone@retrodev.com>
parents:
426
diff
changeset
|
500 context->colors[addr + CRAM_SIZE] = color_map[(value & 0xEEE) | FBUF_SHADOW]; |
2802318c14e1
Refactor duplicated CRAM writing code and fix a bug in the process
Mike Pavone <pavone@retrodev.com>
parents:
426
diff
changeset
|
501 context->colors[addr + CRAM_SIZE*2] = color_map[(value & 0xEEE) | FBUF_HILIGHT]; |
2802318c14e1
Refactor duplicated CRAM writing code and fix a bug in the process
Mike Pavone <pavone@retrodev.com>
parents:
426
diff
changeset
|
502 } |
2802318c14e1
Refactor duplicated CRAM writing code and fix a bug in the process
Mike Pavone <pavone@retrodev.com>
parents:
426
diff
changeset
|
503 |
980
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
504 #define CRAM_BITS 0xEEE |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
505 #define VSRAM_BITS 0x7FF |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
506 #define VSRAM_DIRTY_BITS 0xF800 |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
507 |
984
bd4d698d995b
FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents:
983
diff
changeset
|
508 void vdp_advance_dma(vdp_context * context) |
bd4d698d995b
FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents:
983
diff
changeset
|
509 { |
bd4d698d995b
FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents:
983
diff
changeset
|
510 context->regs[REG_DMASRC_L] += 1; |
bd4d698d995b
FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents:
983
diff
changeset
|
511 if (!context->regs[REG_DMASRC_L]) { |
bd4d698d995b
FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents:
983
diff
changeset
|
512 context->regs[REG_DMASRC_M] += 1; |
bd4d698d995b
FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents:
983
diff
changeset
|
513 } |
bd4d698d995b
FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents:
983
diff
changeset
|
514 context->address += context->regs[REG_AUTOINC]; |
bd4d698d995b
FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents:
983
diff
changeset
|
515 uint16_t dma_len = ((context->regs[REG_DMALEN_H] << 8) | context->regs[REG_DMALEN_L]) - 1; |
bd4d698d995b
FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents:
983
diff
changeset
|
516 context->regs[REG_DMALEN_H] = dma_len >> 8; |
bd4d698d995b
FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents:
983
diff
changeset
|
517 context->regs[REG_DMALEN_L] = dma_len; |
bd4d698d995b
FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents:
983
diff
changeset
|
518 if (!dma_len) { |
bd4d698d995b
FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents:
983
diff
changeset
|
519 context->flags &= ~FLAG_DMA_RUN; |
bd4d698d995b
FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents:
983
diff
changeset
|
520 context->cd &= 0xF; |
bd4d698d995b
FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents:
983
diff
changeset
|
521 } |
bd4d698d995b
FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents:
983
diff
changeset
|
522 } |
1019
e34334e6c682
Fix GST savestate loading to deal with SAT cache to fix sprite corruption on savestate load. Clear out Z80 native_pc so the Z80 state does not get hosed when loading a savestate while the emulator is already running
Michael Pavone <pavone@retrodev.com>
parents:
1001
diff
changeset
|
523 |
998
bf63cbf1d7bb
Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents:
995
diff
changeset
|
524 void write_vram_byte(vdp_context *context, uint16_t address, uint8_t value) |
bf63cbf1d7bb
Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents:
995
diff
changeset
|
525 { |
bf63cbf1d7bb
Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents:
995
diff
changeset
|
526 if (!(address & 4)) { |
bf63cbf1d7bb
Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents:
995
diff
changeset
|
527 uint16_t sat_address = (context->regs[REG_SAT] & 0x7F) << 9; |
1001
1dc749c9c0d9
Fix bug in SAT cache address calculation that caused a crash in Strider II
Michael Pavone <pavone@retrodev.com>
parents:
1000
diff
changeset
|
528 if(address >= sat_address && address < (sat_address + SAT_CACHE_SIZE*2)) { |
1dc749c9c0d9
Fix bug in SAT cache address calculation that caused a crash in Strider II
Michael Pavone <pavone@retrodev.com>
parents:
1000
diff
changeset
|
529 uint16_t cache_address = address - sat_address; |
1dc749c9c0d9
Fix bug in SAT cache address calculation that caused a crash in Strider II
Michael Pavone <pavone@retrodev.com>
parents:
1000
diff
changeset
|
530 cache_address = (cache_address & 3) | (cache_address >> 1 & 0x1FC); |
1dc749c9c0d9
Fix bug in SAT cache address calculation that caused a crash in Strider II
Michael Pavone <pavone@retrodev.com>
parents:
1000
diff
changeset
|
531 context->sat_cache[cache_address] = value; |
998
bf63cbf1d7bb
Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents:
995
diff
changeset
|
532 } |
bf63cbf1d7bb
Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents:
995
diff
changeset
|
533 } |
bf63cbf1d7bb
Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents:
995
diff
changeset
|
534 context->vdpmem[address] = value; |
bf63cbf1d7bb
Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents:
995
diff
changeset
|
535 } |
bf63cbf1d7bb
Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents:
995
diff
changeset
|
536 |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
537 void external_slot(vdp_context * context) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
538 { |
984
bd4d698d995b
FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents:
983
diff
changeset
|
539 if ((context->flags & FLAG_DMA_RUN) && (context->regs[REG_DMASRC_H] & 0xC0) == 0x80 && context->fifo_read < 0) { |
bd4d698d995b
FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents:
983
diff
changeset
|
540 context->fifo_read = (context->fifo_write-1) & (FIFO_SIZE-1); |
bd4d698d995b
FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents:
983
diff
changeset
|
541 fifo_entry * cur = context->fifo + context->fifo_read; |
bd4d698d995b
FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents:
983
diff
changeset
|
542 cur->cycle = context->cycles; |
bd4d698d995b
FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents:
983
diff
changeset
|
543 cur->address = context->address; |
bd4d698d995b
FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents:
983
diff
changeset
|
544 cur->partial = 2; |
bd4d698d995b
FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents:
983
diff
changeset
|
545 vdp_advance_dma(context); |
bd4d698d995b
FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents:
983
diff
changeset
|
546 } |
471
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
547 fifo_entry * start = context->fifo + context->fifo_read; |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
548 if (context->fifo_read >= 0 && start->cycle <= context->cycles) { |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
549 switch (start->cd & 0xF) |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
550 { |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
551 case VRAM_WRITE: |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
552 if (start->partial) { |
471
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
553 //printf("VRAM Write: %X to %X at %d (line %d, slot %d)\n", start->value, start->address ^ 1, context->cycles, context->cycles/MCLKS_LINE, (context->cycles%MCLKS_LINE)/16); |
998
bf63cbf1d7bb
Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents:
995
diff
changeset
|
554 write_vram_byte(context, start->address ^ 1, start->partial == 2 ? start->value >> 8 : start->value); |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
555 } else { |
471
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
556 //printf("VRAM Write High: %X to %X at %d (line %d, slot %d)\n", start->value >> 8, start->address, context->cycles, context->cycles/MCLKS_LINE, (context->cycles%MCLKS_LINE)/16); |
998
bf63cbf1d7bb
Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents:
995
diff
changeset
|
557 write_vram_byte(context, start->address, start->value >> 8); |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
558 start->partial = 1; |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
559 //skip auto-increment and removal of entry from fifo |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
560 return; |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
561 } |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
562 break; |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
563 case CRAM_WRITE: { |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
564 //printf("CRAM Write | %X to %X\n", start->value, (start->address/2) & (CRAM_SIZE-1)); |
479
863e868752cf
Implement funny behavior for DMA fill to CRAM and VSRAM. Return VSRAM address 0 for reads to VSRAM at >= 40
Mike Pavone <pavone@retrodev.com>
parents:
478
diff
changeset
|
565 write_cram(context, start->address, start->partial == 2 ? context->fifo[context->fifo_write].value : start->value); |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
566 break; |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
567 } |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
568 case VSRAM_WRITE: |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
569 if (((start->address/2) & 63) < VSRAM_SIZE) { |
718
eaba6789f316
Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents:
717
diff
changeset
|
570 //printf("VSRAM Write: %X to %X @ vcounter: %d, hslot: %d, cycle: %d\n", start->value, context->address, context->vcounter, context->hslot, context->cycles); |
479
863e868752cf
Implement funny behavior for DMA fill to CRAM and VSRAM. Return VSRAM address 0 for reads to VSRAM at >= 40
Mike Pavone <pavone@retrodev.com>
parents:
478
diff
changeset
|
571 context->vsram[(start->address/2) & 63] = start->partial == 2 ? context->fifo[context->fifo_write].value : start->value; |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
572 } |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
573 |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
574 break; |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
575 } |
471
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
576 context->fifo_read = (context->fifo_read+1) & (FIFO_SIZE-1); |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
577 if (context->fifo_read == context->fifo_write) { |
983
14d2f3b0e45d
Fixes to the DMA busy flag and DMA fill. Now up to 120/122 on VDP FIFO Testing.
Michael Pavone <pavone@retrodev.com>
parents:
981
diff
changeset
|
578 if ((context->cd & 0x20) && (context->regs[REG_DMASRC_H] & 0xC0) == 0x80) { |
14d2f3b0e45d
Fixes to the DMA busy flag and DMA fill. Now up to 120/122 on VDP FIFO Testing.
Michael Pavone <pavone@retrodev.com>
parents:
981
diff
changeset
|
579 context->flags |= FLAG_DMA_RUN; |
14d2f3b0e45d
Fixes to the DMA busy flag and DMA fill. Now up to 120/122 on VDP FIFO Testing.
Michael Pavone <pavone@retrodev.com>
parents:
981
diff
changeset
|
580 } |
471
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
581 context->fifo_read = -1; |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
582 } |
980
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
583 } else if ((context->flags & FLAG_DMA_RUN) && (context->regs[REG_DMASRC_H] & 0xC0) == 0xC0) { |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
584 if (context->flags & FLAG_READ_FETCHED) { |
998
bf63cbf1d7bb
Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents:
995
diff
changeset
|
585 write_vram_byte(context, context->address ^ 1, context->prefetch); |
980
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
586 |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
587 //Update DMA state |
984
bd4d698d995b
FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents:
983
diff
changeset
|
588 vdp_advance_dma(context); |
980
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
589 |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
590 context->flags &= ~FLAG_READ_FETCHED; |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
591 } else { |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
592 context->prefetch = context->vdpmem[(context->regs[REG_DMASRC_M] << 8) | context->regs[REG_DMASRC_L] ^ 1]; |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
593 |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
594 context->flags |= FLAG_READ_FETCHED; |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
595 } |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
596 } else if (!(context->cd & 1) && !(context->flags & FLAG_READ_FETCHED)){ |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
597 switch(context->cd & 0xF) |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
598 { |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
599 case VRAM_READ: |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
600 if (context->flags2 & FLAG2_READ_PENDING) { |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
601 context->prefetch |= context->vdpmem[context->address | 1]; |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
602 context->flags |= FLAG_READ_FETCHED; |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
603 context->flags2 &= ~FLAG2_READ_PENDING; |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
604 //Should this happen after the prefetch or after the read? |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
605 //context->address += context->regs[REG_AUTOINC]; |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
606 } else { |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
607 context->prefetch = context->vdpmem[context->address & 0xFFFE] << 8; |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
608 context->flags2 |= FLAG2_READ_PENDING; |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
609 } |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
610 break; |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
611 case VRAM_READ8: |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
612 context->prefetch = context->vdpmem[context->address ^ 1]; |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
613 context->prefetch |= context->fifo[context->fifo_write].value & 0xFF00; |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
614 context->flags |= FLAG_READ_FETCHED; |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
615 //Should this happen after the prefetch or after the read? |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
616 //context->address += context->regs[REG_AUTOINC]; |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
617 break; |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
618 case CRAM_READ: |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
619 context->prefetch = context->cram[(context->address/2) & (CRAM_SIZE-1)] & CRAM_BITS; |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
620 context->prefetch |= context->fifo[context->fifo_write].value & ~CRAM_BITS; |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
621 context->flags |= FLAG_READ_FETCHED; |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
622 //Should this happen after the prefetch or after the read? |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
623 //context->address += context->regs[REG_AUTOINC]; |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
624 break; |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
625 case VSRAM_READ: { |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
626 uint16_t address = (context->address /2) & 63; |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
627 if (address >= VSRAM_SIZE) { |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
628 address = 0; |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
629 } |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
630 context->prefetch = context->vsram[address] & VSRAM_BITS; |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
631 context->prefetch |= context->fifo[context->fifo_write].value & VSRAM_DIRTY_BITS; |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
632 context->flags |= FLAG_READ_FETCHED; |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
633 //Should this happen after the prefetch or after the read? |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
634 //context->address += context->regs[REG_AUTOINC]; |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
635 break; |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
636 } |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
637 } |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
638 } |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
639 } |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
640 |
924
1b86268a4cb3
Change the sentinel value for the hslot parameter of run_dma_src to something that is not a valid slot number and actually use it for calls during the active display period
Michael Pavone <pavone@retrodev.com>
parents:
923
diff
changeset
|
641 void run_dma_src(vdp_context * context, int32_t slot) |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
642 { |
75 | 643 //TODO: Figure out what happens if CD bit 4 is not set in DMA copy mode |
644 //TODO: Figure out what happens when CD:0-3 is not set to a write mode in DMA operations | |
471
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
645 if (context->fifo_write == context->fifo_read) { |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
646 return; |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
647 } |
478
2e4a4188cfb0
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents:
477
diff
changeset
|
648 fifo_entry * cur = NULL; |
984
bd4d698d995b
FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents:
983
diff
changeset
|
649 if (!(context->regs[REG_DMASRC_H] & 0x80)) |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
650 { |
984
bd4d698d995b
FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents:
983
diff
changeset
|
651 //68K -> VDP |
924
1b86268a4cb3
Change the sentinel value for the hslot parameter of run_dma_src to something that is not a valid slot number and actually use it for calls during the active display period
Michael Pavone <pavone@retrodev.com>
parents:
923
diff
changeset
|
652 if (slot == -1 || !is_refresh(context, slot-1)) { |
478
2e4a4188cfb0
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents:
477
diff
changeset
|
653 cur = context->fifo + context->fifo_write; |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
654 cur->cycle = context->cycles + ((context->regs[REG_MODE_4] & BIT_H40) ? 16 : 20)*FIFO_LATENCY; |
478
2e4a4188cfb0
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents:
477
diff
changeset
|
655 cur->address = context->address; |
2e4a4188cfb0
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents:
477
diff
changeset
|
656 cur->value = read_dma_value((context->regs[REG_DMASRC_H] << 16) | (context->regs[REG_DMASRC_M] << 8) | context->regs[REG_DMASRC_L]); |
2e4a4188cfb0
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents:
477
diff
changeset
|
657 cur->cd = context->cd; |
2e4a4188cfb0
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents:
477
diff
changeset
|
658 cur->partial = 0; |
2e4a4188cfb0
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents:
477
diff
changeset
|
659 if (context->fifo_read < 0) { |
2e4a4188cfb0
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents:
477
diff
changeset
|
660 context->fifo_read = context->fifo_write; |
2e4a4188cfb0
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents:
477
diff
changeset
|
661 } |
2e4a4188cfb0
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents:
477
diff
changeset
|
662 context->fifo_write = (context->fifo_write + 1) & (FIFO_SIZE-1); |
984
bd4d698d995b
FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents:
983
diff
changeset
|
663 vdp_advance_dma(context); |
75 | 664 } |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
665 } |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
666 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
667 |
40 | 668 #define WINDOW_RIGHT 0x80 |
669 #define WINDOW_DOWN 0x80 | |
670 | |
25
4d0c20ad815a
Fix vertical scroll value for plane B
Mike Pavone <pavone@retrodev.com>
parents:
24
diff
changeset
|
671 void read_map_scroll(uint16_t column, uint16_t vsram_off, uint32_t line, uint16_t address, uint16_t hscroll_val, vdp_context * context) |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
672 { |
417
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
415
diff
changeset
|
673 uint16_t window_line_shift, v_offset_mask, vscroll_shift; |
414
51ee0f117365
Fix vscroll calculation in double resultion interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
413
diff
changeset
|
674 if (context->double_res) { |
413
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
675 line *= 2; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
676 if (context->framebuf != context->oddbuf) { |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
677 line++; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
678 } |
417
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
415
diff
changeset
|
679 window_line_shift = 4; |
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
415
diff
changeset
|
680 v_offset_mask = 0xF; |
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
415
diff
changeset
|
681 vscroll_shift = 4; |
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
415
diff
changeset
|
682 } else { |
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
415
diff
changeset
|
683 window_line_shift = 3; |
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
415
diff
changeset
|
684 v_offset_mask = 0x7; |
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
415
diff
changeset
|
685 vscroll_shift = 3; |
414
51ee0f117365
Fix vscroll calculation in double resultion interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
413
diff
changeset
|
686 } |
40 | 687 if (!vsram_off) { |
688 uint16_t left_col, right_col; | |
689 if (context->regs[REG_WINDOW_H] & WINDOW_RIGHT) { | |
920
e64168bb2b25
Fix calculation of window start column when it's on the right side. This removes graphical glitches in Afterburner 2, Fireshark and Dungeons and Dragons: Warriors of the Eternal Sun and probably others
Michael Pavone <pavone@retrodev.com>
parents:
884
diff
changeset
|
690 left_col = (context->regs[REG_WINDOW_H] & 0x1F) * 2 + 2; |
41
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
691 right_col = 42; |
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
692 } else { |
40 | 693 left_col = 0; |
694 right_col = (context->regs[REG_WINDOW_H] & 0x1F) * 2; | |
695 if (right_col) { | |
696 right_col += 2; | |
697 } | |
698 } | |
41
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
699 uint16_t top_line, bottom_line; |
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
700 if (context->regs[REG_WINDOW_V] & WINDOW_DOWN) { |
417
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
415
diff
changeset
|
701 top_line = (context->regs[REG_WINDOW_V] & 0x1F) << window_line_shift; |
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
415
diff
changeset
|
702 bottom_line = context->double_res ? 481 : 241; |
41
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
703 } else { |
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
704 top_line = 0; |
417
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
415
diff
changeset
|
705 bottom_line = (context->regs[REG_WINDOW_V] & 0x1F) << window_line_shift; |
41
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
706 } |
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
707 if ((column >= left_col && column < right_col) || (line >= top_line && line < bottom_line)) { |
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
708 uint16_t address = context->regs[REG_WINDOW] << 10; |
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
709 uint16_t line_offset, offset, mask; |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
710 if (context->regs[REG_MODE_4] & BIT_H40) { |
41
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
711 address &= 0xF000; |
417
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
415
diff
changeset
|
712 line_offset = (((line) >> vscroll_shift) * 64 * 2) & 0xFFF; |
41
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
713 mask = 0x7F; |
450
3758bcdae5de
Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty
Mike Pavone <pavone@retrodev.com>
parents:
438
diff
changeset
|
714 |
41
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
715 } else { |
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
716 address &= 0xF800; |
417
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
415
diff
changeset
|
717 line_offset = (((line) >> vscroll_shift) * 32 * 2) & 0xFFF; |
41
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
718 mask = 0x3F; |
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
719 } |
417
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
415
diff
changeset
|
720 if (context->double_res) { |
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
415
diff
changeset
|
721 mask <<= 1; |
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
415
diff
changeset
|
722 mask |= 1; |
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
415
diff
changeset
|
723 } |
42
6653e67a6811
Fix bug in tile address masking. Remove some debug code from window plane.
Mike Pavone <pavone@retrodev.com>
parents:
41
diff
changeset
|
724 offset = address + line_offset + (((column - 2) * 2) & mask); |
41
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
725 context->col_1 = (context->vdpmem[offset] << 8) | context->vdpmem[offset+1]; |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
726 //printf("Window | top: %d, bot: %d, left: %d, right: %d, base: %X, line: %X offset: %X, tile: %X, reg: %X\n", top_line, bottom_line, left_col, right_col, address, line_offset, offset, ((context->col_1 & 0x3FF) << 5), context->regs[REG_WINDOW]); |
42
6653e67a6811
Fix bug in tile address masking. Remove some debug code from window plane.
Mike Pavone <pavone@retrodev.com>
parents:
41
diff
changeset
|
727 offset = address + line_offset + (((column - 1) * 2) & mask); |
41
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
728 context->col_2 = (context->vdpmem[offset] << 8) | context->vdpmem[offset+1]; |
417
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
415
diff
changeset
|
729 context->v_offset = (line) & v_offset_mask; |
41
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
730 context->flags |= FLAG_WINDOW; |
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
731 return; |
40 | 732 } |
733 context->flags &= ~FLAG_WINDOW; | |
734 } | |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
735 uint16_t vscroll; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
736 switch(context->regs[REG_SCROLL] & 0x30) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
737 { |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
738 case 0: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
739 vscroll = 0xFF; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
740 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
741 case 0x10: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
742 vscroll = 0x1FF; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
743 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
744 case 0x20: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
745 //TODO: Verify this behavior |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
746 vscroll = 0; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
747 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
748 case 0x30: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
749 vscroll = 0x3FF; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
750 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
751 } |
414
51ee0f117365
Fix vscroll calculation in double resultion interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
413
diff
changeset
|
752 if (context->double_res) { |
413
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
753 vscroll <<= 1; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
754 vscroll |= 1; |
414
51ee0f117365
Fix vscroll calculation in double resultion interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
413
diff
changeset
|
755 } |
718
eaba6789f316
Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents:
717
diff
changeset
|
756 //TODO: Further research on vscroll latch behavior and the "first column bug" |
eaba6789f316
Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents:
717
diff
changeset
|
757 if (!column) { |
eaba6789f316
Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents:
717
diff
changeset
|
758 if (context->regs[REG_MODE_3] & BIT_VSCROLL) { |
eaba6789f316
Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents:
717
diff
changeset
|
759 if (context->regs[REG_MODE_4] & BIT_H40) { |
eaba6789f316
Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents:
717
diff
changeset
|
760 //Based on observed behavior documented by Eke-Eke, I'm guessing the VDP |
eaba6789f316
Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents:
717
diff
changeset
|
761 //ends up fetching the last value on the VSRAM bus in the H40 case |
eaba6789f316
Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents:
717
diff
changeset
|
762 //getting the last latched value should be close enough for now |
eaba6789f316
Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents:
717
diff
changeset
|
763 if (!vsram_off) { |
eaba6789f316
Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents:
717
diff
changeset
|
764 context->vscroll_latch[0] = context->vscroll_latch[1]; |
eaba6789f316
Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents:
717
diff
changeset
|
765 } |
eaba6789f316
Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents:
717
diff
changeset
|
766 } else { |
eaba6789f316
Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents:
717
diff
changeset
|
767 //supposedly it's always forced to 0 in the H32 case |
eaba6789f316
Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents:
717
diff
changeset
|
768 context->vscroll_latch[0] = context->vscroll_latch[1] = 0; |
eaba6789f316
Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents:
717
diff
changeset
|
769 } |
eaba6789f316
Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents:
717
diff
changeset
|
770 } else { |
eaba6789f316
Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents:
717
diff
changeset
|
771 context->vscroll_latch[vsram_off] = context->vsram[vsram_off]; |
eaba6789f316
Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents:
717
diff
changeset
|
772 } |
eaba6789f316
Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents:
717
diff
changeset
|
773 } else if (context->regs[REG_MODE_3] & BIT_VSCROLL) { |
710
4cd8823f79e3
First pass at emulating a vscroll latch. Titan's Overdrive demo seems to depend on the scroll value being latched early in the line before the HINT gets a chance to change it
Michael Pavone <pavone@retrodev.com>
parents:
708
diff
changeset
|
774 context->vscroll_latch[vsram_off] = context->vsram[column - 2 + vsram_off]; |
4cd8823f79e3
First pass at emulating a vscroll latch. Titan's Overdrive demo seems to depend on the scroll value being latched early in the line before the HINT gets a chance to change it
Michael Pavone <pavone@retrodev.com>
parents:
708
diff
changeset
|
775 } |
4cd8823f79e3
First pass at emulating a vscroll latch. Titan's Overdrive demo seems to depend on the scroll value being latched early in the line before the HINT gets a chance to change it
Michael Pavone <pavone@retrodev.com>
parents:
708
diff
changeset
|
776 vscroll &= context->vscroll_latch[vsram_off] + line; |
414
51ee0f117365
Fix vscroll calculation in double resultion interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
413
diff
changeset
|
777 context->v_offset = vscroll & v_offset_mask; |
26
a7c2b92d8056
Fix management of context->sprite_draws so the sprite layer only draws when it should
Mike Pavone <pavone@retrodev.com>
parents:
25
diff
changeset
|
778 //printf("%s | line %d, vsram: %d, vscroll: %d, v_offset: %d\n",(vsram_off ? "B" : "A"), line, context->vsram[context->regs[REG_MODE_3] & 0x4 ? column : 0], vscroll, context->v_offset); |
414
51ee0f117365
Fix vscroll calculation in double resultion interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
413
diff
changeset
|
779 vscroll >>= vscroll_shift; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
780 uint16_t hscroll_mask; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
781 uint16_t v_mul; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
782 switch(context->regs[REG_SCROLL] & 0x3) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
783 { |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
784 case 0: |
108
1a551a85cb06
Fix horizontal mask values for scroll plane map address calculation
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
785 hscroll_mask = 0x1F; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
786 v_mul = 64; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
787 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
788 case 0x1: |
39
3c69319269ef
Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should
Mike Pavone <pavone@retrodev.com>
parents:
38
diff
changeset
|
789 hscroll_mask = 0x3F; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
790 v_mul = 128; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
791 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
792 case 0x2: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
793 //TODO: Verify this behavior |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
794 hscroll_mask = 0; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
795 v_mul = 0; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
796 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
797 case 0x3: |
108
1a551a85cb06
Fix horizontal mask values for scroll plane map address calculation
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
798 hscroll_mask = 0x7F; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
799 v_mul = 256; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
800 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
801 } |
28 | 802 uint16_t hscroll, offset; |
803 for (int i = 0; i < 2; i++) { | |
39
3c69319269ef
Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should
Mike Pavone <pavone@retrodev.com>
parents:
38
diff
changeset
|
804 hscroll = (column - 2 + i - ((hscroll_val/8) & 0xFFFE)) & hscroll_mask; |
3c69319269ef
Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should
Mike Pavone <pavone@retrodev.com>
parents:
38
diff
changeset
|
805 offset = address + ((vscroll * v_mul + hscroll*2) & 0x1FFF); |
3c69319269ef
Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should
Mike Pavone <pavone@retrodev.com>
parents:
38
diff
changeset
|
806 //printf("%s | line: %d, col: %d, x: %d, hs_mask %X, scr reg: %X, tbl addr: %X\n", (vsram_off ? "B" : "A"), line, (column-2+i), hscroll, hscroll_mask, context->regs[REG_SCROLL], offset); |
28 | 807 uint16_t col_val = (context->vdpmem[offset] << 8) | context->vdpmem[offset+1]; |
808 if (i) { | |
809 context->col_2 = col_val; | |
810 } else { | |
811 context->col_1 = col_val; | |
812 } | |
813 } | |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
814 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
815 |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
816 void read_map_scroll_a(uint16_t column, uint32_t line, vdp_context * context) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
817 { |
25
4d0c20ad815a
Fix vertical scroll value for plane B
Mike Pavone <pavone@retrodev.com>
parents:
24
diff
changeset
|
818 read_map_scroll(column, 0, line, (context->regs[REG_SCROLL_A] & 0x38) << 10, context->hscroll_a, context); |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
819 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
820 |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
821 void read_map_scroll_b(uint16_t column, uint32_t line, vdp_context * context) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
822 { |
25
4d0c20ad815a
Fix vertical scroll value for plane B
Mike Pavone <pavone@retrodev.com>
parents:
24
diff
changeset
|
823 read_map_scroll(column, 1, line, (context->regs[REG_SCROLL_B] & 0x7) << 13, context->hscroll_b, context); |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
824 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
825 |
436
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
826 void render_map(uint16_t col, uint8_t * tmp_buf, uint8_t offset, vdp_context * context) |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
827 { |
413
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
828 uint16_t address; |
1032
679137a0e78e
Fix bug in vflip implementation when in double resolution interlace mode
Michael Pavone <pavone@retrodev.com>
parents:
1029
diff
changeset
|
829 uint16_t vflip_base; |
413
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
830 if (context->double_res) { |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
831 address = ((col & 0x3FF) << 6); |
1032
679137a0e78e
Fix bug in vflip implementation when in double resolution interlace mode
Michael Pavone <pavone@retrodev.com>
parents:
1029
diff
changeset
|
832 vflip_base = 60; |
413
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
833 } else { |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
834 address = ((col & 0x7FF) << 5); |
1032
679137a0e78e
Fix bug in vflip implementation when in double resolution interlace mode
Michael Pavone <pavone@retrodev.com>
parents:
1029
diff
changeset
|
835 vflip_base = 28; |
413
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
836 } |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
837 if (col & MAP_BIT_V_FLIP) { |
1032
679137a0e78e
Fix bug in vflip implementation when in double resolution interlace mode
Michael Pavone <pavone@retrodev.com>
parents:
1029
diff
changeset
|
838 address += vflip_base - 4 * context->v_offset; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
839 } else { |
1032
679137a0e78e
Fix bug in vflip implementation when in double resolution interlace mode
Michael Pavone <pavone@retrodev.com>
parents:
1029
diff
changeset
|
840 address += 4 * context->v_offset; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
841 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
842 uint16_t pal_priority = (col >> 9) & 0x70; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
843 int32_t dir; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
844 if (col & MAP_BIT_H_FLIP) { |
436
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
845 offset += 7; |
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
846 offset &= SCROLL_BUFFER_MASK; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
847 dir = -1; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
848 } else { |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
849 dir = 1; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
850 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
851 for (uint32_t i=0; i < 4; i++, address++) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
852 { |
436
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
853 tmp_buf[offset] = pal_priority | (context->vdpmem[address] >> 4); |
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
854 offset += dir; |
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
855 offset &= SCROLL_BUFFER_MASK; |
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
856 tmp_buf[offset] = pal_priority | (context->vdpmem[address] & 0xF); |
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
857 offset += dir; |
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
858 offset &= SCROLL_BUFFER_MASK; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
859 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
860 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
861 |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
862 void render_map_1(vdp_context * context) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
863 { |
436
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
864 render_map(context->col_1, context->tmp_buf_a, context->buf_a_off, context); |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
865 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
866 |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
867 void render_map_2(vdp_context * context) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
868 { |
436
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
869 render_map(context->col_2, context->tmp_buf_a, context->buf_a_off+8, context); |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
870 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
871 |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
872 void render_map_3(vdp_context * context) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
873 { |
436
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
874 render_map(context->col_1, context->tmp_buf_b, context->buf_b_off, context); |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
875 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
876 |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
877 void render_map_output(uint32_t line, int32_t col, vdp_context * context) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
878 { |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
879 if (line >= 240) { |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
880 return; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
881 } |
436
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
882 render_map(context->col_2, context->tmp_buf_b, context->buf_b_off+8, context); |
719
019d27995e32
Upgrade to SDL 2.0 and drop support for the non-OpenGL render path
Michael Pavone <pavone@retrodev.com>
parents:
718
diff
changeset
|
883 uint32_t *dst; |
436
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
884 uint8_t *sprite_buf, *plane_a, *plane_b; |
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
885 int plane_a_off, plane_b_off; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
886 if (col) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
887 { |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
888 col-=2; |
719
019d27995e32
Upgrade to SDL 2.0 and drop support for the non-OpenGL render path
Michael Pavone <pavone@retrodev.com>
parents:
718
diff
changeset
|
889 dst = context->framebuf; |
019d27995e32
Upgrade to SDL 2.0 and drop support for the non-OpenGL render path
Michael Pavone <pavone@retrodev.com>
parents:
718
diff
changeset
|
890 dst += line * 320 + col * 8; |
722
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
891 if (context->debug < 2) { |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
892 sprite_buf = context->linebuf + col * 8; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
893 uint8_t a_src, src; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
894 if (context->flags & FLAG_WINDOW) { |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
895 plane_a_off = context->buf_a_off; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
896 a_src = DBG_SRC_W; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
897 } else { |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
898 plane_a_off = context->buf_a_off - (context->hscroll_a & 0xF); |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
899 a_src = DBG_SRC_A; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
900 } |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
901 plane_b_off = context->buf_b_off - (context->hscroll_b & 0xF); |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
902 //printf("A | tmp_buf offset: %d\n", 8 - (context->hscroll_a & 0x7)); |
450
3758bcdae5de
Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty
Mike Pavone <pavone@retrodev.com>
parents:
438
diff
changeset
|
903 |
722
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
904 if (context->regs[REG_MODE_4] & BIT_HILIGHT) { |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
905 for (int i = 0; i < 16; ++plane_a_off, ++plane_b_off, ++sprite_buf, ++i) { |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
906 plane_a = context->tmp_buf_a + (plane_a_off & SCROLL_BUFFER_MASK); |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
907 plane_b = context->tmp_buf_b + (plane_b_off & SCROLL_BUFFER_MASK); |
748
45b62d237b7b
Fixed shadow/highlight mode
Michael Pavone <pavone@retrodev.com>
parents:
724
diff
changeset
|
908 uint8_t pixel = context->regs[REG_BG_COLOR]; |
45b62d237b7b
Fixed shadow/highlight mode
Michael Pavone <pavone@retrodev.com>
parents:
724
diff
changeset
|
909 uint32_t *colors = context->colors; |
722
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
910 src = DBG_SRC_BG; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
911 if (*plane_b & 0xF) { |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
912 pixel = *plane_b; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
913 src = DBG_SRC_B; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
914 } |
748
45b62d237b7b
Fixed shadow/highlight mode
Michael Pavone <pavone@retrodev.com>
parents:
724
diff
changeset
|
915 uint8_t intensity = *plane_b & BUF_BIT_PRIORITY; |
722
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
916 if (*plane_a & 0xF && (*plane_a & BUF_BIT_PRIORITY) >= (pixel & BUF_BIT_PRIORITY)) { |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
917 pixel = *plane_a; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
918 src = DBG_SRC_A; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
919 } |
748
45b62d237b7b
Fixed shadow/highlight mode
Michael Pavone <pavone@retrodev.com>
parents:
724
diff
changeset
|
920 intensity |= *plane_a & BUF_BIT_PRIORITY; |
45b62d237b7b
Fixed shadow/highlight mode
Michael Pavone <pavone@retrodev.com>
parents:
724
diff
changeset
|
921 if (*sprite_buf & 0xF && (*sprite_buf & BUF_BIT_PRIORITY) >= (pixel & BUF_BIT_PRIORITY)) { |
45b62d237b7b
Fixed shadow/highlight mode
Michael Pavone <pavone@retrodev.com>
parents:
724
diff
changeset
|
922 if ((*sprite_buf & 0x3F) == 0x3E) { |
45b62d237b7b
Fixed shadow/highlight mode
Michael Pavone <pavone@retrodev.com>
parents:
724
diff
changeset
|
923 intensity += BUF_BIT_PRIORITY; |
45b62d237b7b
Fixed shadow/highlight mode
Michael Pavone <pavone@retrodev.com>
parents:
724
diff
changeset
|
924 } else if ((*sprite_buf & 0x3F) == 0x3F) { |
45b62d237b7b
Fixed shadow/highlight mode
Michael Pavone <pavone@retrodev.com>
parents:
724
diff
changeset
|
925 intensity = 0; |
45b62d237b7b
Fixed shadow/highlight mode
Michael Pavone <pavone@retrodev.com>
parents:
724
diff
changeset
|
926 } else { |
722
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
927 pixel = *sprite_buf; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
928 src = DBG_SRC_S; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
929 if ((pixel & 0xF) == 0xE) { |
748
45b62d237b7b
Fixed shadow/highlight mode
Michael Pavone <pavone@retrodev.com>
parents:
724
diff
changeset
|
930 intensity = BUF_BIT_PRIORITY; |
45b62d237b7b
Fixed shadow/highlight mode
Michael Pavone <pavone@retrodev.com>
parents:
724
diff
changeset
|
931 } else { |
45b62d237b7b
Fixed shadow/highlight mode
Michael Pavone <pavone@retrodev.com>
parents:
724
diff
changeset
|
932 intensity |= pixel & BUF_BIT_PRIORITY; |
722
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
933 } |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
934 } |
748
45b62d237b7b
Fixed shadow/highlight mode
Michael Pavone <pavone@retrodev.com>
parents:
724
diff
changeset
|
935 } |
45b62d237b7b
Fixed shadow/highlight mode
Michael Pavone <pavone@retrodev.com>
parents:
724
diff
changeset
|
936 if (!intensity) { |
505
b7b7a1cab44a
The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents:
503
diff
changeset
|
937 src |= DBG_SHADOW; |
748
45b62d237b7b
Fixed shadow/highlight mode
Michael Pavone <pavone@retrodev.com>
parents:
724
diff
changeset
|
938 colors += CRAM_SIZE; |
45b62d237b7b
Fixed shadow/highlight mode
Michael Pavone <pavone@retrodev.com>
parents:
724
diff
changeset
|
939 } else if (intensity == BUF_BIT_PRIORITY*2) { |
45b62d237b7b
Fixed shadow/highlight mode
Michael Pavone <pavone@retrodev.com>
parents:
724
diff
changeset
|
940 src |= DBG_HILIGHT; |
45b62d237b7b
Fixed shadow/highlight mode
Michael Pavone <pavone@retrodev.com>
parents:
724
diff
changeset
|
941 colors += CRAM_SIZE*2; |
722
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
942 } |
884
252dfd29831d
Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents:
822
diff
changeset
|
943 |
722
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
944 uint32_t outpixel; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
945 if (context->debug) { |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
946 outpixel = context->debugcolors[src]; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
947 } else { |
748
45b62d237b7b
Fixed shadow/highlight mode
Michael Pavone <pavone@retrodev.com>
parents:
724
diff
changeset
|
948 outpixel = colors[pixel & 0x3F]; |
722
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
949 } |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
950 *(dst++) = outpixel; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
951 } |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
952 } else { |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
953 for (int i = 0; i < 16; ++plane_a_off, ++plane_b_off, ++sprite_buf, ++i) { |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
954 plane_a = context->tmp_buf_a + (plane_a_off & SCROLL_BUFFER_MASK); |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
955 plane_b = context->tmp_buf_b + (plane_b_off & SCROLL_BUFFER_MASK); |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
956 uint8_t pixel = context->regs[REG_BG_COLOR]; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
957 src = DBG_SRC_BG; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
958 if (*plane_b & 0xF) { |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
959 pixel = *plane_b; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
960 src = DBG_SRC_B; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
961 } |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
962 if (*plane_a & 0xF && (*plane_a & BUF_BIT_PRIORITY) >= (pixel & BUF_BIT_PRIORITY)) { |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
963 pixel = *plane_a; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
964 src = DBG_SRC_A; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
965 } |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
966 if (*sprite_buf & 0xF && (*sprite_buf & BUF_BIT_PRIORITY) >= (pixel & BUF_BIT_PRIORITY)) { |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
967 pixel = *sprite_buf; |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
968 src = DBG_SRC_S; |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
969 } |
722
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
970 uint32_t outpixel; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
971 if (context->debug) { |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
972 outpixel = context->debugcolors[src]; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
973 } else { |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
974 outpixel = context->colors[pixel & 0x3F]; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
975 } |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
976 *(dst++) = outpixel; |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
977 } |
722
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
978 } |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
979 } else if (context->debug == 2) { |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
980 if (col < 32) { |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
981 *(dst++) = context->colors[col * 2]; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
982 *(dst++) = context->colors[col * 2]; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
983 *(dst++) = context->colors[col * 2]; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
984 *(dst++) = context->colors[col * 2]; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
985 *(dst++) = context->colors[col * 2 + 1]; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
986 *(dst++) = context->colors[col * 2 + 1]; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
987 *(dst++) = context->colors[col * 2 + 1]; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
988 *(dst++) = context->colors[col * 2 + 1]; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
989 *(dst++) = context->colors[col * 2 + 2]; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
990 *(dst++) = context->colors[col * 2 + 2]; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
991 *(dst++) = context->colors[col * 2 + 2]; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
992 *(dst++) = context->colors[col * 2 + 2]; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
993 *(dst++) = context->colors[col * 2 + 3]; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
994 *(dst++) = context->colors[col * 2 + 3]; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
995 *(dst++) = context->colors[col * 2 + 3]; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
996 *(dst++) = context->colors[col * 2 + 3]; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
997 } else if (col == 32 || line >= 192) { |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
998 for (int32_t i = 0; i < 16; i ++) { |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
999 *(dst++) = 0; |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
1000 } |
722
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1001 } else { |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1002 for (int32_t i = 0; i < 16; i ++) { |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1003 *(dst++) = context->colors[line / 3 + (col - 34) * 0x20]; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1004 } |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1005 } |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
1006 } else { |
771
0565b2c1a034
Add ability to change start address for VRAM viewer. Fix handling of DMA enable flag when it comes to DMA fills. This fixes a bug in James Pond 3
Michael Pavone <pavone@retrodev.com>
parents:
757
diff
changeset
|
1007 uint32_t base = (context->debug - 3) * 0x200; |
0565b2c1a034
Add ability to change start address for VRAM viewer. Fix handling of DMA enable flag when it comes to DMA fills. This fixes a bug in James Pond 3
Michael Pavone <pavone@retrodev.com>
parents:
757
diff
changeset
|
1008 uint32_t cell = base + (line / 8) * (context->regs[REG_MODE_4] & BIT_H40 ? 40 : 32) + col; |
0565b2c1a034
Add ability to change start address for VRAM viewer. Fix handling of DMA enable flag when it comes to DMA fills. This fixes a bug in James Pond 3
Michael Pavone <pavone@retrodev.com>
parents:
757
diff
changeset
|
1009 uint32_t address = (cell * 32 + (line % 8) * 4) & 0xFFFF; |
722
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1010 for (int32_t i = 0; i < 4; i ++) { |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1011 *(dst++) = context->colors[(context->debug_pal << 4) | (context->vdpmem[address] >> 4)]; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1012 *(dst++) = context->colors[(context->debug_pal << 4) | (context->vdpmem[address] & 0xF)]; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1013 address++; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1014 } |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1015 cell++; |
771
0565b2c1a034
Add ability to change start address for VRAM viewer. Fix handling of DMA enable flag when it comes to DMA fills. This fixes a bug in James Pond 3
Michael Pavone <pavone@retrodev.com>
parents:
757
diff
changeset
|
1016 address = (cell * 32 + (line % 8) * 4) & 0xFFFF; |
722
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1017 for (int32_t i = 0; i < 4; i ++) { |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1018 *(dst++) = context->colors[(context->debug_pal << 4) | (context->vdpmem[address] >> 4)]; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1019 *(dst++) = context->colors[(context->debug_pal << 4) | (context->vdpmem[address] & 0xF)]; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1020 address++; |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
1021 } |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1022 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1023 } |
436
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
1024 context->buf_a_off = (context->buf_a_off + SCROLL_BUFFER_DRAW) & SCROLL_BUFFER_MASK; |
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
1025 context->buf_b_off = (context->buf_b_off + SCROLL_BUFFER_DRAW) & SCROLL_BUFFER_MASK; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1026 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1027 |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1028 uint32_t const h40_hsync_cycles[] = {19, 20, 20, 20, 18, 20, 20, 20, 18, 20, 20, 20, 18, 20, 20, 20, 19}; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1029 |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1030 void vdp_advance_line(vdp_context *context) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1031 { |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1032 context->vcounter++; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1033 context->vcounter &= 0x1FF; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1034 if (context->flags2 & FLAG2_REGION_PAL) { |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1035 if (context->latched_mode & BIT_PAL) { |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1036 if (context->vcounter == 0x10B) { |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1037 context->vcounter = 0x1D2; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1038 } |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1039 } else if (context->vcounter == 0x103){ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1040 context->vcounter = 0x1CA; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1041 } |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1042 } else if (!(context->latched_mode & BIT_PAL) && context->vcounter == 0xEB) { |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1043 context->vcounter = 0x1E5; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1044 } |
884
252dfd29831d
Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents:
822
diff
changeset
|
1045 |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1046 if (context->vcounter > (context->latched_mode & BIT_PAL ? PAL_INACTIVE_START : NTSC_INACTIVE_START)) { |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1047 context->hint_counter = context->regs[REG_HINT]; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1048 } else if (context->hint_counter) { |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1049 context->hint_counter--; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1050 } else { |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1051 context->flags2 |= FLAG2_HINT_PENDING; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1052 context->pending_hint_start = context->cycles; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1053 context->hint_counter = context->regs[REG_HINT]; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1054 } |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1055 } |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1056 |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1057 #define CHECK_ONLY if (context->cycles >= target_cycles) { return; } |
924
1b86268a4cb3
Change the sentinel value for the hslot parameter of run_dma_src to something that is not a valid slot number and actually use it for calls during the active display period
Michael Pavone <pavone@retrodev.com>
parents:
923
diff
changeset
|
1058 #define CHECK_LIMIT if (context->flags & FLAG_DMA_RUN) { run_dma_src(context, -1); } context->hslot++; context->cycles += slot_cycles; CHECK_ONLY |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1059 |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1060 #define COLUMN_RENDER_BLOCK(column, startcyc) \ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1061 case startcyc:\ |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1062 read_map_scroll_a(column, context->vcounter, context);\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1063 CHECK_LIMIT\ |
922
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1064 case ((startcyc+1)&0xFF):\ |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1065 external_slot(context);\ |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1066 CHECK_LIMIT\ |
922
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1067 case ((startcyc+2)&0xFF):\ |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1068 render_map_1(context);\ |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1069 CHECK_LIMIT\ |
922
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1070 case ((startcyc+3)&0xFF):\ |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1071 render_map_2(context);\ |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1072 CHECK_LIMIT\ |
922
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1073 case ((startcyc+4)&0xFF):\ |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1074 read_map_scroll_b(column, context->vcounter, context);\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1075 CHECK_LIMIT\ |
922
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1076 case ((startcyc+5)&0xFF):\ |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1077 read_sprite_x(context->vcounter, context);\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1078 CHECK_LIMIT\ |
922
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1079 case ((startcyc+6)&0xFF):\ |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1080 render_map_3(context);\ |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1081 CHECK_LIMIT\ |
922
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1082 case ((startcyc+7)&0xFF):\ |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1083 render_map_output(context->vcounter, column, context);\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1084 CHECK_LIMIT |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1085 |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1086 #define COLUMN_RENDER_BLOCK_REFRESH(column, startcyc) \ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1087 case startcyc:\ |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1088 read_map_scroll_a(column, context->vcounter, context);\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1089 CHECK_LIMIT\ |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1090 case (startcyc+1):\ |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1091 /* refresh, no don't run dma src */\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1092 context->hslot++;\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1093 context->cycles += slot_cycles;\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1094 CHECK_ONLY\ |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1095 case (startcyc+2):\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1096 render_map_1(context);\ |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1097 CHECK_LIMIT\ |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1098 case (startcyc+3):\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1099 render_map_2(context);\ |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1100 CHECK_LIMIT\ |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1101 case (startcyc+4):\ |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1102 read_map_scroll_b(column, context->vcounter, context);\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1103 CHECK_LIMIT\ |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1104 case (startcyc+5):\ |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1105 read_sprite_x(context->vcounter, context);\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1106 CHECK_LIMIT\ |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1107 case (startcyc+6):\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1108 render_map_3(context);\ |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1109 CHECK_LIMIT\ |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1110 case (startcyc+7):\ |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1111 render_map_output(context->vcounter, column, context);\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1112 CHECK_LIMIT |
884
252dfd29831d
Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents:
822
diff
changeset
|
1113 |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1114 #define SPRITE_RENDER_H40(slot) \ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1115 case slot:\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1116 render_sprite_cells( context);\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1117 scan_sprite_table(context->vcounter, context);\ |
924
1b86268a4cb3
Change the sentinel value for the hslot parameter of run_dma_src to something that is not a valid slot number and actually use it for calls during the active display period
Michael Pavone <pavone@retrodev.com>
parents:
923
diff
changeset
|
1118 if (context->flags & FLAG_DMA_RUN) { run_dma_src(context, -1); } \ |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1119 if (slot == 182) {\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1120 context->hslot = 229;\ |
922
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1121 context->cycles += h40_hsync_cycles[0];\ |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1122 } else {\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1123 context->hslot++;\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1124 if (slot >= HSYNC_SLOT_H40 && slot < HSYNC_END_H40) {\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1125 context->cycles += h40_hsync_cycles[slot - HSYNC_SLOT_H40];\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1126 } else {\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1127 context->cycles += slot_cycles;\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1128 }\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1129 }\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1130 CHECK_ONLY |
884
252dfd29831d
Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents:
822
diff
changeset
|
1131 |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1132 #define SPRITE_RENDER_H32(slot) \ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1133 case slot:\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1134 render_sprite_cells( context);\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1135 scan_sprite_table(context->vcounter, context);\ |
924
1b86268a4cb3
Change the sentinel value for the hslot parameter of run_dma_src to something that is not a valid slot number and actually use it for calls during the active display period
Michael Pavone <pavone@retrodev.com>
parents:
923
diff
changeset
|
1136 if (context->flags & FLAG_DMA_RUN) { run_dma_src(context, -1); } \ |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1137 if (slot == 147) {\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1138 context->hslot = 233;\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1139 } else {\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1140 context->hslot++;\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1141 }\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1142 context->cycles += slot_cycles;\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1143 CHECK_ONLY |
884
252dfd29831d
Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents:
822
diff
changeset
|
1144 |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1145 |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1146 void vdp_h40(vdp_context * context, uint32_t target_cycles) |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1147 { |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1148 uint16_t address; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1149 uint32_t mask; |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1150 uint32_t const slot_cycles = MCLKS_SLOT_H40; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1151 switch(context->hslot) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1152 { |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1153 for (;;) |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1154 { |
922
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1155 //sprite attribute table scan starts |
647
5d58dcd94733
Fix the HV counter and adjust the slots of certain VDP events
Michael Pavone <pavone@retrodev.com>
parents:
629
diff
changeset
|
1156 case 165: |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1157 context->sprite_index = 0x80; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1158 context->slot_counter = MAX_SPRITES_LINE; |
21
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
1159 render_sprite_cells( context); |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1160 scan_sprite_table(context->vcounter, context); |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1161 CHECK_LIMIT |
922
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1162 SPRITE_RENDER_H40(166) |
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1163 SPRITE_RENDER_H40(167) |
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1164 case 168: |
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1165 external_slot(context); |
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1166 CHECK_LIMIT |
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1167 SPRITE_RENDER_H40(169) |
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1168 SPRITE_RENDER_H40(170) |
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1169 SPRITE_RENDER_H40(171) |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1170 SPRITE_RENDER_H40(172) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1171 SPRITE_RENDER_H40(173) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1172 SPRITE_RENDER_H40(174) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1173 SPRITE_RENDER_H40(175) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1174 SPRITE_RENDER_H40(176) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1175 SPRITE_RENDER_H40(177) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1176 SPRITE_RENDER_H40(178) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1177 SPRITE_RENDER_H40(179) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1178 SPRITE_RENDER_H40(180) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1179 SPRITE_RENDER_H40(181) |
922
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1180 //!HSYNC asserted |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1181 SPRITE_RENDER_H40(182) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1182 SPRITE_RENDER_H40(229) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1183 SPRITE_RENDER_H40(230) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1184 SPRITE_RENDER_H40(231) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1185 SPRITE_RENDER_H40(232) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1186 SPRITE_RENDER_H40(233) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1187 SPRITE_RENDER_H40(234) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1188 SPRITE_RENDER_H40(235) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1189 SPRITE_RENDER_H40(236) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1190 SPRITE_RENDER_H40(237) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1191 SPRITE_RENDER_H40(238) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1192 SPRITE_RENDER_H40(239) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1193 SPRITE_RENDER_H40(240) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1194 SPRITE_RENDER_H40(241) |
922
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1195 case 242: |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1196 address = (context->regs[REG_HSCROLL] & 0x3F) << 10; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1197 mask = 0; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1198 if (context->regs[REG_MODE_3] & 0x2) { |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1199 mask |= 0xF8; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1200 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1201 if (context->regs[REG_MODE_3] & 0x1) { |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1202 mask |= 0x7; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1203 } |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1204 address += (context->vcounter & mask) * 4; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1205 context->hscroll_a = context->vdpmem[address] << 8 | context->vdpmem[address+1]; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1206 context->hscroll_b = context->vdpmem[address+2] << 8 | context->vdpmem[address+3]; |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1207 //printf("%d: HScroll A: %d, HScroll B: %d\n", context->vcounter, context->hscroll_a, context->hscroll_b); |
924
1b86268a4cb3
Change the sentinel value for the hslot parameter of run_dma_src to something that is not a valid slot number and actually use it for calls during the active display period
Michael Pavone <pavone@retrodev.com>
parents:
923
diff
changeset
|
1208 if (context->flags & FLAG_DMA_RUN) { run_dma_src(context, -1); } |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1209 context->hslot++; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1210 context->cycles += h40_hsync_cycles[14]; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1211 CHECK_ONLY |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1212 //!HSYNC high |
922
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1213 SPRITE_RENDER_H40(243) |
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1214 SPRITE_RENDER_H40(244) |
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1215 SPRITE_RENDER_H40(245) |
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1216 SPRITE_RENDER_H40(246) |
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1217 case 247: |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1218 read_map_scroll_a(0, context->vcounter, context); |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1219 CHECK_LIMIT |
922
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1220 SPRITE_RENDER_H40(248) |
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1221 case 249: |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1222 render_map_1(context); |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1223 scan_sprite_table(context->vcounter, context);//Just a guess |
922
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1224 CHECK_LIMIT |
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1225 case 250: |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1226 render_map_2(context); |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1227 scan_sprite_table(context->vcounter, context);//Just a guess |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1228 CHECK_LIMIT |
922
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1229 case 251: |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1230 read_map_scroll_b(0, context->vcounter, context); |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1231 CHECK_LIMIT |
922
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1232 SPRITE_RENDER_H40(252) |
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1233 case 253: |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1234 render_map_3(context); |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1235 scan_sprite_table(context->vcounter, context);//Just a guess |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1236 CHECK_LIMIT |
922
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1237 case 254: |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1238 if (context->vcounter == (context->latched_mode & BIT_PAL ? PAL_INACTIVE_START : NTSC_INACTIVE_START)) { |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1239 context->flags2 |= FLAG2_VINT_PENDING; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1240 context->pending_vint_start = context->cycles; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1241 } |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1242 render_map_output(context->vcounter, 0, context); |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1243 scan_sprite_table(context->vcounter, context);//Just a guess |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1244 //reverse context slot counter so it counts the number of sprite slots |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1245 //filled rather than the number of available slots |
21
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
1246 //context->slot_counter = MAX_SPRITES_LINE - context->slot_counter; |
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
1247 context->cur_slot = MAX_SPRITES_LINE-1; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1248 context->sprite_draws = MAX_DRAWS; |
36
04672c060062
Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents:
35
diff
changeset
|
1249 context->flags &= (~FLAG_CAN_MASK & ~FLAG_MASKED); |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1250 CHECK_LIMIT |
922
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1251 COLUMN_RENDER_BLOCK(2, 255) |
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1252 COLUMN_RENDER_BLOCK(4, 7) |
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1253 COLUMN_RENDER_BLOCK(6, 15) |
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1254 COLUMN_RENDER_BLOCK_REFRESH(8, 23) |
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1255 COLUMN_RENDER_BLOCK(10, 31) |
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1256 COLUMN_RENDER_BLOCK(12, 39) |
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1257 COLUMN_RENDER_BLOCK(14, 47) |
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1258 COLUMN_RENDER_BLOCK_REFRESH(16, 55) |
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1259 COLUMN_RENDER_BLOCK(18, 63) |
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1260 COLUMN_RENDER_BLOCK(20, 71) |
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1261 COLUMN_RENDER_BLOCK(22, 79) |
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1262 COLUMN_RENDER_BLOCK_REFRESH(24, 87) |
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1263 COLUMN_RENDER_BLOCK(26, 95) |
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1264 COLUMN_RENDER_BLOCK(28, 103) |
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1265 COLUMN_RENDER_BLOCK(30, 111) |
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1266 COLUMN_RENDER_BLOCK_REFRESH(32, 119) |
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1267 COLUMN_RENDER_BLOCK(34, 127) |
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1268 COLUMN_RENDER_BLOCK(36, 135) |
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1269 COLUMN_RENDER_BLOCK(38, 143) |
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1270 COLUMN_RENDER_BLOCK_REFRESH(40, 151) |
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1271 case 159: |
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1272 external_slot(context); |
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1273 CHECK_LIMIT |
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1274 case 160: |
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1275 external_slot(context); |
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1276 CHECK_LIMIT |
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1277 //sprite render to line buffer starts |
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1278 case 161: |
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1279 context->cur_slot = MAX_DRAWS-1; |
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1280 memset(context->linebuf, 0, LINEBUF_SIZE); |
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1281 render_sprite_cells(context); |
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1282 CHECK_LIMIT |
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1283 case 162: |
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1284 render_sprite_cells(context); |
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1285 CHECK_LIMIT |
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1286 case 163: |
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1287 render_sprite_cells(context); |
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1288 CHECK_LIMIT |
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1289 case 164: |
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1290 render_sprite_cells(context); |
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1291 vdp_advance_line(context); |
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1292 if (context->vcounter == (context->latched_mode & BIT_PAL ? PAL_INACTIVE_START : NTSC_INACTIVE_START)) { |
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1293 context->hslot++; |
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1294 context->cycles += slot_cycles; |
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1295 return; |
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1296 } |
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1297 CHECK_LIMIT |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1298 } |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1299 default: |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1300 context->hslot++; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1301 context->cycles += slot_cycles; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1302 return; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1303 } |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1304 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1305 |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1306 void vdp_h32(vdp_context * context, uint32_t target_cycles) |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1307 { |
37 | 1308 uint16_t address; |
1309 uint32_t mask; | |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1310 uint32_t const slot_cycles = MCLKS_SLOT_H32; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1311 switch(context->hslot) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1312 { |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1313 for (;;) |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1314 { |
923
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
1315 //sprite attribute table scan starts |
647
5d58dcd94733
Fix the HV counter and adjust the slots of certain VDP events
Michael Pavone <pavone@retrodev.com>
parents:
629
diff
changeset
|
1316 case 132: |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1317 context->sprite_index = 0x80; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1318 context->slot_counter = MAX_SPRITES_LINE_H32; |
37 | 1319 render_sprite_cells( context); |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1320 scan_sprite_table(context->vcounter, context); |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1321 CHECK_LIMIT |
923
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
1322 SPRITE_RENDER_H32(133) |
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
1323 SPRITE_RENDER_H32(134) |
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
1324 SPRITE_RENDER_H32(135) |
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
1325 SPRITE_RENDER_H32(136) |
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
1326 SPRITE_RENDER_H32(137) |
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
1327 SPRITE_RENDER_H32(138) |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1328 SPRITE_RENDER_H32(139) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1329 SPRITE_RENDER_H32(140) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1330 SPRITE_RENDER_H32(141) |
923
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
1331 case 142: |
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
1332 external_slot(context); |
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
1333 CHECK_LIMIT |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1334 SPRITE_RENDER_H32(143) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1335 SPRITE_RENDER_H32(144) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1336 SPRITE_RENDER_H32(145) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1337 SPRITE_RENDER_H32(146) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1338 SPRITE_RENDER_H32(147) |
923
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
1339 //HSYNC start |
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
1340 SPRITE_RENDER_H32(233) |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1341 SPRITE_RENDER_H32(234) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1342 SPRITE_RENDER_H32(235) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1343 SPRITE_RENDER_H32(236) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1344 SPRITE_RENDER_H32(237) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1345 SPRITE_RENDER_H32(238) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1346 SPRITE_RENDER_H32(239) |
923
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
1347 case 240: |
37 | 1348 external_slot(context); |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1349 CHECK_LIMIT |
923
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
1350 case 241: |
37 | 1351 address = (context->regs[REG_HSCROLL] & 0x3F) << 10; |
1352 mask = 0; | |
1353 if (context->regs[REG_MODE_3] & 0x2) { | |
1354 mask |= 0xF8; | |
1355 } | |
1356 if (context->regs[REG_MODE_3] & 0x1) { | |
1357 mask |= 0x7; | |
1358 } | |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1359 address += (context->vcounter & mask) * 4; |
37 | 1360 context->hscroll_a = context->vdpmem[address] << 8 | context->vdpmem[address+1]; |
1361 context->hscroll_b = context->vdpmem[address+2] << 8 | context->vdpmem[address+3]; | |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1362 //printf("%d: HScroll A: %d, HScroll B: %d\n", context->vcounter, context->hscroll_a, context->hscroll_b); |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1363 CHECK_LIMIT |
923
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
1364 SPRITE_RENDER_H32(242) |
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
1365 SPRITE_RENDER_H32(243) |
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
1366 SPRITE_RENDER_H32(244) |
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
1367 SPRITE_RENDER_H32(245) |
37 | 1368 //!HSYNC high |
923
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
1369 case 246: |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1370 read_map_scroll_a(0, context->vcounter, context); |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1371 CHECK_LIMIT |
923
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
1372 SPRITE_RENDER_H32(247) |
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
1373 case 248: |
37 | 1374 render_map_1(context); |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1375 scan_sprite_table(context->vcounter, context);//Just a guess |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1376 CHECK_LIMIT |
923
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
1377 case 249: |
37 | 1378 render_map_2(context); |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1379 scan_sprite_table(context->vcounter, context);//Just a guess |
923
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
1380 CHECK_LIMIT |
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
1381 case 250: |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1382 read_map_scroll_b(0, context->vcounter, context); |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1383 CHECK_LIMIT |
923
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
1384 case 251: |
37 | 1385 render_sprite_cells(context); |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1386 scan_sprite_table(context->vcounter, context); |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1387 CHECK_LIMIT |
923
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
1388 case 252: |
37 | 1389 render_map_3(context); |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1390 scan_sprite_table(context->vcounter, context);//Just a guess |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1391 CHECK_LIMIT |
923
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
1392 case 253: |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1393 render_map_output(context->vcounter, 0, context); |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1394 scan_sprite_table(context->vcounter, context);//Just a guess |
37 | 1395 //reverse context slot counter so it counts the number of sprite slots |
1396 //filled rather than the number of available slots | |
1397 //context->slot_counter = MAX_SPRITES_LINE - context->slot_counter; | |
1398 context->cur_slot = MAX_SPRITES_LINE_H32-1; | |
1399 context->sprite_draws = MAX_DRAWS_H32; | |
1400 context->flags &= (~FLAG_CAN_MASK & ~FLAG_MASKED); | |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1401 CHECK_LIMIT |
923
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
1402 COLUMN_RENDER_BLOCK(2, 254) |
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
1403 COLUMN_RENDER_BLOCK(4, 6) |
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
1404 COLUMN_RENDER_BLOCK(6, 14) |
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
1405 COLUMN_RENDER_BLOCK_REFRESH(8, 22) |
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
1406 COLUMN_RENDER_BLOCK(10, 30) |
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
1407 COLUMN_RENDER_BLOCK(12, 38) |
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
1408 COLUMN_RENDER_BLOCK(14, 46) |
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
1409 COLUMN_RENDER_BLOCK_REFRESH(16, 54) |
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
1410 COLUMN_RENDER_BLOCK(18, 62) |
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
1411 COLUMN_RENDER_BLOCK(20, 70) |
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
1412 COLUMN_RENDER_BLOCK(22, 78) |
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
1413 COLUMN_RENDER_BLOCK_REFRESH(24, 86) |
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
1414 COLUMN_RENDER_BLOCK(26, 94) |
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
1415 COLUMN_RENDER_BLOCK(28, 102) |
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
1416 COLUMN_RENDER_BLOCK(30, 110) |
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
1417 COLUMN_RENDER_BLOCK_REFRESH(32, 118) |
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
1418 case 126: |
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
1419 external_slot(context); |
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
1420 CHECK_LIMIT |
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
1421 case 127: |
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
1422 external_slot(context); |
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
1423 CHECK_LIMIT |
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
1424 //sprite render to line buffer starts |
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
1425 case 128: |
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
1426 context->cur_slot = MAX_DRAWS_H32-1; |
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
1427 memset(context->linebuf, 0, LINEBUF_SIZE); |
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
1428 render_sprite_cells(context); |
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
1429 CHECK_LIMIT |
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
1430 case 129: |
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
1431 render_sprite_cells(context); |
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
1432 CHECK_LIMIT |
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
1433 case 130: |
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
1434 render_sprite_cells(context); |
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
1435 CHECK_LIMIT |
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
1436 case 131: |
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
1437 render_sprite_cells(context); |
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
1438 vdp_advance_line(context); |
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
1439 if (context->vcounter == (context->latched_mode & BIT_PAL ? PAL_INACTIVE_START : NTSC_INACTIVE_START)) { |
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
1440 context->hslot++; |
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
1441 context->cycles += slot_cycles; |
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
1442 return; |
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
1443 } |
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
1444 CHECK_LIMIT |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1445 } |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1446 default: |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1447 context->hslot++; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1448 context->cycles += MCLKS_SLOT_H32; |
503
eee6be465c47
Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
499
diff
changeset
|
1449 } |
eee6be465c47
Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
499
diff
changeset
|
1450 } |
eee6be465c47
Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
499
diff
changeset
|
1451 |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1452 void latch_mode(vdp_context * context) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1453 { |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1454 context->latched_mode = context->regs[REG_MODE_2] & BIT_PAL; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1455 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1456 |
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1457 void check_render_bg(vdp_context * context, int32_t line, uint32_t slot) |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1458 { |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1459 int starti = -1; |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1460 if (context->regs[REG_MODE_4] & BIT_H40) { |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1461 if (slot >= 12 && slot < 172) { |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1462 uint32_t x = (slot-12)*2; |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1463 starti = line * 320 + x; |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1464 } |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1465 } else { |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1466 if (slot >= 11 && slot < 139) { |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1467 uint32_t x = (slot-11)*2; |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1468 starti = line * 320 + x; |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1469 } |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1470 } |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1471 if (starti >= 0) { |
719
019d27995e32
Upgrade to SDL 2.0 and drop support for the non-OpenGL render path
Michael Pavone <pavone@retrodev.com>
parents:
718
diff
changeset
|
1472 uint32_t color = context->colors[context->regs[REG_BG_COLOR]]; |
019d27995e32
Upgrade to SDL 2.0 and drop support for the non-OpenGL render path
Michael Pavone <pavone@retrodev.com>
parents:
718
diff
changeset
|
1473 uint32_t * start = context->framebuf; |
019d27995e32
Upgrade to SDL 2.0 and drop support for the non-OpenGL render path
Michael Pavone <pavone@retrodev.com>
parents:
718
diff
changeset
|
1474 start += starti; |
019d27995e32
Upgrade to SDL 2.0 and drop support for the non-OpenGL render path
Michael Pavone <pavone@retrodev.com>
parents:
718
diff
changeset
|
1475 for (int i = 0; i < 2; i++) { |
019d27995e32
Upgrade to SDL 2.0 and drop support for the non-OpenGL render path
Michael Pavone <pavone@retrodev.com>
parents:
718
diff
changeset
|
1476 *(start++) = color; |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1477 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1478 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1479 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1480 |
717
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1481 |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1482 void vdp_run_context(vdp_context * context, uint32_t target_cycles) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1483 { |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1484 while(context->cycles < target_cycles) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1485 { |
697
7f96bd1cb1be
Sync fixes and logging to fix more sync issues
Michael Pavone <pavone@retrodev.com>
parents:
680
diff
changeset
|
1486 uint32_t inactive_start = context->latched_mode & BIT_PAL ? PAL_INACTIVE_START : NTSC_INACTIVE_START; |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1487 //line 0x1FF is basically active even though it's not displayed |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1488 uint8_t active_slot = context->vcounter < inactive_start || context->vcounter == 0x1FF; |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1489 uint8_t is_h40 = context->regs[REG_MODE_4] & BIT_H40; |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1490 if (context->regs[REG_MODE_2] & DISPLAY_ENABLE && active_slot) { |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1491 if (is_h40) { |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1492 vdp_h40(context, target_cycles); |
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1493 } else { |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1494 vdp_h32(context, target_cycles); |
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1495 } |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1496 } else { |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1497 if (is_h40) { |
922
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1498 if (context->hslot == 161) { |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1499 context->cur_slot = MAX_DRAWS-1; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1500 memset(context->linebuf, 0, LINEBUF_SIZE); |
922
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1501 } else if (context->hslot == 165) { |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1502 context->sprite_index = 0x80; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1503 context->slot_counter = MAX_SPRITES_LINE; |
503
eee6be465c47
Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
499
diff
changeset
|
1504 } |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1505 } else { |
923
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
1506 if (context->hslot == 128) { |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1507 context->cur_slot = MAX_DRAWS_H32-1; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1508 memset(context->linebuf, 0, LINEBUF_SIZE); |
923
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
1509 } else if (context->hslot == 132) { |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1510 context->sprite_index = 0x80; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1511 context->slot_counter = MAX_SPRITES_LINE_H32; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1512 } |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1513 } |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1514 if(context->vcounter == inactive_start) { |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1515 uint32_t intslot = context->regs[REG_MODE_4] & BIT_H40 ? VINT_SLOT_H40 : VINT_SLOT_H32; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1516 if (context->hslot == intslot) { |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1517 context->flags2 |= FLAG2_VINT_PENDING; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1518 context->pending_vint_start = context->cycles; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1519 } |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1520 } |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1521 uint32_t inccycles; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1522 if (is_h40) { |
922
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1523 if (context->hslot == 182) { |
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1524 inccycles = h40_hsync_cycles[0]; |
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1525 } else if (context->hslot < HSYNC_SLOT_H40 || context->hslot >= HSYNC_END_H40) { |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1526 inccycles = MCLKS_SLOT_H40; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1527 } else { |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1528 inccycles = h40_hsync_cycles[context->hslot-HSYNC_SLOT_H40]; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1529 } |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1530 } else { |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1531 inccycles = MCLKS_SLOT_H32; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1532 } |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1533 if (!is_refresh(context, context->hslot)) { |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1534 external_slot(context); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1535 } |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1536 if (context->vcounter < inactive_start) { |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1537 check_render_bg(context, context->vcounter, context->hslot); |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1538 } |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1539 if (context->flags & FLAG_DMA_RUN && !is_refresh(context, context->hslot)) { |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1540 run_dma_src(context, context->hslot); |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1541 } |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1542 context->cycles += inccycles; |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1543 context->hslot++; |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1544 if (is_h40) { |
647
5d58dcd94733
Fix the HV counter and adjust the slots of certain VDP events
Michael Pavone <pavone@retrodev.com>
parents:
629
diff
changeset
|
1545 if (context->hslot == LINE_CHANGE_H40) { |
717
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1546 vdp_advance_line(context); |
699
d8a1fdec68fc
Fix frame counter increment and VINT cycle time calculation
Michael Pavone <pavone@retrodev.com>
parents:
697
diff
changeset
|
1547 if (context->vcounter == (inactive_start + 8)) { |
d8a1fdec68fc
Fix frame counter increment and VINT cycle time calculation
Michael Pavone <pavone@retrodev.com>
parents:
697
diff
changeset
|
1548 context->frame++; |
d8a1fdec68fc
Fix frame counter increment and VINT cycle time calculation
Michael Pavone <pavone@retrodev.com>
parents:
697
diff
changeset
|
1549 } |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1550 } else if (context->hslot == 183) { |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1551 context->hslot = 229; |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1552 } |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1553 } else { |
647
5d58dcd94733
Fix the HV counter and adjust the slots of certain VDP events
Michael Pavone <pavone@retrodev.com>
parents:
629
diff
changeset
|
1554 if (context->hslot == LINE_CHANGE_H32) { |
717
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1555 vdp_advance_line(context); |
699
d8a1fdec68fc
Fix frame counter increment and VINT cycle time calculation
Michael Pavone <pavone@retrodev.com>
parents:
697
diff
changeset
|
1556 if (context->vcounter == (inactive_start + 8)) { |
d8a1fdec68fc
Fix frame counter increment and VINT cycle time calculation
Michael Pavone <pavone@retrodev.com>
parents:
697
diff
changeset
|
1557 context->frame++; |
d8a1fdec68fc
Fix frame counter increment and VINT cycle time calculation
Michael Pavone <pavone@retrodev.com>
parents:
697
diff
changeset
|
1558 } |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1559 } else if (context->hslot == 148) { |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1560 context->hslot = 233; |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1561 } |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1562 } |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1563 } |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1564 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1565 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1566 |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1567 uint32_t vdp_run_to_vblank(vdp_context * context) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1568 { |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1569 uint32_t target_cycles = ((context->latched_mode & BIT_PAL) ? PAL_INACTIVE_START : NTSC_INACTIVE_START) * MCLKS_LINE; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1570 vdp_run_context(context, target_cycles); |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1571 return context->cycles; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1572 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1573 |
75 | 1574 void vdp_run_dma_done(vdp_context * context, uint32_t target_cycles) |
1575 { | |
1576 for(;;) { | |
1577 uint32_t dmalen = (context->regs[REG_DMALEN_H] << 8) | context->regs[REG_DMALEN_L]; | |
1578 if (!dmalen) { | |
1579 dmalen = 0x10000; | |
1580 } | |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1581 uint32_t min_dma_complete = dmalen * (context->regs[REG_MODE_4] & BIT_H40 ? 16 : 20); |
75 | 1582 if ((context->regs[REG_DMASRC_H] & 0xC0) == 0xC0 || (context->cd & 0xF) == VRAM_WRITE) { |
1583 //DMA copies take twice as long to complete since they require a read and a write | |
1584 //DMA Fills and transfers to VRAM also take twice as long as it requires 2 writes for a single word | |
1585 min_dma_complete *= 2; | |
1586 } | |
1587 min_dma_complete += context->cycles; | |
1588 if (target_cycles < min_dma_complete) { | |
1589 vdp_run_context(context, target_cycles); | |
1590 return; | |
1591 } else { | |
1592 vdp_run_context(context, min_dma_complete); | |
1593 if (!(context->flags & FLAG_DMA_RUN)) { | |
1594 return; | |
1595 } | |
1596 } | |
1597 } | |
1598 } | |
1599 | |
1600 int vdp_control_port_write(vdp_context * context, uint16_t value) | |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1601 { |
471
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1602 //printf("control port write: %X at %d\n", value, context->cycles); |
149
139e5dcd6aa3
Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents:
143
diff
changeset
|
1603 if (context->flags & FLAG_DMA_RUN) { |
139e5dcd6aa3
Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents:
143
diff
changeset
|
1604 return -1; |
139e5dcd6aa3
Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents:
143
diff
changeset
|
1605 } |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1606 if (context->flags & FLAG_PENDING) { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1607 context->address = (context->address & 0x3FFF) | (value << 14); |
983
14d2f3b0e45d
Fixes to the DMA busy flag and DMA fill. Now up to 120/122 on VDP FIFO Testing.
Michael Pavone <pavone@retrodev.com>
parents:
981
diff
changeset
|
1608 //It seems like the DMA enable bit doesn't so much enable DMA so much |
14d2f3b0e45d
Fixes to the DMA busy flag and DMA fill. Now up to 120/122 on VDP FIFO Testing.
Michael Pavone <pavone@retrodev.com>
parents:
981
diff
changeset
|
1609 //as it enables changing CD5 from control port writes |
14d2f3b0e45d
Fixes to the DMA busy flag and DMA fill. Now up to 120/122 on VDP FIFO Testing.
Michael Pavone <pavone@retrodev.com>
parents:
981
diff
changeset
|
1610 uint8_t preserve = (context->regs[REG_MODE_2] & BIT_DMA_ENABLE) ? 0x3 : 0x23; |
14d2f3b0e45d
Fixes to the DMA busy flag and DMA fill. Now up to 120/122 on VDP FIFO Testing.
Michael Pavone <pavone@retrodev.com>
parents:
981
diff
changeset
|
1611 context->cd = (context->cd & preserve) | ((value >> 2) & ~preserve & 0xFF); |
75 | 1612 context->flags &= ~FLAG_PENDING; |
980
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
1613 //Should these be taken care of here or after the first write? |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
1614 context->flags &= ~FLAG_READ_FETCHED; |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
1615 context->flags2 &= ~FLAG2_READ_PENDING; |
453
b491df8bdbc0
Adjust VBLANK flag and refresh timing to be in line with logic analyzer and visual observations of direct color DMA demos. Remove debug print statements.
Mike Pavone <pavone@retrodev.com>
parents:
452
diff
changeset
|
1616 //printf("New Address: %X, New CD: %X\n", context->address, context->cd); |
983
14d2f3b0e45d
Fixes to the DMA busy flag and DMA fill. Now up to 120/122 on VDP FIFO Testing.
Michael Pavone <pavone@retrodev.com>
parents:
981
diff
changeset
|
1617 if (context->cd & 0x20) { |
327
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
1618 // |
75 | 1619 if((context->regs[REG_DMASRC_H] & 0xC0) != 0x80) { |
1620 //DMA copy or 68K -> VDP, transfer starts immediately | |
1621 context->flags |= FLAG_DMA_RUN; | |
131
8fc8e46be691
Fix bug that was causing DMA fills to lock up under certain circumstances
Mike Pavone <pavone@retrodev.com>
parents:
109
diff
changeset
|
1622 context->dma_cd = context->cd; |
717
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1623 //printf("DMA start (length: %X) at cycle %d, frame: %d, vcounter: %d, hslot: %d\n", (context->regs[REG_DMALEN_H] << 8) | context->regs[REG_DMALEN_L], context->cycles, context->frame, context->vcounter, context->hslot); |
75 | 1624 if (!(context->regs[REG_DMASRC_H] & 0x80)) { |
327
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
1625 //printf("DMA Address: %X, New CD: %X, Source: %X, Length: %X\n", context->address, context->cd, (context->regs[REG_DMASRC_H] << 17) | (context->regs[REG_DMASRC_M] << 9) | (context->regs[REG_DMASRC_L] << 1), context->regs[REG_DMALEN_H] << 8 | context->regs[REG_DMALEN_L]); |
75 | 1626 return 1; |
327
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
1627 } else { |
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
1628 //printf("DMA Copy Address: %X, New CD: %X, Source: %X\n", context->address, context->cd, (context->regs[REG_DMASRC_M] << 8) | context->regs[REG_DMASRC_L]); |
75 | 1629 } |
327
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
1630 } else { |
453
b491df8bdbc0
Adjust VBLANK flag and refresh timing to be in line with logic analyzer and visual observations of direct color DMA demos. Remove debug print statements.
Mike Pavone <pavone@retrodev.com>
parents:
452
diff
changeset
|
1631 //printf("DMA Fill Address: %X, New CD: %X\n", context->address, context->cd); |
75 | 1632 } |
63
a6dd5b7a971b
Add FPS counter to console output
Mike Pavone <pavone@retrodev.com>
parents:
58
diff
changeset
|
1633 } |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1634 } else { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1635 if ((value & 0xC000) == 0x8000) { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1636 //Register write |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1637 uint8_t reg = (value >> 8) & 0x1F; |
475
50e0cb475294
Don't allow register writes to regs above when in Mode 4
Mike Pavone <pavone@retrodev.com>
parents:
474
diff
changeset
|
1638 if (reg < (context->regs[REG_MODE_2] & BIT_MODE_5 ? VDP_REGS : 0xA)) { |
453
b491df8bdbc0
Adjust VBLANK flag and refresh timing to be in line with logic analyzer and visual observations of direct color DMA demos. Remove debug print statements.
Mike Pavone <pavone@retrodev.com>
parents:
452
diff
changeset
|
1639 //printf("register %d set to %X\n", reg, value & 0xFF); |
480
0737953132ad
Implement HV counter latch
Mike Pavone <pavone@retrodev.com>
parents:
479
diff
changeset
|
1640 if (reg == REG_MODE_1 && (value & BIT_HVC_LATCH) && !(context->regs[reg] & BIT_HVC_LATCH)) { |
0737953132ad
Implement HV counter latch
Mike Pavone <pavone@retrodev.com>
parents:
479
diff
changeset
|
1641 context->hv_latch = vdp_hv_counter_read(context); |
0737953132ad
Implement HV counter latch
Mike Pavone <pavone@retrodev.com>
parents:
479
diff
changeset
|
1642 } |
505
b7b7a1cab44a
The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents:
503
diff
changeset
|
1643 if (reg == REG_BG_COLOR) { |
b7b7a1cab44a
The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents:
503
diff
changeset
|
1644 value &= 0x3F; |
b7b7a1cab44a
The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents:
503
diff
changeset
|
1645 } |
718
eaba6789f316
Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents:
717
diff
changeset
|
1646 /*if (reg == REG_MODE_4 && ((value ^ context->regs[reg]) & BIT_H40)) { |
717
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1647 printf("Mode changed from H%d to H%d @ %d, frame: %d\n", context->regs[reg] & BIT_H40 ? 40 : 32, value & BIT_H40 ? 40 : 32, context->cycles, context->frame); |
718
eaba6789f316
Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents:
717
diff
changeset
|
1648 }*/ |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1649 context->regs[reg] = value; |
413
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1650 if (reg == REG_MODE_4) { |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1651 context->double_res = (value & (BIT_INTERLACE | BIT_DOUBLE_RES)) == (BIT_INTERLACE | BIT_DOUBLE_RES); |
415
8c60c8c09a0f
Fix sprite y mask in interlace mode. Fix framebuffer selection when switching out of interlace mode.
Mike Pavone <pavone@retrodev.com>
parents:
414
diff
changeset
|
1652 if (!context->double_res) { |
8c60c8c09a0f
Fix sprite y mask in interlace mode. Fix framebuffer selection when switching out of interlace mode.
Mike Pavone <pavone@retrodev.com>
parents:
414
diff
changeset
|
1653 context->framebuf = context->oddbuf; |
8c60c8c09a0f
Fix sprite y mask in interlace mode. Fix framebuffer selection when switching out of interlace mode.
Mike Pavone <pavone@retrodev.com>
parents:
414
diff
changeset
|
1654 } |
983
14d2f3b0e45d
Fixes to the DMA busy flag and DMA fill. Now up to 120/122 on VDP FIFO Testing.
Michael Pavone <pavone@retrodev.com>
parents:
981
diff
changeset
|
1655 } |
476
5d7bc113653b
Clear the low 2 bits of CD when a register is written to
Mike Pavone <pavone@retrodev.com>
parents:
475
diff
changeset
|
1656 context->cd &= 0x3C; |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1657 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1658 } else { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1659 context->flags |= FLAG_PENDING; |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1660 context->address = (context->address &0xC000) | (value & 0x3FFF); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1661 context->cd = (context->cd &0x3C) | (value >> 14); |
980
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
1662 //Should these be taken care of here or after the second write? |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
1663 //context->flags &= ~FLAG_READ_FETCHED; |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
1664 //context->flags2 &= ~FLAG2_READ_PENDING; |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1665 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1666 } |
75 | 1667 return 0; |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1668 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1669 |
149
139e5dcd6aa3
Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents:
143
diff
changeset
|
1670 int vdp_data_port_write(vdp_context * context, uint16_t value) |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1671 { |
471
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1672 //printf("data port write: %X at %d\n", value, context->cycles); |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
1673 if (context->flags & FLAG_DMA_RUN && (context->regs[REG_DMASRC_H] & 0xC0) != 0x80) { |
149
139e5dcd6aa3
Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents:
143
diff
changeset
|
1674 return -1; |
139e5dcd6aa3
Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents:
143
diff
changeset
|
1675 } |
980
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
1676 if (context->flags & FLAG_PENDING) { |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
1677 context->flags &= ~FLAG_PENDING; |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
1678 //Should these be cleared here? |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
1679 context->flags &= ~FLAG_READ_FETCHED; |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
1680 context->flags2 &= ~FLAG2_READ_PENDING; |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
1681 } |
109
004dd46e0a97
COmment out fifo full debug printf
Mike Pavone <pavone@retrodev.com>
parents:
108
diff
changeset
|
1682 /*if (context->fifo_cur == context->fifo_end) { |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1683 printf("FIFO full, waiting for space before next write at cycle %X\n", context->cycles); |
109
004dd46e0a97
COmment out fifo full debug printf
Mike Pavone <pavone@retrodev.com>
parents:
108
diff
changeset
|
1684 }*/ |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
1685 if (context->cd & 0x20 && (context->regs[REG_DMASRC_H] & 0xC0) == 0x80) { |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
1686 context->flags &= ~FLAG_DMA_RUN; |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
1687 } |
471
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1688 while (context->fifo_write == context->fifo_read) { |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1689 vdp_run_context(context, context->cycles + ((context->regs[REG_MODE_4] & BIT_H40) ? 16 : 20)); |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1690 } |
471
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1691 fifo_entry * cur = context->fifo + context->fifo_write; |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1692 cur->cycle = context->cycles + ((context->regs[REG_MODE_4] & BIT_H40) ? 16 : 20)*FIFO_LATENCY; |
471
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1693 cur->address = context->address; |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1694 cur->value = value; |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1695 cur->cd = context->cd; |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1696 cur->partial = 0; |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1697 if (context->fifo_read < 0) { |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1698 context->fifo_read = context->fifo_write; |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1699 } |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1700 context->fifo_write = (context->fifo_write + 1) & (FIFO_SIZE-1); |
138 | 1701 context->address += context->regs[REG_AUTOINC]; |
149
139e5dcd6aa3
Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents:
143
diff
changeset
|
1702 return 0; |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1703 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1704 |
470
541c1ae8abf3
Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1705 void vdp_test_port_write(vdp_context * context, uint16_t value) |
541c1ae8abf3
Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1706 { |
541c1ae8abf3
Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1707 //TODO: implement test register |
541c1ae8abf3
Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1708 } |
541c1ae8abf3
Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1709 |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1710 uint16_t vdp_control_port_read(vdp_context * context) |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1711 { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1712 context->flags &= ~FLAG_PENDING; |
980
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
1713 //Bits 15-10 are not fixed like Charles MacDonald's doc suggests, but instead open bus values that reflect 68K prefetch |
981
902c53d9c16f
Half assed, prefetch based open bus value emulation. Gets BlastEm up to 119/122 in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents:
980
diff
changeset
|
1714 uint16_t value = get_open_bus_value() & 0xFC00; |
471
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1715 if (context->fifo_read < 0) { |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1716 value |= 0x200; |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1717 } |
471
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1718 if (context->fifo_read == context->fifo_write) { |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1719 value |= 0x100; |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1720 } |
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1721 if (context->flags2 & FLAG2_VINT_PENDING) { |
413
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1722 value |= 0x80; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1723 } |
494
8ac0eb05642c
Initial implementation of sprite overflow and sprite collision status register flags
Mike Pavone <pavone@retrodev.com>
parents:
481
diff
changeset
|
1724 if (context->flags & FLAG_DOT_OFLOW) { |
8ac0eb05642c
Initial implementation of sprite overflow and sprite collision status register flags
Mike Pavone <pavone@retrodev.com>
parents:
481
diff
changeset
|
1725 value |= 0x40; |
8ac0eb05642c
Initial implementation of sprite overflow and sprite collision status register flags
Mike Pavone <pavone@retrodev.com>
parents:
481
diff
changeset
|
1726 } |
8ac0eb05642c
Initial implementation of sprite overflow and sprite collision status register flags
Mike Pavone <pavone@retrodev.com>
parents:
481
diff
changeset
|
1727 if (context->flags2 & FLAG2_SPRITE_COLLIDE) { |
8ac0eb05642c
Initial implementation of sprite overflow and sprite collision status register flags
Mike Pavone <pavone@retrodev.com>
parents:
481
diff
changeset
|
1728 value |= 0x20; |
8ac0eb05642c
Initial implementation of sprite overflow and sprite collision status register flags
Mike Pavone <pavone@retrodev.com>
parents:
481
diff
changeset
|
1729 //TODO: Test when this is actually cleared |
8ac0eb05642c
Initial implementation of sprite overflow and sprite collision status register flags
Mike Pavone <pavone@retrodev.com>
parents:
481
diff
changeset
|
1730 context->flags2 &= ~FLAG2_SPRITE_COLLIDE; |
8ac0eb05642c
Initial implementation of sprite overflow and sprite collision status register flags
Mike Pavone <pavone@retrodev.com>
parents:
481
diff
changeset
|
1731 } |
413
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1732 if ((context->regs[REG_MODE_4] & BIT_INTERLACE) && context->framebuf == context->oddbuf) { |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1733 value |= 0x10; |
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1734 } |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1735 uint32_t line= context->vcounter; |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1736 uint32_t slot = context->hslot; |
717
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1737 uint32_t inactive_start = (context->latched_mode & BIT_PAL ? PAL_INACTIVE_START : NTSC_INACTIVE_START); |
921
2be771c4dfbd
After reviewing the results of my test ROM again it seems pretty clear that the VBlank flag gets set at the same time as the vcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
920
diff
changeset
|
1738 if ((line >= inactive_start && line < 0x1FF) || !(context->regs[REG_MODE_2] & BIT_DISP_EN)) { |
318
789f2f5f2277
Implement hblank flag in status register
Mike Pavone <pavone@retrodev.com>
parents:
317
diff
changeset
|
1739 value |= 0x8; |
789f2f5f2277
Implement hblank flag in status register
Mike Pavone <pavone@retrodev.com>
parents:
317
diff
changeset
|
1740 } |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1741 if (context->regs[REG_MODE_4] & BIT_H40) { |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1742 if (slot < HBLANK_END_H40 || slot > HBLANK_START_H40) { |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1743 value |= 0x4; |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1744 } |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1745 } else { |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1746 if (slot < HBLANK_END_H32 || slot > HBLANK_START_H32) { |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1747 value |= 0x4; |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1748 } |
318
789f2f5f2277
Implement hblank flag in status register
Mike Pavone <pavone@retrodev.com>
parents:
317
diff
changeset
|
1749 } |
983
14d2f3b0e45d
Fixes to the DMA busy flag and DMA fill. Now up to 120/122 on VDP FIFO Testing.
Michael Pavone <pavone@retrodev.com>
parents:
981
diff
changeset
|
1750 if (context->cd & 0x20) { |
141
576f55711d8d
Fix DMA in progress flag in VDP status register
Mike Pavone <pavone@retrodev.com>
parents:
138
diff
changeset
|
1751 value |= 0x2; |
75 | 1752 } |
714
e29bc2918f69
Fix VDP status register PAL bit based on observations of the Titan Overdrive demo
Michael Pavone <pavone@retrodev.com>
parents:
711
diff
changeset
|
1753 if (context->flags2 & FLAG2_REGION_PAL) { |
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1754 value |= 0x1; |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1755 } |
459
c49ecf575784
Revert change to VBLANK flag timing based on new direct color DMA test
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
1756 //printf("status read at cycle %d returned %X\n", context->cycles, value); |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1757 return value; |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1758 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1759 |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1760 uint16_t vdp_data_port_read(vdp_context * context) |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1761 { |
980
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
1762 if (context->flags & FLAG_PENDING) { |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
1763 context->flags &= ~FLAG_PENDING; |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
1764 //Should these be cleared here? |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
1765 context->flags &= ~FLAG_READ_FETCHED; |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
1766 context->flags2 &= ~FLAG2_READ_PENDING; |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
1767 } |
138 | 1768 if (context->cd & 1) { |
991
f9ee6f746cb4
Properly emulate machine freeze when reading from VDP while configured for writes
Michael Pavone <pavone@retrodev.com>
parents:
984
diff
changeset
|
1769 warning("Read from VDP data port while writes are configured, CPU is now frozen. VDP Address: %X, CD: %X\n", context->address, context->cd); |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1770 } |
991
f9ee6f746cb4
Properly emulate machine freeze when reading from VDP while configured for writes
Michael Pavone <pavone@retrodev.com>
parents:
984
diff
changeset
|
1771 uint32_t old_frame = context->frame; |
980
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
1772 while (!(context->flags & FLAG_READ_FETCHED)) { |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1773 vdp_run_context(context, context->cycles + ((context->regs[REG_MODE_4] & BIT_H40) ? 16 : 20)); |
991
f9ee6f746cb4
Properly emulate machine freeze when reading from VDP while configured for writes
Michael Pavone <pavone@retrodev.com>
parents:
984
diff
changeset
|
1774 if (context->frame != old_frame) { |
f9ee6f746cb4
Properly emulate machine freeze when reading from VDP while configured for writes
Michael Pavone <pavone@retrodev.com>
parents:
984
diff
changeset
|
1775 if (!headless) { |
f9ee6f746cb4
Properly emulate machine freeze when reading from VDP while configured for writes
Michael Pavone <pavone@retrodev.com>
parents:
984
diff
changeset
|
1776 //TODO: make pushing frames to renderer automatic so this doesn't need to be here |
f9ee6f746cb4
Properly emulate machine freeze when reading from VDP while configured for writes
Michael Pavone <pavone@retrodev.com>
parents:
984
diff
changeset
|
1777 wait_render_frame(context, 0); |
f9ee6f746cb4
Properly emulate machine freeze when reading from VDP while configured for writes
Michael Pavone <pavone@retrodev.com>
parents:
984
diff
changeset
|
1778 } |
f9ee6f746cb4
Properly emulate machine freeze when reading from VDP while configured for writes
Michael Pavone <pavone@retrodev.com>
parents:
984
diff
changeset
|
1779 old_frame = context->frame; |
f9ee6f746cb4
Properly emulate machine freeze when reading from VDP while configured for writes
Michael Pavone <pavone@retrodev.com>
parents:
984
diff
changeset
|
1780 } |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1781 } |
980
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
1782 context->flags &= ~FLAG_READ_FETCHED; |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
1783 //Should this happen after the prefetch or after the read? |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1784 context->address += context->regs[REG_AUTOINC]; |
980
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
1785 return context->prefetch; |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1786 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1787 |
137 | 1788 uint16_t vdp_hv_counter_read(vdp_context * context) |
1789 { | |
480
0737953132ad
Implement HV counter latch
Mike Pavone <pavone@retrodev.com>
parents:
479
diff
changeset
|
1790 if (context->regs[REG_MODE_1] & BIT_HVC_LATCH) { |
0737953132ad
Implement HV counter latch
Mike Pavone <pavone@retrodev.com>
parents:
479
diff
changeset
|
1791 return context->hv_latch; |
0737953132ad
Implement HV counter latch
Mike Pavone <pavone@retrodev.com>
parents:
479
diff
changeset
|
1792 } |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1793 uint32_t line= context->vcounter & 0xFF; |
647
5d58dcd94733
Fix the HV counter and adjust the slots of certain VDP events
Michael Pavone <pavone@retrodev.com>
parents:
629
diff
changeset
|
1794 uint32_t linecyc = context->hslot; |
137 | 1795 linecyc &= 0xFF; |
413
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1796 if (context->double_res) { |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1797 line <<= 1; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1798 if (line & 0x100) { |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1799 line |= 1; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1800 } |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1801 } |
137 | 1802 return (line << 8) | linecyc; |
1803 } | |
1804 | |
470
541c1ae8abf3
Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1805 uint16_t vdp_test_port_read(vdp_context * context) |
541c1ae8abf3
Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1806 { |
541c1ae8abf3
Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1807 //TODO: Find out what actually gets returned here |
541c1ae8abf3
Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1808 return 0xFFFF; |
541c1ae8abf3
Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1809 } |
541c1ae8abf3
Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1810 |
65
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1811 void vdp_adjust_cycles(vdp_context * context, uint32_t deduction) |
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1812 { |
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1813 context->cycles -= deduction; |
717
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1814 if (context->pending_vint_start >= deduction) { |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1815 context->pending_vint_start -= deduction; |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1816 } else { |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1817 context->pending_vint_start = 0; |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1818 } |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1819 if (context->pending_hint_start >= deduction) { |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1820 context->pending_hint_start -= deduction; |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1821 } else { |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1822 context->pending_hint_start = 0; |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1823 } |
471
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1824 if (context->fifo_read >= 0) { |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1825 int32_t idx = context->fifo_read; |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1826 do { |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1827 if (context->fifo[idx].cycle >= deduction) { |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1828 context->fifo[idx].cycle -= deduction; |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1829 } else { |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1830 context->fifo[idx].cycle = 0; |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1831 } |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1832 idx = (idx+1) & (FIFO_SIZE-1); |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1833 } while(idx != context->fifo_write); |
65
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1834 } |
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1835 } |
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1836 |
717
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1837 uint32_t vdp_cycles_hslot_wrap_h40(vdp_context * context) |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1838 { |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1839 if (context->hslot < 183) { |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1840 return MCLKS_LINE - context->hslot * MCLKS_SLOT_H40; |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1841 } else if (context->hslot < HSYNC_END_H40) { |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1842 uint32_t before_hsync = context->hslot < HSYNC_SLOT_H40 ? (HSYNC_SLOT_H40 - context->hslot) * MCLKS_SLOT_H40 : 0; |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1843 uint32_t hsync = 0; |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1844 for (int i = context->hslot <= HSYNC_SLOT_H40 ? 0 : context->hslot - HSYNC_SLOT_H40; i < sizeof(h40_hsync_cycles)/sizeof(uint32_t); i++) |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1845 { |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1846 hsync += h40_hsync_cycles[i]; |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1847 } |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1848 uint32_t after_hsync = (256- HSYNC_END_H40) * MCLKS_SLOT_H40; |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1849 return before_hsync + hsync + after_hsync; |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1850 } else { |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1851 return (256-context->hslot) * MCLKS_SLOT_H40; |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1852 } |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1853 } |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1854 |
623
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1855 uint32_t vdp_cycles_next_line(vdp_context * context) |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1856 { |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1857 if (context->regs[REG_MODE_4] & BIT_H40) { |
647
5d58dcd94733
Fix the HV counter and adjust the slots of certain VDP events
Michael Pavone <pavone@retrodev.com>
parents:
629
diff
changeset
|
1858 if (context->hslot < LINE_CHANGE_H40) { |
697
7f96bd1cb1be
Sync fixes and logging to fix more sync issues
Michael Pavone <pavone@retrodev.com>
parents:
680
diff
changeset
|
1859 return (LINE_CHANGE_H40 - context->hslot) * MCLKS_SLOT_H40; |
623
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1860 } else { |
717
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1861 return vdp_cycles_hslot_wrap_h40(context) + LINE_CHANGE_H40 * MCLKS_SLOT_H40; |
623
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1862 } |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1863 } else { |
647
5d58dcd94733
Fix the HV counter and adjust the slots of certain VDP events
Michael Pavone <pavone@retrodev.com>
parents:
629
diff
changeset
|
1864 if (context->hslot < LINE_CHANGE_H32) { |
5d58dcd94733
Fix the HV counter and adjust the slots of certain VDP events
Michael Pavone <pavone@retrodev.com>
parents:
629
diff
changeset
|
1865 return (LINE_CHANGE_H32 - context->hslot) * MCLKS_SLOT_H32; |
623
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1866 } else if (context->hslot < 148) { |
647
5d58dcd94733
Fix the HV counter and adjust the slots of certain VDP events
Michael Pavone <pavone@retrodev.com>
parents:
629
diff
changeset
|
1867 return MCLKS_LINE - (context->hslot - LINE_CHANGE_H32) * MCLKS_SLOT_H32; |
623
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1868 } else { |
647
5d58dcd94733
Fix the HV counter and adjust the slots of certain VDP events
Michael Pavone <pavone@retrodev.com>
parents:
629
diff
changeset
|
1869 return (256-context->hslot + LINE_CHANGE_H32) * MCLKS_SLOT_H32; |
623
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1870 } |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1871 } |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1872 } |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1873 |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1874 uint32_t vdp_cycles_to_line(vdp_context * context, uint32_t target) |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1875 { |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1876 uint32_t jump_start, jump_dst; |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1877 if (context->flags2 & FLAG2_REGION_PAL) { |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1878 if (context->latched_mode & BIT_PAL) { |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1879 jump_start = 0x10B; |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1880 jump_dst = 0x1D2; |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1881 } else { |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1882 jump_start = 0x103; |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1883 jump_dst = 0x1CA; |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1884 } |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1885 } else { |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1886 if (context->latched_mode & BIT_PAL) { |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1887 jump_start = 0; |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1888 jump_dst = 0; |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1889 } else { |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1890 jump_start = 0xEB; |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1891 jump_dst = 0x1E5; |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1892 } |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1893 } |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1894 uint32_t lines; |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1895 if (context->vcounter < target) { |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1896 if (target < jump_start) { |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1897 lines = target - context->vcounter; |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1898 } else { |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1899 lines = jump_start - context->vcounter + target - jump_dst; |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1900 } |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1901 } else { |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1902 if (context->vcounter < jump_start) { |
718
eaba6789f316
Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents:
717
diff
changeset
|
1903 lines = jump_start - context->vcounter + 512 - jump_dst; |
623
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1904 } else { |
718
eaba6789f316
Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents:
717
diff
changeset
|
1905 lines = 512 - context->vcounter; |
623
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1906 } |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1907 if (target < jump_start) { |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1908 lines += target; |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1909 } else { |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1910 lines += jump_start + target - jump_dst; |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1911 } |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1912 } |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1913 return MCLKS_LINE * (lines - 1) + vdp_cycles_next_line(context); |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1914 } |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1915 |
680
4996369f1463
Some small synchronization improvements that do not seem to fix anything
Michael Pavone <pavone@retrodev.com>
parents:
678
diff
changeset
|
1916 uint32_t vdp_frame_end_line(vdp_context * context) |
623
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1917 { |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1918 uint32_t frame_end; |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1919 if (context->flags2 & FLAG2_REGION_PAL) { |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1920 if (context->latched_mode & BIT_PAL) { |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1921 frame_end = PAL_INACTIVE_START + 8; |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1922 } else { |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1923 frame_end = NTSC_INACTIVE_START + 8; |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1924 } |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1925 } else { |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1926 if (context->latched_mode & BIT_PAL) { |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1927 frame_end = 512; |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1928 } else { |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1929 frame_end = NTSC_INACTIVE_START + 8; |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1930 } |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1931 } |
680
4996369f1463
Some small synchronization improvements that do not seem to fix anything
Michael Pavone <pavone@retrodev.com>
parents:
678
diff
changeset
|
1932 return frame_end; |
4996369f1463
Some small synchronization improvements that do not seem to fix anything
Michael Pavone <pavone@retrodev.com>
parents:
678
diff
changeset
|
1933 } |
4996369f1463
Some small synchronization improvements that do not seem to fix anything
Michael Pavone <pavone@retrodev.com>
parents:
678
diff
changeset
|
1934 |
4996369f1463
Some small synchronization improvements that do not seem to fix anything
Michael Pavone <pavone@retrodev.com>
parents:
678
diff
changeset
|
1935 uint32_t vdp_cycles_to_frame_end(vdp_context * context) |
4996369f1463
Some small synchronization improvements that do not seem to fix anything
Michael Pavone <pavone@retrodev.com>
parents:
678
diff
changeset
|
1936 { |
4996369f1463
Some small synchronization improvements that do not seem to fix anything
Michael Pavone <pavone@retrodev.com>
parents:
678
diff
changeset
|
1937 return context->cycles + vdp_cycles_to_line(context, vdp_frame_end_line(context)); |
4996369f1463
Some small synchronization improvements that do not seem to fix anything
Michael Pavone <pavone@retrodev.com>
parents:
678
diff
changeset
|
1938 } |
4996369f1463
Some small synchronization improvements that do not seem to fix anything
Michael Pavone <pavone@retrodev.com>
parents:
678
diff
changeset
|
1939 |
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1940 uint32_t vdp_next_hint(vdp_context * context) |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1941 { |
327
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
1942 if (!(context->regs[REG_MODE_1] & BIT_HINT_EN)) { |
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1943 return 0xFFFFFFFF; |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1944 } |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1945 if (context->flags2 & FLAG2_HINT_PENDING) { |
717
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1946 return context->pending_hint_start; |
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1947 } |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1948 uint32_t inactive_start = context->latched_mode & BIT_PAL ? PAL_INACTIVE_START : NTSC_INACTIVE_START; |
623
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1949 uint32_t hint_line; |
708
61faa298af07
Small horizontal interrupt fixes
Michael Pavone <pavone@retrodev.com>
parents:
705
diff
changeset
|
1950 if (context->vcounter + context->hint_counter >= inactive_start) { |
724
2174f92c5f9b
Fix bug in vdp_next_hint that was causing HINTs to fire repeatedly when they should not have fired at all based on an HINT interval that was larger than the number of active lines in the display
Michael Pavone <pavone@retrodev.com>
parents:
722
diff
changeset
|
1951 if (context->regs[REG_HINT] > inactive_start) { |
2174f92c5f9b
Fix bug in vdp_next_hint that was causing HINTs to fire repeatedly when they should not have fired at all based on an HINT interval that was larger than the number of active lines in the display
Michael Pavone <pavone@retrodev.com>
parents:
722
diff
changeset
|
1952 return 0xFFFFFFFF; |
2174f92c5f9b
Fix bug in vdp_next_hint that was causing HINTs to fire repeatedly when they should not have fired at all based on an HINT interval that was larger than the number of active lines in the display
Michael Pavone <pavone@retrodev.com>
parents:
722
diff
changeset
|
1953 } |
623
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1954 hint_line = context->regs[REG_HINT]; |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1955 } else { |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1956 hint_line = context->vcounter + context->hint_counter + 1; |
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1957 } |
623
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1958 |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1959 return context->cycles + vdp_cycles_to_line(context, hint_line); |
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1960 } |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1961 |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1962 uint32_t vdp_next_vint(vdp_context * context) |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1963 { |
327
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
1964 if (!(context->regs[REG_MODE_2] & BIT_VINT_EN)) { |
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1965 return 0xFFFFFFFF; |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1966 } |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1967 if (context->flags2 & FLAG2_VINT_PENDING) { |
717
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1968 return context->pending_vint_start; |
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1969 } |
623
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1970 |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1971 |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1972 return vdp_next_vint_z80(context); |
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1973 } |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1974 |
333 | 1975 uint32_t vdp_next_vint_z80(vdp_context * context) |
1976 { | |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1977 uint32_t inactive_start = context->latched_mode & BIT_PAL ? PAL_INACTIVE_START : NTSC_INACTIVE_START; |
623
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1978 if (context->vcounter == inactive_start) { |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1979 if (context->regs[REG_MODE_4] & BIT_H40) { |
995
2bc27415565b
Fix some stuff with interrupt timing. The change in adjust_int_cycle gets Overdrive working again (vint was not being preferred over hint in some cases). One of the changes seems to have broken Fatal Rewind again, but no other regressions that I can see.
Michael Pavone <pavone@retrodev.com>
parents:
991
diff
changeset
|
1980 if (context->hslot >= LINE_CHANGE_H40 && context->hslot <= VINT_SLOT_H40) { |
2bc27415565b
Fix some stuff with interrupt timing. The change in adjust_int_cycle gets Overdrive working again (vint was not being preferred over hint in some cases). One of the changes seems to have broken Fatal Rewind again, but no other regressions that I can see.
Michael Pavone <pavone@retrodev.com>
parents:
991
diff
changeset
|
1981 uint32_t cycles = context->cycles; |
2bc27415565b
Fix some stuff with interrupt timing. The change in adjust_int_cycle gets Overdrive working again (vint was not being preferred over hint in some cases). One of the changes seems to have broken Fatal Rewind again, but no other regressions that I can see.
Michael Pavone <pavone@retrodev.com>
parents:
991
diff
changeset
|
1982 if (context->hslot < 182) { |
2bc27415565b
Fix some stuff with interrupt timing. The change in adjust_int_cycle gets Overdrive working again (vint was not being preferred over hint in some cases). One of the changes seems to have broken Fatal Rewind again, but no other regressions that I can see.
Michael Pavone <pavone@retrodev.com>
parents:
991
diff
changeset
|
1983 cycles += (182 - context->hslot) * MCLKS_SLOT_H40; |
2bc27415565b
Fix some stuff with interrupt timing. The change in adjust_int_cycle gets Overdrive working again (vint was not being preferred over hint in some cases). One of the changes seems to have broken Fatal Rewind again, but no other regressions that I can see.
Michael Pavone <pavone@retrodev.com>
parents:
991
diff
changeset
|
1984 } |
2bc27415565b
Fix some stuff with interrupt timing. The change in adjust_int_cycle gets Overdrive working again (vint was not being preferred over hint in some cases). One of the changes seems to have broken Fatal Rewind again, but no other regressions that I can see.
Michael Pavone <pavone@retrodev.com>
parents:
991
diff
changeset
|
1985 |
2bc27415565b
Fix some stuff with interrupt timing. The change in adjust_int_cycle gets Overdrive working again (vint was not being preferred over hint in some cases). One of the changes seems to have broken Fatal Rewind again, but no other regressions that I can see.
Michael Pavone <pavone@retrodev.com>
parents:
991
diff
changeset
|
1986 if (context->hslot < 229) { |
2bc27415565b
Fix some stuff with interrupt timing. The change in adjust_int_cycle gets Overdrive working again (vint was not being preferred over hint in some cases). One of the changes seems to have broken Fatal Rewind again, but no other regressions that I can see.
Michael Pavone <pavone@retrodev.com>
parents:
991
diff
changeset
|
1987 cycles += h40_hsync_cycles[0]; |
2bc27415565b
Fix some stuff with interrupt timing. The change in adjust_int_cycle gets Overdrive working again (vint was not being preferred over hint in some cases). One of the changes seems to have broken Fatal Rewind again, but no other regressions that I can see.
Michael Pavone <pavone@retrodev.com>
parents:
991
diff
changeset
|
1988 } |
2bc27415565b
Fix some stuff with interrupt timing. The change in adjust_int_cycle gets Overdrive working again (vint was not being preferred over hint in some cases). One of the changes seems to have broken Fatal Rewind again, but no other regressions that I can see.
Michael Pavone <pavone@retrodev.com>
parents:
991
diff
changeset
|
1989 for (int slot = context->hslot <= 229 ? 229 : context->hslot; slot < HSYNC_END_H40; slot++ ) |
2bc27415565b
Fix some stuff with interrupt timing. The change in adjust_int_cycle gets Overdrive working again (vint was not being preferred over hint in some cases). One of the changes seems to have broken Fatal Rewind again, but no other regressions that I can see.
Michael Pavone <pavone@retrodev.com>
parents:
991
diff
changeset
|
1990 { |
2bc27415565b
Fix some stuff with interrupt timing. The change in adjust_int_cycle gets Overdrive working again (vint was not being preferred over hint in some cases). One of the changes seems to have broken Fatal Rewind again, but no other regressions that I can see.
Michael Pavone <pavone@retrodev.com>
parents:
991
diff
changeset
|
1991 cycles += h40_hsync_cycles[slot - HSYNC_SLOT_H40]; |
2bc27415565b
Fix some stuff with interrupt timing. The change in adjust_int_cycle gets Overdrive working again (vint was not being preferred over hint in some cases). One of the changes seems to have broken Fatal Rewind again, but no other regressions that I can see.
Michael Pavone <pavone@retrodev.com>
parents:
991
diff
changeset
|
1992 } |
2bc27415565b
Fix some stuff with interrupt timing. The change in adjust_int_cycle gets Overdrive working again (vint was not being preferred over hint in some cases). One of the changes seems to have broken Fatal Rewind again, but no other regressions that I can see.
Michael Pavone <pavone@retrodev.com>
parents:
991
diff
changeset
|
1993 cycles += (VINT_SLOT_H40 - (context->hslot > HSYNC_SLOT_H40 ? context->hslot : HSYNC_SLOT_H40)) * MCLKS_SLOT_H40; |
2bc27415565b
Fix some stuff with interrupt timing. The change in adjust_int_cycle gets Overdrive working again (vint was not being preferred over hint in some cases). One of the changes seems to have broken Fatal Rewind again, but no other regressions that I can see.
Michael Pavone <pavone@retrodev.com>
parents:
991
diff
changeset
|
1994 return cycles; |
623
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1995 } |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1996 } else { |
995
2bc27415565b
Fix some stuff with interrupt timing. The change in adjust_int_cycle gets Overdrive working again (vint was not being preferred over hint in some cases). One of the changes seems to have broken Fatal Rewind again, but no other regressions that I can see.
Michael Pavone <pavone@retrodev.com>
parents:
991
diff
changeset
|
1997 if (context->hslot >= LINE_CHANGE_H32 && context->hslot <= VINT_SLOT_H32) { |
2bc27415565b
Fix some stuff with interrupt timing. The change in adjust_int_cycle gets Overdrive working again (vint was not being preferred over hint in some cases). One of the changes seems to have broken Fatal Rewind again, but no other regressions that I can see.
Michael Pavone <pavone@retrodev.com>
parents:
991
diff
changeset
|
1998 if (context->hslot < 233) { |
2bc27415565b
Fix some stuff with interrupt timing. The change in adjust_int_cycle gets Overdrive working again (vint was not being preferred over hint in some cases). One of the changes seems to have broken Fatal Rewind again, but no other regressions that I can see.
Michael Pavone <pavone@retrodev.com>
parents:
991
diff
changeset
|
1999 return context->cycles + (148 - context->hslot + VINT_SLOT_H40 - 233) * MCLKS_SLOT_H32; |
623
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
2000 } else { |
995
2bc27415565b
Fix some stuff with interrupt timing. The change in adjust_int_cycle gets Overdrive working again (vint was not being preferred over hint in some cases). One of the changes seems to have broken Fatal Rewind again, but no other regressions that I can see.
Michael Pavone <pavone@retrodev.com>
parents:
991
diff
changeset
|
2001 return context->cycles + (VINT_SLOT_H32 - context->hslot) * MCLKS_SLOT_H32; |
623
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
2002 } |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
2003 } |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
2004 } |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
2005 } |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
2006 int32_t cycles_to_vint = vdp_cycles_to_line(context, inactive_start); |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
2007 if (context->regs[REG_MODE_4] & BIT_H40) { |
995
2bc27415565b
Fix some stuff with interrupt timing. The change in adjust_int_cycle gets Overdrive working again (vint was not being preferred over hint in some cases). One of the changes seems to have broken Fatal Rewind again, but no other regressions that I can see.
Michael Pavone <pavone@retrodev.com>
parents:
991
diff
changeset
|
2008 cycles_to_vint += MCLKS_LINE - (LINE_CHANGE_H40 + (256 - VINT_SLOT_H40)) * MCLKS_SLOT_H40; |
333 | 2009 } else { |
995
2bc27415565b
Fix some stuff with interrupt timing. The change in adjust_int_cycle gets Overdrive working again (vint was not being preferred over hint in some cases). One of the changes seems to have broken Fatal Rewind again, but no other regressions that I can see.
Michael Pavone <pavone@retrodev.com>
parents:
991
diff
changeset
|
2010 cycles_to_vint += (VINT_SLOT_H32 - 233 + 148 - LINE_CHANGE_H32) * MCLKS_SLOT_H32; |
333 | 2011 } |
623
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
2012 return context->cycles + cycles_to_vint; |
333 | 2013 } |
2014 | |
953
08346262990b
Remove the int number argument to vdp_int_ack since it is no longer used
Michael Pavone <pavone@retrodev.com>
parents:
952
diff
changeset
|
2015 void vdp_int_ack(vdp_context * context) |
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
2016 { |
952
7f4a7f07f325
Fix VDP interrupt ack. Big thanks to Eke-Eke or whoever left that helpful comment in Genesis Plus GX. Fixes Fatal Rewind
Michael Pavone <pavone@retrodev.com>
parents:
924
diff
changeset
|
2017 //Apparently the VDP interrupt controller is not very smart |
7f4a7f07f325
Fix VDP interrupt ack. Big thanks to Eke-Eke or whoever left that helpful comment in Genesis Plus GX. Fixes Fatal Rewind
Michael Pavone <pavone@retrodev.com>
parents:
924
diff
changeset
|
2018 //Instead of paying attention to what interrupt is being acknowledged it just |
7f4a7f07f325
Fix VDP interrupt ack. Big thanks to Eke-Eke or whoever left that helpful comment in Genesis Plus GX. Fixes Fatal Rewind
Michael Pavone <pavone@retrodev.com>
parents:
924
diff
changeset
|
2019 //clears the pending flag for whatever interrupt it is currently asserted |
7f4a7f07f325
Fix VDP interrupt ack. Big thanks to Eke-Eke or whoever left that helpful comment in Genesis Plus GX. Fixes Fatal Rewind
Michael Pavone <pavone@retrodev.com>
parents:
924
diff
changeset
|
2020 //which may be different from the interrupt it was asserting when the 68k |
7f4a7f07f325
Fix VDP interrupt ack. Big thanks to Eke-Eke or whoever left that helpful comment in Genesis Plus GX. Fixes Fatal Rewind
Michael Pavone <pavone@retrodev.com>
parents:
924
diff
changeset
|
2021 //started the interrupt process. The window for this is narrow and depends |
7f4a7f07f325
Fix VDP interrupt ack. Big thanks to Eke-Eke or whoever left that helpful comment in Genesis Plus GX. Fixes Fatal Rewind
Michael Pavone <pavone@retrodev.com>
parents:
924
diff
changeset
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2022 //on the latency between the int enable register write and the interrupt being |
7f4a7f07f325
Fix VDP interrupt ack. Big thanks to Eke-Eke or whoever left that helpful comment in Genesis Plus GX. Fixes Fatal Rewind
Michael Pavone <pavone@retrodev.com>
parents:
924
diff
changeset
|
2023 //asserted, but Fatal Rewind depends on this due to some buggy code |
7f4a7f07f325
Fix VDP interrupt ack. Big thanks to Eke-Eke or whoever left that helpful comment in Genesis Plus GX. Fixes Fatal Rewind
Michael Pavone <pavone@retrodev.com>
parents:
924
diff
changeset
|
2024 if ((context->flags2 & FLAG2_VINT_PENDING) && (context->regs[REG_MODE_2] & BIT_VINT_EN)) { |
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
2025 context->flags2 &= ~FLAG2_VINT_PENDING; |
952
7f4a7f07f325
Fix VDP interrupt ack. Big thanks to Eke-Eke or whoever left that helpful comment in Genesis Plus GX. Fixes Fatal Rewind
Michael Pavone <pavone@retrodev.com>
parents:
924
diff
changeset
|
2026 } else if((context->flags2 & FLAG2_HINT_PENDING) && (context->regs[REG_MODE_1] & BIT_HINT_EN)) { |
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
2027 context->flags2 &= ~FLAG2_HINT_PENDING; |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
2028 } |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
2029 } |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
2030 |