Mercurial > repos > blastem
annotate z80_to_x86.c @ 505:b7b7a1cab44a
The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
author | Michael Pavone <pavone@retrodev.com> |
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date | Mon, 06 Jan 2014 22:54:05 -0800 |
parents | 140af5509ce7 |
children | a3b48a57e847 |
rev | line source |
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1 /* |
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2 Copyright 2013 Michael Pavone |
505
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3 This file is part of BlastEm. |
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4 BlastEm is free software distributed under the terms of the GNU General Public License version 3 or greater. See COPYING for full license text. |
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5 */ |
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6 #include "z80inst.h" |
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7 #include "z80_to_x86.h" |
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8 #include "gen_x86.h" |
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9 #include "mem.h" |
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10 #include <stdio.h> |
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11 #include <stdlib.h> |
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12 #include <stddef.h> |
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13 #include <string.h> |
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14 |
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15 #define MODE_UNUSED (MODE_IMMED-1) |
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16 |
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17 #define ZCYCLES RBP |
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18 #define ZLIMIT RDI |
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19 #define SCRATCH1 R13 |
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20 #define SCRATCH2 R14 |
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21 #define CONTEXT RSI |
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22 |
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23 //#define DO_DEBUG_PRINT |
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24 |
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25 #ifdef DO_DEBUG_PRINT |
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26 #define dprintf printf |
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27 #else |
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28 #define dprintf |
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29 #endif |
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30 |
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31 void z80_read_byte(); |
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32 void z80_read_word(); |
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33 void z80_write_byte(); |
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34 void z80_write_word_highfirst(); |
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35 void z80_write_word_lowfirst(); |
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36 void z80_save_context(); |
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37 void z80_native_addr(); |
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38 void z80_do_sync(); |
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39 void z80_handle_cycle_limit_int(); |
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40 void z80_retrans_stub(); |
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41 void z80_io_read(); |
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42 void z80_io_write(); |
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43 void z80_halt(); |
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44 void z80_save_context(); |
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45 void z80_load_context(); |
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46 |
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47 uint8_t z80_size(z80inst * inst) |
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48 { |
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49 uint8_t reg = (inst->reg & 0x1F); |
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50 if (reg != Z80_UNUSED && reg != Z80_USE_IMMED) { |
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51 return reg < Z80_BC ? SZ_B : SZ_W; |
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52 } |
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53 //TODO: Handle any necessary special cases |
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54 return SZ_B; |
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55 } |
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56 |
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57 uint8_t * zcycles(uint8_t * dst, uint32_t num_cycles) |
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58 { |
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59 return add_ir(dst, num_cycles, ZCYCLES, SZ_D); |
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60 } |
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61 |
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62 uint8_t * z80_check_cycles_int(uint8_t * dst, uint16_t address) |
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63 { |
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64 dst = cmp_rr(dst, ZCYCLES, ZLIMIT, SZ_D); |
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65 uint8_t * jmp_off = dst+1; |
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66 dst = jcc(dst, CC_NC, dst + 7); |
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67 dst = mov_ir(dst, address, SCRATCH1, SZ_W); |
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68 dst = call(dst, (uint8_t *)z80_handle_cycle_limit_int); |
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69 *jmp_off = dst - (jmp_off+1); |
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70 return dst; |
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71 } |
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72 |
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73 uint8_t * translate_z80_reg(z80inst * inst, x86_ea * ea, uint8_t * dst, x86_z80_options * opts) |
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74 { |
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75 if (inst->reg == Z80_USE_IMMED) { |
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76 ea->mode = MODE_IMMED; |
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77 ea->disp = inst->immed; |
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78 } else if ((inst->reg & 0x1F) == Z80_UNUSED) { |
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79 ea->mode = MODE_UNUSED; |
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80 } else { |
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81 ea->mode = MODE_REG_DIRECT; |
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82 if (inst->reg == Z80_IYH) { |
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83 if ((inst->addr_mode & 0x1F) == Z80_REG && inst->ea_reg == Z80_IYL) { |
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84 dst = mov_rr(dst, opts->regs[Z80_IY], SCRATCH1, SZ_W); |
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85 dst = ror_ir(dst, 8, SCRATCH1, SZ_W); |
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86 ea->base = SCRATCH1; |
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87 } else { |
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88 ea->base = opts->regs[Z80_IYL]; |
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89 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W); |
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90 } |
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91 } else if(opts->regs[inst->reg] >= 0) { |
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92 ea->base = opts->regs[inst->reg]; |
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93 if (ea->base >= AH && ea->base <= BH) { |
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94 if ((inst->addr_mode & 0x1F) == Z80_REG) { |
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95 uint8_t other_reg = opts->regs[inst->ea_reg]; |
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96 if (other_reg >= R8 || (other_reg >= RSP && other_reg <= RDI)) { |
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97 //we can't mix an *H reg with a register that requires the REX prefix |
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98 ea->base = opts->regs[z80_low_reg(inst->reg)]; |
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99 dst = ror_ir(dst, 8, ea->base, SZ_W); |
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100 } |
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101 } else if((inst->addr_mode & 0x1F) != Z80_UNUSED && (inst->addr_mode & 0x1F) != Z80_IMMED) { |
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102 //temp regs require REX prefix too |
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103 ea->base = opts->regs[z80_low_reg(inst->reg)]; |
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104 dst = ror_ir(dst, 8, ea->base, SZ_W); |
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105 } |
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106 } |
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107 } else { |
262
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108 ea->mode = MODE_REG_DISPLACE8; |
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109 ea->base = CONTEXT; |
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110 ea->disp = offsetof(z80_context, regs) + inst->reg; |
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111 } |
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112 } |
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113 return dst; |
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114 } |
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115 |
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116 uint8_t * z80_save_reg(uint8_t * dst, z80inst * inst, x86_z80_options * opts) |
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117 { |
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118 if (inst->reg == Z80_IYH) { |
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119 if ((inst->addr_mode & 0x1F) == Z80_REG && inst->ea_reg == Z80_IYL) { |
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120 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W); |
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121 dst = mov_rr(dst, SCRATCH1, opts->regs[Z80_IYL], SZ_B); |
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122 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W); |
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123 } else { |
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124 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W); |
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125 } |
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126 } else if (opts->regs[inst->reg] >= AH && opts->regs[inst->reg] <= BH) { |
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127 if ((inst->addr_mode & 0x1F) == Z80_REG) { |
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128 uint8_t other_reg = opts->regs[inst->ea_reg]; |
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129 if (other_reg >= R8 || (other_reg >= RSP && other_reg <= RDI)) { |
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130 //we can't mix an *H reg with a register that requires the REX prefix |
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131 dst = ror_ir(dst, 8, opts->regs[z80_low_reg(inst->reg)], SZ_W); |
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132 } |
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133 } else if((inst->addr_mode & 0x1F) != Z80_UNUSED && (inst->addr_mode & 0x1F) != Z80_IMMED) { |
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134 //temp regs require REX prefix too |
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135 dst = ror_ir(dst, 8, opts->regs[z80_low_reg(inst->reg)], SZ_W); |
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136 } |
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137 } |
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138 return dst; |
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139 } |
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140 |
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141 uint8_t * translate_z80_ea(z80inst * inst, x86_ea * ea, uint8_t * dst, x86_z80_options * opts, uint8_t read, uint8_t modify) |
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142 { |
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143 uint8_t size, reg, areg; |
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144 ea->mode = MODE_REG_DIRECT; |
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145 areg = read ? SCRATCH1 : SCRATCH2; |
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146 switch(inst->addr_mode & 0x1F) |
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147 { |
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148 case Z80_REG: |
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149 if (inst->ea_reg == Z80_IYH) { |
312
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150 if (inst->reg == Z80_IYL) { |
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151 dst = mov_rr(dst, opts->regs[Z80_IY], SCRATCH1, SZ_W); |
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152 dst = ror_ir(dst, 8, SCRATCH1, SZ_W); |
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153 ea->base = SCRATCH1; |
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154 } else { |
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155 ea->base = opts->regs[Z80_IYL]; |
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156 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W); |
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157 } |
213
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158 } else { |
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159 ea->base = opts->regs[inst->ea_reg]; |
267
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160 if (ea->base >= AH && ea->base <= BH && inst->reg != Z80_UNUSED && inst->reg != Z80_USE_IMMED) { |
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161 uint8_t other_reg = opts->regs[inst->reg]; |
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162 if (other_reg >= R8 || (other_reg >= RSP && other_reg <= RDI)) { |
267
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163 //we can't mix an *H reg with a register that requires the REX prefix |
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164 ea->base = opts->regs[z80_low_reg(inst->ea_reg)]; |
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165 dst = ror_ir(dst, 8, ea->base, SZ_W); |
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166 } |
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167 } |
213
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168 } |
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169 break; |
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170 case Z80_REG_INDIRECT: |
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171 dst = mov_rr(dst, opts->regs[inst->ea_reg], areg, SZ_W); |
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172 size = z80_size(inst); |
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173 if (read) { |
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174 if (modify) { |
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175 //dst = push_r(dst, SCRATCH1); |
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176 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(z80_context, scratch1), SZ_W); |
213
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177 } |
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178 if (size == SZ_B) { |
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179 dst = call(dst, (uint8_t *)z80_read_byte); |
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180 } else { |
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181 dst = call(dst, (uint8_t *)z80_read_word); |
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182 } |
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183 if (modify) { |
277
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184 //dst = pop_r(dst, SCRATCH2); |
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185 dst = mov_rdisp8r(dst, CONTEXT, offsetof(z80_context, scratch1), SCRATCH2, SZ_W); |
213
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186 } |
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187 } |
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188 ea->base = SCRATCH1; |
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189 break; |
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190 case Z80_IMMED: |
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191 ea->mode = MODE_IMMED; |
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192 ea->disp = inst->immed; |
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193 break; |
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194 case Z80_IMMED_INDIRECT: |
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195 dst = mov_ir(dst, inst->immed, areg, SZ_W); |
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196 size = z80_size(inst); |
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197 if (read) { |
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198 /*if (modify) { |
213
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199 dst = push_r(dst, SCRATCH1); |
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200 }*/ |
213
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201 if (size == SZ_B) { |
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202 dst = call(dst, (uint8_t *)z80_read_byte); |
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203 } else { |
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204 dst = call(dst, (uint8_t *)z80_read_word); |
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205 } |
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206 if (modify) { |
277
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207 //dst = pop_r(dst, SCRATCH2); |
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208 dst = mov_ir(dst, inst->immed, SCRATCH2, SZ_W); |
213
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209 } |
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210 } |
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211 ea->base = SCRATCH1; |
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212 break; |
235
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213
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213 case Z80_IX_DISPLACE: |
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214 case Z80_IY_DISPLACE: |
300
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215 reg = opts->regs[(inst->addr_mode & 0x1F) == Z80_IX_DISPLACE ? Z80_IX : Z80_IY]; |
213
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216 dst = mov_rr(dst, reg, areg, SZ_W); |
306
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217 dst = add_ir(dst, inst->ea_reg & 0x80 ? inst->ea_reg - 256 : inst->ea_reg, areg, SZ_W); |
213
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218 size = z80_size(inst); |
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219 if (read) { |
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220 if (modify) { |
277
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221 //dst = push_r(dst, SCRATCH1); |
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222 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(z80_context, scratch1), SZ_W); |
213
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223 } |
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224 if (size == SZ_B) { |
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225 dst = call(dst, (uint8_t *)z80_read_byte); |
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226 } else { |
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227 dst = call(dst, (uint8_t *)z80_read_word); |
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228 } |
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229 if (modify) { |
277
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230 //dst = pop_r(dst, SCRATCH2); |
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231 dst = mov_rdisp8r(dst, CONTEXT, offsetof(z80_context, scratch1), SCRATCH2, SZ_W); |
213
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232 } |
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233 } |
269
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234 ea->base = SCRATCH1; |
213
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235 break; |
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236 case Z80_UNUSED: |
235
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237 ea->mode = MODE_UNUSED; |
213
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238 break; |
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239 default: |
300
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240 fprintf(stderr, "Unrecognized Z80 addressing mode %d\n", inst->addr_mode & 0x1F); |
213
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241 exit(1); |
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242 } |
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243 return dst; |
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244 } |
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245 |
235
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246 uint8_t * z80_save_ea(uint8_t * dst, z80inst * inst, x86_z80_options * opts) |
213
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247 { |
267
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248 if ((inst->addr_mode & 0x1F) == Z80_REG) { |
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249 if (inst->ea_reg == Z80_IYH) { |
312
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311
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250 if (inst->reg == Z80_IYL) { |
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251 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W); |
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252 dst = mov_rr(dst, SCRATCH1, opts->regs[Z80_IYL], SZ_B); |
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253 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W); |
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254 } else { |
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255 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W); |
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256 } |
267
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257 } else if (inst->reg != Z80_UNUSED && inst->reg != Z80_USE_IMMED && opts->regs[inst->ea_reg] >= AH && opts->regs[inst->ea_reg] <= BH) { |
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258 uint8_t other_reg = opts->regs[inst->reg]; |
269
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|
259 if (other_reg >= R8 || (other_reg >= RSP && other_reg <= RDI)) { |
267
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260 //we can't mix an *H reg with a register that requires the REX prefix |
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261 dst = ror_ir(dst, 8, opts->regs[z80_low_reg(inst->ea_reg)], SZ_W); |
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|
262 } |
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|
263 } |
213
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|
264 } |
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265 return dst; |
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266 } |
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267 |
235
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268 uint8_t * z80_save_result(uint8_t * dst, z80inst * inst) |
213
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269 { |
253
3b34deba4ca0
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270 switch(inst->addr_mode & 0x1f) |
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271 { |
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272 case Z80_REG_INDIRECT: |
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273 case Z80_IMMED_INDIRECT: |
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274 case Z80_IX_DISPLACE: |
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275 case Z80_IY_DISPLACE: |
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276 if (z80_size(inst) == SZ_B) { |
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277 dst = call(dst, (uint8_t *)z80_write_byte); |
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278 } else { |
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279 dst = call(dst, (uint8_t *)z80_write_word_lowfirst); |
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280 } |
213
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281 } |
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282 return dst; |
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283 } |
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284 |
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|
285 enum { |
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286 DONT_READ=0, |
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|
287 READ |
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|
288 }; |
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289 |
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|
290 enum { |
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291 DONT_MODIFY=0, |
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|
292 MODIFY |
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293 }; |
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294 |
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|
295 uint8_t zf_off(uint8_t flag) |
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296 { |
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297 return offsetof(z80_context, flags) + flag; |
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298 } |
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|
299 |
241
2586d49ddd46
Implement EX, EXX and RST in Z80 core
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239
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|
300 uint8_t zaf_off(uint8_t flag) |
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301 { |
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302 return offsetof(z80_context, alt_flags) + flag; |
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303 } |
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304 |
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305 uint8_t zar_off(uint8_t reg) |
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306 { |
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307 return offsetof(z80_context, alt_regs) + reg; |
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308 } |
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309 |
235
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310 void z80_print_regs_exit(z80_context * context) |
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311 { |
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312 printf("A: %X\nB: %X\nC: %X\nD: %X\nE: %X\nHL: %X\nIX: %X\nIY: %X\nSP: %X\n\nIM: %d, IFF1: %d, IFF2: %d\n", |
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313 context->regs[Z80_A], context->regs[Z80_B], context->regs[Z80_C], |
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314 context->regs[Z80_D], context->regs[Z80_E], |
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315 (context->regs[Z80_H] << 8) | context->regs[Z80_L], |
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316 (context->regs[Z80_IXH] << 8) | context->regs[Z80_IXL], |
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317 (context->regs[Z80_IYH] << 8) | context->regs[Z80_IYL], |
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318 context->sp, context->im, context->iff1, context->iff2); |
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319 puts("--Alternate Regs--"); |
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320 printf("A: %X\nB: %X\nC: %X\nD: %X\nE: %X\nHL: %X\nIX: %X\nIY: %X\n", |
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321 context->alt_regs[Z80_A], context->alt_regs[Z80_B], context->alt_regs[Z80_C], |
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322 context->alt_regs[Z80_D], context->alt_regs[Z80_E], |
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323 (context->alt_regs[Z80_H] << 8) | context->alt_regs[Z80_L], |
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324 (context->alt_regs[Z80_IXH] << 8) | context->alt_regs[Z80_IXL], |
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325 (context->alt_regs[Z80_IYH] << 8) | context->alt_regs[Z80_IYL]); |
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326 exit(0); |
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327 } |
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328 |
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329 uint8_t * translate_z80inst(z80inst * inst, uint8_t * dst, z80_context * context, uint16_t address) |
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330 { |
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331 uint32_t cycles; |
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332 x86_ea src_op, dst_op; |
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333 uint8_t size; |
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334 x86_z80_options *opts = context->options; |
261
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335 uint8_t * start = dst; |
250
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336 dst = z80_check_cycles_int(dst, address); |
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337 switch(inst->op) |
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338 { |
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339 case Z80_LD: |
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340 size = z80_size(inst); |
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341 switch (inst->addr_mode & 0x1F) |
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342 { |
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343 case Z80_REG: |
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344 case Z80_REG_INDIRECT: |
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345 cycles = size == SZ_B ? 4 : 6; |
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346 if (inst->ea_reg == Z80_IX || inst->ea_reg == Z80_IY) { |
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347 cycles += 4; |
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348 } |
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349 break; |
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350 case Z80_IMMED: |
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351 cycles = size == SZ_B ? 7 : 10; |
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352 break; |
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353 case Z80_IMMED_INDIRECT: |
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354 cycles = 10; |
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355 break; |
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356 case Z80_IX_DISPLACE: |
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357 case Z80_IY_DISPLACE: |
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358 cycles = 12; |
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359 break; |
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360 } |
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361 if ((inst->reg >= Z80_IXL && inst->reg <= Z80_IYH) || inst->reg == Z80_IX || inst->reg == Z80_IY) { |
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362 cycles += 4; |
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363 } |
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364 dst = zcycles(dst, cycles); |
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365 if (inst->addr_mode & Z80_DIR) { |
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366 dst = translate_z80_ea(inst, &dst_op, dst, opts, DONT_READ, MODIFY); |
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367 dst = translate_z80_reg(inst, &src_op, dst, opts); |
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368 } else { |
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369 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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370 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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371 } |
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372 if (src_op.mode == MODE_REG_DIRECT) { |
262
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373 if(dst_op.mode == MODE_REG_DISPLACE8) { |
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374 dst = mov_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, size); |
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375 } else { |
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376 dst = mov_rr(dst, src_op.base, dst_op.base, size); |
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377 } |
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378 } else if(src_op.mode == MODE_IMMED) { |
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379 dst = mov_ir(dst, src_op.disp, dst_op.base, size); |
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380 } else { |
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381 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, size); |
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382 } |
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383 dst = z80_save_reg(dst, inst, opts); |
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384 dst = z80_save_ea(dst, inst, opts); |
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385 if (inst->addr_mode & Z80_DIR) { |
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386 dst = z80_save_result(dst, inst); |
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387 } |
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388 break; |
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389 case Z80_PUSH: |
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390 dst = zcycles(dst, (inst->reg == Z80_IX || inst->reg == Z80_IY) ? 9 : 5); |
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391 dst = sub_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
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392 if (inst->reg == Z80_AF) { |
363 | 393 dst = mov_rr(dst, opts->regs[Z80_A], SCRATCH1, SZ_B); |
394 dst = shl_ir(dst, 8, SCRATCH1, SZ_W); | |
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395 dst = mov_rdisp8r(dst, CONTEXT, zf_off(ZF_S), SCRATCH1, SZ_B); |
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396 dst = shl_ir(dst, 1, SCRATCH1, SZ_B); |
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397 dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_Z), SCRATCH1, SZ_B); |
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398 dst = shl_ir(dst, 2, SCRATCH1, SZ_B); |
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399 dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_H), SCRATCH1, SZ_B); |
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400 dst = shl_ir(dst, 2, SCRATCH1, SZ_B); |
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401 dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_PV), SCRATCH1, SZ_B); |
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402 dst = shl_ir(dst, 1, SCRATCH1, SZ_B); |
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403 dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_N), SCRATCH1, SZ_B); |
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404 dst = shl_ir(dst, 1, SCRATCH1, SZ_B); |
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405 dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_C), SCRATCH1, SZ_B); |
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406 } else { |
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407 dst = translate_z80_reg(inst, &src_op, dst, opts); |
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408 dst = mov_rr(dst, src_op.base, SCRATCH1, SZ_W); |
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409 } |
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410 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W); |
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411 dst = call(dst, (uint8_t *)z80_write_word_highfirst); |
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412 //no call to save_z80_reg needed since there's no chance we'll use the only |
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413 //the upper half of a register pair |
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414 break; |
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415 case Z80_POP: |
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416 dst = zcycles(dst, (inst->reg == Z80_IX || inst->reg == Z80_IY) ? 8 : 4); |
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417 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
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418 dst = call(dst, (uint8_t *)z80_read_word); |
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419 dst = add_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
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420 if (inst->reg == Z80_AF) { |
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421 |
294 | 422 dst = bt_ir(dst, 0, SCRATCH1, SZ_W); |
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423 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
294 | 424 dst = bt_ir(dst, 1, SCRATCH1, SZ_W); |
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425 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_N)); |
294 | 426 dst = bt_ir(dst, 2, SCRATCH1, SZ_W); |
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427 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_PV)); |
294 | 428 dst = bt_ir(dst, 4, SCRATCH1, SZ_W); |
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429 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_H)); |
294 | 430 dst = bt_ir(dst, 6, SCRATCH1, SZ_W); |
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431 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_Z)); |
294 | 432 dst = bt_ir(dst, 7, SCRATCH1, SZ_W); |
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433 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_S)); |
294 | 434 dst = shr_ir(dst, 8, SCRATCH1, SZ_W); |
435 dst = mov_rr(dst, SCRATCH1, opts->regs[Z80_A], SZ_B); | |
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436 } else { |
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437 dst = translate_z80_reg(inst, &src_op, dst, opts); |
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438 dst = mov_rr(dst, SCRATCH1, src_op.base, SZ_W); |
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439 } |
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440 //no call to save_z80_reg needed since there's no chance we'll use the only |
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441 //the upper half of a register pair |
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442 break; |
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443 case Z80_EX: |
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444 if (inst->addr_mode == Z80_REG || inst->reg == Z80_HL) { |
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445 cycles = 4; |
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446 } else { |
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447 cycles = 8; |
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448 } |
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449 dst = zcycles(dst, cycles); |
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450 if (inst->addr_mode == Z80_REG) { |
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451 if(inst->reg == Z80_AF) { |
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452 dst = mov_rr(dst, opts->regs[Z80_A], SCRATCH1, SZ_B); |
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453 dst = mov_rdisp8r(dst, CONTEXT, zar_off(Z80_A), opts->regs[Z80_A], SZ_B); |
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454 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, zar_off(Z80_A), SZ_B); |
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455 |
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456 //Flags are currently word aligned, so we can move |
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457 //them efficiently a word at a time |
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458 for (int f = ZF_C; f < ZF_NUM; f+=2) { |
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459 dst = mov_rdisp8r(dst, CONTEXT, zf_off(f), SCRATCH1, SZ_W); |
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460 dst = mov_rdisp8r(dst, CONTEXT, zaf_off(f), SCRATCH2, SZ_W); |
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461 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, zaf_off(f), SZ_W); |
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462 dst = mov_rrdisp8(dst, SCRATCH2, CONTEXT, zf_off(f), SZ_W); |
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463 } |
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464 } else { |
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465 dst = xchg_rr(dst, opts->regs[Z80_DE], opts->regs[Z80_HL], SZ_W); |
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466 } |
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467 } else { |
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468 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
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469 dst = call(dst, (uint8_t *)z80_read_byte); |
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470 dst = xchg_rr(dst, opts->regs[inst->reg], SCRATCH1, SZ_B); |
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471 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W); |
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472 dst = call(dst, (uint8_t *)z80_write_byte); |
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473 dst = zcycles(dst, 1); |
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474 uint8_t high_reg = z80_high_reg(inst->reg); |
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475 uint8_t use_reg; |
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476 //even though some of the upper halves can be used directly |
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477 //the limitations on mixing *H regs with the REX prefix |
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478 //prevent us from taking advantage of it |
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479 use_reg = opts->regs[inst->reg]; |
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480 dst = ror_ir(dst, 8, use_reg, SZ_W); |
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481 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
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482 dst = add_ir(dst, 1, SCRATCH1, SZ_W); |
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483 dst = call(dst, (uint8_t *)z80_read_byte); |
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484 dst = xchg_rr(dst, use_reg, SCRATCH1, SZ_B); |
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485 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W); |
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486 dst = add_ir(dst, 1, SCRATCH2, SZ_W); |
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487 dst = call(dst, (uint8_t *)z80_write_byte); |
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488 //restore reg to normal rotation |
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489 dst = ror_ir(dst, 8, use_reg, SZ_W); |
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490 dst = zcycles(dst, 2); |
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491 } |
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492 break; |
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493 case Z80_EXX: |
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494 dst = zcycles(dst, 4); |
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495 dst = mov_rr(dst, opts->regs[Z80_BC], SCRATCH1, SZ_W); |
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496 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH2, SZ_W); |
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497 dst = mov_rdisp8r(dst, CONTEXT, zar_off(Z80_C), opts->regs[Z80_BC], SZ_W); |
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498 dst = mov_rdisp8r(dst, CONTEXT, zar_off(Z80_L), opts->regs[Z80_HL], SZ_W); |
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499 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, zar_off(Z80_C), SZ_W); |
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500 dst = mov_rrdisp8(dst, SCRATCH2, CONTEXT, zar_off(Z80_L), SZ_W); |
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501 dst = mov_rr(dst, opts->regs[Z80_DE], SCRATCH1, SZ_W); |
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502 dst = mov_rdisp8r(dst, CONTEXT, zar_off(Z80_E), opts->regs[Z80_DE], SZ_W); |
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503 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, zar_off(Z80_E), SZ_W); |
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504 break; |
272 | 505 case Z80_LDI: { |
506 dst = zcycles(dst, 8); | |
507 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH1, SZ_W); | |
508 dst = call(dst, (uint8_t *)z80_read_byte); | |
509 dst = mov_rr(dst, opts->regs[Z80_DE], SCRATCH2, SZ_W); | |
385 | 510 dst = call(dst, (uint8_t *)z80_write_byte); |
272 | 511 dst = zcycles(dst, 2); |
512 dst = add_ir(dst, 1, opts->regs[Z80_DE], SZ_W); | |
513 dst = add_ir(dst, 1, opts->regs[Z80_HL], SZ_W); | |
514 dst = sub_ir(dst, 1, opts->regs[Z80_BC], SZ_W); | |
515 //TODO: Implement half-carry | |
516 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); | |
517 dst = setcc_rdisp8(dst, CC_NZ, CONTEXT, zf_off(ZF_PV)); | |
518 break; | |
519 } | |
261
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520 case Z80_LDIR: { |
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521 dst = zcycles(dst, 8); |
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522 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH1, SZ_W); |
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523 dst = call(dst, (uint8_t *)z80_read_byte); |
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524 dst = mov_rr(dst, opts->regs[Z80_DE], SCRATCH2, SZ_W); |
397 | 525 dst = call(dst, (uint8_t *)z80_write_byte); |
261
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526 dst = add_ir(dst, 1, opts->regs[Z80_DE], SZ_W); |
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527 dst = add_ir(dst, 1, opts->regs[Z80_HL], SZ_W); |
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528 |
261
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529 dst = sub_ir(dst, 1, opts->regs[Z80_BC], SZ_W); |
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530 uint8_t * cont = dst+1; |
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531 dst = jcc(dst, CC_Z, dst+2); |
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532 dst = zcycles(dst, 7); |
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533 //TODO: Figure out what the flag state should be here |
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534 //TODO: Figure out whether an interrupt can interrupt this |
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535 dst = jmp(dst, start); |
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536 *cont = dst - (cont + 1); |
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537 dst = zcycles(dst, 2); |
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538 //TODO: Implement half-carry |
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539 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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540 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_PV), SZ_B); |
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541 break; |
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542 } |
273 | 543 case Z80_LDD: { |
544 dst = zcycles(dst, 8); | |
545 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH1, SZ_W); | |
546 dst = call(dst, (uint8_t *)z80_read_byte); | |
547 dst = mov_rr(dst, opts->regs[Z80_DE], SCRATCH2, SZ_W); | |
388 | 548 dst = call(dst, (uint8_t *)z80_write_byte); |
273 | 549 dst = zcycles(dst, 2); |
550 dst = sub_ir(dst, 1, opts->regs[Z80_DE], SZ_W); | |
551 dst = sub_ir(dst, 1, opts->regs[Z80_HL], SZ_W); | |
552 dst = sub_ir(dst, 1, opts->regs[Z80_BC], SZ_W); | |
553 //TODO: Implement half-carry | |
554 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); | |
555 dst = setcc_rdisp8(dst, CC_NZ, CONTEXT, zf_off(ZF_PV)); | |
556 break; | |
557 } | |
558 case Z80_LDDR: { | |
559 dst = zcycles(dst, 8); | |
560 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH1, SZ_W); | |
561 dst = call(dst, (uint8_t *)z80_read_byte); | |
562 dst = mov_rr(dst, opts->regs[Z80_DE], SCRATCH2, SZ_W); | |
388 | 563 dst = call(dst, (uint8_t *)z80_write_byte); |
273 | 564 dst = sub_ir(dst, 1, opts->regs[Z80_DE], SZ_W); |
565 dst = sub_ir(dst, 1, opts->regs[Z80_HL], SZ_W); | |
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566 |
273 | 567 dst = sub_ir(dst, 1, opts->regs[Z80_BC], SZ_W); |
568 uint8_t * cont = dst+1; | |
569 dst = jcc(dst, CC_Z, dst+2); | |
570 dst = zcycles(dst, 7); | |
571 //TODO: Figure out what the flag state should be here | |
572 //TODO: Figure out whether an interrupt can interrupt this | |
573 dst = jmp(dst, start); | |
574 *cont = dst - (cont + 1); | |
575 dst = zcycles(dst, 2); | |
576 //TODO: Implement half-carry | |
577 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); | |
578 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_PV), SZ_B); | |
579 break; | |
580 } | |
581 /*case Z80_CPI: | |
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582 case Z80_CPIR: |
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583 case Z80_CPD: |
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584 case Z80_CPDR: |
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585 break;*/ |
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586 case Z80_ADD: |
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587 cycles = 4; |
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588 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
213
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589 cycles += 12; |
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590 } else if(inst->addr_mode == Z80_IMMED) { |
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591 cycles += 3; |
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592 } else if(z80_size(inst) == SZ_W) { |
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593 cycles += 4; |
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594 } |
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595 dst = zcycles(dst, cycles); |
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596 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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597 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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598 if (src_op.mode == MODE_REG_DIRECT) { |
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599 dst = add_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
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600 } else { |
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601 dst = add_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
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602 } |
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603 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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604 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
213
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605 //TODO: Implement half-carry flag |
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606 if (z80_size(inst) == SZ_B) { |
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607 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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608 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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609 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
213
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610 } |
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611 dst = z80_save_reg(dst, inst, opts); |
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612 dst = z80_save_ea(dst, inst, opts); |
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613 break; |
248
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614 case Z80_ADC: |
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615 cycles = 4; |
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616 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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617 cycles += 12; |
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618 } else if(inst->addr_mode == Z80_IMMED) { |
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619 cycles += 3; |
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620 } else if(z80_size(inst) == SZ_W) { |
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621 cycles += 4; |
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622 } |
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623 dst = zcycles(dst, cycles); |
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624 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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625 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
399 | 626 dst = bt_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
248
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627 if (src_op.mode == MODE_REG_DIRECT) { |
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628 dst = adc_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
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629 } else { |
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630 dst = adc_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
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631 } |
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632 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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633 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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634 //TODO: Implement half-carry flag |
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635 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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636 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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637 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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638 dst = z80_save_reg(dst, inst, opts); |
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639 dst = z80_save_ea(dst, inst, opts); |
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640 break; |
213
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changeset
|
641 case Z80_SUB: |
4d4559b04c59
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|
642 cycles = 4; |
235
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643 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
213
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diff
changeset
|
644 cycles += 12; |
4d4559b04c59
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parents:
diff
changeset
|
645 } else if(inst->addr_mode == Z80_IMMED) { |
4d4559b04c59
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diff
changeset
|
646 cycles += 3; |
4d4559b04c59
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diff
changeset
|
647 } |
4d4559b04c59
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parents:
diff
changeset
|
648 dst = zcycles(dst, cycles); |
4d4559b04c59
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parents:
diff
changeset
|
649 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
4d4559b04c59
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diff
changeset
|
650 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
4d4559b04c59
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diff
changeset
|
651 if (src_op.mode == MODE_REG_DIRECT) { |
4d4559b04c59
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parents:
diff
changeset
|
652 dst = sub_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
4d4559b04c59
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diff
changeset
|
653 } else { |
4d4559b04c59
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changeset
|
654 dst = sub_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
4d4559b04c59
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changeset
|
655 } |
4d4559b04c59
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changeset
|
656 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
235
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657 dst = mov_irdisp8(dst, 1, CONTEXT, zf_off(ZF_N), SZ_B); |
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658 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
213
4d4559b04c59
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diff
changeset
|
659 //TODO: Implement half-carry flag |
235
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660 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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661 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
213
4d4559b04c59
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changeset
|
662 dst = z80_save_reg(dst, inst, opts); |
4d4559b04c59
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diff
changeset
|
663 dst = z80_save_ea(dst, inst, opts); |
4d4559b04c59
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|
664 break; |
248
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665 case Z80_SBC: |
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666 cycles = 4; |
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667 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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668 cycles += 12; |
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669 } else if(inst->addr_mode == Z80_IMMED) { |
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670 cycles += 3; |
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671 } else if(z80_size(inst) == SZ_W) { |
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672 cycles += 4; |
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673 } |
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674 dst = zcycles(dst, cycles); |
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675 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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676 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
399 | 677 dst = bt_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
248
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678 if (src_op.mode == MODE_REG_DIRECT) { |
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679 dst = sbb_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
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680 } else { |
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681 dst = sbb_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
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682 } |
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changeset
|
683 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
309
cb6a37861e42
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308
diff
changeset
|
684 dst = mov_irdisp8(dst, 1, CONTEXT, zf_off(ZF_N), SZ_B); |
248
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changeset
|
685 //TODO: Implement half-carry flag |
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686 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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247
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changeset
|
687 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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688 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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689 dst = z80_save_reg(dst, inst, opts); |
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690 dst = z80_save_ea(dst, inst, opts); |
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|
691 break; |
213
4d4559b04c59
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changeset
|
692 case Z80_AND: |
236
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235
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|
693 cycles = 4; |
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|
694 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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|
695 cycles += 12; |
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|
696 } else if(inst->addr_mode == Z80_IMMED) { |
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235
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|
697 cycles += 3; |
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|
698 } else if(z80_size(inst) == SZ_W) { |
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|
699 cycles += 4; |
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|
700 } |
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|
701 dst = zcycles(dst, cycles); |
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changeset
|
702 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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changeset
|
703 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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|
704 if (src_op.mode == MODE_REG_DIRECT) { |
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235
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|
705 dst = and_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
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235
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|
706 } else { |
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235
diff
changeset
|
707 dst = and_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
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235
diff
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|
708 } |
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diff
changeset
|
709 //TODO: Cleanup flags |
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235
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changeset
|
710 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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changeset
|
711 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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235
diff
changeset
|
712 //TODO: Implement half-carry flag |
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235
diff
changeset
|
713 if (z80_size(inst) == SZ_B) { |
305
a57fac5b3d65
Contrary to the official documenation, OR and AND also set PV based on parity instead of overflow
Mike Pavone <pavone@retrodev.com>
parents:
304
diff
changeset
|
714 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
236
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
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235
diff
changeset
|
715 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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235
diff
changeset
|
716 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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235
diff
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|
717 } |
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235
diff
changeset
|
718 dst = z80_save_reg(dst, inst, opts); |
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235
diff
changeset
|
719 dst = z80_save_ea(dst, inst, opts); |
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235
diff
changeset
|
720 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
721 case Z80_OR: |
236
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Mike Pavone <pavone@retrodev.com>
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235
diff
changeset
|
722 cycles = 4; |
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Mike Pavone <pavone@retrodev.com>
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235
diff
changeset
|
723 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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235
diff
changeset
|
724 cycles += 12; |
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Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
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235
diff
changeset
|
725 } else if(inst->addr_mode == Z80_IMMED) { |
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235
diff
changeset
|
726 cycles += 3; |
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Mike Pavone <pavone@retrodev.com>
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235
diff
changeset
|
727 } else if(z80_size(inst) == SZ_W) { |
19fb3523a9e5
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235
diff
changeset
|
728 cycles += 4; |
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235
diff
changeset
|
729 } |
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235
diff
changeset
|
730 dst = zcycles(dst, cycles); |
19fb3523a9e5
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235
diff
changeset
|
731 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
19fb3523a9e5
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235
diff
changeset
|
732 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
19fb3523a9e5
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235
diff
changeset
|
733 if (src_op.mode == MODE_REG_DIRECT) { |
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235
diff
changeset
|
734 dst = or_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
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235
diff
changeset
|
735 } else { |
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235
diff
changeset
|
736 dst = or_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
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235
diff
changeset
|
737 } |
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235
diff
changeset
|
738 //TODO: Cleanup flags |
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235
diff
changeset
|
739 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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parents:
235
diff
changeset
|
740 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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235
diff
changeset
|
741 //TODO: Implement half-carry flag |
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Mike Pavone <pavone@retrodev.com>
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235
diff
changeset
|
742 if (z80_size(inst) == SZ_B) { |
305
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743 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
236
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744 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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745 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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746 } |
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747 dst = z80_save_reg(dst, inst, opts); |
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748 dst = z80_save_ea(dst, inst, opts); |
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749 break; |
213
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750 case Z80_XOR: |
236
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751 cycles = 4; |
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752 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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753 cycles += 12; |
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754 } else if(inst->addr_mode == Z80_IMMED) { |
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755 cycles += 3; |
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756 } else if(z80_size(inst) == SZ_W) { |
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757 cycles += 4; |
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758 } |
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759 dst = zcycles(dst, cycles); |
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760 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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761 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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762 if (src_op.mode == MODE_REG_DIRECT) { |
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763 dst = xor_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
236
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764 } else { |
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765 dst = xor_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
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766 } |
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767 //TODO: Cleanup flags |
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768 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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769 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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770 //TODO: Implement half-carry flag |
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771 if (z80_size(inst) == SZ_B) { |
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772 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
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773 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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774 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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775 } |
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776 dst = z80_save_reg(dst, inst, opts); |
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777 dst = z80_save_ea(dst, inst, opts); |
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778 break; |
242 | 779 case Z80_CP: |
780 cycles = 4; | |
781 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { | |
782 cycles += 12; | |
783 } else if(inst->addr_mode == Z80_IMMED) { | |
784 cycles += 3; | |
785 } | |
786 dst = zcycles(dst, cycles); | |
787 dst = translate_z80_reg(inst, &dst_op, dst, opts); | |
788 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); | |
789 if (src_op.mode == MODE_REG_DIRECT) { | |
790 dst = cmp_rr(dst, src_op.base, dst_op.base, z80_size(inst)); | |
791 } else { | |
792 dst = cmp_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); | |
793 } | |
794 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); | |
795 dst = mov_irdisp8(dst, 1, CONTEXT, zf_off(ZF_N), SZ_B); | |
796 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); | |
797 //TODO: Implement half-carry flag | |
798 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); | |
799 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); | |
800 dst = z80_save_reg(dst, inst, opts); | |
801 dst = z80_save_ea(dst, inst, opts); | |
802 break; | |
213
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803 case Z80_INC: |
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804 cycles = 4; |
4d4559b04c59
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|
805 if (inst->reg == Z80_IX || inst->reg == Z80_IY) { |
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806 cycles += 6; |
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807 } else if(z80_size(inst) == SZ_W) { |
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808 cycles += 2; |
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809 } else if(inst->reg == Z80_IXH || inst->reg == Z80_IXL || inst->reg == Z80_IYH || inst->reg == Z80_IYL || inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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|
810 cycles += 4; |
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811 } |
373
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812 dst = zcycles(dst, cycles); |
213
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|
813 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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814 if (dst_op.mode == MODE_UNUSED) { |
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815 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
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|
816 } |
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|
817 dst = add_ir(dst, 1, dst_op.base, z80_size(inst)); |
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818 if (z80_size(inst) == SZ_B) { |
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819 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
213
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|
820 //TODO: Implement half-carry flag |
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821 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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822 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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823 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
213
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|
824 } |
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|
825 dst = z80_save_reg(dst, inst, opts); |
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|
826 dst = z80_save_ea(dst, inst, opts); |
387
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|
827 dst = z80_save_result(dst, inst); |
213
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|
828 break; |
236
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829 case Z80_DEC: |
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830 cycles = 4; |
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831 if (inst->reg == Z80_IX || inst->reg == Z80_IY) { |
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832 cycles += 6; |
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833 } else if(z80_size(inst) == SZ_W) { |
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834 cycles += 2; |
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835 } else if(inst->reg == Z80_IXH || inst->reg == Z80_IXL || inst->reg == Z80_IYH || inst->reg == Z80_IYL || inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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836 cycles += 4; |
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|
837 } |
373
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372
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|
838 dst = zcycles(dst, cycles); |
236
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839 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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840 if (dst_op.mode == MODE_UNUSED) { |
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841 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
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842 } |
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843 dst = sub_ir(dst, 1, dst_op.base, z80_size(inst)); |
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844 if (z80_size(inst) == SZ_B) { |
311
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diff
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845 dst = mov_irdisp8(dst, 1, CONTEXT, zf_off(ZF_N), SZ_B); |
236
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846 //TODO: Implement half-carry flag |
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847 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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848 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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849 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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850 } |
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851 dst = z80_save_reg(dst, inst, opts); |
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852 dst = z80_save_ea(dst, inst, opts); |
387
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|
853 dst = z80_save_result(dst, inst); |
213
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|
854 break; |
274
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855 //case Z80_DAA: |
213
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|
856 case Z80_CPL: |
274
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|
857 dst = zcycles(dst, 4); |
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858 dst = not_r(dst, opts->regs[Z80_A], SZ_B); |
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|
859 //TODO: Implement half-carry flag |
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860 dst = mov_irdisp8(dst, 1, CONTEXT, zf_off(ZF_N), SZ_B); |
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861 break; |
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|
862 case Z80_NEG: |
be2b845d3e94
Implement CPL and NEG (untested)
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parents:
273
diff
changeset
|
863 dst = zcycles(dst, 8); |
be2b845d3e94
Implement CPL and NEG (untested)
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273
diff
changeset
|
864 dst = neg_r(dst, opts->regs[Z80_A], SZ_B); |
be2b845d3e94
Implement CPL and NEG (untested)
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273
diff
changeset
|
865 //TODO: Implement half-carry flag |
be2b845d3e94
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Mike Pavone <pavone@retrodev.com>
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273
diff
changeset
|
866 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
be2b845d3e94
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Mike Pavone <pavone@retrodev.com>
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273
diff
changeset
|
867 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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Implement CPL and NEG (untested)
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273
diff
changeset
|
868 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
be2b845d3e94
Implement CPL and NEG (untested)
Mike Pavone <pavone@retrodev.com>
parents:
273
diff
changeset
|
869 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
be2b845d3e94
Implement CPL and NEG (untested)
Mike Pavone <pavone@retrodev.com>
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273
diff
changeset
|
870 dst = mov_irdisp8(dst, 1, CONTEXT, zf_off(ZF_N), SZ_B); |
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Mike Pavone <pavone@retrodev.com>
parents:
273
diff
changeset
|
871 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
872 case Z80_CCF: |
257 | 873 dst = zcycles(dst, 4); |
874 dst = xor_irdisp8(dst, 1, CONTEXT, zf_off(ZF_C), SZ_B); | |
875 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); | |
876 //TODO: Implement half-carry flag | |
877 break; | |
878 case Z80_SCF: | |
879 dst = zcycles(dst, 4); | |
880 dst = mov_irdisp8(dst, 1, CONTEXT, zf_off(ZF_C), SZ_B); | |
881 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); | |
882 //TODO: Implement half-carry flag | |
883 break; | |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
884 case Z80_NOP: |
4d4559b04c59
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
885 if (inst->immed == 42) { |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
886 dst = call(dst, (uint8_t *)z80_save_context); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
887 dst = mov_rr(dst, CONTEXT, RDI, SZ_Q); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
888 dst = jmp(dst, (uint8_t *)z80_print_regs_exit); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
889 } else { |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
890 dst = zcycles(dst, 4 * inst->immed); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
891 } |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
892 break; |
285
021aeb6df19b
Implement HALT (sort of tested)
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parents:
284
diff
changeset
|
893 case Z80_HALT: |
021aeb6df19b
Implement HALT (sort of tested)
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284
diff
changeset
|
894 dst = zcycles(dst, 4); |
021aeb6df19b
Implement HALT (sort of tested)
Mike Pavone <pavone@retrodev.com>
parents:
284
diff
changeset
|
895 dst = mov_ir(dst, address, SCRATCH1, SZ_W); |
021aeb6df19b
Implement HALT (sort of tested)
Mike Pavone <pavone@retrodev.com>
parents:
284
diff
changeset
|
896 uint8_t * call_inst = dst; |
021aeb6df19b
Implement HALT (sort of tested)
Mike Pavone <pavone@retrodev.com>
parents:
284
diff
changeset
|
897 dst = call(dst, (uint8_t *)z80_halt); |
021aeb6df19b
Implement HALT (sort of tested)
Mike Pavone <pavone@retrodev.com>
parents:
284
diff
changeset
|
898 dst = jmp(dst, call_inst); |
021aeb6df19b
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Mike Pavone <pavone@retrodev.com>
parents:
284
diff
changeset
|
899 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
900 case Z80_DI: |
243
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
901 dst = zcycles(dst, 4); |
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
902 dst = mov_irdisp8(dst, 0, CONTEXT, offsetof(z80_context, iff1), SZ_B); |
2f069a0b487e
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Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
903 dst = mov_irdisp8(dst, 0, CONTEXT, offsetof(z80_context, iff2), SZ_B); |
250
5f1b68cecfc7
Implemented basic interrupt support in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
248
diff
changeset
|
904 dst = mov_rdisp8r(dst, CONTEXT, offsetof(z80_context, sync_cycle), ZLIMIT, SZ_D); |
401 | 905 dst = mov_irdisp8(dst, 0xFFFFFFFF, CONTEXT, offsetof(z80_context, int_cycle), SZ_D); |
243
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
906 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
907 case Z80_EI: |
243
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
908 dst = zcycles(dst, 4); |
420
9fb111b5641f
Fix access to int_enable_cycle in EI
Mike Pavone <pavone@retrodev.com>
parents:
401
diff
changeset
|
909 dst = mov_rrdisp32(dst, ZCYCLES, CONTEXT, offsetof(z80_context, int_enable_cycle), SZ_D); |
243
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
910 dst = mov_irdisp8(dst, 1, CONTEXT, offsetof(z80_context, iff1), SZ_B); |
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
911 dst = mov_irdisp8(dst, 1, CONTEXT, offsetof(z80_context, iff2), SZ_B); |
335 | 912 //interrupt enable has a one-instruction latency, minimum instruction duration is 4 cycles |
420
9fb111b5641f
Fix access to int_enable_cycle in EI
Mike Pavone <pavone@retrodev.com>
parents:
401
diff
changeset
|
913 dst = add_irdisp32(dst, 4, CONTEXT, offsetof(z80_context, int_enable_cycle), SZ_D); |
250
5f1b68cecfc7
Implemented basic interrupt support in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
248
diff
changeset
|
914 dst = call(dst, (uint8_t *)z80_do_sync); |
243
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
915 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
916 case Z80_IM: |
243
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
917 dst = zcycles(dst, 4); |
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
918 dst = mov_irdisp8(dst, inst->immed, CONTEXT, offsetof(z80_context, im), SZ_B); |
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
919 break; |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
920 case Z80_RLC: |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
921 cycles = inst->immed == 0 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8); |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
922 dst = zcycles(dst, cycles); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
923 if (inst->addr_mode != Z80_UNUSED) { |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
924 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
925 dst = translate_z80_reg(inst, &src_op, dst, opts); //For IX/IY variants that also write to a register |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
926 dst = zcycles(dst, 1); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
927 } else { |
302
3b831fe32c15
More fixes for confusion between Z80_UNUSED and MODE_UNUSED
Mike Pavone <pavone@retrodev.com>
parents:
301
diff
changeset
|
928 src_op.mode = MODE_UNUSED; |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
929 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
930 } |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
931 dst = rol_ir(dst, 1, dst_op.base, SZ_B); |
301
6e15509a1257
Compare src_op.mode with the correct constant in shift/rotate instructions
Mike Pavone <pavone@retrodev.com>
parents:
300
diff
changeset
|
932 if (src_op.mode != MODE_UNUSED) { |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
933 dst = mov_rr(dst, dst_op.base, src_op.base, SZ_B); |
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
934 } |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
935 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
936 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
937 //TODO: Implement half-carry flag |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
938 dst = cmp_ir(dst, 0, dst_op.base, SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
939 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
940 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
941 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
942 if (inst->addr_mode != Z80_UNUSED) { |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
943 dst = z80_save_result(dst, inst); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
944 if (src_op.mode != MODE_UNUSED) { |
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
945 dst = z80_save_reg(dst, inst, opts); |
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
946 } |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
947 } else { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
948 dst = z80_save_reg(dst, inst, opts); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
949 } |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
950 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
951 case Z80_RL: |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
952 cycles = inst->immed == 0 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8); |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
953 dst = zcycles(dst, cycles); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
954 if (inst->addr_mode != Z80_UNUSED) { |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
955 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
956 dst = translate_z80_reg(inst, &src_op, dst, opts); //For IX/IY variants that also write to a register |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
957 dst = zcycles(dst, 1); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
958 } else { |
302
3b831fe32c15
More fixes for confusion between Z80_UNUSED and MODE_UNUSED
Mike Pavone <pavone@retrodev.com>
parents:
301
diff
changeset
|
959 src_op.mode = MODE_UNUSED; |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
960 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
961 } |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
962 dst = bt_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
963 dst = rcl_ir(dst, 1, dst_op.base, SZ_B); |
301
6e15509a1257
Compare src_op.mode with the correct constant in shift/rotate instructions
Mike Pavone <pavone@retrodev.com>
parents:
300
diff
changeset
|
964 if (src_op.mode != MODE_UNUSED) { |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
965 dst = mov_rr(dst, dst_op.base, src_op.base, SZ_B); |
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
966 } |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
967 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
968 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
969 //TODO: Implement half-carry flag |
682e505f5757
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246
diff
changeset
|
970 dst = cmp_ir(dst, 0, dst_op.base, SZ_B); |
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246
diff
changeset
|
971 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
682e505f5757
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parents:
246
diff
changeset
|
972 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
682e505f5757
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246
diff
changeset
|
973 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
974 if (inst->addr_mode != Z80_UNUSED) { |
247
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
975 dst = z80_save_result(dst, inst); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
976 if (src_op.mode != MODE_UNUSED) { |
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
977 dst = z80_save_reg(dst, inst, opts); |
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
978 } |
247
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Mike Pavone <pavone@retrodev.com>
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246
diff
changeset
|
979 } else { |
682e505f5757
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parents:
246
diff
changeset
|
980 dst = z80_save_reg(dst, inst, opts); |
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parents:
246
diff
changeset
|
981 } |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
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246
diff
changeset
|
982 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
983 case Z80_RRC: |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
984 cycles = inst->immed == 0 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8); |
247
682e505f5757
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Mike Pavone <pavone@retrodev.com>
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246
diff
changeset
|
985 dst = zcycles(dst, cycles); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
986 if (inst->addr_mode != Z80_UNUSED) { |
247
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
987 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
988 dst = translate_z80_reg(inst, &src_op, dst, opts); //For IX/IY variants that also write to a register |
247
682e505f5757
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Mike Pavone <pavone@retrodev.com>
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246
diff
changeset
|
989 dst = zcycles(dst, 1); |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
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246
diff
changeset
|
990 } else { |
302
3b831fe32c15
More fixes for confusion between Z80_UNUSED and MODE_UNUSED
Mike Pavone <pavone@retrodev.com>
parents:
301
diff
changeset
|
991 src_op.mode = MODE_UNUSED; |
247
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
992 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
993 } |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
994 dst = ror_ir(dst, 1, dst_op.base, SZ_B); |
301
6e15509a1257
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Mike Pavone <pavone@retrodev.com>
parents:
300
diff
changeset
|
995 if (src_op.mode != MODE_UNUSED) { |
299
42e1a986f2d0
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Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
996 dst = mov_rr(dst, dst_op.base, src_op.base, SZ_B); |
42e1a986f2d0
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Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
997 } |
247
682e505f5757
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Mike Pavone <pavone@retrodev.com>
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246
diff
changeset
|
998 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
682e505f5757
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246
diff
changeset
|
999 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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246
diff
changeset
|
1000 //TODO: Implement half-carry flag |
682e505f5757
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246
diff
changeset
|
1001 dst = cmp_ir(dst, 0, dst_op.base, SZ_B); |
682e505f5757
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parents:
246
diff
changeset
|
1002 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
682e505f5757
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246
diff
changeset
|
1003 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
682e505f5757
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parents:
246
diff
changeset
|
1004 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1005 if (inst->addr_mode != Z80_UNUSED) { |
247
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1006 dst = z80_save_result(dst, inst); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1007 if (src_op.mode != MODE_UNUSED) { |
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1008 dst = z80_save_reg(dst, inst, opts); |
42e1a986f2d0
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Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1009 } |
247
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246
diff
changeset
|
1010 } else { |
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parents:
246
diff
changeset
|
1011 dst = z80_save_reg(dst, inst, opts); |
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246
diff
changeset
|
1012 } |
682e505f5757
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246
diff
changeset
|
1013 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1014 case Z80_RR: |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1015 cycles = inst->immed == 0 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8); |
247
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parents:
246
diff
changeset
|
1016 dst = zcycles(dst, cycles); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1017 if (inst->addr_mode != Z80_UNUSED) { |
247
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parents:
246
diff
changeset
|
1018 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1019 dst = translate_z80_reg(inst, &src_op, dst, opts); //For IX/IY variants that also write to a register |
247
682e505f5757
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parents:
246
diff
changeset
|
1020 dst = zcycles(dst, 1); |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1021 } else { |
302
3b831fe32c15
More fixes for confusion between Z80_UNUSED and MODE_UNUSED
Mike Pavone <pavone@retrodev.com>
parents:
301
diff
changeset
|
1022 src_op.mode = MODE_UNUSED; |
247
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1023 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
682e505f5757
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parents:
246
diff
changeset
|
1024 } |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1025 dst = bt_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1026 dst = rcr_ir(dst, 1, dst_op.base, SZ_B); |
301
6e15509a1257
Compare src_op.mode with the correct constant in shift/rotate instructions
Mike Pavone <pavone@retrodev.com>
parents:
300
diff
changeset
|
1027 if (src_op.mode != MODE_UNUSED) { |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1028 dst = mov_rr(dst, dst_op.base, src_op.base, SZ_B); |
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1029 } |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1030 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1031 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1032 //TODO: Implement half-carry flag |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1033 dst = cmp_ir(dst, 0, dst_op.base, SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1034 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1035 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1036 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1037 if (inst->addr_mode != Z80_UNUSED) { |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1038 dst = z80_save_result(dst, inst); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1039 if (src_op.mode != MODE_UNUSED) { |
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1040 dst = z80_save_reg(dst, inst, opts); |
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1041 } |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1042 } else { |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1043 dst = z80_save_reg(dst, inst, opts); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1044 } |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1045 break; |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1046 case Z80_SLA: |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1047 case Z80_SLL: |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1048 cycles = inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8; |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1049 dst = zcycles(dst, cycles); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1050 if (inst->addr_mode != Z80_UNUSED) { |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1051 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1052 dst = translate_z80_reg(inst, &src_op, dst, opts); //For IX/IY variants that also write to a register |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1053 dst = zcycles(dst, 1); |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1054 } else { |
302
3b831fe32c15
More fixes for confusion between Z80_UNUSED and MODE_UNUSED
Mike Pavone <pavone@retrodev.com>
parents:
301
diff
changeset
|
1055 src_op.mode = MODE_UNUSED; |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1056 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1057 } |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1058 dst = shl_ir(dst, 1, dst_op.base, SZ_B); |
310
bf440db64086
Implement carry flag for shift instructions. Implement weird behavior for bit 0 of SLL. Fix missing break statement in SRL.
Mike Pavone <pavone@retrodev.com>
parents:
309
diff
changeset
|
1059 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
bf440db64086
Implement carry flag for shift instructions. Implement weird behavior for bit 0 of SLL. Fix missing break statement in SRL.
Mike Pavone <pavone@retrodev.com>
parents:
309
diff
changeset
|
1060 if (inst->op == Z80_SLL) { |
bf440db64086
Implement carry flag for shift instructions. Implement weird behavior for bit 0 of SLL. Fix missing break statement in SRL.
Mike Pavone <pavone@retrodev.com>
parents:
309
diff
changeset
|
1061 dst = or_ir(dst, 1, dst_op.base, SZ_B); |
bf440db64086
Implement carry flag for shift instructions. Implement weird behavior for bit 0 of SLL. Fix missing break statement in SRL.
Mike Pavone <pavone@retrodev.com>
parents:
309
diff
changeset
|
1062 } |
301
6e15509a1257
Compare src_op.mode with the correct constant in shift/rotate instructions
Mike Pavone <pavone@retrodev.com>
parents:
300
diff
changeset
|
1063 if (src_op.mode != MODE_UNUSED) { |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1064 dst = mov_rr(dst, dst_op.base, src_op.base, SZ_B); |
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1065 } |
275
1a7d0a964ad2
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1066 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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1067 //TODO: Implement half-carry flag |
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1068 dst = cmp_ir(dst, 0, dst_op.base, SZ_B); |
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1069 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
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1070 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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1071 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
299
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1072 if (inst->addr_mode != Z80_UNUSED) { |
275
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1073 dst = z80_save_result(dst, inst); |
299
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1074 if (src_op.mode != MODE_UNUSED) { |
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1075 dst = z80_save_reg(dst, inst, opts); |
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1076 } |
275
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1077 } else { |
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1078 dst = z80_save_reg(dst, inst, opts); |
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1079 } |
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1080 break; |
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1081 case Z80_SRA: |
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1082 cycles = inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8; |
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1083 dst = zcycles(dst, cycles); |
299
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1084 if (inst->addr_mode != Z80_UNUSED) { |
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1085 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
299
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1086 dst = translate_z80_reg(inst, &src_op, dst, opts); //For IX/IY variants that also write to a register |
275
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1087 dst = zcycles(dst, 1); |
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1088 } else { |
302
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301
diff
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1089 src_op.mode = MODE_UNUSED; |
275
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1090 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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1091 } |
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1092 dst = sar_ir(dst, 1, dst_op.base, SZ_B); |
301
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1093 if (src_op.mode != MODE_UNUSED) { |
299
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1094 dst = mov_rr(dst, dst_op.base, src_op.base, SZ_B); |
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1095 } |
310
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1096 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
275
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1097 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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1098 //TODO: Implement half-carry flag |
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1099 dst = cmp_ir(dst, 0, dst_op.base, SZ_B); |
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1100 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
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1101 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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1102 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
299
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1103 if (inst->addr_mode != Z80_UNUSED) { |
275
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1104 dst = z80_save_result(dst, inst); |
299
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1105 if (src_op.mode != MODE_UNUSED) { |
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1106 dst = z80_save_reg(dst, inst, opts); |
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1107 } |
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1108 } else { |
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1109 dst = z80_save_reg(dst, inst, opts); |
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1110 } |
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1111 break; |
213
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1112 case Z80_SRL: |
275
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1113 cycles = inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8; |
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1114 dst = zcycles(dst, cycles); |
299
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1115 if (inst->addr_mode != Z80_UNUSED) { |
275
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1116 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
299
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1117 dst = translate_z80_reg(inst, &src_op, dst, opts); //For IX/IY variants that also write to a register |
275
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1118 dst = zcycles(dst, 1); |
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1119 } else { |
302
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1120 src_op.mode = MODE_UNUSED; |
275
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1121 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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1122 } |
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1123 dst = shr_ir(dst, 1, dst_op.base, SZ_B); |
301
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1124 if (src_op.mode != MODE_UNUSED) { |
299
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1125 dst = mov_rr(dst, dst_op.base, src_op.base, SZ_B); |
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1126 } |
310
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1127 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
275
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1128 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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1129 //TODO: Implement half-carry flag |
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1130 dst = cmp_ir(dst, 0, dst_op.base, SZ_B); |
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1131 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
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1132 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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1133 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
299
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1134 if (inst->addr_mode != Z80_UNUSED) { |
275
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1135 dst = z80_save_result(dst, inst); |
299
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|
1136 if (src_op.mode != MODE_UNUSED) { |
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1137 dst = z80_save_reg(dst, inst, opts); |
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1138 } |
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1139 } else { |
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1140 dst = z80_save_reg(dst, inst, opts); |
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1141 } |
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1142 break; |
286 | 1143 case Z80_RLD: |
1144 dst = zcycles(dst, 8); | |
1145 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH1, SZ_W); | |
1146 dst = call(dst, (uint8_t *)z80_read_byte); | |
1147 //Before: (HL) = 0x12, A = 0x34 | |
1148 //After: (HL) = 0x24, A = 0x31 | |
1149 dst = mov_rr(dst, opts->regs[Z80_A], SCRATCH2, SZ_B); | |
1150 dst = shl_ir(dst, 4, SCRATCH1, SZ_W); | |
1151 dst = and_ir(dst, 0xF, SCRATCH2, SZ_W); | |
1152 dst = and_ir(dst, 0xFFF, SCRATCH1, SZ_W); | |
1153 dst = and_ir(dst, 0xF0, opts->regs[Z80_A], SZ_B); | |
1154 dst = or_rr(dst, SCRATCH2, SCRATCH1, SZ_W); | |
1155 //SCRATCH1 = 0x0124 | |
1156 dst = ror_ir(dst, 8, SCRATCH1, SZ_W); | |
1157 dst = zcycles(dst, 4); | |
1158 dst = or_rr(dst, SCRATCH1, opts->regs[Z80_A], SZ_B); | |
287
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1159 //set flags |
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1160 //TODO: Implement half-carry flag |
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1161 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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1162 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
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1163 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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1164 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
505
b7b7a1cab44a
The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
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1165 |
286 | 1166 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH2, SZ_W); |
1167 dst = ror_ir(dst, 8, SCRATCH1, SZ_W); | |
1168 dst = call(dst, (uint8_t *)z80_write_byte); | |
1169 break; | |
287
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1170 case Z80_RRD: |
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1171 dst = zcycles(dst, 8); |
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1172 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH1, SZ_W); |
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1173 dst = call(dst, (uint8_t *)z80_read_byte); |
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1174 //Before: (HL) = 0x12, A = 0x34 |
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1175 //After: (HL) = 0x41, A = 0x32 |
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1176 dst = movzx_rr(dst, opts->regs[Z80_A], SCRATCH2, SZ_B, SZ_W); |
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changeset
|
1177 dst = ror_ir(dst, 4, SCRATCH1, SZ_W); |
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Implement RRD and implement flags on RLD
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diff
changeset
|
1178 dst = shl_ir(dst, 4, SCRATCH2, SZ_W); |
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286
diff
changeset
|
1179 dst = and_ir(dst, 0xF00F, SCRATCH1, SZ_W); |
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286
diff
changeset
|
1180 dst = and_ir(dst, 0xF0, opts->regs[Z80_A], SZ_B); |
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Implement RRD and implement flags on RLD
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286
diff
changeset
|
1181 //SCRATCH1 = 0x2001 |
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286
diff
changeset
|
1182 //SCRATCH2 = 0x0040 |
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parents:
286
diff
changeset
|
1183 dst = or_rr(dst, SCRATCH2, SCRATCH1, SZ_W); |
fb840e0a48cd
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Mike Pavone <pavone@retrodev.com>
parents:
286
diff
changeset
|
1184 //SCRATCH1 = 0x2041 |
fb840e0a48cd
Implement RRD and implement flags on RLD
Mike Pavone <pavone@retrodev.com>
parents:
286
diff
changeset
|
1185 dst = ror_ir(dst, 8, SCRATCH1, SZ_W); |
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parents:
286
diff
changeset
|
1186 dst = zcycles(dst, 4); |
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Mike Pavone <pavone@retrodev.com>
parents:
286
diff
changeset
|
1187 dst = shr_ir(dst, 4, SCRATCH1, SZ_B); |
fb840e0a48cd
Implement RRD and implement flags on RLD
Mike Pavone <pavone@retrodev.com>
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286
diff
changeset
|
1188 dst = or_rr(dst, SCRATCH1, opts->regs[Z80_A], SZ_B); |
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286
diff
changeset
|
1189 //set flags |
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parents:
286
diff
changeset
|
1190 //TODO: Implement half-carry flag |
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parents:
286
diff
changeset
|
1191 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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Mike Pavone <pavone@retrodev.com>
parents:
286
diff
changeset
|
1192 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
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Mike Pavone <pavone@retrodev.com>
parents:
286
diff
changeset
|
1193 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
fb840e0a48cd
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Mike Pavone <pavone@retrodev.com>
parents:
286
diff
changeset
|
1194 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
505
b7b7a1cab44a
The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1195 |
287
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286
diff
changeset
|
1196 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH2, SZ_W); |
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286
diff
changeset
|
1197 dst = ror_ir(dst, 8, SCRATCH1, SZ_W); |
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parents:
286
diff
changeset
|
1198 dst = call(dst, (uint8_t *)z80_write_byte); |
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parents:
286
diff
changeset
|
1199 break; |
308
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1200 case Z80_BIT: { |
239
a5bea9711a46
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diff
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|
1201 cycles = (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) ? 8 : 16; |
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238
diff
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|
1202 dst = zcycles(dst, cycles); |
308
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parents:
307
diff
changeset
|
1203 uint8_t bit; |
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parents:
307
diff
changeset
|
1204 if ((inst->addr_mode & 0x1F) == Z80_REG && opts->regs[inst->ea_reg] >= AH && opts->regs[inst->ea_reg] <= BH) { |
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parents:
307
diff
changeset
|
1205 src_op.base = opts->regs[z80_word_reg(inst->ea_reg)]; |
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parents:
307
diff
changeset
|
1206 size = SZ_W; |
e0e81551fd7e
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1207 bit = inst->immed + 8; |
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1208 } else { |
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1209 size = SZ_B; |
e0e81551fd7e
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1210 bit = inst->immed; |
e0e81551fd7e
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1211 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
e0e81551fd7e
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1212 } |
239
a5bea9711a46
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Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
1213 if (inst->addr_mode != Z80_REG) { |
a5bea9711a46
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Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
1214 //Reads normally take 3 cycles, but the read at the end of a bit instruction takes 4 |
a5bea9711a46
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Mike Pavone <pavone@retrodev.com>
parents:
238
diff
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|
1215 dst = zcycles(dst, 1); |
a5bea9711a46
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Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
1216 } |
308
e0e81551fd7e
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1217 dst = bt_ir(dst, bit, src_op.base, size); |
303
8290d3086ff0
BIT was setting the zero flag to the opposite of what it should have. This is now fixed.
Mike Pavone <pavone@retrodev.com>
parents:
302
diff
changeset
|
1218 dst = setcc_rdisp8(dst, CC_NC, CONTEXT, zf_off(ZF_Z)); |
307
b6393b89a7e4
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Mike Pavone <pavone@retrodev.com>
parents:
306
diff
changeset
|
1219 dst = setcc_rdisp8(dst, CC_NC, CONTEXT, zf_off(ZF_PV)); |
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parents:
306
diff
changeset
|
1220 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
b6393b89a7e4
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parents:
306
diff
changeset
|
1221 if (inst->immed == 7) { |
308
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1222 dst = cmp_ir(dst, 0, src_op.base, size); |
307
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Complete flag behavior for Z80 BIT instruction
Mike Pavone <pavone@retrodev.com>
parents:
306
diff
changeset
|
1223 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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Mike Pavone <pavone@retrodev.com>
parents:
306
diff
changeset
|
1224 } else { |
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parents:
306
diff
changeset
|
1225 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_S), SZ_B); |
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Complete flag behavior for Z80 BIT instruction
Mike Pavone <pavone@retrodev.com>
parents:
306
diff
changeset
|
1226 } |
239
a5bea9711a46
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Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
1227 break; |
308
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1228 } |
e0e81551fd7e
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1229 case Z80_SET: { |
247
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1230 cycles = (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) ? 8 : 16; |
682e505f5757
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parents:
246
diff
changeset
|
1231 dst = zcycles(dst, cycles); |
308
e0e81551fd7e
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1232 uint8_t bit; |
e0e81551fd7e
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1233 if ((inst->addr_mode & 0x1F) == Z80_REG && opts->regs[inst->ea_reg] >= AH && opts->regs[inst->ea_reg] <= BH) { |
e0e81551fd7e
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1234 src_op.base = opts->regs[z80_word_reg(inst->ea_reg)]; |
e0e81551fd7e
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parents:
307
diff
changeset
|
1235 size = SZ_W; |
e0e81551fd7e
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1236 bit = inst->immed + 8; |
e0e81551fd7e
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1237 } else { |
e0e81551fd7e
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1238 size = SZ_B; |
e0e81551fd7e
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1239 bit = inst->immed; |
384
5500d1d1269e
Fix set/res when the operand is in memory
Mike Pavone <pavone@retrodev.com>
parents:
373
diff
changeset
|
1240 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, MODIFY); |
308
e0e81551fd7e
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1241 } |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1242 if (inst->reg != Z80_USE_IMMED) { |
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1243 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1244 } |
247
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1245 if (inst->addr_mode != Z80_REG) { |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1246 //Reads normally take 3 cycles, but the read in the middle of a set instruction takes 4 |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1247 dst = zcycles(dst, 1); |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1248 } |
308
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1249 dst = bts_ir(dst, bit, src_op.base, size); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1250 if (inst->reg != Z80_USE_IMMED) { |
308
e0e81551fd7e
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parents:
307
diff
changeset
|
1251 if (size == SZ_W) { |
e0e81551fd7e
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parents:
307
diff
changeset
|
1252 if (dst_op.base >= R8) { |
e0e81551fd7e
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parents:
307
diff
changeset
|
1253 dst = ror_ir(dst, 8, src_op.base, SZ_W); |
e0e81551fd7e
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parents:
307
diff
changeset
|
1254 dst = mov_rr(dst, opts->regs[z80_low_reg(inst->ea_reg)], dst_op.base, SZ_B); |
e0e81551fd7e
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parents:
307
diff
changeset
|
1255 dst = ror_ir(dst, 8, src_op.base, SZ_W); |
e0e81551fd7e
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parents:
307
diff
changeset
|
1256 } else { |
e0e81551fd7e
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parents:
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diff
changeset
|
1257 dst = mov_rr(dst, opts->regs[inst->ea_reg], dst_op.base, SZ_B); |
505
b7b7a1cab44a
The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1258 } |
308
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parents:
307
diff
changeset
|
1259 } else { |
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parents:
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diff
changeset
|
1260 dst = mov_rr(dst, src_op.base, dst_op.base, SZ_B); |
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parents:
307
diff
changeset
|
1261 } |
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parents:
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diff
changeset
|
1262 } |
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parents:
307
diff
changeset
|
1263 if ((inst->addr_mode & 0x1F) != Z80_REG) { |
e0e81551fd7e
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parents:
307
diff
changeset
|
1264 dst = z80_save_result(dst, inst); |
e0e81551fd7e
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parents:
307
diff
changeset
|
1265 if (inst->reg != Z80_USE_IMMED) { |
e0e81551fd7e
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parents:
307
diff
changeset
|
1266 dst = z80_save_reg(dst, inst, opts); |
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parents:
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diff
changeset
|
1267 } |
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parents:
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diff
changeset
|
1268 } |
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parents:
307
diff
changeset
|
1269 break; |
e0e81551fd7e
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1270 } |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
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parents:
307
diff
changeset
|
1271 case Z80_RES: { |
e0e81551fd7e
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parents:
307
diff
changeset
|
1272 cycles = (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) ? 8 : 16; |
e0e81551fd7e
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parents:
307
diff
changeset
|
1273 dst = zcycles(dst, cycles); |
e0e81551fd7e
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1274 uint8_t bit; |
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307
diff
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|
1275 if ((inst->addr_mode & 0x1F) == Z80_REG && opts->regs[inst->ea_reg] >= AH && opts->regs[inst->ea_reg] <= BH) { |
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parents:
307
diff
changeset
|
1276 src_op.base = opts->regs[z80_word_reg(inst->ea_reg)]; |
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1277 size = SZ_W; |
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1278 bit = inst->immed + 8; |
e0e81551fd7e
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1279 } else { |
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1280 size = SZ_B; |
e0e81551fd7e
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1281 bit = inst->immed; |
384
5500d1d1269e
Fix set/res when the operand is in memory
Mike Pavone <pavone@retrodev.com>
parents:
373
diff
changeset
|
1282 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, MODIFY); |
308
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1283 } |
e0e81551fd7e
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
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|
1284 if (inst->reg != Z80_USE_IMMED) { |
e0e81551fd7e
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1285 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1286 } |
e0e81551fd7e
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1287 if (inst->addr_mode != Z80_REG) { |
e0e81551fd7e
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1288 //Reads normally take 3 cycles, but the read in the middle of a set instruction takes 4 |
e0e81551fd7e
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1289 dst = zcycles(dst, 1); |
e0e81551fd7e
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1290 } |
e0e81551fd7e
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1291 dst = btr_ir(dst, bit, src_op.base, size); |
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1292 if (inst->reg != Z80_USE_IMMED) { |
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1293 if (size == SZ_W) { |
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parents:
307
diff
changeset
|
1294 if (dst_op.base >= R8) { |
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1295 dst = ror_ir(dst, 8, src_op.base, SZ_W); |
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307
diff
changeset
|
1296 dst = mov_rr(dst, opts->regs[z80_low_reg(inst->ea_reg)], dst_op.base, SZ_B); |
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Mike Pavone <pavone@retrodev.com>
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307
diff
changeset
|
1297 dst = ror_ir(dst, 8, src_op.base, SZ_W); |
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1298 } else { |
e0e81551fd7e
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1299 dst = mov_rr(dst, opts->regs[inst->ea_reg], dst_op.base, SZ_B); |
505
b7b7a1cab44a
The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1300 } |
308
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parents:
307
diff
changeset
|
1301 } else { |
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parents:
307
diff
changeset
|
1302 dst = mov_rr(dst, src_op.base, dst_op.base, SZ_B); |
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parents:
307
diff
changeset
|
1303 } |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1304 } |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1305 if (inst->addr_mode != Z80_REG) { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
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parents:
246
diff
changeset
|
1306 dst = z80_save_result(dst, inst); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1307 if (inst->reg != Z80_USE_IMMED) { |
42e1a986f2d0
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Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1308 dst = z80_save_reg(dst, inst, opts); |
42e1a986f2d0
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Mike Pavone <pavone@retrodev.com>
parents:
295
diff
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|
1309 } |
247
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1310 } |
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1311 break; |
308
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diff
changeset
|
1312 } |
236
19fb3523a9e5
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235
diff
changeset
|
1313 case Z80_JP: { |
19fb3523a9e5
Implement more Z80 instructions (untested)
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parents:
235
diff
changeset
|
1314 cycles = 4; |
239
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
1315 if (inst->addr_mode != Z80_REG) { |
236
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parents:
235
diff
changeset
|
1316 cycles += 6; |
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235
diff
changeset
|
1317 } else if(inst->ea_reg == Z80_IX || inst->ea_reg == Z80_IY) { |
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235
diff
changeset
|
1318 cycles += 4; |
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diff
changeset
|
1319 } |
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235
diff
changeset
|
1320 dst = zcycles(dst, cycles); |
239
a5bea9711a46
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Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
1321 if (inst->addr_mode != Z80_REG_INDIRECT && inst->immed < 0x4000) { |
236
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1322 uint8_t * call_dst = z80_get_native_address(context, inst->immed); |
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235
diff
changeset
|
1323 if (!call_dst) { |
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Mike Pavone <pavone@retrodev.com>
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235
diff
changeset
|
1324 opts->deferred = defer_address(opts->deferred, inst->immed, dst + 1); |
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Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1325 //fake address to force large displacement |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1326 call_dst = dst + 256; |
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1327 } |
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Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1328 dst = jmp(dst, call_dst); |
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1329 } else { |
239
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
1330 if (inst->addr_mode == Z80_REG_INDIRECT) { |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1331 dst = mov_rr(dst, opts->regs[inst->ea_reg], SCRATCH1, SZ_W); |
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1332 } else { |
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1333 dst = mov_ir(dst, inst->immed, SCRATCH1, SZ_W); |
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1334 } |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1335 dst = call(dst, (uint8_t *)z80_native_addr); |
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Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1336 dst = jmp_r(dst, SCRATCH1); |
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1337 } |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1338 break; |
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1339 } |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1340 case Z80_JPCC: { |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1341 dst = zcycles(dst, 7);//T States: 4,3 |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1342 uint8_t cond = CC_Z; |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1343 switch (inst->reg) |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1344 { |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1345 case Z80_CC_NZ: |
19fb3523a9e5
Implement more Z80 instructions (untested)
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parents:
235
diff
changeset
|
1346 cond = CC_NZ; |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1347 case Z80_CC_Z: |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1348 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_Z), SZ_B); |
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Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1349 break; |
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Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1350 case Z80_CC_NC: |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1351 cond = CC_NZ; |
19fb3523a9e5
Implement more Z80 instructions (untested)
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parents:
235
diff
changeset
|
1352 case Z80_CC_C: |
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Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1353 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1354 break; |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1355 case Z80_CC_PO: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1356 cond = CC_NZ; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1357 case Z80_CC_PE: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1358 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_PV), SZ_B); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1359 break; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1360 case Z80_CC_P: |
367
f20562f2a570
Fix P condition in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
366
diff
changeset
|
1361 cond = CC_NZ; |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1362 case Z80_CC_M: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1363 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_S), SZ_B); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1364 break; |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1365 } |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1366 uint8_t *no_jump_off = dst+1; |
19fb3523a9e5
Implement more Z80 instructions (untested)
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parents:
235
diff
changeset
|
1367 dst = jcc(dst, cond, dst+2); |
19fb3523a9e5
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parents:
235
diff
changeset
|
1368 dst = zcycles(dst, 5);//T States: 5 |
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1369 uint16_t dest_addr = inst->immed; |
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parents:
235
diff
changeset
|
1370 if (dest_addr < 0x4000) { |
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parents:
235
diff
changeset
|
1371 uint8_t * call_dst = z80_get_native_address(context, dest_addr); |
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parents:
235
diff
changeset
|
1372 if (!call_dst) { |
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parents:
235
diff
changeset
|
1373 opts->deferred = defer_address(opts->deferred, dest_addr, dst + 1); |
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parents:
235
diff
changeset
|
1374 //fake address to force large displacement |
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1375 call_dst = dst + 256; |
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1376 } |
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parents:
235
diff
changeset
|
1377 dst = jmp(dst, call_dst); |
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1378 } else { |
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1379 dst = mov_ir(dst, dest_addr, SCRATCH1, SZ_W); |
19fb3523a9e5
Implement more Z80 instructions (untested)
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|
1380 dst = call(dst, (uint8_t *)z80_native_addr); |
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1381 dst = jmp_r(dst, SCRATCH1); |
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|
1382 } |
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|
1383 *no_jump_off = dst - (no_jump_off+1); |
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diff
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|
1384 break; |
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diff
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|
1385 } |
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|
1386 case Z80_JR: { |
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|
1387 dst = zcycles(dst, 12);//T States: 4,3,5 |
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235
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|
1388 uint16_t dest_addr = address + inst->immed + 2; |
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|
1389 if (dest_addr < 0x4000) { |
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diff
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|
1390 uint8_t * call_dst = z80_get_native_address(context, dest_addr); |
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diff
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|
1391 if (!call_dst) { |
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235
diff
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|
1392 opts->deferred = defer_address(opts->deferred, dest_addr, dst + 1); |
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235
diff
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|
1393 //fake address to force large displacement |
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Implement more Z80 instructions (untested)
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235
diff
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|
1394 call_dst = dst + 256; |
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|
1395 } |
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diff
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|
1396 dst = jmp(dst, call_dst); |
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|
1397 } else { |
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|
1398 dst = mov_ir(dst, dest_addr, SCRATCH1, SZ_W); |
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Implement more Z80 instructions (untested)
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|
1399 dst = call(dst, (uint8_t *)z80_native_addr); |
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235
diff
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|
1400 dst = jmp_r(dst, SCRATCH1); |
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diff
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|
1401 } |
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diff
changeset
|
1402 break; |
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235
diff
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|
1403 } |
235
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Get Z80 core working for simple programs
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|
1404 case Z80_JRCC: { |
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1405 dst = zcycles(dst, 7);//T States: 4,3 |
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diff
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|
1406 uint8_t cond = CC_Z; |
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diff
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|
1407 switch (inst->reg) |
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diff
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|
1408 { |
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|
1409 case Z80_CC_NZ: |
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1410 cond = CC_NZ; |
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|
1411 case Z80_CC_Z: |
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1412 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_Z), SZ_B); |
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|
1413 break; |
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diff
changeset
|
1414 case Z80_CC_NC: |
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diff
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|
1415 cond = CC_NZ; |
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diff
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|
1416 case Z80_CC_C: |
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diff
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|
1417 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1418 break; |
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213
diff
changeset
|
1419 } |
d9bf8e61c33c
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213
diff
changeset
|
1420 uint8_t *no_jump_off = dst+1; |
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213
diff
changeset
|
1421 dst = jcc(dst, cond, dst+2); |
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213
diff
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|
1422 dst = zcycles(dst, 5);//T States: 5 |
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Get Z80 core working for simple programs
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213
diff
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|
1423 uint16_t dest_addr = address + inst->immed + 2; |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1424 if (dest_addr < 0x4000) { |
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Get Z80 core working for simple programs
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213
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changeset
|
1425 uint8_t * call_dst = z80_get_native_address(context, dest_addr); |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1426 if (!call_dst) { |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1427 opts->deferred = defer_address(opts->deferred, dest_addr, dst + 1); |
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Get Z80 core working for simple programs
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213
diff
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|
1428 //fake address to force large displacement |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1429 call_dst = dst + 256; |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1430 } |
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diff
changeset
|
1431 dst = jmp(dst, call_dst); |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1432 } else { |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1433 dst = mov_ir(dst, dest_addr, SCRATCH1, SZ_W); |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1434 dst = call(dst, (uint8_t *)z80_native_addr); |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1435 dst = jmp_r(dst, SCRATCH1); |
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Get Z80 core working for simple programs
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213
diff
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|
1436 } |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1437 *no_jump_off = dst - (no_jump_off+1); |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1438 break; |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1439 } |
239
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
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238
diff
changeset
|
1440 case Z80_DJNZ: |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
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238
diff
changeset
|
1441 dst = zcycles(dst, 8);//T States: 5,3 |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
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238
diff
changeset
|
1442 dst = sub_ir(dst, 1, opts->regs[Z80_B], SZ_B); |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
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238
diff
changeset
|
1443 uint8_t *no_jump_off = dst+1; |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
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238
diff
changeset
|
1444 dst = jcc(dst, CC_Z, dst+2); |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
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238
diff
changeset
|
1445 dst = zcycles(dst, 5);//T States: 5 |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
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238
diff
changeset
|
1446 uint16_t dest_addr = address + inst->immed + 2; |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
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238
diff
changeset
|
1447 if (dest_addr < 0x4000) { |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
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238
diff
changeset
|
1448 uint8_t * call_dst = z80_get_native_address(context, dest_addr); |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
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238
diff
changeset
|
1449 if (!call_dst) { |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
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238
diff
changeset
|
1450 opts->deferred = defer_address(opts->deferred, dest_addr, dst + 1); |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
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238
diff
changeset
|
1451 //fake address to force large displacement |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
1452 call_dst = dst + 256; |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
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238
diff
changeset
|
1453 } |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
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238
diff
changeset
|
1454 dst = jmp(dst, call_dst); |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
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238
diff
changeset
|
1455 } else { |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
1456 dst = mov_ir(dst, dest_addr, SCRATCH1, SZ_W); |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
1457 dst = call(dst, (uint8_t *)z80_native_addr); |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
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238
diff
changeset
|
1458 dst = jmp_r(dst, SCRATCH1); |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
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238
diff
changeset
|
1459 } |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
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238
diff
changeset
|
1460 *no_jump_off = dst - (no_jump_off+1); |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
1461 break; |
235
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Get Z80 core working for simple programs
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213
diff
changeset
|
1462 case Z80_CALL: { |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1463 dst = zcycles(dst, 11);//T States: 4,3,4 |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1464 dst = sub_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
253
3b34deba4ca0
Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents:
252
diff
changeset
|
1465 dst = mov_ir(dst, address + 3, SCRATCH1, SZ_W); |
3b34deba4ca0
Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
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252
diff
changeset
|
1466 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W); |
235
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Get Z80 core working for simple programs
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diff
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|
1467 dst = call(dst, (uint8_t *)z80_write_word_highfirst);//T States: 3, 3 |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1468 if (inst->immed < 0x4000) { |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1469 uint8_t * call_dst = z80_get_native_address(context, inst->immed); |
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213
diff
changeset
|
1470 if (!call_dst) { |
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213
diff
changeset
|
1471 opts->deferred = defer_address(opts->deferred, inst->immed, dst + 1); |
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213
diff
changeset
|
1472 //fake address to force large displacement |
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Get Z80 core working for simple programs
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diff
changeset
|
1473 call_dst = dst + 256; |
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213
diff
changeset
|
1474 } |
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diff
changeset
|
1475 dst = jmp(dst, call_dst); |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1476 } else { |
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diff
changeset
|
1477 dst = mov_ir(dst, inst->immed, SCRATCH1, SZ_W); |
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Get Z80 core working for simple programs
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changeset
|
1478 dst = call(dst, (uint8_t *)z80_native_addr); |
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changeset
|
1479 dst = jmp_r(dst, SCRATCH1); |
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213
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changeset
|
1480 } |
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diff
changeset
|
1481 break; |
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213
diff
changeset
|
1482 } |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
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236
diff
changeset
|
1483 case Z80_CALLCC: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
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236
diff
changeset
|
1484 dst = zcycles(dst, 10);//T States: 4,3,3 (false case) |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
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236
diff
changeset
|
1485 uint8_t cond = CC_Z; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
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236
diff
changeset
|
1486 switch (inst->reg) |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
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236
diff
changeset
|
1487 { |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
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236
diff
changeset
|
1488 case Z80_CC_NZ: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
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236
diff
changeset
|
1489 cond = CC_NZ; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
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236
diff
changeset
|
1490 case Z80_CC_Z: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
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236
diff
changeset
|
1491 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_Z), SZ_B); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1492 break; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1493 case Z80_CC_NC: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1494 cond = CC_NZ; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1495 case Z80_CC_C: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1496 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1497 break; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1498 case Z80_CC_PO: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1499 cond = CC_NZ; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1500 case Z80_CC_PE: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1501 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_PV), SZ_B); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1502 break; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1503 case Z80_CC_P: |
367
f20562f2a570
Fix P condition in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
366
diff
changeset
|
1504 cond = CC_NZ; |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1505 case Z80_CC_M: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1506 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_S), SZ_B); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1507 break; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1508 } |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1509 uint8_t *no_call_off = dst+1; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1510 dst = jcc(dst, cond, dst+2); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1511 dst = zcycles(dst, 1);//Last of the above T states takes an extra cycle in the true case |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1512 dst = sub_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
253
3b34deba4ca0
Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents:
252
diff
changeset
|
1513 dst = mov_ir(dst, address + 3, SCRATCH1, SZ_W); |
3b34deba4ca0
Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents:
252
diff
changeset
|
1514 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W); |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1515 dst = call(dst, (uint8_t *)z80_write_word_highfirst);//T States: 3, 3 |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1516 if (inst->immed < 0x4000) { |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1517 uint8_t * call_dst = z80_get_native_address(context, inst->immed); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1518 if (!call_dst) { |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1519 opts->deferred = defer_address(opts->deferred, inst->immed, dst + 1); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1520 //fake address to force large displacement |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1521 call_dst = dst + 256; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1522 } |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1523 dst = jmp(dst, call_dst); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1524 } else { |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1525 dst = mov_ir(dst, inst->immed, SCRATCH1, SZ_W); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1526 dst = call(dst, (uint8_t *)z80_native_addr); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1527 dst = jmp_r(dst, SCRATCH1); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1528 } |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1529 *no_call_off = dst - (no_call_off+1); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1530 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1531 case Z80_RET: |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1532 dst = zcycles(dst, 4);//T States: 4 |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1533 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1534 dst = call(dst, (uint8_t *)z80_read_word);//T STates: 3, 3 |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1535 dst = add_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1536 dst = call(dst, (uint8_t *)z80_native_addr); |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1537 dst = jmp_r(dst, SCRATCH1); |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1538 break; |
246
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1539 case Z80_RETCC: { |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1540 dst = zcycles(dst, 5);//T States: 5 |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1541 uint8_t cond = CC_Z; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1542 switch (inst->reg) |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1543 { |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1544 case Z80_CC_NZ: |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1545 cond = CC_NZ; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1546 case Z80_CC_Z: |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1547 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_Z), SZ_B); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1548 break; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1549 case Z80_CC_NC: |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1550 cond = CC_NZ; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1551 case Z80_CC_C: |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1552 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1553 break; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1554 case Z80_CC_PO: |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1555 cond = CC_NZ; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1556 case Z80_CC_PE: |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1557 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_PV), SZ_B); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1558 break; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1559 case Z80_CC_P: |
367
f20562f2a570
Fix P condition in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
366
diff
changeset
|
1560 cond = CC_NZ; |
246
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1561 case Z80_CC_M: |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1562 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_S), SZ_B); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1563 break; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1564 } |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1565 uint8_t *no_call_off = dst+1; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1566 dst = jcc(dst, cond, dst+2); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1567 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1568 dst = call(dst, (uint8_t *)z80_read_word);//T STates: 3, 3 |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1569 dst = add_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1570 dst = call(dst, (uint8_t *)z80_native_addr); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1571 dst = jmp_r(dst, SCRATCH1); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1572 *no_call_off = dst - (no_call_off+1); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1573 break; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1574 } |
283
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1575 case Z80_RETI: |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1576 //For some systems, this may need a callback for signalling interrupt routine completion |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1577 dst = zcycles(dst, 8);//T States: 4, 4 |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1578 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1579 dst = call(dst, (uint8_t *)z80_read_word);//T STates: 3, 3 |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1580 dst = add_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1581 dst = call(dst, (uint8_t *)z80_native_addr); |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1582 dst = jmp_r(dst, SCRATCH1); |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1583 break; |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1584 case Z80_RETN: |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1585 dst = zcycles(dst, 8);//T States: 4, 4 |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1586 dst = mov_rdisp8r(dst, CONTEXT, offsetof(z80_context, iff2), SCRATCH2, SZ_B); |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1587 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1588 dst = mov_rrdisp8(dst, SCRATCH2, CONTEXT, offsetof(z80_context, iff1), SZ_B); |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1589 dst = call(dst, (uint8_t *)z80_read_word);//T STates: 3, 3 |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1590 dst = add_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1591 dst = call(dst, (uint8_t *)z80_native_addr); |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1592 dst = jmp_r(dst, SCRATCH1); |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1593 break; |
241
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1594 case Z80_RST: { |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1595 //RST is basically CALL to an address in page 0 |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1596 dst = zcycles(dst, 5);//T States: 5 |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1597 dst = sub_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
315
684e71e9f0d0
Fix return address for RST
Mike Pavone <pavone@retrodev.com>
parents:
314
diff
changeset
|
1598 dst = mov_ir(dst, address + 1, SCRATCH1, SZ_W); |
253
3b34deba4ca0
Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents:
252
diff
changeset
|
1599 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W); |
241
2586d49ddd46
Implement EX, EXX and RST in Z80 core
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parents:
239
diff
changeset
|
1600 dst = call(dst, (uint8_t *)z80_write_word_highfirst);//T States: 3, 3 |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
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239
diff
changeset
|
1601 uint8_t * call_dst = z80_get_native_address(context, inst->immed); |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
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239
diff
changeset
|
1602 if (!call_dst) { |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
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parents:
239
diff
changeset
|
1603 opts->deferred = defer_address(opts->deferred, inst->immed, dst + 1); |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
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parents:
239
diff
changeset
|
1604 //fake address to force large displacement |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
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parents:
239
diff
changeset
|
1605 call_dst = dst + 256; |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1606 } |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1607 dst = jmp(dst, call_dst); |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1608 break; |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1609 } |
284
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
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283
diff
changeset
|
1610 case Z80_IN: |
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Implement IN and OUT (untested)
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283
diff
changeset
|
1611 dst = zcycles(dst, inst->reg == Z80_A ? 7 : 8);//T States: 4 3/4 |
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Implement IN and OUT (untested)
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parents:
283
diff
changeset
|
1612 if (inst->addr_mode == Z80_IMMED_INDIRECT) { |
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283
diff
changeset
|
1613 dst = mov_ir(dst, inst->immed, SCRATCH1, SZ_B); |
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Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1614 } else { |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
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283
diff
changeset
|
1615 dst = mov_rr(dst, opts->regs[Z80_C], SCRATCH1, SZ_B); |
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Implement IN and OUT (untested)
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283
diff
changeset
|
1616 } |
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Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
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283
diff
changeset
|
1617 dst = call(dst, (uint8_t *)z80_io_read); |
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Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1618 translate_z80_reg(inst, &dst_op, dst, opts); |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
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283
diff
changeset
|
1619 dst = mov_rr(dst, SCRATCH1, dst_op.base, SZ_B); |
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Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1620 dst = z80_save_reg(dst, inst, opts); |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
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283
diff
changeset
|
1621 break; |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
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283
diff
changeset
|
1622 /*case Z80_INI: |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1623 case Z80_INIR: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1624 case Z80_IND: |
284
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
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283
diff
changeset
|
1625 case Z80_INDR:*/ |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1626 case Z80_OUT: |
284
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
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|
1627 dst = zcycles(dst, inst->reg == Z80_A ? 7 : 8);//T States: 4 3/4 |
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Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1628 if ((inst->addr_mode & 0x1F) == Z80_IMMED_INDIRECT) { |
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Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
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283
diff
changeset
|
1629 dst = mov_ir(dst, inst->immed, SCRATCH2, SZ_B); |
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Mike Pavone <pavone@retrodev.com>
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283
diff
changeset
|
1630 } else { |
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Mike Pavone <pavone@retrodev.com>
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283
diff
changeset
|
1631 dst = mov_rr(dst, opts->regs[Z80_C], SCRATCH2, SZ_B); |
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Mike Pavone <pavone@retrodev.com>
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283
diff
changeset
|
1632 } |
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Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
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283
diff
changeset
|
1633 translate_z80_reg(inst, &src_op, dst, opts); |
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Mike Pavone <pavone@retrodev.com>
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283
diff
changeset
|
1634 dst = mov_rr(dst, dst_op.base, SCRATCH1, SZ_B); |
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Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1635 dst = call(dst, (uint8_t *)z80_io_write); |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1636 dst = z80_save_reg(dst, inst, opts); |
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Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1637 break; |
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283
diff
changeset
|
1638 /*case Z80_OUTI: |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1639 case Z80_OTIR: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1640 case Z80_OUTD: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1641 case Z80_OTDR:*/ |
235
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Get Z80 core working for simple programs
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213
diff
changeset
|
1642 default: { |
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213
diff
changeset
|
1643 char disbuf[80]; |
314
54c0e5f22198
Show absolute addresses for JR, JRCC and DJNZ in Z80 disassembler
Mike Pavone <pavone@retrodev.com>
parents:
313
diff
changeset
|
1644 z80_disasm(inst, disbuf, address); |
424
7e8e179116af
Add support for loading GST format savestates
Mike Pavone <pavone@retrodev.com>
parents:
420
diff
changeset
|
1645 fprintf(stderr, "unimplemented instruction: %s at %X\n", disbuf, address); |
259
d9417261366f
Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called.
Mike Pavone <pavone@retrodev.com>
parents:
257
diff
changeset
|
1646 FILE * f = fopen("zram.bin", "wb"); |
d9417261366f
Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called.
Mike Pavone <pavone@retrodev.com>
parents:
257
diff
changeset
|
1647 fwrite(context->mem_pointers[0], 1, 8 * 1024, f); |
d9417261366f
Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called.
Mike Pavone <pavone@retrodev.com>
parents:
257
diff
changeset
|
1648 fclose(f); |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1649 exit(1); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1650 } |
235
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1651 } |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1652 return dst; |
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1653 } |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1654 |
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1655 uint8_t * z80_get_native_address(z80_context * context, uint32_t address) |
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1656 { |
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1657 native_map_slot *map; |
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1658 if (address < 0x4000) { |
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1659 address &= 0x1FFF; |
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1660 map = context->static_code_map; |
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1661 } else if (address >= 0x8000) { |
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1662 address &= 0x7FFF; |
279
6be6056735a9
Fix native address lookup in bannked memory area
Mike Pavone <pavone@retrodev.com>
parents:
277
diff
changeset
|
1663 map = context->banked_code_map + context->bank_reg; |
235
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1664 } else { |
313
a13329645ea3
Fix terminal instruction detection in disassembler
Mike Pavone <pavone@retrodev.com>
parents:
312
diff
changeset
|
1665 //dprintf("z80_get_native_address: %X NULL\n", address); |
235
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1666 return NULL; |
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1667 } |
268
6c2d7e003a55
Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents:
267
diff
changeset
|
1668 if (!map->base || !map->offsets || map->offsets[address] == INVALID_OFFSET || map->offsets[address] == EXTENSION_WORD) { |
313
a13329645ea3
Fix terminal instruction detection in disassembler
Mike Pavone <pavone@retrodev.com>
parents:
312
diff
changeset
|
1669 //dprintf("z80_get_native_address: %X NULL\n", address); |
235
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1670 return NULL; |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1671 } |
313
a13329645ea3
Fix terminal instruction detection in disassembler
Mike Pavone <pavone@retrodev.com>
parents:
312
diff
changeset
|
1672 //dprintf("z80_get_native_address: %X %p\n", address, map->base + map->offsets[address]); |
235
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1673 return map->base + map->offsets[address]; |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1674 } |
d9bf8e61c33c
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213
diff
changeset
|
1675 |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1676 uint8_t z80_get_native_inst_size(x86_z80_options * opts, uint32_t address) |
235
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1677 { |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1678 if (address >= 0x4000) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
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250
diff
changeset
|
1679 return 0; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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250
diff
changeset
|
1680 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
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250
diff
changeset
|
1681 return opts->ram_inst_sizes[address & 0x1FFF]; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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250
diff
changeset
|
1682 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1683 |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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250
diff
changeset
|
1684 void z80_map_native_address(z80_context * context, uint32_t address, uint8_t * native_address, uint8_t size, uint8_t native_size) |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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250
diff
changeset
|
1685 { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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250
diff
changeset
|
1686 uint32_t orig_address = address; |
235
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213
diff
changeset
|
1687 native_map_slot *map; |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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250
diff
changeset
|
1688 x86_z80_options * opts = context->options; |
235
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diff
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|
1689 if (address < 0x4000) { |
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diff
changeset
|
1690 address &= 0x1FFF; |
d9bf8e61c33c
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diff
changeset
|
1691 map = context->static_code_map; |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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diff
changeset
|
1692 opts->ram_inst_sizes[address] = native_size; |
63b9a500a00b
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changeset
|
1693 context->ram_code_flags[(address & 0x1C00) >> 10] |= 1 << ((address & 0x380) >> 7); |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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changeset
|
1694 context->ram_code_flags[((address + size) & 0x1C00) >> 10] |= 1 << (((address + size) & 0x380) >> 7); |
235
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diff
changeset
|
1695 } else if (address >= 0x8000) { |
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213
diff
changeset
|
1696 address &= 0x7FFF; |
279
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Fix native address lookup in bannked memory area
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277
diff
changeset
|
1697 map = context->banked_code_map + context->bank_reg; |
235
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diff
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|
1698 if (!map->offsets) { |
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213
diff
changeset
|
1699 map->offsets = malloc(sizeof(int32_t) * 0x8000); |
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213
diff
changeset
|
1700 memset(map->offsets, 0xFF, sizeof(int32_t) * 0x8000); |
d9bf8e61c33c
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213
diff
changeset
|
1701 } |
d9bf8e61c33c
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213
diff
changeset
|
1702 } else { |
d9bf8e61c33c
Get Z80 core working for simple programs
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diff
changeset
|
1703 return; |
d9bf8e61c33c
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changeset
|
1704 } |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1705 if (!map->base) { |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1706 map->base = native_address; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1707 } |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1708 map->offsets[address] = native_address - map->base; |
253
3b34deba4ca0
Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents:
252
diff
changeset
|
1709 for(--size, orig_address++; size; --size, orig_address++) { |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1710 address = orig_address; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1711 if (address < 0x4000) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1712 address &= 0x1FFF; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1713 map = context->static_code_map; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1714 } else if (address >= 0x8000) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1715 address &= 0x7FFF; |
279
6be6056735a9
Fix native address lookup in bannked memory area
Mike Pavone <pavone@retrodev.com>
parents:
277
diff
changeset
|
1716 map = context->banked_code_map + context->bank_reg; |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1717 } else { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1718 return; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1719 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1720 if (!map->offsets) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1721 map->offsets = malloc(sizeof(int32_t) * 0x8000); |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1722 memset(map->offsets, 0xFF, sizeof(int32_t) * 0x8000); |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1723 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1724 map->offsets[address] = EXTENSION_WORD; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1725 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1726 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1727 |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1728 #define INVALID_INSTRUCTION_START 0xFEEDFEED |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1729 |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1730 uint32_t z80_get_instruction_start(native_map_slot * static_code_map, uint32_t address) |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1731 { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1732 if (!static_code_map->base || address >= 0x4000) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1733 return INVALID_INSTRUCTION_START; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1734 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1735 address &= 0x1FFF; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1736 if (static_code_map->offsets[address] == INVALID_OFFSET) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1737 return INVALID_INSTRUCTION_START; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1738 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1739 while (static_code_map->offsets[address] == EXTENSION_WORD) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1740 --address; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1741 address &= 0x1FFF; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1742 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1743 return address; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1744 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1745 |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1746 z80_context * z80_handle_code_write(uint32_t address, z80_context * context) |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1747 { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1748 uint32_t inst_start = z80_get_instruction_start(context->static_code_map, address); |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1749 if (inst_start != INVALID_INSTRUCTION_START) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1750 uint8_t * dst = z80_get_native_address(context, inst_start); |
268
6c2d7e003a55
Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents:
267
diff
changeset
|
1751 dprintf("patching code at %p for Z80 instruction at %X due to write to %X\n", dst, inst_start, address); |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1752 dst = mov_ir(dst, inst_start, SCRATCH1, SZ_D); |
390
561fe3ea3fc8
Use a call instruction to figure out the original native address when retranslating so that it does not get lost when the byte transforms from a instruction word to extension word
Mike Pavone <pavone@retrodev.com>
parents:
389
diff
changeset
|
1753 dst = call(dst, (uint8_t *)z80_retrans_stub); |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1754 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1755 return context; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1756 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1757 |
264
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1758 uint8_t * z80_get_native_address_trans(z80_context * context, uint32_t address) |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1759 { |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1760 uint8_t * addr = z80_get_native_address(context, address); |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1761 if (!addr) { |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1762 translate_z80_stream(context, address); |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1763 addr = z80_get_native_address(context, address); |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1764 if (!addr) { |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1765 printf("Failed to translate %X to native code\n", address); |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1766 } |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1767 } |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1768 return addr; |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1769 } |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1770 |
266
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1771 void z80_handle_deferred(z80_context * context) |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1772 { |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1773 x86_z80_options * opts = context->options; |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1774 process_deferred(&opts->deferred, context, (native_addr_func)z80_get_native_address); |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1775 if (opts->deferred) { |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1776 translate_z80_stream(context, opts->deferred->address); |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1777 } |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1778 } |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1779 |
390
561fe3ea3fc8
Use a call instruction to figure out the original native address when retranslating so that it does not get lost when the byte transforms from a instruction word to extension word
Mike Pavone <pavone@retrodev.com>
parents:
389
diff
changeset
|
1780 void * z80_retranslate_inst(uint32_t address, z80_context * context, uint8_t * orig_start) |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1781 { |
266
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1782 char disbuf[80]; |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1783 x86_z80_options * opts = context->options; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1784 uint8_t orig_size = z80_get_native_inst_size(opts, address); |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1785 uint32_t orig = address; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1786 address &= 0x1FFF; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1787 uint8_t * dst = opts->cur_code; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1788 uint8_t * dst_end = opts->code_end; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1789 uint8_t *after, *inst = context->mem_pointers[0] + address; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1790 z80inst instbuf; |
268
6c2d7e003a55
Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents:
267
diff
changeset
|
1791 dprintf("Retranslating code at Z80 address %X, native address %p\n", address, orig_start); |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1792 after = z80_decode(inst, &instbuf); |
268
6c2d7e003a55
Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents:
267
diff
changeset
|
1793 #ifdef DO_DEBUG_PRINT |
314
54c0e5f22198
Show absolute addresses for JR, JRCC and DJNZ in Z80 disassembler
Mike Pavone <pavone@retrodev.com>
parents:
313
diff
changeset
|
1794 z80_disasm(&instbuf, disbuf, address); |
266
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1795 if (instbuf.op == Z80_NOP) { |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1796 printf("%X\t%s(%d)\n", address, disbuf, instbuf.immed); |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1797 } else { |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1798 printf("%X\t%s\n", address, disbuf); |
267
1788e3f29c28
Don't mix *H regs with the REX prefix
Mike Pavone <pavone@retrodev.com>
parents:
266
diff
changeset
|
1799 } |
268
6c2d7e003a55
Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents:
267
diff
changeset
|
1800 #endif |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1801 if (orig_size != ZMAX_NATIVE_SIZE) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1802 if (dst_end - dst < ZMAX_NATIVE_SIZE) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1803 size_t size = 1024*1024; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1804 dst = alloc_code(&size); |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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1805 opts->code_end = dst_end = dst + size; |
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1806 opts->cur_code = dst; |
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1807 } |
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1808 deferred_addr * orig_deferred = opts->deferred; |
252
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1809 uint8_t * native_end = translate_z80inst(&instbuf, dst, context, address); |
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1810 if ((native_end - dst) <= orig_size) { |
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1811 uint8_t * native_next = z80_get_native_address(context, address + after-inst); |
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1812 if (native_next && ((native_next == orig_start + orig_size) || (orig_size - (native_end - dst)) > 5)) { |
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1813 remove_deferred_until(&opts->deferred, orig_deferred); |
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1814 native_end = translate_z80inst(&instbuf, orig_start, context, address); |
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1815 if (native_next == orig_start + orig_size && (native_next-native_end) < 2) { |
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1816 while (native_end < orig_start + orig_size) { |
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1817 *(native_end++) = 0x90; //NOP |
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1818 } |
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1819 } else { |
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1820 jmp(native_end, native_next); |
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1821 } |
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1822 z80_handle_deferred(context); |
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1823 return orig_start; |
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1824 } |
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1825 } |
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1826 z80_map_native_address(context, address, dst, after-inst, ZMAX_NATIVE_SIZE); |
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1827 opts->cur_code = dst+ZMAX_NATIVE_SIZE; |
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1828 jmp(orig_start, dst); |
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1829 if (!z80_is_terminal(&instbuf)) { |
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1830 jmp(native_end, z80_get_native_address_trans(context, address + after-inst)); |
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1831 } |
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1832 z80_handle_deferred(context); |
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1833 return dst; |
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1834 } else { |
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1835 dst = translate_z80inst(&instbuf, orig_start, context, address); |
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1836 if (!z80_is_terminal(&instbuf)) { |
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1837 dst = jmp(dst, z80_get_native_address_trans(context, address + after-inst)); |
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1838 } |
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1839 z80_handle_deferred(context); |
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1840 return orig_start; |
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1841 } |
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1842 } |
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1843 |
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1844 void translate_z80_stream(z80_context * context, uint32_t address) |
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1845 { |
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1846 char disbuf[80]; |
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1847 if (z80_get_native_address(context, address)) { |
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1848 return; |
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1849 } |
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1850 x86_z80_options * opts = context->options; |
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1851 uint32_t start_address = address; |
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1852 uint8_t * encoded = NULL, *next; |
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1853 if (address < 0x4000) { |
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1854 encoded = context->mem_pointers[0] + (address & 0x1FFF); |
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1855 } else if(address >= 0x8000 && context->mem_pointers[1]) { |
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1856 printf("attempt to translate Z80 code from banked area at address %X\n", address); |
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1857 exit(1); |
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1858 //encoded = context->mem_pointers[1] + (address & 0x7FFF); |
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1859 } |
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1860 while (encoded != NULL) |
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1861 { |
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1862 z80inst inst; |
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1863 dprintf("translating Z80 code at address %X\n", address); |
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1864 do { |
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1865 if (opts->code_end-opts->cur_code < ZMAX_NATIVE_SIZE) { |
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1866 if (opts->code_end-opts->cur_code < 5) { |
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1867 puts("out of code memory, not enough space for jmp to next chunk"); |
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1868 exit(1); |
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1869 } |
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1870 size_t size = 1024*1024; |
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1871 opts->cur_code = alloc_code(&size); |
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1872 opts->code_end = opts->cur_code + size; |
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1873 jmp(opts->cur_code, opts->cur_code); |
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1874 } |
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1875 if (address > 0x4000 && address < 0x8000) { |
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1876 opts->cur_code = xor_rr(opts->cur_code, RDI, RDI, SZ_D); |
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1877 opts->cur_code = call(opts->cur_code, (uint8_t *)exit); |
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1878 break; |
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1879 } |
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1880 uint8_t * existing = z80_get_native_address(context, address); |
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1881 if (existing) { |
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1882 opts->cur_code = jmp(opts->cur_code, existing); |
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1883 break; |
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1884 } |
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1885 next = z80_decode(encoded, &inst); |
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1886 #ifdef DO_DEBUG_PRINT |
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1887 z80_disasm(&inst, disbuf, address); |
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1888 if (inst.op == Z80_NOP) { |
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1889 printf("%X\t%s(%d)\n", address, disbuf, inst.immed); |
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1890 } else { |
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1891 printf("%X\t%s\n", address, disbuf); |
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1892 } |
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1893 #endif |
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1894 uint8_t *after = translate_z80inst(&inst, opts->cur_code, context, address); |
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1895 z80_map_native_address(context, address, opts->cur_code, next-encoded, after - opts->cur_code); |
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1896 opts->cur_code = after; |
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1897 address += next-encoded; |
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1898 if (address > 0xFFFF) { |
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1899 address &= 0xFFFF; |
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1900 |
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1901 } else { |
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1902 encoded = next; |
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1903 } |
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1904 } while (!z80_is_terminal(&inst)); |
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1905 process_deferred(&opts->deferred, context, (native_addr_func)z80_get_native_address); |
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1906 if (opts->deferred) { |
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1907 address = opts->deferred->address; |
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1908 dprintf("defferred address: %X\n", address); |
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1909 if (address < 0x4000) { |
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1910 encoded = context->mem_pointers[0] + (address & 0x1FFF); |
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1911 } else if (address > 0x8000 && context->mem_pointers[1]) { |
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1912 encoded = context->mem_pointers[1] + (address & 0x7FFF); |
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1913 } else { |
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1914 printf("attempt to translate non-memory address: %X\n", address); |
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1915 exit(1); |
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1916 } |
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1917 } else { |
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1918 encoded = NULL; |
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1919 } |
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1920 } |
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1921 } |
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1922 |
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1923 void init_x86_z80_opts(x86_z80_options * options) |
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1924 { |
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1925 options->flags = 0; |
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1926 options->regs[Z80_B] = BH; |
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1927 options->regs[Z80_C] = RBX; |
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1928 options->regs[Z80_D] = CH; |
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1929 options->regs[Z80_E] = RCX; |
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1930 options->regs[Z80_H] = AH; |
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1931 options->regs[Z80_L] = RAX; |
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1932 options->regs[Z80_IXH] = DH; |
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1933 options->regs[Z80_IXL] = RDX; |
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1934 options->regs[Z80_IYH] = -1; |
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1935 options->regs[Z80_IYL] = R8; |
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1936 options->regs[Z80_I] = -1; |
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1937 options->regs[Z80_R] = -1; |
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1938 options->regs[Z80_A] = R10; |
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1939 options->regs[Z80_BC] = RBX; |
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1940 options->regs[Z80_DE] = RCX; |
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1941 options->regs[Z80_HL] = RAX; |
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1942 options->regs[Z80_SP] = R9; |
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1943 options->regs[Z80_AF] = -1; |
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1944 options->regs[Z80_IX] = RDX; |
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1945 options->regs[Z80_IY] = R8; |
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1946 size_t size = 1024 * 1024; |
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1947 options->cur_code = alloc_code(&size); |
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1948 options->code_end = options->cur_code + size; |
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1949 options->ram_inst_sizes = malloc(sizeof(uint8_t) * 0x2000); |
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1950 memset(options->ram_inst_sizes, 0, sizeof(uint8_t) * 0x2000); |
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1951 options->deferred = NULL; |
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1952 } |
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1953 |
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1954 void init_z80_context(z80_context * context, x86_z80_options * options) |
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1955 { |
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1956 memset(context, 0, sizeof(*context)); |
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1957 context->static_code_map = malloc(sizeof(*context->static_code_map)); |
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1958 context->static_code_map->base = NULL; |
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1959 context->static_code_map->offsets = malloc(sizeof(int32_t) * 0x2000); |
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1960 memset(context->static_code_map->offsets, 0xFF, sizeof(int32_t) * 0x2000); |
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1961 context->banked_code_map = malloc(sizeof(native_map_slot) * (1 << 9)); |
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1962 memset(context->banked_code_map, 0, sizeof(native_map_slot) * (1 << 9)); |
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1963 context->options = options; |
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1964 } |
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1965 |
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1966 void z80_reset(z80_context * context) |
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1967 { |
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1968 context->im = 0; |
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1969 context->iff1 = context->iff2 = 0; |
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1970 context->native_pc = z80_get_native_address_trans(context, 0); |
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1971 context->extra_pc = NULL; |
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1972 } |
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1973 |
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1974 void zinsert_breakpoint(z80_context * context, uint16_t address, uint8_t * bp_handler) |
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1975 { |
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1976 static uint8_t * bp_stub = NULL; |
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1977 uint8_t * native = z80_get_native_address_trans(context, address); |
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1978 uint8_t * start_native = native; |
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1979 native = mov_ir(native, address, SCRATCH1, SZ_W); |
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1980 if (!bp_stub) { |
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1981 x86_z80_options * opts = context->options; |
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1982 uint8_t * dst = opts->cur_code; |
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1983 uint8_t * dst_end = opts->code_end; |
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1984 if (dst_end - dst < 128) { |
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1985 size_t size = 1024*1024; |
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1986 dst = alloc_code(&size); |
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1987 opts->code_end = dst_end = dst + size; |
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1988 } |
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1989 bp_stub = dst; |
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1990 native = call(native, bp_stub); |
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1991 |
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1992 //Calculate length of prologue |
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1993 dst = z80_check_cycles_int(dst, address); |
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1994 int check_int_size = dst-bp_stub; |
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1995 dst = bp_stub; |
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1996 |
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1997 //Save context and call breakpoint handler |
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1998 dst = call(dst, (uint8_t *)z80_save_context); |
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1999 dst = push_r(dst, SCRATCH1); |
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2000 dst = mov_rr(dst, CONTEXT, RDI, SZ_Q); |
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2001 dst = mov_rr(dst, SCRATCH1, RSI, SZ_W); |
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2002 dst = call(dst, bp_handler); |
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2003 dst = mov_rr(dst, RAX, CONTEXT, SZ_Q); |
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2004 //Restore context |
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2005 dst = call(dst, (uint8_t *)z80_load_context); |
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2006 dst = pop_r(dst, SCRATCH1); |
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2007 //do prologue stuff |
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2008 dst = cmp_rr(dst, ZCYCLES, ZLIMIT, SZ_D); |
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2009 uint8_t * jmp_off = dst+1; |
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2010 dst = jcc(dst, CC_NC, dst + 7); |
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2011 dst = pop_r(dst, SCRATCH1); |
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2012 dst = add_ir(dst, check_int_size - (native-start_native), SCRATCH1, SZ_Q); |
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2013 dst = push_r(dst, SCRATCH1); |
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2014 dst = jmp(dst, (uint8_t *)z80_handle_cycle_limit_int); |
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2015 *jmp_off = dst - (jmp_off+1); |
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2016 //jump back to body of translated instruction |
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2017 dst = pop_r(dst, SCRATCH1); |
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2018 dst = add_ir(dst, check_int_size - (native-start_native), SCRATCH1, SZ_Q); |
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2019 dst = jmp_r(dst, SCRATCH1); |
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2020 opts->cur_code = dst; |
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2021 } else { |
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2022 native = call(native, bp_stub); |
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2023 } |
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2024 } |
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2025 |
366
836585d389b8
Partial implementation of Z80 debugger
Mike Pavone <pavone@retrodev.com>
parents:
363
diff
changeset
|
2026 void zremove_breakpoint(z80_context * context, uint16_t address) |
836585d389b8
Partial implementation of Z80 debugger
Mike Pavone <pavone@retrodev.com>
parents:
363
diff
changeset
|
2027 { |
836585d389b8
Partial implementation of Z80 debugger
Mike Pavone <pavone@retrodev.com>
parents:
363
diff
changeset
|
2028 uint8_t * native = z80_get_native_address(context, address); |
836585d389b8
Partial implementation of Z80 debugger
Mike Pavone <pavone@retrodev.com>
parents:
363
diff
changeset
|
2029 z80_check_cycles_int(native, address); |
836585d389b8
Partial implementation of Z80 debugger
Mike Pavone <pavone@retrodev.com>
parents:
363
diff
changeset
|
2030 } |
836585d389b8
Partial implementation of Z80 debugger
Mike Pavone <pavone@retrodev.com>
parents:
363
diff
changeset
|
2031 |
836585d389b8
Partial implementation of Z80 debugger
Mike Pavone <pavone@retrodev.com>
parents:
363
diff
changeset
|
2032 |