Mercurial > repos > blastem
annotate cpu_dsl.py @ 2476:aaf7bb58ffca
Fix bug in Gen/MD serialize routine that could cause a use-after free in some cases
author | Michael Pavone <pavone@retrodev.com> |
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date | Sun, 03 Mar 2024 13:47:59 -0800 |
parents | 0ca78837e4d2 |
children | ea37200967c7 |
rev | line source |
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1 #!/usr/bin/env python3 |
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2 |
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3 assignmentOps = { |
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4 '=': 'mov', |
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5 '+=': 'add', |
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6 '-=': 'sub', |
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7 '<<=': 'lsl', |
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8 '>>=': 'lsr', |
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9 '&=': 'and', |
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10 '|=': 'or', |
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11 '^=': 'xor' |
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12 } |
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13 binaryOps = { |
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14 '+': 'add', |
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15 '-': 'sub', |
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16 '<<': 'lsl', |
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17 '>>': 'lsr', |
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18 '&': 'and', |
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19 '|': 'or', |
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20 '^': 'xor' |
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21 } |
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22 unaryOps = { |
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23 '~': 'not', |
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24 '!': 'lnot', |
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25 '-': 'neg' |
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26 } |
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27 compareOps = {'>=U', '=', '!='} |
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28 class Block: |
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29 def addOp(self, op): |
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30 pass |
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31 |
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32 def processLine(self, parts): |
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33 if parts[0] == 'switch': |
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34 o = Switch(self, parts[1]) |
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35 self.addOp(o) |
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36 return o |
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37 elif parts[0] == 'if': |
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38 if len(parts) == 4 and parts[2] in compareOps: |
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39 self.addOp(NormalOp(['cmp', parts[3], parts[1]])) |
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40 cond = parts[2] |
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41 else: |
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42 cond = parts[1] |
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43 o = If(self, cond) |
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44 self.addOp(o) |
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45 return o |
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46 elif parts[0] == 'end': |
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47 raise Exception('end is only allowed inside a switch or if block') |
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48 else: |
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49 if len(parts) > 1 and parts[1] in assignmentOps: |
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50 dst = parts[0] |
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51 dst,_,size = dst.partition(':') |
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52 op = parts[1] |
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53 parts = [assignmentOps[op]] + parts[2:] |
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54 if op == '=': |
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55 if len(parts) > 2 and parts[2] in binaryOps: |
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56 op = parts[2] |
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57 parts[0] = binaryOps[op] |
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58 del parts[2] |
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59 elif len(parts) > 1 and parts[1][0] in unaryOps: |
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60 rest = parts[1][1:] |
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61 op = parts[1][0] |
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62 if rest: |
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63 parts[1] = rest |
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64 else: |
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65 del parts[1] |
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66 parts[0] = unaryOps[op] |
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67 else: |
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68 if op == '<<=' or op == '>>=': |
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69 parts.insert(1, dst) |
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70 else: |
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71 parts.append(dst) |
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72 parts.append(dst) |
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73 if size: |
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74 parts.append(size) |
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75 self.addOp(NormalOp(parts)) |
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76 return self |
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77 |
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78 def processOps(self, prog, fieldVals, output, otype, oplist): |
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79 for i in range(0, len(oplist)): |
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80 if i + 1 < len(oplist) and oplist[i+1].op == 'update_flags': |
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81 flagUpdates, _ = prog.flags.parseFlagUpdate(oplist[i+1].params[0]) |
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82 else: |
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83 flagUpdates = None |
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84 oplist[i].generate(prog, self, fieldVals, output, otype, flagUpdates) |
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85 |
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86 def resolveLocal(self, name): |
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87 return None |
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88 |
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89 class ChildBlock(Block): |
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90 def processLine(self, parts): |
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91 if parts[0] == 'end': |
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92 return self.parent |
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93 return super().processLine(parts) |
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94 |
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95 #Represents an instruction of the emulated CPU |
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96 class Instruction(Block): |
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97 def __init__(self, value, fields, name): |
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98 self.value = value |
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99 self.fields = fields |
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100 self.name = name |
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101 self.implementation = [] |
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102 self.locals = {} |
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103 self.regValues = {} |
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104 self.varyingBits = 0 |
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105 self.invalidFieldValues = {} |
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106 self.invalidCombos = [] |
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107 self.newLocals = [] |
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108 for field in fields: |
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109 self.varyingBits += fields[field][1] |
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110 |
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111 def addOp(self, op): |
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112 if op.op == 'local': |
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113 name = op.params[0] |
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114 size = int(op.params[1]) |
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115 self.locals[name] = size |
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116 elif op.op == 'invalid': |
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117 if len(op.params) < 3: |
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118 name = op.params[0] |
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119 value = int(op.params[1]) |
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120 self.invalidFieldValues.setdefault(name, set()).add(value) |
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121 else: |
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122 vmap = {} |
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123 for i in range(0, len(op.params), 2): |
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124 name = op.params[i] |
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125 value = int(op.params[i+1]) |
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126 vmap[name] = value |
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127 self.invalidCombos.append(vmap) |
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128 else: |
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129 self.implementation.append(op) |
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130 |
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131 def resolveLocal(self, name): |
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132 if name in self.locals: |
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133 return name |
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134 return None |
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135 |
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136 def addLocal(self, name, size): |
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137 self.locals[name] = size |
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138 self.newLocals.append(name) |
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139 |
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140 def localSize(self, name): |
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141 return self.locals.get(name) |
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142 |
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143 def __lt__(self, other): |
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144 if isinstance(other, Instruction): |
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145 if self.varyingBits != other.varyingBits: |
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146 return self.varyingBits < other.varyingBits |
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147 return self.value < other.value |
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148 else: |
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149 return NotImplemented |
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150 |
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151 def allValues(self): |
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152 values = [] |
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153 for i in range(0, 1 << self.varyingBits): |
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154 iword = self.value |
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155 doIt = True |
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156 combos = [] |
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157 for combo in self.invalidCombos: |
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158 combos.append(dict(combo)) |
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159 for field in self.fields: |
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160 shift,bits = self.fields[field] |
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161 val = i & ((1 << bits) - 1) |
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162 if field in self.invalidFieldValues and val in self.invalidFieldValues[field]: |
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163 doIt = False |
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164 break |
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165 nextcombos = [] |
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166 for combo in combos: |
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167 if field in combo: |
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168 if combo[field] == val: |
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169 del combo[field] |
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170 if not combo: |
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171 doIt = False |
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172 break |
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173 else: |
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174 continue |
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175 nextcombos.append(combo) |
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176 combos = nextcombos |
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177 if not doIt: |
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178 break |
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179 i >>= bits |
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180 iword |= val << shift |
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181 if doIt: |
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182 values.append(iword) |
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183 return values |
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184 |
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185 def getFieldVals(self, value): |
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186 fieldVals = {} |
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187 fieldBits = {} |
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188 for field in self.fields: |
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189 shift,bits = self.fields[field] |
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190 val = (value >> shift) & ((1 << bits) - 1) |
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191 fieldVals[field] = val |
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192 fieldBits[field] = bits |
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193 return (fieldVals, fieldBits) |
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194 |
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195 def generateName(self, value): |
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196 fieldVals,fieldBits = self.getFieldVals(value) |
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197 names = list(fieldVals.keys()) |
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198 names.sort() |
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199 funName = self.name |
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200 for name in names: |
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201 funName += '_{0}_{1:0>{2}}'.format(name, bin(fieldVals[name])[2:], fieldBits[name]) |
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202 return funName |
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203 |
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204 def generateBody(self, value, prog, otype): |
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205 output = [] |
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206 prog.meta = {} |
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207 prog.pushScope(self) |
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208 self.regValues = {} |
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209 for var in self.locals: |
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210 output.append('\n\tuint{sz}_t {name};'.format(sz=self.locals[var], name=var)) |
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211 self.newLocals = [] |
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212 fieldVals,_ = self.getFieldVals(value) |
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213 self.processOps(prog, fieldVals, output, otype, self.implementation) |
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214 |
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215 if prog.dispatch == 'call': |
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216 begin = '\nvoid ' + self.generateName(value) + '(' + prog.context_type + ' *context, uint32_t target_cycle)\n{' |
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217 elif prog.dispatch == 'goto': |
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218 begin = '\n' + self.generateName(value) + ': {' |
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219 else: |
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220 raise Exception('Unsupported dispatch type ' + prog.dispatch) |
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221 if prog.needFlagCoalesce: |
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222 begin += prog.flags.coalesceFlags(prog, otype) |
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223 if prog.needFlagDisperse: |
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224 output.append(prog.flags.disperseFlags(prog, otype)) |
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225 for var in self.newLocals: |
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226 begin += '\n\tuint{sz}_t {name};'.format(sz=self.locals[var], name=var) |
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227 for size in prog.temp: |
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228 begin += '\n\tuint{sz}_t gen_tmp{sz}__;'.format(sz=size) |
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229 prog.popScope() |
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230 if prog.dispatch == 'goto': |
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231 output += prog.nextInstruction(otype) |
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232 return begin + ''.join(output) + '\n}' |
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233 |
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234 def __str__(self): |
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235 pieces = [self.name + ' ' + hex(self.value) + ' ' + str(self.fields)] |
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236 for name in self.locals: |
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237 pieces.append('\n\tlocal {0} {1}'.format(name, self.locals[name])) |
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238 for op in self.implementation: |
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239 pieces.append(str(op)) |
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240 return ''.join(pieces) |
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241 |
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242 #Represents the definition of a helper function |
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243 class SubRoutine(Block): |
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244 def __init__(self, name): |
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245 self.name = name |
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246 self.implementation = [] |
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247 self.args = [] |
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248 self.arg_map = {} |
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249 self.locals = {} |
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250 self.regValues = {} |
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251 self.argValues = {} |
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252 |
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253 def addOp(self, op): |
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254 if op.op == 'arg': |
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255 name = op.params[0] |
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256 size = int(op.params[1]) |
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257 self.arg_map[name] = len(self.args) |
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258 self.args.append((name, size)) |
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259 elif op.op == 'local': |
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260 name = op.params[0] |
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261 size = int(op.params[1]) |
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262 self.locals[name] = size |
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263 else: |
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264 self.implementation.append(op) |
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265 |
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266 def resolveLocal(self, name): |
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267 if name in self.locals: |
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268 return self.name + '_' + name |
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269 return None |
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270 |
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271 def addLocal(self, name, size): |
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272 self.locals[name] = size |
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273 |
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274 def localSize(self, name): |
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275 if name in self.locals: |
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276 return self.locals[name] |
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277 if name in self.arg_map: |
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278 argIndex = self.arg_map[name] |
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279 return self.args[argIndex][1] |
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280 return None |
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281 |
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282 def inline(self, prog, params, output, otype, parent): |
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283 if len(params) != len(self.args): |
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284 raise Exception('{0} expects {1} arguments, but was called with {2}'.format(self.name, len(self.args), len(params))) |
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285 argValues = {} |
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286 if parent: |
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287 self.regValues = parent.regValues |
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288 prog.pushScope(self) |
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289 i = 0 |
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290 for name,size in self.args: |
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291 argValues[name] = params[i] |
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292 i += 1 |
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293 for name in self.locals: |
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294 size = self.locals[name] |
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295 output.append('\n\tuint{size}_t {sub}_{local};'.format(size=size, sub=self.name, local=name)) |
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296 self.argValues = argValues |
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297 self.processOps(prog, argValues, output, otype, self.implementation) |
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298 prog.popScope() |
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299 |
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300 def __str__(self): |
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301 pieces = [self.name] |
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302 for name,size in self.args: |
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303 pieces.append('\n\targ {0} {1}'.format(name, size)) |
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304 for name in self.locals: |
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305 pieces.append('\n\tlocal {0} {1}'.format(name, self.locals[name])) |
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306 for op in self.implementation: |
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307 pieces.append(str(op)) |
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308 return ''.join(pieces) |
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309 |
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310 class Op: |
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311 def __init__(self, evalFun = None): |
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312 self.evalFun = evalFun |
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313 self.impls = {} |
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314 self.outOp = () |
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315 def cBinaryOperator(self, op): |
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316 def _impl(prog, params, rawParams, flagUpdates): |
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317 if op == '-': |
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318 a = params[1] |
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319 b = params[0] |
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320 else: |
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321 a = params[0] |
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322 b = params[1] |
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323 needsSizeAdjust = False |
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324 if len(params) > 3: |
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325 size = params[3] |
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326 if size == 0: |
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327 size = 8 |
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328 elif size == 1: |
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329 size = 16 |
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330 else: |
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331 size = 32 |
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332 prog.lastSize = size |
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333 destSize = prog.paramSize(rawParams[2]) |
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334 if destSize > size: |
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335 needsSizeAdjust = True |
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336 prog.sizeAdjust = size |
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337 needsCarry = needsOflow = needsHalf = False |
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338 if flagUpdates: |
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339 for flag in flagUpdates: |
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340 calc = prog.flags.flagCalc[flag] |
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341 if calc == 'carry': |
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342 needsCarry = True |
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343 elif calc == 'half-carry': |
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344 needsHalf = True |
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345 elif calc == 'overflow': |
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346 needsOflow = True |
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347 decl = '' |
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348 if needsCarry or needsOflow or needsHalf or (flagUpdates and needsSizeAdjust): |
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349 if len(params) <= 3: |
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350 size = prog.paramSize(rawParams[2]) |
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351 if needsCarry and op != '>>': |
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352 size *= 2 |
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353 decl,name = prog.getTemp(size) |
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354 dst = prog.carryFlowDst = name |
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355 prog.lastA = a |
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356 prog.lastB = b |
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357 if size == 64: |
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358 a = '((uint64_t){a})'.format(a=a) |
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359 b = '((uint64_t){b})'.format(b=b) |
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360 prog.lastBFlow = b if op == '-' else '(~{b})'.format(b=b) |
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361 elif needsSizeAdjust: |
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362 decl,name = prog.getTemp(size) |
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363 dst = params[2] |
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364 return '{decl}\n\t{tmp} = ({a} & {mask}) {op} ({b} & {mask});\n\t{dst} = ({dst} & ~{mask}) | {tmp};'.format( |
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365 decl = decl, tmp = name, a = a, b = b, op = op, dst = dst, mask = ((1 << size) - 1) |
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366 ) |
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367 else: |
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368 dst = params[2] |
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369 if needsSizeAdjust: |
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370 return decl + '\n\t{dst} = ({a} & {mask}) {op} ({b} & {mask});'.format( |
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371 dst = dst, a = a, b = b, op = op, mask = (1 << prog.sizeAdjust) - 1 |
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372 ) |
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373 else: |
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374 return decl + '\n\t{dst} = {a} {op} {b};'.format( |
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375 dst = dst, a = a, b = b, op = op |
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376 ) |
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377 self.impls['c'] = _impl |
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378 self.outOp = (2,) |
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379 return self |
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380 def cUnaryOperator(self, op): |
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381 def _impl(prog, params, rawParams, flagUpdates): |
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382 dst = params[1] |
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383 decl = '' |
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384 needsSizeAdjust = False |
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385 if len(params) > 2: |
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386 size = params[2] |
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387 if size == 0: |
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388 size = 8 |
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389 elif size == 1: |
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390 size = 16 |
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391 else: |
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392 size = 32 |
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393 prog.lastSize = size |
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394 destSize = prog.paramSize(rawParams[1]) |
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395 if destSize > size: |
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396 needsSizeAdjust = True |
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397 prog.sizeAdjust = size |
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398 needsCarry = needsOflow = needsHalf = False |
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399 if op == '-': |
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400 if flagUpdates: |
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401 for flag in flagUpdates: |
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402 calc = prog.flags.flagCalc[flag] |
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403 if calc == 'carry': |
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404 needsCarry = True |
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405 elif calc == 'half-carry': |
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406 needsHalf = True |
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407 elif calc == 'overflow': |
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408 needsOflow = True |
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409 if needsCarry or needsOflow or needsHalf or (flagUpdates and needsSizeAdjust): |
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410 size = prog.paramSize(rawParams[1]) |
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411 decl,name = prog.getTemp(size) |
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412 dst = prog.carryFlowDst = name |
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413 prog.lastA = 0 |
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414 prog.lastB = params[0] |
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415 prog.lastBFlow = params[0] |
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416 if needsSizeAdjust: |
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417 return decl + '\n\t{dst} = {op}({a} & {mask});'.format( |
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418 dst = dst, a = params[0], op = op, mask = (1 << prog.sizeAdjust) - 1 |
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|
419 ) |
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420 if needsSizeAdjust: |
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421 return decl + '\n\t{dst} = ({dst} & ~{mask}) | (({op}{a}) & {mask});'.format( |
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422 dst = dst, a = params[0], op = op, mask = (1 << prog.sizeAdjust) - 1 |
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423 ) |
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424 else: |
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425 return decl + '\n\t{dst} = {op}{a};'.format( |
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426 dst = dst, a = params[0], op = op |
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427 ) |
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428 self.impls['c'] = _impl |
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|
429 self.outOp = (1,) |
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430 return self |
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|
431 def addImplementation(self, lang, outOp, impl): |
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|
432 self.impls[lang] = impl |
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|
433 if not outOp is None: |
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|
434 if type(outOp) is tuple: |
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|
435 self.outOp = outOp |
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|
436 else: |
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|
437 self.outOp = (outOp,) |
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|
438 return self |
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|
439 def evaluate(self, params): |
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|
440 return self.evalFun(*params) |
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|
441 def canEval(self): |
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|
442 return not self.evalFun is None |
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|
443 def numArgs(self): |
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|
444 return self.evalFun.__code__.co_argcount |
1716
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|
445 def numParams(self): |
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446 if self.outOp: |
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447 params = max(self.outOp) + 1 |
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448 else: |
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|
449 params = 0 |
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|
450 if self.evalFun: |
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451 params = max(params, self.numArgs()) |
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|
452 return params |
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|
453 def generate(self, otype, prog, params, rawParams, flagUpdates): |
1613
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|
454 if self.impls[otype].__code__.co_argcount == 2: |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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changeset
|
455 return self.impls[otype](prog, params) |
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|
456 elif self.impls[otype].__code__.co_argcount == 3: |
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|
457 return self.impls[otype](prog, params, rawParams) |
1613
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
diff
changeset
|
458 else: |
1704
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First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
459 return self.impls[otype](prog, params, rawParams, flagUpdates) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
460 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
461 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
diff
changeset
|
462 def _xchgCImpl(prog, params, rawParams): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
diff
changeset
|
463 size = prog.paramSize(rawParams[0]) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
diff
changeset
|
464 decl,name = prog.getTemp(size) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
diff
changeset
|
465 return decl + '\n\t{tmp} = {a};\n\t{a} = {b};\n\t{b} = {tmp};'.format(a = params[0], b = params[1], tmp = name) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
466 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
467 def _dispatchCImpl(prog, params): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
468 if len(params) == 1: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
469 table = 'main' |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
470 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
471 table = params[1] |
1749
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
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parents:
1748
diff
changeset
|
472 if prog.dispatch == 'call': |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
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parents:
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diff
changeset
|
473 return '\n\timpl_{tbl}[{op}](context, target_cycle);'.format(tbl = table, op = params[0]) |
1749
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
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parents:
1748
diff
changeset
|
474 elif prog.dispatch == 'goto': |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
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parents:
1748
diff
changeset
|
475 return '\n\tgoto *impl_{tbl}[{op}];'.format(tbl = table, op = params[0]) |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
476 else: |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
477 raise Exception('Unsupported dispatch type ' + prog.dispatch) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
478 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
479 def _updateFlagsCImpl(prog, params, rawParams): |
1704
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
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parents:
1703
diff
changeset
|
480 autoUpdate, explicit = prog.flags.parseFlagUpdate(params[0]) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
diff
changeset
|
481 output = [] |
1713
0264d8b288e2
Implement parity flag calculation type
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parents:
1711
diff
changeset
|
482 parity = None |
1747
89ddf41a50bb
Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1745
diff
changeset
|
483 directFlags = {} |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
484 for flag in autoUpdate: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
diff
changeset
|
485 calc = prog.flags.flagCalc[flag] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
diff
changeset
|
486 calc,_,resultBit = calc.partition('-') |
1704
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
487 if prog.carryFlowDst: |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
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parents:
1703
diff
changeset
|
488 lastDst = prog.carryFlowDst |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
489 else: |
1734
88fbc4e711fd
Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1733
diff
changeset
|
490 lastDst = prog.resolveParam(prog.lastDst, prog.currentScope, {}) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
491 storage = prog.flags.getStorage(flag) |
1705
9ab64ef5cba0
Initial stab at overflow flag implementation in CPU DSL. Probably broken for subtraction
Michael Pavone <pavone@retrodev.com>
parents:
1704
diff
changeset
|
492 if calc == 'bit' or calc == 'sign' or calc == 'carry' or calc == 'half' or calc == 'overflow': |
1704
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
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parents:
1703
diff
changeset
|
493 myRes = lastDst |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
494 if calc == 'sign': |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
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parents:
1765
diff
changeset
|
495 resultBit = prog.getLastSize() - 1 |
1704
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
496 elif calc == 'carry': |
1723
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
497 if prog.lastOp.op in ('asr', 'lsr'): |
2448
d1eec03dca09
Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents:
2443
diff
changeset
|
498 if type(prog.lastB) is int: |
d1eec03dca09
Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents:
2443
diff
changeset
|
499 resultBit = prog.lastB - 1 |
d1eec03dca09
Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents:
2443
diff
changeset
|
500 else: |
d1eec03dca09
Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents:
2443
diff
changeset
|
501 #FIXME!!!!! |
d1eec03dca09
Fix some issues in new 68K core and add implementations of negx and clr instructions
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parents:
2443
diff
changeset
|
502 resultBit = 0 |
1723
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
503 myRes = prog.lastA |
2463
679c31768013
Fix carry flag calculation for neg instruction in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
2452
diff
changeset
|
504 elif prog.lastOp.op == 'neg': |
679c31768013
Fix carry flag calculation for neg instruction in CPU DSL
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parents:
2452
diff
changeset
|
505 if prog.carryFlowDst: |
679c31768013
Fix carry flag calculation for neg instruction in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
2452
diff
changeset
|
506 realSize = prog.getLastSize() |
679c31768013
Fix carry flag calculation for neg instruction in CPU DSL
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parents:
2452
diff
changeset
|
507 if realSize != prog.paramSize(prog.carryFlowDst): |
679c31768013
Fix carry flag calculation for neg instruction in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
2452
diff
changeset
|
508 lastDst = '({res} & {mask})'.format(res=lastDst, mask = (1 << realSize) - 1) |
679c31768013
Fix carry flag calculation for neg instruction in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
2452
diff
changeset
|
509 if type(storage) is tuple: |
679c31768013
Fix carry flag calculation for neg instruction in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
2452
diff
changeset
|
510 reg,storageBit = storage |
679c31768013
Fix carry flag calculation for neg instruction in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
2452
diff
changeset
|
511 reg = prog.resolveParam(reg, None, {}) |
679c31768013
Fix carry flag calculation for neg instruction in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
2452
diff
changeset
|
512 output.append('\n\t{reg} = {res} ? ({reg} | {bit}U) : ({reg} & {mask}U);'.format( |
679c31768013
Fix carry flag calculation for neg instruction in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
2452
diff
changeset
|
513 reg = reg, mask = ~(1 << storageBit), res = lastDst, bit = 1 << storageBit |
679c31768013
Fix carry flag calculation for neg instruction in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
2452
diff
changeset
|
514 )) |
679c31768013
Fix carry flag calculation for neg instruction in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
2452
diff
changeset
|
515 else: |
679c31768013
Fix carry flag calculation for neg instruction in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
2452
diff
changeset
|
516 reg = prog.resolveParam(storage, None, {}) |
679c31768013
Fix carry flag calculation for neg instruction in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
2452
diff
changeset
|
517 output.append('\n\t{reg} = {res} != 0;'.format( |
679c31768013
Fix carry flag calculation for neg instruction in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
2452
diff
changeset
|
518 reg = reg, res = lastDst |
679c31768013
Fix carry flag calculation for neg instruction in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
2452
diff
changeset
|
519 )) |
679c31768013
Fix carry flag calculation for neg instruction in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
2452
diff
changeset
|
520 continue |
1723
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
521 else: |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
522 resultBit = prog.getLastSize() |
1723
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
523 if prog.lastOp.op == 'ror': |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
524 resultBit -= 1 |
1704
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
525 elif calc == 'half': |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
526 resultBit = prog.getLastSize() - 4 |
1708
5bfed2eedc9d
Fixed flag calculation for sub instructions in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1707
diff
changeset
|
527 myRes = '({a} ^ {b} ^ {res})'.format(a = prog.lastA, b = prog.lastB, res = lastDst) |
1705
9ab64ef5cba0
Initial stab at overflow flag implementation in CPU DSL. Probably broken for subtraction
Michael Pavone <pavone@retrodev.com>
parents:
1704
diff
changeset
|
528 elif calc == 'overflow': |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
529 resultBit = prog.getLastSize() - 1 |
1711
87d4f0b4bf1d
Actually correct overflow flag calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1710
diff
changeset
|
530 myRes = '((({a} ^ {b})) & ({a} ^ {res}))'.format(a = prog.lastA, b = prog.lastBFlow, res = lastDst) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
531 else: |
1715
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1713
diff
changeset
|
532 #Note: offsetting this by the operation size - 8 makes sense for the Z80 |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1713
diff
changeset
|
533 #but might not for other CPUs with this kind of fixed bit flag behavior |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
534 resultBit = int(resultBit) + prog.getLastSize() - 8 |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
535 if type(storage) is tuple: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
536 reg,storageBit = storage |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
537 if storageBit == resultBit: |
1747
89ddf41a50bb
Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1745
diff
changeset
|
538 directFlags.setdefault((reg, myRes), []).append(resultBit) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
539 else: |
1747
89ddf41a50bb
Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1745
diff
changeset
|
540 reg = prog.resolveParam(reg, None, {}) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
541 if resultBit > storageBit: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
542 op = '>>' |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
543 shift = resultBit - storageBit |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
544 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
545 op = '<<' |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
546 shift = storageBit - resultBit |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
547 output.append('\n\t{reg} = ({reg} & ~{mask}U) | ({res} {op} {shift}U & {mask}U);'.format( |
1704
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
548 reg = reg, mask = 1 << storageBit, res = myRes, op = op, shift = shift |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
549 )) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
550 else: |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
551 reg = prog.resolveParam(storage, None, {}) |
1715
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1713
diff
changeset
|
552 maxBit = prog.paramSize(storage) - 1 |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1713
diff
changeset
|
553 if resultBit > maxBit: |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1713
diff
changeset
|
554 output.append('\n\t{reg} = {res} >> {shift} & {mask}U;'.format(reg=reg, res=myRes, shift = resultBit - maxBit, mask = 1 << maxBit)) |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1713
diff
changeset
|
555 else: |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1713
diff
changeset
|
556 output.append('\n\t{reg} = {res} & {mask}U;'.format(reg=reg, res=myRes, mask = 1 << resultBit)) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
557 elif calc == 'zero': |
1721
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
558 if prog.carryFlowDst: |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
559 realSize = prog.getLastSize() |
1721
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
560 if realSize != prog.paramSize(prog.carryFlowDst): |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
561 lastDst = '({res} & {mask})'.format(res=lastDst, mask = (1 << realSize) - 1) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
562 if type(storage) is tuple: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
563 reg,storageBit = storage |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
564 reg = prog.resolveParam(reg, None, {}) |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
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diff
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|
565 output.append('\n\t{reg} = {res} ? ({reg} & {mask}U) : ({reg} | {bit}U);'.format( |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
566 reg = reg, mask = ~(1 << storageBit), res = lastDst, bit = 1 << storageBit |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
567 )) |
1703
49a52c737bf0
Fix zero flag calculation in CPU DSL
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parents:
1702
diff
changeset
|
568 else: |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
569 reg = prog.resolveParam(storage, None, {}) |
1703
49a52c737bf0
Fix zero flag calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1702
diff
changeset
|
570 output.append('\n\t{reg} = {res} == 0;'.format( |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
571 reg = reg, res = lastDst |
1705
9ab64ef5cba0
Initial stab at overflow flag implementation in CPU DSL. Probably broken for subtraction
Michael Pavone <pavone@retrodev.com>
parents:
1704
diff
changeset
|
572 )) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
573 elif calc == 'parity': |
1713
0264d8b288e2
Implement parity flag calculation type
Michael Pavone <pavone@retrodev.com>
parents:
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diff
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|
574 parity = storage |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
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575 paritySize = prog.getLastSize() |
1713
0264d8b288e2
Implement parity flag calculation type
Michael Pavone <pavone@retrodev.com>
parents:
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|
576 if prog.carryFlowDst: |
0264d8b288e2
Implement parity flag calculation type
Michael Pavone <pavone@retrodev.com>
parents:
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577 parityDst = paritySrc = prog.carryFlowDst |
0264d8b288e2
Implement parity flag calculation type
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parents:
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diff
changeset
|
578 else: |
0264d8b288e2
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diff
changeset
|
579 paritySrc = lastDst |
0264d8b288e2
Implement parity flag calculation type
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diff
changeset
|
580 decl,name = prog.getTemp(paritySize) |
0264d8b288e2
Implement parity flag calculation type
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parents:
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diff
changeset
|
581 output.append(decl) |
0264d8b288e2
Implement parity flag calculation type
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parents:
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diff
changeset
|
582 parityDst = name |
1704
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
583 else: |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
584 raise Exception('Unknown flag calc type: ' + calc) |
1747
89ddf41a50bb
Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
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diff
changeset
|
585 for reg, myRes in directFlags: |
89ddf41a50bb
Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL
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parents:
1745
diff
changeset
|
586 bits = directFlags[(reg, myRes)] |
89ddf41a50bb
Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
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587 resolved = prog.resolveParam(reg, None, {}) |
89ddf41a50bb
Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
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diff
changeset
|
588 if len(bits) == len(prog.flags.storageToFlags[reg]): |
89ddf41a50bb
Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
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diff
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|
589 output.append('\n\t{reg} = {res};'.format(reg = resolved, res = myRes)) |
89ddf41a50bb
Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
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diff
changeset
|
590 else: |
89ddf41a50bb
Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL
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parents:
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diff
changeset
|
591 mask = 0 |
89ddf41a50bb
Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL
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parents:
1745
diff
changeset
|
592 for bit in bits: |
89ddf41a50bb
Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
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changeset
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593 mask |= 1 << bit |
89ddf41a50bb
Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
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594 output.append('\n\t{reg} = ({reg} & ~{mask}U) | ({res} & {mask}U);'.format( |
89ddf41a50bb
Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1745
diff
changeset
|
595 reg = resolved, mask = mask, res = myRes |
89ddf41a50bb
Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
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changeset
|
596 )) |
1704
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
597 if prog.carryFlowDst: |
1719
fb5ae8c20b85
Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1716
diff
changeset
|
598 if prog.lastOp.op != 'cmp': |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
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|
599 if prog.sizeAdjust: |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
600 output.append('\n\t{dst} = ({dst} & ~{mask}) | ({tmpdst} & {mask});'.format( |
0c1491818f4b
WIP new 68K core using CPU DSL
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changeset
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601 dst = prog.resolveParam(prog.lastDst, prog.currentScope, {}), tmpdst = prog.carryFlowDst, mask = ((1 << prog.sizeAdjust) - 1) |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
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|
602 )) |
0c1491818f4b
WIP new 68K core using CPU DSL
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603 prog.sizeAdjust = None |
0c1491818f4b
WIP new 68K core using CPU DSL
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diff
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|
604 else: |
0c1491818f4b
WIP new 68K core using CPU DSL
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changeset
|
605 output.append('\n\t{dst} = {tmpdst};'.format(dst = prog.resolveParam(prog.lastDst, prog.currentScope, {}), tmpdst = prog.carryFlowDst)) |
1704
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
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changeset
|
606 prog.carryFlowDst = None |
1713
0264d8b288e2
Implement parity flag calculation type
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diff
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|
607 if parity: |
0264d8b288e2
Implement parity flag calculation type
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changeset
|
608 if paritySize > 8: |
0264d8b288e2
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|
609 if paritySize > 16: |
0264d8b288e2
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|
610 output.append('\n\t{dst} = {src} ^ ({src} >> 16);'.format(dst=parityDst, src=paritySrc)) |
0264d8b288e2
Implement parity flag calculation type
Michael Pavone <pavone@retrodev.com>
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611 paritySrc = parityDst |
0264d8b288e2
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Michael Pavone <pavone@retrodev.com>
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|
612 output.append('\n\t{dst} = {src} ^ ({src} >> 8);'.format(dst=parityDst, src=paritySrc)) |
0264d8b288e2
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|
613 paritySrc = parityDst |
0264d8b288e2
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|
614 output.append('\n\t{dst} = ({src} ^ ({src} >> 4)) & 0xF;'.format(dst=parityDst, src=paritySrc)) |
0264d8b288e2
Implement parity flag calculation type
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diff
changeset
|
615 if type(parity) is tuple: |
0264d8b288e2
Implement parity flag calculation type
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parents:
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diff
changeset
|
616 reg,bit = parity |
0264d8b288e2
Implement parity flag calculation type
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parents:
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diff
changeset
|
617 reg = prog.resolveParam(reg, None, {}) |
0264d8b288e2
Implement parity flag calculation type
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parents:
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diff
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|
618 output.append('\n\t{flag} = ({flag} & ~{mask}U) | ((0x6996 >> {parity}) << {bit} & {mask}U);'.format( |
0264d8b288e2
Implement parity flag calculation type
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parents:
1711
diff
changeset
|
619 flag=reg, mask = 1 << bit, bit = bit, parity = parityDst |
0264d8b288e2
Implement parity flag calculation type
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parents:
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|
620 )) |
0264d8b288e2
Implement parity flag calculation type
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parents:
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diff
changeset
|
621 else: |
0264d8b288e2
Implement parity flag calculation type
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parents:
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diff
changeset
|
622 reg = prog.resolveParam(parity, None, {}) |
0264d8b288e2
Implement parity flag calculation type
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parents:
1711
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changeset
|
623 output.append('\n\t{flag} = 0x9669 >> {parity} & 1;'.format(flag=reg, parity=parityDst)) |
0264d8b288e2
Implement parity flag calculation type
Michael Pavone <pavone@retrodev.com>
parents:
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changeset
|
624 |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
625 #TODO: combine explicit flags targeting the same storage location |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
626 for flag in explicit: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
627 location = prog.flags.getStorage(flag) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
628 if type(location) is tuple: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
629 reg,bit = location |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
630 reg = prog.resolveReg(reg, None, {}) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
631 value = str(1 << bit) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
632 if explicit[flag]: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
633 operator = '|=' |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
634 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
635 operator = '&=' |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
636 value = '~' + value |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
637 output.append('\n\t{reg} {op} {val};'.format(reg=reg, op=operator, val=value)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
638 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
639 reg = prog.resolveReg(location, None, {}) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
640 output.append('\n\t{reg} = {val};'.format(reg=reg, val=explicit[flag])) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
641 return ''.join(output) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
642 |
1719
fb5ae8c20b85
Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1716
diff
changeset
|
643 def _cmpCImpl(prog, params, rawParams, flagUpdates): |
2451
edd73a009537
Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands
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parents:
2448
diff
changeset
|
644 b_size = size = prog.paramSize(rawParams[1]) |
1719
fb5ae8c20b85
Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1716
diff
changeset
|
645 needsCarry = False |
fb5ae8c20b85
Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1716
diff
changeset
|
646 if flagUpdates: |
fb5ae8c20b85
Fix cp instruction in new Z80 core and implement its DD/FD prefixes
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parents:
1716
diff
changeset
|
647 for flag in flagUpdates: |
fb5ae8c20b85
Fix cp instruction in new Z80 core and implement its DD/FD prefixes
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parents:
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diff
changeset
|
648 calc = prog.flags.flagCalc[flag] |
fb5ae8c20b85
Fix cp instruction in new Z80 core and implement its DD/FD prefixes
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parents:
1716
diff
changeset
|
649 if calc == 'carry': |
fb5ae8c20b85
Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents:
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diff
changeset
|
650 needsCarry = True |
fb5ae8c20b85
Fix cp instruction in new Z80 core and implement its DD/FD prefixes
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parents:
1716
diff
changeset
|
651 break |
2451
edd73a009537
Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands
Michael Pavone <pavone@retrodev.com>
parents:
2448
diff
changeset
|
652 if len(params) > 2: |
edd73a009537
Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands
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parents:
2448
diff
changeset
|
653 size = params[2] |
edd73a009537
Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands
Michael Pavone <pavone@retrodev.com>
parents:
2448
diff
changeset
|
654 if size == 0: |
edd73a009537
Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands
Michael Pavone <pavone@retrodev.com>
parents:
2448
diff
changeset
|
655 size = 8 |
edd73a009537
Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands
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parents:
2448
diff
changeset
|
656 elif size == 1: |
edd73a009537
Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands
Michael Pavone <pavone@retrodev.com>
parents:
2448
diff
changeset
|
657 size = 16 |
edd73a009537
Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands
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parents:
2448
diff
changeset
|
658 else: |
edd73a009537
Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands
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parents:
2448
diff
changeset
|
659 size = 32 |
edd73a009537
Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands
Michael Pavone <pavone@retrodev.com>
parents:
2448
diff
changeset
|
660 prog.lastSize = size |
1719
fb5ae8c20b85
Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1716
diff
changeset
|
661 if needsCarry: |
fb5ae8c20b85
Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1716
diff
changeset
|
662 size *= 2 |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
663 tmpvar = 'cmp_tmp{sz}__'.format(sz=size) |
1745
a8f04b0ab744
Fixes to DAA, SCF and CCF to pass ZEXALL in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1744
diff
changeset
|
664 if flagUpdates: |
a8f04b0ab744
Fixes to DAA, SCF and CCF to pass ZEXALL in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1744
diff
changeset
|
665 prog.carryFlowDst = tmpvar |
a8f04b0ab744
Fixes to DAA, SCF and CCF to pass ZEXALL in new Z80 core
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parents:
1744
diff
changeset
|
666 prog.lastA = params[1] |
a8f04b0ab744
Fixes to DAA, SCF and CCF to pass ZEXALL in new Z80 core
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parents:
1744
diff
changeset
|
667 prog.lastB = params[0] |
a8f04b0ab744
Fixes to DAA, SCF and CCF to pass ZEXALL in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1744
diff
changeset
|
668 prog.lastBFlow = params[0] |
1618
5dbc453cd345
Getting SVP core closer to compiling
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parents:
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diff
changeset
|
669 scope = prog.getRootScope() |
5dbc453cd345
Getting SVP core closer to compiling
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parents:
1616
diff
changeset
|
670 if not scope.resolveLocal(tmpvar): |
5dbc453cd345
Getting SVP core closer to compiling
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parents:
1616
diff
changeset
|
671 scope.addLocal(tmpvar, size) |
1719
fb5ae8c20b85
Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1716
diff
changeset
|
672 prog.lastDst = rawParams[1] |
2451
edd73a009537
Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands
Michael Pavone <pavone@retrodev.com>
parents:
2448
diff
changeset
|
673 a = params[0] |
edd73a009537
Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands
Michael Pavone <pavone@retrodev.com>
parents:
2448
diff
changeset
|
674 b = params[1] |
edd73a009537
Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands
Michael Pavone <pavone@retrodev.com>
parents:
2448
diff
changeset
|
675 a_size = prog.paramSize(rawParams[0]) |
edd73a009537
Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands
Michael Pavone <pavone@retrodev.com>
parents:
2448
diff
changeset
|
676 if prog.lastSize != a_size: |
edd73a009537
Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands
Michael Pavone <pavone@retrodev.com>
parents:
2448
diff
changeset
|
677 a = '(({a}) & {mask})'.format(a = a, mask = (1 << prog.lastSize) - 1) |
edd73a009537
Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands
Michael Pavone <pavone@retrodev.com>
parents:
2448
diff
changeset
|
678 if prog.lastSize != b_size: |
edd73a009537
Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands
Michael Pavone <pavone@retrodev.com>
parents:
2448
diff
changeset
|
679 b = '(({b}) & {mask})'.format(b = b, mask = (1 << prog.lastSize) - 1) |
edd73a009537
Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands
Michael Pavone <pavone@retrodev.com>
parents:
2448
diff
changeset
|
680 if size == 64: |
edd73a009537
Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands
Michael Pavone <pavone@retrodev.com>
parents:
2448
diff
changeset
|
681 a = '((uint64_t){a})'.format(a = a) |
edd73a009537
Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands
Michael Pavone <pavone@retrodev.com>
parents:
2448
diff
changeset
|
682 b = '((uint64_t){b})'.format(b = b) |
edd73a009537
Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands
Michael Pavone <pavone@retrodev.com>
parents:
2448
diff
changeset
|
683 return '\n\t{var} = {b} - {a};'.format(var = tmpvar, a = a, b = b) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
684 |
1723
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
685 def _asrCImpl(prog, params, rawParams, flagUpdates): |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
686 needsCarry = False |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
687 if flagUpdates: |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
688 for flag in flagUpdates: |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
689 calc = prog.flags.flagCalc[flag] |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
690 if calc == 'carry': |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
691 needsCarry = True |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
692 decl = '' |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
693 size = prog.paramSize(rawParams[2]) |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
694 if needsCarry: |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
695 decl,name = prog.getTemp(size * 2) |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
696 dst = prog.carryFlowDst = name |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
697 prog.lastA = params[0] |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
698 else: |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
699 dst = params[2] |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
700 mask = 1 << (size - 1) |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
701 return decl + '\n\t{dst} = ({a} >> {b}) | ({a} & {mask} ? 0xFFFFFFFFU << ({size} - {b}) : 0);'.format( |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
702 a = params[0], b = params[1], dst = dst, mask = mask, size=size) |
1697
44d8c6e61ad4
Added new sext instruction for sign extension to CPU sdl
Michael Pavone <pavone@retrodev.com>
parents:
1621
diff
changeset
|
703 |
44d8c6e61ad4
Added new sext instruction for sign extension to CPU sdl
Michael Pavone <pavone@retrodev.com>
parents:
1621
diff
changeset
|
704 def _sext(size, src): |
44d8c6e61ad4
Added new sext instruction for sign extension to CPU sdl
Michael Pavone <pavone@retrodev.com>
parents:
1621
diff
changeset
|
705 if size == 16: |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
706 return src | 0xFF00 if src & 0x80 else src & 0x7F |
1697
44d8c6e61ad4
Added new sext instruction for sign extension to CPU sdl
Michael Pavone <pavone@retrodev.com>
parents:
1621
diff
changeset
|
707 else: |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
708 return src | 0xFFFF0000 if src & 0x8000 else src & 0x7FFF |
1697
44d8c6e61ad4
Added new sext instruction for sign extension to CPU sdl
Michael Pavone <pavone@retrodev.com>
parents:
1621
diff
changeset
|
709 |
44d8c6e61ad4
Added new sext instruction for sign extension to CPU sdl
Michael Pavone <pavone@retrodev.com>
parents:
1621
diff
changeset
|
710 def _sextCImpl(prog, params, rawParms): |
44d8c6e61ad4
Added new sext instruction for sign extension to CPU sdl
Michael Pavone <pavone@retrodev.com>
parents:
1621
diff
changeset
|
711 if params[0] == 16: |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
712 fmt = '\n\t{dst} = {src} & 0x80 ? {src} | 0xFF00 : {src} & 0x7F;' |
1697
44d8c6e61ad4
Added new sext instruction for sign extension to CPU sdl
Michael Pavone <pavone@retrodev.com>
parents:
1621
diff
changeset
|
713 else: |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
714 fmt = '\n\t{dst} = {src} & 0x8000 ? {src} | 0xFFFF0000 : {src} & 0x7FFF;' |
2468
0ca78837e4d2
Implement ext instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
2463
diff
changeset
|
715 prog.lastSize = params[0] |
1697
44d8c6e61ad4
Added new sext instruction for sign extension to CPU sdl
Michael Pavone <pavone@retrodev.com>
parents:
1621
diff
changeset
|
716 return fmt.format(src=params[1], dst=params[2]) |
1702
73ac2e59fa3f
Implemented sbc instruction in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1701
diff
changeset
|
717 |
73ac2e59fa3f
Implemented sbc instruction in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1701
diff
changeset
|
718 def _getCarryCheck(prog): |
1701
4fd34fde390c
Added adc instruction to CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1700
diff
changeset
|
719 carryFlag = None |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
720 for flag in prog.flags.flagOrder: |
1701
4fd34fde390c
Added adc instruction to CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1700
diff
changeset
|
721 if prog.flags.flagCalc[flag] == 'carry': |
4fd34fde390c
Added adc instruction to CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1700
diff
changeset
|
722 carryFlag = flag |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
723 break |
1701
4fd34fde390c
Added adc instruction to CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1700
diff
changeset
|
724 if carryFlag is None: |
4fd34fde390c
Added adc instruction to CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1700
diff
changeset
|
725 raise Exception('adc requires a defined carry flag') |
4fd34fde390c
Added adc instruction to CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1700
diff
changeset
|
726 carryStorage = prog.flags.getStorage(carryFlag) |
4fd34fde390c
Added adc instruction to CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1700
diff
changeset
|
727 if type(carryStorage) is tuple: |
4fd34fde390c
Added adc instruction to CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1700
diff
changeset
|
728 reg,bit = carryStorage |
4fd34fde390c
Added adc instruction to CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1700
diff
changeset
|
729 reg = prog.resolveReg(reg, None, (), False) |
1702
73ac2e59fa3f
Implemented sbc instruction in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1701
diff
changeset
|
730 return '({reg} & 1 << {bit})'.format(reg=reg, bit=bit) |
1701
4fd34fde390c
Added adc instruction to CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1700
diff
changeset
|
731 else: |
1702
73ac2e59fa3f
Implemented sbc instruction in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1701
diff
changeset
|
732 return prog.resolveReg(carryStorage, None, (), False) |
73ac2e59fa3f
Implemented sbc instruction in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1701
diff
changeset
|
733 |
1709
9c058ea77b7a
Implementation of carry/overflow flags for adc instructions in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1708
diff
changeset
|
734 def _adcCImpl(prog, params, rawParams, flagUpdates): |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
735 needsSizeAdjust = False |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
736 if len(params) > 3: |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
737 size = params[3] |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
738 if size == 0: |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
739 size = 8 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
740 elif size == 1: |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
741 size = 16 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
742 else: |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
743 size = 32 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
744 prog.lastSize = size |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
745 destSize = prog.paramSize(rawParams[2]) |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
746 if destSize > size: |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
747 needsSizeAdjust = True |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
748 prog.sizeAdjust = size |
1709
9c058ea77b7a
Implementation of carry/overflow flags for adc instructions in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1708
diff
changeset
|
749 needsCarry = needsOflow = needsHalf = False |
9c058ea77b7a
Implementation of carry/overflow flags for adc instructions in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1708
diff
changeset
|
750 if flagUpdates: |
9c058ea77b7a
Implementation of carry/overflow flags for adc instructions in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1708
diff
changeset
|
751 for flag in flagUpdates: |
9c058ea77b7a
Implementation of carry/overflow flags for adc instructions in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1708
diff
changeset
|
752 calc = prog.flags.flagCalc[flag] |
9c058ea77b7a
Implementation of carry/overflow flags for adc instructions in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1708
diff
changeset
|
753 if calc == 'carry': |
9c058ea77b7a
Implementation of carry/overflow flags for adc instructions in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1708
diff
changeset
|
754 needsCarry = True |
9c058ea77b7a
Implementation of carry/overflow flags for adc instructions in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1708
diff
changeset
|
755 elif calc == 'half-carry': |
9c058ea77b7a
Implementation of carry/overflow flags for adc instructions in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1708
diff
changeset
|
756 needsHalf = True |
9c058ea77b7a
Implementation of carry/overflow flags for adc instructions in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1708
diff
changeset
|
757 elif calc == 'overflow': |
9c058ea77b7a
Implementation of carry/overflow flags for adc instructions in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1708
diff
changeset
|
758 needsOflow = True |
9c058ea77b7a
Implementation of carry/overflow flags for adc instructions in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1708
diff
changeset
|
759 decl = '' |
9c058ea77b7a
Implementation of carry/overflow flags for adc instructions in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1708
diff
changeset
|
760 carryCheck = _getCarryCheck(prog) |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
761 vals = '1 : 0' |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
762 if needsCarry or needsOflow or needsHalf or (flagUpdates and needsSizeAdjust): |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
763 if len(params) <= 3: |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
764 size = prog.paramSize(rawParams[2]) |
1709
9c058ea77b7a
Implementation of carry/overflow flags for adc instructions in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1708
diff
changeset
|
765 if needsCarry: |
9c058ea77b7a
Implementation of carry/overflow flags for adc instructions in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1708
diff
changeset
|
766 size *= 2 |
9c058ea77b7a
Implementation of carry/overflow flags for adc instructions in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1708
diff
changeset
|
767 decl,name = prog.getTemp(size) |
9c058ea77b7a
Implementation of carry/overflow flags for adc instructions in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1708
diff
changeset
|
768 dst = prog.carryFlowDst = name |
9c058ea77b7a
Implementation of carry/overflow flags for adc instructions in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1708
diff
changeset
|
769 prog.lastA = params[0] |
1744
91aa789e57bd
Fixed half-carry flag calcuation for adc/sbc in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1742
diff
changeset
|
770 prog.lastB = params[1] |
1711
87d4f0b4bf1d
Actually correct overflow flag calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1710
diff
changeset
|
771 prog.lastBFlow = '(~{b})'.format(b=params[1]) |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
772 if size == 64: |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
773 params[0] = '((uint64_t){a})'.format(a=params[0]) |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
774 params[1] = '((uint64_t){b})'.format(b=params[1]) |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
775 vals = '((uint64_t)1) : ((uint64_t)0)' |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
776 elif needsSizeAdjust: |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
777 decl,name = prog.getTemp(size) |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
778 dst = params[2] |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
779 return '{decl}\n\t{tmp} = ({a} & {mask}) + ({b} & {mask}) + ({check} ? 1 : 0);\n\t{dst} = ({dst} & ~{mask}) | {tmp};'.format( |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
780 decl = decl, tmp = name, a = a, b = b, op = op, dst = dst, mask = ((1 << size) - 1), check = carryCheck |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
781 ) |
1709
9c058ea77b7a
Implementation of carry/overflow flags for adc instructions in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1708
diff
changeset
|
782 else: |
9c058ea77b7a
Implementation of carry/overflow flags for adc instructions in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1708
diff
changeset
|
783 dst = params[2] |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
784 return decl + '\n\t{dst} = {a} + {b} + ({check} ? {vals});'.format(dst = dst, |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
785 a = params[0], b = params[1], check = carryCheck, vals = vals |
1702
73ac2e59fa3f
Implemented sbc instruction in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1701
diff
changeset
|
786 ) |
73ac2e59fa3f
Implemented sbc instruction in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1701
diff
changeset
|
787 |
1710
2344b3650b38
Fix sbc and implement carry/overflow flags for it in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1709
diff
changeset
|
788 def _sbcCImpl(prog, params, rawParams, flagUpdates): |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
789 needsSizeAdjust = False |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
790 if len(params) > 3: |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
791 size = params[3] |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
792 if size == 0: |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
793 size = 8 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
794 elif size == 1: |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
795 size = 16 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
796 else: |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
797 size = 32 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
798 prog.lastSize = size |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
799 destSize = prog.paramSize(rawParams[2]) |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
800 if destSize > size: |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
801 needsSizeAdjust = True |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
802 prog.sizeAdjust = size |
1710
2344b3650b38
Fix sbc and implement carry/overflow flags for it in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1709
diff
changeset
|
803 needsCarry = needsOflow = needsHalf = False |
2344b3650b38
Fix sbc and implement carry/overflow flags for it in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1709
diff
changeset
|
804 if flagUpdates: |
2344b3650b38
Fix sbc and implement carry/overflow flags for it in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1709
diff
changeset
|
805 for flag in flagUpdates: |
2344b3650b38
Fix sbc and implement carry/overflow flags for it in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1709
diff
changeset
|
806 calc = prog.flags.flagCalc[flag] |
2344b3650b38
Fix sbc and implement carry/overflow flags for it in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1709
diff
changeset
|
807 if calc == 'carry': |
2344b3650b38
Fix sbc and implement carry/overflow flags for it in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1709
diff
changeset
|
808 needsCarry = True |
2344b3650b38
Fix sbc and implement carry/overflow flags for it in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1709
diff
changeset
|
809 elif calc == 'half-carry': |
2344b3650b38
Fix sbc and implement carry/overflow flags for it in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1709
diff
changeset
|
810 needsHalf = True |
2344b3650b38
Fix sbc and implement carry/overflow flags for it in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1709
diff
changeset
|
811 elif calc == 'overflow': |
2344b3650b38
Fix sbc and implement carry/overflow flags for it in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1709
diff
changeset
|
812 needsOflow = True |
2344b3650b38
Fix sbc and implement carry/overflow flags for it in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1709
diff
changeset
|
813 decl = '' |
2344b3650b38
Fix sbc and implement carry/overflow flags for it in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1709
diff
changeset
|
814 carryCheck = _getCarryCheck(prog) |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
815 vals = '1 : 0' |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
816 if needsCarry or needsOflow or needsHalf or (flagUpdates and needsSizeAdjust): |
1710
2344b3650b38
Fix sbc and implement carry/overflow flags for it in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1709
diff
changeset
|
817 size = prog.paramSize(rawParams[2]) |
2344b3650b38
Fix sbc and implement carry/overflow flags for it in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1709
diff
changeset
|
818 if needsCarry: |
2344b3650b38
Fix sbc and implement carry/overflow flags for it in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1709
diff
changeset
|
819 size *= 2 |
2344b3650b38
Fix sbc and implement carry/overflow flags for it in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1709
diff
changeset
|
820 decl,name = prog.getTemp(size) |
2344b3650b38
Fix sbc and implement carry/overflow flags for it in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1709
diff
changeset
|
821 dst = prog.carryFlowDst = name |
2344b3650b38
Fix sbc and implement carry/overflow flags for it in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1709
diff
changeset
|
822 prog.lastA = params[1] |
1744
91aa789e57bd
Fixed half-carry flag calcuation for adc/sbc in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1742
diff
changeset
|
823 prog.lastB = params[0] |
1711
87d4f0b4bf1d
Actually correct overflow flag calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1710
diff
changeset
|
824 prog.lastBFlow = params[0] |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
825 if size == 64: |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
826 params[1] = '((uint64_t){a})'.format(a=params[1]) |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
827 params[0] = '((uint64_t){b})'.format(b=params[0]) |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
828 vals = '((uint64_t)1) : ((uint64_t)0)' |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
829 elif needsSizeAdjust: |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
830 decl,name = prog.getTemp(size) |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
831 dst = params[2] |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
832 return '{decl}\n\t{tmp} = ({b} & {mask}) - ({a} & {mask}) - ({check} ? 1 : 0);\n\t{dst} = ({dst} & ~{mask}) | {tmp};'.format( |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
833 decl = decl, tmp = name, a = params[0], b = params[1], op = op, dst = dst, mask = ((1 << size) - 1), check = carryCheck |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
834 ) |
1710
2344b3650b38
Fix sbc and implement carry/overflow flags for it in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1709
diff
changeset
|
835 else: |
2344b3650b38
Fix sbc and implement carry/overflow flags for it in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1709
diff
changeset
|
836 dst = params[2] |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
837 return decl + '\n\t{dst} = {b} - {a} - ({check} ? {vals});'.format(dst = dst, |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
838 a = params[0], b = params[1], check=_getCarryCheck(prog), vals = vals |
1702
73ac2e59fa3f
Implemented sbc instruction in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1701
diff
changeset
|
839 ) |
1721
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
840 |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
841 def _rolCImpl(prog, params, rawParams, flagUpdates): |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
842 needsCarry = False |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
843 if flagUpdates: |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
844 for flag in flagUpdates: |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
845 calc = prog.flags.flagCalc[flag] |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
846 if calc == 'carry': |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
847 needsCarry = True |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
848 decl = '' |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
849 size = prog.paramSize(rawParams[2]) |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
850 if needsCarry: |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
851 decl,name = prog.getTemp(size * 2) |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
852 dst = prog.carryFlowDst = name |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
853 else: |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
854 dst = params[2] |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
855 return decl + '\n\t{dst} = {a} << {b} | {a} >> ({size} - {b});'.format(dst = dst, |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
856 a = params[0], b = params[1], size=size |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
857 ) |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
858 |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
859 def _rlcCImpl(prog, params, rawParams, flagUpdates): |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
860 needsCarry = False |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
861 if flagUpdates: |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
862 for flag in flagUpdates: |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
863 calc = prog.flags.flagCalc[flag] |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
864 if calc == 'carry': |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
865 needsCarry = True |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
866 decl = '' |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
867 carryCheck = _getCarryCheck(prog) |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
868 size = prog.paramSize(rawParams[2]) |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
869 if needsCarry: |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
870 decl,name = prog.getTemp(size * 2) |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
871 dst = prog.carryFlowDst = name |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
872 else: |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
873 dst = params[2] |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
874 return decl + '\n\t{dst} = {a} << {b} | {a} >> ({size} + 1 - {b}) | ({check} ? 1 : 0) << ({b} - 1);'.format(dst = dst, |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
875 a = params[0], b = params[1], size=size, check=carryCheck |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
876 ) |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
877 |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
878 def _rorCImpl(prog, params, rawParams, flagUpdates): |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
879 size = prog.paramSize(rawParams[2]) |
1722
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
880 return '\n\t{dst} = {a} >> {b} | {a} << ({size} - {b});'.format(dst = params[2], |
1721
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
881 a = params[0], b = params[1], size=size |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
882 ) |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
883 |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
884 def _rrcCImpl(prog, params, rawParams, flagUpdates): |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
885 needsCarry = False |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
886 if flagUpdates: |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
887 for flag in flagUpdates: |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
888 calc = prog.flags.flagCalc[flag] |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
889 if calc == 'carry': |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
890 needsCarry = True |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
891 decl = '' |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
892 carryCheck = _getCarryCheck(prog) |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
893 size = prog.paramSize(rawParams[2]) |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
894 if needsCarry: |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
895 decl,name = prog.getTemp(size * 2) |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
896 dst = prog.carryFlowDst = name |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
897 else: |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
898 dst = params[2] |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
899 return decl + '\n\t{dst} = {a} >> {b} | {a} << ({size} + 1 - {b}) | ({check} ? 1 : 0) << ({size}-{b});'.format(dst = dst, |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
900 a = params[0], b = params[1], size=size, check=carryCheck |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
901 ) |
1752
d6d4c006a7b3
Initial attempt at interrupts in new Z80 core and integrating it into main executable
Michael Pavone <pavone@retrodev.com>
parents:
1750
diff
changeset
|
902 |
d6d4c006a7b3
Initial attempt at interrupts in new Z80 core and integrating it into main executable
Michael Pavone <pavone@retrodev.com>
parents:
1750
diff
changeset
|
903 def _updateSyncCImpl(prog, params): |
1759
6e4faa10f9ee
Store sync_cycle in context rather than in a local in CPU DSL. Fix the timing of a number of instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1754
diff
changeset
|
904 return '\n\t{sync}(context, target_cycle);'.format(sync=prog.sync_cycle) |
1701
4fd34fde390c
Added adc instruction to CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1700
diff
changeset
|
905 |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
906 _opMap = { |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
907 'mov': Op(lambda val: val).cUnaryOperator(''), |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
908 'not': Op(lambda val: ~val).cUnaryOperator('~'), |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
909 'lnot': Op(lambda val: 0 if val else 1).cUnaryOperator('!'), |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
910 'neg': Op(lambda val: -val).cUnaryOperator('-'), |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
911 'add': Op(lambda a, b: a + b).cBinaryOperator('+'), |
1701
4fd34fde390c
Added adc instruction to CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1700
diff
changeset
|
912 'adc': Op().addImplementation('c', 2, _adcCImpl), |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
913 'sub': Op(lambda a, b: b - a).cBinaryOperator('-'), |
1702
73ac2e59fa3f
Implemented sbc instruction in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1701
diff
changeset
|
914 'sbc': Op().addImplementation('c', 2, _sbcCImpl), |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
915 'lsl': Op(lambda a, b: a << b).cBinaryOperator('<<'), |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
916 'lsr': Op(lambda a, b: a >> b).cBinaryOperator('>>'), |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
917 'asr': Op(lambda a, b: a >> b).addImplementation('c', 2, _asrCImpl), |
1721
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
918 'rol': Op().addImplementation('c', 2, _rolCImpl), |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
919 'rlc': Op().addImplementation('c', 2, _rlcCImpl), |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
920 'ror': Op().addImplementation('c', 2, _rorCImpl), |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
921 'rrc': Op().addImplementation('c', 2, _rrcCImpl), |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
922 'and': Op(lambda a, b: a & b).cBinaryOperator('&'), |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
923 'or': Op(lambda a, b: a | b).cBinaryOperator('|'), |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
924 'xor': Op(lambda a, b: a ^ b).cBinaryOperator('^'), |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
925 'abs': Op(lambda val: abs(val)).addImplementation( |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
926 'c', 1, lambda prog, params: '\n\t{dst} = abs({src});'.format(dst=params[1], src=params[0]) |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
927 ), |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
928 'cmp': Op().addImplementation('c', None, _cmpCImpl), |
1697
44d8c6e61ad4
Added new sext instruction for sign extension to CPU sdl
Michael Pavone <pavone@retrodev.com>
parents:
1621
diff
changeset
|
929 'sext': Op(_sext).addImplementation('c', 2, _sextCImpl), |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
930 'ocall': Op().addImplementation('c', None, lambda prog, params: '\n\t{pre}{fun}({args});'.format( |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
931 pre = prog.prefix, fun = params[0], args = ', '.join(['context'] + [str(p) for p in params[1:]]) |
1759
6e4faa10f9ee
Store sync_cycle in context rather than in a local in CPU DSL. Fix the timing of a number of instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1754
diff
changeset
|
932 )), |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
933 'pcall': Op().addImplementation('c', None, lambda prog, params: '\n\t(({typ}){fun})({args});'.format( |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
934 typ = params[1], fun = params[0], args = ', '.join([str(p) for p in params[2:]]) |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
935 )), |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
936 'cycles': Op().addImplementation('c', None, |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
937 lambda prog, params: '\n\tcontext->cycles += context->opts->gen.clock_divider * {0};'.format( |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
938 params[0] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
939 ) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
940 ), |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
941 'addsize': Op( |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
942 lambda a, b: b + (2 * a if a else 1) |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
943 ).addImplementation('c', 2, lambda prog, params: '\n\t{dst} = {val} + ({sz} ? {sz} * 2 : 1);'.format( |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
944 dst = params[2], sz = params[0], val = params[1] |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
945 )), |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
946 'decsize': Op( |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
947 lambda a, b: b - (2 * a if a else 1) |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
948 ).addImplementation('c', 2, lambda prog, params: '\n\t{dst} = {val} - ({sz} ? {sz} * 2 : 1);'.format( |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
949 dst = params[2], sz = params[0], val = params[1] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
950 )), |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
951 'xchg': Op().addImplementation('c', (0,1), _xchgCImpl), |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
952 'dispatch': Op().addImplementation('c', None, _dispatchCImpl), |
1752
d6d4c006a7b3
Initial attempt at interrupts in new Z80 core and integrating it into main executable
Michael Pavone <pavone@retrodev.com>
parents:
1750
diff
changeset
|
953 'update_flags': Op().addImplementation('c', None, _updateFlagsCImpl), |
d6d4c006a7b3
Initial attempt at interrupts in new Z80 core and integrating it into main executable
Michael Pavone <pavone@retrodev.com>
parents:
1750
diff
changeset
|
954 'update_sync': Op().addImplementation('c', None, _updateSyncCImpl) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
955 } |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
956 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
957 #represents a simple DSL instruction |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
958 class NormalOp: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
959 def __init__(self, parts): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
960 self.op = parts[0] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
961 self.params = parts[1:] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
962 |
1704
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
963 def generate(self, prog, parent, fieldVals, output, otype, flagUpdates): |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
964 procParams = [] |
1737
2207cd2bae14
Fixed some issues involving conditional execution and temporaries/constant folding
Michael Pavone <pavone@retrodev.com>
parents:
1735
diff
changeset
|
965 allParamsConst = flagUpdates is None and not prog.conditional |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
966 opDef = _opMap.get(self.op) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
967 for param in self.params: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
968 isDst = (not opDef is None) and len(procParams) in opDef.outOp |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
969 allowConst = (self.op in prog.subroutines or not isDst) and param in parent.regValues |
1765
7b6831305a6a
Fix calculation for whether coalesceFlags is needed for xchg instruction in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1759
diff
changeset
|
970 if isDst and self.op == 'xchg': |
7b6831305a6a
Fix calculation for whether coalesceFlags is needed for xchg instruction in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1759
diff
changeset
|
971 #xchg uses its regs as both source and destination |
7b6831305a6a
Fix calculation for whether coalesceFlags is needed for xchg instruction in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1759
diff
changeset
|
972 #we need to resolve as both so that disperse/coalesce flag stuff gets done |
7b6831305a6a
Fix calculation for whether coalesceFlags is needed for xchg instruction in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1759
diff
changeset
|
973 prog.resolveParam(param, parent, fieldVals, allowConst, False) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
974 param = prog.resolveParam(param, parent, fieldVals, allowConst, isDst) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
975 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
976 if (not type(param) is int) and len(procParams) != len(self.params) - 1: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
977 allParamsConst = False |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
978 procParams.append(param) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
979 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
980 if self.op == 'meta': |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
981 param,_,index = self.params[1].partition('.') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
982 if index: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
983 index = (parent.resolveLocal(index) or index) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
984 if index in fieldVals: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
985 index = str(fieldVals[index]) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
986 param = param + '.' + index |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
987 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
988 param = parent.resolveLocal(param) or param |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
989 if param in fieldVals: |
1991
7d4df6b74263
Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
1938
diff
changeset
|
990 param = fieldVals[param] |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
991 prog.meta[self.params[0]] = param |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
992 elif self.op == 'dis': |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
993 #TODO: Disassembler |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
994 pass |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
995 elif not opDef is None: |
1716
04cafe626118
Better error reporting when an instruction is given an insufficient number of parameters
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
996 if opDef.numParams() > len(procParams): |
04cafe626118
Better error reporting when an instruction is given an insufficient number of parameters
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
997 raise Exception('Insufficient params for ' + self.op + ' (' + ', '.join(self.params) + ')') |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
998 if opDef.canEval() and allParamsConst: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
999 #do constant folding |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1000 if opDef.numArgs() >= len(procParams): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1001 raise Exception('Insufficient args for ' + self.op + ' (' + ', '.join(self.params) + ')') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1002 dst = self.params[opDef.numArgs()] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1003 result = opDef.evaluate(procParams[:opDef.numArgs()]) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1004 while dst in prog.meta: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1005 dst = prog.meta[dst] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1006 maybeLocal = parent.resolveLocal(dst) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1007 if maybeLocal: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1008 dst = maybeLocal |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1009 parent.regValues[dst] = result |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1010 if prog.isReg(dst): |
1699
93103ad9d7f7
Fix constant propagation to a non-ephemeral destination in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1698
diff
changeset
|
1011 shortProc = (procParams[0], procParams[-1]) |
93103ad9d7f7
Fix constant propagation to a non-ephemeral destination in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1698
diff
changeset
|
1012 shortParams = (self.params[0], self.params[-1]) |
1704
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1013 output.append(_opMap['mov'].generate(otype, prog, shortProc, shortParams, None)) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1014 else: |
1704
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1015 output.append(opDef.generate(otype, prog, procParams, self.params, flagUpdates)) |
1728
b0e01e64d76d
Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1725
diff
changeset
|
1016 for dstIdx in opDef.outOp: |
b0e01e64d76d
Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1725
diff
changeset
|
1017 dst = self.params[dstIdx] |
b0e01e64d76d
Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1725
diff
changeset
|
1018 while dst in prog.meta: |
b0e01e64d76d
Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1725
diff
changeset
|
1019 dst = prog.meta[dst] |
b0e01e64d76d
Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1725
diff
changeset
|
1020 if dst in parent.regValues: |
b0e01e64d76d
Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1725
diff
changeset
|
1021 del parent.regValues[dst] |
b0e01e64d76d
Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1725
diff
changeset
|
1022 |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1023 elif self.op in prog.subroutines: |
1721
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1024 procParams = [] |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1025 for param in self.params: |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1026 begin,sep,end = param.partition('.') |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1027 if sep: |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1028 if end in fieldVals: |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1029 param = begin + '.' + str(fieldVals[end]) |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1030 else: |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1031 if param in fieldVals: |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1032 param = fieldVals[param] |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
1033 else: |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
1034 maybeLocal = parent.resolveLocal(param) |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
1035 if maybeLocal and maybeLocal in parent.regValues: |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
1036 param = parent.regValues[maybeLocal] |
1721
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1037 procParams.append(param) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1038 prog.subroutines[self.op].inline(prog, procParams, output, otype, parent) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1039 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1040 output.append('\n\t' + self.op + '(' + ', '.join([str(p) for p in procParams]) + ');') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1041 prog.lastOp = self |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1042 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1043 def __str__(self): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1044 return '\n\t' + self.op + ' ' + ' '.join(self.params) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1045 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1046 #represents a DSL switch construct |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1047 class Switch(ChildBlock): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1048 def __init__(self, parent, param): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1049 self.op = 'switch' |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1050 self.parent = parent |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1051 self.param = param |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1052 self.cases = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1053 self.regValues = None |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1054 self.current_locals = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1055 self.case_locals = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1056 self.current_case = None |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1057 self.default = None |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1058 self.default_locals = None |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1059 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1060 def addOp(self, op): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1061 if op.op == 'case': |
1619
0e8438a4c76f
Clean up warnings from -1 case
Michael Pavone <pavone@retrodev.com>
parents:
1618
diff
changeset
|
1062 val = int(op.params[0], 16) if op.params[0].startswith('0x') else int(op.params[0]) |
0e8438a4c76f
Clean up warnings from -1 case
Michael Pavone <pavone@retrodev.com>
parents:
1618
diff
changeset
|
1063 self.cases[val] = self.current_case = [] |
0e8438a4c76f
Clean up warnings from -1 case
Michael Pavone <pavone@retrodev.com>
parents:
1618
diff
changeset
|
1064 self.case_locals[val] = self.current_locals = {} |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1065 elif op.op == 'default': |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1066 self.default = self.current_case = [] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1067 self.default_locals = self.current_locals = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1068 elif self.current_case == None: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1069 raise ion('Orphan instruction in switch') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1070 elif op.op == 'local': |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1071 name = op.params[0] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1072 size = op.params[1] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1073 self.current_locals[name] = size |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1074 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1075 self.current_case.append(op) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1076 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1077 def resolveLocal(self, name): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1078 if name in self.current_locals: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1079 return name |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1080 return self.parent.resolveLocal(name) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1081 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1082 def addLocal(self, name, size): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1083 self.current_locals[name] = size |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1084 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1085 def localSize(self, name): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1086 if name in self.current_locals: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1087 return self.current_locals[name] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1088 return self.parent.localSize(name) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1089 |
1704
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1090 def generate(self, prog, parent, fieldVals, output, otype, flagUpdates): |
1618
5dbc453cd345
Getting SVP core closer to compiling
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parents:
1616
diff
changeset
|
1091 prog.pushScope(self) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1092 param = prog.resolveParam(self.param, parent, fieldVals) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1093 if type(param) is int: |
1614
c9639139aedf
Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents:
1613
diff
changeset
|
1094 self.regValues = self.parent.regValues |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
diff
changeset
|
1095 if param in self.cases: |
1618
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Getting SVP core closer to compiling
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parents:
1616
diff
changeset
|
1096 self.current_locals = self.case_locals[param] |
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Getting SVP core closer to compiling
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parents:
1616
diff
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|
1097 output.append('\n\t{') |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1098 for local in self.case_locals[param]: |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1099 output.append('\n\tuint{0}_t {1};'.format(self.case_locals[param][local], local)) |
1704
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
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parents:
1703
diff
changeset
|
1100 self.processOps(prog, fieldVals, output, otype, self.cases[param]) |
1618
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Getting SVP core closer to compiling
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parents:
1616
diff
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|
1101 output.append('\n\t}') |
1613
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
diff
changeset
|
1102 elif self.default: |
1618
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Getting SVP core closer to compiling
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1616
diff
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|
1103 self.current_locals = self.default_locals |
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Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1104 output.append('\n\t{') |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1105 for local in self.default_locals: |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1106 output.append('\n\tuint{0}_t {1};'.format(self.default[local], local)) |
1704
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1107 self.processOps(prog, fieldVals, output, otype, self.default) |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1108 output.append('\n\t}') |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1109 else: |
1737
2207cd2bae14
Fixed some issues involving conditional execution and temporaries/constant folding
Michael Pavone <pavone@retrodev.com>
parents:
1735
diff
changeset
|
1110 oldCond = prog.conditional |
2207cd2bae14
Fixed some issues involving conditional execution and temporaries/constant folding
Michael Pavone <pavone@retrodev.com>
parents:
1735
diff
changeset
|
1111 prog.conditional = True |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1112 output.append('\n\tswitch(' + param + ')') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1113 output.append('\n\t{') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1114 for case in self.cases: |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
1115 #temp = prog.temp.copy() |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1116 self.current_locals = self.case_locals[case] |
1614
c9639139aedf
Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents:
1613
diff
changeset
|
1117 self.regValues = dict(self.parent.regValues) |
1619
0e8438a4c76f
Clean up warnings from -1 case
Michael Pavone <pavone@retrodev.com>
parents:
1618
diff
changeset
|
1118 output.append('\n\tcase {0}U: '.format(case) + '{') |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1119 for local in self.case_locals[case]: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1120 output.append('\n\tuint{0}_t {1};'.format(self.case_locals[case][local], local)) |
1704
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1121 self.processOps(prog, fieldVals, output, otype, self.cases[case]) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1122 output.append('\n\tbreak;') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1123 output.append('\n\t}') |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
1124 #prog.temp = temp |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1125 if self.default: |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
1126 #temp = prog.temp.copy() |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1127 self.current_locals = self.default_locals |
1614
c9639139aedf
Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents:
1613
diff
changeset
|
1128 self.regValues = dict(self.parent.regValues) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1129 output.append('\n\tdefault: {') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1130 for local in self.default_locals: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1131 output.append('\n\tuint{0}_t {1};'.format(self.default_locals[local], local)) |
1704
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1132 self.processOps(prog, fieldVals, output, otype, self.default) |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
1133 #prog.temp = temp |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1134 output.append('\n\t}') |
1737
2207cd2bae14
Fixed some issues involving conditional execution and temporaries/constant folding
Michael Pavone <pavone@retrodev.com>
parents:
1735
diff
changeset
|
1135 prog.conditional = oldCond |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1136 prog.popScope() |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1137 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1138 def __str__(self): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1139 keys = self.cases.keys() |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1140 keys.sort() |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1141 lines = ['\n\tswitch'] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1142 for case in keys: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1143 lines.append('\n\tcase {0}'.format(case)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1144 lines.append(''.join([str(op) for op in self.cases[case]])) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1145 lines.append('\n\tend') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1146 return ''.join(lines) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1147 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1148 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1149 def _geuCImpl(prog, parent, fieldVals, output): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1150 if prog.lastOp.op == 'cmp': |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1151 output.pop() |
1616
8c78543c4783
Fix implementation cmp+condition version of if in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1615
diff
changeset
|
1152 params = [prog.resolveParam(p, parent, fieldVals) for p in prog.lastOp.params] |
8c78543c4783
Fix implementation cmp+condition version of if in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1615
diff
changeset
|
1153 return '\n\tif ({a} >= {b}) '.format(a=params[1], b = params[0]) + '{' |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1154 else: |
1733
1f0a86f5e055
Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1728
diff
changeset
|
1155 raise Exception(">=U not implemented in the general case yet") |
1f0a86f5e055
Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1728
diff
changeset
|
1156 |
1f0a86f5e055
Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1728
diff
changeset
|
1157 def _eqCImpl(prog, parent, fieldVals, output): |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
1158 if prog.lastOp.op == 'cmp': |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
1159 output.pop() |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
1160 params = [prog.resolveParam(p, parent, fieldVals) for p in prog.lastOp.params] |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
1161 return '\n\tif ({a} == {b}) '.format(a=params[1], b = params[0]) + '{' |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
1162 else: |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
1163 return '\n\tif (!{a}) {{'.format(a=prog.resolveParam(prog.lastDst, None, {})) |
1733
1f0a86f5e055
Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1728
diff
changeset
|
1164 |
1f0a86f5e055
Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1728
diff
changeset
|
1165 def _neqCImpl(prog, parent, fieldVals, output): |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
1166 return '\n\tif ({a}) {{'.format(a=prog.resolveParam(prog.lastDst, None, {})) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1167 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1168 _ifCmpImpl = { |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1169 'c': { |
1733
1f0a86f5e055
Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1728
diff
changeset
|
1170 '>=U': _geuCImpl, |
1f0a86f5e055
Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1728
diff
changeset
|
1171 '=': _eqCImpl, |
1f0a86f5e055
Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1728
diff
changeset
|
1172 '!=': _neqCImpl |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1173 } |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1174 } |
2452
8b3daed1c076
Allow more if statements to be constant folded in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
2451
diff
changeset
|
1175 _ifCmpEval = { |
8b3daed1c076
Allow more if statements to be constant folded in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
2451
diff
changeset
|
1176 '>=U': lambda a, b: a >= b, |
8b3daed1c076
Allow more if statements to be constant folded in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
2451
diff
changeset
|
1177 '=': lambda a, b: a == b, |
8b3daed1c076
Allow more if statements to be constant folded in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
2451
diff
changeset
|
1178 '!=': lambda a, b: a != b |
8b3daed1c076
Allow more if statements to be constant folded in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
2451
diff
changeset
|
1179 } |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1180 #represents a DSL conditional construct |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1181 class If(ChildBlock): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1182 def __init__(self, parent, cond): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1183 self.op = 'if' |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1184 self.parent = parent |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1185 self.cond = cond |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1186 self.body = [] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1187 self.elseBody = [] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1188 self.curBody = self.body |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1189 self.locals = {} |
1614
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Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents:
1613
diff
changeset
|
1190 self.elseLocals = {} |
c9639139aedf
Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
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parents:
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diff
changeset
|
1191 self.curLocals = self.locals |
c9639139aedf
Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
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changeset
|
1192 self.regValues = None |
1613
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1193 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1194 def addOp(self, op): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1195 if op.op in ('case', 'arg'): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1196 raise Exception(self.op + ' is not allows inside an if block') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1197 if op.op == 'local': |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1198 name = op.params[0] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1199 size = op.params[1] |
1737
2207cd2bae14
Fixed some issues involving conditional execution and temporaries/constant folding
Michael Pavone <pavone@retrodev.com>
parents:
1735
diff
changeset
|
1200 self.curLocals[name] = size |
1613
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1201 elif op.op == 'else': |
1614
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Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents:
1613
diff
changeset
|
1202 self.curLocals = self.elseLocals |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1203 self.curBody = self.elseBody |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1204 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1205 self.curBody.append(op) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1206 |
1614
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Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents:
1613
diff
changeset
|
1207 def localSize(self, name): |
c9639139aedf
Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents:
1613
diff
changeset
|
1208 return self.curLocals.get(name) |
c9639139aedf
Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
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1613
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changeset
|
1209 |
c9639139aedf
Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents:
1613
diff
changeset
|
1210 def resolveLocal(self, name): |
1737
2207cd2bae14
Fixed some issues involving conditional execution and temporaries/constant folding
Michael Pavone <pavone@retrodev.com>
parents:
1735
diff
changeset
|
1211 if name in self.curLocals: |
1614
c9639139aedf
Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents:
1613
diff
changeset
|
1212 return name |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1213 return self.parent.resolveLocal(name) |
1614
c9639139aedf
Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents:
1613
diff
changeset
|
1214 |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1215 def _genTrueBody(self, prog, fieldVals, output, otype): |
1614
c9639139aedf
Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents:
1613
diff
changeset
|
1216 self.curLocals = self.locals |
1737
2207cd2bae14
Fixed some issues involving conditional execution and temporaries/constant folding
Michael Pavone <pavone@retrodev.com>
parents:
1735
diff
changeset
|
1217 subOut = [] |
2207cd2bae14
Fixed some issues involving conditional execution and temporaries/constant folding
Michael Pavone <pavone@retrodev.com>
parents:
1735
diff
changeset
|
1218 self.processOps(prog, fieldVals, subOut, otype, self.body) |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1219 for local in self.locals: |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1220 output.append('\n\tuint{sz}_t {nm};'.format(sz=self.locals[local], nm=local)) |
1737
2207cd2bae14
Fixed some issues involving conditional execution and temporaries/constant folding
Michael Pavone <pavone@retrodev.com>
parents:
1735
diff
changeset
|
1221 output += subOut |
1614
c9639139aedf
Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents:
1613
diff
changeset
|
1222 |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1223 def _genFalseBody(self, prog, fieldVals, output, otype): |
1614
c9639139aedf
Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents:
1613
diff
changeset
|
1224 self.curLocals = self.elseLocals |
1737
2207cd2bae14
Fixed some issues involving conditional execution and temporaries/constant folding
Michael Pavone <pavone@retrodev.com>
parents:
1735
diff
changeset
|
1225 subOut = [] |
2207cd2bae14
Fixed some issues involving conditional execution and temporaries/constant folding
Michael Pavone <pavone@retrodev.com>
parents:
1735
diff
changeset
|
1226 self.processOps(prog, fieldVals, subOut, otype, self.elseBody) |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1227 for local in self.elseLocals: |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1228 output.append('\n\tuint{sz}_t {nm};'.format(sz=self.elseLocals[local], nm=local)) |
1737
2207cd2bae14
Fixed some issues involving conditional execution and temporaries/constant folding
Michael Pavone <pavone@retrodev.com>
parents:
1735
diff
changeset
|
1229 output += subOut |
1614
c9639139aedf
Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents:
1613
diff
changeset
|
1230 |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1231 def _genConstParam(self, param, prog, fieldVals, output, otype): |
1614
c9639139aedf
Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents:
1613
diff
changeset
|
1232 if param: |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1233 self._genTrueBody(prog, fieldVals, output, otype) |
1614
c9639139aedf
Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents:
1613
diff
changeset
|
1234 else: |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1235 self._genFalseBody(prog, fieldVals, output, otype) |
1614
c9639139aedf
Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents:
1613
diff
changeset
|
1236 |
1704
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1237 def generate(self, prog, parent, fieldVals, output, otype, flagUpdates): |
1614
c9639139aedf
Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents:
1613
diff
changeset
|
1238 self.regValues = parent.regValues |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
1239 if self.cond in prog.booleans: |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1240 self._genConstParam(prog.checkBool(self.cond), prog, fieldVals, output, otype) |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
1241 else: |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1242 if self.cond in _ifCmpImpl[otype]: |
2452
8b3daed1c076
Allow more if statements to be constant folded in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
2451
diff
changeset
|
1243 if prog.lastOp.op == 'cmp': |
8b3daed1c076
Allow more if statements to be constant folded in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
2451
diff
changeset
|
1244 params = [prog.resolveParam(p, parent, fieldVals) for p in prog.lastOp.params] |
8b3daed1c076
Allow more if statements to be constant folded in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
2451
diff
changeset
|
1245 if type(params[0]) is int and type(params[1]) is int: |
8b3daed1c076
Allow more if statements to be constant folded in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
2451
diff
changeset
|
1246 output.pop() |
8b3daed1c076
Allow more if statements to be constant folded in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
2451
diff
changeset
|
1247 res = _ifCmpEval[self.cond](params[1], params[0]) |
8b3daed1c076
Allow more if statements to be constant folded in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
2451
diff
changeset
|
1248 self._genConstParam(res, prog, fieldVals, output, otype) |
8b3daed1c076
Allow more if statements to be constant folded in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
2451
diff
changeset
|
1249 return |
1737
2207cd2bae14
Fixed some issues involving conditional execution and temporaries/constant folding
Michael Pavone <pavone@retrodev.com>
parents:
1735
diff
changeset
|
1250 oldCond = prog.conditional |
2207cd2bae14
Fixed some issues involving conditional execution and temporaries/constant folding
Michael Pavone <pavone@retrodev.com>
parents:
1735
diff
changeset
|
1251 prog.conditional = True |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
1252 #temp = prog.temp.copy() |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1253 output.append(_ifCmpImpl[otype][self.cond](prog, parent, fieldVals, output)) |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1254 self._genTrueBody(prog, fieldVals, output, otype) |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
1255 #prog.temp = temp |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1256 if self.elseBody: |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
1257 #temp = prog.temp.copy() |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1258 output.append('\n\t} else {') |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1259 self._genFalseBody(prog, fieldVals, output, otype) |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
1260 #prog.temp = temp |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1261 output.append('\n\t}') |
1737
2207cd2bae14
Fixed some issues involving conditional execution and temporaries/constant folding
Michael Pavone <pavone@retrodev.com>
parents:
1735
diff
changeset
|
1262 prog.conditional = oldCond |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1263 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1264 cond = prog.resolveParam(self.cond, parent, fieldVals) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1265 if type(cond) is int: |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1266 self._genConstParam(cond, prog, fieldVals, output, otype) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1267 else: |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
1268 #temp = prog.temp.copy() |
1614
c9639139aedf
Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents:
1613
diff
changeset
|
1269 output.append('\n\tif ({cond}) '.format(cond=cond) + '{') |
1737
2207cd2bae14
Fixed some issues involving conditional execution and temporaries/constant folding
Michael Pavone <pavone@retrodev.com>
parents:
1735
diff
changeset
|
1270 oldCond = prog.conditional |
2207cd2bae14
Fixed some issues involving conditional execution and temporaries/constant folding
Michael Pavone <pavone@retrodev.com>
parents:
1735
diff
changeset
|
1271 prog.conditional = True |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1272 self._genTrueBody(prog, fieldVals, output, otype) |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
1273 #prog.temp = temp |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1274 if self.elseBody: |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
1275 #temp = prog.temp.copy() |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1276 output.append('\n\t} else {') |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1277 self._genFalseBody(prog, fieldVals, output, otype) |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
1278 #prog.temp = temp |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1279 output.append('\n\t}') |
1737
2207cd2bae14
Fixed some issues involving conditional execution and temporaries/constant folding
Michael Pavone <pavone@retrodev.com>
parents:
1735
diff
changeset
|
1280 prog.conditional = oldCond |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1281 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1282 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1283 def __str__(self): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1284 lines = ['\n\tif'] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1285 for op in self.body: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1286 lines.append(str(op)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1287 lines.append('\n\tend') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1288 return ''.join(lines) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1289 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1290 class Registers: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1291 def __init__(self): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1292 self.regs = {} |
1621
ca158bc091f9
Implement program ROM reads
Michael Pavone <pavone@retrodev.com>
parents:
1620
diff
changeset
|
1293 self.pointers = {} |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1294 self.regArrays = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1295 self.regToArray = {} |
1752
d6d4c006a7b3
Initial attempt at interrupts in new Z80 core and integrating it into main executable
Michael Pavone <pavone@retrodev.com>
parents:
1750
diff
changeset
|
1296 self.addReg('cycles', 32) |
1759
6e4faa10f9ee
Store sync_cycle in context rather than in a local in CPU DSL. Fix the timing of a number of instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1754
diff
changeset
|
1297 self.addReg('sync_cycle', 32) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1298 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1299 def addReg(self, name, size): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1300 self.regs[name] = size |
1621
ca158bc091f9
Implement program ROM reads
Michael Pavone <pavone@retrodev.com>
parents:
1620
diff
changeset
|
1301 |
1750
01236179fc71
Optimization to memory access in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1749
diff
changeset
|
1302 def addPointer(self, name, size, count): |
01236179fc71
Optimization to memory access in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1749
diff
changeset
|
1303 self.pointers[name] = (size, count) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1304 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1305 def addRegArray(self, name, size, regs): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1306 self.regArrays[name] = (size, regs) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1307 idx = 0 |
1615
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
1308 if not type(regs) is int: |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
1309 for reg in regs: |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
1310 self.regs[reg] = size |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
1311 self.regToArray[reg] = (name, idx) |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
1312 idx += 1 |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1313 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1314 def isReg(self, name): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1315 return name in self.regs |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1316 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1317 def isRegArray(self, name): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1318 return name in self.regArrays |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1319 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1320 def isRegArrayMember(self, name): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1321 return name in self.regToArray |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1322 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1323 def arrayMemberParent(self, name): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1324 return self.regToArray[name][0] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1325 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1326 def arrayMemberIndex(self, name): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1327 return self.regToArray[name][1] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1328 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1329 def arrayMemberName(self, array, index): |
1615
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
1330 if type(index) is int and not type(self.regArrays[array][1]) is int: |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1331 return self.regArrays[array][1][index] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1332 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1333 return None |
1615
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
1334 |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
1335 def isNamedArray(self, array): |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
1336 return array in self.regArrays and type(self.regArrays[array][1]) is int |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1337 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1338 def processLine(self, parts): |
1615
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
1339 if len(parts) == 3: |
1750
01236179fc71
Optimization to memory access in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1749
diff
changeset
|
1340 if parts[1].startswith('ptr'): |
01236179fc71
Optimization to memory access in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1749
diff
changeset
|
1341 self.addPointer(parts[0], parts[1][3:], int(parts[2])) |
01236179fc71
Optimization to memory access in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1749
diff
changeset
|
1342 else: |
01236179fc71
Optimization to memory access in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1749
diff
changeset
|
1343 self.addRegArray(parts[0], int(parts[1]), int(parts[2])) |
1615
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
1344 elif len(parts) > 2: |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1345 self.addRegArray(parts[0], int(parts[1]), parts[2:]) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1346 else: |
1621
ca158bc091f9
Implement program ROM reads
Michael Pavone <pavone@retrodev.com>
parents:
1620
diff
changeset
|
1347 if parts[1].startswith('ptr'): |
1750
01236179fc71
Optimization to memory access in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1749
diff
changeset
|
1348 self.addPointer(parts[0], parts[1][3:], 1) |
1621
ca158bc091f9
Implement program ROM reads
Michael Pavone <pavone@retrodev.com>
parents:
1620
diff
changeset
|
1349 else: |
ca158bc091f9
Implement program ROM reads
Michael Pavone <pavone@retrodev.com>
parents:
1620
diff
changeset
|
1350 self.addReg(parts[0], int(parts[1])) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1351 return self |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1352 |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1353 def writeHeader(self, otype, hFile): |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1354 fieldList = [] |
1621
ca158bc091f9
Implement program ROM reads
Michael Pavone <pavone@retrodev.com>
parents:
1620
diff
changeset
|
1355 for pointer in self.pointers: |
1735
ca2336469397
Get new Z80 core running in CPM harness
Michael Pavone <pavone@retrodev.com>
parents:
1734
diff
changeset
|
1356 stars = '*' |
1750
01236179fc71
Optimization to memory access in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1749
diff
changeset
|
1357 ptype, count = self.pointers[pointer] |
1735
ca2336469397
Get new Z80 core running in CPM harness
Michael Pavone <pavone@retrodev.com>
parents:
1734
diff
changeset
|
1358 while ptype.startswith('ptr'): |
ca2336469397
Get new Z80 core running in CPM harness
Michael Pavone <pavone@retrodev.com>
parents:
1734
diff
changeset
|
1359 stars += '*' |
ca2336469397
Get new Z80 core running in CPM harness
Michael Pavone <pavone@retrodev.com>
parents:
1734
diff
changeset
|
1360 ptype = ptype[3:] |
ca2336469397
Get new Z80 core running in CPM harness
Michael Pavone <pavone@retrodev.com>
parents:
1734
diff
changeset
|
1361 if ptype.isdigit(): |
ca2336469397
Get new Z80 core running in CPM harness
Michael Pavone <pavone@retrodev.com>
parents:
1734
diff
changeset
|
1362 ptype = 'uint{sz}_t'.format(sz=ptype) |
1750
01236179fc71
Optimization to memory access in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1749
diff
changeset
|
1363 if count > 1: |
01236179fc71
Optimization to memory access in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1749
diff
changeset
|
1364 arr = '[{n}]'.format(n=count) |
01236179fc71
Optimization to memory access in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1749
diff
changeset
|
1365 else: |
01236179fc71
Optimization to memory access in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1749
diff
changeset
|
1366 arr = '' |
01236179fc71
Optimization to memory access in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1749
diff
changeset
|
1367 hFile.write('\n\t{ptype} {stars}{nm}{arr};'.format(nm=pointer, ptype=ptype, stars=stars, arr=arr)) |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1368 for reg in self.regs: |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1369 if not self.isRegArrayMember(reg): |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1370 fieldList.append((self.regs[reg], 1, reg)) |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1371 for arr in self.regArrays: |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1372 size,regs = self.regArrays[arr] |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1373 if not type(regs) is int: |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1374 regs = len(regs) |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1375 fieldList.append((size, regs, arr)) |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1376 fieldList.sort() |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1377 fieldList.reverse() |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1378 for size, count, name in fieldList: |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1379 if count > 1: |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1380 hFile.write('\n\tuint{sz}_t {nm}[{ct}];'.format(sz=size, nm=name, ct=count)) |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1381 else: |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1382 hFile.write('\n\tuint{sz}_t {nm};'.format(sz=size, nm=name)) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1383 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1384 class Flags: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1385 def __init__(self): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1386 self.flagBits = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1387 self.flagCalc = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1388 self.flagStorage = {} |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
1389 self.flagOrder = [] |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1390 self.flagReg = None |
1747
89ddf41a50bb
Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1745
diff
changeset
|
1391 self.storageToFlags = {} |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1392 self.maxBit = -1 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1393 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1394 def processLine(self, parts): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1395 if parts[0] == 'register': |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1396 self.flagReg = parts[1] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1397 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1398 flag,bit,calc,storage = parts |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1399 bit,_,top = bit.partition('-') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1400 bit = int(bit) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1401 if top: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1402 top = int(bit) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1403 if top > self.maxBit: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1404 self.maxBit = top |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1405 self.flagBits[flag] = (bit,top) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1406 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1407 if bit > self.maxBit: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1408 self.maxBit = bit |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1409 self.flagBits[flag] = bit |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1410 self.flagCalc[flag] = calc |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1411 self.flagStorage[flag] = storage |
1747
89ddf41a50bb
Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1745
diff
changeset
|
1412 storage,_,storebit = storage.partition('.') |
89ddf41a50bb
Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1745
diff
changeset
|
1413 self.storageToFlags.setdefault(storage, []).append((storebit, flag)) |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
1414 self.flagOrder.append(flag) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1415 return self |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1416 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1417 def getStorage(self, flag): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1418 if not flag in self.flagStorage: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1419 raise Exception('Undefined flag ' + flag) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1420 loc,_,bit = self.flagStorage[flag].partition('.') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1421 if bit: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1422 return (loc, int(bit)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1423 else: |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1424 return loc |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1425 |
1704
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1426 def parseFlagUpdate(self, flagString): |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1427 last = '' |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1428 autoUpdate = set() |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1429 explicit = {} |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1430 for c in flagString: |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1431 if c.isdigit(): |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1432 if last.isalpha(): |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1433 num = int(c) |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1434 if num > 1: |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1435 raise Exception(c + ' is not a valid digit for update_flags') |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1436 explicit[last] = num |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1437 last = c |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1438 else: |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1439 raise Exception('Digit must follow flag letter in update_flags') |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1440 else: |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1441 if last.isalpha(): |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1442 autoUpdate.add(last) |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1443 last = c |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1444 if last.isalpha(): |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1445 autoUpdate.add(last) |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1446 return (autoUpdate, explicit) |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1447 |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1448 def disperseFlags(self, prog, otype): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1449 bitToFlag = [None] * (self.maxBit+1) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1450 src = prog.resolveReg(self.flagReg, None, {}) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1451 output = [] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1452 for flag in self.flagBits: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1453 bit = self.flagBits[flag] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1454 if type(bit) is tuple: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1455 bot,top = bit |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1456 mask = ((1 << (top + 1 - bot)) - 1) << bot |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1457 output.append('\n\t{dst} = {src} & mask;'.format( |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1458 dst=prog.resolveReg(self.flagStorage[flag], None, {}), src=src, mask=mask |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1459 )) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1460 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1461 bitToFlag[self.flagBits[flag]] = flag |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1462 multi = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1463 for bit in range(len(bitToFlag)-1,-1,-1): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1464 flag = bitToFlag[bit] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1465 if not flag is None: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1466 field,_,dstbit = self.flagStorage[flag].partition('.') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1467 dst = prog.resolveReg(field, None, {}) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1468 if dstbit: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1469 dstbit = int(dstbit) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1470 multi.setdefault(dst, []).append((dstbit, bit)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1471 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1472 output.append('\n\t{dst} = {src} & {mask};'.format(dst=dst, src=src, mask=(1 << bit))) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1473 for dst in multi: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1474 didClear = False |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1475 direct = [] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1476 for dstbit, bit in multi[dst]: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1477 if dstbit == bit: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1478 direct.append(bit) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1479 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1480 if not didClear: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1481 output.append('\n\t{dst} = 0;'.format(dst=dst)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1482 didClear = True |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1483 if dstbit > bit: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1484 shift = '<<' |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1485 diff = dstbit - bit |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1486 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1487 shift = '>>' |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1488 diff = bit - dstbit |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1489 output.append('\n\t{dst} |= {src} {shift} {diff} & {mask};'.format( |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1490 src=src, dst=dst, shift=shift, diff=diff, mask=(1 << dstbit) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1491 )) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1492 if direct: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1493 if len(direct) == len(multi[dst]): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1494 output.append('\n\t{dst} = {src};'.format(dst=dst, src=src)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1495 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1496 mask = 0 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1497 for bit in direct: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1498 mask = mask | (1 << bit) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1499 output.append('\n\t{dst} = {src} & {mask};'.format(dst=dst, src=src, mask=mask)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1500 return ''.join(output) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1501 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1502 def coalesceFlags(self, prog, otype): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1503 dst = prog.resolveReg(self.flagReg, None, {}) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1504 output = ['\n\t{dst} = 0;'.format(dst=dst)] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1505 bitToFlag = [None] * (self.maxBit+1) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1506 for flag in self.flagBits: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1507 bit = self.flagBits[flag] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1508 if type(bit) is tuple: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1509 bot,_ = bit |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1510 src = prog.resolveReg(self.flagStorage[flag], None, {}) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1511 if bot: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1512 output.append('\n\t{dst} |= {src} << {shift};'.format( |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1513 dst=dst, src = src, shift = bot |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1514 )) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1515 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1516 output.append('\n\t{dst} |= {src};'.format( |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1517 dst=dst, src = src |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1518 )) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1519 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1520 bitToFlag[bit] = flag |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1521 multi = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1522 for bit in range(len(bitToFlag)-1,-1,-1): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1523 flag = bitToFlag[bit] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1524 if not flag is None: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1525 field,_,srcbit = self.flagStorage[flag].partition('.') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1526 src = prog.resolveReg(field, None, {}) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1527 if srcbit: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1528 srcbit = int(srcbit) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1529 multi.setdefault(src, []).append((srcbit,bit)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1530 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1531 output.append('\n\tif ({src}) {{\n\t\t{dst} |= 1 << {bit};\n\t}}'.format( |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1532 dst=dst, src=src, bit=bit |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1533 )) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1534 for src in multi: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1535 direct = 0 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1536 for srcbit, dstbit in multi[src]: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1537 if srcbit == dstbit: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1538 direct = direct | (1 << srcbit) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1539 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1540 output.append('\n\tif ({src} & (1 << {srcbit})) {{\n\t\t{dst} |= 1 << {dstbit};\n\t}}'.format( |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1541 src=src, dst=dst, srcbit=srcbit, dstbit=dstbit |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1542 )) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1543 if direct: |
1698
90272218469c
Fixed missing semicolon in coalesceFlags
Michael Pavone <pavone@retrodev.com>
parents:
1697
diff
changeset
|
1544 output.append('\n\t{dst} |= {src} & {mask};'.format( |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1545 dst=dst, src=src, mask=direct |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1546 )) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1547 return ''.join(output) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1548 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1549 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1550 class Program: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1551 def __init__(self, regs, instructions, subs, info, flags): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1552 self.regs = regs |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1553 self.instructions = instructions |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1554 self.subroutines = subs |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1555 self.meta = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1556 self.booleans = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1557 self.prefix = info.get('prefix', [''])[0] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1558 self.opsize = int(info.get('opcode_size', ['8'])[0]) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1559 self.extra_tables = info.get('extra_tables', []) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1560 self.context_type = self.prefix + 'context' |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1561 self.body = info.get('body', [None])[0] |
1752
d6d4c006a7b3
Initial attempt at interrupts in new Z80 core and integrating it into main executable
Michael Pavone <pavone@retrodev.com>
parents:
1750
diff
changeset
|
1562 self.interrupt = info.get('interrupt', [None])[0] |
d6d4c006a7b3
Initial attempt at interrupts in new Z80 core and integrating it into main executable
Michael Pavone <pavone@retrodev.com>
parents:
1750
diff
changeset
|
1563 self.sync_cycle = info.get('sync_cycle', [None])[0] |
1620
a172f97d873f
Add the ability for a CPU definition to reference arbitrary C includes and use it to add a placeholder definition of svp_read_16
Michael Pavone <pavone@retrodev.com>
parents:
1619
diff
changeset
|
1564 self.includes = info.get('include', []) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1565 self.flags = flags |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1566 self.lastDst = None |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1567 self.scopes = [] |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1568 self.currentScope = None |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1569 self.lastOp = None |
1704
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1570 self.carryFlowDst = None |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1571 self.lastA = None |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1572 self.lastB = None |
1708
5bfed2eedc9d
Fixed flag calculation for sub instructions in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1707
diff
changeset
|
1573 self.lastBFlow = None |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
1574 self.sizeAdjust = None |
1737
2207cd2bae14
Fixed some issues involving conditional execution and temporaries/constant folding
Michael Pavone <pavone@retrodev.com>
parents:
1735
diff
changeset
|
1575 self.conditional = False |
1748
48a43dff4dc0
Added init functions to z80_util.c so new Z80 core is closer to a drop in replacement for the old one
Michael Pavone <pavone@retrodev.com>
parents:
1747
diff
changeset
|
1576 self.declares = [] |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
1577 self.lastSize = None |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1578 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1579 def __str__(self): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1580 pieces = [] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1581 for reg in self.regs: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1582 pieces.append(str(self.regs[reg])) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1583 for name in self.subroutines: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1584 pieces.append('\n'+str(self.subroutines[name])) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1585 for instruction in self.instructions: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1586 pieces.append('\n'+str(instruction)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1587 return ''.join(pieces) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1588 |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1589 def writeHeader(self, otype, header): |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1590 hFile = open(header, 'w') |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1591 macro = header.upper().replace('.', '_') |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1592 hFile.write('#ifndef {0}_'.format(macro)) |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1593 hFile.write('\n#define {0}_'.format(macro)) |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1594 hFile.write('\n#include "backend.h"') |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1595 hFile.write('\n\ntypedef struct {') |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1596 hFile.write('\n\tcpu_options gen;') |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1597 hFile.write('\n}} {0}options;'.format(self.prefix)) |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1598 hFile.write('\n\ntypedef struct {') |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1599 hFile.write('\n\t{0}options *opts;'.format(self.prefix)) |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1600 self.regs.writeHeader(otype, hFile) |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1601 hFile.write('\n}} {0}context;'.format(self.prefix)) |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1602 hFile.write('\n') |
1703
49a52c737bf0
Fix zero flag calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1702
diff
changeset
|
1603 hFile.write('\nvoid {pre}execute({type} *context, uint32_t target_cycle);'.format(pre = self.prefix, type = self.context_type)) |
1748
48a43dff4dc0
Added init functions to z80_util.c so new Z80 core is closer to a drop in replacement for the old one
Michael Pavone <pavone@retrodev.com>
parents:
1747
diff
changeset
|
1604 for decl in self.declares: |
48a43dff4dc0
Added init functions to z80_util.c so new Z80 core is closer to a drop in replacement for the old one
Michael Pavone <pavone@retrodev.com>
parents:
1747
diff
changeset
|
1605 hFile.write('\n' + decl) |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1606 hFile.write('\n#endif //{0}_'.format(macro)) |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1607 hFile.write('\n') |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1608 hFile.close() |
1700
e4b4e21a37fa
Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
1699
diff
changeset
|
1609 |
1749
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1610 def _buildTable(self, otype, table, body, lateBody): |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1611 pieces = [] |
1700
e4b4e21a37fa
Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
1699
diff
changeset
|
1612 opmap = [None] * (1 << self.opsize) |
e4b4e21a37fa
Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
1699
diff
changeset
|
1613 bodymap = {} |
e4b4e21a37fa
Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
1699
diff
changeset
|
1614 if table in self.instructions: |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1615 instructions = self.instructions[table] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1616 instructions.sort() |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1617 for inst in instructions: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1618 for val in inst.allValues(): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1619 if opmap[val] is None: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1620 self.meta = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1621 self.temp = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1622 self.needFlagCoalesce = False |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1623 self.needFlagDisperse = False |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1624 self.lastOp = None |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1625 opmap[val] = inst.generateName(val) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1626 bodymap[val] = inst.generateBody(val, self, otype) |
1700
e4b4e21a37fa
Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
1699
diff
changeset
|
1627 |
1749
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1628 if self.dispatch == 'call': |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1629 pieces.append('\nstatic impl_fun impl_{name}[{sz}] = {{'.format(name = table, sz=len(opmap))) |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1630 for inst in range(0, len(opmap)): |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1631 op = opmap[inst] |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1632 if op is None: |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1633 pieces.append('\n\tunimplemented,') |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1634 else: |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1635 pieces.append('\n\t' + op + ',') |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1636 body.append(bodymap[inst]) |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1637 pieces.append('\n};') |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1638 elif self.dispatch == 'goto': |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1639 body.append('\n\tstatic void *impl_{name}[{sz}] = {{'.format(name = table, sz=len(opmap))) |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1640 for inst in range(0, len(opmap)): |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1641 op = opmap[inst] |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1642 if op is None: |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1643 body.append('\n\t\t&&unimplemented,') |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1644 else: |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1645 body.append('\n\t\t&&' + op + ',') |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1646 lateBody.append(bodymap[inst]) |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1647 body.append('\n\t};') |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1648 else: |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1649 raise Exception("unimplmeneted dispatch type " + self.dispatch) |
1700
e4b4e21a37fa
Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
1699
diff
changeset
|
1650 body.extend(pieces) |
1749
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1651 |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1652 def nextInstruction(self, otype): |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1653 output = [] |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1654 if self.dispatch == 'goto': |
1752
d6d4c006a7b3
Initial attempt at interrupts in new Z80 core and integrating it into main executable
Michael Pavone <pavone@retrodev.com>
parents:
1750
diff
changeset
|
1655 if self.interrupt in self.subroutines: |
1759
6e4faa10f9ee
Store sync_cycle in context rather than in a local in CPU DSL. Fix the timing of a number of instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1754
diff
changeset
|
1656 output.append('\n\tif (context->cycles >= context->sync_cycle) {') |
1749
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1657 output.append('\n\tif (context->cycles >= target_cycle) { return; }') |
1752
d6d4c006a7b3
Initial attempt at interrupts in new Z80 core and integrating it into main executable
Michael Pavone <pavone@retrodev.com>
parents:
1750
diff
changeset
|
1658 if self.interrupt in self.subroutines: |
d6d4c006a7b3
Initial attempt at interrupts in new Z80 core and integrating it into main executable
Michael Pavone <pavone@retrodev.com>
parents:
1750
diff
changeset
|
1659 self.meta = {} |
d6d4c006a7b3
Initial attempt at interrupts in new Z80 core and integrating it into main executable
Michael Pavone <pavone@retrodev.com>
parents:
1750
diff
changeset
|
1660 self.temp = {} |
d6d4c006a7b3
Initial attempt at interrupts in new Z80 core and integrating it into main executable
Michael Pavone <pavone@retrodev.com>
parents:
1750
diff
changeset
|
1661 self.subroutines[self.interrupt].inline(self, [], output, otype, None) |
d6d4c006a7b3
Initial attempt at interrupts in new Z80 core and integrating it into main executable
Michael Pavone <pavone@retrodev.com>
parents:
1750
diff
changeset
|
1662 output.append('\n\t}') |
d6d4c006a7b3
Initial attempt at interrupts in new Z80 core and integrating it into main executable
Michael Pavone <pavone@retrodev.com>
parents:
1750
diff
changeset
|
1663 |
1749
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1664 self.meta = {} |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1665 self.temp = {} |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1666 self.subroutines[self.body].inline(self, [], output, otype, None) |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1667 return output |
1700
e4b4e21a37fa
Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
1699
diff
changeset
|
1668 |
e4b4e21a37fa
Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
1699
diff
changeset
|
1669 def build(self, otype): |
e4b4e21a37fa
Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
1699
diff
changeset
|
1670 body = [] |
e4b4e21a37fa
Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
1699
diff
changeset
|
1671 pieces = [] |
e4b4e21a37fa
Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
1699
diff
changeset
|
1672 for include in self.includes: |
e4b4e21a37fa
Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
1699
diff
changeset
|
1673 body.append('#include "{0}"\n'.format(include)) |
1749
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1674 if self.dispatch == 'call': |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
1675 body.append('\nstatic void unimplemented({pre}context *context, uint32_t target_cycle)'.format(pre = self.prefix)) |
1749
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1676 body.append('\n{') |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1677 body.append('\n\tfatal_error("Unimplemented instruction\\n");') |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1678 body.append('\n}\n') |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
1679 body.append('\ntypedef void (*impl_fun)({pre}context *context, uint32_t target_cycle);'.format(pre=self.prefix)) |
1749
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1680 for table in self.extra_tables: |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1681 body.append('\nstatic impl_fun impl_{name}[{sz}];'.format(name = table, sz=(1 << self.opsize))) |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1682 body.append('\nstatic impl_fun impl_main[{sz}];'.format(sz=(1 << self.opsize))) |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1683 elif self.dispatch == 'goto': |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1684 body.append('\nvoid {pre}execute({type} *context, uint32_t target_cycle)'.format(pre = self.prefix, type = self.context_type)) |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1685 body.append('\n{') |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1686 |
1740
28ab56ff8cea
Implement DD/FD prefixes for instructions that don't reference HL
Michael Pavone <pavone@retrodev.com>
parents:
1737
diff
changeset
|
1687 for table in self.extra_tables: |
1749
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1688 self._buildTable(otype, table, body, pieces) |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1689 self._buildTable(otype, 'main', body, pieces) |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1690 if self.dispatch == 'call' and self.body in self.subroutines: |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1691 pieces.append('\nvoid {pre}execute({type} *context, uint32_t target_cycle)'.format(pre = self.prefix, type = self.context_type)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1692 pieces.append('\n{') |
1759
6e4faa10f9ee
Store sync_cycle in context rather than in a local in CPU DSL. Fix the timing of a number of instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1754
diff
changeset
|
1693 pieces.append('\n\t{sync}(context, target_cycle);'.format(sync=self.sync_cycle)) |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1694 pieces.append('\n\twhile (context->cycles < target_cycle)') |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1695 pieces.append('\n\t{') |
1883
9ab5184811ea
Implement interrupts in call dispatch mode in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1838
diff
changeset
|
1696 if self.interrupt in self.subroutines: |
9ab5184811ea
Implement interrupts in call dispatch mode in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1838
diff
changeset
|
1697 pieces.append('\n\t\tif (context->cycles >= context->sync_cycle) {') |
9ab5184811ea
Implement interrupts in call dispatch mode in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1838
diff
changeset
|
1698 self.meta = {} |
9ab5184811ea
Implement interrupts in call dispatch mode in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1838
diff
changeset
|
1699 self.temp = {} |
1938
1dae90605199
Fix autogenerated temp variables in interrupt subroutine in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1883
diff
changeset
|
1700 intpieces = [] |
1dae90605199
Fix autogenerated temp variables in interrupt subroutine in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1883
diff
changeset
|
1701 self.subroutines[self.interrupt].inline(self, [], intpieces, otype, None) |
1dae90605199
Fix autogenerated temp variables in interrupt subroutine in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1883
diff
changeset
|
1702 for size in self.temp: |
1dae90605199
Fix autogenerated temp variables in interrupt subroutine in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1883
diff
changeset
|
1703 pieces.append('\n\tuint{sz}_t gen_tmp{sz}__;'.format(sz=size)) |
1dae90605199
Fix autogenerated temp variables in interrupt subroutine in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1883
diff
changeset
|
1704 pieces += intpieces |
1883
9ab5184811ea
Implement interrupts in call dispatch mode in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1838
diff
changeset
|
1705 pieces.append('\n\t\t}') |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1706 self.meta = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1707 self.temp = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1708 self.subroutines[self.body].inline(self, [], pieces, otype, None) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1709 pieces.append('\n\t}') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1710 pieces.append('\n}') |
1749
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1711 elif self.dispatch == 'goto': |
1759
6e4faa10f9ee
Store sync_cycle in context rather than in a local in CPU DSL. Fix the timing of a number of instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1754
diff
changeset
|
1712 body.append('\n\t{sync}(context, target_cycle);'.format(sync=self.sync_cycle)) |
1749
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1713 body += self.nextInstruction(otype) |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1714 pieces.append('\nunimplemented:') |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1715 pieces.append('\n\tfatal_error("Unimplemented instruction\\n");') |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1716 pieces.append('\n}') |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1717 return ''.join(body) + ''.join(pieces) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1718 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1719 def checkBool(self, name): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1720 if not name in self.booleans: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1721 raise Exception(name + ' is not a defined boolean flag') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1722 return self.booleans[name] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1723 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1724 def getTemp(self, size): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1725 if size in self.temp: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1726 return ('', self.temp[size]) |
1742
6290c88949bd
Fixed CPI/CPD/CPIR/CPDR in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1740
diff
changeset
|
1727 self.temp[size] = 'gen_tmp{sz}__'.format(sz=size); |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
1728 return ('', self.temp[size]) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1729 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1730 def resolveParam(self, param, parent, fieldVals, allowConstant=True, isdst=False): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1731 keepGoing = True |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1732 while keepGoing: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1733 keepGoing = False |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1734 try: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1735 if type(param) is int: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1736 pass |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1737 elif param.startswith('0x'): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1738 param = int(param, 16) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1739 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1740 param = int(param) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1741 except ValueError: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1742 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1743 if parent: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1744 if param in parent.regValues and allowConstant: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1745 return parent.regValues[param] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1746 maybeLocal = parent.resolveLocal(param) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1747 if maybeLocal: |
1715
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1713
diff
changeset
|
1748 if isdst: |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1713
diff
changeset
|
1749 self.lastDst = param |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
1750 self.lastSize = None |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1751 return maybeLocal |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1752 if param in fieldVals: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1753 param = fieldVals[param] |
1721
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1754 fieldVals = {} |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1755 keepGoing = True |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1756 elif param in self.meta: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1757 param = self.meta[param] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1758 keepGoing = True |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1759 elif self.isReg(param): |
1715
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1713
diff
changeset
|
1760 return self.resolveReg(param, parent, fieldVals, isdst) |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
1761 elif param in self.regs.pointers: |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
1762 return 'context->' + param |
1715
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1713
diff
changeset
|
1763 if isdst: |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1713
diff
changeset
|
1764 self.lastDst = param |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
1765 self.lastSize = None |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1766 return param |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1767 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1768 def isReg(self, name): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1769 if not type(name) is str: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1770 return False |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1771 begin,sep,_ = name.partition('.') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1772 if sep: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1773 if begin in self.meta: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1774 begin = self.meta[begin] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1775 return self.regs.isRegArray(begin) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1776 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1777 return self.regs.isReg(name) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1778 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1779 def resolveReg(self, name, parent, fieldVals, isDst=False): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1780 begin,sep,end = name.partition('.') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1781 if sep: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1782 if begin in self.meta: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1783 begin = self.meta[begin] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1784 if not self.regs.isRegArrayMember(end): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1785 end = self.resolveParam(end, parent, fieldVals) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1786 if not type(end) is int and self.regs.isRegArrayMember(end): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1787 arrayName = self.regs.arrayMemberParent(end) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1788 end = self.regs.arrayMemberIndex(end) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1789 if arrayName != begin: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1790 end = 'context->{0}[{1}]'.format(arrayName, end) |
1615
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
1791 if self.regs.isNamedArray(begin): |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
1792 regName = self.regs.arrayMemberName(begin, end) |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
1793 else: |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
1794 regName = '{0}.{1}'.format(begin, end) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1795 ret = 'context->{0}[{1}]'.format(begin, end) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1796 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1797 regName = name |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1798 if self.regs.isRegArrayMember(name): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1799 arr,idx = self.regs.regToArray[name] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1800 ret = 'context->{0}[{1}]'.format(arr, idx) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1801 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1802 ret = 'context->' + name |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1803 if regName == self.flags.flagReg: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1804 if isDst: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1805 self.needFlagDisperse = True |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1806 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1807 self.needFlagCoalesce = True |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1808 if isDst: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1809 self.lastDst = regName |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1810 return ret |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1811 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1812 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1813 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1814 def paramSize(self, name): |
1715
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1713
diff
changeset
|
1815 if name in self.meta: |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1713
diff
changeset
|
1816 return self.paramSize(self.meta[name]) |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1713
diff
changeset
|
1817 for i in range(len(self.scopes) -1, -1, -1): |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1713
diff
changeset
|
1818 size = self.scopes[i].localSize(name) |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1713
diff
changeset
|
1819 if size: |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1713
diff
changeset
|
1820 return size |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1821 begin,sep,_ = name.partition('.') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1822 if sep and self.regs.isRegArray(begin): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1823 return self.regs.regArrays[begin][0] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1824 if self.regs.isReg(name): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1825 return self.regs.regs[name] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1826 return 32 |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1827 |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
1828 def getLastSize(self): |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
1829 if self.lastSize: |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
1830 return self.lastSize |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
1831 return self.paramSize(self.lastDst) |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
1832 |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1833 def pushScope(self, scope): |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1834 self.scopes.append(scope) |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1835 self.currentScope = scope |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1836 |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1837 def popScope(self): |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1838 ret = self.scopes.pop() |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1839 self.currentScope = self.scopes[-1] if self.scopes else None |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1840 return ret |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1841 |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1842 def getRootScope(self): |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1843 return self.scopes[0] |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1844 |
1749
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1845 def parse(args): |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1846 f = args.source |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1847 instructions = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1848 subroutines = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1849 registers = None |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1850 flags = None |
1748
48a43dff4dc0
Added init functions to z80_util.c so new Z80 core is closer to a drop in replacement for the old one
Michael Pavone <pavone@retrodev.com>
parents:
1747
diff
changeset
|
1851 declares = [] |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1852 errors = [] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1853 info = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1854 line_num = 0 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1855 cur_object = None |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1856 for line in f: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1857 line_num += 1 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1858 line,_,comment = line.partition('#') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1859 if not line.strip(): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1860 continue |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1861 if line[0].isspace(): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1862 if not cur_object is None: |
1754
043cf458704c
Basic support for string operands in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1753
diff
changeset
|
1863 sep = True |
043cf458704c
Basic support for string operands in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1753
diff
changeset
|
1864 parts = [] |
043cf458704c
Basic support for string operands in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1753
diff
changeset
|
1865 while sep: |
043cf458704c
Basic support for string operands in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1753
diff
changeset
|
1866 before,sep,after = line.partition('"') |
043cf458704c
Basic support for string operands in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1753
diff
changeset
|
1867 before = before.strip() |
043cf458704c
Basic support for string operands in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1753
diff
changeset
|
1868 if before: |
2440
338c78da3fff
Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents:
1991
diff
changeset
|
1869 parts += [el.strip() for el in before.split(' ') if el.strip()] |
1754
043cf458704c
Basic support for string operands in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1753
diff
changeset
|
1870 if sep: |
043cf458704c
Basic support for string operands in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1753
diff
changeset
|
1871 #TODO: deal with escaped quotes |
043cf458704c
Basic support for string operands in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1753
diff
changeset
|
1872 inside,sep,after = after.partition('"') |
043cf458704c
Basic support for string operands in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1753
diff
changeset
|
1873 parts.append('"' + inside + '"') |
043cf458704c
Basic support for string operands in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1753
diff
changeset
|
1874 line = after |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1875 if type(cur_object) is dict: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1876 cur_object[parts[0]] = parts[1:] |
1748
48a43dff4dc0
Added init functions to z80_util.c so new Z80 core is closer to a drop in replacement for the old one
Michael Pavone <pavone@retrodev.com>
parents:
1747
diff
changeset
|
1877 elif type(cur_object) is list: |
1754
043cf458704c
Basic support for string operands in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1753
diff
changeset
|
1878 cur_object.append(' '.join(parts)) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1879 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1880 cur_object = cur_object.processLine(parts) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1881 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1882 # if type(cur_object) is Registers: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1883 # if len(parts) > 2: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1884 # cur_object.addRegArray(parts[0], int(parts[1]), parts[2:]) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1885 # else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1886 # cur_object.addReg(parts[0], int(parts[1])) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1887 # elif type(cur_object) is dict: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1888 # cur_object[parts[0]] = parts[1:] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1889 # elif parts[0] == 'switch': |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1890 # o = Switch(cur_object, parts[1]) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1891 # cur_object.addOp(o) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1892 # cur_object = o |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1893 # elif parts[0] == 'if': |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1894 # o = If(cur_object, parts[1]) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1895 # cur_object.addOp(o) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1896 # cur_object = o |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1897 # elif parts[0] == 'end': |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1898 # cur_object = cur_object.parent |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1899 # else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1900 # cur_object.addOp(NormalOp(parts)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1901 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1902 errors.append("Orphan instruction on line {0}".format(line_num)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1903 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1904 parts = line.split(' ') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1905 if len(parts) > 1: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1906 if len(parts) > 2: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1907 table,bitpattern,name = parts |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1908 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1909 bitpattern,name = parts |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1910 table = 'main' |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1911 value = 0 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1912 fields = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1913 curbit = len(bitpattern) - 1 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1914 for char in bitpattern: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1915 value <<= 1 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1916 if char in ('0', '1'): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1917 value |= int(char) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1918 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1919 if char in fields: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1920 fields[char] = (curbit, fields[char][1] + 1) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1921 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1922 fields[char] = (curbit, 1) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1923 curbit -= 1 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1924 cur_object = Instruction(value, fields, name.strip()) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1925 instructions.setdefault(table, []).append(cur_object) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1926 elif line.strip() == 'regs': |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1927 if registers is None: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1928 registers = Registers() |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1929 cur_object = registers |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1930 elif line.strip() == 'info': |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1931 cur_object = info |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1932 elif line.strip() == 'flags': |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1933 if flags is None: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1934 flags = Flags() |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1935 cur_object = flags |
1748
48a43dff4dc0
Added init functions to z80_util.c so new Z80 core is closer to a drop in replacement for the old one
Michael Pavone <pavone@retrodev.com>
parents:
1747
diff
changeset
|
1936 elif line.strip() == 'declare': |
48a43dff4dc0
Added init functions to z80_util.c so new Z80 core is closer to a drop in replacement for the old one
Michael Pavone <pavone@retrodev.com>
parents:
1747
diff
changeset
|
1937 cur_object = declares |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1938 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1939 cur_object = SubRoutine(line.strip()) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1940 subroutines[cur_object.name] = cur_object |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1941 if errors: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1942 print(errors) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1943 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1944 p = Program(registers, instructions, subroutines, info, flags) |
1749
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1945 p.dispatch = args.dispatch |
1748
48a43dff4dc0
Added init functions to z80_util.c so new Z80 core is closer to a drop in replacement for the old one
Michael Pavone <pavone@retrodev.com>
parents:
1747
diff
changeset
|
1946 p.declares = declares |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1947 p.booleans['dynarec'] = False |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1948 p.booleans['interp'] = True |
1749
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1949 if args.define: |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1950 for define in args.define: |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1951 name,sep,val = define.partition('=') |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1952 name = name.strip() |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1953 val = val.strip() |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1954 if sep: |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1955 p.booleans[name] = bool(val) |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1956 else: |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1957 p.booleans[name] = True |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1958 |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1959 if 'header' in info: |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1960 print('#include "{0}"'.format(info['header'][0])) |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1961 p.writeHeader('c', info['header'][0]) |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1962 print('#include "util.h"') |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1963 print('#include <stdlib.h>') |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1964 print(p.build('c')) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1965 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1966 def main(argv): |
1749
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1967 from argparse import ArgumentParser, FileType |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1968 argParser = ArgumentParser(description='CPU emulator DSL compiler') |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1969 argParser.add_argument('source', type=FileType('r')) |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1970 argParser.add_argument('-D', '--define', action='append') |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1971 argParser.add_argument('-d', '--dispatch', choices=('call', 'switch', 'goto'), default='call') |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1972 parse(argParser.parse_args(argv[1:])) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1973 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1974 if __name__ == '__main__': |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1975 from sys import argv |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1976 main(argv) |