Mercurial > repos > blastem
annotate svp.cpu @ 1620:a172f97d873f
Add the ability for a CPU definition to reference arbitrary C includes and use it to add a placeholder definition of svp_read_16
author | Michael Pavone <pavone@retrodev.com> |
---|---|
date | Thu, 04 Oct 2018 19:12:56 -0700 |
parents | 0e8438a4c76f |
children | ca158bc091f9 |
rev | line source |
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1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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1 info |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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2 prefix svp_ |
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3 opcode_size 16 |
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4 body svp_run_op |
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Getting SVP core closer to compiling
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5 header svp.h |
1620
a172f97d873f
Add the ability for a CPU definition to reference arbitrary C includes and use it to add a placeholder definition of svp_read_16
Michael Pavone <pavone@retrodev.com>
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1619
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6 include svp_util.c |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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7 |
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8 regs |
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9 internal 16 scratch1 x y scratch2 st pad pc |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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10 a 32 |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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11 stack 16 stack0 stack1 stack2 stack3 stack4 stack5 |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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12 stackidx 8 |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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13 p 32 |
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14 external 16 pm0 pm1 pm2 xst pm4 ext5 pmc |
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15 pointers0 8 r0 r1 r2 r3 |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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16 pointers1 8 r4 r5 r6 r7 |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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17 iram 16 1024 |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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18 ram0 16 256 |
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19 ram1 16 256 |
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20 zflag 8 |
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21 nflag 8 |
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22 rpl 16 |
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23 |
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24 flags |
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25 register st |
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26 Z 13 zero zflag |
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27 N 15 sign nflag |
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28 R 0-2 none rpl |
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29 |
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30 svp_pop |
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31 mov stack.stackidx dst |
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32 add 1 stackidx stackidx |
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33 switch stackidx |
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34 case 6 |
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35 mov 0 stackidx |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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36 end |
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37 |
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38 svp_push |
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39 arg src 16 |
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Clean up warnings from -1 case
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40 sub 1 stackidx stackidx |
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41 switch stackidx |
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42 case 0xFF |
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43 mov 5 stackidx |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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44 end |
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45 mov src stack.stackidx |
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46 |
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47 svp_ram_read |
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48 arg mode 16 |
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49 arg banki 16 |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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50 arg regi 16 |
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51 local idx 16 |
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52 |
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53 switch banki |
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54 case 0 |
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55 meta bank ram0 |
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56 meta reg pointers0.regi |
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57 |
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58 default |
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59 meta bank ram1 |
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60 meta reg pointers1.regi |
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61 end |
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62 |
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63 mov reg idx |
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64 switch mode |
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65 case 0 |
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66 meta modestr "" |
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67 |
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68 case 1 |
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69 meta modestr +! |
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70 add 1 reg reg |
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71 |
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72 case 2 |
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73 #loop decremenet |
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74 meta modestr - |
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Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
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75 |
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76 if rpl |
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77 local tmp 16 |
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78 mov reg tmp |
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79 lsl 1 rpl rpl |
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80 sub 1 rpl rpl |
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81 local mask 16 |
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82 not rpl mask |
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83 and reg mask reg |
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84 sub 1 tmp tmp |
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85 and rpl tmp tmp |
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86 or tmp reg reg |
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87 else |
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88 sub 1 reg reg |
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Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
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89 end |
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90 |
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91 case 3 |
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92 #loop increment |
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93 meta modestr + |
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94 |
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95 and 7 st rpl |
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96 if rpl |
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97 local tmp 16 |
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98 mov reg tmp |
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99 lsl 1 rpl rpl |
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100 sub 1 rpl rpl |
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101 local mask 16 |
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102 not rpl mask |
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103 and reg mask reg |
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104 add 1 tmp tmp |
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105 and rpl tmp tmp |
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106 or tmp reg reg |
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Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
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107 else |
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108 sub 1 reg reg |
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109 end |
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110 end |
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111 |
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112 and 255 idx idx |
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113 meta val bank.idx |
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114 |
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115 svp_read_ext |
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|
116 arg regidxr 16 |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
117 switch regidxr |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
118 case 7 |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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119 meta val a |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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120 |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
121 default |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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122 #TODO: PMAR stuff |
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123 meta val external.regidxr |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
124 end |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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125 |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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126 svp_write_ext |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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127 arg regidxw 16 |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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128 switch regidxw |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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129 case 7 |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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130 and 0xFFFF0000 a a |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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131 or src a a |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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132 |
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133 default |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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134 #TODO: PMAR stuff |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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135 mov src external.regidxw |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
136 end |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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137 |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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138 svp_alu_op |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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139 arg P 16 |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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140 arg param 32 |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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141 |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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142 switch P |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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143 case 1 |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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144 dis "sub %s" name |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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145 sub param a a |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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146 |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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147 case 3 |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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148 dis "cmp %s" name |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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149 cmp param a |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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150 |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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151 case 4 |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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152 dis "add %s" name |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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153 add param a a |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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154 |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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155 case 5 |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
156 dis "and %s" name |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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157 and param a a |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
158 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
159 case 6 |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
160 dis "or %s" name |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
161 or param a a |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
162 |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
163 case 7 |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
164 dis "eor %s" name |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
165 xor param a a |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
166 end |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
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|
167 update_flags ZN |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
168 |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
169 svp_check_cond |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
170 arg fval 16 |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
171 arg cond 16 |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
172 local invert 8 |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
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|
173 switch cond |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
174 case 0 |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
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|
175 meta flag 1 |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
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|
176 |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
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|
177 case 5 |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
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|
178 meta flag zflag |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
179 |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
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|
180 case 7 |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
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|
181 meta flag nflag |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
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|
182 |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
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|
183 default |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
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|
184 meta flag 0 |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
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|
185 end |
1614
c9639139aedf
Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents:
1613
diff
changeset
|
186 |
c9639139aedf
Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents:
1613
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|
187 if fval |
c9639139aedf
Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents:
1613
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|
188 meta istrue flag |
c9639139aedf
Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents:
1613
diff
changeset
|
189 |
c9639139aedf
Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents:
1613
diff
changeset
|
190 else |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
191 lnot flag invert |
1614
c9639139aedf
Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents:
1613
diff
changeset
|
192 meta istrue invert |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
diff
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|
193 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
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changeset
|
194 end |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
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|
195 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
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|
196 PPP0000000000000 alu_n1 |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
diff
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|
197 invalid P 0 |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
diff
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|
198 invalid P 2 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
diff
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|
199 meta name "-" |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
diff
changeset
|
200 svp_alu_op P 0xFFFF0000 |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
201 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
diff
changeset
|
202 PPP0000000000RRR alu_r |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
diff
changeset
|
203 invalid P 0 |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
diff
changeset
|
204 invalid P 2 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
diff
changeset
|
205 local tmp 32 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
206 lsl internal.R 16 tmp |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
diff
changeset
|
207 meta name internal.R |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
diff
changeset
|
208 svp_alu_op P tmp |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
diff
changeset
|
209 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
diff
changeset
|
210 PPP0000000000011 alu_a |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
diff
changeset
|
211 invalid P 0 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
212 invalid P 2 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
diff
changeset
|
213 svp_alu_op P a |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
diff
changeset
|
214 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
diff
changeset
|
215 PPP0000000000101 alu_stack |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
diff
changeset
|
216 invalid P 0 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
217 invalid P 2 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
diff
changeset
|
218 local tmp 32 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
diff
changeset
|
219 meta dst tmp |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
220 svp_pop |
1615
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
221 meta name "stack" |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
diff
changeset
|
222 svp_alu_op P tmp |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
diff
changeset
|
223 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
224 PPP0000000000111 alu_p |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
diff
changeset
|
225 invalid P 0 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
diff
changeset
|
226 invalid P 2 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
diff
changeset
|
227 meta name p |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
diff
changeset
|
228 svp_alu_op P p |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
diff
changeset
|
229 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
diff
changeset
|
230 PPP0000000001RRR alu_ext |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
diff
changeset
|
231 invalid P 0 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
232 invalid P 2 |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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233 local tmp 32 |
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234 svp_read_ext R |
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235 lsl val 16 tmp |
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236 meta name val |
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237 svp_alu_op P tmp |
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238 |
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239 PPP0001B0000MMRR alu_ram |
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240 invalid P 0 |
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241 invalid P 2 |
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242 svp_ram_read M B R |
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243 local tmp 32 |
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244 lsl val 16 tmp |
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245 |
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246 switch P |
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247 case 1 |
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248 dis "sub (%s%s)" reg modestr |
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249 sub tmp a a |
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250 |
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251 case 3 |
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252 dis "cmp (%s%s)" reg modestr |
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253 cmp tmp a |
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254 |
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255 case 4 |
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256 dis "add (%s%s)" reg modestr |
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257 add tmp a a |
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258 |
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259 case 5 |
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260 dis "and (%s%s)" reg modestr |
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261 and tmp a a |
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262 |
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263 case 6 |
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264 dis "or (%s%s)" reg modestr |
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265 or tmp a a |
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266 |
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267 case 7 |
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268 dis "eor (%s%s)" reg modestr |
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269 xor tmp a a |
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270 end |
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271 |
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272 update_flags ZN |
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273 |
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274 PPP0101B0000MMRR alu_ram_indirect |
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275 invalid P 0 |
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276 invalid P 2 |
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277 svp_ram_read M B R |
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278 svp_prog_ram_read val |
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279 local tmp 32 |
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280 lsl scratch1 16 tmp |
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281 |
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282 switch P |
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283 case 1 |
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284 dis "sub ((%s%s))" reg modestr |
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285 sub tmp a a |
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286 |
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287 case 3 |
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288 dis "cmp ((%s%s))" reg modestr |
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289 cmp tmp a |
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290 |
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291 case 4 |
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292 dis "add ((%s%s))" reg modestr |
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293 add tmp a a |
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294 |
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295 case 5 |
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296 dis "and ((%s%s))" reg modestr |
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297 and tmp a a |
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298 |
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299 case 6 |
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300 dis "or ((%s%s))" reg modestr |
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Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
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301 or tmp a a |
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302 |
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Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
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303 case 7 |
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Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
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304 dis "eor ((%s%s))" reg modestr |
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Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
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305 xor tmp a a |
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306 end |
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307 |
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308 update_flags ZN |
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309 |
1613
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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310 PPP0000000001111 alu_al |
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311 invalid P 0 |
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312 invalid P 2 |
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313 local tmp 32 |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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314 lsl a 16 tmp |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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315 |
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316 meta name al |
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317 svp_alu_op P tmp |
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318 |
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Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
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319 PPP0011JAAAAAAAA alu_ram_direct |
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320 invalid P 0 |
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Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
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321 invalid P 2 |
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322 if J |
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323 meta src ram1.A |
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324 else |
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325 meta src ram0.A |
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326 end |
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327 svp_alu_op P src |
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328 |
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329 PPP0010000000000 alu_immed |
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330 invalid P 0 |
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331 invalid P 2 |
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332 svp_op_fetch |
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333 svp_alu_op P scratch1 |
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334 |
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335 1001000FCCCC0OOO cond_mod |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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changeset
|
336 svp_check_cond F C |
1614
c9639139aedf
Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents:
1613
diff
changeset
|
337 if istrue |
c9639139aedf
Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents:
1613
diff
changeset
|
338 |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
339 switch O |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
340 case 2 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
341 asr a 1 a |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
342 update_flags ZN |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
343 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
344 case 3 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
345 lsl a 1 a |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
346 update_flags ZN |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
347 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
348 case 6 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
349 neg a a |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
350 update_flags ZN |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
351 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
352 case 7 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
353 abs a a |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
354 update_flags N |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
355 end |
1614
c9639139aedf
Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents:
1613
diff
changeset
|
356 end |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
357 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
358 000000000DDD0SSS ld_int_int |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
359 dis "ld %s, %s" internal.D internal.S |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
360 mov internal.S internal.D |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
361 |
1615
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
362 000000000DDD0101 ld_int_stack |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
363 dis "ld %s, stack" internal.D |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
364 meta dst internal.D |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
365 svp_pop |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
366 |
1615
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
367 0000000000110101 ld_a_stack |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
368 dis "ld a, stack" |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
369 local tmp 32 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
370 meta dst tmp |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
371 svp_pop |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
372 lsl tmp 16 tmp |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
373 and 0xFFFF a a |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
374 or tmp a a |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
375 |
1615
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
376 0000000001110101 ld_p_stack |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
377 dis "ld p, stack" |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
378 local tmp 32 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
379 meta dst tmp |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
380 svp_pop |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
381 lsl tmp 16 tmp |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
382 and 0xFFFF p p |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
383 or tmp p p |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
384 |
1615
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
385 0000000001010SSS ld_stack_int |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
386 dis "ld stack, %s" internal.S |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
387 svp_push internal.S |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
388 |
1615
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
389 0000000001010011 ld_stack_a |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
390 dis "ld stack, a" |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
391 local tmp 32 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
392 lsr a 16 tmp |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
393 svp_push tmp |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
394 |
1615
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
395 0000000001010111 ld_stack_p |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
396 dis "ld stack, p" |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
397 local tmp 32 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
398 lsr p 16 tmp |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
399 svp_push tmp |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
400 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
401 0000000000000000 ld_n1_n1 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
402 #nop? |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
403 dis "ld -, -" |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
404 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
405 0000000000000SSS ld_n1_int |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
406 #nop? |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
407 dis "nop??" |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
408 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
409 0000000000110111 ld_a_p |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
410 dis "ld a, p" |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
411 mov p a |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
412 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
413 0000000001110011 ld_p_a |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
414 dis "ld p, a" |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
415 mov a p |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
416 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
417 0000000000110011 ld_a_a |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
418 dis "ld a, a" |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
419 mov a a |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
420 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
421 0000000001110111 ld_p_p |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
422 dis "ld p, p" |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
423 mov p p |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
424 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
425 000000000DDD0111 ld_int_p |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
426 local tmp 32 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
427 lsr p 16 tmp |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
428 mov tmp internal.D |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
429 dis "ld %s, p" internal.D |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
430 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
431 000000000DDD0111 ld_int_a |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
432 local tmp 32 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
433 lsr a 16 tmp |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
434 mov tmp internal.D |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
435 dis "ld %s, a" internal.D |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
436 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
437 0000000001110SSS ld_p_int |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
438 local tmp 32 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
439 lsl internal.S 16 tmp |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
440 mov tmp p |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
441 dis "ld p, %s" internal.S |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
442 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
443 0000000000110SSS ld_a_int |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
444 local tmp 32 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
445 lsl internal.S 16 tmp |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
446 mov tmp a |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
447 dis "ld a, %s" internal.S |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
448 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
449 000000000DDD0000 ld_int_n1 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
450 dis "ld %s, -" internal.D |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
451 mov 0xFFFF internal.D |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
452 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
453 0000000000110000 ld_a_n1 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
454 dis "ld a, -" |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
455 and 0xFFFF a a |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
456 or 0xFFFF0000 a a |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
457 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
458 0000000001110000 ld_p_n1 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
459 dis "ld p, -" |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
460 and 0xFFFF p p |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
461 or 0xFFFF0000 p p |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
462 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
463 000000000DDD1SSS ld_int_ext |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
464 svp_read_ext S |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
465 dis "ld %s, %s" internal.D val |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
466 mov val internal.D |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
467 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
468 0000000000111SSS ld_a_ext |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
469 svp_read_ext S |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
470 dis "ld a, %s" val |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
471 local tmp 32 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
472 lsl val 16 tmp |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
473 and 0xFFFF a a |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
474 or tmp a a |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
475 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
476 0000000001111SSS ld_p_ext |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
477 svp_read_ext S |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
478 dis "ld p, %s" val |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
479 local tmp 32 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
480 lsl val 16 tmp |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
481 and 0xFFFF p p |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
482 or tmp p p |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
483 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
484 000000001DDD0SSS ld_ext_int |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
485 meta src internal.S |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
486 svp_write_ext D |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
487 switch D |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
488 case 7 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
489 dis "ld al, %s" src |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
490 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
491 default |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
492 dis "ld %s, %s" external.D src |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
493 end |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
494 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
495 000000001DDD0011 ld_ext_a |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
496 local tmp 32 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
497 lsr a 16 tmp |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
498 meta src tmp |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
499 svp_write_ext D |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
500 switch D |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
501 case 7 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
502 dis "ld al, a" |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
503 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
504 default |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
505 dis "ld %s, a" external.D |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
506 end |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
507 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
508 000000001DDD0111 ld_ext_p |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
509 local tmp 32 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
510 lsr p 16 tmp |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
511 meta src tmp |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
512 svp_write_ext D |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
513 switch D |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
514 case 7 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
515 dis "ld al, p" |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
516 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
517 default |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
518 dis "ld %s, p" external.D |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
519 end |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
520 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
521 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
522 000000001DDD1SSS ld_ext_ext |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
523 svp_read_ext S |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
524 meta src val |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
525 svp_write_ext D |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
526 switch D |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
527 case 7 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
528 dis "ld al, %s" src |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
529 default |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
530 dis "ld %s, %s" external.D src |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
531 end |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
532 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
533 0000001B0DDDMMPP ld_int_ram |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
534 svp_ram_read M B P |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
535 dis "ld %s, (%s%s)" internal.D reg modestr |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
536 mov val internal.D |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
537 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
538 0000001B0011MMPP ld_a_ram |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
539 svp_ram_read M B P |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
540 dis "ld a, (%s%s)" reg modestr |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
541 local tmp 32 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
542 lsl val 16 tmp |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
543 and 0xFFFF a a |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
544 or tmp a a |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
545 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
546 0000001B0111MMPP ld_p_ram |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
547 svp_ram_read M B P |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
548 dis "ld p, (%s%s)" reg modestr |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
549 local tmp 32 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
550 lsl val 16 tmp |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
551 and 0xFFFF p p |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
552 or tmp p p |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
553 |
1615
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
554 0000001B0101MMPP ld_stack_ram |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
555 svp_ram_read M B P |
1615
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
556 dis "ld stack, (%s%s)" reg modestr |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
557 svp_push val |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
558 |
1615
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
559 000010000DDD0000 ld_int_immed |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
560 svp_op_fetch |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
561 dis "ld %s, %X" internal.D scratch1 |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
562 mov scratch1 internal.D |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
563 |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
564 0000100000000000 ld_n1_immed |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
565 svp_op_fetch |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
566 dis "ld -, %X" scratch1 |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
567 |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
568 0000100000110000 ld_a_immed |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
569 local tmp 32 |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
570 svp_op_fetch |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
571 dis "ld a, %X" scratch1 |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
572 lsl 16 scratch1 tmp |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
573 and 0xFFFF a a |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
574 or tmp a a |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
575 |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
576 0000100001010000 ld_stack_immed |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
577 svp_op_fetch |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
578 dis "ld stack, %X" scratch1 |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
579 svp_push scratch1 |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
580 |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
581 0000100001110000 ld_p_immed |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
582 local tmp 32 |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
583 svp_op_fetch |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
584 dis "ld p, %X" scratch1 |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
585 lsl 16 scratch1 tmp |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
586 and 0xFFFF p p |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
587 or tmp p p |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
588 |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
589 000010001DDD0000 ld_ext_immed |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
590 svp_op_fetch |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
591 dis "ld %s, %X", external.D, scratch1 |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
592 meta src scratch1 |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
593 svp_write_ext D |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
594 switch D |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
595 case 7 |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
596 dis "ld al, %X" scratch1 |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
597 |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
598 default |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
599 dis "ld %s, %X" external.D scratch1 |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
600 end |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
601 |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
602 0100100FCCCC0000 call_cond |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
603 svp_check_cond F C |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
604 svp_op_fetch |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
605 |
1614
c9639139aedf
Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents:
1613
diff
changeset
|
606 if istrue |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
607 svp_push pc |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
608 mov scratch1 pc |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
609 end |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
610 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
611 0100110FCCCC0000 bra_cond |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
612 svp_check_cond F C |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
613 svp_op_fetch |
1614
c9639139aedf
Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents:
1613
diff
changeset
|
614 if istrue |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
615 mov scratch1 pc |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
616 end |
1615
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
617 |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
618 svp_prog_ram_read |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
619 arg src 16 |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
620 cycles 1 |
1615
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
621 cmp 1024 src |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
622 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
623 if >=U |
1615
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
624 add src src scratch1 |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
625 ocall read_16 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
626 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
627 else |
1615
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
628 mov iram.src scratch1 |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
629 end |
1615
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
630 |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
631 svp_op_fetch |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
632 svp_prog_ram_read pc |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
633 add 1 pc pc |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
634 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
635 svp_run_op |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
636 svp_op_fetch |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
637 dispatch scratch1 |