Mercurial > repos > blastem
annotate z80_to_x86.c @ 248:9c7a3db7bcd0
Implement ADC and SBC in Z80 core (untested)
author | Mike Pavone <pavone@retrodev.com> |
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date | Sun, 28 Apr 2013 23:25:18 -0700 |
parents | 682e505f5757 |
children | 5f1b68cecfc7 |
rev | line source |
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1 #include "z80inst.h" |
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2 #include "z80_to_x86.h" |
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3 #include "gen_x86.h" |
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4 #include "mem.h" |
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5 #include <stdio.h> |
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6 #include <stdlib.h> |
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7 #include <stddef.h> |
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8 #include <string.h> |
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9 |
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10 #define MODE_UNUSED (MODE_IMMED-1) |
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11 |
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12 #define ZCYCLES RBP |
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13 #define SCRATCH1 R13 |
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14 #define SCRATCH2 R14 |
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15 #define CONTEXT RSI |
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16 |
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17 //TODO: Find out the actual value for this |
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18 #define MAX_NATIVE_SIZE 128 |
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19 |
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20 void z80_read_byte(); |
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21 void z80_read_word(); |
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22 void z80_write_byte(); |
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23 void z80_write_word_highfirst(); |
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24 void z80_write_word_lowfirst(); |
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25 void z80_save_context(); |
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26 void z80_native_addr(); |
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27 |
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28 uint8_t z80_size(z80inst * inst) |
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29 { |
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30 uint8_t reg = (inst->reg & 0x1F); |
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31 if (reg != Z80_UNUSED && reg != Z80_USE_IMMED) { |
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32 return reg < Z80_BC ? SZ_B : SZ_W; |
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33 } |
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34 //TODO: Handle any necessary special cases |
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35 return SZ_B; |
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36 } |
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37 |
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38 uint8_t z80_high_reg(uint8_t reg) |
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39 { |
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40 switch(reg) |
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41 { |
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42 case Z80_C: |
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43 case Z80_BC: |
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44 return Z80_B; |
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45 case Z80_E: |
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46 case Z80_DE: |
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47 return Z80_D; |
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48 case Z80_L: |
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49 case Z80_HL: |
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50 return Z80_H; |
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51 case Z80_IXL: |
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52 case Z80_IX: |
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53 return Z80_IXH; |
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54 case Z80_IYL: |
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55 case Z80_IY: |
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56 return Z80_IYH; |
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57 default: |
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58 return Z80_UNUSED; |
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59 } |
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60 } |
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61 |
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62 uint8_t * zcycles(uint8_t * dst, uint32_t num_cycles) |
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63 { |
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64 return add_ir(dst, num_cycles, ZCYCLES, SZ_D); |
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65 } |
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66 |
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67 uint8_t * translate_z80_reg(z80inst * inst, x86_ea * ea, uint8_t * dst, x86_z80_options * opts) |
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68 { |
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69 if (inst->reg == Z80_USE_IMMED) { |
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70 ea->mode = MODE_IMMED; |
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71 ea->disp = inst->immed; |
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72 } else if ((inst->reg & 0x1F) == Z80_UNUSED) { |
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73 ea->mode = MODE_UNUSED; |
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74 } else { |
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75 ea->mode = MODE_REG_DIRECT; |
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76 if (inst->reg == Z80_IYH) { |
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77 ea->base = opts->regs[Z80_IYL]; |
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78 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W); |
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79 } else { |
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80 ea->base = opts->regs[inst->reg]; |
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81 } |
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82 } |
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83 return dst; |
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84 } |
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85 |
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86 uint8_t * z80_save_reg(uint8_t * dst, z80inst * inst, x86_z80_options * opts) |
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87 { |
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88 if (inst->reg == Z80_IYH) { |
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89 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W); |
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90 } |
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91 return dst; |
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92 } |
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93 |
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94 uint8_t * translate_z80_ea(z80inst * inst, x86_ea * ea, uint8_t * dst, x86_z80_options * opts, uint8_t read, uint8_t modify) |
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95 { |
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96 uint8_t size, reg, areg; |
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97 ea->mode = MODE_REG_DIRECT; |
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98 areg = read ? SCRATCH1 : SCRATCH2; |
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99 switch(inst->addr_mode & 0x1F) |
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100 { |
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101 case Z80_REG: |
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102 if (inst->ea_reg == Z80_IYH) { |
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103 ea->base = opts->regs[Z80_IYL]; |
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104 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W); |
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105 } else { |
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106 ea->base = opts->regs[inst->ea_reg]; |
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107 } |
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108 break; |
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109 case Z80_REG_INDIRECT: |
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110 dst = mov_rr(dst, opts->regs[inst->ea_reg], areg, SZ_W); |
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111 size = z80_size(inst); |
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112 if (read) { |
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113 if (modify) { |
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114 dst = push_r(dst, SCRATCH1); |
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115 } |
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116 if (size == SZ_B) { |
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117 dst = call(dst, (uint8_t *)z80_read_byte); |
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118 } else { |
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119 dst = call(dst, (uint8_t *)z80_read_word); |
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120 } |
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121 if (modify) { |
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122 dst = pop_r(dst, SCRATCH2); |
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123 } |
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124 } |
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125 ea->base = SCRATCH1; |
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126 break; |
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127 case Z80_IMMED: |
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128 ea->mode = MODE_IMMED; |
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129 ea->disp = inst->immed; |
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130 break; |
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131 case Z80_IMMED_INDIRECT: |
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132 dst = mov_ir(dst, inst->immed, areg, SZ_W); |
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133 size = z80_size(inst); |
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134 if (read) { |
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135 if (modify) { |
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136 dst = push_r(dst, SCRATCH1); |
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137 } |
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138 if (size == SZ_B) { |
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139 dst = call(dst, (uint8_t *)z80_read_byte); |
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140 } else { |
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141 dst = call(dst, (uint8_t *)z80_read_word); |
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142 } |
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143 if (modify) { |
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144 dst = pop_r(dst, SCRATCH2); |
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145 } |
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146 } |
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147 ea->base = SCRATCH1; |
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148 break; |
235
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149 case Z80_IX_DISPLACE: |
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150 case Z80_IY_DISPLACE: |
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151 reg = opts->regs[inst->addr_mode == Z80_IX_DISPLACE ? Z80_IX : Z80_IY]; |
213
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152 dst = mov_rr(dst, reg, areg, SZ_W); |
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153 dst = add_ir(dst, inst->immed, areg, SZ_W); |
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154 size = z80_size(inst); |
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155 if (read) { |
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156 if (modify) { |
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157 dst = push_r(dst, SCRATCH1); |
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158 } |
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159 if (size == SZ_B) { |
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160 dst = call(dst, (uint8_t *)z80_read_byte); |
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161 } else { |
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162 dst = call(dst, (uint8_t *)z80_read_word); |
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163 } |
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164 if (modify) { |
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165 dst = pop_r(dst, SCRATCH2); |
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166 } |
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167 } |
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168 break; |
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169 case Z80_UNUSED: |
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170 ea->mode = MODE_UNUSED; |
213
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171 break; |
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172 default: |
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173 fprintf(stderr, "Unrecognized Z80 addressing mode %d\n", inst->addr_mode); |
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174 exit(1); |
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175 } |
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176 return dst; |
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177 } |
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178 |
235
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179 uint8_t * z80_save_ea(uint8_t * dst, z80inst * inst, x86_z80_options * opts) |
213
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180 { |
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181 if (inst->addr_mode == Z80_REG && inst->ea_reg == Z80_IYH) { |
213
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182 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W); |
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183 } |
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184 return dst; |
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185 } |
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186 |
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187 uint8_t * z80_save_result(uint8_t * dst, z80inst * inst) |
213
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188 { |
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189 if (z80_size(inst) == SZ_B) { |
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190 dst = call(dst, (uint8_t *)z80_write_byte); |
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191 } else { |
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192 dst = call(dst, (uint8_t *)z80_write_word_lowfirst); |
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193 } |
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194 return dst; |
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195 } |
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196 |
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197 enum { |
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198 DONT_READ=0, |
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199 READ |
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200 }; |
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201 |
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202 enum { |
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203 DONT_MODIFY=0, |
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204 MODIFY |
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205 }; |
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206 |
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207 uint8_t zf_off(uint8_t flag) |
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208 { |
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209 return offsetof(z80_context, flags) + flag; |
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210 } |
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211 |
241
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212 uint8_t zaf_off(uint8_t flag) |
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213 { |
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214 return offsetof(z80_context, alt_flags) + flag; |
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215 } |
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216 |
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217 uint8_t zar_off(uint8_t reg) |
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218 { |
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219 return offsetof(z80_context, alt_regs) + reg; |
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220 } |
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221 |
235
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222 void z80_print_regs_exit(z80_context * context) |
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223 { |
243
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224 printf("A: %X\nB: %X\nC: %X\nD: %X\nE: %X\nHL: %X\nIX: %X\nIY: %X\nSP: %X\n\nIM: %d, IFF1: %d, IFF2: %d\n", |
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225 context->regs[Z80_A], context->regs[Z80_B], context->regs[Z80_C], |
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226 context->regs[Z80_D], context->regs[Z80_E], |
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227 (context->regs[Z80_H] << 8) | context->regs[Z80_L], |
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228 (context->regs[Z80_IXH] << 8) | context->regs[Z80_IXL], |
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229 (context->regs[Z80_IYH] << 8) | context->regs[Z80_IYL], |
243
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230 context->sp, context->im, context->iff1, context->iff2); |
241
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231 puts("--Alternate Regs--"); |
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232 printf("A: %X\nB: %X\nC: %X\nD: %X\nE: %X\nHL: %X\nIX: %X\nIY: %X\n", |
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233 context->alt_regs[Z80_A], context->alt_regs[Z80_B], context->alt_regs[Z80_C], |
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234 context->alt_regs[Z80_D], context->alt_regs[Z80_E], |
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235 (context->alt_regs[Z80_H] << 8) | context->alt_regs[Z80_L], |
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236 (context->alt_regs[Z80_IXH] << 8) | context->alt_regs[Z80_IXL], |
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237 (context->alt_regs[Z80_IYH] << 8) | context->alt_regs[Z80_IYL]); |
235
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238 exit(0); |
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239 } |
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240 |
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241 uint8_t * translate_z80inst(z80inst * inst, uint8_t * dst, z80_context * context, uint16_t address) |
213
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242 { |
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243 uint32_t cycles; |
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244 x86_ea src_op, dst_op; |
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245 uint8_t size; |
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246 x86_z80_options *opts = context->options; |
213
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247 switch(inst->op) |
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248 { |
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249 case Z80_LD: |
235
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250 size = z80_size(inst); |
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251 switch (inst->addr_mode & 0x1F) |
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252 { |
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253 case Z80_REG: |
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254 case Z80_REG_INDIRECT: |
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255 cycles = size == SZ_B ? 4 : 6; |
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256 if (inst->ea_reg == Z80_IX || inst->ea_reg == Z80_IY) { |
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257 cycles += 4; |
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258 } |
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259 break; |
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260 case Z80_IMMED: |
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261 cycles = size == SZ_B ? 7 : 10; |
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262 break; |
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263 case Z80_IMMED_INDIRECT: |
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264 cycles = 10; |
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265 break; |
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266 case Z80_IX_DISPLACE: |
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267 case Z80_IY_DISPLACE: |
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268 cycles = 12; |
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269 break; |
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270 } |
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271 if ((inst->reg >= Z80_IXL && inst->reg <= Z80_IYH) || inst->reg == Z80_IX || inst->reg == Z80_IY) { |
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272 cycles += 4; |
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273 } |
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274 dst = zcycles(dst, cycles); |
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275 if (inst->addr_mode & Z80_DIR) { |
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276 dst = translate_z80_reg(inst, &src_op, dst, opts); |
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277 dst = translate_z80_ea(inst, &dst_op, dst, opts, DONT_READ, MODIFY); |
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278 } else { |
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279 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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280 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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281 } |
235
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282 if (src_op.mode == MODE_REG_DIRECT) { |
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283 dst = mov_rr(dst, src_op.base, dst_op.base, size); |
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284 } else { |
235
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285 dst = mov_ir(dst, src_op.disp, dst_op.base, size); |
213
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286 } |
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287 dst = z80_save_reg(dst, inst, opts); |
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288 dst = z80_save_ea(dst, inst, opts); |
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289 if (inst->addr_mode & Z80_DIR) { |
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290 dst = z80_save_result(dst, inst); |
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291 } |
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292 break; |
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293 case Z80_PUSH: |
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294 dst = zcycles(dst, (inst->reg == Z80_IX || inst->reg == Z80_IY) ? 9 : 5); |
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295 dst = sub_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
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296 if (inst->reg == Z80_AF) { |
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297 dst = mov_rdisp8r(dst, CONTEXT, zf_off(ZF_S), SCRATCH2, SZ_B); |
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298 dst = shl_ir(dst, 1, SCRATCH2, SZ_B); |
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299 dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_Z), SCRATCH2, SZ_B); |
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300 dst = shl_ir(dst, 2, SCRATCH2, SZ_B); |
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301 dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_H), SCRATCH2, SZ_B); |
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302 dst = shl_ir(dst, 2, SCRATCH2, SZ_B); |
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303 dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_PV), SCRATCH2, SZ_B); |
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304 dst = shl_ir(dst, 1, SCRATCH2, SZ_B); |
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305 dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_N), SCRATCH2, SZ_B); |
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306 dst = shl_ir(dst, 1, SCRATCH2, SZ_B); |
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307 dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_C), SCRATCH2, SZ_B); |
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308 dst = shl_ir(dst, 8, SCRATCH2, SZ_W); |
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309 dst = mov_rr(dst, opts->regs[Z80_A], SCRATCH2, SZ_B); |
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310 } else { |
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311 dst = translate_z80_reg(inst, &src_op, dst, opts); |
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312 dst = mov_rr(dst, src_op.base, SCRATCH2, SZ_W); |
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313 } |
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314 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
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315 dst = call(dst, (uint8_t *)z80_write_word_highfirst); |
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316 //no call to save_z80_reg needed since there's no chance we'll use the only |
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317 //the upper half of a register pair |
213
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318 break; |
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319 case Z80_POP: |
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320 dst = zcycles(dst, (inst->reg == Z80_IX || inst->reg == Z80_IY) ? 8 : 4); |
235
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321 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
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322 dst = call(dst, (uint8_t *)z80_read_word); |
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323 dst = add_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
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324 if (inst->reg == Z80_AF) { |
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325 dst = mov_rr(dst, SCRATCH1, opts->regs[Z80_A], SZ_B); |
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326 dst = bt_ir(dst, 8, SCRATCH1, SZ_W); |
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327 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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328 dst = bt_ir(dst, 9, SCRATCH1, SZ_W); |
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329 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_N)); |
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330 dst = bt_ir(dst, 10, SCRATCH1, SZ_W); |
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331 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_PV)); |
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332 dst = bt_ir(dst, 12, SCRATCH1, SZ_W); |
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333 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_H)); |
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334 dst = bt_ir(dst, 14, SCRATCH1, SZ_W); |
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335 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_Z)); |
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336 dst = bt_ir(dst, 15, SCRATCH1, SZ_W); |
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337 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_S)); |
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338 } else { |
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339 dst = translate_z80_reg(inst, &src_op, dst, opts); |
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340 dst = mov_rr(dst, SCRATCH1, src_op.base, SZ_W); |
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341 } |
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342 //no call to save_z80_reg needed since there's no chance we'll use the only |
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343 //the upper half of a register pair |
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344 break; |
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345 case Z80_EX: |
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346 if (inst->addr_mode == Z80_REG || inst->reg == Z80_HL) { |
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347 cycles = 4; |
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348 } else { |
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349 cycles = 8; |
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350 } |
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351 dst = zcycles(dst, cycles); |
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352 if (inst->addr_mode == Z80_REG) { |
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353 if(inst->reg == Z80_AF) { |
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354 dst = mov_rr(dst, opts->regs[Z80_A], SCRATCH1, SZ_B); |
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355 dst = mov_rdisp8r(dst, CONTEXT, zar_off(Z80_A), opts->regs[Z80_A], SZ_B); |
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356 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, zar_off(Z80_A), SZ_B); |
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357 |
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358 //Flags are currently word aligned, so we can move |
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359 //them efficiently a word at a time |
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360 for (int f = ZF_C; f < ZF_NUM; f+=2) { |
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361 dst = mov_rdisp8r(dst, CONTEXT, zf_off(f), SCRATCH1, SZ_W); |
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362 dst = mov_rdisp8r(dst, CONTEXT, zaf_off(f), SCRATCH2, SZ_W); |
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363 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, zaf_off(f), SZ_W); |
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364 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, zf_off(f), SZ_W); |
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365 } |
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366 } else { |
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367 dst = xchg_rr(dst, opts->regs[Z80_DE], opts->regs[Z80_HL], SZ_W); |
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368 } |
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369 } else { |
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370 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
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371 dst = call(dst, (uint8_t *)z80_read_byte); |
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372 dst = mov_rr(dst, opts->regs[inst->reg], SCRATCH2, SZ_B); |
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373 dst = mov_rr(dst, SCRATCH1, opts->regs[inst->reg], SZ_B); |
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374 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
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375 dst = call(dst, (uint8_t *)z80_write_byte); |
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376 dst = zcycles(dst, 1); |
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377 uint8_t high_reg = z80_high_reg(inst->reg); |
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378 uint8_t use_reg; |
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379 //even though some of the upper halves can be used directly |
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380 //the limitations on mixing *H regs with the REX prefix |
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381 //prevent us from taking advantage of it |
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382 use_reg = opts->regs[inst->reg]; |
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383 dst = ror_ir(dst, 8, use_reg, SZ_W); |
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384 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
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385 dst = add_ir(dst, 1, SCRATCH1, SZ_W); |
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386 dst = call(dst, (uint8_t *)z80_read_byte); |
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387 dst = mov_rr(dst, use_reg, SCRATCH2, SZ_B); |
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388 dst = mov_rr(dst, SCRATCH1, use_reg, SZ_B); |
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389 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
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390 dst = add_ir(dst, 1, SCRATCH1, SZ_W); |
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391 dst = call(dst, (uint8_t *)z80_write_byte); |
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392 //restore reg to normal rotation |
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393 dst = ror_ir(dst, 8, use_reg, SZ_W); |
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394 dst = zcycles(dst, 2); |
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395 } |
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396 break; |
213
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397 case Z80_EXX: |
241
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398 dst = zcycles(dst, 4); |
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399 dst = mov_rr(dst, opts->regs[Z80_BC], SCRATCH1, SZ_W); |
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400 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH2, SZ_W); |
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401 dst = mov_rdisp8r(dst, CONTEXT, zar_off(Z80_C), opts->regs[Z80_BC], SZ_W); |
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402 dst = mov_rdisp8r(dst, CONTEXT, zar_off(Z80_L), opts->regs[Z80_HL], SZ_W); |
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403 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, zar_off(Z80_C), SZ_W); |
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404 dst = mov_rrdisp8(dst, SCRATCH2, CONTEXT, zar_off(Z80_L), SZ_W); |
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405 dst = mov_rr(dst, opts->regs[Z80_DE], SCRATCH1, SZ_W); |
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406 dst = mov_rdisp8r(dst, CONTEXT, zar_off(Z80_E), opts->regs[Z80_DE], SZ_W); |
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407 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, zar_off(Z80_E), SZ_W); |
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408 break; |
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409 /*case Z80_LDI: |
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410 case Z80_LDIR: |
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411 case Z80_LDD: |
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412 case Z80_LDDR: |
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413 case Z80_CPI: |
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414 case Z80_CPIR: |
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415 case Z80_CPD: |
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416 case Z80_CPDR: |
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417 break;*/ |
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418 case Z80_ADD: |
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419 cycles = 4; |
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420 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
213
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421 cycles += 12; |
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422 } else if(inst->addr_mode == Z80_IMMED) { |
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423 cycles += 3; |
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424 } else if(z80_size(inst) == SZ_W) { |
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425 cycles += 4; |
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426 } |
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427 dst = zcycles(dst, cycles); |
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428 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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429 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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430 if (src_op.mode == MODE_REG_DIRECT) { |
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431 dst = add_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
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432 } else { |
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433 dst = add_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
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434 } |
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435 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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436 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
213
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437 //TODO: Implement half-carry flag |
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438 if (z80_size(inst) == SZ_B) { |
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439 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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440 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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441 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
213
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442 } |
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443 dst = z80_save_reg(dst, inst, opts); |
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444 dst = z80_save_ea(dst, inst, opts); |
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445 break; |
248
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446 case Z80_ADC: |
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447 cycles = 4; |
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448 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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449 cycles += 12; |
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450 } else if(inst->addr_mode == Z80_IMMED) { |
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451 cycles += 3; |
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452 } else if(z80_size(inst) == SZ_W) { |
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453 cycles += 4; |
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454 } |
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455 dst = zcycles(dst, cycles); |
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456 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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457 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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458 if (src_op.mode == MODE_REG_DIRECT) { |
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459 dst = adc_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
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460 } else { |
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461 dst = adc_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
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462 } |
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463 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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464 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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465 //TODO: Implement half-carry flag |
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466 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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467 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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468 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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469 dst = z80_save_reg(dst, inst, opts); |
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470 dst = z80_save_ea(dst, inst, opts); |
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471 break; |
213
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472 case Z80_SUB: |
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473 cycles = 4; |
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474 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
213
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475 cycles += 12; |
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476 } else if(inst->addr_mode == Z80_IMMED) { |
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477 cycles += 3; |
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478 } |
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479 dst = zcycles(dst, cycles); |
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|
480 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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481 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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|
482 if (src_op.mode == MODE_REG_DIRECT) { |
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483 dst = sub_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
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|
484 } else { |
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|
485 dst = sub_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
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|
486 } |
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|
487 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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488 dst = mov_irdisp8(dst, 1, CONTEXT, zf_off(ZF_N), SZ_B); |
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489 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
213
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|
490 //TODO: Implement half-carry flag |
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491 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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492 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
213
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|
493 dst = z80_save_reg(dst, inst, opts); |
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|
494 dst = z80_save_ea(dst, inst, opts); |
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|
495 break; |
248
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496 case Z80_SBC: |
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497 cycles = 4; |
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498 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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499 cycles += 12; |
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500 } else if(inst->addr_mode == Z80_IMMED) { |
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501 cycles += 3; |
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502 } else if(z80_size(inst) == SZ_W) { |
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503 cycles += 4; |
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504 } |
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505 dst = zcycles(dst, cycles); |
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506 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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507 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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508 if (src_op.mode == MODE_REG_DIRECT) { |
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509 dst = sbb_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
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510 } else { |
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511 dst = sbb_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
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512 } |
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513 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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514 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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515 //TODO: Implement half-carry flag |
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516 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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517 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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518 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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519 dst = z80_save_reg(dst, inst, opts); |
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520 dst = z80_save_ea(dst, inst, opts); |
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521 break; |
213
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522 case Z80_AND: |
236
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523 cycles = 4; |
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524 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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525 cycles += 12; |
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526 } else if(inst->addr_mode == Z80_IMMED) { |
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527 cycles += 3; |
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528 } else if(z80_size(inst) == SZ_W) { |
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529 cycles += 4; |
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530 } |
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531 dst = zcycles(dst, cycles); |
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532 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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533 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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534 if (src_op.mode == MODE_REG_DIRECT) { |
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535 dst = and_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
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536 } else { |
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537 dst = and_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
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538 } |
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539 //TODO: Cleanup flags |
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540 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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541 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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542 //TODO: Implement half-carry flag |
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543 if (z80_size(inst) == SZ_B) { |
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544 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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545 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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546 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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547 } |
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548 dst = z80_save_reg(dst, inst, opts); |
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549 dst = z80_save_ea(dst, inst, opts); |
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550 break; |
213
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551 case Z80_OR: |
236
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552 cycles = 4; |
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553 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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554 cycles += 12; |
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555 } else if(inst->addr_mode == Z80_IMMED) { |
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556 cycles += 3; |
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557 } else if(z80_size(inst) == SZ_W) { |
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558 cycles += 4; |
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|
559 } |
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560 dst = zcycles(dst, cycles); |
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561 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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562 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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563 if (src_op.mode == MODE_REG_DIRECT) { |
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564 dst = or_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
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565 } else { |
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566 dst = or_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
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567 } |
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568 //TODO: Cleanup flags |
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569 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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570 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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571 //TODO: Implement half-carry flag |
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572 if (z80_size(inst) == SZ_B) { |
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573 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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574 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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575 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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576 } |
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577 dst = z80_save_reg(dst, inst, opts); |
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578 dst = z80_save_ea(dst, inst, opts); |
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579 break; |
213
4d4559b04c59
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580 case Z80_XOR: |
236
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581 cycles = 4; |
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582 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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583 cycles += 12; |
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584 } else if(inst->addr_mode == Z80_IMMED) { |
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235
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585 cycles += 3; |
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235
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586 } else if(z80_size(inst) == SZ_W) { |
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587 cycles += 4; |
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|
588 } |
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589 dst = zcycles(dst, cycles); |
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590 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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591 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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592 if (src_op.mode == MODE_REG_DIRECT) { |
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235
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593 dst = add_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
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594 } else { |
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595 dst = add_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
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596 } |
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235
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|
597 //TODO: Cleanup flags |
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diff
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598 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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599 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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235
diff
changeset
|
600 //TODO: Implement half-carry flag |
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235
diff
changeset
|
601 if (z80_size(inst) == SZ_B) { |
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602 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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235
diff
changeset
|
603 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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604 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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235
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|
605 } |
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606 dst = z80_save_reg(dst, inst, opts); |
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607 dst = z80_save_ea(dst, inst, opts); |
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608 break; |
242 | 609 case Z80_CP: |
610 cycles = 4; | |
611 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { | |
612 cycles += 12; | |
613 } else if(inst->addr_mode == Z80_IMMED) { | |
614 cycles += 3; | |
615 } | |
616 dst = zcycles(dst, cycles); | |
617 dst = translate_z80_reg(inst, &dst_op, dst, opts); | |
618 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); | |
619 if (src_op.mode == MODE_REG_DIRECT) { | |
620 dst = cmp_rr(dst, src_op.base, dst_op.base, z80_size(inst)); | |
621 } else { | |
622 dst = cmp_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); | |
623 } | |
624 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); | |
625 dst = mov_irdisp8(dst, 1, CONTEXT, zf_off(ZF_N), SZ_B); | |
626 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); | |
627 //TODO: Implement half-carry flag | |
628 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); | |
629 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); | |
630 dst = z80_save_reg(dst, inst, opts); | |
631 dst = z80_save_ea(dst, inst, opts); | |
632 break; | |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
633 case Z80_INC: |
4d4559b04c59
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parents:
diff
changeset
|
634 cycles = 4; |
4d4559b04c59
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parents:
diff
changeset
|
635 if (inst->reg == Z80_IX || inst->reg == Z80_IY) { |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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diff
changeset
|
636 cycles += 6; |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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diff
changeset
|
637 } else if(z80_size(inst) == SZ_W) { |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff
changeset
|
638 cycles += 2; |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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diff
changeset
|
639 } else if(inst->reg == Z80_IXH || inst->reg == Z80_IXL || inst->reg == Z80_IYH || inst->reg == Z80_IYL || inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
4d4559b04c59
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diff
changeset
|
640 cycles += 4; |
4d4559b04c59
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diff
changeset
|
641 } |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff
changeset
|
642 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff
changeset
|
643 if (dst_op.mode == MODE_UNUSED) { |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff
changeset
|
644 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff
changeset
|
645 } |
4d4559b04c59
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diff
changeset
|
646 dst = add_ir(dst, 1, dst_op.base, z80_size(inst)); |
4d4559b04c59
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changeset
|
647 if (z80_size(inst) == SZ_B) { |
235
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648 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
213
4d4559b04c59
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|
649 //TODO: Implement half-carry flag |
235
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650 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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651 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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652 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
213
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|
653 } |
4d4559b04c59
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changeset
|
654 dst = z80_save_reg(dst, inst, opts); |
4d4559b04c59
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|
655 dst = z80_save_ea(dst, inst, opts); |
4d4559b04c59
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|
656 break; |
236
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657 case Z80_DEC: |
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658 cycles = 4; |
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659 if (inst->reg == Z80_IX || inst->reg == Z80_IY) { |
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660 cycles += 6; |
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661 } else if(z80_size(inst) == SZ_W) { |
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662 cycles += 2; |
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663 } else if(inst->reg == Z80_IXH || inst->reg == Z80_IXL || inst->reg == Z80_IYH || inst->reg == Z80_IYL || inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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664 cycles += 4; |
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665 } |
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666 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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667 if (dst_op.mode == MODE_UNUSED) { |
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668 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
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|
669 } |
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670 dst = sub_ir(dst, 1, dst_op.base, z80_size(inst)); |
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671 if (z80_size(inst) == SZ_B) { |
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672 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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673 //TODO: Implement half-carry flag |
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674 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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675 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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676 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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677 } |
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|
678 dst = z80_save_reg(dst, inst, opts); |
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|
679 dst = z80_save_ea(dst, inst, opts); |
213
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|
680 break; |
236
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changeset
|
681 /*case Z80_DAA: |
213
4d4559b04c59
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changeset
|
682 case Z80_CPL: |
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changeset
|
683 case Z80_NEG: |
4d4559b04c59
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|
684 case Z80_CCF: |
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changeset
|
685 case Z80_SCF:*/ |
4d4559b04c59
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parents:
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changeset
|
686 case Z80_NOP: |
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|
687 if (inst->immed == 42) { |
4d4559b04c59
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changeset
|
688 dst = call(dst, (uint8_t *)z80_save_context); |
4d4559b04c59
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changeset
|
689 dst = mov_rr(dst, CONTEXT, RDI, SZ_Q); |
4d4559b04c59
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changeset
|
690 dst = jmp(dst, (uint8_t *)z80_print_regs_exit); |
4d4559b04c59
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parents:
diff
changeset
|
691 } else { |
4d4559b04c59
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changeset
|
692 dst = zcycles(dst, 4 * inst->immed); |
4d4559b04c59
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parents:
diff
changeset
|
693 } |
4d4559b04c59
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changeset
|
694 break; |
243
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242
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|
695 //case Z80_HALT: |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff
changeset
|
696 case Z80_DI: |
243
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242
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|
697 dst = zcycles(dst, 4); |
2f069a0b487e
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242
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changeset
|
698 dst = mov_irdisp8(dst, 0, CONTEXT, offsetof(z80_context, iff1), SZ_B); |
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242
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changeset
|
699 dst = mov_irdisp8(dst, 0, CONTEXT, offsetof(z80_context, iff2), SZ_B); |
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242
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changeset
|
700 break; |
213
4d4559b04c59
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
701 case Z80_EI: |
243
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242
diff
changeset
|
702 //TODO: Implement interrupt enable latency of 1 instruction afer EI |
2f069a0b487e
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242
diff
changeset
|
703 dst = zcycles(dst, 4); |
2f069a0b487e
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242
diff
changeset
|
704 dst = mov_irdisp8(dst, 1, CONTEXT, offsetof(z80_context, iff1), SZ_B); |
2f069a0b487e
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242
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changeset
|
705 dst = mov_irdisp8(dst, 1, CONTEXT, offsetof(z80_context, iff2), SZ_B); |
2f069a0b487e
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242
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changeset
|
706 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
707 case Z80_IM: |
243
2f069a0b487e
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242
diff
changeset
|
708 dst = zcycles(dst, 4); |
2f069a0b487e
Implement EI, DI and IM in the Z80 core
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242
diff
changeset
|
709 dst = mov_irdisp8(dst, inst->immed, CONTEXT, offsetof(z80_context, im), SZ_B); |
2f069a0b487e
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242
diff
changeset
|
710 break; |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
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246
diff
changeset
|
711 case Z80_RLC: |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
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parents:
246
diff
changeset
|
712 cycles = inst->immed == 1 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8); |
682e505f5757
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246
diff
changeset
|
713 dst = zcycles(dst, cycles); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
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246
diff
changeset
|
714 if (inst->reg == Z80_UNUSED) { |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
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246
diff
changeset
|
715 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
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246
diff
changeset
|
716 dst = zcycles(dst, 1); |
682e505f5757
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parents:
246
diff
changeset
|
717 } else { |
682e505f5757
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parents:
246
diff
changeset
|
718 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
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246
diff
changeset
|
719 } |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
720 dst = rol_ir(dst, 1, dst_op.base, SZ_B); |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
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246
diff
changeset
|
721 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
682e505f5757
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246
diff
changeset
|
722 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
723 //TODO: Implement half-carry flag |
682e505f5757
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246
diff
changeset
|
724 dst = cmp_ir(dst, 0, dst_op.base, SZ_B); |
682e505f5757
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246
diff
changeset
|
725 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
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246
diff
changeset
|
726 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
682e505f5757
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246
diff
changeset
|
727 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
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246
diff
changeset
|
728 if (inst->reg == Z80_UNUSED) { |
682e505f5757
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246
diff
changeset
|
729 dst = z80_save_result(dst, inst); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
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parents:
246
diff
changeset
|
730 } else { |
682e505f5757
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parents:
246
diff
changeset
|
731 dst = z80_save_reg(dst, inst, opts); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
732 } |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
733 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
734 case Z80_RL: |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
735 cycles = inst->immed == 1 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
736 dst = zcycles(dst, cycles); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
737 if (inst->reg == Z80_UNUSED) { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
738 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
739 dst = zcycles(dst, 1); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
740 } else { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
741 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
742 } |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
743 dst = bt_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
744 dst = rcl_ir(dst, 1, dst_op.base, SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
745 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
746 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
747 //TODO: Implement half-carry flag |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
748 dst = cmp_ir(dst, 0, dst_op.base, SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
749 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
750 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
751 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
752 if (inst->reg == Z80_UNUSED) { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
753 dst = z80_save_result(dst, inst); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
754 } else { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
755 dst = z80_save_reg(dst, inst, opts); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
756 } |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
757 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
758 case Z80_RRC: |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
759 cycles = inst->immed == 1 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
760 dst = zcycles(dst, cycles); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
761 if (inst->reg == Z80_UNUSED) { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
762 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
763 dst = zcycles(dst, 1); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
764 } else { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
765 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
766 } |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
767 dst = ror_ir(dst, 1, dst_op.base, SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
768 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
769 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
770 //TODO: Implement half-carry flag |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
771 dst = cmp_ir(dst, 0, dst_op.base, SZ_B); |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
772 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
773 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
774 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
775 if (inst->reg == Z80_UNUSED) { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
776 dst = z80_save_result(dst, inst); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
777 } else { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
778 dst = z80_save_reg(dst, inst, opts); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
779 } |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
780 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
781 case Z80_RR: |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
782 cycles = inst->immed == 1 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8); |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
783 dst = zcycles(dst, cycles); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
784 if (inst->reg == Z80_UNUSED) { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
785 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
786 dst = zcycles(dst, 1); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
787 } else { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
788 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
789 } |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
790 dst = bt_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
791 dst = rcr_ir(dst, 1, dst_op.base, SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
792 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
793 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
794 //TODO: Implement half-carry flag |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
795 dst = cmp_ir(dst, 0, dst_op.base, SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
796 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
797 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
798 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
799 if (inst->reg == Z80_UNUSED) { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
800 dst = z80_save_result(dst, inst); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
801 } else { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
802 dst = z80_save_reg(dst, inst, opts); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
803 } |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
804 break; |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
805 /*case Z80_SLA: |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
806 case Z80_SRA: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
807 case Z80_SLL: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
808 case Z80_SRL: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
809 case Z80_RLD: |
239
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
810 case Z80_RRD:*/ |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
811 case Z80_BIT: |
239
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
812 cycles = (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) ? 8 : 16; |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
813 dst = zcycles(dst, cycles); |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
814 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
815 if (inst->addr_mode != Z80_REG) { |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
816 //Reads normally take 3 cycles, but the read at the end of a bit instruction takes 4 |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
817 dst = zcycles(dst, 1); |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
818 } |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
819 dst = bt_ir(dst, inst->immed, src_op.base, SZ_B); |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
820 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_Z)); |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
821 break; |
247
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
822 case Z80_SET: |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
823 cycles = (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) ? 8 : 16; |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
824 dst = zcycles(dst, cycles); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
825 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
826 if (inst->addr_mode != Z80_REG) { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
827 //Reads normally take 3 cycles, but the read in the middle of a set instruction takes 4 |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
828 dst = zcycles(dst, 1); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
829 } |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
830 dst = bts_ir(dst, inst->immed, src_op.base, SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
831 if (inst->addr_mode != Z80_REG) { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
832 dst = z80_save_result(dst, inst); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
833 } |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
834 break; |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
835 case Z80_RES: |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
836 cycles = (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) ? 8 : 16; |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
837 dst = zcycles(dst, cycles); |
682e505f5757
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246
diff
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838 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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839 if (inst->addr_mode != Z80_REG) { |
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|
840 //Reads normally take 3 cycles, but the read in the middle of a set instruction takes 4 |
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841 dst = zcycles(dst, 1); |
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|
842 } |
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|
843 dst = btr_ir(dst, inst->immed, src_op.base, SZ_B); |
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diff
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|
844 if (inst->addr_mode != Z80_REG) { |
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246
diff
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|
845 dst = z80_save_result(dst, inst); |
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|
846 } |
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diff
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|
847 break; |
236
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|
848 case Z80_JP: { |
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|
849 cycles = 4; |
239
a5bea9711a46
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238
diff
changeset
|
850 if (inst->addr_mode != Z80_REG) { |
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diff
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|
851 cycles += 6; |
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diff
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|
852 } else if(inst->ea_reg == Z80_IX || inst->ea_reg == Z80_IY) { |
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|
853 cycles += 4; |
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|
854 } |
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|
855 dst = zcycles(dst, cycles); |
239
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238
diff
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|
856 if (inst->addr_mode != Z80_REG_INDIRECT && inst->immed < 0x4000) { |
236
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|
857 uint8_t * call_dst = z80_get_native_address(context, inst->immed); |
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|
858 if (!call_dst) { |
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|
859 opts->deferred = defer_address(opts->deferred, inst->immed, dst + 1); |
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|
860 //fake address to force large displacement |
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861 call_dst = dst + 256; |
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diff
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|
862 } |
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|
863 dst = jmp(dst, call_dst); |
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235
diff
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|
864 } else { |
239
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238
diff
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|
865 if (inst->addr_mode == Z80_REG_INDIRECT) { |
236
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diff
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|
866 dst = mov_rr(dst, opts->regs[inst->ea_reg], SCRATCH1, SZ_W); |
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235
diff
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|
867 } else { |
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|
868 dst = mov_ir(dst, inst->immed, SCRATCH1, SZ_W); |
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diff
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|
869 } |
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|
870 dst = call(dst, (uint8_t *)z80_native_addr); |
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|
871 dst = jmp_r(dst, SCRATCH1); |
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235
diff
changeset
|
872 } |
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diff
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|
873 break; |
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235
diff
changeset
|
874 } |
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235
diff
changeset
|
875 case Z80_JPCC: { |
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235
diff
changeset
|
876 dst = zcycles(dst, 7);//T States: 4,3 |
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235
diff
changeset
|
877 uint8_t cond = CC_Z; |
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235
diff
changeset
|
878 switch (inst->reg) |
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235
diff
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|
879 { |
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diff
changeset
|
880 case Z80_CC_NZ: |
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diff
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|
881 cond = CC_NZ; |
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diff
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|
882 case Z80_CC_Z: |
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235
diff
changeset
|
883 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_Z), SZ_B); |
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235
diff
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|
884 break; |
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diff
changeset
|
885 case Z80_CC_NC: |
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235
diff
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|
886 cond = CC_NZ; |
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235
diff
changeset
|
887 case Z80_CC_C: |
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235
diff
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|
888 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
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235
diff
changeset
|
889 break; |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
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236
diff
changeset
|
890 case Z80_CC_PO: |
827ebce557bf
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Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
891 cond = CC_NZ; |
827ebce557bf
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236
diff
changeset
|
892 case Z80_CC_PE: |
827ebce557bf
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236
diff
changeset
|
893 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_PV), SZ_B); |
827ebce557bf
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Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
894 break; |
827ebce557bf
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236
diff
changeset
|
895 case Z80_CC_P: |
827ebce557bf
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Mike Pavone <pavone@retrodev.com>
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236
diff
changeset
|
896 case Z80_CC_M: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
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236
diff
changeset
|
897 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_S), SZ_B); |
827ebce557bf
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parents:
236
diff
changeset
|
898 break; |
236
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parents:
235
diff
changeset
|
899 } |
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235
diff
changeset
|
900 uint8_t *no_jump_off = dst+1; |
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235
diff
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|
901 dst = jcc(dst, cond, dst+2); |
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235
diff
changeset
|
902 dst = zcycles(dst, 5);//T States: 5 |
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235
diff
changeset
|
903 uint16_t dest_addr = inst->immed; |
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235
diff
changeset
|
904 if (dest_addr < 0x4000) { |
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235
diff
changeset
|
905 uint8_t * call_dst = z80_get_native_address(context, dest_addr); |
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235
diff
changeset
|
906 if (!call_dst) { |
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235
diff
changeset
|
907 opts->deferred = defer_address(opts->deferred, dest_addr, dst + 1); |
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235
diff
changeset
|
908 //fake address to force large displacement |
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235
diff
changeset
|
909 call_dst = dst + 256; |
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235
diff
changeset
|
910 } |
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235
diff
changeset
|
911 dst = jmp(dst, call_dst); |
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235
diff
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|
912 } else { |
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235
diff
changeset
|
913 dst = mov_ir(dst, dest_addr, SCRATCH1, SZ_W); |
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235
diff
changeset
|
914 dst = call(dst, (uint8_t *)z80_native_addr); |
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235
diff
changeset
|
915 dst = jmp_r(dst, SCRATCH1); |
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235
diff
changeset
|
916 } |
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235
diff
changeset
|
917 *no_jump_off = dst - (no_jump_off+1); |
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235
diff
changeset
|
918 break; |
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parents:
235
diff
changeset
|
919 } |
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235
diff
changeset
|
920 case Z80_JR: { |
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235
diff
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|
921 dst = zcycles(dst, 12);//T States: 4,3,5 |
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235
diff
changeset
|
922 uint16_t dest_addr = address + inst->immed + 2; |
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235
diff
changeset
|
923 if (dest_addr < 0x4000) { |
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235
diff
changeset
|
924 uint8_t * call_dst = z80_get_native_address(context, dest_addr); |
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235
diff
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|
925 if (!call_dst) { |
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235
diff
changeset
|
926 opts->deferred = defer_address(opts->deferred, dest_addr, dst + 1); |
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235
diff
changeset
|
927 //fake address to force large displacement |
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235
diff
changeset
|
928 call_dst = dst + 256; |
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235
diff
changeset
|
929 } |
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235
diff
changeset
|
930 dst = jmp(dst, call_dst); |
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235
diff
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|
931 } else { |
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235
diff
changeset
|
932 dst = mov_ir(dst, dest_addr, SCRATCH1, SZ_W); |
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235
diff
changeset
|
933 dst = call(dst, (uint8_t *)z80_native_addr); |
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235
diff
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|
934 dst = jmp_r(dst, SCRATCH1); |
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235
diff
changeset
|
935 } |
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235
diff
changeset
|
936 break; |
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Mike Pavone <pavone@retrodev.com>
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235
diff
changeset
|
937 } |
235
d9bf8e61c33c
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Mike Pavone <pavone@retrodev.com>
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213
diff
changeset
|
938 case Z80_JRCC: { |
d9bf8e61c33c
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diff
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|
939 dst = zcycles(dst, 7);//T States: 4,3 |
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213
diff
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|
940 uint8_t cond = CC_Z; |
d9bf8e61c33c
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213
diff
changeset
|
941 switch (inst->reg) |
d9bf8e61c33c
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213
diff
changeset
|
942 { |
d9bf8e61c33c
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213
diff
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|
943 case Z80_CC_NZ: |
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213
diff
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|
944 cond = CC_NZ; |
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diff
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|
945 case Z80_CC_Z: |
d9bf8e61c33c
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diff
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|
946 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_Z), SZ_B); |
d9bf8e61c33c
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parents:
213
diff
changeset
|
947 break; |
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diff
changeset
|
948 case Z80_CC_NC: |
d9bf8e61c33c
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213
diff
changeset
|
949 cond = CC_NZ; |
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213
diff
changeset
|
950 case Z80_CC_C: |
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diff
changeset
|
951 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
d9bf8e61c33c
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diff
changeset
|
952 break; |
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953 } |
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954 uint8_t *no_jump_off = dst+1; |
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955 dst = jcc(dst, cond, dst+2); |
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956 dst = zcycles(dst, 5);//T States: 5 |
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957 uint16_t dest_addr = address + inst->immed + 2; |
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958 if (dest_addr < 0x4000) { |
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959 uint8_t * call_dst = z80_get_native_address(context, dest_addr); |
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960 if (!call_dst) { |
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961 opts->deferred = defer_address(opts->deferred, dest_addr, dst + 1); |
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962 //fake address to force large displacement |
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963 call_dst = dst + 256; |
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964 } |
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965 dst = jmp(dst, call_dst); |
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966 } else { |
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967 dst = mov_ir(dst, dest_addr, SCRATCH1, SZ_W); |
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968 dst = call(dst, (uint8_t *)z80_native_addr); |
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969 dst = jmp_r(dst, SCRATCH1); |
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970 } |
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971 *no_jump_off = dst - (no_jump_off+1); |
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972 break; |
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973 } |
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974 case Z80_DJNZ: |
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975 dst = zcycles(dst, 8);//T States: 5,3 |
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976 dst = sub_ir(dst, 1, opts->regs[Z80_B], SZ_B); |
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977 uint8_t *no_jump_off = dst+1; |
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978 dst = jcc(dst, CC_Z, dst+2); |
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979 dst = zcycles(dst, 5);//T States: 5 |
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980 uint16_t dest_addr = address + inst->immed + 2; |
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981 if (dest_addr < 0x4000) { |
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982 uint8_t * call_dst = z80_get_native_address(context, dest_addr); |
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983 if (!call_dst) { |
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984 opts->deferred = defer_address(opts->deferred, dest_addr, dst + 1); |
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985 //fake address to force large displacement |
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986 call_dst = dst + 256; |
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987 } |
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988 dst = jmp(dst, call_dst); |
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989 } else { |
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990 dst = mov_ir(dst, dest_addr, SCRATCH1, SZ_W); |
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991 dst = call(dst, (uint8_t *)z80_native_addr); |
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992 dst = jmp_r(dst, SCRATCH1); |
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993 } |
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994 *no_jump_off = dst - (no_jump_off+1); |
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995 break; |
235
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996 case Z80_CALL: { |
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997 dst = zcycles(dst, 11);//T States: 4,3,4 |
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998 dst = sub_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
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999 dst = mov_ir(dst, address + 3, SCRATCH2, SZ_W); |
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1000 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
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1001 dst = call(dst, (uint8_t *)z80_write_word_highfirst);//T States: 3, 3 |
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1002 if (inst->immed < 0x4000) { |
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1003 uint8_t * call_dst = z80_get_native_address(context, inst->immed); |
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1004 if (!call_dst) { |
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1005 opts->deferred = defer_address(opts->deferred, inst->immed, dst + 1); |
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1006 //fake address to force large displacement |
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1007 call_dst = dst + 256; |
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1008 } |
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1009 dst = jmp(dst, call_dst); |
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1010 } else { |
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1011 dst = mov_ir(dst, inst->immed, SCRATCH1, SZ_W); |
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1012 dst = call(dst, (uint8_t *)z80_native_addr); |
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1013 dst = jmp_r(dst, SCRATCH1); |
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1014 } |
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1015 break; |
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1016 } |
238
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1017 case Z80_CALLCC: |
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1018 dst = zcycles(dst, 10);//T States: 4,3,3 (false case) |
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1019 uint8_t cond = CC_Z; |
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1020 switch (inst->reg) |
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1021 { |
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1022 case Z80_CC_NZ: |
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1023 cond = CC_NZ; |
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1024 case Z80_CC_Z: |
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1025 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_Z), SZ_B); |
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1026 break; |
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1027 case Z80_CC_NC: |
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1028 cond = CC_NZ; |
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1029 case Z80_CC_C: |
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1030 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
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1031 break; |
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|
1032 case Z80_CC_PO: |
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1033 cond = CC_NZ; |
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1034 case Z80_CC_PE: |
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1035 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_PV), SZ_B); |
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1036 break; |
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1037 case Z80_CC_P: |
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1038 case Z80_CC_M: |
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|
1039 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_S), SZ_B); |
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1040 break; |
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|
1041 } |
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|
1042 uint8_t *no_call_off = dst+1; |
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1043 dst = jcc(dst, cond, dst+2); |
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1044 dst = zcycles(dst, 1);//Last of the above T states takes an extra cycle in the true case |
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1045 dst = sub_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
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1046 dst = mov_ir(dst, address + 3, SCRATCH2, SZ_W); |
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|
1047 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
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1048 dst = call(dst, (uint8_t *)z80_write_word_highfirst);//T States: 3, 3 |
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1049 if (inst->immed < 0x4000) { |
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|
1050 uint8_t * call_dst = z80_get_native_address(context, inst->immed); |
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|
1051 if (!call_dst) { |
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|
1052 opts->deferred = defer_address(opts->deferred, inst->immed, dst + 1); |
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|
1053 //fake address to force large displacement |
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|
1054 call_dst = dst + 256; |
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|
1055 } |
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|
1056 dst = jmp(dst, call_dst); |
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|
1057 } else { |
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|
1058 dst = mov_ir(dst, inst->immed, SCRATCH1, SZ_W); |
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|
1059 dst = call(dst, (uint8_t *)z80_native_addr); |
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|
1060 dst = jmp_r(dst, SCRATCH1); |
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1061 } |
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|
1062 *no_call_off = dst - (no_call_off+1); |
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|
1063 break; |
213
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|
1064 case Z80_RET: |
235
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1065 dst = zcycles(dst, 4);//T States: 4 |
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1066 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
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1067 dst = call(dst, (uint8_t *)z80_read_word);//T STates: 3, 3 |
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1068 dst = add_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
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1069 dst = call(dst, (uint8_t *)z80_native_addr); |
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1070 dst = jmp_r(dst, SCRATCH1); |
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1071 break; |
246
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|
1072 case Z80_RETCC: { |
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1073 dst = zcycles(dst, 5);//T States: 5 |
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1074 uint8_t cond = CC_Z; |
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1075 switch (inst->reg) |
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1076 { |
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1077 case Z80_CC_NZ: |
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1078 cond = CC_NZ; |
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1079 case Z80_CC_Z: |
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1080 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_Z), SZ_B); |
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1081 break; |
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1082 case Z80_CC_NC: |
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1083 cond = CC_NZ; |
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1084 case Z80_CC_C: |
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1085 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
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1086 break; |
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1087 case Z80_CC_PO: |
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1088 cond = CC_NZ; |
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1089 case Z80_CC_PE: |
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1090 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_PV), SZ_B); |
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|
1091 break; |
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|
1092 case Z80_CC_P: |
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1093 case Z80_CC_M: |
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1094 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_S), SZ_B); |
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|
1095 break; |
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|
1096 } |
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|
1097 uint8_t *no_call_off = dst+1; |
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1098 dst = jcc(dst, cond, dst+2); |
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1099 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
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1100 dst = call(dst, (uint8_t *)z80_read_word);//T STates: 3, 3 |
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1101 dst = add_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
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1102 dst = call(dst, (uint8_t *)z80_native_addr); |
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1103 dst = jmp_r(dst, SCRATCH1); |
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1104 *no_call_off = dst - (no_call_off+1); |
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|
1105 break; |
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1106 } |
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|
1107 /*case Z80_RETI: |
241
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|
1108 case Z80_RETN:*/ |
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|
1109 case Z80_RST: { |
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|
1110 //RST is basically CALL to an address in page 0 |
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|
1111 dst = zcycles(dst, 5);//T States: 5 |
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|
1112 dst = sub_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
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|
1113 dst = mov_ir(dst, address + 3, SCRATCH2, SZ_W); |
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|
1114 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
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|
1115 dst = call(dst, (uint8_t *)z80_write_word_highfirst);//T States: 3, 3 |
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239
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|
1116 uint8_t * call_dst = z80_get_native_address(context, inst->immed); |
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|
1117 if (!call_dst) { |
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|
1118 opts->deferred = defer_address(opts->deferred, inst->immed, dst + 1); |
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|
1119 //fake address to force large displacement |
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|
1120 call_dst = dst + 256; |
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|
1121 } |
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|
1122 dst = jmp(dst, call_dst); |
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Implement EX, EXX and RST in Z80 core
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|
1123 break; |
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|
1124 } |
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|
1125 /*case Z80_IN: |
213
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|
1126 case Z80_INI: |
4d4559b04c59
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diff
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|
1127 case Z80_INIR: |
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|
1128 case Z80_IND: |
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Mike Pavone <pavone@retrodev.com>
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|
1129 case Z80_INDR: |
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diff
changeset
|
1130 case Z80_OUT: |
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Mike Pavone <pavone@retrodev.com>
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|
1131 case Z80_OUTI: |
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Mike Pavone <pavone@retrodev.com>
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changeset
|
1132 case Z80_OTIR: |
4d4559b04c59
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diff
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|
1133 case Z80_OUTD: |
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|
1134 case Z80_OTDR:*/ |
235
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|
1135 default: { |
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|
1136 char disbuf[80]; |
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|
1137 z80_disasm(inst, disbuf); |
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|
1138 fprintf(stderr, "unimplemented instruction: %s\n", disbuf); |
213
4d4559b04c59
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diff
changeset
|
1139 exit(1); |
4d4559b04c59
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|
1140 } |
235
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|
1141 } |
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|
1142 return dst; |
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|
1143 } |
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|
1144 |
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|
1145 uint8_t * z80_get_native_address(z80_context * context, uint32_t address) |
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|
1146 { |
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|
1147 native_map_slot *map; |
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|
1148 if (address < 0x4000) { |
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1149 address &= 0x1FFF; |
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1150 map = context->static_code_map; |
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1151 } else if (address >= 0x8000) { |
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|
1152 address &= 0x7FFF; |
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1153 map = context->banked_code_map + context->bank_reg; |
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1154 } else { |
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|
1155 return NULL; |
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|
1156 } |
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1157 if (!map->base || !map->offsets || map->offsets[address] == INVALID_OFFSET) { |
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|
1158 return NULL; |
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|
1159 } |
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|
1160 return map->base + map->offsets[address]; |
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|
1161 } |
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|
1162 |
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|
1163 //TODO: Record z80 instruction size and code size for addresses to support modification of translated code |
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1164 void z80_map_native_address(z80_context * context, uint32_t address, uint8_t * native_address) |
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1165 { |
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|
1166 native_map_slot *map; |
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|
1167 if (address < 0x4000) { |
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1168 address &= 0x1FFF; |
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1169 map = context->static_code_map; |
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1170 } else if (address >= 0x8000) { |
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|
1171 address &= 0x7FFF; |
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1172 map = context->banked_code_map + context->bank_reg; |
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1173 if (!map->offsets) { |
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|
1174 map->offsets = malloc(sizeof(int32_t) * 0x8000); |
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1175 memset(map->offsets, 0xFF, sizeof(int32_t) * 0x8000); |
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1176 } |
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1177 } else { |
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1178 return; |
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1179 } |
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1180 if (!map->base) { |
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1181 map->base = native_address; |
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1182 } |
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1183 map->offsets[address] = native_address - map->base; |
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1184 } |
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1185 |
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1186 uint8_t * z80_get_native_address_trans(z80_context * context, uint32_t address) |
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1187 { |
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1188 uint8_t * addr = z80_get_native_address(context, address); |
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1189 if (!addr) { |
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1190 translate_z80_stream(context, address); |
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1191 addr = z80_get_native_address(context, address); |
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1192 } |
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1193 return addr; |
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1194 } |
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1195 |
248
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1196 //uint32_t max_size = 0; |
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1197 |
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1198 void translate_z80_stream(z80_context * context, uint32_t address) |
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1199 { |
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1200 char disbuf[80]; |
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1201 if (z80_get_native_address(context, address)) { |
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1202 return; |
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1203 } |
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1204 x86_z80_options * opts = context->options; |
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1205 uint8_t * encoded = NULL, *next; |
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1206 if (address < 0x4000) { |
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1207 encoded = context->mem_pointers[0] + (address & 0x1FFF); |
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1208 } else if(address >= 0x8000 && context->mem_pointers[1]) { |
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1209 encoded = context->mem_pointers[1] + (address & 0x7FFF); |
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1210 } |
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1211 while (encoded != NULL) |
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1212 { |
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1213 z80inst inst; |
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1214 printf("translating Z80 code at address %X\n", address); |
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1215 do { |
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1216 if (opts->code_end-opts->cur_code < MAX_NATIVE_SIZE) { |
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1217 if (opts->code_end-opts->cur_code < 5) { |
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1218 puts("out of code memory, not enough space for jmp to next chunk"); |
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1219 exit(1); |
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1220 } |
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1221 size_t size = 1024*1024; |
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1222 opts->cur_code = alloc_code(&size); |
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1223 opts->code_end = opts->cur_code + size; |
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1224 jmp(opts->cur_code, opts->cur_code); |
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1225 } |
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1226 if (address > 0x4000 & address < 0x8000) { |
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1227 opts->cur_code = xor_rr(opts->cur_code, RDI, RDI, SZ_D); |
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1228 opts->cur_code = call(opts->cur_code, (uint8_t *)exit); |
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1229 break; |
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1230 } |
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1231 uint8_t * existing = z80_get_native_address(context, address); |
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diff
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1232 if (existing) { |
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1233 opts->cur_code = jmp(opts->cur_code, existing); |
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1234 break; |
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1235 } |
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1236 next = z80_decode(encoded, &inst); |
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1237 z80_disasm(&inst, disbuf); |
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Get Z80 core working for simple programs
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1238 if (inst.op == Z80_NOP) { |
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1239 printf("%X\t%s(%d)\n", address, disbuf, inst.immed); |
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1240 } else { |
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diff
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|
1241 printf("%X\t%s\n", address, disbuf); |
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diff
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1242 } |
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diff
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1243 z80_map_native_address(context, address, opts->cur_code); |
248
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Implement ADC and SBC in Z80 core (untested)
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|
1244 uint8_t *after = translate_z80inst(&inst, opts->cur_code, context, address); |
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Implement ADC and SBC in Z80 core (untested)
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|
1245 //max_size = (after - opts->cur_code) > max_size ? (after - opts->cur_code) : max_size; |
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1246 opts->cur_code = after; |
235
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1247 address += next-encoded; |
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Get Z80 core working for simple programs
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diff
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1248 encoded = next; |
246
ed548c77b598
Implement RETCC in Z80 core.
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243
diff
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|
1249 } while (!(inst.op == Z80_RET || inst.op == Z80_RETI || inst.op == Z80_RETN || inst.op == Z80_JP || (inst.op = Z80_NOP && inst.immed == 42))); |
235
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1250 process_deferred(&opts->deferred, context, (native_addr_func)z80_get_native_address); |
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diff
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|
1251 if (opts->deferred) { |
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diff
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1252 address = opts->deferred->address; |
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diff
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|
1253 printf("defferred address: %X\n", address); |
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diff
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|
1254 if (address < 0x4000) { |
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|
1255 encoded = context->mem_pointers[0] + (address & 0x1FFF); |
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1256 } else if (address > 0x8000 && context->mem_pointers[1]) { |
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|
1257 encoded = context->mem_pointers[1] + (address & 0x7FFF); |
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1258 } else { |
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Get Z80 core working for simple programs
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diff
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|
1259 printf("attempt to translate non-memory address: %X\n", address); |
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diff
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|
1260 exit(1); |
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diff
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|
1261 } |
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Get Z80 core working for simple programs
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|
1262 } else { |
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Get Z80 core working for simple programs
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diff
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|
1263 encoded = NULL; |
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diff
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|
1264 } |
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diff
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|
1265 } |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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|
1266 } |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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1267 |
235
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1268 void init_x86_z80_opts(x86_z80_options * options) |
213
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Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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|
1269 { |
235
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1270 options->flags = 0; |
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1271 options->regs[Z80_B] = BH; |
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1272 options->regs[Z80_C] = RBX; |
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1273 options->regs[Z80_D] = CH; |
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1274 options->regs[Z80_E] = RCX; |
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1275 options->regs[Z80_H] = AH; |
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|
1276 options->regs[Z80_L] = RAX; |
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1277 options->regs[Z80_IXH] = DH; |
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1278 options->regs[Z80_IXL] = RDX; |
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|
1279 options->regs[Z80_IYH] = -1; |
239
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
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1280 options->regs[Z80_IYL] = R8; |
235
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1281 options->regs[Z80_I] = -1; |
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1282 options->regs[Z80_R] = -1; |
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1283 options->regs[Z80_A] = R10; |
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1284 options->regs[Z80_BC] = RBX; |
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1285 options->regs[Z80_DE] = RCX; |
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|
1286 options->regs[Z80_HL] = RAX; |
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|
1287 options->regs[Z80_SP] = R9; |
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1288 options->regs[Z80_AF] = -1; |
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1289 options->regs[Z80_IX] = RDX; |
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1290 options->regs[Z80_IY] = R8; |
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1291 size_t size = 1024 * 1024; |
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1292 options->cur_code = alloc_code(&size); |
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1293 options->code_end = options->cur_code + size; |
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1294 options->deferred = NULL; |
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1295 } |
235
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1296 |
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1297 void init_z80_context(z80_context * context, x86_z80_options * options) |
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1298 { |
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1299 memset(context, 0, sizeof(*context)); |
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1300 context->static_code_map = malloc(sizeof(context->static_code_map)); |
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1301 context->static_code_map->offsets = malloc(sizeof(int32_t) * 0x2000); |
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1302 memset(context->static_code_map->offsets, 0xFF, sizeof(int32_t) * 0x2000); |
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1303 context->banked_code_map = malloc(sizeof(native_map_slot) * (1 << 9)); |
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1304 context->options = options; |
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1305 } |
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1306 |
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1307 void z80_reset(z80_context * context) |
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1308 { |
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1309 context->native_pc = z80_get_native_address_trans(context, 0); |
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1310 } |
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1311 |
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1312 |