Mercurial > repos > blastem
annotate z80_to_x86.c @ 591:966b46c68942
Get Z80 core back into compileable state
author | Michael Pavone <pavone@retrodev.com> |
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date | Wed, 17 Dec 2014 09:53:51 -0800 |
parents | ea80559c67cb |
children | 4ff7bbb3943b |
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1 /* |
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2 Copyright 2013 Michael Pavone |
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The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
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3 This file is part of BlastEm. |
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4 BlastEm is free software distributed under the terms of the GNU General Public License version 3 or greater. See COPYING for full license text. |
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5 */ |
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6 #include "z80inst.h" |
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7 #include "z80_to_x86.h" |
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8 #include "gen_x86.h" |
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9 #include "mem.h" |
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10 #include <stdio.h> |
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11 #include <stdlib.h> |
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12 #include <stddef.h> |
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13 #include <string.h> |
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14 |
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15 #define MODE_UNUSED (MODE_IMMED-1) |
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16 |
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17 #define ZCYCLES RBP |
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18 #define ZLIMIT RDI |
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19 #define SCRATCH1 R13 |
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20 #define SCRATCH2 R14 |
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21 #define CONTEXT RSI |
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22 |
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23 //#define DO_DEBUG_PRINT |
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24 |
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25 #ifdef DO_DEBUG_PRINT |
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26 #define dprintf printf |
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27 #else |
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28 #define dprintf |
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29 #endif |
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30 |
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31 void z80_read_byte(); |
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32 void z80_read_word(); |
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33 void z80_write_byte(); |
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34 void z80_write_word_highfirst(); |
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35 void z80_write_word_lowfirst(); |
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36 void z80_save_context(); |
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37 void z80_native_addr(); |
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38 void z80_do_sync(); |
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39 void z80_handle_cycle_limit_int(); |
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40 void z80_retrans_stub(); |
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41 void z80_io_read(); |
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42 void z80_io_write(); |
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43 void z80_halt(); |
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44 void z80_save_context(); |
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45 void z80_load_context(); |
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46 |
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47 uint8_t z80_size(z80inst * inst) |
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48 { |
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49 uint8_t reg = (inst->reg & 0x1F); |
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50 if (reg != Z80_UNUSED && reg != Z80_USE_IMMED) { |
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51 return reg < Z80_BC ? SZ_B : SZ_W; |
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52 } |
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53 //TODO: Handle any necessary special cases |
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54 return SZ_B; |
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55 } |
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56 |
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57 void translate_z80_reg(z80inst * inst, host_ea * ea, z80_options * opts) |
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58 { |
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59 code_info *code = &opts->gen.code; |
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60 if (inst->reg == Z80_USE_IMMED) { |
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61 ea->mode = MODE_IMMED; |
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62 ea->disp = inst->immed; |
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63 } else if ((inst->reg & 0x1F) == Z80_UNUSED) { |
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64 ea->mode = MODE_UNUSED; |
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65 } else { |
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66 ea->mode = MODE_REG_DIRECT; |
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67 if (inst->reg == Z80_IYH) { |
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68 if ((inst->addr_mode & 0x1F) == Z80_REG && inst->ea_reg == Z80_IYL) { |
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69 mov_rr(code, opts->regs[Z80_IY], opts->gen.scratch1, SZ_W); |
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70 ror_ir(code, 8, opts->gen.scratch1, SZ_W); |
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71 ea->base = opts->gen.scratch1; |
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72 } else { |
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73 ea->base = opts->regs[Z80_IYL]; |
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74 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W); |
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75 } |
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76 } else if(opts->regs[inst->reg] >= 0) { |
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77 ea->base = opts->regs[inst->reg]; |
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78 if (ea->base >= AH && ea->base <= BH) { |
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79 if ((inst->addr_mode & 0x1F) == Z80_REG) { |
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80 uint8_t other_reg = opts->regs[inst->ea_reg]; |
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81 if (other_reg >= R8 || (other_reg >= RSP && other_reg <= RDI)) { |
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82 //we can't mix an *H reg with a register that requires the REX prefix |
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83 ea->base = opts->regs[z80_low_reg(inst->reg)]; |
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84 ror_ir(code, 8, ea->base, SZ_W); |
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85 } |
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86 } else if((inst->addr_mode & 0x1F) != Z80_UNUSED && (inst->addr_mode & 0x1F) != Z80_IMMED) { |
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87 //temp regs require REX prefix too |
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88 ea->base = opts->regs[z80_low_reg(inst->reg)]; |
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89 ror_ir(code, 8, ea->base, SZ_W); |
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90 } |
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91 } |
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92 } else { |
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93 ea->mode = MODE_REG_DISPLACE8; |
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94 ea->base = opts->gen.context_reg; |
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95 ea->disp = offsetof(z80_context, regs) + inst->reg; |
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96 } |
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97 } |
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98 } |
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99 |
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100 void z80_save_reg(z80inst * inst, z80_options * opts) |
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101 { |
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102 code_info *code = &opts->gen.code; |
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103 if (inst->reg == Z80_IYH) { |
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104 if ((inst->addr_mode & 0x1F) == Z80_REG && inst->ea_reg == Z80_IYL) { |
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105 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W); |
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106 mov_rr(code, opts->gen.scratch1, opts->regs[Z80_IYL], SZ_B); |
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107 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W); |
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108 } else { |
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109 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W); |
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110 } |
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111 } else if (opts->regs[inst->reg] >= AH && opts->regs[inst->reg] <= BH) { |
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112 if ((inst->addr_mode & 0x1F) == Z80_REG) { |
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113 uint8_t other_reg = opts->regs[inst->ea_reg]; |
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114 if (other_reg >= R8 || (other_reg >= RSP && other_reg <= RDI)) { |
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115 //we can't mix an *H reg with a register that requires the REX prefix |
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116 ror_ir(code, 8, opts->regs[z80_low_reg(inst->reg)], SZ_W); |
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117 } |
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118 } else if((inst->addr_mode & 0x1F) != Z80_UNUSED && (inst->addr_mode & 0x1F) != Z80_IMMED) { |
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119 //temp regs require REX prefix too |
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120 ror_ir(code, 8, opts->regs[z80_low_reg(inst->reg)], SZ_W); |
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121 } |
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122 } |
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123 } |
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124 |
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125 void translate_z80_ea(z80inst * inst, host_ea * ea, z80_options * opts, uint8_t read, uint8_t modify) |
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126 { |
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127 code_info *code = &opts->gen.code; |
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128 uint8_t size, reg, areg; |
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129 ea->mode = MODE_REG_DIRECT; |
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130 areg = read ? opts->gen.scratch1 : opts->gen.scratch2; |
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131 switch(inst->addr_mode & 0x1F) |
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132 { |
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133 case Z80_REG: |
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134 if (inst->ea_reg == Z80_IYH) { |
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135 if (inst->reg == Z80_IYL) { |
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136 mov_rr(code, opts->regs[Z80_IY], opts->gen.scratch1, SZ_W); |
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137 ror_ir(code, 8, opts->gen.scratch1, SZ_W); |
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138 ea->base = opts->gen.scratch1; |
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139 } else { |
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140 ea->base = opts->regs[Z80_IYL]; |
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141 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W); |
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142 } |
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143 } else { |
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144 ea->base = opts->regs[inst->ea_reg]; |
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145 if (ea->base >= AH && ea->base <= BH && inst->reg != Z80_UNUSED && inst->reg != Z80_USE_IMMED) { |
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146 uint8_t other_reg = opts->regs[inst->reg]; |
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147 if (other_reg >= R8 || (other_reg >= RSP && other_reg <= RDI)) { |
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148 //we can't mix an *H reg with a register that requires the REX prefix |
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149 ea->base = opts->regs[z80_low_reg(inst->ea_reg)]; |
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150 ror_ir(code, 8, ea->base, SZ_W); |
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151 } |
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152 } |
213
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153 } |
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154 break; |
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155 case Z80_REG_INDIRECT: |
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156 mov_rr(code, opts->regs[inst->ea_reg], areg, SZ_W); |
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157 size = z80_size(inst); |
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158 if (read) { |
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159 if (modify) { |
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160 //push_r(code, opts->gen.scratch1); |
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161 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, offsetof(z80_context, scratch1), SZ_W); |
213
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162 } |
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163 if (size == SZ_B) { |
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164 call(code, opts->read_8); |
213
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165 } else { |
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166 call(code, opts->read_16); |
213
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167 } |
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168 if (modify) { |
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169 //pop_r(code, opts->gen.scratch2); |
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170 mov_rdispr(code, opts->gen.context_reg, offsetof(z80_context, scratch1), opts->gen.scratch2, SZ_W); |
213
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171 } |
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172 } |
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173 ea->base = opts->gen.scratch1; |
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174 break; |
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175 case Z80_IMMED: |
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176 ea->mode = MODE_IMMED; |
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177 ea->disp = inst->immed; |
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178 break; |
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179 case Z80_IMMED_INDIRECT: |
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180 mov_ir(code, inst->immed, areg, SZ_W); |
213
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181 size = z80_size(inst); |
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182 if (read) { |
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183 /*if (modify) { |
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184 push_r(code, opts->gen.scratch1); |
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185 }*/ |
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186 if (size == SZ_B) { |
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187 call(code, (uint8_t *)z80_read_byte); |
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188 } else { |
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189 call(code, (uint8_t *)z80_read_word); |
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190 } |
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191 if (modify) { |
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192 //pop_r(code, opts->gen.scratch2); |
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193 mov_ir(code, inst->immed, opts->gen.scratch2, SZ_W); |
213
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194 } |
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195 } |
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196 ea->base = opts->gen.scratch1; |
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197 break; |
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198 case Z80_IX_DISPLACE: |
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199 case Z80_IY_DISPLACE: |
300
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200 reg = opts->regs[(inst->addr_mode & 0x1F) == Z80_IX_DISPLACE ? Z80_IX : Z80_IY]; |
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201 mov_rr(code, reg, areg, SZ_W); |
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202 add_ir(code, inst->ea_reg & 0x80 ? inst->ea_reg - 256 : inst->ea_reg, areg, SZ_W); |
213
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203 size = z80_size(inst); |
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204 if (read) { |
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205 if (modify) { |
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206 //push_r(code, opts->gen.scratch1); |
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207 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, offsetof(z80_context, scratch1), SZ_W); |
213
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208 } |
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209 if (size == SZ_B) { |
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210 call(code, (uint8_t *)z80_read_byte); |
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211 } else { |
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212 call(code, (uint8_t *)z80_read_word); |
213
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213 } |
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214 if (modify) { |
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215 //pop_r(code, opts->gen.scratch2); |
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216 mov_rdispr(code, opts->gen.context_reg, offsetof(z80_context, scratch1), opts->gen.scratch2, SZ_W); |
213
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217 } |
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218 } |
590
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219 ea->base = opts->gen.scratch1; |
213
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220 break; |
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221 case Z80_UNUSED: |
235
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222 ea->mode = MODE_UNUSED; |
213
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223 break; |
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224 default: |
300
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225 fprintf(stderr, "Unrecognized Z80 addressing mode %d\n", inst->addr_mode & 0x1F); |
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226 exit(1); |
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227 } |
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228 } |
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229 |
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230 void z80_save_ea(code_info *code, z80inst * inst, z80_options * opts) |
213
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231 { |
267
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232 if ((inst->addr_mode & 0x1F) == Z80_REG) { |
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233 if (inst->ea_reg == Z80_IYH) { |
312
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234 if (inst->reg == Z80_IYL) { |
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235 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W); |
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236 mov_rr(code, opts->gen.scratch1, opts->regs[Z80_IYL], SZ_B); |
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237 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W); |
312
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238 } else { |
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239 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W); |
312
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240 } |
267
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241 } else if (inst->reg != Z80_UNUSED && inst->reg != Z80_USE_IMMED && opts->regs[inst->ea_reg] >= AH && opts->regs[inst->ea_reg] <= BH) { |
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242 uint8_t other_reg = opts->regs[inst->reg]; |
269
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243 if (other_reg >= R8 || (other_reg >= RSP && other_reg <= RDI)) { |
267
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244 //we can't mix an *H reg with a register that requires the REX prefix |
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245 ror_ir(code, 8, opts->regs[z80_low_reg(inst->ea_reg)], SZ_W); |
267
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246 } |
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247 } |
213
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248 } |
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249 } |
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250 |
591
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251 void z80_save_result(code_info *code, z80inst * inst) |
213
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252 { |
253
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253 switch(inst->addr_mode & 0x1f) |
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254 { |
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255 case Z80_REG_INDIRECT: |
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256 case Z80_IMMED_INDIRECT: |
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257 case Z80_IX_DISPLACE: |
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258 case Z80_IY_DISPLACE: |
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259 if (z80_size(inst) == SZ_B) { |
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260 call(code, (uint8_t *)z80_write_byte); |
253
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261 } else { |
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262 call(code, (uint8_t *)z80_write_word_lowfirst); |
253
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263 } |
213
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264 } |
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265 } |
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266 |
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267 enum { |
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268 DONT_READ=0, |
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269 READ |
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270 }; |
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271 |
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272 enum { |
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273 DONT_MODIFY=0, |
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274 MODIFY |
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275 }; |
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276 |
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277 uint8_t zf_off(uint8_t flag) |
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278 { |
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279 return offsetof(z80_context, flags) + flag; |
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280 } |
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281 |
241
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282 uint8_t zaf_off(uint8_t flag) |
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283 { |
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284 return offsetof(z80_context, alt_flags) + flag; |
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285 } |
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286 |
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287 uint8_t zar_off(uint8_t reg) |
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288 { |
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289 return offsetof(z80_context, alt_regs) + reg; |
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290 } |
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291 |
235
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292 void z80_print_regs_exit(z80_context * context) |
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293 { |
505
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The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
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294 printf("A: %X\nB: %X\nC: %X\nD: %X\nE: %X\nHL: %X\nIX: %X\nIY: %X\nSP: %X\n\nIM: %d, IFF1: %d, IFF2: %d\n", |
235
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295 context->regs[Z80_A], context->regs[Z80_B], context->regs[Z80_C], |
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296 context->regs[Z80_D], context->regs[Z80_E], |
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297 (context->regs[Z80_H] << 8) | context->regs[Z80_L], |
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298 (context->regs[Z80_IXH] << 8) | context->regs[Z80_IXL], |
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299 (context->regs[Z80_IYH] << 8) | context->regs[Z80_IYL], |
243
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300 context->sp, context->im, context->iff1, context->iff2); |
241
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301 puts("--Alternate Regs--"); |
505
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302 printf("A: %X\nB: %X\nC: %X\nD: %X\nE: %X\nHL: %X\nIX: %X\nIY: %X\n", |
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303 context->alt_regs[Z80_A], context->alt_regs[Z80_B], context->alt_regs[Z80_C], |
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304 context->alt_regs[Z80_D], context->alt_regs[Z80_E], |
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305 (context->alt_regs[Z80_H] << 8) | context->alt_regs[Z80_L], |
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306 (context->alt_regs[Z80_IXH] << 8) | context->alt_regs[Z80_IXL], |
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307 (context->alt_regs[Z80_IYH] << 8) | context->alt_regs[Z80_IYL]); |
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308 exit(0); |
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309 } |
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310 |
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311 void translate_z80inst(z80inst * inst, z80_context * context, uint16_t address) |
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312 { |
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313 uint32_t num_cycles; |
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314 host_ea src_op, dst_op; |
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315 uint8_t size; |
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316 z80_options *opts = context->options; |
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317 uint8_t * start = opts->gen.code.cur; |
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318 code_info *code = &opts->gen.code; |
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319 check_cycles_int(&opts->gen, address); |
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320 switch(inst->op) |
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321 { |
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322 case Z80_LD: |
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323 size = z80_size(inst); |
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324 switch (inst->addr_mode & 0x1F) |
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325 { |
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326 case Z80_REG: |
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327 case Z80_REG_INDIRECT: |
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328 num_cycles = size == SZ_B ? 4 : 6; |
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329 if (inst->ea_reg == Z80_IX || inst->ea_reg == Z80_IY) { |
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330 num_cycles += 4; |
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331 } |
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332 if (inst->reg == Z80_I || inst->ea_reg == Z80_I) { |
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333 num_cycles += 5; |
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334 } |
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335 break; |
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336 case Z80_IMMED: |
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337 num_cycles = size == SZ_B ? 7 : 10; |
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338 break; |
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339 case Z80_IMMED_INDIRECT: |
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340 num_cycles = 10; |
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341 break; |
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342 case Z80_IX_DISPLACE: |
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343 case Z80_IY_DISPLACE: |
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344 num_cycles = 16; |
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345 break; |
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346 } |
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347 if ((inst->reg >= Z80_IXL && inst->reg <= Z80_IYH) || inst->reg == Z80_IX || inst->reg == Z80_IY) { |
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348 num_cycles += 4; |
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349 } |
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350 cycles(&opts->gen, num_cycles); |
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351 if (inst->addr_mode & Z80_DIR) { |
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352 translate_z80_ea(inst, &dst_op, opts, DONT_READ, MODIFY); |
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353 translate_z80_reg(inst, &src_op, opts); |
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354 } else { |
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355 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY); |
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356 translate_z80_reg(inst, &dst_op, opts); |
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357 } |
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358 if (src_op.mode == MODE_REG_DIRECT) { |
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359 if(dst_op.mode == MODE_REG_DISPLACE8) { |
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360 mov_rrdisp(code, src_op.base, dst_op.base, dst_op.disp, size); |
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361 } else { |
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362 mov_rr(code, src_op.base, dst_op.base, size); |
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363 } |
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364 } else if(src_op.mode == MODE_IMMED) { |
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365 mov_ir(code, src_op.disp, dst_op.base, size); |
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366 } else { |
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367 mov_rdispr(code, src_op.base, src_op.disp, dst_op.base, size); |
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368 } |
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369 z80_save_reg(inst, opts); |
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370 z80_save_ea(code, inst, opts); |
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371 if (inst->addr_mode & Z80_DIR) { |
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372 z80_save_result(code, inst); |
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373 } |
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374 break; |
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375 case Z80_PUSH: |
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376 cycles(&opts->gen, (inst->reg == Z80_IX || inst->reg == Z80_IY) ? 9 : 5); |
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377 sub_ir(code, 2, opts->regs[Z80_SP], SZ_W); |
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378 if (inst->reg == Z80_AF) { |
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379 mov_rr(code, opts->regs[Z80_A], opts->gen.scratch1, SZ_B); |
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380 shl_ir(code, 8, opts->gen.scratch1, SZ_W); |
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381 mov_rdispr(code, opts->gen.context_reg, zf_off(ZF_S), opts->gen.scratch1, SZ_B); |
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382 shl_ir(code, 1, opts->gen.scratch1, SZ_B); |
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383 or_rdispr(code, opts->gen.context_reg, zf_off(ZF_Z), opts->gen.scratch1, SZ_B); |
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384 shl_ir(code, 2, opts->gen.scratch1, SZ_B); |
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385 or_rdispr(code, opts->gen.context_reg, zf_off(ZF_H), opts->gen.scratch1, SZ_B); |
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386 shl_ir(code, 2, opts->gen.scratch1, SZ_B); |
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387 or_rdispr(code, opts->gen.context_reg, zf_off(ZF_PV), opts->gen.scratch1, SZ_B); |
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388 shl_ir(code, 1, opts->gen.scratch1, SZ_B); |
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389 or_rdispr(code, opts->gen.context_reg, zf_off(ZF_N), opts->gen.scratch1, SZ_B); |
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390 shl_ir(code, 1, opts->gen.scratch1, SZ_B); |
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391 or_rdispr(code, opts->gen.context_reg, zf_off(ZF_C), opts->gen.scratch1, SZ_B); |
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392 } else { |
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393 translate_z80_reg(inst, &src_op, opts); |
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394 mov_rr(code, src_op.base, opts->gen.scratch1, SZ_W); |
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395 } |
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396 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch2, SZ_W); |
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397 call(code, (uint8_t *)z80_write_word_highfirst); |
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398 //no call to save_z80_reg needed since there's no chance we'll use the only |
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399 //the upper half of a register pair |
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400 break; |
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401 case Z80_POP: |
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402 cycles(&opts->gen, (inst->reg == Z80_IX || inst->reg == Z80_IY) ? 8 : 4); |
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403 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W); |
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404 call(code, (uint8_t *)z80_read_word); |
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405 add_ir(code, 2, opts->regs[Z80_SP], SZ_W); |
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406 if (inst->reg == Z80_AF) { |
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407 |
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408 bt_ir(code, 0, opts->gen.scratch1, SZ_W); |
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409 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
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410 bt_ir(code, 1, opts->gen.scratch1, SZ_W); |
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411 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_N)); |
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412 bt_ir(code, 2, opts->gen.scratch1, SZ_W); |
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413 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_PV)); |
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414 bt_ir(code, 4, opts->gen.scratch1, SZ_W); |
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415 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H)); |
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416 bt_ir(code, 6, opts->gen.scratch1, SZ_W); |
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417 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_Z)); |
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418 bt_ir(code, 7, opts->gen.scratch1, SZ_W); |
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419 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_S)); |
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420 shr_ir(code, 8, opts->gen.scratch1, SZ_W); |
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421 mov_rr(code, opts->gen.scratch1, opts->regs[Z80_A], SZ_B); |
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422 } else { |
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423 translate_z80_reg(inst, &src_op, opts); |
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424 mov_rr(code, opts->gen.scratch1, src_op.base, SZ_W); |
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425 } |
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426 //no call to save_z80_reg needed since there's no chance we'll use the only |
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427 //the upper half of a register pair |
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428 break; |
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429 case Z80_EX: |
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430 if (inst->addr_mode == Z80_REG || inst->reg == Z80_HL) { |
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431 num_cycles = 4; |
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432 } else { |
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433 num_cycles = 8; |
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434 } |
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435 cycles(&opts->gen, num_cycles); |
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436 if (inst->addr_mode == Z80_REG) { |
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437 if(inst->reg == Z80_AF) { |
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438 mov_rr(code, opts->regs[Z80_A], opts->gen.scratch1, SZ_B); |
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439 mov_rdispr(code, opts->gen.context_reg, zar_off(Z80_A), opts->regs[Z80_A], SZ_B); |
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440 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zar_off(Z80_A), SZ_B); |
505
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The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
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441 |
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442 //Flags are currently word aligned, so we can move |
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443 //them efficiently a word at a time |
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444 for (int f = ZF_C; f < ZF_NUM; f+=2) { |
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445 mov_rdispr(code, opts->gen.context_reg, zf_off(f), opts->gen.scratch1, SZ_W); |
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446 mov_rdispr(code, opts->gen.context_reg, zaf_off(f), opts->gen.scratch2, SZ_W); |
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447 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zaf_off(f), SZ_W); |
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448 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(f), SZ_W); |
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449 } |
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450 } else { |
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451 xchg_rr(code, opts->regs[Z80_DE], opts->regs[Z80_HL], SZ_W); |
241
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452 } |
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453 } else { |
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454 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W); |
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455 call(code, (uint8_t *)z80_read_byte); |
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456 xchg_rr(code, opts->regs[inst->reg], opts->gen.scratch1, SZ_B); |
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457 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch2, SZ_W); |
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458 call(code, (uint8_t *)z80_write_byte); |
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459 cycles(&opts->gen, 1); |
241
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460 uint8_t high_reg = z80_high_reg(inst->reg); |
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461 uint8_t use_reg; |
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462 //even though some of the upper halves can be used directly |
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463 //the limitations on mixing *H regs with the REX prefix |
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464 //prevent us from taking advantage of it |
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465 use_reg = opts->regs[inst->reg]; |
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466 ror_ir(code, 8, use_reg, SZ_W); |
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467 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W); |
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468 add_ir(code, 1, opts->gen.scratch1, SZ_W); |
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469 call(code, (uint8_t *)z80_read_byte); |
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470 xchg_rr(code, use_reg, opts->gen.scratch1, SZ_B); |
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471 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch2, SZ_W); |
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472 add_ir(code, 1, opts->gen.scratch2, SZ_W); |
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473 call(code, (uint8_t *)z80_write_byte); |
241
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474 //restore reg to normal rotation |
591
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475 ror_ir(code, 8, use_reg, SZ_W); |
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476 cycles(&opts->gen, 2); |
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477 } |
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478 break; |
213
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479 case Z80_EXX: |
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480 cycles(&opts->gen, 4); |
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481 mov_rr(code, opts->regs[Z80_BC], opts->gen.scratch1, SZ_W); |
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482 mov_rr(code, opts->regs[Z80_HL], opts->gen.scratch2, SZ_W); |
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483 mov_rdispr(code, opts->gen.context_reg, zar_off(Z80_C), opts->regs[Z80_BC], SZ_W); |
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484 mov_rdispr(code, opts->gen.context_reg, zar_off(Z80_L), opts->regs[Z80_HL], SZ_W); |
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485 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zar_off(Z80_C), SZ_W); |
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486 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zar_off(Z80_L), SZ_W); |
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487 mov_rr(code, opts->regs[Z80_DE], opts->gen.scratch1, SZ_W); |
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488 mov_rdispr(code, opts->gen.context_reg, zar_off(Z80_E), opts->regs[Z80_DE], SZ_W); |
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489 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zar_off(Z80_E), SZ_W); |
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490 break; |
272 | 491 case Z80_LDI: { |
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492 cycles(&opts->gen, 8); |
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493 mov_rr(code, opts->regs[Z80_HL], opts->gen.scratch1, SZ_W); |
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494 call(code, (uint8_t *)z80_read_byte); |
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495 mov_rr(code, opts->regs[Z80_DE], opts->gen.scratch2, SZ_W); |
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496 call(code, (uint8_t *)z80_write_byte); |
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497 cycles(&opts->gen, 2); |
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498 add_ir(code, 1, opts->regs[Z80_DE], SZ_W); |
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499 add_ir(code, 1, opts->regs[Z80_HL], SZ_W); |
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500 sub_ir(code, 1, opts->regs[Z80_BC], SZ_W); |
272 | 501 //TODO: Implement half-carry |
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502 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
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503 setcc_rdisp(code, CC_NZ, opts->gen.context_reg, zf_off(ZF_PV)); |
272 | 504 break; |
505 } | |
261
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506 case Z80_LDIR: { |
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507 cycles(&opts->gen, 8); |
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508 mov_rr(code, opts->regs[Z80_HL], opts->gen.scratch1, SZ_W); |
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509 call(code, (uint8_t *)z80_read_byte); |
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510 mov_rr(code, opts->regs[Z80_DE], opts->gen.scratch2, SZ_W); |
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511 call(code, (uint8_t *)z80_write_byte); |
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512 add_ir(code, 1, opts->regs[Z80_DE], SZ_W); |
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513 add_ir(code, 1, opts->regs[Z80_HL], SZ_W); |
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The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
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514 |
591
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515 sub_ir(code, 1, opts->regs[Z80_BC], SZ_W); |
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516 uint8_t * cont = code->cur+1; |
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517 jcc(code, CC_Z, code->cur+2); |
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518 cycles(&opts->gen, 7); |
261
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519 //TODO: Figure out what the flag state should be here |
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520 //TODO: Figure out whether an interrupt can interrupt this |
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521 jmp(code, start); |
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522 *cont = code->cur - (cont + 1); |
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523 cycles(&opts->gen, 2); |
261
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524 //TODO: Implement half-carry |
591
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525 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
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526 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_PV), SZ_B); |
261
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527 break; |
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528 } |
273 | 529 case Z80_LDD: { |
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530 cycles(&opts->gen, 8); |
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531 mov_rr(code, opts->regs[Z80_HL], opts->gen.scratch1, SZ_W); |
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532 call(code, (uint8_t *)z80_read_byte); |
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533 mov_rr(code, opts->regs[Z80_DE], opts->gen.scratch2, SZ_W); |
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534 call(code, (uint8_t *)z80_write_byte); |
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535 cycles(&opts->gen, 2); |
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536 sub_ir(code, 1, opts->regs[Z80_DE], SZ_W); |
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537 sub_ir(code, 1, opts->regs[Z80_HL], SZ_W); |
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538 sub_ir(code, 1, opts->regs[Z80_BC], SZ_W); |
273 | 539 //TODO: Implement half-carry |
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540 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
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541 setcc_rdisp(code, CC_NZ, opts->gen.context_reg, zf_off(ZF_PV)); |
273 | 542 break; |
543 } | |
544 case Z80_LDDR: { | |
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545 cycles(&opts->gen, 8); |
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546 mov_rr(code, opts->regs[Z80_HL], opts->gen.scratch1, SZ_W); |
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547 call(code, (uint8_t *)z80_read_byte); |
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548 mov_rr(code, opts->regs[Z80_DE], opts->gen.scratch2, SZ_W); |
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549 call(code, (uint8_t *)z80_write_byte); |
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550 sub_ir(code, 1, opts->regs[Z80_DE], SZ_W); |
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551 sub_ir(code, 1, opts->regs[Z80_HL], SZ_W); |
505
b7b7a1cab44a
The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
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552 |
591
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553 sub_ir(code, 1, opts->regs[Z80_BC], SZ_W); |
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554 uint8_t * cont = code->cur+1; |
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555 jcc(code, CC_Z, code->cur+2); |
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556 cycles(&opts->gen, 7); |
273 | 557 //TODO: Figure out what the flag state should be here |
558 //TODO: Figure out whether an interrupt can interrupt this | |
591
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559 jmp(code, start); |
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560 *cont = code->cur - (cont + 1); |
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561 cycles(&opts->gen, 2); |
273 | 562 //TODO: Implement half-carry |
591
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563 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
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564 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_PV), SZ_B); |
273 | 565 break; |
566 } | |
567 /*case Z80_CPI: | |
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568 case Z80_CPIR: |
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569 case Z80_CPD: |
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570 case Z80_CPDR: |
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571 break;*/ |
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572 case Z80_ADD: |
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573 num_cycles = 4; |
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574 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
591
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575 num_cycles += 12; |
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576 } else if(inst->addr_mode == Z80_IMMED) { |
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577 num_cycles += 3; |
213
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578 } else if(z80_size(inst) == SZ_W) { |
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579 num_cycles += 4; |
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580 } |
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581 cycles(&opts->gen, num_cycles); |
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582 translate_z80_reg(inst, &dst_op, opts); |
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583 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY); |
213
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584 if (src_op.mode == MODE_REG_DIRECT) { |
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585 add_rr(code, src_op.base, dst_op.base, z80_size(inst)); |
213
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586 } else { |
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587 add_ir(code, src_op.disp, dst_op.base, z80_size(inst)); |
213
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588 } |
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589 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
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590 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
213
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591 //TODO: Implement half-carry flag |
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592 if (z80_size(inst) == SZ_B) { |
591
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593 setcc_rdisp(code, CC_O, opts->gen.context_reg, zf_off(ZF_PV)); |
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594 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
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595 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
213
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596 } |
591
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597 z80_save_reg(inst, opts); |
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598 z80_save_ea(code, inst, opts); |
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599 break; |
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600 case Z80_ADC: |
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601 num_cycles = 4; |
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602 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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603 num_cycles += 12; |
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604 } else if(inst->addr_mode == Z80_IMMED) { |
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605 num_cycles += 3; |
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606 } else if(z80_size(inst) == SZ_W) { |
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607 num_cycles += 4; |
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608 } |
591
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609 cycles(&opts->gen, num_cycles); |
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610 translate_z80_reg(inst, &dst_op, opts); |
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611 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY); |
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612 bt_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B); |
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613 if (src_op.mode == MODE_REG_DIRECT) { |
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614 adc_rr(code, src_op.base, dst_op.base, z80_size(inst)); |
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615 } else { |
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616 adc_ir(code, src_op.disp, dst_op.base, z80_size(inst)); |
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617 } |
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618 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
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619 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
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620 //TODO: Implement half-carry flag |
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621 setcc_rdisp(code, CC_O, opts->gen.context_reg, zf_off(ZF_PV)); |
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622 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
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623 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
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624 z80_save_reg(inst, opts); |
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625 z80_save_ea(code, inst, opts); |
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626 break; |
213
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627 case Z80_SUB: |
591
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628 num_cycles = 4; |
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629 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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630 num_cycles += 12; |
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631 } else if(inst->addr_mode == Z80_IMMED) { |
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632 num_cycles += 3; |
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633 } |
591
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634 cycles(&opts->gen, num_cycles); |
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635 translate_z80_reg(inst, &dst_op, opts); |
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636 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY); |
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637 if (src_op.mode == MODE_REG_DIRECT) { |
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638 sub_rr(code, src_op.base, dst_op.base, z80_size(inst)); |
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639 } else { |
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640 sub_ir(code, src_op.disp, dst_op.base, z80_size(inst)); |
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641 } |
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642 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
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643 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
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644 setcc_rdisp(code, CC_O, opts->gen.context_reg, zf_off(ZF_PV)); |
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645 //TODO: Implement half-carry flag |
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646 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
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647 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
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648 z80_save_reg(inst, opts); |
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649 z80_save_ea(code, inst, opts); |
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650 break; |
248
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651 case Z80_SBC: |
591
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652 num_cycles = 4; |
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653 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
591
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654 num_cycles += 12; |
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655 } else if(inst->addr_mode == Z80_IMMED) { |
591
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656 num_cycles += 3; |
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657 } else if(z80_size(inst) == SZ_W) { |
591
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658 num_cycles += 4; |
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659 } |
591
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660 cycles(&opts->gen, num_cycles); |
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661 translate_z80_reg(inst, &dst_op, opts); |
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662 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY); |
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663 bt_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B); |
248
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664 if (src_op.mode == MODE_REG_DIRECT) { |
591
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665 sbb_rr(code, src_op.base, dst_op.base, z80_size(inst)); |
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666 } else { |
591
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667 sbb_ir(code, src_op.disp, dst_op.base, z80_size(inst)); |
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668 } |
591
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669 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
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670 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
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671 //TODO: Implement half-carry flag |
591
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672 setcc_rdisp(code, CC_O, opts->gen.context_reg, zf_off(ZF_PV)); |
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673 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
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674 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
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675 z80_save_reg(inst, opts); |
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676 z80_save_ea(code, inst, opts); |
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677 break; |
213
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678 case Z80_AND: |
591
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679 num_cycles = 4; |
236
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680 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
591
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681 num_cycles += 12; |
236
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682 } else if(inst->addr_mode == Z80_IMMED) { |
591
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683 num_cycles += 3; |
236
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684 } else if(z80_size(inst) == SZ_W) { |
591
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685 num_cycles += 4; |
236
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686 } |
591
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687 cycles(&opts->gen, num_cycles); |
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688 translate_z80_reg(inst, &dst_op, opts); |
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689 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY); |
236
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690 if (src_op.mode == MODE_REG_DIRECT) { |
591
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691 and_rr(code, src_op.base, dst_op.base, z80_size(inst)); |
236
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692 } else { |
591
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693 and_ir(code, src_op.disp, dst_op.base, z80_size(inst)); |
236
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694 } |
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695 //TODO: Cleanup flags |
591
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696 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
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697 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
236
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698 //TODO: Implement half-carry flag |
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699 if (z80_size(inst) == SZ_B) { |
591
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700 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV)); |
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701 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
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702 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
236
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703 } |
591
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|
704 z80_save_reg(inst, opts); |
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|
705 z80_save_ea(code, inst, opts); |
236
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706 break; |
213
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|
707 case Z80_OR: |
591
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708 num_cycles = 4; |
236
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709 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
591
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710 num_cycles += 12; |
236
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711 } else if(inst->addr_mode == Z80_IMMED) { |
591
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712 num_cycles += 3; |
236
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713 } else if(z80_size(inst) == SZ_W) { |
591
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|
714 num_cycles += 4; |
236
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715 } |
591
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716 cycles(&opts->gen, num_cycles); |
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|
717 translate_z80_reg(inst, &dst_op, opts); |
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|
718 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY); |
236
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719 if (src_op.mode == MODE_REG_DIRECT) { |
591
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|
720 or_rr(code, src_op.base, dst_op.base, z80_size(inst)); |
236
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721 } else { |
591
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722 or_ir(code, src_op.disp, dst_op.base, z80_size(inst)); |
236
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723 } |
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724 //TODO: Cleanup flags |
591
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|
725 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
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|
726 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
236
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727 //TODO: Implement half-carry flag |
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728 if (z80_size(inst) == SZ_B) { |
591
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|
729 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV)); |
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changeset
|
730 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
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731 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
236
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732 } |
591
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|
733 z80_save_reg(inst, opts); |
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734 z80_save_ea(code, inst, opts); |
236
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735 break; |
213
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diff
changeset
|
736 case Z80_XOR: |
591
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diff
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|
737 num_cycles = 4; |
236
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738 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
591
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|
739 num_cycles += 12; |
236
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740 } else if(inst->addr_mode == Z80_IMMED) { |
591
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|
741 num_cycles += 3; |
236
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742 } else if(z80_size(inst) == SZ_W) { |
591
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diff
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743 num_cycles += 4; |
236
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|
744 } |
591
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diff
changeset
|
745 cycles(&opts->gen, num_cycles); |
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diff
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|
746 translate_z80_reg(inst, &dst_op, opts); |
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diff
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|
747 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY); |
236
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748 if (src_op.mode == MODE_REG_DIRECT) { |
591
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|
749 xor_rr(code, src_op.base, dst_op.base, z80_size(inst)); |
236
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750 } else { |
591
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751 xor_ir(code, src_op.disp, dst_op.base, z80_size(inst)); |
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752 } |
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|
753 //TODO: Cleanup flags |
591
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changeset
|
754 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
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Get Z80 core back into compileable state
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755 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
236
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756 //TODO: Implement half-carry flag |
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757 if (z80_size(inst) == SZ_B) { |
591
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|
758 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV)); |
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|
759 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
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760 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
236
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761 } |
591
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changeset
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762 z80_save_reg(inst, opts); |
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changeset
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763 z80_save_ea(code, inst, opts); |
236
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|
764 break; |
242 | 765 case Z80_CP: |
591
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diff
changeset
|
766 num_cycles = 4; |
242 | 767 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
591
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diff
changeset
|
768 num_cycles += 12; |
242 | 769 } else if(inst->addr_mode == Z80_IMMED) { |
591
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diff
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|
770 num_cycles += 3; |
242 | 771 } |
591
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diff
changeset
|
772 cycles(&opts->gen, num_cycles); |
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Get Z80 core back into compileable state
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590
diff
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|
773 translate_z80_reg(inst, &dst_op, opts); |
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|
774 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY); |
242 | 775 if (src_op.mode == MODE_REG_DIRECT) { |
591
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|
776 cmp_rr(code, src_op.base, dst_op.base, z80_size(inst)); |
242 | 777 } else { |
591
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778 cmp_ir(code, src_op.disp, dst_op.base, z80_size(inst)); |
242 | 779 } |
591
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|
780 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
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|
781 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
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|
782 setcc_rdisp(code, CC_O, opts->gen.context_reg, zf_off(ZF_PV)); |
242 | 783 //TODO: Implement half-carry flag |
591
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|
784 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
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785 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
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diff
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|
786 z80_save_reg(inst, opts); |
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|
787 z80_save_ea(code, inst, opts); |
242 | 788 break; |
213
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diff
changeset
|
789 case Z80_INC: |
591
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|
790 num_cycles = 4; |
213
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changeset
|
791 if (inst->reg == Z80_IX || inst->reg == Z80_IY) { |
591
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792 num_cycles += 6; |
213
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changeset
|
793 } else if(z80_size(inst) == SZ_W) { |
591
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|
794 num_cycles += 2; |
213
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changeset
|
795 } else if(inst->reg == Z80_IXH || inst->reg == Z80_IXL || inst->reg == Z80_IYH || inst->reg == Z80_IYL || inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
591
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|
796 num_cycles += 4; |
213
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|
797 } |
591
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|
798 cycles(&opts->gen, num_cycles); |
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diff
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|
799 translate_z80_reg(inst, &dst_op, opts); |
213
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changeset
|
800 if (dst_op.mode == MODE_UNUSED) { |
591
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|
801 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY); |
213
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diff
changeset
|
802 } |
591
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|
803 add_ir(code, 1, dst_op.base, z80_size(inst)); |
213
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diff
changeset
|
804 if (z80_size(inst) == SZ_B) { |
591
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changeset
|
805 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
213
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diff
changeset
|
806 //TODO: Implement half-carry flag |
591
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|
807 setcc_rdisp(code, CC_O, opts->gen.context_reg, zf_off(ZF_PV)); |
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diff
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|
808 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
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|
809 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
213
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|
810 } |
591
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|
811 z80_save_reg(inst, opts); |
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|
812 z80_save_ea(code, inst, opts); |
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diff
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|
813 z80_save_result(code, inst); |
213
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diff
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|
814 break; |
236
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|
815 case Z80_DEC: |
591
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|
816 num_cycles = 4; |
236
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817 if (inst->reg == Z80_IX || inst->reg == Z80_IY) { |
591
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|
818 num_cycles += 6; |
236
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819 } else if(z80_size(inst) == SZ_W) { |
591
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|
820 num_cycles += 2; |
236
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821 } else if(inst->reg == Z80_IXH || inst->reg == Z80_IXL || inst->reg == Z80_IYH || inst->reg == Z80_IYL || inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
591
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|
822 num_cycles += 4; |
236
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|
823 } |
591
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|
824 cycles(&opts->gen, num_cycles); |
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|
825 translate_z80_reg(inst, &dst_op, opts); |
236
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|
826 if (dst_op.mode == MODE_UNUSED) { |
591
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|
827 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY); |
236
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828 } |
591
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changeset
|
829 sub_ir(code, 1, dst_op.base, z80_size(inst)); |
236
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|
830 if (z80_size(inst) == SZ_B) { |
591
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changeset
|
831 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
236
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|
832 //TODO: Implement half-carry flag |
591
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diff
changeset
|
833 setcc_rdisp(code, CC_O, opts->gen.context_reg, zf_off(ZF_PV)); |
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diff
changeset
|
834 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
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diff
changeset
|
835 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
236
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|
836 } |
591
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diff
changeset
|
837 z80_save_reg(inst, opts); |
966b46c68942
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diff
changeset
|
838 z80_save_ea(code, inst, opts); |
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diff
changeset
|
839 z80_save_result(code, inst); |
213
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Mike Pavone <pavone@retrodev.com>
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diff
changeset
|
840 break; |
274
be2b845d3e94
Implement CPL and NEG (untested)
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273
diff
changeset
|
841 //case Z80_DAA: |
213
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842 case Z80_CPL: |
591
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843 cycles(&opts->gen, 4); |
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|
844 not_r(code, opts->regs[Z80_A], SZ_B); |
274
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845 //TODO: Implement half-carry flag |
591
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846 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
274
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847 break; |
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848 case Z80_NEG: |
591
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diff
changeset
|
849 cycles(&opts->gen, 8); |
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|
850 neg_r(code, opts->regs[Z80_A], SZ_B); |
274
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273
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851 //TODO: Implement half-carry flag |
591
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852 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
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|
853 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
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854 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
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|
855 setcc_rdisp(code, CC_O, opts->gen.context_reg, zf_off(ZF_PV)); |
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diff
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|
856 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
274
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857 break; |
213
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diff
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|
858 case Z80_CCF: |
591
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|
859 cycles(&opts->gen, 4); |
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|
860 xor_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_C), SZ_B); |
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changeset
|
861 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
257 | 862 //TODO: Implement half-carry flag |
863 break; | |
864 case Z80_SCF: | |
591
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|
865 cycles(&opts->gen, 4); |
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|
866 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_C), SZ_B); |
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diff
changeset
|
867 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
257 | 868 //TODO: Implement half-carry flag |
869 break; | |
213
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diff
changeset
|
870 case Z80_NOP: |
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|
871 if (inst->immed == 42) { |
591
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|
872 call(code, (uint8_t *)z80_save_context); |
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|
873 mov_rr(code, opts->gen.context_reg, RDI, SZ_Q); |
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diff
changeset
|
874 jmp(code, (uint8_t *)z80_print_regs_exit); |
213
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diff
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|
875 } else { |
591
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changeset
|
876 cycles(&opts->gen, 4 * inst->immed); |
213
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Mike Pavone <pavone@retrodev.com>
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diff
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|
877 } |
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changeset
|
878 break; |
285
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879 case Z80_HALT: |
591
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|
880 cycles(&opts->gen, 4); |
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|
881 mov_ir(code, address, opts->gen.scratch1, SZ_W); |
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590
diff
changeset
|
882 uint8_t * call_inst = code->cur; |
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diff
changeset
|
883 call(code, (uint8_t *)z80_halt); |
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diff
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|
884 jmp(code, call_inst); |
285
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|
885 break; |
213
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diff
changeset
|
886 case Z80_DI: |
591
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|
887 cycles(&opts->gen, 4); |
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diff
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|
888 mov_irdisp(code, 0, opts->gen.context_reg, offsetof(z80_context, iff1), SZ_B); |
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|
889 mov_irdisp(code, 0, opts->gen.context_reg, offsetof(z80_context, iff2), SZ_B); |
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changeset
|
890 mov_rdispr(code, opts->gen.context_reg, offsetof(z80_context, sync_cycle), opts->gen.limit, SZ_D); |
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|
891 mov_irdisp(code, 0xFFFFFFFF, opts->gen.context_reg, offsetof(z80_context, int_cycle), SZ_D); |
243
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242
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|
892 break; |
213
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diff
changeset
|
893 case Z80_EI: |
591
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|
894 cycles(&opts->gen, 4); |
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diff
changeset
|
895 mov_rrdisp(code, opts->gen.cycles, opts->gen.context_reg, offsetof(z80_context, int_enable_cycle), SZ_D); |
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changeset
|
896 mov_irdisp(code, 1, opts->gen.context_reg, offsetof(z80_context, iff1), SZ_B); |
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diff
changeset
|
897 mov_irdisp(code, 1, opts->gen.context_reg, offsetof(z80_context, iff2), SZ_B); |
335 | 898 //interrupt enable has a one-instruction latency, minimum instruction duration is 4 cycles |
591
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590
diff
changeset
|
899 add_irdisp(code, 4, opts->gen.context_reg, offsetof(z80_context, int_enable_cycle), SZ_D); |
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590
diff
changeset
|
900 call(code, (uint8_t *)z80_do_sync); |
243
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242
diff
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|
901 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
902 case Z80_IM: |
591
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590
diff
changeset
|
903 cycles(&opts->gen, 4); |
966b46c68942
Get Z80 core back into compileable state
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590
diff
changeset
|
904 mov_irdisp(code, inst->immed, opts->gen.context_reg, offsetof(z80_context, im), SZ_B); |
243
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|
905 break; |
247
682e505f5757
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Mike Pavone <pavone@retrodev.com>
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246
diff
changeset
|
906 case Z80_RLC: |
591
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590
diff
changeset
|
907 num_cycles = inst->immed == 0 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8); |
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Michael Pavone <pavone@retrodev.com>
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590
diff
changeset
|
908 cycles(&opts->gen, num_cycles); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
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295
diff
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|
909 if (inst->addr_mode != Z80_UNUSED) { |
591
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590
diff
changeset
|
910 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
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590
diff
changeset
|
911 translate_z80_reg(inst, &src_op, opts); //For IX/IY variants that also write to a register |
966b46c68942
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590
diff
changeset
|
912 cycles(&opts->gen, 1); |
247
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Mike Pavone <pavone@retrodev.com>
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246
diff
changeset
|
913 } else { |
302
3b831fe32c15
More fixes for confusion between Z80_UNUSED and MODE_UNUSED
Mike Pavone <pavone@retrodev.com>
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301
diff
changeset
|
914 src_op.mode = MODE_UNUSED; |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
915 translate_z80_reg(inst, &dst_op, opts); |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
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246
diff
changeset
|
916 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
917 rol_ir(code, 1, dst_op.base, SZ_B); |
301
6e15509a1257
Compare src_op.mode with the correct constant in shift/rotate instructions
Mike Pavone <pavone@retrodev.com>
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300
diff
changeset
|
918 if (src_op.mode != MODE_UNUSED) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
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590
diff
changeset
|
919 mov_rr(code, dst_op.base, src_op.base, SZ_B); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
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295
diff
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|
920 } |
591
966b46c68942
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diff
changeset
|
921 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
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590
diff
changeset
|
922 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
247
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246
diff
changeset
|
923 //TODO: Implement half-carry flag |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
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590
diff
changeset
|
924 cmp_ir(code, 0, dst_op.base, SZ_B); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
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590
diff
changeset
|
925 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
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590
diff
changeset
|
926 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
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590
diff
changeset
|
927 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
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295
diff
changeset
|
928 if (inst->addr_mode != Z80_UNUSED) { |
591
966b46c68942
Get Z80 core back into compileable state
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590
diff
changeset
|
929 z80_save_result(code, inst); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
930 if (src_op.mode != MODE_UNUSED) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
931 z80_save_reg(inst, opts); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
932 } |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
933 } else { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
934 z80_save_reg(inst, opts); |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
935 } |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
936 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
937 case Z80_RL: |
591
966b46c68942
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Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
938 num_cycles = inst->immed == 0 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
939 cycles(&opts->gen, num_cycles); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
940 if (inst->addr_mode != Z80_UNUSED) { |
591
966b46c68942
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Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
941 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
942 translate_z80_reg(inst, &src_op, opts); //For IX/IY variants that also write to a register |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
943 cycles(&opts->gen, 1); |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
944 } else { |
302
3b831fe32c15
More fixes for confusion between Z80_UNUSED and MODE_UNUSED
Mike Pavone <pavone@retrodev.com>
parents:
301
diff
changeset
|
945 src_op.mode = MODE_UNUSED; |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
946 translate_z80_reg(inst, &dst_op, opts); |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
947 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
948 bt_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B); |
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diff
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|
949 rcl_ir(code, 1, dst_op.base, SZ_B); |
301
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950 if (src_op.mode != MODE_UNUSED) { |
591
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|
951 mov_rr(code, dst_op.base, src_op.base, SZ_B); |
299
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|
952 } |
591
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|
953 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
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diff
changeset
|
954 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
247
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diff
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|
955 //TODO: Implement half-carry flag |
591
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diff
changeset
|
956 cmp_ir(code, 0, dst_op.base, SZ_B); |
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590
diff
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|
957 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV)); |
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958 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
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590
diff
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|
959 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
299
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Mike Pavone <pavone@retrodev.com>
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295
diff
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|
960 if (inst->addr_mode != Z80_UNUSED) { |
591
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|
961 z80_save_result(code, inst); |
299
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diff
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|
962 if (src_op.mode != MODE_UNUSED) { |
591
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diff
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|
963 z80_save_reg(inst, opts); |
299
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295
diff
changeset
|
964 } |
247
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Implement rotation and bit set/reset instructions (untested).
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diff
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|
965 } else { |
591
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diff
changeset
|
966 z80_save_reg(inst, opts); |
247
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246
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|
967 } |
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Mike Pavone <pavone@retrodev.com>
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|
968 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
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diff
changeset
|
969 case Z80_RRC: |
591
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|
970 num_cycles = inst->immed == 0 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8); |
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|
971 cycles(&opts->gen, num_cycles); |
299
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Mike Pavone <pavone@retrodev.com>
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295
diff
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|
972 if (inst->addr_mode != Z80_UNUSED) { |
591
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changeset
|
973 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY); |
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diff
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|
974 translate_z80_reg(inst, &src_op, opts); //For IX/IY variants that also write to a register |
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|
975 cycles(&opts->gen, 1); |
247
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976 } else { |
302
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301
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|
977 src_op.mode = MODE_UNUSED; |
591
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590
diff
changeset
|
978 translate_z80_reg(inst, &dst_op, opts); |
247
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246
diff
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|
979 } |
591
966b46c68942
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changeset
|
980 ror_ir(code, 1, dst_op.base, SZ_B); |
301
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|
981 if (src_op.mode != MODE_UNUSED) { |
591
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diff
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|
982 mov_rr(code, dst_op.base, src_op.base, SZ_B); |
299
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295
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changeset
|
983 } |
591
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diff
changeset
|
984 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
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|
985 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
247
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246
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changeset
|
986 //TODO: Implement half-carry flag |
591
966b46c68942
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diff
changeset
|
987 cmp_ir(code, 0, dst_op.base, SZ_B); |
966b46c68942
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diff
changeset
|
988 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV)); |
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989 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
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|
990 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
299
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295
diff
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|
991 if (inst->addr_mode != Z80_UNUSED) { |
591
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590
diff
changeset
|
992 z80_save_result(code, inst); |
299
42e1a986f2d0
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295
diff
changeset
|
993 if (src_op.mode != MODE_UNUSED) { |
591
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590
diff
changeset
|
994 z80_save_reg(inst, opts); |
299
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diff
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|
995 } |
247
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changeset
|
996 } else { |
591
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parents:
590
diff
changeset
|
997 z80_save_reg(inst, opts); |
247
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|
998 } |
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diff
changeset
|
999 break; |
213
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1000 case Z80_RR: |
591
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590
diff
changeset
|
1001 num_cycles = inst->immed == 0 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8); |
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diff
changeset
|
1002 cycles(&opts->gen, num_cycles); |
299
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295
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changeset
|
1003 if (inst->addr_mode != Z80_UNUSED) { |
591
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changeset
|
1004 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY); |
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diff
changeset
|
1005 translate_z80_reg(inst, &src_op, opts); //For IX/IY variants that also write to a register |
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diff
changeset
|
1006 cycles(&opts->gen, 1); |
247
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246
diff
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|
1007 } else { |
302
3b831fe32c15
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301
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changeset
|
1008 src_op.mode = MODE_UNUSED; |
591
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diff
changeset
|
1009 translate_z80_reg(inst, &dst_op, opts); |
247
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|
1010 } |
591
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changeset
|
1011 bt_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B); |
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changeset
|
1012 rcr_ir(code, 1, dst_op.base, SZ_B); |
301
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changeset
|
1013 if (src_op.mode != MODE_UNUSED) { |
591
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diff
changeset
|
1014 mov_rr(code, dst_op.base, src_op.base, SZ_B); |
299
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|
1015 } |
591
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diff
changeset
|
1016 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
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diff
changeset
|
1017 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
247
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changeset
|
1018 //TODO: Implement half-carry flag |
591
966b46c68942
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590
diff
changeset
|
1019 cmp_ir(code, 0, dst_op.base, SZ_B); |
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diff
changeset
|
1020 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV)); |
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diff
changeset
|
1021 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
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diff
changeset
|
1022 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
299
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295
diff
changeset
|
1023 if (inst->addr_mode != Z80_UNUSED) { |
591
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diff
changeset
|
1024 z80_save_result(code, inst); |
299
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295
diff
changeset
|
1025 if (src_op.mode != MODE_UNUSED) { |
591
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changeset
|
1026 z80_save_reg(inst, opts); |
299
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|
1027 } |
247
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|
1028 } else { |
591
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diff
changeset
|
1029 z80_save_reg(inst, opts); |
247
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|
1030 } |
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changeset
|
1031 break; |
275
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274
diff
changeset
|
1032 case Z80_SLA: |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1033 case Z80_SLL: |
591
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590
diff
changeset
|
1034 num_cycles = inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8; |
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diff
changeset
|
1035 cycles(&opts->gen, num_cycles); |
299
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295
diff
changeset
|
1036 if (inst->addr_mode != Z80_UNUSED) { |
591
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590
diff
changeset
|
1037 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY); |
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590
diff
changeset
|
1038 translate_z80_reg(inst, &src_op, opts); //For IX/IY variants that also write to a register |
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diff
changeset
|
1039 cycles(&opts->gen, 1); |
275
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274
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|
1040 } else { |
302
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301
diff
changeset
|
1041 src_op.mode = MODE_UNUSED; |
591
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diff
changeset
|
1042 translate_z80_reg(inst, &dst_op, opts); |
275
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274
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changeset
|
1043 } |
591
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diff
changeset
|
1044 shl_ir(code, 1, dst_op.base, SZ_B); |
966b46c68942
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590
diff
changeset
|
1045 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
310
bf440db64086
Implement carry flag for shift instructions. Implement weird behavior for bit 0 of SLL. Fix missing break statement in SRL.
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309
diff
changeset
|
1046 if (inst->op == Z80_SLL) { |
591
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590
diff
changeset
|
1047 or_ir(code, 1, dst_op.base, SZ_B); |
310
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309
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|
1048 } |
301
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1049 if (src_op.mode != MODE_UNUSED) { |
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1050 mov_rr(code, dst_op.base, src_op.base, SZ_B); |
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1051 } |
591
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1052 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
275
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1053 //TODO: Implement half-carry flag |
591
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1054 cmp_ir(code, 0, dst_op.base, SZ_B); |
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1055 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV)); |
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1056 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
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1057 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
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1058 if (inst->addr_mode != Z80_UNUSED) { |
591
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1059 z80_save_result(code, inst); |
299
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1060 if (src_op.mode != MODE_UNUSED) { |
591
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|
1061 z80_save_reg(inst, opts); |
299
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1062 } |
275
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1063 } else { |
591
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1064 z80_save_reg(inst, opts); |
275
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1065 } |
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1066 break; |
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1067 case Z80_SRA: |
591
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1068 num_cycles = inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8; |
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1069 cycles(&opts->gen, num_cycles); |
299
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1070 if (inst->addr_mode != Z80_UNUSED) { |
591
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1071 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY); |
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1072 translate_z80_reg(inst, &src_op, opts); //For IX/IY variants that also write to a register |
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1073 cycles(&opts->gen, 1); |
275
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1074 } else { |
302
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1075 src_op.mode = MODE_UNUSED; |
591
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1076 translate_z80_reg(inst, &dst_op, opts); |
275
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1077 } |
591
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|
1078 sar_ir(code, 1, dst_op.base, SZ_B); |
301
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1079 if (src_op.mode != MODE_UNUSED) { |
591
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1080 mov_rr(code, dst_op.base, src_op.base, SZ_B); |
299
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1081 } |
591
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1082 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
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1083 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
275
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1084 //TODO: Implement half-carry flag |
591
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1085 cmp_ir(code, 0, dst_op.base, SZ_B); |
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1086 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV)); |
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1087 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
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1088 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
299
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1089 if (inst->addr_mode != Z80_UNUSED) { |
591
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|
1090 z80_save_result(code, inst); |
299
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1091 if (src_op.mode != MODE_UNUSED) { |
591
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|
1092 z80_save_reg(inst, opts); |
299
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|
1093 } |
275
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1094 } else { |
591
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1095 z80_save_reg(inst, opts); |
275
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1096 } |
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|
1097 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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diff
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|
1098 case Z80_SRL: |
591
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|
1099 num_cycles = inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8; |
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1100 cycles(&opts->gen, num_cycles); |
299
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1101 if (inst->addr_mode != Z80_UNUSED) { |
591
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|
1102 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY); |
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1103 translate_z80_reg(inst, &src_op, opts); //For IX/IY variants that also write to a register |
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1104 cycles(&opts->gen, 1); |
275
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1105 } else { |
302
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1106 src_op.mode = MODE_UNUSED; |
591
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|
1107 translate_z80_reg(inst, &dst_op, opts); |
275
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1108 } |
591
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|
1109 shr_ir(code, 1, dst_op.base, SZ_B); |
301
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1110 if (src_op.mode != MODE_UNUSED) { |
591
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1111 mov_rr(code, dst_op.base, src_op.base, SZ_B); |
299
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1112 } |
591
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|
1113 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
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1114 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
275
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1115 //TODO: Implement half-carry flag |
591
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|
1116 cmp_ir(code, 0, dst_op.base, SZ_B); |
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1117 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV)); |
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1118 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
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1119 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
299
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1120 if (inst->addr_mode != Z80_UNUSED) { |
591
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|
1121 z80_save_result(code, inst); |
299
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1122 if (src_op.mode != MODE_UNUSED) { |
591
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|
1123 z80_save_reg(inst, opts); |
299
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1124 } |
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1125 } else { |
591
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|
1126 z80_save_reg(inst, opts); |
275
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1127 } |
310
bf440db64086
Implement carry flag for shift instructions. Implement weird behavior for bit 0 of SLL. Fix missing break statement in SRL.
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1128 break; |
286 | 1129 case Z80_RLD: |
591
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|
1130 cycles(&opts->gen, 8); |
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|
1131 mov_rr(code, opts->regs[Z80_HL], opts->gen.scratch1, SZ_W); |
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|
1132 call(code, (uint8_t *)z80_read_byte); |
286 | 1133 //Before: (HL) = 0x12, A = 0x34 |
1134 //After: (HL) = 0x24, A = 0x31 | |
591
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1135 mov_rr(code, opts->regs[Z80_A], opts->gen.scratch2, SZ_B); |
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1136 shl_ir(code, 4, opts->gen.scratch1, SZ_W); |
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|
1137 and_ir(code, 0xF, opts->gen.scratch2, SZ_W); |
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|
1138 and_ir(code, 0xFFF, opts->gen.scratch1, SZ_W); |
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|
1139 and_ir(code, 0xF0, opts->regs[Z80_A], SZ_B); |
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|
1140 or_rr(code, opts->gen.scratch2, opts->gen.scratch1, SZ_W); |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
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|
1141 //opts->gen.scratch1 = 0x0124 |
591
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|
1142 ror_ir(code, 8, opts->gen.scratch1, SZ_W); |
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|
1143 cycles(&opts->gen, 4); |
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|
1144 or_rr(code, opts->gen.scratch1, opts->regs[Z80_A], SZ_B); |
287
fb840e0a48cd
Implement RRD and implement flags on RLD
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286
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|
1145 //set flags |
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1146 //TODO: Implement half-carry flag |
591
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|
1147 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
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|
1148 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV)); |
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|
1149 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
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|
1150 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
505
b7b7a1cab44a
The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
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1151 |
591
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1152 mov_rr(code, opts->regs[Z80_HL], opts->gen.scratch2, SZ_W); |
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1153 ror_ir(code, 8, opts->gen.scratch1, SZ_W); |
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1154 call(code, (uint8_t *)z80_write_byte); |
286 | 1155 break; |
287
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1156 case Z80_RRD: |
591
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1157 cycles(&opts->gen, 8); |
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1158 mov_rr(code, opts->regs[Z80_HL], opts->gen.scratch1, SZ_W); |
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1159 call(code, (uint8_t *)z80_read_byte); |
287
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1160 //Before: (HL) = 0x12, A = 0x34 |
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1161 //After: (HL) = 0x41, A = 0x32 |
591
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1162 movzx_rr(code, opts->regs[Z80_A], opts->gen.scratch2, SZ_B, SZ_W); |
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1163 ror_ir(code, 4, opts->gen.scratch1, SZ_W); |
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1164 shl_ir(code, 4, opts->gen.scratch2, SZ_W); |
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1165 and_ir(code, 0xF00F, opts->gen.scratch1, SZ_W); |
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1166 and_ir(code, 0xF0, opts->regs[Z80_A], SZ_B); |
590
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1167 //opts->gen.scratch1 = 0x2001 |
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1168 //opts->gen.scratch2 = 0x0040 |
591
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1169 or_rr(code, opts->gen.scratch2, opts->gen.scratch1, SZ_W); |
590
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1170 //opts->gen.scratch1 = 0x2041 |
591
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1171 ror_ir(code, 8, opts->gen.scratch1, SZ_W); |
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1172 cycles(&opts->gen, 4); |
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1173 shr_ir(code, 4, opts->gen.scratch1, SZ_B); |
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1174 or_rr(code, opts->gen.scratch1, opts->regs[Z80_A], SZ_B); |
287
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1175 //set flags |
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1176 //TODO: Implement half-carry flag |
591
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1177 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
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1178 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV)); |
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1179 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
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1180 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
505
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1181 |
591
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1182 mov_rr(code, opts->regs[Z80_HL], opts->gen.scratch2, SZ_W); |
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1183 ror_ir(code, 8, opts->gen.scratch1, SZ_W); |
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1184 call(code, (uint8_t *)z80_write_byte); |
287
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1185 break; |
308
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1186 case Z80_BIT: { |
591
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1187 num_cycles = (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) ? 8 : 16; |
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1188 cycles(&opts->gen, num_cycles); |
308
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1189 uint8_t bit; |
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1190 if ((inst->addr_mode & 0x1F) == Z80_REG && opts->regs[inst->ea_reg] >= AH && opts->regs[inst->ea_reg] <= BH) { |
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1191 src_op.base = opts->regs[z80_word_reg(inst->ea_reg)]; |
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1192 size = SZ_W; |
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1193 bit = inst->immed + 8; |
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1194 } else { |
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1195 size = SZ_B; |
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1196 bit = inst->immed; |
591
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1197 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY); |
308
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1198 } |
239
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1199 if (inst->addr_mode != Z80_REG) { |
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1200 //Reads normally take 3 cycles, but the read at the end of a bit instruction takes 4 |
591
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1201 cycles(&opts->gen, 1); |
239
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1202 } |
591
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1203 bt_ir(code, bit, src_op.base, size); |
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1204 setcc_rdisp(code, CC_NC, opts->gen.context_reg, zf_off(ZF_Z)); |
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1205 setcc_rdisp(code, CC_NC, opts->gen.context_reg, zf_off(ZF_PV)); |
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1206 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
307
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1207 if (inst->immed == 7) { |
591
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1208 cmp_ir(code, 0, src_op.base, size); |
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1209 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
307
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1210 } else { |
591
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1211 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_S), SZ_B); |
307
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1212 } |
239
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1213 break; |
308
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1214 } |
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1215 case Z80_SET: { |
591
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1216 num_cycles = (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) ? 8 : 16; |
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1217 cycles(&opts->gen, num_cycles); |
308
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1218 uint8_t bit; |
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1219 if ((inst->addr_mode & 0x1F) == Z80_REG && opts->regs[inst->ea_reg] >= AH && opts->regs[inst->ea_reg] <= BH) { |
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1220 src_op.base = opts->regs[z80_word_reg(inst->ea_reg)]; |
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1221 size = SZ_W; |
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1222 bit = inst->immed + 8; |
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1223 } else { |
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1224 size = SZ_B; |
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1225 bit = inst->immed; |
591
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1226 translate_z80_ea(inst, &src_op, opts, READ, MODIFY); |
308
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1227 } |
299
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1228 if (inst->reg != Z80_USE_IMMED) { |
591
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1229 translate_z80_reg(inst, &dst_op, opts); |
299
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1230 } |
247
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1231 if (inst->addr_mode != Z80_REG) { |
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1232 //Reads normally take 3 cycles, but the read in the middle of a set instruction takes 4 |
591
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|
1233 cycles(&opts->gen, 1); |
247
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1234 } |
591
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1235 bts_ir(code, bit, src_op.base, size); |
299
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1236 if (inst->reg != Z80_USE_IMMED) { |
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1237 if (size == SZ_W) { |
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1238 if (dst_op.base >= R8) { |
591
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1239 ror_ir(code, 8, src_op.base, SZ_W); |
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1240 mov_rr(code, opts->regs[z80_low_reg(inst->ea_reg)], dst_op.base, SZ_B); |
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1241 ror_ir(code, 8, src_op.base, SZ_W); |
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1242 } else { |
591
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1243 mov_rr(code, opts->regs[inst->ea_reg], dst_op.base, SZ_B); |
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|
1244 } |
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1245 } else { |
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1246 mov_rr(code, src_op.base, dst_op.base, SZ_B); |
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1247 } |
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1248 } |
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1249 if ((inst->addr_mode & 0x1F) != Z80_REG) { |
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1250 z80_save_result(code, inst); |
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1251 if (inst->reg != Z80_USE_IMMED) { |
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parents:
590
diff
changeset
|
1252 z80_save_reg(inst, opts); |
308
e0e81551fd7e
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1253 } |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1254 } |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1255 break; |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1256 } |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1257 case Z80_RES: { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1258 num_cycles = (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) ? 8 : 16; |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1259 cycles(&opts->gen, num_cycles); |
308
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1260 uint8_t bit; |
e0e81551fd7e
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1261 if ((inst->addr_mode & 0x1F) == Z80_REG && opts->regs[inst->ea_reg] >= AH && opts->regs[inst->ea_reg] <= BH) { |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1262 src_op.base = opts->regs[z80_word_reg(inst->ea_reg)]; |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1263 size = SZ_W; |
e0e81551fd7e
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1264 bit = inst->immed + 8; |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1265 } else { |
e0e81551fd7e
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1266 size = SZ_B; |
e0e81551fd7e
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1267 bit = inst->immed; |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1268 translate_z80_ea(inst, &src_op, opts, READ, MODIFY); |
308
e0e81551fd7e
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1269 } |
e0e81551fd7e
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Mike Pavone <pavone@retrodev.com>
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307
diff
changeset
|
1270 if (inst->reg != Z80_USE_IMMED) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1271 translate_z80_reg(inst, &dst_op, opts); |
308
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1272 } |
e0e81551fd7e
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1273 if (inst->addr_mode != Z80_REG) { |
e0e81551fd7e
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1274 //Reads normally take 3 cycles, but the read in the middle of a set instruction takes 4 |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1275 cycles(&opts->gen, 1); |
308
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307
diff
changeset
|
1276 } |
591
966b46c68942
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590
diff
changeset
|
1277 btr_ir(code, bit, src_op.base, size); |
308
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Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
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parents:
307
diff
changeset
|
1278 if (inst->reg != Z80_USE_IMMED) { |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1279 if (size == SZ_W) { |
e0e81551fd7e
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1280 if (dst_op.base >= R8) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1281 ror_ir(code, 8, src_op.base, SZ_W); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1282 mov_rr(code, opts->regs[z80_low_reg(inst->ea_reg)], dst_op.base, SZ_B); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1283 ror_ir(code, 8, src_op.base, SZ_W); |
308
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Mike Pavone <pavone@retrodev.com>
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307
diff
changeset
|
1284 } else { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1285 mov_rr(code, opts->regs[inst->ea_reg], dst_op.base, SZ_B); |
505
b7b7a1cab44a
The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1286 } |
308
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parents:
307
diff
changeset
|
1287 } else { |
591
966b46c68942
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parents:
590
diff
changeset
|
1288 mov_rr(code, src_op.base, dst_op.base, SZ_B); |
308
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307
diff
changeset
|
1289 } |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1290 } |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1291 if (inst->addr_mode != Z80_REG) { |
591
966b46c68942
Get Z80 core back into compileable state
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parents:
590
diff
changeset
|
1292 z80_save_result(code, inst); |
299
42e1a986f2d0
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Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1293 if (inst->reg != Z80_USE_IMMED) { |
591
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parents:
590
diff
changeset
|
1294 z80_save_reg(inst, opts); |
299
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Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1295 } |
247
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parents:
246
diff
changeset
|
1296 } |
682e505f5757
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parents:
246
diff
changeset
|
1297 break; |
308
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307
diff
changeset
|
1298 } |
236
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235
diff
changeset
|
1299 case Z80_JP: { |
591
966b46c68942
Get Z80 core back into compileable state
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parents:
590
diff
changeset
|
1300 num_cycles = 4; |
506
a3b48a57e847
Fix timing of certain ld and jp instructions in the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
505
diff
changeset
|
1301 if (inst->addr_mode != Z80_REG_INDIRECT) { |
591
966b46c68942
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590
diff
changeset
|
1302 num_cycles += 6; |
236
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235
diff
changeset
|
1303 } else if(inst->ea_reg == Z80_IX || inst->ea_reg == Z80_IY) { |
591
966b46c68942
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590
diff
changeset
|
1304 num_cycles += 4; |
236
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235
diff
changeset
|
1305 } |
591
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diff
changeset
|
1306 cycles(&opts->gen, num_cycles); |
239
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
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238
diff
changeset
|
1307 if (inst->addr_mode != Z80_REG_INDIRECT && inst->immed < 0x4000) { |
591
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590
diff
changeset
|
1308 code_ptr call_dst = z80_get_native_address(context, inst->immed); |
236
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diff
changeset
|
1309 if (!call_dst) { |
591
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Get Z80 core back into compileable state
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diff
changeset
|
1310 opts->gen.deferred = defer_address(opts->gen.deferred, inst->immed, code->cur + 1); |
236
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235
diff
changeset
|
1311 //fake address to force large displacement |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1312 call_dst + 256; |
236
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235
diff
changeset
|
1313 } |
591
966b46c68942
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Michael Pavone <pavone@retrodev.com>
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590
diff
changeset
|
1314 jmp(code, call_dst); |
236
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235
diff
changeset
|
1315 } else { |
239
a5bea9711a46
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Mike Pavone <pavone@retrodev.com>
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238
diff
changeset
|
1316 if (inst->addr_mode == Z80_REG_INDIRECT) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
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590
diff
changeset
|
1317 mov_rr(code, opts->regs[inst->ea_reg], opts->gen.scratch1, SZ_W); |
236
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235
diff
changeset
|
1318 } else { |
591
966b46c68942
Get Z80 core back into compileable state
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diff
changeset
|
1319 mov_ir(code, inst->immed, opts->gen.scratch1, SZ_W); |
236
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235
diff
changeset
|
1320 } |
591
966b46c68942
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parents:
590
diff
changeset
|
1321 call(code, (uint8_t *)z80_native_addr); |
966b46c68942
Get Z80 core back into compileable state
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590
diff
changeset
|
1322 jmp_r(code, opts->gen.scratch1); |
236
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235
diff
changeset
|
1323 } |
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235
diff
changeset
|
1324 break; |
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235
diff
changeset
|
1325 } |
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235
diff
changeset
|
1326 case Z80_JPCC: { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1327 cycles(&opts->gen, 7);//T States: 4,3 |
236
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235
diff
changeset
|
1328 uint8_t cond = CC_Z; |
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235
diff
changeset
|
1329 switch (inst->reg) |
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235
diff
changeset
|
1330 { |
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diff
changeset
|
1331 case Z80_CC_NZ: |
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diff
changeset
|
1332 cond = CC_NZ; |
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diff
changeset
|
1333 case Z80_CC_Z: |
591
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Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1334 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_Z), SZ_B); |
236
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235
diff
changeset
|
1335 break; |
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235
diff
changeset
|
1336 case Z80_CC_NC: |
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235
diff
changeset
|
1337 cond = CC_NZ; |
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235
diff
changeset
|
1338 case Z80_CC_C: |
591
966b46c68942
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Michael Pavone <pavone@retrodev.com>
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590
diff
changeset
|
1339 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B); |
236
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235
diff
changeset
|
1340 break; |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1341 case Z80_CC_PO: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1342 cond = CC_NZ; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1343 case Z80_CC_PE: |
591
966b46c68942
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parents:
590
diff
changeset
|
1344 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_PV), SZ_B); |
238
827ebce557bf
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Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1345 break; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1346 case Z80_CC_P: |
367
f20562f2a570
Fix P condition in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
366
diff
changeset
|
1347 cond = CC_NZ; |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1348 case Z80_CC_M: |
591
966b46c68942
Get Z80 core back into compileable state
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parents:
590
diff
changeset
|
1349 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_S), SZ_B); |
238
827ebce557bf
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Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1350 break; |
236
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235
diff
changeset
|
1351 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1352 uint8_t *no_jump_off = code->cur+1; |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1353 jcc(code, cond, code->cur+2); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1354 cycles(&opts->gen, 5);//T States: 5 |
236
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235
diff
changeset
|
1355 uint16_t dest_addr = inst->immed; |
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235
diff
changeset
|
1356 if (dest_addr < 0x4000) { |
591
966b46c68942
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Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1357 code_ptr call_dst = z80_get_native_address(context, dest_addr); |
236
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1358 if (!call_dst) { |
591
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diff
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|
1359 opts->gen.deferred = defer_address(opts->gen.deferred, dest_addr, code->cur + 1); |
236
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diff
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|
1360 //fake address to force large displacement |
591
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Get Z80 core back into compileable state
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|
1361 call_dst + 256; |
236
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235
diff
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|
1362 } |
591
966b46c68942
Get Z80 core back into compileable state
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diff
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|
1363 jmp(code, call_dst); |
236
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diff
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|
1364 } else { |
591
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Get Z80 core back into compileable state
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590
diff
changeset
|
1365 mov_ir(code, dest_addr, opts->gen.scratch1, SZ_W); |
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Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
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590
diff
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|
1366 call(code, (uint8_t *)z80_native_addr); |
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Get Z80 core back into compileable state
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590
diff
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|
1367 jmp_r(code, opts->gen.scratch1); |
236
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235
diff
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|
1368 } |
591
966b46c68942
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diff
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|
1369 *no_jump_off = code->cur - (no_jump_off+1); |
236
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Implement more Z80 instructions (untested)
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235
diff
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|
1370 break; |
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Implement more Z80 instructions (untested)
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235
diff
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|
1371 } |
19fb3523a9e5
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diff
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|
1372 case Z80_JR: { |
591
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Get Z80 core back into compileable state
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590
diff
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|
1373 cycles(&opts->gen, 12);//T States: 4,3,5 |
236
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235
diff
changeset
|
1374 uint16_t dest_addr = address + inst->immed + 2; |
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235
diff
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|
1375 if (dest_addr < 0x4000) { |
591
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Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
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diff
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|
1376 code_ptr call_dst = z80_get_native_address(context, dest_addr); |
236
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Implement more Z80 instructions (untested)
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235
diff
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|
1377 if (!call_dst) { |
591
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Get Z80 core back into compileable state
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590
diff
changeset
|
1378 opts->gen.deferred = defer_address(opts->gen.deferred, dest_addr, code->cur + 1); |
236
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Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
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235
diff
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|
1379 //fake address to force large displacement |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
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590
diff
changeset
|
1380 call_dst + 256; |
236
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235
diff
changeset
|
1381 } |
591
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590
diff
changeset
|
1382 jmp(code, call_dst); |
236
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Implement more Z80 instructions (untested)
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235
diff
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|
1383 } else { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
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590
diff
changeset
|
1384 mov_ir(code, dest_addr, opts->gen.scratch1, SZ_W); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
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590
diff
changeset
|
1385 call(code, (uint8_t *)z80_native_addr); |
966b46c68942
Get Z80 core back into compileable state
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590
diff
changeset
|
1386 jmp_r(code, opts->gen.scratch1); |
236
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235
diff
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|
1387 } |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
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235
diff
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|
1388 break; |
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235
diff
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|
1389 } |
235
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Get Z80 core working for simple programs
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diff
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|
1390 case Z80_JRCC: { |
591
966b46c68942
Get Z80 core back into compileable state
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590
diff
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|
1391 cycles(&opts->gen, 7);//T States: 4,3 |
235
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|
1392 uint8_t cond = CC_Z; |
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Get Z80 core working for simple programs
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213
diff
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|
1393 switch (inst->reg) |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1394 { |
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213
diff
changeset
|
1395 case Z80_CC_NZ: |
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diff
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|
1396 cond = CC_NZ; |
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Get Z80 core working for simple programs
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213
diff
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|
1397 case Z80_CC_Z: |
591
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Get Z80 core back into compileable state
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590
diff
changeset
|
1398 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_Z), SZ_B); |
235
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213
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|
1399 break; |
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213
diff
changeset
|
1400 case Z80_CC_NC: |
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213
diff
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|
1401 cond = CC_NZ; |
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Get Z80 core working for simple programs
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213
diff
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|
1402 case Z80_CC_C: |
591
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Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
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590
diff
changeset
|
1403 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B); |
235
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213
diff
changeset
|
1404 break; |
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213
diff
changeset
|
1405 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
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590
diff
changeset
|
1406 uint8_t *no_jump_off = code->cur+1; |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1407 jcc(code, cond, code->cur+2); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
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590
diff
changeset
|
1408 cycles(&opts->gen, 5);//T States: 5 |
235
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213
diff
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|
1409 uint16_t dest_addr = address + inst->immed + 2; |
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diff
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|
1410 if (dest_addr < 0x4000) { |
591
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Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
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590
diff
changeset
|
1411 code_ptr call_dst = z80_get_native_address(context, dest_addr); |
235
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diff
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|
1412 if (!call_dst) { |
591
966b46c68942
Get Z80 core back into compileable state
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590
diff
changeset
|
1413 opts->gen.deferred = defer_address(opts->gen.deferred, dest_addr, code->cur + 1); |
235
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Get Z80 core working for simple programs
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diff
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|
1414 //fake address to force large displacement |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
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590
diff
changeset
|
1415 call_dst + 256; |
235
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diff
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|
1416 } |
591
966b46c68942
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diff
changeset
|
1417 jmp(code, call_dst); |
235
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diff
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|
1418 } else { |
591
966b46c68942
Get Z80 core back into compileable state
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590
diff
changeset
|
1419 mov_ir(code, dest_addr, opts->gen.scratch1, SZ_W); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
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590
diff
changeset
|
1420 call(code, (uint8_t *)z80_native_addr); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
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590
diff
changeset
|
1421 jmp_r(code, opts->gen.scratch1); |
235
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diff
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|
1422 } |
591
966b46c68942
Get Z80 core back into compileable state
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diff
changeset
|
1423 *no_jump_off = code->cur - (no_jump_off+1); |
235
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Get Z80 core working for simple programs
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213
diff
changeset
|
1424 break; |
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213
diff
changeset
|
1425 } |
239
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
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238
diff
changeset
|
1426 case Z80_DJNZ: |
591
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Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
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590
diff
changeset
|
1427 cycles(&opts->gen, 8);//T States: 5,3 |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
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590
diff
changeset
|
1428 sub_ir(code, 1, opts->regs[Z80_B], SZ_B); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
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590
diff
changeset
|
1429 uint8_t *no_jump_off = code->cur+1; |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1430 jcc(code, CC_Z, code->cur+2); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
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590
diff
changeset
|
1431 cycles(&opts->gen, 5);//T States: 5 |
239
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
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238
diff
changeset
|
1432 uint16_t dest_addr = address + inst->immed + 2; |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
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238
diff
changeset
|
1433 if (dest_addr < 0x4000) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
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590
diff
changeset
|
1434 code_ptr call_dst = z80_get_native_address(context, dest_addr); |
239
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
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238
diff
changeset
|
1435 if (!call_dst) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
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diff
changeset
|
1436 opts->gen.deferred = defer_address(opts->gen.deferred, dest_addr, code->cur + 1); |
239
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
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238
diff
changeset
|
1437 //fake address to force large displacement |
591
966b46c68942
Get Z80 core back into compileable state
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590
diff
changeset
|
1438 call_dst + 256; |
239
a5bea9711a46
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238
diff
changeset
|
1439 } |
591
966b46c68942
Get Z80 core back into compileable state
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diff
changeset
|
1440 jmp(code, call_dst); |
239
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238
diff
changeset
|
1441 } else { |
591
966b46c68942
Get Z80 core back into compileable state
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590
diff
changeset
|
1442 mov_ir(code, dest_addr, opts->gen.scratch1, SZ_W); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
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590
diff
changeset
|
1443 call(code, (uint8_t *)z80_native_addr); |
966b46c68942
Get Z80 core back into compileable state
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590
diff
changeset
|
1444 jmp_r(code, opts->gen.scratch1); |
239
a5bea9711a46
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238
diff
changeset
|
1445 } |
591
966b46c68942
Get Z80 core back into compileable state
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diff
changeset
|
1446 *no_jump_off = code->cur - (no_jump_off+1); |
239
a5bea9711a46
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238
diff
changeset
|
1447 break; |
235
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diff
changeset
|
1448 case Z80_CALL: { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1449 cycles(&opts->gen, 11);//T States: 4,3,4 |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1450 sub_ir(code, 2, opts->regs[Z80_SP], SZ_W); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
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590
diff
changeset
|
1451 mov_ir(code, address + 3, opts->gen.scratch1, SZ_W); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
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590
diff
changeset
|
1452 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch2, SZ_W); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
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590
diff
changeset
|
1453 call(code, (uint8_t *)z80_write_word_highfirst);//T States: 3, 3 |
235
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diff
changeset
|
1454 if (inst->immed < 0x4000) { |
591
966b46c68942
Get Z80 core back into compileable state
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590
diff
changeset
|
1455 code_ptr call_dst = z80_get_native_address(context, inst->immed); |
235
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diff
changeset
|
1456 if (!call_dst) { |
591
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Get Z80 core back into compileable state
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590
diff
changeset
|
1457 opts->gen.deferred = defer_address(opts->gen.deferred, inst->immed, code->cur + 1); |
235
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diff
changeset
|
1458 //fake address to force large displacement |
591
966b46c68942
Get Z80 core back into compileable state
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590
diff
changeset
|
1459 call_dst + 256; |
235
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diff
changeset
|
1460 } |
591
966b46c68942
Get Z80 core back into compileable state
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diff
changeset
|
1461 jmp(code, call_dst); |
235
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diff
changeset
|
1462 } else { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
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590
diff
changeset
|
1463 mov_ir(code, inst->immed, opts->gen.scratch1, SZ_W); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1464 call(code, (uint8_t *)z80_native_addr); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
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590
diff
changeset
|
1465 jmp_r(code, opts->gen.scratch1); |
235
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213
diff
changeset
|
1466 } |
d9bf8e61c33c
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213
diff
changeset
|
1467 break; |
d9bf8e61c33c
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213
diff
changeset
|
1468 } |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
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236
diff
changeset
|
1469 case Z80_CALLCC: |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1470 cycles(&opts->gen, 10);//T States: 4,3,3 (false case) |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1471 uint8_t cond = CC_Z; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1472 switch (inst->reg) |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1473 { |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1474 case Z80_CC_NZ: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1475 cond = CC_NZ; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1476 case Z80_CC_Z: |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1477 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_Z), SZ_B); |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1478 break; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1479 case Z80_CC_NC: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1480 cond = CC_NZ; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1481 case Z80_CC_C: |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1482 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B); |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1483 break; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1484 case Z80_CC_PO: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1485 cond = CC_NZ; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1486 case Z80_CC_PE: |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1487 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_PV), SZ_B); |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1488 break; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1489 case Z80_CC_P: |
367
f20562f2a570
Fix P condition in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
366
diff
changeset
|
1490 cond = CC_NZ; |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1491 case Z80_CC_M: |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1492 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_S), SZ_B); |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1493 break; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1494 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1495 uint8_t *no_call_off = code->cur+1; |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1496 jcc(code, cond, code->cur+2); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1497 cycles(&opts->gen, 1);//Last of the above T states takes an extra cycle in the true case |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1498 sub_ir(code, 2, opts->regs[Z80_SP], SZ_W); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1499 mov_ir(code, address + 3, opts->gen.scratch1, SZ_W); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1500 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch2, SZ_W); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1501 call(code, (uint8_t *)z80_write_word_highfirst);//T States: 3, 3 |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1502 if (inst->immed < 0x4000) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1503 code_ptr call_dst = z80_get_native_address(context, inst->immed); |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1504 if (!call_dst) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1505 opts->gen.deferred = defer_address(opts->gen.deferred, inst->immed, code->cur + 1); |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1506 //fake address to force large displacement |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1507 call_dst + 256; |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1508 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1509 jmp(code, call_dst); |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1510 } else { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1511 mov_ir(code, inst->immed, opts->gen.scratch1, SZ_W); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1512 call(code, (uint8_t *)z80_native_addr); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1513 jmp_r(code, opts->gen.scratch1); |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1514 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1515 *no_call_off = code->cur - (no_call_off+1); |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1516 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1517 case Z80_RET: |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1518 cycles(&opts->gen, 4);//T States: 4 |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1519 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1520 call(code, (uint8_t *)z80_read_word);//T STates: 3, 3 |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1521 add_ir(code, 2, opts->regs[Z80_SP], SZ_W); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1522 call(code, (uint8_t *)z80_native_addr); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1523 jmp_r(code, opts->gen.scratch1); |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1524 break; |
246
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1525 case Z80_RETCC: { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1526 cycles(&opts->gen, 5);//T States: 5 |
246
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1527 uint8_t cond = CC_Z; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1528 switch (inst->reg) |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1529 { |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1530 case Z80_CC_NZ: |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1531 cond = CC_NZ; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1532 case Z80_CC_Z: |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1533 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_Z), SZ_B); |
246
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1534 break; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1535 case Z80_CC_NC: |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1536 cond = CC_NZ; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1537 case Z80_CC_C: |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1538 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B); |
246
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1539 break; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1540 case Z80_CC_PO: |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1541 cond = CC_NZ; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1542 case Z80_CC_PE: |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1543 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_PV), SZ_B); |
246
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1544 break; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1545 case Z80_CC_P: |
367
f20562f2a570
Fix P condition in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
366
diff
changeset
|
1546 cond = CC_NZ; |
246
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1547 case Z80_CC_M: |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1548 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_S), SZ_B); |
246
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1549 break; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1550 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1551 uint8_t *no_call_off = code->cur+1; |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1552 jcc(code, cond, code->cur+2); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1553 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1554 call(code, (uint8_t *)z80_read_word);//T STates: 3, 3 |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1555 add_ir(code, 2, opts->regs[Z80_SP], SZ_W); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1556 call(code, (uint8_t *)z80_native_addr); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1557 jmp_r(code, opts->gen.scratch1); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1558 *no_call_off = code->cur - (no_call_off+1); |
246
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1559 break; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1560 } |
283
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1561 case Z80_RETI: |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1562 //For some systems, this may need a callback for signalling interrupt routine completion |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1563 cycles(&opts->gen, 8);//T States: 4, 4 |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1564 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1565 call(code, (uint8_t *)z80_read_word);//T STates: 3, 3 |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1566 add_ir(code, 2, opts->regs[Z80_SP], SZ_W); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1567 call(code, (uint8_t *)z80_native_addr); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1568 jmp_r(code, opts->gen.scratch1); |
283
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1569 break; |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1570 case Z80_RETN: |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1571 cycles(&opts->gen, 8);//T States: 4, 4 |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1572 mov_rdispr(code, opts->gen.context_reg, offsetof(z80_context, iff2), opts->gen.scratch2, SZ_B); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1573 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1574 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, offsetof(z80_context, iff1), SZ_B); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1575 call(code, (uint8_t *)z80_read_word);//T STates: 3, 3 |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1576 add_ir(code, 2, opts->regs[Z80_SP], SZ_W); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1577 call(code, (uint8_t *)z80_native_addr); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1578 jmp_r(code, opts->gen.scratch1); |
283
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1579 break; |
241
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1580 case Z80_RST: { |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
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239
diff
changeset
|
1581 //RST is basically CALL to an address in page 0 |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1582 cycles(&opts->gen, 5);//T States: 5 |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1583 sub_ir(code, 2, opts->regs[Z80_SP], SZ_W); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1584 mov_ir(code, address + 1, opts->gen.scratch1, SZ_W); |
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Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1585 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch2, SZ_W); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1586 call(code, (uint8_t *)z80_write_word_highfirst);//T States: 3, 3 |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1587 code_ptr call_dst = z80_get_native_address(context, inst->immed); |
241
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1588 if (!call_dst) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1589 opts->gen.deferred = defer_address(opts->gen.deferred, inst->immed, code->cur + 1); |
241
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1590 //fake address to force large displacement |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1591 call_dst + 256; |
241
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1592 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1593 jmp(code, call_dst); |
241
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1594 break; |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1595 } |
284
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1596 case Z80_IN: |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1597 cycles(&opts->gen, inst->reg == Z80_A ? 7 : 8);//T States: 4 3/4 |
284
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1598 if (inst->addr_mode == Z80_IMMED_INDIRECT) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1599 mov_ir(code, inst->immed, opts->gen.scratch1, SZ_B); |
284
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
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283
diff
changeset
|
1600 } else { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1601 mov_rr(code, opts->regs[Z80_C], opts->gen.scratch1, SZ_B); |
284
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1602 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1603 call(code, (uint8_t *)z80_io_read); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1604 translate_z80_reg(inst, &dst_op, opts); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1605 mov_rr(code, opts->gen.scratch1, dst_op.base, SZ_B); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1606 z80_save_reg(inst, opts); |
284
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1607 break; |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
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283
diff
changeset
|
1608 /*case Z80_INI: |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1609 case Z80_INIR: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1610 case Z80_IND: |
284
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1611 case Z80_INDR:*/ |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1612 case Z80_OUT: |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1613 cycles(&opts->gen, inst->reg == Z80_A ? 7 : 8);//T States: 4 3/4 |
284
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1614 if ((inst->addr_mode & 0x1F) == Z80_IMMED_INDIRECT) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
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590
diff
changeset
|
1615 mov_ir(code, inst->immed, opts->gen.scratch2, SZ_B); |
284
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1616 } else { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
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590
diff
changeset
|
1617 mov_rr(code, opts->regs[Z80_C], opts->gen.scratch2, SZ_B); |
284
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Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
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283
diff
changeset
|
1618 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1619 translate_z80_reg(inst, &src_op, opts); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1620 mov_rr(code, dst_op.base, opts->gen.scratch1, SZ_B); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1621 call(code, (uint8_t *)z80_io_write); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1622 z80_save_reg(inst, opts); |
284
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
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283
diff
changeset
|
1623 break; |
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Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
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283
diff
changeset
|
1624 /*case Z80_OUTI: |
213
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Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1625 case Z80_OTIR: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1626 case Z80_OUTD: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1627 case Z80_OTDR:*/ |
235
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1628 default: { |
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Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1629 char disbuf[80]; |
314
54c0e5f22198
Show absolute addresses for JR, JRCC and DJNZ in Z80 disassembler
Mike Pavone <pavone@retrodev.com>
parents:
313
diff
changeset
|
1630 z80_disasm(inst, disbuf, address); |
424
7e8e179116af
Add support for loading GST format savestates
Mike Pavone <pavone@retrodev.com>
parents:
420
diff
changeset
|
1631 fprintf(stderr, "unimplemented instruction: %s at %X\n", disbuf, address); |
259
d9417261366f
Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called.
Mike Pavone <pavone@retrodev.com>
parents:
257
diff
changeset
|
1632 FILE * f = fopen("zram.bin", "wb"); |
d9417261366f
Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called.
Mike Pavone <pavone@retrodev.com>
parents:
257
diff
changeset
|
1633 fwrite(context->mem_pointers[0], 1, 8 * 1024, f); |
d9417261366f
Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called.
Mike Pavone <pavone@retrodev.com>
parents:
257
diff
changeset
|
1634 fclose(f); |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1635 exit(1); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1636 } |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
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213
diff
changeset
|
1637 } |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
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213
diff
changeset
|
1638 } |
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1639 |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1640 uint8_t * z80_get_native_address(z80_context * context, uint32_t address) |
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1641 { |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1642 native_map_slot *map; |
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1643 if (address < 0x4000) { |
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1644 address &= 0x1FFF; |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1645 map = context->static_code_map; |
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1646 } else if (address >= 0x8000) { |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1647 address &= 0x7FFF; |
279
6be6056735a9
Fix native address lookup in bannked memory area
Mike Pavone <pavone@retrodev.com>
parents:
277
diff
changeset
|
1648 map = context->banked_code_map + context->bank_reg; |
235
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1649 } else { |
313
a13329645ea3
Fix terminal instruction detection in disassembler
Mike Pavone <pavone@retrodev.com>
parents:
312
diff
changeset
|
1650 //dprintf("z80_get_native_address: %X NULL\n", address); |
235
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1651 return NULL; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1652 } |
268
6c2d7e003a55
Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents:
267
diff
changeset
|
1653 if (!map->base || !map->offsets || map->offsets[address] == INVALID_OFFSET || map->offsets[address] == EXTENSION_WORD) { |
313
a13329645ea3
Fix terminal instruction detection in disassembler
Mike Pavone <pavone@retrodev.com>
parents:
312
diff
changeset
|
1654 //dprintf("z80_get_native_address: %X NULL\n", address); |
235
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1655 return NULL; |
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1656 } |
313
a13329645ea3
Fix terminal instruction detection in disassembler
Mike Pavone <pavone@retrodev.com>
parents:
312
diff
changeset
|
1657 //dprintf("z80_get_native_address: %X %p\n", address, map->base + map->offsets[address]); |
235
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1658 return map->base + map->offsets[address]; |
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1659 } |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1660 |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
1661 uint8_t z80_get_native_inst_size(z80_options * opts, uint32_t address) |
235
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1662 { |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1663 if (address >= 0x4000) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1664 return 0; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
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250
diff
changeset
|
1665 } |
591
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Get Z80 core back into compileable state
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590
diff
changeset
|
1666 return opts->gen.ram_inst_sizes[0][address & 0x1FFF]; |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
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250
diff
changeset
|
1667 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1668 |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
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250
diff
changeset
|
1669 void z80_map_native_address(z80_context * context, uint32_t address, uint8_t * native_address, uint8_t size, uint8_t native_size) |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
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250
diff
changeset
|
1670 { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
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250
diff
changeset
|
1671 uint32_t orig_address = address; |
235
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213
diff
changeset
|
1672 native_map_slot *map; |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
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parents:
506
diff
changeset
|
1673 z80_options * opts = context->options; |
235
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213
diff
changeset
|
1674 if (address < 0x4000) { |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1675 address &= 0x1FFF; |
d9bf8e61c33c
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213
diff
changeset
|
1676 map = context->static_code_map; |
591
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590
diff
changeset
|
1677 opts->gen.ram_inst_sizes[0][address] = native_size; |
252
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Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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changeset
|
1678 context->ram_code_flags[(address & 0x1C00) >> 10] |= 1 << ((address & 0x380) >> 7); |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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changeset
|
1679 context->ram_code_flags[((address + size) & 0x1C00) >> 10] |= 1 << (((address + size) & 0x380) >> 7); |
235
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213
diff
changeset
|
1680 } else if (address >= 0x8000) { |
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213
diff
changeset
|
1681 address &= 0x7FFF; |
279
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Fix native address lookup in bannked memory area
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277
diff
changeset
|
1682 map = context->banked_code_map + context->bank_reg; |
235
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213
diff
changeset
|
1683 if (!map->offsets) { |
d9bf8e61c33c
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213
diff
changeset
|
1684 map->offsets = malloc(sizeof(int32_t) * 0x8000); |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1685 memset(map->offsets, 0xFF, sizeof(int32_t) * 0x8000); |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1686 } |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1687 } else { |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1688 return; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1689 } |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1690 if (!map->base) { |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1691 map->base = native_address; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1692 } |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1693 map->offsets[address] = native_address - map->base; |
253
3b34deba4ca0
Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents:
252
diff
changeset
|
1694 for(--size, orig_address++; size; --size, orig_address++) { |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1695 address = orig_address; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1696 if (address < 0x4000) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1697 address &= 0x1FFF; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1698 map = context->static_code_map; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1699 } else if (address >= 0x8000) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1700 address &= 0x7FFF; |
279
6be6056735a9
Fix native address lookup in bannked memory area
Mike Pavone <pavone@retrodev.com>
parents:
277
diff
changeset
|
1701 map = context->banked_code_map + context->bank_reg; |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1702 } else { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1703 return; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1704 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1705 if (!map->offsets) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1706 map->offsets = malloc(sizeof(int32_t) * 0x8000); |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1707 memset(map->offsets, 0xFF, sizeof(int32_t) * 0x8000); |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1708 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1709 map->offsets[address] = EXTENSION_WORD; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1710 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1711 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1712 |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1713 #define INVALID_INSTRUCTION_START 0xFEEDFEED |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1714 |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1715 uint32_t z80_get_instruction_start(native_map_slot * static_code_map, uint32_t address) |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1716 { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1717 if (!static_code_map->base || address >= 0x4000) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1718 return INVALID_INSTRUCTION_START; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1719 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1720 address &= 0x1FFF; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1721 if (static_code_map->offsets[address] == INVALID_OFFSET) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1722 return INVALID_INSTRUCTION_START; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1723 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1724 while (static_code_map->offsets[address] == EXTENSION_WORD) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1725 --address; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1726 address &= 0x1FFF; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1727 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1728 return address; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1729 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1730 |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1731 z80_context * z80_handle_code_write(uint32_t address, z80_context * context) |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1732 { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1733 uint32_t inst_start = z80_get_instruction_start(context->static_code_map, address); |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1734 if (inst_start != INVALID_INSTRUCTION_START) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1735 code_ptr dst = z80_get_native_address(context, inst_start); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1736 code_info code = {dst, dst+16}; |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1737 z80_options * opts = context->options; |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1738 dprintf("patching code at %p for Z80 instruction at %X due to write to %X\n", code, inst_start, address); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1739 mov_ir(&code, inst_start, opts->gen.scratch1, SZ_D); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1740 call(&code, (uint8_t *)z80_retrans_stub); |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1741 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1742 return context; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1743 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1744 |
264
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1745 uint8_t * z80_get_native_address_trans(z80_context * context, uint32_t address) |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1746 { |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1747 uint8_t * addr = z80_get_native_address(context, address); |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1748 if (!addr) { |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1749 translate_z80_stream(context, address); |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1750 addr = z80_get_native_address(context, address); |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1751 if (!addr) { |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1752 printf("Failed to translate %X to native code\n", address); |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1753 } |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1754 } |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1755 return addr; |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1756 } |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1757 |
266
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1758 void z80_handle_deferred(z80_context * context) |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1759 { |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
1760 z80_options * opts = context->options; |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1761 process_deferred(&opts->gen.deferred, context, (native_addr_func)z80_get_native_address); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1762 if (opts->gen.deferred) { |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1763 translate_z80_stream(context, opts->gen.deferred->address); |
266
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1764 } |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1765 } |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1766 |
390
561fe3ea3fc8
Use a call instruction to figure out the original native address when retranslating so that it does not get lost when the byte transforms from a instruction word to extension word
Mike Pavone <pavone@retrodev.com>
parents:
389
diff
changeset
|
1767 void * z80_retranslate_inst(uint32_t address, z80_context * context, uint8_t * orig_start) |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1768 { |
266
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1769 char disbuf[80]; |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
1770 z80_options * opts = context->options; |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1771 uint8_t orig_size = z80_get_native_inst_size(opts, address); |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1772 uint32_t orig = address; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1773 address &= 0x1FFF; |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1774 code_info *code = &opts->gen.code; |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1775 uint8_t *after, *inst = context->mem_pointers[0] + address; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1776 z80inst instbuf; |
268
6c2d7e003a55
Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents:
267
diff
changeset
|
1777 dprintf("Retranslating code at Z80 address %X, native address %p\n", address, orig_start); |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1778 after = z80_decode(inst, &instbuf); |
268
6c2d7e003a55
Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents:
267
diff
changeset
|
1779 #ifdef DO_DEBUG_PRINT |
314
54c0e5f22198
Show absolute addresses for JR, JRCC and DJNZ in Z80 disassembler
Mike Pavone <pavone@retrodev.com>
parents:
313
diff
changeset
|
1780 z80_disasm(&instbuf, disbuf, address); |
266
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1781 if (instbuf.op == Z80_NOP) { |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1782 printf("%X\t%s(%d)\n", address, disbuf, instbuf.immed); |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1783 } else { |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1784 printf("%X\t%s\n", address, disbuf); |
267
1788e3f29c28
Don't mix *H regs with the REX prefix
Mike Pavone <pavone@retrodev.com>
parents:
266
diff
changeset
|
1785 } |
268
6c2d7e003a55
Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents:
267
diff
changeset
|
1786 #endif |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1787 if (orig_size != ZMAX_NATIVE_SIZE) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1788 code_ptr start = code->cur; |
966b46c68942
Get Z80 core back into compileable state
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1789 deferred_addr * orig_deferred = opts->gen.deferred; |
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1790 translate_z80inst(&instbuf, context, address); |
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1791 /* |
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1792 if ((native_end - dst) <= orig_size) { |
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1793 uint8_t * native_next = z80_get_native_address(context, address + after-inst); |
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1794 if (native_next && ((native_next == orig_start + orig_size) || (orig_size - (native_end - dst)) > 5)) { |
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1795 remove_deferred_until(&opts->gen.deferred, orig_deferred); |
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1796 native_end = translate_z80inst(&instbuf, orig_start, context, address); |
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1797 if (native_next == orig_start + orig_size && (native_next-native_end) < 2) { |
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1798 while (native_end < orig_start + orig_size) { |
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1799 *(native_end++) = 0x90; //NOP |
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1800 } |
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1801 } else { |
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1802 jmp(native_end, native_next); |
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1803 } |
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|
1804 z80_handle_deferred(context); |
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1805 return orig_start; |
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1806 } |
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|
1807 }*/ |
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1808 z80_map_native_address(context, address, start, after-inst, ZMAX_NATIVE_SIZE); |
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1809 code_info tmp_code = {orig_start, orig_start + 16}; |
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1810 jmp(&tmp_code, start); |
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1811 if (!z80_is_terminal(&instbuf)) { |
591
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1812 jmp(code, z80_get_native_address_trans(context, address + after-inst)); |
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1813 } |
591
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1814 code->cur = start + ZMAX_NATIVE_SIZE; |
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1815 z80_handle_deferred(context); |
591
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1816 return start; |
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1817 } else { |
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1818 code_info tmp_code = *code; |
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1819 code->cur = orig_start; |
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1820 code->last = orig_start + ZMAX_NATIVE_SIZE; |
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1821 translate_z80inst(&instbuf, context, address); |
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1822 if (!z80_is_terminal(&instbuf)) { |
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1823 jmp(code, z80_get_native_address_trans(context, address + after-inst)); |
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1824 } |
591
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1825 *code = tmp_code; |
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1826 z80_handle_deferred(context); |
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1827 return orig_start; |
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1828 } |
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1829 } |
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1830 |
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1831 void translate_z80_stream(z80_context * context, uint32_t address) |
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1832 { |
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1833 char disbuf[80]; |
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1834 if (z80_get_native_address(context, address)) { |
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1835 return; |
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1836 } |
590
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diff
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|
1837 z80_options * opts = context->options; |
505
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|
1838 uint32_t start_address = address; |
235
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1839 uint8_t * encoded = NULL, *next; |
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1840 if (address < 0x4000) { |
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1841 encoded = context->mem_pointers[0] + (address & 0x1FFF); |
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1842 } else if(address >= 0x8000 && context->mem_pointers[1]) { |
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|
1843 printf("attempt to translate Z80 code from banked area at address %X\n", address); |
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|
1844 exit(1); |
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1845 //encoded = context->mem_pointers[1] + (address & 0x7FFF); |
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1846 } |
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1847 while (encoded != NULL) |
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|
1848 { |
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1849 z80inst inst; |
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1850 dprintf("translating Z80 code at address %X\n", address); |
235
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1851 do { |
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|
1852 if (address > 0x4000 && address < 0x8000) { |
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|
1853 xor_rr(&opts->gen.code, RDI, RDI, SZ_D); |
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1854 call(&opts->gen.code, (uint8_t *)exit); |
235
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|
1855 break; |
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|
1856 } |
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1857 uint8_t * existing = z80_get_native_address(context, address); |
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1858 if (existing) { |
591
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|
1859 jmp(&opts->gen.code, existing); |
235
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1860 break; |
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1861 } |
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1862 next = z80_decode(encoded, &inst); |
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|
1863 #ifdef DO_DEBUG_PRINT |
314
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|
1864 z80_disasm(&inst, disbuf, address); |
235
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1865 if (inst.op == Z80_NOP) { |
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1866 printf("%X\t%s(%d)\n", address, disbuf, inst.immed); |
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1867 } else { |
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1868 printf("%X\t%s\n", address, disbuf); |
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1869 } |
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1870 #endif |
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1871 code_ptr start = opts->gen.code.cur; |
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1872 translate_z80inst(&inst, context, address); |
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1873 z80_map_native_address(context, address, start, next-encoded, opts->gen.code.cur - start); |
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1874 address += next-encoded; |
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1875 if (address > 0xFFFF) { |
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1876 address &= 0xFFFF; |
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1877 |
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1878 } else { |
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1879 encoded = next; |
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1880 } |
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1881 } while (!z80_is_terminal(&inst)); |
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1882 process_deferred(&opts->gen.deferred, context, (native_addr_func)z80_get_native_address); |
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1883 if (opts->gen.deferred) { |
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1884 address = opts->gen.deferred->address; |
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1885 dprintf("defferred address: %X\n", address); |
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1886 if (address < 0x4000) { |
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1887 encoded = context->mem_pointers[0] + (address & 0x1FFF); |
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1888 } else if (address > 0x8000 && context->mem_pointers[1]) { |
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1889 encoded = context->mem_pointers[1] + (address & 0x7FFF); |
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1890 } else { |
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1891 printf("attempt to translate non-memory address: %X\n", address); |
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1892 exit(1); |
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1893 } |
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1894 } else { |
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1895 encoded = NULL; |
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1896 } |
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1897 } |
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1898 } |
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1899 |
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1900 void init_x86_z80_opts(z80_options * options, memmap_chunk * chunks, uint32_t num_chunks) |
213
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1901 { |
590
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1902 memset(options, 0, sizeof(*options)); |
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1903 |
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1904 options->gen.address_size = SZ_W; |
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1905 options->gen.address_mask = 0xFFFF; |
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1906 options->gen.max_address = 0x10000; |
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1907 options->gen.bus_cycles = 3; |
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1908 options->gen.mem_ptr_off = offsetof(z80_context, mem_pointers); |
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1909 options->gen.ram_flags_off = offsetof(z80_context, ram_code_flags); |
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1910 |
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1911 options->flags = 0; |
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1912 options->regs[Z80_B] = BH; |
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1913 options->regs[Z80_C] = RBX; |
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1914 options->regs[Z80_D] = CH; |
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1915 options->regs[Z80_E] = RCX; |
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1916 options->regs[Z80_H] = AH; |
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1917 options->regs[Z80_L] = RAX; |
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1918 options->regs[Z80_IXH] = DH; |
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1919 options->regs[Z80_IXL] = RDX; |
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1920 options->regs[Z80_IYH] = -1; |
239
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1921 options->regs[Z80_IYL] = R8; |
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1922 options->regs[Z80_I] = -1; |
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1923 options->regs[Z80_R] = -1; |
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1924 options->regs[Z80_A] = R10; |
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1925 options->regs[Z80_BC] = RBX; |
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1926 options->regs[Z80_DE] = RCX; |
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1927 options->regs[Z80_HL] = RAX; |
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1928 options->regs[Z80_SP] = R9; |
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1929 options->regs[Z80_AF] = -1; |
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1930 options->regs[Z80_IX] = RDX; |
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1931 options->regs[Z80_IY] = R8; |
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1932 |
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1933 options->bank_reg = R15; |
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1934 options->bank_pointer = R12; |
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1935 |
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1936 options->gen.context_reg = RSI; |
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1937 options->gen.cycles = RBP; |
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1938 options->gen.limit = RDI; |
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1939 options->gen.scratch1 = R13; |
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1940 options->gen.scratch2 = R14; |
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1941 |
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1942 options->gen.native_code_map = malloc(sizeof(native_map_slot)); |
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1943 memset(options->gen.native_code_map, 0, sizeof(native_map_slot)); |
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1944 options->gen.deferred = NULL; |
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1945 options->gen.ram_inst_sizes = malloc(sizeof(uint8_t) * 0x2000 + sizeof(uint8_t *)); |
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1946 options->gen.ram_inst_sizes[0] = (uint8_t *)(options->gen.ram_inst_sizes + 1); |
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1947 memset(options->gen.ram_inst_sizes[0], 0, sizeof(uint8_t) * 0x2000); |
590
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1948 |
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1949 code_info *code = &options->gen.code; |
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1950 init_code_info(code); |
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1951 |
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1952 options->save_context_scratch = code->cur; |
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1953 mov_rrdisp(code, options->gen.scratch1, options->gen.context_reg, offsetof(z80_context, scratch1), SZ_W); |
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1954 mov_rrdisp(code, options->gen.scratch2, options->gen.context_reg, offsetof(z80_context, scratch2), SZ_W); |
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|
1955 |
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1956 options->gen.save_context = code->cur; |
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1957 for (int i = 0; i <= Z80_A; i++) |
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1958 { |
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1959 int reg; |
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1960 uint8_t size; |
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1961 if (i < Z80_I) { |
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1962 int reg = i /2 + Z80_BC; |
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1963 size = SZ_W; |
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|
1964 |
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|
1965 } else { |
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|
1966 reg = i; |
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1967 size = SZ_B; |
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|
1968 } |
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|
1969 if (options->regs[reg] >= 0) { |
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|
1970 mov_rrdisp(code, options->regs[reg], options->gen.context_reg, offsetof(z80_context, regs) + i, size); |
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changeset
|
1971 } |
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WIP effort to update z80 core for code gen changes
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changeset
|
1972 } |
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WIP effort to update z80 core for code gen changes
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changeset
|
1973 if (options->regs[Z80_SP] >= 0) { |
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|
1974 mov_rrdisp(code, options->regs[Z80_SP], options->gen.context_reg, offsetof(z80_context, sp), SZ_W); |
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WIP effort to update z80 core for code gen changes
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changeset
|
1975 } |
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changeset
|
1976 mov_rrdisp(code, options->gen.limit, options->gen.context_reg, offsetof(z80_context, target_cycle), SZ_D); |
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|
1977 mov_rrdisp(code, options->gen.cycles, options->gen.context_reg, offsetof(z80_context, current_cycle), SZ_D); |
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|
1978 mov_rrdisp(code, options->bank_reg, options->gen.context_reg, offsetof(z80_context, bank_reg), SZ_W); |
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|
1979 mov_rrdisp(code, options->bank_pointer, options->gen.context_reg, offsetof(z80_context, mem_pointers) + sizeof(uint8_t *) * 1, SZ_PTR); |
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changeset
|
1980 |
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|
1981 options->load_context_scratch = code->cur; |
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changeset
|
1982 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, scratch1), options->gen.scratch1, SZ_W); |
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1983 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, scratch2), options->gen.scratch2, SZ_W); |
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|
1984 options->gen.load_context = code->cur; |
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|
1985 for (int i = 0; i <= Z80_A; i++) |
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|
1986 { |
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|
1987 int reg; |
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|
1988 uint8_t size; |
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|
1989 if (i < Z80_I) { |
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1990 int reg = i /2 + Z80_BC; |
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|
1991 size = SZ_W; |
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|
1992 |
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|
1993 } else { |
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|
1994 reg = i; |
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|
1995 size = SZ_B; |
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|
1996 } |
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|
1997 if (options->regs[reg] >= 0) { |
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|
1998 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, regs) + i, options->regs[reg], size); |
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|
1999 } |
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|
2000 } |
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|
2001 if (options->regs[Z80_SP] >= 0) { |
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|
2002 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, sp), options->regs[Z80_SP], SZ_W); |
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WIP effort to update z80 core for code gen changes
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|
2003 } |
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changeset
|
2004 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, target_cycle), options->gen.limit, SZ_D); |
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changeset
|
2005 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, current_cycle), options->gen.cycles, SZ_D); |
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changeset
|
2006 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, bank_reg), options->bank_reg, SZ_W); |
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changeset
|
2007 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, mem_pointers) + sizeof(uint8_t *) * 1, options->bank_pointer, SZ_PTR); |
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WIP effort to update z80 core for code gen changes
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|
2008 |
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changeset
|
2009 options->gen.handle_cycle_limit = code->cur; |
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changeset
|
2010 cmp_rdispr(code, options->gen.context_reg, offsetof(z80_context, sync_cycle), options->gen.cycles, SZ_D); |
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2011 code_ptr no_sync = code->cur+1; |
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2012 jcc(code, CC_B, no_sync); |
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2013 mov_irdisp(code, 0, options->gen.context_reg, offsetof(z80_context, pc), SZ_W); |
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WIP effort to update z80 core for code gen changes
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2014 call(code, options->save_context_scratch); |
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2015 pop_r(code, RAX); //return address in read/write func |
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2016 pop_r(code, RBX); //return address in translated code |
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2017 sub_ir(code, 5, RAX, SZ_PTR); //adjust return address to point to the call that got us here |
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2018 mov_rrdisp(code, RBX, options->gen.context_reg, offsetof(z80_context, extra_pc), SZ_PTR); |
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2019 mov_rrind(code, RAX, options->gen.context_reg, SZ_PTR); |
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2020 //restore callee saved registers |
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2021 pop_r(code, R15); |
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2022 pop_r(code, R14); |
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Get Z80 core back into compileable state
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2023 pop_r(code, R13); |
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Get Z80 core back into compileable state
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|
2024 pop_r(code, R12); |
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diff
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|
2025 pop_r(code, RBP); |
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Get Z80 core back into compileable state
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|
2026 pop_r(code, RBX); |
590
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|
2027 *no_sync = code->cur - no_sync; |
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diff
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|
2028 //return to caller of z80_run |
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WIP effort to update z80 core for code gen changes
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|
2029 retn(code); |
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2030 |
591
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2031 options->read_8 = gen_mem_fun(&options->gen, chunks, num_chunks, READ_8, NULL); |
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Get Z80 core back into compileable state
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diff
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|
2032 options->write_8 = gen_mem_fun(&options->gen, chunks, num_chunks, WRITE_8, &options->write_8_noinc); |
590
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2033 |
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WIP effort to update z80 core for code gen changes
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|
2034 options->gen.handle_cycle_limit_int = code->cur; |
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WIP effort to update z80 core for code gen changes
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diff
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|
2035 cmp_rdispr(code, options->gen.context_reg, offsetof(z80_context, int_cycle), options->gen.cycles, SZ_D); |
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WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
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506
diff
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|
2036 code_ptr skip_int = code->cur+1; |
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WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
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diff
changeset
|
2037 jcc(code, CC_B, skip_int); |
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WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
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diff
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|
2038 //set limit to the cycle limit |
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WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
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diff
changeset
|
2039 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, sync_cycle), options->gen.limit, SZ_D); |
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506
diff
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|
2040 //disable interrupts |
591
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Get Z80 core back into compileable state
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|
2041 mov_irdisp(code, 0, options->gen.context_reg, offsetof(z80_context, iff1), SZ_B); |
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Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
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diff
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|
2042 mov_irdisp(code, 0, options->gen.context_reg, offsetof(z80_context, iff2), SZ_B); |
590
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diff
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|
2043 cycles(&options->gen, 7); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
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506
diff
changeset
|
2044 //save return address (in scratch1) to Z80 stack |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
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506
diff
changeset
|
2045 sub_ir(code, 2, options->regs[Z80_SP], SZ_W); |
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WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
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506
diff
changeset
|
2046 mov_rr(code, options->regs[Z80_SP], options->gen.scratch2, SZ_W); |
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WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
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506
diff
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|
2047 //we need to do check_cycles and cycles outside of the write_8 call |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
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506
diff
changeset
|
2048 //so that the stack has the correct depth if we need to return to C |
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WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2049 //for a synchronization |
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WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
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506
diff
changeset
|
2050 check_cycles(&options->gen); |
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WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
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506
diff
changeset
|
2051 cycles(&options->gen, 3); |
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WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
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506
diff
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|
2052 //save word to write before call to write_8_noinc |
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WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
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506
diff
changeset
|
2053 push_r(code, options->gen.scratch1); |
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WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
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506
diff
changeset
|
2054 call(code, options->write_8_noinc); |
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WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
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506
diff
changeset
|
2055 //restore word to write |
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WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2056 pop_r(code, options->gen.scratch1); |
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WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
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506
diff
changeset
|
2057 //write high byte to SP+1 |
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WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
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506
diff
changeset
|
2058 mov_rr(code, options->regs[Z80_SP], options->gen.scratch2, SZ_W); |
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WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
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506
diff
changeset
|
2059 add_ir(code, 1, options->gen.scratch2, SZ_W); |
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WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2060 shr_ir(code, 8, options->gen.scratch1, SZ_W); |
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WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
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506
diff
changeset
|
2061 check_cycles(&options->gen); |
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WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
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diff
changeset
|
2062 cycles(&options->gen, 3); |
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WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
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506
diff
changeset
|
2063 call(code, options->write_8_noinc); |
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WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
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506
diff
changeset
|
2064 //dispose of return address as we'll be jumping somewhere else |
591
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Get Z80 core back into compileable state
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diff
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|
2065 pop_r(code, options->gen.scratch2); |
590
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WIP effort to update z80 core for code gen changes
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506
diff
changeset
|
2066 //TODO: Support interrupt mode 0 and 2 |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
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506
diff
changeset
|
2067 mov_ir(code, 0x38, options->gen.scratch1, SZ_W); |
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WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
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506
diff
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|
2068 call(code, (code_ptr)z80_native_addr); |
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WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
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506
diff
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|
2069 jmp_r(code, options->gen.scratch1); |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
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diff
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|
2070 } |
235
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|
2071 |
590
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|
2072 void init_z80_context(z80_context * context, z80_options * options) |
235
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|
2073 { |
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|
2074 memset(context, 0, sizeof(*context)); |
360
c42fae88d346
Fix sizeof expression passed to malloc in z80_init to avoid a minor memory error
Mike Pavone <pavone@retrodev.com>
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335
diff
changeset
|
2075 context->static_code_map = malloc(sizeof(*context->static_code_map)); |
259
d9417261366f
Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called.
Mike Pavone <pavone@retrodev.com>
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257
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|
2076 context->static_code_map->base = NULL; |
235
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2077 context->static_code_map->offsets = malloc(sizeof(int32_t) * 0x2000); |
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|
2078 memset(context->static_code_map->offsets, 0xFF, sizeof(int32_t) * 0x2000); |
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Get Z80 core working for simple programs
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|
2079 context->banked_code_map = malloc(sizeof(native_map_slot) * (1 << 9)); |
259
d9417261366f
Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called.
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|
2080 memset(context->banked_code_map, 0, sizeof(native_map_slot) * (1 << 9)); |
235
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2081 context->options = options; |
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|
2082 } |
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|
2083 |
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|
2084 void z80_reset(z80_context * context) |
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2085 { |
259
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|
2086 context->im = 0; |
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|
2087 context->iff1 = context->iff2 = 0; |
235
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2088 context->native_pc = z80_get_native_address_trans(context, 0); |
268
6c2d7e003a55
Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
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|
2089 context->extra_pc = NULL; |
235
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2090 } |
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|
2091 |
366
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2092 void zinsert_breakpoint(z80_context * context, uint16_t address, uint8_t * bp_handler) |
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|
2093 { |
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|
2094 static uint8_t * bp_stub = NULL; |
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2095 z80_options * opts = context->options; |
366
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2096 uint8_t * native = z80_get_native_address_trans(context, address); |
591
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|
2097 code_info tmp_code = {native, native+16}; |
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2098 mov_ir(&tmp_code, address, opts->gen.scratch1, SZ_W); |
366
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2099 if (!bp_stub) { |
591
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2100 code_info *code = &opts->gen.code; |
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2101 //TODO: do an alloc check here to make sure the prologue length calc works |
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|
2102 bp_stub = code->cur; |
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changeset
|
2103 call(&tmp_code, bp_stub); |
505
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2104 |
366
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2105 //Calculate length of prologue |
591
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|
2106 check_cycles_int(&opts->gen, address); |
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|
2107 int check_int_size = code->cur-bp_stub; |
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|
2108 code->cur = bp_stub; |
505
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The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
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|
2109 |
366
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2110 //Save context and call breakpoint handler |
591
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|
2111 call(code, (uint8_t *)z80_save_context); |
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changeset
|
2112 push_r(code, opts->gen.scratch1); |
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changeset
|
2113 mov_rr(code, opts->gen.context_reg, RDI, SZ_Q); |
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changeset
|
2114 mov_rr(code, opts->gen.scratch1, RSI, SZ_W); |
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changeset
|
2115 call(code, bp_handler); |
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Get Z80 core back into compileable state
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|
2116 mov_rr(code, RAX, opts->gen.context_reg, SZ_Q); |
366
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2117 //Restore context |
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2118 call(code, (uint8_t *)z80_load_context); |
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2119 pop_r(code, opts->gen.scratch1); |
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2120 //do prologue stuff |
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2121 cmp_rr(code, opts->gen.cycles, opts->gen.limit, SZ_D); |
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2122 uint8_t * jmp_off = code->cur+1; |
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2123 jcc(code, CC_NC, code->cur + 7); |
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2124 pop_r(code, opts->gen.scratch1); |
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2125 add_ir(code, check_int_size - (code->cur-native), opts->gen.scratch1, SZ_Q); |
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2126 push_r(code, opts->gen.scratch1); |
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2127 jmp(code, (uint8_t *)z80_handle_cycle_limit_int); |
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2128 *jmp_off = code->cur - (jmp_off+1); |
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2129 //jump back to body of translated instruction |
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2130 pop_r(code, opts->gen.scratch1); |
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2131 add_ir(code, check_int_size - (code->cur-native), opts->gen.scratch1, SZ_Q); |
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2132 jmp_r(code, opts->gen.scratch1); |
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2133 } else { |
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2134 call(&tmp_code, bp_stub); |
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2135 } |
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2136 } |
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2137 |
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2138 void zremove_breakpoint(z80_context * context, uint16_t address) |
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2139 { |
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2140 uint8_t * native = z80_get_native_address(context, address); |
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2141 z80_options * opts = context->options; |
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2142 code_info tmp_code = opts->gen.code; |
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2143 opts->gen.code.cur = native; |
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2144 opts->gen.code.last = native + 16; |
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2145 check_cycles_int(&opts->gen, address); |
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2146 opts->gen.code = tmp_code; |
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2147 } |
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2148 |
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2149 |