Mercurial > repos > blastem
annotate z80_to_x86.c @ 657:92ce5ea5ffc9
Use call_args and call_args_abi in Z80 core
author | Michael Pavone <pavone@retrodev.com> |
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date | Thu, 01 Jan 2015 20:07:47 -0800 |
parents | a18e3923481e |
children | 759c38bf97f8 |
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1 /* |
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2 Copyright 2013 Michael Pavone |
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The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
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3 This file is part of BlastEm. |
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4 BlastEm is free software distributed under the terms of the GNU General Public License version 3 or greater. See COPYING for full license text. |
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5 */ |
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6 #include "z80inst.h" |
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7 #include "z80_to_x86.h" |
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8 #include "gen_x86.h" |
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9 #include "mem.h" |
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10 #include <stdio.h> |
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11 #include <stdlib.h> |
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12 #include <stddef.h> |
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13 #include <string.h> |
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14 |
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15 #define MODE_UNUSED (MODE_IMMED-1) |
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16 |
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17 #define ZCYCLES RBP |
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18 #define ZLIMIT RDI |
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19 #define SCRATCH1 R13 |
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20 #define SCRATCH2 R14 |
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21 #define CONTEXT RSI |
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22 |
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23 //#define DO_DEBUG_PRINT |
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24 |
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25 #ifdef DO_DEBUG_PRINT |
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26 #define dprintf printf |
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27 #else |
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28 #define dprintf |
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29 #endif |
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30 |
652 | 31 uint32_t zbreakpoint_patch(z80_context * context, uint16_t address, code_ptr dst); |
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32 |
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33 uint8_t z80_size(z80inst * inst) |
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34 { |
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35 uint8_t reg = (inst->reg & 0x1F); |
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36 if (reg != Z80_UNUSED && reg != Z80_USE_IMMED) { |
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37 return reg < Z80_BC ? SZ_B : SZ_W; |
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38 } |
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39 //TODO: Handle any necessary special cases |
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40 return SZ_B; |
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41 } |
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42 |
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43 void translate_z80_reg(z80inst * inst, host_ea * ea, z80_options * opts) |
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44 { |
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45 code_info *code = &opts->gen.code; |
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46 if (inst->reg == Z80_USE_IMMED) { |
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47 ea->mode = MODE_IMMED; |
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48 ea->disp = inst->immed; |
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49 } else if ((inst->reg & 0x1F) == Z80_UNUSED) { |
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50 ea->mode = MODE_UNUSED; |
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51 } else { |
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52 ea->mode = MODE_REG_DIRECT; |
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53 if (inst->reg == Z80_IYH) { |
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54 if ((inst->addr_mode & 0x1F) == Z80_REG && inst->ea_reg == Z80_IYL) { |
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55 mov_rr(code, opts->regs[Z80_IY], opts->gen.scratch1, SZ_W); |
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56 ror_ir(code, 8, opts->gen.scratch1, SZ_W); |
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57 ea->base = opts->gen.scratch1; |
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58 } else { |
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59 ea->base = opts->regs[Z80_IYL]; |
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60 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W); |
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61 } |
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62 } else if(opts->regs[inst->reg] >= 0) { |
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63 ea->base = opts->regs[inst->reg]; |
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64 if (ea->base >= AH && ea->base <= BH) { |
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65 if ((inst->addr_mode & 0x1F) == Z80_REG) { |
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66 uint8_t other_reg = opts->regs[inst->ea_reg]; |
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67 if (other_reg >= R8 || (other_reg >= RSP && other_reg <= RDI)) { |
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68 //we can't mix an *H reg with a register that requires the REX prefix |
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69 ea->base = opts->regs[z80_low_reg(inst->reg)]; |
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70 ror_ir(code, 8, ea->base, SZ_W); |
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71 } |
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72 } else if((inst->addr_mode & 0x1F) != Z80_UNUSED && (inst->addr_mode & 0x1F) != Z80_IMMED) { |
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73 //temp regs require REX prefix too |
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74 ea->base = opts->regs[z80_low_reg(inst->reg)]; |
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75 ror_ir(code, 8, ea->base, SZ_W); |
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76 } |
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77 } |
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78 } else { |
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79 ea->mode = MODE_REG_DISPLACE8; |
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80 ea->base = opts->gen.context_reg; |
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81 ea->disp = offsetof(z80_context, regs) + inst->reg; |
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82 } |
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83 } |
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84 } |
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85 |
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86 void z80_save_reg(z80inst * inst, z80_options * opts) |
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87 { |
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88 code_info *code = &opts->gen.code; |
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89 if (inst->reg == Z80_IYH) { |
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90 if ((inst->addr_mode & 0x1F) == Z80_REG && inst->ea_reg == Z80_IYL) { |
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91 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W); |
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92 mov_rr(code, opts->gen.scratch1, opts->regs[Z80_IYL], SZ_B); |
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93 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W); |
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94 } else { |
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95 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W); |
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96 } |
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97 } else if (opts->regs[inst->reg] >= AH && opts->regs[inst->reg] <= BH) { |
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98 if ((inst->addr_mode & 0x1F) == Z80_REG) { |
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99 uint8_t other_reg = opts->regs[inst->ea_reg]; |
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100 if (other_reg >= R8 || (other_reg >= RSP && other_reg <= RDI)) { |
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101 //we can't mix an *H reg with a register that requires the REX prefix |
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102 ror_ir(code, 8, opts->regs[z80_low_reg(inst->reg)], SZ_W); |
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103 } |
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104 } else if((inst->addr_mode & 0x1F) != Z80_UNUSED && (inst->addr_mode & 0x1F) != Z80_IMMED) { |
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105 //temp regs require REX prefix too |
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106 ror_ir(code, 8, opts->regs[z80_low_reg(inst->reg)], SZ_W); |
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107 } |
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108 } |
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109 } |
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110 |
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111 void translate_z80_ea(z80inst * inst, host_ea * ea, z80_options * opts, uint8_t read, uint8_t modify) |
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112 { |
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113 code_info *code = &opts->gen.code; |
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114 uint8_t size, reg, areg; |
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115 ea->mode = MODE_REG_DIRECT; |
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116 areg = read ? opts->gen.scratch1 : opts->gen.scratch2; |
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117 switch(inst->addr_mode & 0x1F) |
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118 { |
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119 case Z80_REG: |
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120 if (inst->ea_reg == Z80_IYH) { |
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121 if (inst->reg == Z80_IYL) { |
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122 mov_rr(code, opts->regs[Z80_IY], opts->gen.scratch1, SZ_W); |
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123 ror_ir(code, 8, opts->gen.scratch1, SZ_W); |
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124 ea->base = opts->gen.scratch1; |
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125 } else { |
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126 ea->base = opts->regs[Z80_IYL]; |
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127 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W); |
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128 } |
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129 } else if(opts->regs[inst->ea_reg] >= 0) { |
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130 ea->base = opts->regs[inst->ea_reg]; |
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131 if (ea->base >= AH && ea->base <= BH && inst->reg != Z80_UNUSED && inst->reg != Z80_USE_IMMED) { |
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132 uint8_t other_reg = opts->regs[inst->reg]; |
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133 if (other_reg >= R8 || (other_reg >= RSP && other_reg <= RDI)) { |
267
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134 //we can't mix an *H reg with a register that requires the REX prefix |
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135 ea->base = opts->regs[z80_low_reg(inst->ea_reg)]; |
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136 ror_ir(code, 8, ea->base, SZ_W); |
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137 } |
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138 } |
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139 } else { |
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140 ea->mode = MODE_REG_DISPLACE8; |
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141 ea->base = CONTEXT; |
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142 ea->disp = offsetof(z80_context, regs) + inst->ea_reg; |
213
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143 } |
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144 break; |
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145 case Z80_REG_INDIRECT: |
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146 mov_rr(code, opts->regs[inst->ea_reg], areg, SZ_W); |
213
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147 size = z80_size(inst); |
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148 if (read) { |
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149 if (modify) { |
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150 //push_r(code, opts->gen.scratch1); |
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151 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, offsetof(z80_context, scratch1), SZ_W); |
213
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152 } |
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153 if (size == SZ_B) { |
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154 call(code, opts->read_8); |
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155 } else { |
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156 call(code, opts->read_16); |
213
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157 } |
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158 if (modify) { |
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159 //pop_r(code, opts->gen.scratch2); |
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160 mov_rdispr(code, opts->gen.context_reg, offsetof(z80_context, scratch1), opts->gen.scratch2, SZ_W); |
213
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161 } |
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162 } |
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163 ea->base = opts->gen.scratch1; |
213
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164 break; |
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165 case Z80_IMMED: |
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166 ea->mode = MODE_IMMED; |
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167 ea->disp = inst->immed; |
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168 break; |
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169 case Z80_IMMED_INDIRECT: |
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170 mov_ir(code, inst->immed, areg, SZ_W); |
213
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171 size = z80_size(inst); |
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172 if (read) { |
277
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173 /*if (modify) { |
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174 push_r(code, opts->gen.scratch1); |
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175 }*/ |
213
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176 if (size == SZ_B) { |
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177 call(code, opts->read_8); |
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178 } else { |
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179 call(code, opts->read_16); |
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180 } |
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181 if (modify) { |
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182 //pop_r(code, opts->gen.scratch2); |
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183 mov_ir(code, inst->immed, opts->gen.scratch2, SZ_W); |
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184 } |
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185 } |
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186 ea->base = opts->gen.scratch1; |
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187 break; |
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188 case Z80_IX_DISPLACE: |
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189 case Z80_IY_DISPLACE: |
300
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190 reg = opts->regs[(inst->addr_mode & 0x1F) == Z80_IX_DISPLACE ? Z80_IX : Z80_IY]; |
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191 mov_rr(code, reg, areg, SZ_W); |
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192 add_ir(code, inst->ea_reg & 0x80 ? inst->ea_reg - 256 : inst->ea_reg, areg, SZ_W); |
213
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193 size = z80_size(inst); |
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194 if (read) { |
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195 if (modify) { |
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196 //push_r(code, opts->gen.scratch1); |
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197 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, offsetof(z80_context, scratch1), SZ_W); |
213
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198 } |
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199 if (size == SZ_B) { |
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200 call(code, opts->read_8); |
213
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201 } else { |
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202 call(code, opts->read_16); |
213
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203 } |
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204 if (modify) { |
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205 //pop_r(code, opts->gen.scratch2); |
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206 mov_rdispr(code, opts->gen.context_reg, offsetof(z80_context, scratch1), opts->gen.scratch2, SZ_W); |
213
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207 } |
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208 } |
590
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209 ea->base = opts->gen.scratch1; |
213
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210 break; |
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211 case Z80_UNUSED: |
235
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212 ea->mode = MODE_UNUSED; |
213
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213 break; |
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214 default: |
300
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215 fprintf(stderr, "Unrecognized Z80 addressing mode %d\n", inst->addr_mode & 0x1F); |
213
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216 exit(1); |
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217 } |
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218 } |
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219 |
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220 void z80_save_ea(code_info *code, z80inst * inst, z80_options * opts) |
213
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221 { |
267
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222 if ((inst->addr_mode & 0x1F) == Z80_REG) { |
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223 if (inst->ea_reg == Z80_IYH) { |
312
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224 if (inst->reg == Z80_IYL) { |
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225 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W); |
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226 mov_rr(code, opts->gen.scratch1, opts->regs[Z80_IYL], SZ_B); |
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227 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W); |
312
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228 } else { |
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229 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W); |
312
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230 } |
267
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231 } else if (inst->reg != Z80_UNUSED && inst->reg != Z80_USE_IMMED && opts->regs[inst->ea_reg] >= AH && opts->regs[inst->ea_reg] <= BH) { |
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232 uint8_t other_reg = opts->regs[inst->reg]; |
269
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233 if (other_reg >= R8 || (other_reg >= RSP && other_reg <= RDI)) { |
267
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234 //we can't mix an *H reg with a register that requires the REX prefix |
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235 ror_ir(code, 8, opts->regs[z80_low_reg(inst->ea_reg)], SZ_W); |
267
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236 } |
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237 } |
213
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238 } |
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239 } |
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240 |
593
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241 void z80_save_result(z80_options *opts, z80inst * inst) |
213
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242 { |
253
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243 switch(inst->addr_mode & 0x1f) |
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244 { |
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245 case Z80_REG_INDIRECT: |
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246 case Z80_IMMED_INDIRECT: |
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247 case Z80_IX_DISPLACE: |
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248 case Z80_IY_DISPLACE: |
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249 if (z80_size(inst) == SZ_B) { |
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250 call(&opts->gen.code, opts->write_8); |
253
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251 } else { |
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252 call(&opts->gen.code, opts->write_16_lowfirst); |
253
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253 } |
213
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254 } |
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255 } |
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256 |
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257 enum { |
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258 DONT_READ=0, |
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259 READ |
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260 }; |
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261 |
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262 enum { |
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263 DONT_MODIFY=0, |
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264 MODIFY |
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265 }; |
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266 |
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267 uint8_t zf_off(uint8_t flag) |
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268 { |
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269 return offsetof(z80_context, flags) + flag; |
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270 } |
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271 |
241
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272 uint8_t zaf_off(uint8_t flag) |
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273 { |
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274 return offsetof(z80_context, alt_flags) + flag; |
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275 } |
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276 |
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277 uint8_t zar_off(uint8_t reg) |
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278 { |
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279 return offsetof(z80_context, alt_regs) + reg; |
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280 } |
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281 |
235
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282 void z80_print_regs_exit(z80_context * context) |
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283 { |
505
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284 printf("A: %X\nB: %X\nC: %X\nD: %X\nE: %X\nHL: %X\nIX: %X\nIY: %X\nSP: %X\n\nIM: %d, IFF1: %d, IFF2: %d\n", |
235
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285 context->regs[Z80_A], context->regs[Z80_B], context->regs[Z80_C], |
505
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286 context->regs[Z80_D], context->regs[Z80_E], |
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287 (context->regs[Z80_H] << 8) | context->regs[Z80_L], |
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288 (context->regs[Z80_IXH] << 8) | context->regs[Z80_IXL], |
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289 (context->regs[Z80_IYH] << 8) | context->regs[Z80_IYL], |
243
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290 context->sp, context->im, context->iff1, context->iff2); |
241
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291 puts("--Alternate Regs--"); |
505
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292 printf("A: %X\nB: %X\nC: %X\nD: %X\nE: %X\nHL: %X\nIX: %X\nIY: %X\n", |
241
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293 context->alt_regs[Z80_A], context->alt_regs[Z80_B], context->alt_regs[Z80_C], |
505
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294 context->alt_regs[Z80_D], context->alt_regs[Z80_E], |
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295 (context->alt_regs[Z80_H] << 8) | context->alt_regs[Z80_L], |
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296 (context->alt_regs[Z80_IXH] << 8) | context->alt_regs[Z80_IXL], |
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297 (context->alt_regs[Z80_IYH] << 8) | context->alt_regs[Z80_IYL]); |
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298 exit(0); |
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299 } |
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300 |
652 | 301 void translate_z80inst(z80inst * inst, z80_context * context, uint16_t address, uint8_t interp) |
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302 { |
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303 uint32_t num_cycles; |
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304 host_ea src_op, dst_op; |
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305 uint8_t size; |
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306 z80_options *opts = context->options; |
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307 uint8_t * start = opts->gen.code.cur; |
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308 code_info *code = &opts->gen.code; |
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309 if (!interp) { |
652 | 310 check_cycles_int(&opts->gen, address); |
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311 if (context->breakpoint_flags[address / sizeof(uint8_t)] & (1 << (address % sizeof(uint8_t)))) { |
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312 zbreakpoint_patch(context, address, start); |
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313 } |
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314 } |
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315 switch(inst->op) |
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316 { |
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317 case Z80_LD: |
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318 size = z80_size(inst); |
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319 switch (inst->addr_mode & 0x1F) |
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320 { |
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321 case Z80_REG: |
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322 case Z80_REG_INDIRECT: |
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323 num_cycles = size == SZ_B ? 4 : 6; |
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324 if (inst->ea_reg == Z80_IX || inst->ea_reg == Z80_IY) { |
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325 num_cycles += 4; |
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326 } |
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327 if (inst->reg == Z80_I || inst->ea_reg == Z80_I) { |
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328 num_cycles += 5; |
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329 } |
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330 break; |
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331 case Z80_IMMED: |
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332 num_cycles = size == SZ_B ? 7 : 10; |
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333 break; |
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334 case Z80_IMMED_INDIRECT: |
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335 num_cycles = 10; |
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336 break; |
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337 case Z80_IX_DISPLACE: |
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338 case Z80_IY_DISPLACE: |
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339 num_cycles = 16; |
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340 break; |
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341 } |
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342 if ((inst->reg >= Z80_IXL && inst->reg <= Z80_IYH) || inst->reg == Z80_IX || inst->reg == Z80_IY) { |
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343 num_cycles += 4; |
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344 } |
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345 cycles(&opts->gen, num_cycles); |
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346 if (inst->addr_mode & Z80_DIR) { |
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347 translate_z80_ea(inst, &dst_op, opts, DONT_READ, MODIFY); |
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348 translate_z80_reg(inst, &src_op, opts); |
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349 } else { |
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350 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY); |
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351 translate_z80_reg(inst, &dst_op, opts); |
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352 } |
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353 if (src_op.mode == MODE_REG_DIRECT) { |
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354 if(dst_op.mode == MODE_REG_DISPLACE8) { |
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355 mov_rrdisp(code, src_op.base, dst_op.base, dst_op.disp, size); |
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356 } else { |
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357 mov_rr(code, src_op.base, dst_op.base, size); |
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358 } |
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359 } else if(src_op.mode == MODE_IMMED) { |
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360 mov_ir(code, src_op.disp, dst_op.base, size); |
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361 } else { |
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362 mov_rdispr(code, src_op.base, src_op.disp, dst_op.base, size); |
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363 } |
651
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364 if (inst->ea_reg == Z80_I && inst->addr_mode == Z80_REG) { |
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365 //ld a, i sets some flags |
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366 //TODO: Implement half-carry flag |
652 | 367 cmp_ir(code, 0, dst_op.base, SZ_B); |
368 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); | |
369 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); | |
370 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);; | |
371 mov_rdispr(code, opts->gen.context_reg, offsetof(z80_context, iff2), SCRATCH1, SZ_B); | |
372 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_PV), SZ_B); | |
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373 } |
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374 z80_save_reg(inst, opts); |
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375 z80_save_ea(code, inst, opts); |
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376 if (inst->addr_mode & Z80_DIR) { |
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377 z80_save_result(opts, inst); |
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378 } |
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379 break; |
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380 case Z80_PUSH: |
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381 cycles(&opts->gen, (inst->reg == Z80_IX || inst->reg == Z80_IY) ? 9 : 5); |
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382 sub_ir(code, 2, opts->regs[Z80_SP], SZ_W); |
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383 if (inst->reg == Z80_AF) { |
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384 mov_rr(code, opts->regs[Z80_A], opts->gen.scratch1, SZ_B); |
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385 shl_ir(code, 8, opts->gen.scratch1, SZ_W); |
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386 mov_rdispr(code, opts->gen.context_reg, zf_off(ZF_S), opts->gen.scratch1, SZ_B); |
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387 shl_ir(code, 1, opts->gen.scratch1, SZ_B); |
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388 or_rdispr(code, opts->gen.context_reg, zf_off(ZF_Z), opts->gen.scratch1, SZ_B); |
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389 shl_ir(code, 2, opts->gen.scratch1, SZ_B); |
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390 or_rdispr(code, opts->gen.context_reg, zf_off(ZF_H), opts->gen.scratch1, SZ_B); |
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391 shl_ir(code, 2, opts->gen.scratch1, SZ_B); |
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392 or_rdispr(code, opts->gen.context_reg, zf_off(ZF_PV), opts->gen.scratch1, SZ_B); |
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393 shl_ir(code, 1, opts->gen.scratch1, SZ_B); |
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394 or_rdispr(code, opts->gen.context_reg, zf_off(ZF_N), opts->gen.scratch1, SZ_B); |
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395 shl_ir(code, 1, opts->gen.scratch1, SZ_B); |
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396 or_rdispr(code, opts->gen.context_reg, zf_off(ZF_C), opts->gen.scratch1, SZ_B); |
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397 } else { |
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398 translate_z80_reg(inst, &src_op, opts); |
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399 mov_rr(code, src_op.base, opts->gen.scratch1, SZ_W); |
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400 } |
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401 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch2, SZ_W); |
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402 call(code, opts->write_16_highfirst); |
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403 //no call to save_z80_reg needed since there's no chance we'll use the only |
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404 //the upper half of a register pair |
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405 break; |
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406 case Z80_POP: |
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407 cycles(&opts->gen, (inst->reg == Z80_IX || inst->reg == Z80_IY) ? 8 : 4); |
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408 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W); |
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409 call(code, opts->read_16); |
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410 add_ir(code, 2, opts->regs[Z80_SP], SZ_W); |
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411 if (inst->reg == Z80_AF) { |
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412 |
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413 bt_ir(code, 0, opts->gen.scratch1, SZ_W); |
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414 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
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415 bt_ir(code, 1, opts->gen.scratch1, SZ_W); |
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416 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_N)); |
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417 bt_ir(code, 2, opts->gen.scratch1, SZ_W); |
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418 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_PV)); |
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419 bt_ir(code, 4, opts->gen.scratch1, SZ_W); |
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420 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H)); |
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421 bt_ir(code, 6, opts->gen.scratch1, SZ_W); |
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422 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_Z)); |
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423 bt_ir(code, 7, opts->gen.scratch1, SZ_W); |
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424 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_S)); |
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425 shr_ir(code, 8, opts->gen.scratch1, SZ_W); |
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426 mov_rr(code, opts->gen.scratch1, opts->regs[Z80_A], SZ_B); |
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427 } else { |
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428 translate_z80_reg(inst, &src_op, opts); |
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429 mov_rr(code, opts->gen.scratch1, src_op.base, SZ_W); |
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430 } |
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431 //no call to save_z80_reg needed since there's no chance we'll use the only |
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432 //the upper half of a register pair |
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433 break; |
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434 case Z80_EX: |
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435 if (inst->addr_mode == Z80_REG || inst->reg == Z80_HL) { |
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436 num_cycles = 4; |
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437 } else { |
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438 num_cycles = 8; |
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439 } |
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440 cycles(&opts->gen, num_cycles); |
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441 if (inst->addr_mode == Z80_REG) { |
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442 if(inst->reg == Z80_AF) { |
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443 mov_rr(code, opts->regs[Z80_A], opts->gen.scratch1, SZ_B); |
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444 mov_rdispr(code, opts->gen.context_reg, zar_off(Z80_A), opts->regs[Z80_A], SZ_B); |
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445 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zar_off(Z80_A), SZ_B); |
505
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446 |
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447 //Flags are currently word aligned, so we can move |
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448 //them efficiently a word at a time |
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449 for (int f = ZF_C; f < ZF_NUM; f+=2) { |
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450 mov_rdispr(code, opts->gen.context_reg, zf_off(f), opts->gen.scratch1, SZ_W); |
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451 mov_rdispr(code, opts->gen.context_reg, zaf_off(f), opts->gen.scratch2, SZ_W); |
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452 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zaf_off(f), SZ_W); |
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453 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(f), SZ_W); |
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454 } |
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455 } else { |
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456 xchg_rr(code, opts->regs[Z80_DE], opts->regs[Z80_HL], SZ_W); |
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457 } |
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458 } else { |
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459 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W); |
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460 call(code, opts->read_8); |
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461 xchg_rr(code, opts->regs[inst->reg], opts->gen.scratch1, SZ_B); |
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462 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch2, SZ_W); |
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463 call(code, opts->write_8); |
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464 cycles(&opts->gen, 1); |
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465 uint8_t high_reg = z80_high_reg(inst->reg); |
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466 uint8_t use_reg; |
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467 //even though some of the upper halves can be used directly |
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468 //the limitations on mixing *H regs with the REX prefix |
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469 //prevent us from taking advantage of it |
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470 use_reg = opts->regs[inst->reg]; |
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471 ror_ir(code, 8, use_reg, SZ_W); |
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472 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W); |
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473 add_ir(code, 1, opts->gen.scratch1, SZ_W); |
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474 call(code, opts->read_8); |
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475 xchg_rr(code, use_reg, opts->gen.scratch1, SZ_B); |
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476 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch2, SZ_W); |
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477 add_ir(code, 1, opts->gen.scratch2, SZ_W); |
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478 call(code, opts->write_8); |
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479 //restore reg to normal rotation |
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480 ror_ir(code, 8, use_reg, SZ_W); |
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481 cycles(&opts->gen, 2); |
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482 } |
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483 break; |
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484 case Z80_EXX: |
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485 cycles(&opts->gen, 4); |
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486 mov_rr(code, opts->regs[Z80_BC], opts->gen.scratch1, SZ_W); |
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487 mov_rr(code, opts->regs[Z80_HL], opts->gen.scratch2, SZ_W); |
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488 mov_rdispr(code, opts->gen.context_reg, zar_off(Z80_C), opts->regs[Z80_BC], SZ_W); |
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489 mov_rdispr(code, opts->gen.context_reg, zar_off(Z80_L), opts->regs[Z80_HL], SZ_W); |
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490 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zar_off(Z80_C), SZ_W); |
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491 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zar_off(Z80_L), SZ_W); |
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492 mov_rr(code, opts->regs[Z80_DE], opts->gen.scratch1, SZ_W); |
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493 mov_rdispr(code, opts->gen.context_reg, zar_off(Z80_E), opts->regs[Z80_DE], SZ_W); |
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494 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zar_off(Z80_E), SZ_W); |
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495 break; |
272 | 496 case Z80_LDI: { |
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497 cycles(&opts->gen, 8); |
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498 mov_rr(code, opts->regs[Z80_HL], opts->gen.scratch1, SZ_W); |
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499 call(code, opts->read_8); |
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500 mov_rr(code, opts->regs[Z80_DE], opts->gen.scratch2, SZ_W); |
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501 call(code, opts->write_8); |
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502 cycles(&opts->gen, 2); |
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503 add_ir(code, 1, opts->regs[Z80_DE], SZ_W); |
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504 add_ir(code, 1, opts->regs[Z80_HL], SZ_W); |
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505 sub_ir(code, 1, opts->regs[Z80_BC], SZ_W); |
272 | 506 //TODO: Implement half-carry |
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507 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
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508 setcc_rdisp(code, CC_NZ, opts->gen.context_reg, zf_off(ZF_PV)); |
272 | 509 break; |
510 } | |
261
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511 case Z80_LDIR: { |
591
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512 cycles(&opts->gen, 8); |
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513 mov_rr(code, opts->regs[Z80_HL], opts->gen.scratch1, SZ_W); |
593
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514 call(code, opts->read_8); |
591
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515 mov_rr(code, opts->regs[Z80_DE], opts->gen.scratch2, SZ_W); |
593
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516 call(code, opts->write_8); |
591
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517 add_ir(code, 1, opts->regs[Z80_DE], SZ_W); |
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518 add_ir(code, 1, opts->regs[Z80_HL], SZ_W); |
505
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The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
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519 |
591
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520 sub_ir(code, 1, opts->regs[Z80_BC], SZ_W); |
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521 uint8_t * cont = code->cur+1; |
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522 jcc(code, CC_Z, code->cur+2); |
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523 cycles(&opts->gen, 7); |
261
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524 //TODO: Figure out what the flag state should be here |
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525 //TODO: Figure out whether an interrupt can interrupt this |
591
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526 jmp(code, start); |
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527 *cont = code->cur - (cont + 1); |
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528 cycles(&opts->gen, 2); |
261
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529 //TODO: Implement half-carry |
591
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530 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
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531 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_PV), SZ_B); |
261
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532 break; |
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533 } |
273 | 534 case Z80_LDD: { |
591
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535 cycles(&opts->gen, 8); |
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536 mov_rr(code, opts->regs[Z80_HL], opts->gen.scratch1, SZ_W); |
593
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537 call(code, opts->read_8); |
591
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538 mov_rr(code, opts->regs[Z80_DE], opts->gen.scratch2, SZ_W); |
593
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539 call(code, opts->write_8); |
591
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540 cycles(&opts->gen, 2); |
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541 sub_ir(code, 1, opts->regs[Z80_DE], SZ_W); |
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542 sub_ir(code, 1, opts->regs[Z80_HL], SZ_W); |
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543 sub_ir(code, 1, opts->regs[Z80_BC], SZ_W); |
273 | 544 //TODO: Implement half-carry |
591
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545 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
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546 setcc_rdisp(code, CC_NZ, opts->gen.context_reg, zf_off(ZF_PV)); |
273 | 547 break; |
548 } | |
549 case Z80_LDDR: { | |
591
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550 cycles(&opts->gen, 8); |
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551 mov_rr(code, opts->regs[Z80_HL], opts->gen.scratch1, SZ_W); |
593
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552 call(code, opts->read_8); |
591
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553 mov_rr(code, opts->regs[Z80_DE], opts->gen.scratch2, SZ_W); |
593
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554 call(code, opts->write_8); |
591
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555 sub_ir(code, 1, opts->regs[Z80_DE], SZ_W); |
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556 sub_ir(code, 1, opts->regs[Z80_HL], SZ_W); |
505
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The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
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557 |
591
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558 sub_ir(code, 1, opts->regs[Z80_BC], SZ_W); |
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559 uint8_t * cont = code->cur+1; |
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560 jcc(code, CC_Z, code->cur+2); |
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561 cycles(&opts->gen, 7); |
273 | 562 //TODO: Figure out what the flag state should be here |
563 //TODO: Figure out whether an interrupt can interrupt this | |
591
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564 jmp(code, start); |
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565 *cont = code->cur - (cont + 1); |
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566 cycles(&opts->gen, 2); |
273 | 567 //TODO: Implement half-carry |
591
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568 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
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569 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_PV), SZ_B); |
273 | 570 break; |
571 } | |
572 /*case Z80_CPI: | |
213
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573 case Z80_CPIR: |
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574 case Z80_CPD: |
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575 case Z80_CPDR: |
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576 break;*/ |
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577 case Z80_ADD: |
591
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578 num_cycles = 4; |
235
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579 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
591
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580 num_cycles += 12; |
213
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581 } else if(inst->addr_mode == Z80_IMMED) { |
591
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582 num_cycles += 3; |
213
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583 } else if(z80_size(inst) == SZ_W) { |
591
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584 num_cycles += 4; |
213
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585 } |
591
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586 cycles(&opts->gen, num_cycles); |
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587 translate_z80_reg(inst, &dst_op, opts); |
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588 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY); |
213
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589 if (src_op.mode == MODE_REG_DIRECT) { |
591
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590 add_rr(code, src_op.base, dst_op.base, z80_size(inst)); |
213
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591 } else { |
591
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592 add_ir(code, src_op.disp, dst_op.base, z80_size(inst)); |
213
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|
593 } |
591
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594 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
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595 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
213
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|
596 //TODO: Implement half-carry flag |
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597 if (z80_size(inst) == SZ_B) { |
591
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598 setcc_rdisp(code, CC_O, opts->gen.context_reg, zf_off(ZF_PV)); |
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599 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
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600 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
213
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601 } |
591
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602 z80_save_reg(inst, opts); |
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603 z80_save_ea(code, inst, opts); |
213
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604 break; |
248
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605 case Z80_ADC: |
591
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606 num_cycles = 4; |
248
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607 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
591
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608 num_cycles += 12; |
248
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609 } else if(inst->addr_mode == Z80_IMMED) { |
591
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610 num_cycles += 3; |
248
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611 } else if(z80_size(inst) == SZ_W) { |
591
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612 num_cycles += 4; |
248
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613 } |
591
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614 cycles(&opts->gen, num_cycles); |
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615 translate_z80_reg(inst, &dst_op, opts); |
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616 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY); |
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617 bt_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B); |
248
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618 if (src_op.mode == MODE_REG_DIRECT) { |
591
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619 adc_rr(code, src_op.base, dst_op.base, z80_size(inst)); |
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620 } else { |
591
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621 adc_ir(code, src_op.disp, dst_op.base, z80_size(inst)); |
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622 } |
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623 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
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624 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
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625 //TODO: Implement half-carry flag |
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626 setcc_rdisp(code, CC_O, opts->gen.context_reg, zf_off(ZF_PV)); |
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627 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
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628 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
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629 z80_save_reg(inst, opts); |
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630 z80_save_ea(code, inst, opts); |
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631 break; |
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632 case Z80_SUB: |
591
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633 num_cycles = 4; |
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634 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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635 num_cycles += 12; |
213
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636 } else if(inst->addr_mode == Z80_IMMED) { |
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637 num_cycles += 3; |
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638 } |
591
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639 cycles(&opts->gen, num_cycles); |
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640 translate_z80_reg(inst, &dst_op, opts); |
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641 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY); |
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642 if (src_op.mode == MODE_REG_DIRECT) { |
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643 sub_rr(code, src_op.base, dst_op.base, z80_size(inst)); |
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644 } else { |
591
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645 sub_ir(code, src_op.disp, dst_op.base, z80_size(inst)); |
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646 } |
591
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647 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
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648 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
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649 setcc_rdisp(code, CC_O, opts->gen.context_reg, zf_off(ZF_PV)); |
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650 //TODO: Implement half-carry flag |
591
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651 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
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652 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
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653 z80_save_reg(inst, opts); |
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654 z80_save_ea(code, inst, opts); |
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655 break; |
248
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656 case Z80_SBC: |
591
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657 num_cycles = 4; |
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658 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
591
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659 num_cycles += 12; |
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660 } else if(inst->addr_mode == Z80_IMMED) { |
591
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661 num_cycles += 3; |
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662 } else if(z80_size(inst) == SZ_W) { |
591
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663 num_cycles += 4; |
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664 } |
591
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665 cycles(&opts->gen, num_cycles); |
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666 translate_z80_reg(inst, &dst_op, opts); |
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667 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY); |
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668 bt_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B); |
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669 if (src_op.mode == MODE_REG_DIRECT) { |
591
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670 sbb_rr(code, src_op.base, dst_op.base, z80_size(inst)); |
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671 } else { |
591
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672 sbb_ir(code, src_op.disp, dst_op.base, z80_size(inst)); |
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673 } |
591
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674 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
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675 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
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676 //TODO: Implement half-carry flag |
591
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677 setcc_rdisp(code, CC_O, opts->gen.context_reg, zf_off(ZF_PV)); |
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678 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
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679 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
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680 z80_save_reg(inst, opts); |
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681 z80_save_ea(code, inst, opts); |
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682 break; |
213
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683 case Z80_AND: |
591
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684 num_cycles = 4; |
236
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685 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
591
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686 num_cycles += 12; |
236
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687 } else if(inst->addr_mode == Z80_IMMED) { |
591
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688 num_cycles += 3; |
236
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689 } else if(z80_size(inst) == SZ_W) { |
591
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690 num_cycles += 4; |
236
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691 } |
591
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692 cycles(&opts->gen, num_cycles); |
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693 translate_z80_reg(inst, &dst_op, opts); |
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694 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY); |
236
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695 if (src_op.mode == MODE_REG_DIRECT) { |
591
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696 and_rr(code, src_op.base, dst_op.base, z80_size(inst)); |
236
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697 } else { |
591
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698 and_ir(code, src_op.disp, dst_op.base, z80_size(inst)); |
236
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699 } |
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700 //TODO: Cleanup flags |
591
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701 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
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702 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
236
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703 //TODO: Implement half-carry flag |
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704 if (z80_size(inst) == SZ_B) { |
591
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705 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV)); |
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706 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
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707 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
236
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708 } |
591
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|
709 z80_save_reg(inst, opts); |
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|
710 z80_save_ea(code, inst, opts); |
236
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711 break; |
213
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|
712 case Z80_OR: |
591
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713 num_cycles = 4; |
236
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714 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
591
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715 num_cycles += 12; |
236
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716 } else if(inst->addr_mode == Z80_IMMED) { |
591
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717 num_cycles += 3; |
236
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718 } else if(z80_size(inst) == SZ_W) { |
591
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719 num_cycles += 4; |
236
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720 } |
591
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721 cycles(&opts->gen, num_cycles); |
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|
722 translate_z80_reg(inst, &dst_op, opts); |
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|
723 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY); |
236
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724 if (src_op.mode == MODE_REG_DIRECT) { |
591
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|
725 or_rr(code, src_op.base, dst_op.base, z80_size(inst)); |
236
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726 } else { |
591
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727 or_ir(code, src_op.disp, dst_op.base, z80_size(inst)); |
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728 } |
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729 //TODO: Cleanup flags |
591
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730 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
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731 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
236
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732 //TODO: Implement half-carry flag |
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733 if (z80_size(inst) == SZ_B) { |
591
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734 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV)); |
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|
735 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
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736 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
236
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737 } |
591
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738 z80_save_reg(inst, opts); |
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739 z80_save_ea(code, inst, opts); |
236
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740 break; |
213
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|
741 case Z80_XOR: |
591
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742 num_cycles = 4; |
236
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743 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
591
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744 num_cycles += 12; |
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745 } else if(inst->addr_mode == Z80_IMMED) { |
591
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746 num_cycles += 3; |
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747 } else if(z80_size(inst) == SZ_W) { |
591
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748 num_cycles += 4; |
236
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749 } |
591
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750 cycles(&opts->gen, num_cycles); |
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751 translate_z80_reg(inst, &dst_op, opts); |
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752 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY); |
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753 if (src_op.mode == MODE_REG_DIRECT) { |
591
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754 xor_rr(code, src_op.base, dst_op.base, z80_size(inst)); |
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755 } else { |
591
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756 xor_ir(code, src_op.disp, dst_op.base, z80_size(inst)); |
236
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757 } |
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|
758 //TODO: Cleanup flags |
591
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759 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
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760 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
236
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761 //TODO: Implement half-carry flag |
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762 if (z80_size(inst) == SZ_B) { |
591
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763 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV)); |
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764 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
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765 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
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766 } |
591
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767 z80_save_reg(inst, opts); |
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768 z80_save_ea(code, inst, opts); |
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769 break; |
242 | 770 case Z80_CP: |
591
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771 num_cycles = 4; |
242 | 772 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
591
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773 num_cycles += 12; |
242 | 774 } else if(inst->addr_mode == Z80_IMMED) { |
591
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775 num_cycles += 3; |
242 | 776 } |
591
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777 cycles(&opts->gen, num_cycles); |
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778 translate_z80_reg(inst, &dst_op, opts); |
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779 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY); |
242 | 780 if (src_op.mode == MODE_REG_DIRECT) { |
591
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781 cmp_rr(code, src_op.base, dst_op.base, z80_size(inst)); |
242 | 782 } else { |
591
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783 cmp_ir(code, src_op.disp, dst_op.base, z80_size(inst)); |
242 | 784 } |
591
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785 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
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786 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
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787 setcc_rdisp(code, CC_O, opts->gen.context_reg, zf_off(ZF_PV)); |
242 | 788 //TODO: Implement half-carry flag |
591
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789 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
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790 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
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791 z80_save_reg(inst, opts); |
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792 z80_save_ea(code, inst, opts); |
242 | 793 break; |
213
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|
794 case Z80_INC: |
591
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795 num_cycles = 4; |
213
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|
796 if (inst->reg == Z80_IX || inst->reg == Z80_IY) { |
591
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797 num_cycles += 6; |
213
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|
798 } else if(z80_size(inst) == SZ_W) { |
591
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|
799 num_cycles += 2; |
213
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|
800 } else if(inst->reg == Z80_IXH || inst->reg == Z80_IXL || inst->reg == Z80_IYH || inst->reg == Z80_IYL || inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
591
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|
801 num_cycles += 4; |
213
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|
802 } |
591
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|
803 cycles(&opts->gen, num_cycles); |
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|
804 translate_z80_reg(inst, &dst_op, opts); |
213
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|
805 if (dst_op.mode == MODE_UNUSED) { |
591
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|
806 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY); |
213
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|
807 } |
591
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|
808 add_ir(code, 1, dst_op.base, z80_size(inst)); |
213
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|
809 if (z80_size(inst) == SZ_B) { |
591
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|
810 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
213
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changeset
|
811 //TODO: Implement half-carry flag |
591
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|
812 setcc_rdisp(code, CC_O, opts->gen.context_reg, zf_off(ZF_PV)); |
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|
813 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
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|
814 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
213
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|
815 } |
591
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|
816 z80_save_reg(inst, opts); |
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diff
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|
817 z80_save_ea(code, inst, opts); |
593
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592
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changeset
|
818 z80_save_result(opts, inst); |
213
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|
819 break; |
236
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820 case Z80_DEC: |
591
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821 num_cycles = 4; |
236
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822 if (inst->reg == Z80_IX || inst->reg == Z80_IY) { |
591
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823 num_cycles += 6; |
236
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824 } else if(z80_size(inst) == SZ_W) { |
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|
825 num_cycles += 2; |
236
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826 } else if(inst->reg == Z80_IXH || inst->reg == Z80_IXL || inst->reg == Z80_IYH || inst->reg == Z80_IYL || inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
591
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|
827 num_cycles += 4; |
236
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828 } |
591
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changeset
|
829 cycles(&opts->gen, num_cycles); |
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|
830 translate_z80_reg(inst, &dst_op, opts); |
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|
831 if (dst_op.mode == MODE_UNUSED) { |
591
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|
832 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY); |
236
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833 } |
591
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|
834 sub_ir(code, 1, dst_op.base, z80_size(inst)); |
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835 if (z80_size(inst) == SZ_B) { |
591
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diff
changeset
|
836 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
236
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|
837 //TODO: Implement half-carry flag |
591
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838 setcc_rdisp(code, CC_O, opts->gen.context_reg, zf_off(ZF_PV)); |
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|
839 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
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|
840 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
236
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841 } |
591
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|
842 z80_save_reg(inst, opts); |
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diff
changeset
|
843 z80_save_ea(code, inst, opts); |
593
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diff
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|
844 z80_save_result(opts, inst); |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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|
845 break; |
274
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846 //case Z80_DAA: |
213
4d4559b04c59
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diff
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|
847 case Z80_CPL: |
591
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848 cycles(&opts->gen, 4); |
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|
849 not_r(code, opts->regs[Z80_A], SZ_B); |
274
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850 //TODO: Implement half-carry flag |
591
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|
851 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
274
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852 break; |
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853 case Z80_NEG: |
591
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|
854 cycles(&opts->gen, 8); |
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|
855 neg_r(code, opts->regs[Z80_A], SZ_B); |
274
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856 //TODO: Implement half-carry flag |
591
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857 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
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858 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
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859 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
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|
860 setcc_rdisp(code, CC_O, opts->gen.context_reg, zf_off(ZF_PV)); |
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|
861 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
274
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862 break; |
213
4d4559b04c59
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diff
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|
863 case Z80_CCF: |
591
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864 cycles(&opts->gen, 4); |
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|
865 xor_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_C), SZ_B); |
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diff
changeset
|
866 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
257 | 867 //TODO: Implement half-carry flag |
868 break; | |
869 case Z80_SCF: | |
591
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|
870 cycles(&opts->gen, 4); |
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871 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_C), SZ_B); |
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|
872 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
257 | 873 //TODO: Implement half-carry flag |
874 break; | |
213
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|
875 case Z80_NOP: |
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|
876 if (inst->immed == 42) { |
593
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|
877 call(code, opts->gen.save_context); |
657
92ce5ea5ffc9
Use call_args and call_args_abi in Z80 core
Michael Pavone <pavone@retrodev.com>
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653
diff
changeset
|
878 call_args(code, (code_ptr)z80_print_regs_exit, 1, opts->gen.context_reg); |
213
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diff
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|
879 } else { |
591
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|
880 cycles(&opts->gen, 4 * inst->immed); |
213
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diff
changeset
|
881 } |
4d4559b04c59
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Mike Pavone <pavone@retrodev.com>
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diff
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|
882 break; |
593
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diff
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|
883 case Z80_HALT: { |
591
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|
884 cycles(&opts->gen, 4); |
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|
885 mov_ir(code, address, opts->gen.scratch1, SZ_W); |
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diff
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|
886 uint8_t * call_inst = code->cur; |
593
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diff
changeset
|
887 mov_rr(code, opts->gen.limit, opts->gen.scratch2, SZ_D); |
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|
888 sub_rr(code, opts->gen.cycles, opts->gen.scratch2, SZ_D); |
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diff
changeset
|
889 and_ir(code, 0xFFFFFFFC, opts->gen.scratch2, SZ_D); |
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diff
changeset
|
890 add_rr(code, opts->gen.scratch2, opts->gen.cycles, SZ_D); |
5ef3fe516da9
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diff
changeset
|
891 cmp_rr(code, opts->gen.limit, opts->gen.cycles, SZ_D); |
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592
diff
changeset
|
892 code_ptr skip_last = code->cur+1; |
594
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
893 jcc(code, CC_NB, code->cur+2); |
593
5ef3fe516da9
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592
diff
changeset
|
894 cycles(&opts->gen, 4); |
5ef3fe516da9
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592
diff
changeset
|
895 *skip_last = code->cur - (skip_last+1); |
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592
diff
changeset
|
896 call(code, opts->gen.handle_cycle_limit_int); |
591
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Get Z80 core back into compileable state
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590
diff
changeset
|
897 jmp(code, call_inst); |
285
021aeb6df19b
Implement HALT (sort of tested)
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284
diff
changeset
|
898 break; |
593
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diff
changeset
|
899 } |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
900 case Z80_DI: |
591
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diff
changeset
|
901 cycles(&opts->gen, 4); |
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590
diff
changeset
|
902 mov_irdisp(code, 0, opts->gen.context_reg, offsetof(z80_context, iff1), SZ_B); |
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Get Z80 core back into compileable state
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diff
changeset
|
903 mov_irdisp(code, 0, opts->gen.context_reg, offsetof(z80_context, iff2), SZ_B); |
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Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
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diff
changeset
|
904 mov_rdispr(code, opts->gen.context_reg, offsetof(z80_context, sync_cycle), opts->gen.limit, SZ_D); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
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590
diff
changeset
|
905 mov_irdisp(code, 0xFFFFFFFF, opts->gen.context_reg, offsetof(z80_context, int_cycle), SZ_D); |
243
2f069a0b487e
Implement EI, DI and IM in the Z80 core
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242
diff
changeset
|
906 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
907 case Z80_EI: |
591
966b46c68942
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590
diff
changeset
|
908 cycles(&opts->gen, 4); |
966b46c68942
Get Z80 core back into compileable state
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590
diff
changeset
|
909 mov_rrdisp(code, opts->gen.cycles, opts->gen.context_reg, offsetof(z80_context, int_enable_cycle), SZ_D); |
966b46c68942
Get Z80 core back into compileable state
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590
diff
changeset
|
910 mov_irdisp(code, 1, opts->gen.context_reg, offsetof(z80_context, iff1), SZ_B); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
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diff
changeset
|
911 mov_irdisp(code, 1, opts->gen.context_reg, offsetof(z80_context, iff2), SZ_B); |
335 | 912 //interrupt enable has a one-instruction latency, minimum instruction duration is 4 cycles |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
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590
diff
changeset
|
913 add_irdisp(code, 4, opts->gen.context_reg, offsetof(z80_context, int_enable_cycle), SZ_D); |
593
5ef3fe516da9
Z80 core is sort of working again
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592
diff
changeset
|
914 call(code, opts->do_sync); |
243
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
915 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
916 case Z80_IM: |
591
966b46c68942
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590
diff
changeset
|
917 cycles(&opts->gen, 4); |
966b46c68942
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590
diff
changeset
|
918 mov_irdisp(code, inst->immed, opts->gen.context_reg, offsetof(z80_context, im), SZ_B); |
243
2f069a0b487e
Implement EI, DI and IM in the Z80 core
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242
diff
changeset
|
919 break; |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
920 case Z80_RLC: |
591
966b46c68942
Get Z80 core back into compileable state
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590
diff
changeset
|
921 num_cycles = inst->immed == 0 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
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590
diff
changeset
|
922 cycles(&opts->gen, num_cycles); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
923 if (inst->addr_mode != Z80_UNUSED) { |
591
966b46c68942
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Michael Pavone <pavone@retrodev.com>
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590
diff
changeset
|
924 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
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590
diff
changeset
|
925 translate_z80_reg(inst, &src_op, opts); //For IX/IY variants that also write to a register |
966b46c68942
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Michael Pavone <pavone@retrodev.com>
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590
diff
changeset
|
926 cycles(&opts->gen, 1); |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
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246
diff
changeset
|
927 } else { |
302
3b831fe32c15
More fixes for confusion between Z80_UNUSED and MODE_UNUSED
Mike Pavone <pavone@retrodev.com>
parents:
301
diff
changeset
|
928 src_op.mode = MODE_UNUSED; |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
929 translate_z80_reg(inst, &dst_op, opts); |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
930 } |
591
966b46c68942
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Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
931 rol_ir(code, 1, dst_op.base, SZ_B); |
301
6e15509a1257
Compare src_op.mode with the correct constant in shift/rotate instructions
Mike Pavone <pavone@retrodev.com>
parents:
300
diff
changeset
|
932 if (src_op.mode != MODE_UNUSED) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
933 mov_rr(code, dst_op.base, src_op.base, SZ_B); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
934 } |
591
966b46c68942
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Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
935 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
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590
diff
changeset
|
936 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
247
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
937 //TODO: Implement half-carry flag |
651
103d5cabbe14
Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents:
644
diff
changeset
|
938 if (inst->immed) { |
103d5cabbe14
Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents:
644
diff
changeset
|
939 //rlca does not set these flags |
591
966b46c68942
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Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
940 cmp_ir(code, 0, dst_op.base, SZ_B); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
941 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
942 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
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590
diff
changeset
|
943 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
651
103d5cabbe14
Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents:
644
diff
changeset
|
944 } |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
945 if (inst->addr_mode != Z80_UNUSED) { |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
946 z80_save_result(opts, inst); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
947 if (src_op.mode != MODE_UNUSED) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
948 z80_save_reg(inst, opts); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
949 } |
247
682e505f5757
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Mike Pavone <pavone@retrodev.com>
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246
diff
changeset
|
950 } else { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
951 z80_save_reg(inst, opts); |
247
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Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
952 } |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
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246
diff
changeset
|
953 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
954 case Z80_RL: |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
955 num_cycles = inst->immed == 0 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8); |
966b46c68942
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Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
956 cycles(&opts->gen, num_cycles); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
957 if (inst->addr_mode != Z80_UNUSED) { |
591
966b46c68942
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parents:
590
diff
changeset
|
958 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
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590
diff
changeset
|
959 translate_z80_reg(inst, &src_op, opts); //For IX/IY variants that also write to a register |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
960 cycles(&opts->gen, 1); |
247
682e505f5757
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Mike Pavone <pavone@retrodev.com>
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246
diff
changeset
|
961 } else { |
302
3b831fe32c15
More fixes for confusion between Z80_UNUSED and MODE_UNUSED
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parents:
301
diff
changeset
|
962 src_op.mode = MODE_UNUSED; |
591
966b46c68942
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Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
963 translate_z80_reg(inst, &dst_op, opts); |
247
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246
diff
changeset
|
964 } |
591
966b46c68942
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Michael Pavone <pavone@retrodev.com>
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590
diff
changeset
|
965 bt_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B); |
966b46c68942
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diff
changeset
|
966 rcl_ir(code, 1, dst_op.base, SZ_B); |
301
6e15509a1257
Compare src_op.mode with the correct constant in shift/rotate instructions
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300
diff
changeset
|
967 if (src_op.mode != MODE_UNUSED) { |
591
966b46c68942
Get Z80 core back into compileable state
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590
diff
changeset
|
968 mov_rr(code, dst_op.base, src_op.base, SZ_B); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
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295
diff
changeset
|
969 } |
591
966b46c68942
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diff
changeset
|
970 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
966b46c68942
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diff
changeset
|
971 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
247
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246
diff
changeset
|
972 //TODO: Implement half-carry flag |
651
103d5cabbe14
Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents:
644
diff
changeset
|
973 if (inst->immed) { |
103d5cabbe14
Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents:
644
diff
changeset
|
974 //rla does not set these flags |
591
966b46c68942
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590
diff
changeset
|
975 cmp_ir(code, 0, dst_op.base, SZ_B); |
966b46c68942
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Michael Pavone <pavone@retrodev.com>
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diff
changeset
|
976 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV)); |
966b46c68942
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590
diff
changeset
|
977 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
966b46c68942
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Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
978 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
651
103d5cabbe14
Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents:
644
diff
changeset
|
979 } |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
980 if (inst->addr_mode != Z80_UNUSED) { |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
981 z80_save_result(opts, inst); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
982 if (src_op.mode != MODE_UNUSED) { |
591
966b46c68942
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Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
983 z80_save_reg(inst, opts); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
984 } |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
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246
diff
changeset
|
985 } else { |
591
966b46c68942
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Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
986 z80_save_reg(inst, opts); |
247
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
987 } |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
988 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
989 case Z80_RRC: |
591
966b46c68942
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Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
990 num_cycles = inst->immed == 0 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8); |
966b46c68942
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Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
991 cycles(&opts->gen, num_cycles); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
992 if (inst->addr_mode != Z80_UNUSED) { |
591
966b46c68942
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Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
993 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
994 translate_z80_reg(inst, &src_op, opts); //For IX/IY variants that also write to a register |
966b46c68942
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Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
995 cycles(&opts->gen, 1); |
247
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Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
996 } else { |
302
3b831fe32c15
More fixes for confusion between Z80_UNUSED and MODE_UNUSED
Mike Pavone <pavone@retrodev.com>
parents:
301
diff
changeset
|
997 src_op.mode = MODE_UNUSED; |
591
966b46c68942
Get Z80 core back into compileable state
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parents:
590
diff
changeset
|
998 translate_z80_reg(inst, &dst_op, opts); |
247
682e505f5757
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246
diff
changeset
|
999 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1000 ror_ir(code, 1, dst_op.base, SZ_B); |
301
6e15509a1257
Compare src_op.mode with the correct constant in shift/rotate instructions
Mike Pavone <pavone@retrodev.com>
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300
diff
changeset
|
1001 if (src_op.mode != MODE_UNUSED) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1002 mov_rr(code, dst_op.base, src_op.base, SZ_B); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1003 } |
591
966b46c68942
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parents:
590
diff
changeset
|
1004 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1005 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
247
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1006 //TODO: Implement half-carry flag |
651
103d5cabbe14
Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents:
644
diff
changeset
|
1007 if (inst->immed) { |
103d5cabbe14
Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents:
644
diff
changeset
|
1008 //rrca does not set these flags |
591
966b46c68942
Get Z80 core back into compileable state
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parents:
590
diff
changeset
|
1009 cmp_ir(code, 0, dst_op.base, SZ_B); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1010 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV)); |
966b46c68942
Get Z80 core back into compileable state
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590
diff
changeset
|
1011 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
966b46c68942
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Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1012 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
651
103d5cabbe14
Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents:
644
diff
changeset
|
1013 } |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
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295
diff
changeset
|
1014 if (inst->addr_mode != Z80_UNUSED) { |
593
5ef3fe516da9
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parents:
592
diff
changeset
|
1015 z80_save_result(opts, inst); |
299
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Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
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295
diff
changeset
|
1016 if (src_op.mode != MODE_UNUSED) { |
591
966b46c68942
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590
diff
changeset
|
1017 z80_save_reg(inst, opts); |
299
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295
diff
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|
1018 } |
247
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246
diff
changeset
|
1019 } else { |
591
966b46c68942
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590
diff
changeset
|
1020 z80_save_reg(inst, opts); |
247
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246
diff
changeset
|
1021 } |
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Implement rotation and bit set/reset instructions (untested).
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246
diff
changeset
|
1022 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1023 case Z80_RR: |
591
966b46c68942
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parents:
590
diff
changeset
|
1024 num_cycles = inst->immed == 0 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8); |
966b46c68942
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590
diff
changeset
|
1025 cycles(&opts->gen, num_cycles); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
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295
diff
changeset
|
1026 if (inst->addr_mode != Z80_UNUSED) { |
591
966b46c68942
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590
diff
changeset
|
1027 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY); |
966b46c68942
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parents:
590
diff
changeset
|
1028 translate_z80_reg(inst, &src_op, opts); //For IX/IY variants that also write to a register |
966b46c68942
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parents:
590
diff
changeset
|
1029 cycles(&opts->gen, 1); |
247
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246
diff
changeset
|
1030 } else { |
302
3b831fe32c15
More fixes for confusion between Z80_UNUSED and MODE_UNUSED
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301
diff
changeset
|
1031 src_op.mode = MODE_UNUSED; |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1032 translate_z80_reg(inst, &dst_op, opts); |
247
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246
diff
changeset
|
1033 } |
591
966b46c68942
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parents:
590
diff
changeset
|
1034 bt_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B); |
966b46c68942
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590
diff
changeset
|
1035 rcr_ir(code, 1, dst_op.base, SZ_B); |
301
6e15509a1257
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300
diff
changeset
|
1036 if (src_op.mode != MODE_UNUSED) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1037 mov_rr(code, dst_op.base, src_op.base, SZ_B); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
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295
diff
changeset
|
1038 } |
591
966b46c68942
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590
diff
changeset
|
1039 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
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590
diff
changeset
|
1040 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
247
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Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
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246
diff
changeset
|
1041 //TODO: Implement half-carry flag |
651
103d5cabbe14
Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents:
644
diff
changeset
|
1042 if (inst->immed) { |
103d5cabbe14
Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents:
644
diff
changeset
|
1043 //rra does not set these flags |
591
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diff
changeset
|
1044 cmp_ir(code, 0, dst_op.base, SZ_B); |
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diff
changeset
|
1045 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV)); |
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590
diff
changeset
|
1046 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
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Get Z80 core back into compileable state
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diff
changeset
|
1047 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
651
103d5cabbe14
Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents:
644
diff
changeset
|
1048 } |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1049 if (inst->addr_mode != Z80_UNUSED) { |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
1050 z80_save_result(opts, inst); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
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295
diff
changeset
|
1051 if (src_op.mode != MODE_UNUSED) { |
591
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diff
changeset
|
1052 z80_save_reg(inst, opts); |
299
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Mike Pavone <pavone@retrodev.com>
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diff
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|
1053 } |
247
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|
1054 } else { |
591
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diff
changeset
|
1055 z80_save_reg(inst, opts); |
247
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|
1056 } |
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1057 break; |
275
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diff
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|
1058 case Z80_SLA: |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1059 case Z80_SLL: |
591
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diff
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|
1060 num_cycles = inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8; |
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diff
changeset
|
1061 cycles(&opts->gen, num_cycles); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1062 if (inst->addr_mode != Z80_UNUSED) { |
591
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590
diff
changeset
|
1063 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY); |
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diff
changeset
|
1064 translate_z80_reg(inst, &src_op, opts); //For IX/IY variants that also write to a register |
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diff
changeset
|
1065 cycles(&opts->gen, 1); |
275
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274
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1066 } else { |
302
3b831fe32c15
More fixes for confusion between Z80_UNUSED and MODE_UNUSED
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301
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|
1067 src_op.mode = MODE_UNUSED; |
591
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|
1068 translate_z80_reg(inst, &dst_op, opts); |
275
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1069 } |
591
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changeset
|
1070 shl_ir(code, 1, dst_op.base, SZ_B); |
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diff
changeset
|
1071 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
310
bf440db64086
Implement carry flag for shift instructions. Implement weird behavior for bit 0 of SLL. Fix missing break statement in SRL.
Mike Pavone <pavone@retrodev.com>
parents:
309
diff
changeset
|
1072 if (inst->op == Z80_SLL) { |
591
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diff
changeset
|
1073 or_ir(code, 1, dst_op.base, SZ_B); |
310
bf440db64086
Implement carry flag for shift instructions. Implement weird behavior for bit 0 of SLL. Fix missing break statement in SRL.
Mike Pavone <pavone@retrodev.com>
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309
diff
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|
1074 } |
301
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300
diff
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|
1075 if (src_op.mode != MODE_UNUSED) { |
591
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|
1076 mov_rr(code, dst_op.base, src_op.base, SZ_B); |
299
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|
1077 } |
591
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changeset
|
1078 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
275
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changeset
|
1079 //TODO: Implement half-carry flag |
591
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|
1080 cmp_ir(code, 0, dst_op.base, SZ_B); |
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changeset
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1081 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV)); |
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|
1082 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
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changeset
|
1083 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1084 if (inst->addr_mode != Z80_UNUSED) { |
593
5ef3fe516da9
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parents:
592
diff
changeset
|
1085 z80_save_result(opts, inst); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1086 if (src_op.mode != MODE_UNUSED) { |
591
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diff
changeset
|
1087 z80_save_reg(inst, opts); |
299
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Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
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295
diff
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|
1088 } |
275
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|
1089 } else { |
591
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changeset
|
1090 z80_save_reg(inst, opts); |
275
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274
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|
1091 } |
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274
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changeset
|
1092 break; |
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changeset
|
1093 case Z80_SRA: |
591
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590
diff
changeset
|
1094 num_cycles = inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8; |
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diff
changeset
|
1095 cycles(&opts->gen, num_cycles); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1096 if (inst->addr_mode != Z80_UNUSED) { |
591
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parents:
590
diff
changeset
|
1097 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY); |
966b46c68942
Get Z80 core back into compileable state
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590
diff
changeset
|
1098 translate_z80_reg(inst, &src_op, opts); //For IX/IY variants that also write to a register |
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Get Z80 core back into compileable state
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diff
changeset
|
1099 cycles(&opts->gen, 1); |
275
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274
diff
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|
1100 } else { |
302
3b831fe32c15
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301
diff
changeset
|
1101 src_op.mode = MODE_UNUSED; |
591
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diff
changeset
|
1102 translate_z80_reg(inst, &dst_op, opts); |
275
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|
1103 } |
591
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changeset
|
1104 sar_ir(code, 1, dst_op.base, SZ_B); |
301
6e15509a1257
Compare src_op.mode with the correct constant in shift/rotate instructions
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300
diff
changeset
|
1105 if (src_op.mode != MODE_UNUSED) { |
591
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diff
changeset
|
1106 mov_rr(code, dst_op.base, src_op.base, SZ_B); |
299
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295
diff
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|
1107 } |
591
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diff
changeset
|
1108 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
966b46c68942
Get Z80 core back into compileable state
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diff
changeset
|
1109 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
275
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changeset
|
1110 //TODO: Implement half-carry flag |
591
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parents:
590
diff
changeset
|
1111 cmp_ir(code, 0, dst_op.base, SZ_B); |
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Get Z80 core back into compileable state
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590
diff
changeset
|
1112 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV)); |
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diff
changeset
|
1113 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
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diff
changeset
|
1114 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
299
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Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
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295
diff
changeset
|
1115 if (inst->addr_mode != Z80_UNUSED) { |
593
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diff
changeset
|
1116 z80_save_result(opts, inst); |
299
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295
diff
changeset
|
1117 if (src_op.mode != MODE_UNUSED) { |
591
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diff
changeset
|
1118 z80_save_reg(inst, opts); |
299
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|
1119 } |
275
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|
1120 } else { |
591
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diff
changeset
|
1121 z80_save_reg(inst, opts); |
275
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|
1122 } |
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|
1123 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1124 case Z80_SRL: |
591
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diff
changeset
|
1125 num_cycles = inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8; |
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diff
changeset
|
1126 cycles(&opts->gen, num_cycles); |
299
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295
diff
changeset
|
1127 if (inst->addr_mode != Z80_UNUSED) { |
591
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diff
changeset
|
1128 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY); |
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diff
changeset
|
1129 translate_z80_reg(inst, &src_op, opts); //For IX/IY variants that also write to a register |
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diff
changeset
|
1130 cycles(&opts->gen, 1); |
275
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|
1131 } else { |
302
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diff
changeset
|
1132 src_op.mode = MODE_UNUSED; |
591
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diff
changeset
|
1133 translate_z80_reg(inst, &dst_op, opts); |
275
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|
1134 } |
591
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diff
changeset
|
1135 shr_ir(code, 1, dst_op.base, SZ_B); |
301
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300
diff
changeset
|
1136 if (src_op.mode != MODE_UNUSED) { |
591
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diff
changeset
|
1137 mov_rr(code, dst_op.base, src_op.base, SZ_B); |
299
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1138 } |
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1139 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
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1140 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
275
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1141 //TODO: Implement half-carry flag |
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1142 cmp_ir(code, 0, dst_op.base, SZ_B); |
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1143 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV)); |
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1144 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
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1145 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
299
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1146 if (inst->addr_mode != Z80_UNUSED) { |
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1147 z80_save_result(opts, inst); |
299
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1148 if (src_op.mode != MODE_UNUSED) { |
591
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1149 z80_save_reg(inst, opts); |
299
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1150 } |
275
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1151 } else { |
591
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1152 z80_save_reg(inst, opts); |
275
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1153 } |
310
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Implement carry flag for shift instructions. Implement weird behavior for bit 0 of SLL. Fix missing break statement in SRL.
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1154 break; |
286 | 1155 case Z80_RLD: |
591
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1156 cycles(&opts->gen, 8); |
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1157 mov_rr(code, opts->regs[Z80_HL], opts->gen.scratch1, SZ_W); |
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1158 call(code, opts->read_8); |
286 | 1159 //Before: (HL) = 0x12, A = 0x34 |
1160 //After: (HL) = 0x24, A = 0x31 | |
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1161 mov_rr(code, opts->regs[Z80_A], opts->gen.scratch2, SZ_B); |
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1162 shl_ir(code, 4, opts->gen.scratch1, SZ_W); |
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1163 and_ir(code, 0xF, opts->gen.scratch2, SZ_W); |
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1164 and_ir(code, 0xFFF, opts->gen.scratch1, SZ_W); |
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1165 and_ir(code, 0xF0, opts->regs[Z80_A], SZ_B); |
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1166 or_rr(code, opts->gen.scratch2, opts->gen.scratch1, SZ_W); |
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1167 //opts->gen.scratch1 = 0x0124 |
591
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1168 ror_ir(code, 8, opts->gen.scratch1, SZ_W); |
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1169 cycles(&opts->gen, 4); |
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1170 or_rr(code, opts->gen.scratch1, opts->regs[Z80_A], SZ_B); |
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1171 //set flags |
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1172 //TODO: Implement half-carry flag |
591
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1173 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
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1174 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV)); |
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1175 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
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1176 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
505
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The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
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1177 |
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1178 mov_rr(code, opts->regs[Z80_HL], opts->gen.scratch2, SZ_W); |
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1179 ror_ir(code, 8, opts->gen.scratch1, SZ_W); |
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1180 call(code, opts->write_8); |
286 | 1181 break; |
287
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1182 case Z80_RRD: |
591
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1183 cycles(&opts->gen, 8); |
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1184 mov_rr(code, opts->regs[Z80_HL], opts->gen.scratch1, SZ_W); |
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1185 call(code, opts->read_8); |
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1186 //Before: (HL) = 0x12, A = 0x34 |
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1187 //After: (HL) = 0x41, A = 0x32 |
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1188 movzx_rr(code, opts->regs[Z80_A], opts->gen.scratch2, SZ_B, SZ_W); |
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1189 ror_ir(code, 4, opts->gen.scratch1, SZ_W); |
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1190 shl_ir(code, 4, opts->gen.scratch2, SZ_W); |
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1191 and_ir(code, 0xF00F, opts->gen.scratch1, SZ_W); |
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1192 and_ir(code, 0xF0, opts->regs[Z80_A], SZ_B); |
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1193 //opts->gen.scratch1 = 0x2001 |
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1194 //opts->gen.scratch2 = 0x0040 |
591
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1195 or_rr(code, opts->gen.scratch2, opts->gen.scratch1, SZ_W); |
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1196 //opts->gen.scratch1 = 0x2041 |
591
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1197 ror_ir(code, 8, opts->gen.scratch1, SZ_W); |
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1198 cycles(&opts->gen, 4); |
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1199 shr_ir(code, 4, opts->gen.scratch1, SZ_B); |
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1200 or_rr(code, opts->gen.scratch1, opts->regs[Z80_A], SZ_B); |
287
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1201 //set flags |
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1202 //TODO: Implement half-carry flag |
591
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1203 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
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1204 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV)); |
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1205 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
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1206 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
505
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The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
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1207 |
591
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1208 mov_rr(code, opts->regs[Z80_HL], opts->gen.scratch2, SZ_W); |
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1209 ror_ir(code, 8, opts->gen.scratch1, SZ_W); |
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1210 call(code, opts->write_8); |
287
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1211 break; |
308
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1212 case Z80_BIT: { |
591
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1213 num_cycles = (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) ? 8 : 16; |
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1214 cycles(&opts->gen, num_cycles); |
308
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1215 uint8_t bit; |
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1216 if ((inst->addr_mode & 0x1F) == Z80_REG && opts->regs[inst->ea_reg] >= AH && opts->regs[inst->ea_reg] <= BH) { |
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1217 src_op.base = opts->regs[z80_word_reg(inst->ea_reg)]; |
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1218 size = SZ_W; |
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1219 bit = inst->immed + 8; |
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1220 } else { |
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1221 size = SZ_B; |
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1222 bit = inst->immed; |
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1223 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY); |
308
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1224 } |
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1225 if (inst->addr_mode != Z80_REG) { |
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1226 //Reads normally take 3 cycles, but the read at the end of a bit instruction takes 4 |
591
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1227 cycles(&opts->gen, 1); |
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1228 } |
591
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1229 bt_ir(code, bit, src_op.base, size); |
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1230 setcc_rdisp(code, CC_NC, opts->gen.context_reg, zf_off(ZF_Z)); |
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1231 setcc_rdisp(code, CC_NC, opts->gen.context_reg, zf_off(ZF_PV)); |
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1232 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
307
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1233 if (inst->immed == 7) { |
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1234 cmp_ir(code, 0, src_op.base, size); |
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1235 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
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1236 } else { |
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1237 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_S), SZ_B); |
307
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1238 } |
239
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1239 break; |
308
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1240 } |
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changeset
|
1241 case Z80_SET: { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1242 num_cycles = (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) ? 8 : 16; |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1243 cycles(&opts->gen, num_cycles); |
308
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1244 uint8_t bit; |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1245 if ((inst->addr_mode & 0x1F) == Z80_REG && opts->regs[inst->ea_reg] >= AH && opts->regs[inst->ea_reg] <= BH) { |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1246 src_op.base = opts->regs[z80_word_reg(inst->ea_reg)]; |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1247 size = SZ_W; |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1248 bit = inst->immed + 8; |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1249 } else { |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1250 size = SZ_B; |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1251 bit = inst->immed; |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1252 translate_z80_ea(inst, &src_op, opts, READ, MODIFY); |
308
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1253 } |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1254 if (inst->reg != Z80_USE_IMMED) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1255 translate_z80_reg(inst, &dst_op, opts); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1256 } |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1257 if (inst->addr_mode != Z80_REG) { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1258 //Reads normally take 3 cycles, but the read in the middle of a set instruction takes 4 |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1259 cycles(&opts->gen, 1); |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
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246
diff
changeset
|
1260 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1261 bts_ir(code, bit, src_op.base, size); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1262 if (inst->reg != Z80_USE_IMMED) { |
308
e0e81551fd7e
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1263 if (size == SZ_W) { |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1264 if (dst_op.base >= R8) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1265 ror_ir(code, 8, src_op.base, SZ_W); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1266 mov_rr(code, opts->regs[z80_low_reg(inst->ea_reg)], dst_op.base, SZ_B); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
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590
diff
changeset
|
1267 ror_ir(code, 8, src_op.base, SZ_W); |
308
e0e81551fd7e
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Mike Pavone <pavone@retrodev.com>
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307
diff
changeset
|
1268 } else { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1269 mov_rr(code, opts->regs[inst->ea_reg], dst_op.base, SZ_B); |
505
b7b7a1cab44a
The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1270 } |
308
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Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
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307
diff
changeset
|
1271 } else { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1272 mov_rr(code, src_op.base, dst_op.base, SZ_B); |
308
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1273 } |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1274 } |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1275 if ((inst->addr_mode & 0x1F) != Z80_REG) { |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
1276 z80_save_result(opts, inst); |
308
e0e81551fd7e
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Mike Pavone <pavone@retrodev.com>
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307
diff
changeset
|
1277 if (inst->reg != Z80_USE_IMMED) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1278 z80_save_reg(inst, opts); |
308
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Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1279 } |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
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307
diff
changeset
|
1280 } |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1281 break; |
e0e81551fd7e
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1282 } |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1283 case Z80_RES: { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1284 num_cycles = (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) ? 8 : 16; |
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Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1285 cycles(&opts->gen, num_cycles); |
308
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parents:
307
diff
changeset
|
1286 uint8_t bit; |
e0e81551fd7e
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parents:
307
diff
changeset
|
1287 if ((inst->addr_mode & 0x1F) == Z80_REG && opts->regs[inst->ea_reg] >= AH && opts->regs[inst->ea_reg] <= BH) { |
e0e81551fd7e
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parents:
307
diff
changeset
|
1288 src_op.base = opts->regs[z80_word_reg(inst->ea_reg)]; |
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parents:
307
diff
changeset
|
1289 size = SZ_W; |
e0e81551fd7e
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parents:
307
diff
changeset
|
1290 bit = inst->immed + 8; |
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1291 } else { |
e0e81551fd7e
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parents:
307
diff
changeset
|
1292 size = SZ_B; |
e0e81551fd7e
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parents:
307
diff
changeset
|
1293 bit = inst->immed; |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1294 translate_z80_ea(inst, &src_op, opts, READ, MODIFY); |
308
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parents:
307
diff
changeset
|
1295 } |
e0e81551fd7e
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parents:
307
diff
changeset
|
1296 if (inst->reg != Z80_USE_IMMED) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1297 translate_z80_reg(inst, &dst_op, opts); |
308
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parents:
307
diff
changeset
|
1298 } |
e0e81551fd7e
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parents:
307
diff
changeset
|
1299 if (inst->addr_mode != Z80_REG) { |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
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parents:
307
diff
changeset
|
1300 //Reads normally take 3 cycles, but the read in the middle of a set instruction takes 4 |
591
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Get Z80 core back into compileable state
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parents:
590
diff
changeset
|
1301 cycles(&opts->gen, 1); |
308
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parents:
307
diff
changeset
|
1302 } |
591
966b46c68942
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Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1303 btr_ir(code, bit, src_op.base, size); |
308
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parents:
307
diff
changeset
|
1304 if (inst->reg != Z80_USE_IMMED) { |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
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parents:
307
diff
changeset
|
1305 if (size == SZ_W) { |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
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parents:
307
diff
changeset
|
1306 if (dst_op.base >= R8) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1307 ror_ir(code, 8, src_op.base, SZ_W); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1308 mov_rr(code, opts->regs[z80_low_reg(inst->ea_reg)], dst_op.base, SZ_B); |
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parents:
590
diff
changeset
|
1309 ror_ir(code, 8, src_op.base, SZ_W); |
308
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307
diff
changeset
|
1310 } else { |
591
966b46c68942
Get Z80 core back into compileable state
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parents:
590
diff
changeset
|
1311 mov_rr(code, opts->regs[inst->ea_reg], dst_op.base, SZ_B); |
505
b7b7a1cab44a
The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1312 } |
308
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307
diff
changeset
|
1313 } else { |
591
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parents:
590
diff
changeset
|
1314 mov_rr(code, src_op.base, dst_op.base, SZ_B); |
308
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diff
changeset
|
1315 } |
299
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Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
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295
diff
changeset
|
1316 } |
247
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246
diff
changeset
|
1317 if (inst->addr_mode != Z80_REG) { |
593
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parents:
592
diff
changeset
|
1318 z80_save_result(opts, inst); |
299
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parents:
295
diff
changeset
|
1319 if (inst->reg != Z80_USE_IMMED) { |
591
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590
diff
changeset
|
1320 z80_save_reg(inst, opts); |
299
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diff
changeset
|
1321 } |
247
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diff
changeset
|
1322 } |
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diff
changeset
|
1323 break; |
308
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diff
changeset
|
1324 } |
236
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diff
changeset
|
1325 case Z80_JP: { |
591
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parents:
590
diff
changeset
|
1326 num_cycles = 4; |
506
a3b48a57e847
Fix timing of certain ld and jp instructions in the Z80 core
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parents:
505
diff
changeset
|
1327 if (inst->addr_mode != Z80_REG_INDIRECT) { |
591
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parents:
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diff
changeset
|
1328 num_cycles += 6; |
236
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diff
changeset
|
1329 } else if(inst->ea_reg == Z80_IX || inst->ea_reg == Z80_IY) { |
591
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parents:
590
diff
changeset
|
1330 num_cycles += 4; |
236
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diff
changeset
|
1331 } |
591
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parents:
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diff
changeset
|
1332 cycles(&opts->gen, num_cycles); |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1333 if (inst->addr_mode != Z80_REG_INDIRECT) { |
591
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parents:
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diff
changeset
|
1334 code_ptr call_dst = z80_get_native_address(context, inst->immed); |
236
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changeset
|
1335 if (!call_dst) { |
591
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diff
changeset
|
1336 opts->gen.deferred = defer_address(opts->gen.deferred, inst->immed, code->cur + 1); |
236
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diff
changeset
|
1337 //fake address to force large displacement |
601
f0061e3d2ad9
Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor
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parents:
598
diff
changeset
|
1338 call_dst = code->cur + 256; |
236
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diff
changeset
|
1339 } |
591
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parents:
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diff
changeset
|
1340 jmp(code, call_dst); |
236
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diff
changeset
|
1341 } else { |
239
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
1342 if (inst->addr_mode == Z80_REG_INDIRECT) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1343 mov_rr(code, opts->regs[inst->ea_reg], opts->gen.scratch1, SZ_W); |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1344 } else { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1345 mov_ir(code, inst->immed, opts->gen.scratch1, SZ_W); |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1346 } |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
1347 call(code, opts->native_addr); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1348 jmp_r(code, opts->gen.scratch1); |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1349 } |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1350 break; |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1351 } |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1352 case Z80_JPCC: { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1353 cycles(&opts->gen, 7);//T States: 4,3 |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1354 uint8_t cond = CC_Z; |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1355 switch (inst->reg) |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1356 { |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1357 case Z80_CC_NZ: |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1358 cond = CC_NZ; |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1359 case Z80_CC_Z: |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1360 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_Z), SZ_B); |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1361 break; |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1362 case Z80_CC_NC: |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1363 cond = CC_NZ; |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1364 case Z80_CC_C: |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1365 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B); |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1366 break; |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1367 case Z80_CC_PO: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1368 cond = CC_NZ; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1369 case Z80_CC_PE: |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1370 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_PV), SZ_B); |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1371 break; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1372 case Z80_CC_P: |
367
f20562f2a570
Fix P condition in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
366
diff
changeset
|
1373 cond = CC_NZ; |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1374 case Z80_CC_M: |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1375 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_S), SZ_B); |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1376 break; |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1377 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1378 uint8_t *no_jump_off = code->cur+1; |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1379 jcc(code, cond, code->cur+2); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1380 cycles(&opts->gen, 5);//T States: 5 |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1381 uint16_t dest_addr = inst->immed; |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1382 code_ptr call_dst = z80_get_native_address(context, dest_addr); |
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1383 if (!call_dst) { |
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1384 opts->gen.deferred = defer_address(opts->gen.deferred, dest_addr, code->cur + 1); |
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1385 //fake address to force large displacement |
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1386 call_dst = code->cur + 256; |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1387 } |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1388 jmp(code, call_dst); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1389 *no_jump_off = code->cur - (no_jump_off+1); |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1390 break; |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1391 } |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1392 case Z80_JR: { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1393 cycles(&opts->gen, 12);//T States: 4,3,5 |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1394 uint16_t dest_addr = address + inst->immed + 2; |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1395 code_ptr call_dst = z80_get_native_address(context, dest_addr); |
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1396 if (!call_dst) { |
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1397 opts->gen.deferred = defer_address(opts->gen.deferred, dest_addr, code->cur + 1); |
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1398 //fake address to force large displacement |
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1399 call_dst = code->cur + 256; |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1400 } |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1401 jmp(code, call_dst); |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1402 break; |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1403 } |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1404 case Z80_JRCC: { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1405 cycles(&opts->gen, 7);//T States: 4,3 |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1406 uint8_t cond = CC_Z; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1407 switch (inst->reg) |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1408 { |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1409 case Z80_CC_NZ: |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1410 cond = CC_NZ; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1411 case Z80_CC_Z: |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1412 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_Z), SZ_B); |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1413 break; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1414 case Z80_CC_NC: |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1415 cond = CC_NZ; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1416 case Z80_CC_C: |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1417 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B); |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1418 break; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1419 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1420 uint8_t *no_jump_off = code->cur+1; |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1421 jcc(code, cond, code->cur+2); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1422 cycles(&opts->gen, 5);//T States: 5 |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1423 uint16_t dest_addr = address + inst->immed + 2; |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1424 code_ptr call_dst = z80_get_native_address(context, dest_addr); |
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1425 if (!call_dst) { |
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1426 opts->gen.deferred = defer_address(opts->gen.deferred, dest_addr, code->cur + 1); |
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1427 //fake address to force large displacement |
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1428 call_dst = code->cur + 256; |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1429 } |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1430 jmp(code, call_dst); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1431 *no_jump_off = code->cur - (no_jump_off+1); |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1432 break; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1433 } |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1434 case Z80_DJNZ: { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1435 cycles(&opts->gen, 8);//T States: 5,3 |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1436 sub_ir(code, 1, opts->regs[Z80_B], SZ_B); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1437 uint8_t *no_jump_off = code->cur+1; |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1438 jcc(code, CC_Z, code->cur+2); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1439 cycles(&opts->gen, 5);//T States: 5 |
239
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
1440 uint16_t dest_addr = address + inst->immed + 2; |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1441 code_ptr call_dst = z80_get_native_address(context, dest_addr); |
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1442 if (!call_dst) { |
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1443 opts->gen.deferred = defer_address(opts->gen.deferred, dest_addr, code->cur + 1); |
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1444 //fake address to force large displacement |
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1445 call_dst = code->cur + 256; |
239
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
1446 } |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1447 jmp(code, call_dst); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1448 *no_jump_off = code->cur - (no_jump_off+1); |
239
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
1449 break; |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1450 } |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1451 case Z80_CALL: { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1452 cycles(&opts->gen, 11);//T States: 4,3,4 |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1453 sub_ir(code, 2, opts->regs[Z80_SP], SZ_W); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1454 mov_ir(code, address + 3, opts->gen.scratch1, SZ_W); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1455 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch2, SZ_W); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
1456 call(code, opts->write_16_highfirst);//T States: 3, 3 |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1457 code_ptr call_dst = z80_get_native_address(context, inst->immed); |
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1458 if (!call_dst) { |
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1459 opts->gen.deferred = defer_address(opts->gen.deferred, inst->immed, code->cur + 1); |
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1460 //fake address to force large displacement |
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1461 call_dst = code->cur + 256; |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1462 } |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1463 jmp(code, call_dst); |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1464 break; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1465 } |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1466 case Z80_CALLCC: { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1467 cycles(&opts->gen, 10);//T States: 4,3,3 (false case) |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1468 uint8_t cond = CC_Z; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1469 switch (inst->reg) |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1470 { |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1471 case Z80_CC_NZ: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1472 cond = CC_NZ; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1473 case Z80_CC_Z: |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1474 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_Z), SZ_B); |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1475 break; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1476 case Z80_CC_NC: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1477 cond = CC_NZ; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1478 case Z80_CC_C: |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1479 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B); |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1480 break; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1481 case Z80_CC_PO: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1482 cond = CC_NZ; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1483 case Z80_CC_PE: |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1484 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_PV), SZ_B); |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1485 break; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1486 case Z80_CC_P: |
367
f20562f2a570
Fix P condition in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
366
diff
changeset
|
1487 cond = CC_NZ; |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1488 case Z80_CC_M: |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1489 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_S), SZ_B); |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1490 break; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1491 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1492 uint8_t *no_call_off = code->cur+1; |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1493 jcc(code, cond, code->cur+2); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1494 cycles(&opts->gen, 1);//Last of the above T states takes an extra cycle in the true case |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1495 sub_ir(code, 2, opts->regs[Z80_SP], SZ_W); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1496 mov_ir(code, address + 3, opts->gen.scratch1, SZ_W); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1497 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch2, SZ_W); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
1498 call(code, opts->write_16_highfirst);//T States: 3, 3 |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1499 code_ptr call_dst = z80_get_native_address(context, inst->immed); |
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1500 if (!call_dst) { |
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1501 opts->gen.deferred = defer_address(opts->gen.deferred, inst->immed, code->cur + 1); |
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1502 //fake address to force large displacement |
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1503 call_dst = code->cur + 256; |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1504 } |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1505 jmp(code, call_dst); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1506 *no_call_off = code->cur - (no_call_off+1); |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1507 break; |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1508 } |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1509 case Z80_RET: |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1510 cycles(&opts->gen, 4);//T States: 4 |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1511 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
1512 call(code, opts->read_16);//T STates: 3, 3 |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1513 add_ir(code, 2, opts->regs[Z80_SP], SZ_W); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
1514 call(code, opts->native_addr); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1515 jmp_r(code, opts->gen.scratch1); |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1516 break; |
246
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1517 case Z80_RETCC: { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1518 cycles(&opts->gen, 5);//T States: 5 |
246
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1519 uint8_t cond = CC_Z; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1520 switch (inst->reg) |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1521 { |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1522 case Z80_CC_NZ: |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1523 cond = CC_NZ; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1524 case Z80_CC_Z: |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1525 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_Z), SZ_B); |
246
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1526 break; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1527 case Z80_CC_NC: |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1528 cond = CC_NZ; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1529 case Z80_CC_C: |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1530 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B); |
246
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1531 break; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1532 case Z80_CC_PO: |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1533 cond = CC_NZ; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1534 case Z80_CC_PE: |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1535 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_PV), SZ_B); |
246
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1536 break; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1537 case Z80_CC_P: |
367
f20562f2a570
Fix P condition in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
366
diff
changeset
|
1538 cond = CC_NZ; |
246
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1539 case Z80_CC_M: |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1540 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_S), SZ_B); |
246
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1541 break; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1542 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1543 uint8_t *no_call_off = code->cur+1; |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1544 jcc(code, cond, code->cur+2); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1545 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
1546 call(code, opts->read_16);//T STates: 3, 3 |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1547 add_ir(code, 2, opts->regs[Z80_SP], SZ_W); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
1548 call(code, opts->native_addr); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1549 jmp_r(code, opts->gen.scratch1); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1550 *no_call_off = code->cur - (no_call_off+1); |
246
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1551 break; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1552 } |
283
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1553 case Z80_RETI: |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1554 //For some systems, this may need a callback for signalling interrupt routine completion |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1555 cycles(&opts->gen, 8);//T States: 4, 4 |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1556 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
1557 call(code, opts->read_16);//T STates: 3, 3 |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1558 add_ir(code, 2, opts->regs[Z80_SP], SZ_W); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
1559 call(code, opts->native_addr); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1560 jmp_r(code, opts->gen.scratch1); |
283
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1561 break; |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1562 case Z80_RETN: |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1563 cycles(&opts->gen, 8);//T States: 4, 4 |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1564 mov_rdispr(code, opts->gen.context_reg, offsetof(z80_context, iff2), opts->gen.scratch2, SZ_B); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1565 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1566 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, offsetof(z80_context, iff1), SZ_B); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
1567 call(code, opts->read_16);//T STates: 3, 3 |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1568 add_ir(code, 2, opts->regs[Z80_SP], SZ_W); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
1569 call(code, opts->native_addr); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1570 jmp_r(code, opts->gen.scratch1); |
283
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1571 break; |
241
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1572 case Z80_RST: { |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1573 //RST is basically CALL to an address in page 0 |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1574 cycles(&opts->gen, 5);//T States: 5 |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1575 sub_ir(code, 2, opts->regs[Z80_SP], SZ_W); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1576 mov_ir(code, address + 1, opts->gen.scratch1, SZ_W); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1577 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch2, SZ_W); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
1578 call(code, opts->write_16_highfirst);//T States: 3, 3 |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1579 code_ptr call_dst = z80_get_native_address(context, inst->immed); |
241
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1580 if (!call_dst) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1581 opts->gen.deferred = defer_address(opts->gen.deferred, inst->immed, code->cur + 1); |
241
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1582 //fake address to force large displacement |
601
f0061e3d2ad9
Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor
Michael Pavone <pavone@retrodev.com>
parents:
598
diff
changeset
|
1583 call_dst = code->cur + 256; |
241
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1584 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1585 jmp(code, call_dst); |
241
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1586 break; |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1587 } |
284
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1588 case Z80_IN: |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1589 cycles(&opts->gen, inst->reg == Z80_A ? 7 : 8);//T States: 4 3/4 |
284
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1590 if (inst->addr_mode == Z80_IMMED_INDIRECT) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1591 mov_ir(code, inst->immed, opts->gen.scratch1, SZ_B); |
284
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1592 } else { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1593 mov_rr(code, opts->regs[Z80_C], opts->gen.scratch1, SZ_B); |
284
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1594 } |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
1595 call(code, opts->read_io); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1596 translate_z80_reg(inst, &dst_op, opts); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1597 mov_rr(code, opts->gen.scratch1, dst_op.base, SZ_B); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1598 z80_save_reg(inst, opts); |
284
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1599 break; |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1600 /*case Z80_INI: |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1601 case Z80_INIR: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1602 case Z80_IND: |
284
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1603 case Z80_INDR:*/ |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1604 case Z80_OUT: |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1605 cycles(&opts->gen, inst->reg == Z80_A ? 7 : 8);//T States: 4 3/4 |
284
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1606 if ((inst->addr_mode & 0x1F) == Z80_IMMED_INDIRECT) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1607 mov_ir(code, inst->immed, opts->gen.scratch2, SZ_B); |
284
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1608 } else { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1609 mov_rr(code, opts->regs[Z80_C], opts->gen.scratch2, SZ_B); |
284
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1610 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1611 translate_z80_reg(inst, &src_op, opts); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1612 mov_rr(code, dst_op.base, opts->gen.scratch1, SZ_B); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
1613 call(code, opts->write_io); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1614 z80_save_reg(inst, opts); |
284
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1615 break; |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1616 /*case Z80_OUTI: |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1617 case Z80_OTIR: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1618 case Z80_OUTD: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1619 case Z80_OTDR:*/ |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1620 default: { |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1621 char disbuf[80]; |
314
54c0e5f22198
Show absolute addresses for JR, JRCC and DJNZ in Z80 disassembler
Mike Pavone <pavone@retrodev.com>
parents:
313
diff
changeset
|
1622 z80_disasm(inst, disbuf, address); |
424
7e8e179116af
Add support for loading GST format savestates
Mike Pavone <pavone@retrodev.com>
parents:
420
diff
changeset
|
1623 fprintf(stderr, "unimplemented instruction: %s at %X\n", disbuf, address); |
259
d9417261366f
Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called.
Mike Pavone <pavone@retrodev.com>
parents:
257
diff
changeset
|
1624 FILE * f = fopen("zram.bin", "wb"); |
d9417261366f
Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called.
Mike Pavone <pavone@retrodev.com>
parents:
257
diff
changeset
|
1625 fwrite(context->mem_pointers[0], 1, 8 * 1024, f); |
d9417261366f
Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called.
Mike Pavone <pavone@retrodev.com>
parents:
257
diff
changeset
|
1626 fclose(f); |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1627 exit(1); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1628 } |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1629 } |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1630 } |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1631 |
627
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1632 uint8_t * z80_interp_handler(uint8_t opcode, z80_context * context) |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1633 { |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1634 if (!context->interp_code[opcode]) { |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1635 if (opcode == 0xCB || (opcode >= 0xDD && opcode & 0xF == 0xD)) { |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1636 fprintf(stderr, "Encountered prefix byte %X at address %X. Z80 interpeter doesn't support those yet.", opcode, context->pc); |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1637 exit(1); |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1638 } |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1639 uint8_t codebuf[8]; |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1640 memset(codebuf, 0, sizeof(codebuf)); |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1641 codebuf[0] = opcode; |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1642 z80inst inst; |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1643 uint8_t * after = z80_decode(codebuf, &inst); |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1644 if (after - codebuf > 1) { |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1645 fprintf(stderr, "Encountered multi-byte Z80 instruction at %X. Z80 interpeter doesn't support those yet.", context->pc); |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1646 exit(1); |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1647 } |
652 | 1648 |
1649 z80_options * opts = context->options; | |
1650 code_info *code = &opts->gen.code; | |
1651 check_alloc_code(code, ZMAX_NATIVE_SIZE); | |
1652 context->interp_code[opcode] = code->cur; | |
1653 translate_z80inst(&inst, context, 0, 1); | |
1654 mov_rdispr(code, opts->gen.context_reg, offsetof(z80_context, pc), opts->gen.scratch1, SZ_W); | |
1655 add_ir(code, after - codebuf, opts->gen.scratch1, SZ_W); | |
1656 call(code, opts->native_addr); | |
1657 jmp_r(code, opts->gen.scratch1); | |
627
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1658 } |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1659 return context->interp_code[opcode]; |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1660 } |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1661 |
652 | 1662 code_info z80_make_interp_stub(z80_context * context, uint16_t address) |
627
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1663 { |
652 | 1664 z80_options *opts = context->options; |
1665 code_info * code = &opts->gen.code; | |
1666 check_alloc_code(code, 32); | |
1667 code_info stub = {code->cur, NULL}; | |
627
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1668 //TODO: make this play well with the breakpoint code |
652 | 1669 mov_ir(code, address, opts->gen.scratch1, SZ_W); |
1670 call(code, opts->read_8); | |
627
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1671 //normal opcode fetch is already factored into instruction timing |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1672 //back out the base 3 cycles from a read here |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1673 //not quite perfect, but it will have to do for now |
652 | 1674 cycles(&opts->gen, -3); |
1675 check_cycles_int(&opts->gen, address); | |
1676 call(code, opts->gen.save_context); | |
1677 mov_irdisp(code, address, opts->gen.context_reg, offsetof(z80_context, pc), SZ_W); | |
1678 push_r(code, opts->gen.context_reg); | |
657
92ce5ea5ffc9
Use call_args and call_args_abi in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
653
diff
changeset
|
1679 call_args(code, (code_ptr)z80_interp_handler, 2, opts->gen.scratch1, opts->gen.scratch2); |
652 | 1680 mov_rr(code, RAX, opts->gen.scratch1, SZ_Q); |
1681 pop_r(code, opts->gen.context_reg); | |
1682 call(code, opts->gen.load_context); | |
1683 jmp_r(code, opts->gen.scratch1); | |
1684 stub.last = code->cur; | |
1685 return stub; | |
627
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1686 } |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1687 |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1688 |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1689 uint8_t * z80_get_native_address(z80_context * context, uint32_t address) |
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Get Z80 core working for simple programs
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1690 { |
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|
1691 native_map_slot *map; |
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|
1692 if (address < 0x4000) { |
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|
1693 address &= 0x1FFF; |
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|
1694 map = context->static_code_map; |
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|
1695 } else { |
627
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Added some preliminary support for interpreting Z80 code from non-RAM addresses
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parents:
626
diff
changeset
|
1696 address -= 0x4000; |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
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626
diff
changeset
|
1697 map = context->banked_code_map; |
235
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|
1698 } |
268
6c2d7e003a55
Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
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267
diff
changeset
|
1699 if (!map->base || !map->offsets || map->offsets[address] == INVALID_OFFSET || map->offsets[address] == EXTENSION_WORD) { |
313
a13329645ea3
Fix terminal instruction detection in disassembler
Mike Pavone <pavone@retrodev.com>
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312
diff
changeset
|
1700 //dprintf("z80_get_native_address: %X NULL\n", address); |
235
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Get Z80 core working for simple programs
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|
1701 return NULL; |
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Get Z80 core working for simple programs
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diff
changeset
|
1702 } |
313
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Fix terminal instruction detection in disassembler
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|
1703 //dprintf("z80_get_native_address: %X %p\n", address, map->base + map->offsets[address]); |
235
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|
1704 return map->base + map->offsets[address]; |
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Get Z80 core working for simple programs
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diff
changeset
|
1705 } |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1706 |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
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diff
changeset
|
1707 uint8_t z80_get_native_inst_size(z80_options * opts, uint32_t address) |
235
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Get Z80 core working for simple programs
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|
1708 { |
627
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Added some preliminary support for interpreting Z80 code from non-RAM addresses
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|
1709 //TODO: Fix for addresses >= 0x4000 |
252
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Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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diff
changeset
|
1710 if (address >= 0x4000) { |
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Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
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diff
changeset
|
1711 return 0; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
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diff
changeset
|
1712 } |
591
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Get Z80 core back into compileable state
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|
1713 return opts->gen.ram_inst_sizes[0][address & 0x1FFF]; |
252
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Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
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diff
changeset
|
1714 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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changeset
|
1715 |
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Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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changeset
|
1716 void z80_map_native_address(z80_context * context, uint32_t address, uint8_t * native_address, uint8_t size, uint8_t native_size) |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
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|
1717 { |
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Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
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changeset
|
1718 uint32_t orig_address = address; |
235
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Get Z80 core working for simple programs
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|
1719 native_map_slot *map; |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
1720 z80_options * opts = context->options; |
235
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Get Z80 core working for simple programs
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|
1721 if (address < 0x4000) { |
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Get Z80 core working for simple programs
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|
1722 address &= 0x1FFF; |
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Get Z80 core working for simple programs
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changeset
|
1723 map = context->static_code_map; |
591
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Get Z80 core back into compileable state
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parents:
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diff
changeset
|
1724 opts->gen.ram_inst_sizes[0][address] = native_size; |
252
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Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
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changeset
|
1725 context->ram_code_flags[(address & 0x1C00) >> 10] |= 1 << ((address & 0x380) >> 7); |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
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diff
changeset
|
1726 context->ram_code_flags[((address + size) & 0x1C00) >> 10] |= 1 << (((address + size) & 0x380) >> 7); |
627
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1727 } else { |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1728 //HERE |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1729 address -= 0x4000; |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
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626
diff
changeset
|
1730 map = context->banked_code_map; |
235
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Get Z80 core working for simple programs
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diff
changeset
|
1731 if (!map->offsets) { |
627
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1732 map->offsets = malloc(sizeof(int32_t) * 0xC000); |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
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diff
changeset
|
1733 memset(map->offsets, 0xFF, sizeof(int32_t) * 0xC000); |
235
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Get Z80 core working for simple programs
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changeset
|
1734 } |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1735 } |
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Get Z80 core working for simple programs
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diff
changeset
|
1736 if (!map->base) { |
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Get Z80 core working for simple programs
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diff
changeset
|
1737 map->base = native_address; |
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Get Z80 core working for simple programs
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diff
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|
1738 } |
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Get Z80 core working for simple programs
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diff
changeset
|
1739 map->offsets[address] = native_address - map->base; |
253
3b34deba4ca0
Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents:
252
diff
changeset
|
1740 for(--size, orig_address++; size; --size, orig_address++) { |
252
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Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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changeset
|
1741 address = orig_address; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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parents:
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changeset
|
1742 if (address < 0x4000) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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diff
changeset
|
1743 address &= 0x1FFF; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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parents:
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diff
changeset
|
1744 map = context->static_code_map; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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parents:
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diff
changeset
|
1745 } else { |
627
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1746 address -= 0x4000; |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1747 map = context->banked_code_map; |
252
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Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
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changeset
|
1748 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1749 if (!map->offsets) { |
627
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1750 map->offsets = malloc(sizeof(int32_t) * 0xC000); |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1751 memset(map->offsets, 0xFF, sizeof(int32_t) * 0xC000); |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1752 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1753 map->offsets[address] = EXTENSION_WORD; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1754 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1755 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
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diff
changeset
|
1756 |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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diff
changeset
|
1757 #define INVALID_INSTRUCTION_START 0xFEEDFEED |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1758 |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
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diff
changeset
|
1759 uint32_t z80_get_instruction_start(native_map_slot * static_code_map, uint32_t address) |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1760 { |
627
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1761 //TODO: Fixme for address >= 0x4000 |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1762 if (!static_code_map->base || address >= 0x4000) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1763 return INVALID_INSTRUCTION_START; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1764 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1765 address &= 0x1FFF; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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parents:
250
diff
changeset
|
1766 if (static_code_map->offsets[address] == INVALID_OFFSET) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
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250
diff
changeset
|
1767 return INVALID_INSTRUCTION_START; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
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250
diff
changeset
|
1768 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1769 while (static_code_map->offsets[address] == EXTENSION_WORD) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
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diff
changeset
|
1770 --address; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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250
diff
changeset
|
1771 address &= 0x1FFF; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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diff
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|
1772 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1773 return address; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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250
diff
changeset
|
1774 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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diff
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|
1775 |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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diff
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|
1776 z80_context * z80_handle_code_write(uint32_t address, z80_context * context) |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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250
diff
changeset
|
1777 { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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diff
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|
1778 uint32_t inst_start = z80_get_instruction_start(context->static_code_map, address); |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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diff
changeset
|
1779 if (inst_start != INVALID_INSTRUCTION_START) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1780 code_ptr dst = z80_get_native_address(context, inst_start); |
966b46c68942
Get Z80 core back into compileable state
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590
diff
changeset
|
1781 code_info code = {dst, dst+16}; |
966b46c68942
Get Z80 core back into compileable state
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parents:
590
diff
changeset
|
1782 z80_options * opts = context->options; |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
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diff
changeset
|
1783 dprintf("patching code at %p for Z80 instruction at %X due to write to %X\n", code, inst_start, address); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
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diff
changeset
|
1784 mov_ir(&code, inst_start, opts->gen.scratch1, SZ_D); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
1785 call(&code, opts->retrans_stub); |
252
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|
1786 } |
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|
1787 return context; |
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|
1788 } |
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|
1789 |
264
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diff
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|
1790 uint8_t * z80_get_native_address_trans(z80_context * context, uint32_t address) |
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262
diff
changeset
|
1791 { |
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changeset
|
1792 uint8_t * addr = z80_get_native_address(context, address); |
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Mike Pavone <pavone@retrodev.com>
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262
diff
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|
1793 if (!addr) { |
8fd6652e56f8
Fix a crash bug in instruction retranslation
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262
diff
changeset
|
1794 translate_z80_stream(context, address); |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
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|
1795 addr = z80_get_native_address(context, address); |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
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262
diff
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|
1796 if (!addr) { |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1797 printf("Failed to translate %X to native code\n", address); |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
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|
1798 } |
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Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
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262
diff
changeset
|
1799 } |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
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262
diff
changeset
|
1800 return addr; |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
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|
1801 } |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
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262
diff
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|
1802 |
266
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Fix some more retranslation bugs in the Z80 core
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264
diff
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|
1803 void z80_handle_deferred(z80_context * context) |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
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|
1804 { |
590
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WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
1805 z80_options * opts = context->options; |
591
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Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1806 process_deferred(&opts->gen.deferred, context, (native_addr_func)z80_get_native_address); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1807 if (opts->gen.deferred) { |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
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diff
changeset
|
1808 translate_z80_stream(context, opts->gen.deferred->address); |
266
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264
diff
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|
1809 } |
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Mike Pavone <pavone@retrodev.com>
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264
diff
changeset
|
1810 } |
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Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1811 |
390
561fe3ea3fc8
Use a call instruction to figure out the original native address when retranslating so that it does not get lost when the byte transforms from a instruction word to extension word
Mike Pavone <pavone@retrodev.com>
parents:
389
diff
changeset
|
1812 void * z80_retranslate_inst(uint32_t address, z80_context * context, uint8_t * orig_start) |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
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250
diff
changeset
|
1813 { |
266
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Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
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264
diff
changeset
|
1814 char disbuf[80]; |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
1815 z80_options * opts = context->options; |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
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250
diff
changeset
|
1816 uint8_t orig_size = z80_get_native_inst_size(opts, address); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1817 code_info *code = &opts->gen.code; |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1818 uint8_t *after, *inst = get_native_pointer(address, (void **)context->mem_pointers, &opts->gen); |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
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250
diff
changeset
|
1819 z80inst instbuf; |
268
6c2d7e003a55
Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents:
267
diff
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|
1820 dprintf("Retranslating code at Z80 address %X, native address %p\n", address, orig_start); |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
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250
diff
changeset
|
1821 after = z80_decode(inst, &instbuf); |
268
6c2d7e003a55
Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents:
267
diff
changeset
|
1822 #ifdef DO_DEBUG_PRINT |
314
54c0e5f22198
Show absolute addresses for JR, JRCC and DJNZ in Z80 disassembler
Mike Pavone <pavone@retrodev.com>
parents:
313
diff
changeset
|
1823 z80_disasm(&instbuf, disbuf, address); |
266
376df762ddf5
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Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1824 if (instbuf.op == Z80_NOP) { |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
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|
1825 printf("%X\t%s(%d)\n", address, disbuf, instbuf.immed); |
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Mike Pavone <pavone@retrodev.com>
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264
diff
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|
1826 } else { |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1827 printf("%X\t%s\n", address, disbuf); |
267
1788e3f29c28
Don't mix *H regs with the REX prefix
Mike Pavone <pavone@retrodev.com>
parents:
266
diff
changeset
|
1828 } |
268
6c2d7e003a55
Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents:
267
diff
changeset
|
1829 #endif |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1830 if (orig_size != ZMAX_NATIVE_SIZE) { |
597
8d6ae5b3b87b
Update code->cur before calling z80_get_address_trans in z80_retranslate_inst to avoid any newly translated instructions from being placed in the "buffer zone". Save the current value of the code_info struct for placing the final jmp instruction in the correct place
Michael Pavone <pavone@retrodev.com>
parents:
594
diff
changeset
|
1831 check_alloc_code(code, ZMAX_NATIVE_SIZE); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1832 code_ptr start = code->cur; |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1833 deferred_addr * orig_deferred = opts->gen.deferred; |
652 | 1834 translate_z80inst(&instbuf, context, address, 0); |
644
2d7e84ae818c
Temporarily comment out code to translate Z80 instructions in place as in rare cases it can stomp the next instruction if a branch goes from a short from to a long one
Michael Pavone <pavone@retrodev.com>
parents:
628
diff
changeset
|
1835 /* |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
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250
diff
changeset
|
1836 if ((native_end - dst) <= orig_size) { |
264
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Mike Pavone <pavone@retrodev.com>
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262
diff
changeset
|
1837 uint8_t * native_next = z80_get_native_address(context, address + after-inst); |
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Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
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262
diff
changeset
|
1838 if (native_next && ((native_next == orig_start + orig_size) || (orig_size - (native_end - dst)) > 5)) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1839 remove_deferred_until(&opts->gen.deferred, orig_deferred); |
627
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1840 native_end = translate_z80inst(&instbuf, orig_start, context, address, 0); |
266
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Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1841 if (native_next == orig_start + orig_size && (native_next-native_end) < 2) { |
264
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1842 while (native_end < orig_start + orig_size) { |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1843 *(native_end++) = 0x90; //NOP |
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Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1844 } |
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Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
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262
diff
changeset
|
1845 } else { |
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Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1846 jmp(native_end, native_next); |
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Mike Pavone <pavone@retrodev.com>
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262
diff
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|
1847 } |
266
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264
diff
changeset
|
1848 z80_handle_deferred(context); |
264
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Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
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262
diff
changeset
|
1849 return orig_start; |
252
63b9a500a00b
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Mike Pavone <pavone@retrodev.com>
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250
diff
changeset
|
1850 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1851 }*/ |
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Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1852 z80_map_native_address(context, address, start, after-inst, ZMAX_NATIVE_SIZE); |
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Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
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590
diff
changeset
|
1853 code_info tmp_code = {orig_start, orig_start + 16}; |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1854 jmp(&tmp_code, start); |
597
8d6ae5b3b87b
Update code->cur before calling z80_get_address_trans in z80_retranslate_inst to avoid any newly translated instructions from being placed in the "buffer zone". Save the current value of the code_info struct for placing the final jmp instruction in the correct place
Michael Pavone <pavone@retrodev.com>
parents:
594
diff
changeset
|
1855 tmp_code = *code; |
8d6ae5b3b87b
Update code->cur before calling z80_get_address_trans in z80_retranslate_inst to avoid any newly translated instructions from being placed in the "buffer zone". Save the current value of the code_info struct for placing the final jmp instruction in the correct place
Michael Pavone <pavone@retrodev.com>
parents:
594
diff
changeset
|
1856 code->cur = start + ZMAX_NATIVE_SIZE; |
283
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1857 if (!z80_is_terminal(&instbuf)) { |
597
8d6ae5b3b87b
Update code->cur before calling z80_get_address_trans in z80_retranslate_inst to avoid any newly translated instructions from being placed in the "buffer zone". Save the current value of the code_info struct for placing the final jmp instruction in the correct place
Michael Pavone <pavone@retrodev.com>
parents:
594
diff
changeset
|
1858 jmp(&tmp_code, z80_get_native_address_trans(context, address + after-inst)); |
264
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262
diff
changeset
|
1859 } |
266
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264
diff
changeset
|
1860 z80_handle_deferred(context); |
591
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Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1861 return start; |
252
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Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
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250
diff
changeset
|
1862 } else { |
591
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Get Z80 core back into compileable state
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diff
changeset
|
1863 code_info tmp_code = *code; |
966b46c68942
Get Z80 core back into compileable state
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590
diff
changeset
|
1864 code->cur = orig_start; |
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Get Z80 core back into compileable state
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parents:
590
diff
changeset
|
1865 code->last = orig_start + ZMAX_NATIVE_SIZE; |
652 | 1866 translate_z80inst(&instbuf, context, address, 0); |
601
f0061e3d2ad9
Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor
Michael Pavone <pavone@retrodev.com>
parents:
598
diff
changeset
|
1867 code_info tmp2 = *code; |
f0061e3d2ad9
Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor
Michael Pavone <pavone@retrodev.com>
parents:
598
diff
changeset
|
1868 *code = tmp_code; |
283
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1869 if (!z80_is_terminal(&instbuf)) { |
652 | 1870 |
601
f0061e3d2ad9
Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor
Michael Pavone <pavone@retrodev.com>
parents:
598
diff
changeset
|
1871 jmp(&tmp2, z80_get_native_address_trans(context, address + after-inst)); |
252
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250
diff
changeset
|
1872 } |
266
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diff
changeset
|
1873 z80_handle_deferred(context); |
252
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Mike Pavone <pavone@retrodev.com>
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250
diff
changeset
|
1874 return orig_start; |
63b9a500a00b
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diff
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|
1875 } |
235
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Get Z80 core working for simple programs
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213
diff
changeset
|
1876 } |
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213
diff
changeset
|
1877 |
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diff
changeset
|
1878 void translate_z80_stream(z80_context * context, uint32_t address) |
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diff
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|
1879 { |
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213
diff
changeset
|
1880 char disbuf[80]; |
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diff
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|
1881 if (z80_get_native_address(context, address)) { |
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213
diff
changeset
|
1882 return; |
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213
diff
changeset
|
1883 } |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
1884 z80_options * opts = context->options; |
505
b7b7a1cab44a
The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1885 uint32_t start_address = address; |
627
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1886 |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
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parents:
652
diff
changeset
|
1887 do |
235
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parents:
213
diff
changeset
|
1888 { |
d9bf8e61c33c
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213
diff
changeset
|
1889 z80inst inst; |
268
6c2d7e003a55
Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents:
267
diff
changeset
|
1890 dprintf("translating Z80 code at address %X\n", address); |
235
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parents:
213
diff
changeset
|
1891 do { |
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213
diff
changeset
|
1892 uint8_t * existing = z80_get_native_address(context, address); |
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213
diff
changeset
|
1893 if (existing) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1894 jmp(&opts->gen.code, existing); |
235
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213
diff
changeset
|
1895 break; |
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213
diff
changeset
|
1896 } |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1897 uint8_t * encoded, *next; |
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1898 encoded = get_native_pointer(address, (void **)context->mem_pointers, &opts->gen); |
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1899 if (!encoded) { |
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
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|
1900 code_info stub = z80_make_interp_stub(context, address); |
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1901 z80_map_native_address(context, address, stub.cur, 1, stub.last - stub.cur); |
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1902 break; |
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1903 } |
601
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1904 //make sure prologue is in a contiguous chunk of code |
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1905 check_code_prologue(&opts->gen.code); |
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1906 next = z80_decode(encoded, &inst); |
268
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1907 #ifdef DO_DEBUG_PRINT |
314
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1908 z80_disasm(&inst, disbuf, address); |
235
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1909 if (inst.op == Z80_NOP) { |
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1910 printf("%X\t%s(%d)\n", address, disbuf, inst.immed); |
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1911 } else { |
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1912 printf("%X\t%s\n", address, disbuf); |
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1913 } |
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1914 #endif |
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1915 code_ptr start = opts->gen.code.cur; |
652 | 1916 translate_z80inst(&inst, context, address, 0); |
591
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1917 z80_map_native_address(context, address, start, next-encoded, opts->gen.code.cur - start); |
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1918 address += next-encoded; |
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1919 address &= 0xFFFF; |
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1920 } while (!z80_is_terminal(&inst)); |
591
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1921 process_deferred(&opts->gen.deferred, context, (native_addr_func)z80_get_native_address); |
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1922 if (opts->gen.deferred) { |
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1923 address = opts->gen.deferred->address; |
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1924 dprintf("defferred address: %X\n", address); |
235
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1925 } |
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1926 } while (opts->gen.deferred); |
213
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1927 } |
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1928 |
592
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1929 void init_x86_z80_opts(z80_options * options, memmap_chunk const * chunks, uint32_t num_chunks) |
213
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1930 { |
590
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1931 memset(options, 0, sizeof(*options)); |
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1932 |
653
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1933 options->gen.memmap = chunks; |
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1934 options->gen.memmap_chunks = num_chunks; |
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1935 options->gen.address_size = SZ_W; |
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1936 options->gen.address_mask = 0xFFFF; |
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1937 options->gen.max_address = 0x10000; |
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1938 options->gen.bus_cycles = 3; |
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1939 options->gen.mem_ptr_off = offsetof(z80_context, mem_pointers); |
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1940 options->gen.ram_flags_off = offsetof(z80_context, ram_code_flags); |
620
9d6fed6501ba
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1941 options->gen.ram_flags_shift = 7; |
590
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1942 |
235
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1943 options->flags = 0; |
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1944 options->regs[Z80_B] = BH; |
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1945 options->regs[Z80_C] = RBX; |
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1946 options->regs[Z80_D] = CH; |
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1947 options->regs[Z80_E] = RCX; |
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1948 options->regs[Z80_H] = AH; |
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1949 options->regs[Z80_L] = RAX; |
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1950 options->regs[Z80_IXH] = DH; |
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1951 options->regs[Z80_IXL] = RDX; |
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1952 options->regs[Z80_IYH] = -1; |
239
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1953 options->regs[Z80_IYL] = R8; |
235
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1954 options->regs[Z80_I] = -1; |
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1955 options->regs[Z80_R] = -1; |
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1956 options->regs[Z80_A] = R10; |
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1957 options->regs[Z80_BC] = RBX; |
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1958 options->regs[Z80_DE] = RCX; |
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1959 options->regs[Z80_HL] = RAX; |
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1960 options->regs[Z80_SP] = R9; |
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1961 options->regs[Z80_AF] = -1; |
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1962 options->regs[Z80_IX] = RDX; |
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1963 options->regs[Z80_IY] = R8; |
590
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1964 |
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1965 options->bank_reg = R15; |
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1966 options->bank_pointer = R12; |
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|
1967 |
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1968 options->gen.context_reg = RSI; |
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1969 options->gen.cycles = RBP; |
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1970 options->gen.limit = RDI; |
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1971 options->gen.scratch1 = R13; |
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1972 options->gen.scratch2 = R14; |
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|
1973 |
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1974 options->gen.native_code_map = malloc(sizeof(native_map_slot)); |
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1975 memset(options->gen.native_code_map, 0, sizeof(native_map_slot)); |
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1976 options->gen.deferred = NULL; |
591
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1977 options->gen.ram_inst_sizes = malloc(sizeof(uint8_t) * 0x2000 + sizeof(uint8_t *)); |
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1978 options->gen.ram_inst_sizes[0] = (uint8_t *)(options->gen.ram_inst_sizes + 1); |
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1979 memset(options->gen.ram_inst_sizes[0], 0, sizeof(uint8_t) * 0x2000); |
590
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|
1980 |
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1981 code_info *code = &options->gen.code; |
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1982 init_code_info(code); |
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|
1983 |
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1984 options->save_context_scratch = code->cur; |
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1985 mov_rrdisp(code, options->gen.scratch1, options->gen.context_reg, offsetof(z80_context, scratch1), SZ_W); |
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1986 mov_rrdisp(code, options->gen.scratch2, options->gen.context_reg, offsetof(z80_context, scratch2), SZ_W); |
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|
1987 |
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|
1988 options->gen.save_context = code->cur; |
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1989 for (int i = 0; i <= Z80_A; i++) |
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|
1990 { |
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|
1991 int reg; |
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1992 uint8_t size; |
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1993 if (i < Z80_I) { |
594
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1994 reg = i /2 + Z80_BC + (i > Z80_H ? 2 : 0); |
590
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1995 size = SZ_W; |
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1996 } else { |
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|
1997 reg = i; |
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1998 size = SZ_B; |
652 | 1999 } |
590
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2000 if (options->regs[reg] >= 0) { |
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2001 mov_rrdisp(code, options->regs[reg], options->gen.context_reg, offsetof(z80_context, regs) + i, size); |
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2002 } |
594
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|
2003 if (size == SZ_W) { |
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|
2004 i++; |
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2005 } |
590
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|
2006 } |
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|
2007 if (options->regs[Z80_SP] >= 0) { |
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|
2008 mov_rrdisp(code, options->regs[Z80_SP], options->gen.context_reg, offsetof(z80_context, sp), SZ_W); |
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|
2009 } |
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|
2010 mov_rrdisp(code, options->gen.limit, options->gen.context_reg, offsetof(z80_context, target_cycle), SZ_D); |
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changeset
|
2011 mov_rrdisp(code, options->gen.cycles, options->gen.context_reg, offsetof(z80_context, current_cycle), SZ_D); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2012 mov_rrdisp(code, options->bank_reg, options->gen.context_reg, offsetof(z80_context, bank_reg), SZ_W); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2013 mov_rrdisp(code, options->bank_pointer, options->gen.context_reg, offsetof(z80_context, mem_pointers) + sizeof(uint8_t *) * 1, SZ_PTR); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2014 retn(code); |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2015 |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2016 options->load_context_scratch = code->cur; |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2017 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, scratch1), options->gen.scratch1, SZ_W); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2018 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, scratch2), options->gen.scratch2, SZ_W); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2019 options->gen.load_context = code->cur; |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2020 for (int i = 0; i <= Z80_A; i++) |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2021 { |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2022 int reg; |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2023 uint8_t size; |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2024 if (i < Z80_I) { |
594
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2025 reg = i /2 + Z80_BC + (i > Z80_H ? 2 : 0); |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2026 size = SZ_W; |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2027 } else { |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2028 reg = i; |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2029 size = SZ_B; |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2030 } |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2031 if (options->regs[reg] >= 0) { |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2032 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, regs) + i, options->regs[reg], size); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2033 } |
594
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2034 if (size == SZ_W) { |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2035 i++; |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2036 } |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2037 } |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2038 if (options->regs[Z80_SP] >= 0) { |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2039 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, sp), options->regs[Z80_SP], SZ_W); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2040 } |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2041 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, target_cycle), options->gen.limit, SZ_D); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2042 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, current_cycle), options->gen.cycles, SZ_D); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2043 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, bank_reg), options->bank_reg, SZ_W); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2044 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, mem_pointers) + sizeof(uint8_t *) * 1, options->bank_pointer, SZ_PTR); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2045 retn(code); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2046 |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2047 options->native_addr = code->cur; |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2048 call(code, options->gen.save_context); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2049 push_r(code, options->gen.context_reg); |
657
92ce5ea5ffc9
Use call_args and call_args_abi in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
653
diff
changeset
|
2050 movzx_rr(code, options->gen.scratch1, options->gen.scratch1, SZ_W, SZ_D); |
92ce5ea5ffc9
Use call_args and call_args_abi in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
653
diff
changeset
|
2051 call_args(code, (code_ptr)z80_get_native_address_trans, 2, options->gen.context_reg, options->gen.scratch1); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2052 mov_rr(code, RAX, options->gen.scratch1, SZ_PTR); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2053 pop_r(code, options->gen.context_reg); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2054 call(code, options->gen.load_context); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2055 retn(code); |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2056 |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2057 options->gen.handle_cycle_limit = code->cur; |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2058 cmp_rdispr(code, options->gen.context_reg, offsetof(z80_context, sync_cycle), options->gen.cycles, SZ_D); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2059 code_ptr no_sync = code->cur+1; |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2060 jcc(code, CC_B, no_sync); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2061 mov_irdisp(code, 0, options->gen.context_reg, offsetof(z80_context, pc), SZ_W); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2062 call(code, options->save_context_scratch); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2063 pop_r(code, RAX); //return address in read/write func |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2064 pop_r(code, RBX); //return address in translated code |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2065 sub_ir(code, 5, RAX, SZ_PTR); //adjust return address to point to the call that got us here |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2066 mov_rrdisp(code, RBX, options->gen.context_reg, offsetof(z80_context, extra_pc), SZ_PTR); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2067 mov_rrind(code, RAX, options->gen.context_reg, SZ_PTR); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2068 //restore callee saved registers |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2069 pop_r(code, R15); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2070 pop_r(code, R14); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2071 pop_r(code, R13); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2072 pop_r(code, R12); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2073 pop_r(code, RBP); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2074 pop_r(code, RBX); |
598
faad1927d836
Fix an off-by-one error in a branch destination in the generation of handle_cycle_limit for the Z80
Michael Pavone <pavone@retrodev.com>
parents:
597
diff
changeset
|
2075 *no_sync = code->cur - (no_sync + 1); |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2076 //return to caller of z80_run |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2077 retn(code); |
652 | 2078 |
594
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2079 options->gen.handle_code_write = (code_ptr)z80_handle_code_write; |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2080 |
594
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2081 options->read_8 = gen_mem_fun(&options->gen, chunks, num_chunks, READ_8, &options->read_8_noinc); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2082 options->write_8 = gen_mem_fun(&options->gen, chunks, num_chunks, WRITE_8, &options->write_8_noinc); |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2083 |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2084 options->gen.handle_cycle_limit_int = code->cur; |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2085 cmp_rdispr(code, options->gen.context_reg, offsetof(z80_context, int_cycle), options->gen.cycles, SZ_D); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2086 code_ptr skip_int = code->cur+1; |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2087 jcc(code, CC_B, skip_int); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2088 //set limit to the cycle limit |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2089 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, sync_cycle), options->gen.limit, SZ_D); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2090 //disable interrupts |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2091 mov_irdisp(code, 0, options->gen.context_reg, offsetof(z80_context, iff1), SZ_B); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2092 mov_irdisp(code, 0, options->gen.context_reg, offsetof(z80_context, iff2), SZ_B); |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2093 cycles(&options->gen, 7); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2094 //save return address (in scratch1) to Z80 stack |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2095 sub_ir(code, 2, options->regs[Z80_SP], SZ_W); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2096 mov_rr(code, options->regs[Z80_SP], options->gen.scratch2, SZ_W); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2097 //we need to do check_cycles and cycles outside of the write_8 call |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2098 //so that the stack has the correct depth if we need to return to C |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2099 //for a synchronization |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2100 check_cycles(&options->gen); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2101 cycles(&options->gen, 3); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2102 //save word to write before call to write_8_noinc |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2103 push_r(code, options->gen.scratch1); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2104 call(code, options->write_8_noinc); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2105 //restore word to write |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2106 pop_r(code, options->gen.scratch1); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2107 //write high byte to SP+1 |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2108 mov_rr(code, options->regs[Z80_SP], options->gen.scratch2, SZ_W); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2109 add_ir(code, 1, options->gen.scratch2, SZ_W); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2110 shr_ir(code, 8, options->gen.scratch1, SZ_W); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2111 check_cycles(&options->gen); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2112 cycles(&options->gen, 3); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2113 call(code, options->write_8_noinc); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2114 //dispose of return address as we'll be jumping somewhere else |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2115 pop_r(code, options->gen.scratch2); |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2116 //TODO: Support interrupt mode 0 and 2 |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2117 mov_ir(code, 0x38, options->gen.scratch1, SZ_W); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2118 call(code, options->native_addr); |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2119 jmp_r(code, options->gen.scratch1); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2120 *skip_int = code->cur - (skip_int+1); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2121 cmp_rdispr(code, options->gen.context_reg, offsetof(z80_context, sync_cycle), options->gen.cycles, SZ_D); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2122 code_ptr skip_sync = code->cur + 1; |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2123 jcc(code, CC_B, skip_sync); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2124 options->do_sync = code->cur; |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2125 call(code, options->gen.save_context); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2126 pop_rind(code, options->gen.context_reg); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2127 //restore callee saved registers |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2128 pop_r(code, R15); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2129 pop_r(code, R14); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2130 pop_r(code, R13); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2131 pop_r(code, R12); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2132 pop_r(code, RBP); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2133 pop_r(code, RBX); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2134 //return to caller of z80_run |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2135 *skip_sync = code->cur - (skip_sync+1); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2136 retn(code); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2137 |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2138 options->read_io = code->cur; |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2139 check_cycles(&options->gen); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2140 cycles(&options->gen, 4); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2141 //Genesis has no IO hardware and always returns FF |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2142 //eventually this should use a second memory map array |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2143 mov_ir(code, 0xFF, options->gen.scratch1, SZ_B); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2144 retn(code); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2145 |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2146 options->write_io = code->cur; |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2147 check_cycles(&options->gen); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2148 cycles(&options->gen, 4); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2149 retn(code); |
652 | 2150 |
594
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2151 options->read_16 = code->cur; |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2152 cycles(&options->gen, 3); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2153 check_cycles(&options->gen); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2154 //TODO: figure out how to handle the extra wait state for word reads to bank area |
657
92ce5ea5ffc9
Use call_args and call_args_abi in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
653
diff
changeset
|
2155 //may also need special handling to avoid too much stack depth when access is blocked |
594
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2156 push_r(code, options->gen.scratch1); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2157 call(code, options->read_8_noinc); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2158 mov_rr(code, options->gen.scratch1, options->gen.scratch2, SZ_B); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2159 pop_r(code, options->gen.scratch1); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2160 add_ir(code, 1, options->gen.scratch1, SZ_W); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2161 cycles(&options->gen, 3); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2162 check_cycles(&options->gen); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2163 call(code, options->read_8_noinc); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2164 shl_ir(code, 8, options->gen.scratch1, SZ_W); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2165 mov_rr(code, options->gen.scratch2, options->gen.scratch1, SZ_B); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2166 retn(code); |
652 | 2167 |
594
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2168 options->write_16_highfirst = code->cur; |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2169 cycles(&options->gen, 3); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2170 check_cycles(&options->gen); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2171 push_r(code, options->gen.scratch2); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2172 push_r(code, options->gen.scratch1); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2173 add_ir(code, 1, options->gen.scratch2, SZ_W); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2174 shr_ir(code, 8, options->gen.scratch1, SZ_W); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2175 call(code, options->write_8_noinc); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2176 pop_r(code, options->gen.scratch1); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2177 pop_r(code, options->gen.scratch2); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2178 cycles(&options->gen, 3); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2179 check_cycles(&options->gen); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2180 //TODO: Check if we can get away with TCO here |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2181 call(code, options->write_8_noinc); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2182 retn(code); |
652 | 2183 |
594
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2184 options->write_16_lowfirst = code->cur; |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2185 cycles(&options->gen, 3); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2186 check_cycles(&options->gen); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2187 push_r(code, options->gen.scratch2); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2188 push_r(code, options->gen.scratch1); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2189 call(code, options->write_8_noinc); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2190 pop_r(code, options->gen.scratch1); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2191 pop_r(code, options->gen.scratch2); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2192 add_ir(code, 1, options->gen.scratch2, SZ_W); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2193 shr_ir(code, 8, options->gen.scratch1, SZ_W); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2194 cycles(&options->gen, 3); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2195 check_cycles(&options->gen); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2196 //TODO: Check if we can get away with TCO here |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2197 call(code, options->write_8_noinc); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2198 retn(code); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2199 |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2200 options->retrans_stub = code->cur; |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2201 //pop return address |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2202 pop_r(code, options->gen.scratch2); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2203 call(code, options->gen.save_context); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2204 //adjust pointer before move and call instructions that got us here |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2205 sub_ir(code, 11, options->gen.scratch2, SZ_PTR); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2206 push_r(code, options->gen.context_reg); |
657
92ce5ea5ffc9
Use call_args and call_args_abi in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
653
diff
changeset
|
2207 call_args(code, (code_ptr)z80_retranslate_inst, 3, options->gen.scratch1, options->gen.context_reg, options->gen.scratch2); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2208 pop_r(code, options->gen.context_reg); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2209 mov_rr(code, RAX, options->gen.scratch1, SZ_PTR); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2210 call(code, options->gen.load_context); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2211 jmp_r(code, options->gen.scratch1); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2212 |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2213 options->run = (z80_run_fun)code->cur; |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2214 //save callee save registers |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2215 push_r(code, RBX); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2216 push_r(code, RBP); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2217 push_r(code, R12); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2218 push_r(code, R13); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2219 push_r(code, R14); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2220 push_r(code, R15); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2221 mov_rr(code, RDI, options->gen.context_reg, SZ_PTR); |
594
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2222 call(code, options->load_context_scratch); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
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2223 cmp_irdisp(code, 0, options->gen.context_reg, offsetof(z80_context, extra_pc), SZ_PTR); |
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2224 code_ptr no_extra = code->cur+1; |
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2225 jcc(code, CC_Z, no_extra); |
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2226 push_rdisp(code, options->gen.context_reg, offsetof(z80_context, extra_pc)); |
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2227 mov_irdisp(code, 0, options->gen.context_reg, offsetof(z80_context, extra_pc), SZ_PTR); |
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2228 *no_extra = code->cur - (no_extra + 1); |
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2229 jmp_rind(code, options->gen.context_reg); |
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2230 } |
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2231 |
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2232 void * z80_gen_bank_write(uint32_t start_address, void * voptions) |
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2233 { |
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2234 z80_options * options = voptions; |
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|
2235 //TODO: Handle writes to bank register |
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2236 return options; |
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2237 } |
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2238 |
590
ea80559c67cb
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2239 void init_z80_context(z80_context * context, z80_options * options) |
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2240 { |
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2241 memset(context, 0, sizeof(*context)); |
360
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2242 context->static_code_map = malloc(sizeof(*context->static_code_map)); |
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2243 context->static_code_map->base = NULL; |
235
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2244 context->static_code_map->offsets = malloc(sizeof(int32_t) * 0x2000); |
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2245 memset(context->static_code_map->offsets, 0xFF, sizeof(int32_t) * 0x2000); |
627
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diff
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2246 context->banked_code_map = malloc(sizeof(native_map_slot)); |
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2247 memset(context->banked_code_map, 0, sizeof(native_map_slot)); |
235
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2248 context->options = options; |
625
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Michael Pavone <pavone@retrodev.com>
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506
diff
changeset
|
2249 context->int_cycle = 0xFFFFFFFF; |
628 | 2250 context->int_pulse_start = 0xFFFFFFFF; |
2251 context->int_pulse_end = 0xFFFFFFFF; | |
593
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2252 context->run = options->run; |
235
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2253 } |
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2254 |
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2255 void z80_reset(z80_context * context) |
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2256 { |
259
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|
2257 context->im = 0; |
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2258 context->iff1 = context->iff2 = 0; |
235
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2259 context->native_pc = z80_get_native_address_trans(context, 0); |
268
6c2d7e003a55
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2260 context->extra_pc = NULL; |
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2261 } |
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2262 |
652 | 2263 uint32_t zbreakpoint_patch(z80_context * context, uint16_t address, code_ptr dst) |
626
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Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
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diff
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|
2264 { |
652 | 2265 code_info code = {dst, dst+16}; |
2266 mov_ir(&code, address, SCRATCH1, SZ_W); | |
2267 call(&code, context->bp_stub); | |
2268 return code.cur-dst; | |
626
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Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
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|
2269 } |
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|
2270 |
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Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
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diff
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|
2271 void zcreate_stub(z80_context * context) |
7c46891a29b1
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|
2272 { |
652 | 2273 z80_options * opts = context->options; |
2274 code_info *code = &opts->gen.code; | |
2275 check_code_prologue(code); | |
2276 context->bp_stub = code->cur; | |
626
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|
2277 |
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diff
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|
2278 //Calculate length of prologue |
652 | 2279 check_cycles_int(&opts->gen, 0); |
2280 int check_int_size = code->cur-context->bp_stub; | |
2281 code->cur = context->bp_stub; | |
626
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|
2282 |
7c46891a29b1
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diff
changeset
|
2283 //Calculate length of patch |
652 | 2284 int patch_size = zbreakpoint_patch(context, 0, code->cur); |
626
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|
2285 |
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|
2286 //Save context and call breakpoint handler |
652 | 2287 call(code, opts->gen.save_context); |
2288 push_r(code, opts->gen.scratch1); | |
657
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Michael Pavone <pavone@retrodev.com>
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653
diff
changeset
|
2289 call_args_abi(code, context->bp_handler, 2, opts->gen.context_reg, opts->gen.scratch1); |
652 | 2290 mov_rr(code, RAX, opts->gen.context_reg, SZ_Q); |
626
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|
2291 //Restore context |
652 | 2292 call(code, opts->gen.load_context); |
2293 pop_r(code, opts->gen.scratch1); | |
626
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diff
changeset
|
2294 //do prologue stuff |
652 | 2295 cmp_rr(code, opts->gen.cycles, opts->gen.limit, SZ_D); |
2296 uint8_t * jmp_off = code->cur+1; | |
2297 jcc(code, CC_NC, code->cur + 7); | |
2298 pop_r(code, opts->gen.scratch1); | |
2299 add_ir(code, check_int_size - patch_size, opts->gen.scratch1, SZ_Q); | |
2300 push_r(code, opts->gen.scratch1); | |
2301 jmp(code, opts->gen.handle_cycle_limit_int); | |
2302 *jmp_off = code->cur - (jmp_off+1); | |
626
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diff
changeset
|
2303 //jump back to body of translated instruction |
652 | 2304 pop_r(code, opts->gen.scratch1); |
2305 add_ir(code, check_int_size - patch_size, opts->gen.scratch1, SZ_Q); | |
2306 jmp_r(code, opts->gen.scratch1); | |
626
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Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
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2307 } |
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2308 |
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2309 void zinsert_breakpoint(z80_context * context, uint16_t address, uint8_t * bp_handler) |
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2310 { |
626
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|
2311 context->bp_handler = bp_handler; |
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|
2312 uint8_t bit = 1 << (address % sizeof(uint8_t)); |
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2313 if (!(bit & context->breakpoint_flags[address / sizeof(uint8_t)])) { |
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diff
changeset
|
2314 context->breakpoint_flags[address / sizeof(uint8_t)] |= bit; |
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|
2315 if (!context->bp_stub) { |
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|
2316 zcreate_stub(context); |
366
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2317 } |
626
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|
2318 uint8_t * native = z80_get_native_address(context, address); |
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|
2319 if (native) { |
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|
2320 zbreakpoint_patch(context, address, native); |
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2321 } |
366
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2322 } |
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2323 } |
235
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2324 |
366
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2325 void zremove_breakpoint(z80_context * context, uint16_t address) |
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2326 { |
651
103d5cabbe14
Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
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|
2327 context->breakpoint_flags[address / sizeof(uint8_t)] &= ~(1 << (address % sizeof(uint8_t))); |
366
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|
2328 uint8_t * native = z80_get_native_address(context, address); |
626
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changeset
|
2329 if (native) { |
652 | 2330 z80_options * opts = context->options; |
2331 code_info tmp_code = opts->gen.code; | |
2332 opts->gen.code.cur = native; | |
2333 opts->gen.code.last = native + 16; | |
2334 check_cycles_int(&opts->gen, address); | |
2335 opts->gen.code = tmp_code; | |
626
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2336 } |
366
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2337 } |
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|
2338 |