Mercurial > repos > blastem
annotate vdp.c @ 494:8ac0eb05642c
Initial implementation of sprite overflow and sprite collision status register flags
author | Mike Pavone <pavone@retrodev.com> |
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date | Mon, 07 Oct 2013 10:02:08 -0700 |
parents | 1f3450d1129f |
children | 27345a67225d |
rev | line source |
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1 /* |
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2 Copyright 2013 Michael Pavone |
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3 This file is part of BlastEm. |
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4 BlastEm is free software distributed under the terms of the GNU General Public License version 3 or greater. See COPYING for full license text. |
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5 */ |
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6 #include "vdp.h" |
75 | 7 #include "blastem.h" |
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8 #include <stdlib.h> |
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9 #include <string.h> |
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10 #include "render.h" |
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11 |
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12 #define NTSC_ACTIVE 225 |
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13 #define PAL_ACTIVE 241 |
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14 #define BUF_BIT_PRIORITY 0x40 |
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15 #define MAP_BIT_PRIORITY 0x8000 |
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16 #define MAP_BIT_H_FLIP 0x800 |
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17 #define MAP_BIT_V_FLIP 0x1000 |
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18 |
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19 #define SCROLL_BUFFER_SIZE 32 |
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20 #define SCROLL_BUFFER_MASK (SCROLL_BUFFER_SIZE-1) |
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21 #define SCROLL_BUFFER_DRAW (SCROLL_BUFFER_SIZE/2) |
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22 |
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23 #define MCLKS_SLOT_H40 16 |
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24 #define MCLKS_SLOT_H32 20 |
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25 #define VINT_CYCLE_H40 (21*MCLKS_SLOT_H40+332+9*MCLKS_SLOT_H40) //21 slots before HSYNC, 16 during, 10 after |
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26 #define VINT_CYCLE_H32 ((33+20+7)*MCLKS_SLOT_H32) //33 slots before HSYNC, 20 during, 7 after TODO: confirm final number |
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27 #define HSYNC_SLOT_H40 21 |
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28 #define MCLK_WEIRD_END (HSYNC_SLOT_H40*MCLKS_SLOT_H40 + 332) |
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29 #define SLOT_WEIRD_END (HSYNC_SLOT_H40+17) |
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30 #define HSYNC_END_H32 (33 * MCLKS_SLOT_H32) |
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31 #define HBLANK_CLEAR_H40 (MCLK_WEIRD_END+61*4) |
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32 #define HBLANK_CLEAR_H32 (HSYNC_END_H32 + 46*5) |
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33 #define FIFO_LATENCY 3 |
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34 |
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35 int32_t color_map[1 << 12]; |
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36 uint8_t levels[] = {0, 27, 49, 71, 87, 103, 119, 130, 146, 157, 174, 190, 206, 228, 255}; |
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37 |
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38 uint8_t debug_base[][3] = { |
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39 {127, 127, 127}, //BG |
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40 {0, 0, 127}, //A |
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41 {127, 0, 0}, //Window |
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42 {0, 127, 0}, //B |
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43 {127, 0, 127} //Sprites |
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44 }; |
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45 |
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46 uint8_t color_map_init_done; |
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47 |
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48 void init_vdp_context(vdp_context * context) |
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49 { |
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50 memset(context, 0, sizeof(*context)); |
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51 context->vdpmem = malloc(VRAM_SIZE); |
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52 memset(context->vdpmem, 0, VRAM_SIZE); |
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53 context->oddbuf = context->framebuf = malloc(FRAMEBUF_ENTRIES * (render_depth() / 8)); |
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54 memset(context->framebuf, 0, FRAMEBUF_ENTRIES * (render_depth() / 8)); |
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55 context->evenbuf = malloc(FRAMEBUF_ENTRIES * (render_depth() / 8)); |
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56 memset(context->evenbuf, 0, FRAMEBUF_ENTRIES * (render_depth() / 8)); |
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57 context->linebuf = malloc(LINEBUF_SIZE + SCROLL_BUFFER_SIZE*2); |
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58 memset(context->linebuf, 0, LINEBUF_SIZE + SCROLL_BUFFER_SIZE*2); |
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59 context->tmp_buf_a = context->linebuf + LINEBUF_SIZE; |
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60 context->tmp_buf_b = context->tmp_buf_a + SCROLL_BUFFER_SIZE; |
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61 context->sprite_draws = MAX_DRAWS; |
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62 context->fifo_write = 0; |
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63 context->fifo_read = -1; |
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64 context->b32 = render_depth() == 32; |
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65 if (!color_map_init_done) { |
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66 uint8_t b,g,r; |
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67 for (uint16_t color = 0; color < (1 << 12); color++) { |
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68 if (color & FBUF_SHADOW) { |
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69 b = levels[(color >> 9) & 0x7]; |
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70 g = levels[(color >> 5) & 0x7]; |
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71 r = levels[(color >> 1) & 0x7]; |
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72 } else if(color & FBUF_HILIGHT) { |
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73 b = levels[((color >> 9) & 0x7) + 7]; |
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74 g = levels[((color >> 5) & 0x7) + 7]; |
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75 r = levels[((color >> 1) & 0x7) + 7]; |
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76 } else { |
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77 b = levels[(color >> 8) & 0xE]; |
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78 g = levels[(color >> 4) & 0xE]; |
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79 r = levels[color & 0xE]; |
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80 } |
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81 color_map[color] = render_map_color(r, g, b); |
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82 } |
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83 color_map_init_done = 1; |
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84 } |
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85 for (uint8_t color = 0; color < (1 << (3 + 1 + 1 + 1)); color++) |
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86 { |
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87 uint8_t src = color & DBG_SRC_MASK; |
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88 if (src > DBG_SRC_S) { |
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89 context->debugcolors[color] = 0; |
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90 } else { |
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91 uint8_t r,g,b; |
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92 b = debug_base[src][0]; |
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93 g = debug_base[src][1]; |
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94 r = debug_base[src][2]; |
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95 if (color & DBG_PRIORITY) |
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96 { |
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97 if (b) { |
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98 b += 48; |
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99 } |
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100 if (g) { |
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101 g += 48; |
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102 } |
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103 if (r) { |
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104 r += 48; |
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105 } |
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106 } |
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107 if (color & DBG_SHADOW) { |
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108 b /= 2; |
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109 g /= 2; |
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110 r /=2 ; |
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111 } |
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112 if (color & DBG_HILIGHT) { |
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113 if (b) { |
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114 b += 72; |
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115 } |
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116 if (g) { |
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117 g += 72; |
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118 } |
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119 if (r) { |
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120 r += 72; |
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121 } |
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122 } |
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123 context->debugcolors[color] = render_map_color(r, g, b); |
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124 } |
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125 } |
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126 } |
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127 |
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128 int is_refresh(vdp_context * context, uint32_t slot) |
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129 { |
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130 if (context->latched_mode & BIT_H40) { |
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131 return (slot == 37 || slot == 69 || slot == 102 || slot == 133 || slot == 165 || slot == 197 || slot >= 210); |
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132 } else { |
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133 //TODO: Figure out which slots are refresh when display is off in 32-cell mode |
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134 //These numbers are guesses based on H40 numbers |
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135 return (slot == 24 || slot == 56 || slot == 88 || slot == 120 || slot == 152); |
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136 //The numbers below are the refresh slots during active display |
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137 //return (slot == 66 || slot == 98 || slot == 130 || slot == 162); |
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138 } |
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139 } |
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140 |
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141 void render_sprite_cells(vdp_context * context) |
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142 { |
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143 if (context->cur_slot >= context->sprite_draws) { |
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144 sprite_draw * d = context->sprite_draw_list + context->cur_slot; |
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145 |
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146 uint16_t dir; |
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147 int16_t x; |
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148 if (d->h_flip) { |
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149 x = d->x_pos + 7; |
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150 dir = -1; |
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151 } else { |
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152 x = d->x_pos; |
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153 dir = 1; |
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154 } |
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155 //printf("Draw Slot %d of %d, Rendering sprite cell from %X to x: %d\n", context->cur_slot, context->sprite_draws, d->address, x); |
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156 context->cur_slot--; |
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157 for (uint16_t address = d->address; address != ((d->address+4) & 0xFFFF); address++) { |
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158 if (x >= 0 && x < 320 && !(context->linebuf[x] & 0xF)) { |
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159 if (context->linebuf[x] && (context->vdpmem[address] >> 4)) { |
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160 context->flags2 |= FLAG2_SPRITE_COLLIDE; |
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161 } |
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162 context->linebuf[x] = (context->vdpmem[address] >> 4) | d->pal_priority; |
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163 } |
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164 x += dir; |
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165 if (x >= 0 && x < 320 && !(context->linebuf[x] & 0xF)) { |
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166 if (context->linebuf[x] && (context->vdpmem[address] & 0xF)) { |
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167 context->flags2 |= FLAG2_SPRITE_COLLIDE; |
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168 } |
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169 context->linebuf[x] = (context->vdpmem[address] & 0xF) | d->pal_priority; |
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170 } |
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171 x += dir; |
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172 } |
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173 } |
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174 } |
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175 |
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176 void vdp_print_sprite_table(vdp_context * context) |
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177 { |
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178 uint16_t sat_address = (context->regs[REG_SAT] & 0x7F) << 9; |
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179 uint16_t current_index = 0; |
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180 uint8_t count = 0; |
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181 do { |
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182 uint16_t address = current_index * 8 + sat_address; |
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183 uint8_t height = ((context->vdpmem[address+2] & 0x3) + 1) * 8; |
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184 uint8_t width = (((context->vdpmem[address+2] >> 2) & 0x3) + 1) * 8; |
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185 int16_t y = ((context->vdpmem[address] & 0x3) << 8 | context->vdpmem[address+1]) & 0x1FF; |
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186 int16_t x = ((context->vdpmem[address+ 6] & 0x3) << 8 | context->vdpmem[address + 7]) & 0x1FF; |
322
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187 uint16_t link = context->vdpmem[address+3] & 0x7F; |
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188 uint8_t pal = context->vdpmem[address + 4] >> 5 & 0x3; |
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189 uint8_t pri = context->vdpmem[address + 4] >> 7; |
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190 uint16_t pattern = ((context->vdpmem[address + 4] << 8 | context->vdpmem[address + 5]) & 0x7FF) << 5; |
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191 //printf("Sprite %d: X=%d(%d), Y=%d(%d), Width=%u, Height=%u, Link=%u, Pal=%u, Pri=%u, Pat=%X\n", current_index, x, x-128, y, y-128, width, height, link, pal, pri, pattern); |
322
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192 current_index = link; |
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193 count++; |
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194 } while (current_index != 0 && count < 80); |
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195 } |
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196 |
327
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197 void vdp_print_reg_explain(vdp_context * context) |
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198 { |
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199 char * hscroll[] = {"full", "7-line", "cell", "line"}; |
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200 printf("**Mode Group**\n" |
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201 "00: %.2X | H-ints %s, Pal Select %d, HVC latch %s, Display gen %s\n" |
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202 "01: %.2X | Display %s, V-ints %s, Height: %d, Mode %d\n" |
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203 "0B: %.2X | E-ints %s, V-Scroll: %s, H-Scroll: %s\n" |
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204 "0C: %.2X | Width: %d, Shadow/Highlight: %s\n", |
450
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205 context->regs[REG_MODE_1], context->regs[REG_MODE_1] & BIT_HINT_EN ? "enabled" : "disabled", context->regs[REG_MODE_1] & BIT_PAL_SEL != 0, |
327
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206 context->regs[REG_MODE_1] & BIT_HVC_LATCH ? "enabled" : "disabled", context->regs[REG_MODE_1] & BIT_DISP_DIS ? "disabled" : "enabled", |
450
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207 context->regs[REG_MODE_2], context->regs[REG_MODE_2] & BIT_DISP_EN ? "enabled" : "disabled", context->regs[REG_MODE_2] & BIT_VINT_EN ? "enabled" : "disabled", |
327
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208 context->regs[REG_MODE_2] & BIT_PAL ? 30 : 28, context->regs[REG_MODE_2] & BIT_MODE_5 ? 5 : 4, |
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209 context->regs[REG_MODE_3], context->regs[REG_MODE_3] & BIT_EINT_EN ? "enabled" : "disabled", context->regs[REG_MODE_3] & BIT_VSCROLL ? "2 cell" : "full", |
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210 hscroll[context->regs[REG_MODE_3] & 0x3], |
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211 context->regs[REG_MODE_4], context->regs[REG_MODE_4] & BIT_H40 ? 40 : 32, context->regs[REG_MODE_4] & BIT_HILIGHT ? "enabled" : "disabled"); |
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212 printf("\n**Table Group**\n" |
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213 "02: %.2X | Scroll A Name Table: $%.4X\n" |
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214 "03: %.2X | Window Name Table: $%.4X\n" |
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215 "04: %.2X | Scroll B Name Table: $%.4X\n" |
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216 "05: %.2X | Sprite Attribute Table: $%.4X\n" |
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217 "0D: %.2X | HScroll Data Table: $%.4X\n", |
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218 context->regs[REG_SCROLL_A], (context->regs[REG_SCROLL_A] & 0x38) << 10, |
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219 context->regs[REG_WINDOW], (context->regs[REG_WINDOW] & (context->regs[REG_MODE_4] & BIT_H40 ? 0x3C : 0x3E)) << 10, |
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220 context->regs[REG_SCROLL_B], (context->regs[REG_SCROLL_B] & 0x7) << 13, |
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221 context->regs[REG_SAT], (context->regs[REG_SAT] & (context->regs[REG_MODE_4] & BIT_H40 ? 0x3E : 0x3F)) << 9, |
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222 context->regs[REG_HSCROLL], (context->regs[REG_HSCROLL] & 0x1F) << 10); |
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223 char * sizes[] = {"32", "64", "invalid", "128"}; |
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224 printf("\n**Misc Group**\n" |
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225 "07: %.2X | Backdrop Color: $%X\n" |
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226 "0A: %.2X | H-Int Counter: %u\n" |
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227 "0F: %.2X | Auto-increment: $%X\n" |
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228 "10: %.2X | Scroll A/B Size: %sx%s\n", |
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229 context->regs[REG_BG_COLOR], context->regs[REG_BG_COLOR] & 0x3F, |
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230 context->regs[REG_HINT], context->regs[REG_HINT], |
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231 context->regs[REG_AUTOINC], context->regs[REG_AUTOINC], |
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232 context->regs[REG_SCROLL], sizes[context->regs[REG_SCROLL] & 0x3], sizes[context->regs[REG_SCROLL] >> 4 & 0x3]); |
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233 printf("\n**Internal Group**\n" |
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234 "Address: %X\n" |
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235 "CD: %X\n" |
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236 "Pending: %s\n", |
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237 context->address, context->cd, (context->flags & FLAG_PENDING) ? "true" : "false"); |
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238 |
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239 //TODO: Window Group, DMA Group |
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240 } |
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241 |
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242 void scan_sprite_table(uint32_t line, vdp_context * context) |
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243 { |
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244 if (context->sprite_index && context->slot_counter) { |
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245 line += 1; |
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246 line &= 0xFF; |
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247 uint16_t ymask, ymin; |
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248 uint8_t height_mult; |
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249 if (context->double_res) { |
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250 line *= 2; |
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251 if (context->framebuf != context->oddbuf) { |
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252 line++; |
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253 } |
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254 ymask = 0x3FF; |
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255 ymin = 256; |
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256 height_mult = 16; |
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257 } else { |
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258 ymask = 0x1FF; |
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259 ymin = 128; |
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260 height_mult = 8; |
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261 } |
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262 context->sprite_index &= 0x7F; |
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263 if (context->latched_mode & BIT_H40) { |
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264 if (context->sprite_index >= MAX_SPRITES_FRAME) { |
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265 context->sprite_index = 0; |
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266 return; |
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267 } |
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268 } else if(context->sprite_index >= MAX_SPRITES_FRAME_H32) { |
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269 context->sprite_index = 0; |
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270 return; |
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271 } |
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272 //TODO: Read from SAT cache rather than from VRAM |
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273 uint16_t sat_address = (context->regs[REG_SAT] & 0x7F) << 9; |
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274 uint16_t address = context->sprite_index * 8 + sat_address; |
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275 line += ymin; |
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276 uint16_t y = ((context->vdpmem[address] & 0x3) << 8 | context->vdpmem[address+1]) & ymask; |
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277 uint8_t height = ((context->vdpmem[address+2] & 0x3) + 1) * height_mult; |
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278 //printf("Sprite %d | y: %d, height: %d\n", context->sprite_index, y, height); |
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279 if (y <= line && line < (y + height)) { |
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280 //printf("Sprite %d at y: %d with height %d is on line %d\n", context->sprite_index, y, height, line); |
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281 context->sprite_info_list[--(context->slot_counter)].size = context->vdpmem[address+2]; |
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282 context->sprite_info_list[context->slot_counter].index = context->sprite_index; |
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283 context->sprite_info_list[context->slot_counter].y = y-ymin; |
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284 } |
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285 context->sprite_index = context->vdpmem[address+3] & 0x7F; |
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286 if (context->sprite_index && context->slot_counter) |
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287 { |
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288 address = context->sprite_index * 8 + sat_address; |
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289 y = ((context->vdpmem[address] & 0x3) << 8 | context->vdpmem[address+1]) & ymask; |
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290 height = ((context->vdpmem[address+2] & 0x3) + 1) * height_mult; |
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291 //printf("Sprite %d | y: %d, height: %d\n", context->sprite_index, y, height); |
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292 if (y <= line && line < (y + height)) { |
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293 //printf("Sprite %d at y: %d with height %d is on line %d\n", context->sprite_index, y, height, line); |
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294 context->sprite_info_list[--(context->slot_counter)].size = context->vdpmem[address+2]; |
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295 context->sprite_info_list[context->slot_counter].index = context->sprite_index; |
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296 context->sprite_info_list[context->slot_counter].y = y-ymin; |
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297 } |
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298 context->sprite_index = context->vdpmem[address+3] & 0x7F; |
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299 } |
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300 } |
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301 } |
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302 |
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303 void read_sprite_x(uint32_t line, vdp_context * context) |
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304 { |
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305 if (context->cur_slot >= context->slot_counter) { |
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306 if (context->sprite_draws) { |
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307 line += 1; |
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308 line &= 0xFF; |
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309 //in tiles |
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310 uint8_t width = ((context->sprite_info_list[context->cur_slot].size >> 2) & 0x3) + 1; |
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311 //in pixels |
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312 uint8_t height = ((context->sprite_info_list[context->cur_slot].size & 0x3) + 1) * 8; |
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313 if (context->double_res) { |
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314 line *= 2; |
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315 if (context->framebuf != context->oddbuf) { |
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316 line++; |
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317 } |
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318 height *= 2; |
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319 } |
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320 uint16_t att_addr = ((context->regs[REG_SAT] & 0x7F) << 9) + context->sprite_info_list[context->cur_slot].index * 8 + 4; |
450
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321 uint16_t tileinfo = (context->vdpmem[att_addr] << 8) | context->vdpmem[att_addr+1]; |
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322 uint8_t pal_priority = (tileinfo >> 9) & 0x70; |
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323 uint8_t row; |
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324 if (tileinfo & MAP_BIT_V_FLIP) { |
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325 row = (context->sprite_info_list[context->cur_slot].y + height - 1) - line; |
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326 } else { |
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327 row = line-context->sprite_info_list[context->cur_slot].y; |
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328 } |
413
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329 uint16_t address; |
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330 if (context->double_res) { |
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331 address = ((tileinfo & 0x3FF) << 6) + row * 4; |
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332 } else { |
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333 address = ((tileinfo & 0x7FF) << 5) + row * 4; |
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334 } |
323
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335 int16_t x = ((context->vdpmem[att_addr+ 2] & 0x3) << 8 | context->vdpmem[att_addr + 3]) & 0x1FF; |
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336 if (x) { |
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337 context->flags |= FLAG_CAN_MASK; |
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338 } else if(context->flags & (FLAG_CAN_MASK | FLAG_DOT_OFLOW)) { |
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339 context->flags |= FLAG_MASKED; |
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340 } |
450
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341 |
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342 context->flags &= ~FLAG_DOT_OFLOW; |
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343 int16_t i; |
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344 if (context->flags & FLAG_MASKED) { |
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345 for (i=0; i < width && context->sprite_draws; i++) { |
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346 --context->sprite_draws; |
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347 context->sprite_draw_list[context->sprite_draws].x_pos = -128; |
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348 } |
36
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349 } else { |
34
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350 x -= 128; |
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351 int16_t base_x = x; |
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352 int16_t dir; |
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353 if (tileinfo & MAP_BIT_H_FLIP) { |
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354 x += (width-1) * 8; |
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355 dir = -8; |
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356 } else { |
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357 dir = 8; |
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358 } |
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359 //printf("Sprite %d | x: %d, y: %d, width: %d, height: %d, pal_priority: %X, row: %d, tile addr: %X\n", context->sprite_info_list[context->cur_slot].index, x, context->sprite_info_list[context->cur_slot].y, width, height, pal_priority, row, address); |
35
233c7737c152
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diff
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|
360 for (i=0; i < width && context->sprite_draws; i++, x += dir) { |
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361 --context->sprite_draws; |
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362 context->sprite_draw_list[context->sprite_draws].address = address + i * height * 4; |
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363 context->sprite_draw_list[context->sprite_draws].x_pos = x; |
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364 context->sprite_draw_list[context->sprite_draws].pal_priority = pal_priority; |
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365 context->sprite_draw_list[context->sprite_draws].h_flip = (tileinfo & MAP_BIT_H_FLIP) ? 1 : 0; |
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366 } |
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367 } |
36
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368 if (i < width) { |
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369 context->flags |= FLAG_DOT_OFLOW; |
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370 } |
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371 context->cur_slot--; |
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372 } else { |
34
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373 context->flags |= FLAG_DOT_OFLOW; |
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374 } |
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375 } |
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376 } |
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377 |
427
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378 void write_cram(vdp_context * context, uint16_t address, uint16_t value) |
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379 { |
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380 uint16_t addr = (address/2) & (CRAM_SIZE-1); |
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|
381 context->cram[addr] = value; |
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426
diff
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382 context->colors[addr] = color_map[value & 0xEEE]; |
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426
diff
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|
383 context->colors[addr + CRAM_SIZE] = color_map[(value & 0xEEE) | FBUF_SHADOW]; |
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426
diff
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|
384 context->colors[addr + CRAM_SIZE*2] = color_map[(value & 0xEEE) | FBUF_HILIGHT]; |
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426
diff
changeset
|
385 } |
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426
diff
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|
386 |
473
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diff
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|
387 #define VRAM_READ 0 //0000 |
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|
388 #define VRAM_WRITE 1 //0001 |
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389 //2 would trigger register write 0010 |
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390 #define CRAM_WRITE 3 //0011 |
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391 #define VSRAM_READ 4 //0100 |
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392 #define VSRAM_WRITE 5//0101 |
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|
393 //6 would trigger regsiter write 0110 |
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|
394 //7 is a mystery |
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395 #define CRAM_READ 8 //1000 |
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396 //9 is also a mystery //1001 |
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|
397 //A would trigger register write 1010 |
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398 //B is a mystery 1011 |
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|
399 #define VRAM_READ8 0xC //1100 |
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400 //D is a mystery 1101 |
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|
401 //E would trigger register write 1110 |
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diff
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|
402 //F is a mystery 1111 |
75 | 403 #define DMA_START 0x20 |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
404 |
20
f664eeb55cb4
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|
405 void external_slot(vdp_context * context) |
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|
406 { |
471
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
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470
diff
changeset
|
407 fifo_entry * start = context->fifo + context->fifo_read; |
474
e128e55710bd
Remove read pending stuff, that had been added in an attempt to fix CRAM/VSRAM undefined bit results. Set number of bits actually saved in VSRAM to 11
Mike Pavone <pavone@retrodev.com>
parents:
473
diff
changeset
|
408 /*if (context->flags2 & FLAG2_READ_PENDING) { |
470
541c1ae8abf3
Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
409 context->flags2 &= ~FLAG2_READ_PENDING; |
541c1ae8abf3
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parents:
467
diff
changeset
|
410 context->flags |= FLAG_UNUSED_SLOT; |
541c1ae8abf3
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Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
411 return; |
474
e128e55710bd
Remove read pending stuff, that had been added in an attempt to fix CRAM/VSRAM undefined bit results. Set number of bits actually saved in VSRAM to 11
Mike Pavone <pavone@retrodev.com>
parents:
473
diff
changeset
|
412 }*/ |
471
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
413 if (context->fifo_read >= 0 && start->cycle <= context->cycles) { |
460
788ba843a731
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parents:
454
diff
changeset
|
414 switch (start->cd & 0xF) |
788ba843a731
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parents:
454
diff
changeset
|
415 { |
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454
diff
changeset
|
416 case VRAM_WRITE: |
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454
diff
changeset
|
417 if (start->partial) { |
471
f065769836e8
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Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
418 //printf("VRAM Write: %X to %X at %d (line %d, slot %d)\n", start->value, start->address ^ 1, context->cycles, context->cycles/MCLKS_LINE, (context->cycles%MCLKS_LINE)/16); |
478
2e4a4188cfb0
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents:
477
diff
changeset
|
419 context->vdpmem[start->address ^ 1] = start->partial == 2 ? start->value >> 8 : start->value; |
460
788ba843a731
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454
diff
changeset
|
420 } else { |
471
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Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
421 //printf("VRAM Write High: %X to %X at %d (line %d, slot %d)\n", start->value >> 8, start->address, context->cycles, context->cycles/MCLKS_LINE, (context->cycles%MCLKS_LINE)/16); |
460
788ba843a731
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454
diff
changeset
|
422 context->vdpmem[start->address] = start->value >> 8; |
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diff
changeset
|
423 start->partial = 1; |
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diff
changeset
|
424 //skip auto-increment and removal of entry from fifo |
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454
diff
changeset
|
425 return; |
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diff
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|
426 } |
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diff
changeset
|
427 break; |
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454
diff
changeset
|
428 case CRAM_WRITE: { |
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diff
changeset
|
429 //printf("CRAM Write | %X to %X\n", start->value, (start->address/2) & (CRAM_SIZE-1)); |
479
863e868752cf
Implement funny behavior for DMA fill to CRAM and VSRAM. Return VSRAM address 0 for reads to VSRAM at >= 40
Mike Pavone <pavone@retrodev.com>
parents:
478
diff
changeset
|
430 write_cram(context, start->address, start->partial == 2 ? context->fifo[context->fifo_write].value : start->value); |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
431 break; |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
432 } |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
433 case VSRAM_WRITE: |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
434 if (((start->address/2) & 63) < VSRAM_SIZE) { |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
435 //printf("VSRAM Write: %X to %X\n", start->value, context->address); |
479
863e868752cf
Implement funny behavior for DMA fill to CRAM and VSRAM. Return VSRAM address 0 for reads to VSRAM at >= 40
Mike Pavone <pavone@retrodev.com>
parents:
478
diff
changeset
|
436 context->vsram[(start->address/2) & 63] = start->partial == 2 ? context->fifo[context->fifo_write].value : start->value; |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
437 } |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
438 |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
439 break; |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
440 } |
471
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
441 context->fifo_read = (context->fifo_read+1) & (FIFO_SIZE-1); |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
442 if (context->fifo_read == context->fifo_write) { |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
443 context->fifo_read = -1; |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
444 } |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
445 } else { |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
446 context->flags |= FLAG_UNUSED_SLOT; |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
447 } |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
448 } |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
449 |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
450 void run_dma_src(vdp_context * context, uint32_t slot) |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
451 { |
75 | 452 //TODO: Figure out what happens if CD bit 4 is not set in DMA copy mode |
453 //TODO: Figure out what happens when CD:0-3 is not set to a write mode in DMA operations | |
454 //TODO: Figure out what happens if DMA gets disabled part way through a DMA fill or DMA copy | |
471
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
455 if (context->fifo_write == context->fifo_read) { |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
456 return; |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
457 } |
478
2e4a4188cfb0
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents:
477
diff
changeset
|
458 fifo_entry * cur = NULL; |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
459 switch(context->regs[REG_DMASRC_H] & 0xC0) |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
460 { |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
461 //68K -> VDP |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
462 case 0: |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
463 case 0x40: |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
464 if (!slot || !is_refresh(context, slot-1)) { |
478
2e4a4188cfb0
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents:
477
diff
changeset
|
465 cur = context->fifo + context->fifo_write; |
2e4a4188cfb0
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents:
477
diff
changeset
|
466 cur->cycle = context->cycles + ((context->latched_mode & BIT_H40) ? 16 : 20)*FIFO_LATENCY; |
2e4a4188cfb0
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents:
477
diff
changeset
|
467 cur->address = context->address; |
2e4a4188cfb0
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents:
477
diff
changeset
|
468 cur->value = read_dma_value((context->regs[REG_DMASRC_H] << 16) | (context->regs[REG_DMASRC_M] << 8) | context->regs[REG_DMASRC_L]); |
2e4a4188cfb0
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents:
477
diff
changeset
|
469 cur->cd = context->cd; |
2e4a4188cfb0
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents:
477
diff
changeset
|
470 cur->partial = 0; |
2e4a4188cfb0
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents:
477
diff
changeset
|
471 if (context->fifo_read < 0) { |
2e4a4188cfb0
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents:
477
diff
changeset
|
472 context->fifo_read = context->fifo_write; |
2e4a4188cfb0
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents:
477
diff
changeset
|
473 } |
2e4a4188cfb0
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents:
477
diff
changeset
|
474 context->fifo_write = (context->fifo_write + 1) & (FIFO_SIZE-1); |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
475 } |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
476 break; |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
477 //Copy |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
478 case 0xC0: |
478
2e4a4188cfb0
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents:
477
diff
changeset
|
479 if (context->flags & FLAG_UNUSED_SLOT && context->fifo_read < 0) { |
2e4a4188cfb0
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents:
477
diff
changeset
|
480 //TODO: Fix this to not use the FIFO at all once read-caching is properly implemented |
2e4a4188cfb0
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents:
477
diff
changeset
|
481 context->fifo_read = (context->fifo_write-1) & (FIFO_SIZE-1); |
2e4a4188cfb0
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents:
477
diff
changeset
|
482 cur = context->fifo + context->fifo_read; |
2e4a4188cfb0
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents:
477
diff
changeset
|
483 cur->cycle = context->cycles; |
2e4a4188cfb0
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents:
477
diff
changeset
|
484 cur->address = context->address; |
2e4a4188cfb0
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents:
477
diff
changeset
|
485 cur->partial = 1; |
2e4a4188cfb0
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents:
477
diff
changeset
|
486 cur->value = context->vdpmem[(context->regs[REG_DMASRC_M] << 8) | context->regs[REG_DMASRC_L] ^ 1] | (cur->value & 0xFF00); |
2e4a4188cfb0
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents:
477
diff
changeset
|
487 cur->cd = VRAM_WRITE; |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
488 context->flags &= ~FLAG_UNUSED_SLOT; |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
489 } |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
490 break; |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
491 case 0x80: |
478
2e4a4188cfb0
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents:
477
diff
changeset
|
492 if (context->fifo_read < 0) { |
2e4a4188cfb0
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents:
477
diff
changeset
|
493 context->fifo_read = (context->fifo_write-1) & (FIFO_SIZE-1); |
2e4a4188cfb0
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents:
477
diff
changeset
|
494 cur = context->fifo + context->fifo_read; |
2e4a4188cfb0
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents:
477
diff
changeset
|
495 cur->cycle = context->cycles; |
2e4a4188cfb0
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents:
477
diff
changeset
|
496 cur->address = context->address; |
2e4a4188cfb0
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents:
477
diff
changeset
|
497 cur->partial = 2; |
2e4a4188cfb0
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents:
477
diff
changeset
|
498 } |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
499 break; |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
500 } |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
501 |
478
2e4a4188cfb0
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents:
477
diff
changeset
|
502 if (cur) { |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
503 context->regs[REG_DMASRC_L] += 1; |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
504 if (!context->regs[REG_DMASRC_L]) { |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
505 context->regs[REG_DMASRC_M] += 1; |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
506 } |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
507 context->address += context->regs[REG_AUTOINC]; |
478
2e4a4188cfb0
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents:
477
diff
changeset
|
508 uint16_t dma_len = ((context->regs[REG_DMALEN_H] << 8) | context->regs[REG_DMALEN_L]) - 1; |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
509 context->regs[REG_DMALEN_H] = dma_len >> 8; |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
510 context->regs[REG_DMALEN_L] = dma_len; |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
511 if (!dma_len) { |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
512 //printf("DMA end at cycle %d\n", context->cycles); |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
513 context->flags &= ~FLAG_DMA_RUN; |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
514 context->cd &= 0xF; |
75 | 515 } |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
516 } |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
517 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
518 |
40 | 519 #define WINDOW_RIGHT 0x80 |
520 #define WINDOW_DOWN 0x80 | |
521 | |
25
4d0c20ad815a
Fix vertical scroll value for plane B
Mike Pavone <pavone@retrodev.com>
parents:
24
diff
changeset
|
522 void read_map_scroll(uint16_t column, uint16_t vsram_off, uint32_t line, uint16_t address, uint16_t hscroll_val, vdp_context * context) |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
523 { |
417
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
415
diff
changeset
|
524 uint16_t window_line_shift, v_offset_mask, vscroll_shift; |
414
51ee0f117365
Fix vscroll calculation in double resultion interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
413
diff
changeset
|
525 if (context->double_res) { |
413
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
526 line *= 2; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
527 if (context->framebuf != context->oddbuf) { |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
528 line++; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
529 } |
417
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
415
diff
changeset
|
530 window_line_shift = 4; |
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
415
diff
changeset
|
531 v_offset_mask = 0xF; |
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
415
diff
changeset
|
532 vscroll_shift = 4; |
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
415
diff
changeset
|
533 } else { |
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
415
diff
changeset
|
534 window_line_shift = 3; |
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
415
diff
changeset
|
535 v_offset_mask = 0x7; |
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536 vscroll_shift = 3; |
414
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413
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537 } |
40 | 538 if (!vsram_off) { |
539 uint16_t left_col, right_col; | |
540 if (context->regs[REG_WINDOW_H] & WINDOW_RIGHT) { | |
41
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40
diff
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541 left_col = (context->regs[REG_WINDOW_H] & 0x1F) * 2; |
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diff
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542 right_col = 42; |
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diff
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|
543 } else { |
40 | 544 left_col = 0; |
545 right_col = (context->regs[REG_WINDOW_H] & 0x1F) * 2; | |
546 if (right_col) { | |
547 right_col += 2; | |
548 } | |
549 } | |
41
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40
diff
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|
550 uint16_t top_line, bottom_line; |
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diff
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551 if (context->regs[REG_WINDOW_V] & WINDOW_DOWN) { |
417
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parents:
415
diff
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552 top_line = (context->regs[REG_WINDOW_V] & 0x1F) << window_line_shift; |
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Fix window layer in double res interlace mode
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|
553 bottom_line = context->double_res ? 481 : 241; |
41
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40
diff
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|
554 } else { |
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diff
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|
555 top_line = 0; |
417
acdd6c5240fe
Fix window layer in double res interlace mode
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diff
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|
556 bottom_line = (context->regs[REG_WINDOW_V] & 0x1F) << window_line_shift; |
41
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parents:
40
diff
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|
557 } |
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diff
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|
558 if ((column >= left_col && column < right_col) || (line >= top_line && line < bottom_line)) { |
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diff
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559 uint16_t address = context->regs[REG_WINDOW] << 10; |
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|
560 uint16_t line_offset, offset, mask; |
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40
diff
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|
561 if (context->latched_mode & BIT_H40) { |
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40
diff
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|
562 address &= 0xF000; |
417
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415
diff
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|
563 line_offset = (((line) >> vscroll_shift) * 64 * 2) & 0xFFF; |
41
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|
564 mask = 0x7F; |
450
3758bcdae5de
Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty
Mike Pavone <pavone@retrodev.com>
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438
diff
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|
565 |
41
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|
566 } else { |
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|
567 address &= 0xF800; |
417
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changeset
|
568 line_offset = (((line) >> vscroll_shift) * 32 * 2) & 0xFFF; |
41
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|
569 mask = 0x3F; |
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diff
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|
570 } |
417
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415
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571 if (context->double_res) { |
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parents:
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572 mask <<= 1; |
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573 mask |= 1; |
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Mike Pavone <pavone@retrodev.com>
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|
574 } |
42
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Fix bug in tile address masking. Remove some debug code from window plane.
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41
diff
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|
575 offset = address + line_offset + (((column - 2) * 2) & mask); |
41
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|
576 context->col_1 = (context->vdpmem[offset] << 8) | context->vdpmem[offset+1]; |
54
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parents:
43
diff
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|
577 //printf("Window | top: %d, bot: %d, left: %d, right: %d, base: %X, line: %X offset: %X, tile: %X, reg: %X\n", top_line, bottom_line, left_col, right_col, address, line_offset, offset, ((context->col_1 & 0x3FF) << 5), context->regs[REG_WINDOW]); |
42
6653e67a6811
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parents:
41
diff
changeset
|
578 offset = address + line_offset + (((column - 1) * 2) & mask); |
41
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diff
changeset
|
579 context->col_2 = (context->vdpmem[offset] << 8) | context->vdpmem[offset+1]; |
417
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diff
changeset
|
580 context->v_offset = (line) & v_offset_mask; |
41
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parents:
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diff
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|
581 context->flags |= FLAG_WINDOW; |
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parents:
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diff
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|
582 return; |
40 | 583 } |
584 context->flags &= ~FLAG_WINDOW; | |
585 } | |
20
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586 uint16_t vscroll; |
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diff
changeset
|
587 switch(context->regs[REG_SCROLL] & 0x30) |
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diff
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|
588 { |
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diff
changeset
|
589 case 0: |
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diff
changeset
|
590 vscroll = 0xFF; |
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parents:
diff
changeset
|
591 break; |
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|
592 case 0x10: |
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593 vscroll = 0x1FF; |
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594 break; |
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595 case 0x20: |
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596 //TODO: Verify this behavior |
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597 vscroll = 0; |
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598 break; |
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599 case 0x30: |
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600 vscroll = 0x3FF; |
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601 break; |
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602 } |
414
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diff
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|
603 if (context->double_res) { |
413
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604 vscroll <<= 1; |
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605 vscroll |= 1; |
414
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diff
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|
606 } |
454
e9b6fe443bf2
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Mike Pavone <pavone@retrodev.com>
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453
diff
changeset
|
607 vscroll &= (context->vsram[(context->regs[REG_MODE_3] & BIT_VSCROLL ? (column-2)&63 : 0) + vsram_off] + line); |
414
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parents:
413
diff
changeset
|
608 context->v_offset = vscroll & v_offset_mask; |
26
a7c2b92d8056
Fix management of context->sprite_draws so the sprite layer only draws when it should
Mike Pavone <pavone@retrodev.com>
parents:
25
diff
changeset
|
609 //printf("%s | line %d, vsram: %d, vscroll: %d, v_offset: %d\n",(vsram_off ? "B" : "A"), line, context->vsram[context->regs[REG_MODE_3] & 0x4 ? column : 0], vscroll, context->v_offset); |
414
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diff
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|
610 vscroll >>= vscroll_shift; |
20
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diff
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|
611 uint16_t hscroll_mask; |
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parents:
diff
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|
612 uint16_t v_mul; |
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|
613 switch(context->regs[REG_SCROLL] & 0x3) |
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diff
changeset
|
614 { |
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diff
changeset
|
615 case 0: |
108
1a551a85cb06
Fix horizontal mask values for scroll plane map address calculation
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87
diff
changeset
|
616 hscroll_mask = 0x1F; |
20
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diff
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617 v_mul = 64; |
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changeset
|
618 break; |
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diff
changeset
|
619 case 0x1: |
39
3c69319269ef
Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should
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38
diff
changeset
|
620 hscroll_mask = 0x3F; |
20
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diff
changeset
|
621 v_mul = 128; |
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diff
changeset
|
622 break; |
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changeset
|
623 case 0x2: |
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diff
changeset
|
624 //TODO: Verify this behavior |
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diff
changeset
|
625 hscroll_mask = 0; |
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changeset
|
626 v_mul = 0; |
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diff
changeset
|
627 break; |
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diff
changeset
|
628 case 0x3: |
108
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Fix horizontal mask values for scroll plane map address calculation
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parents:
87
diff
changeset
|
629 hscroll_mask = 0x7F; |
20
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diff
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|
630 v_mul = 256; |
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diff
changeset
|
631 break; |
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diff
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|
632 } |
28 | 633 uint16_t hscroll, offset; |
634 for (int i = 0; i < 2; i++) { | |
39
3c69319269ef
Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should
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parents:
38
diff
changeset
|
635 hscroll = (column - 2 + i - ((hscroll_val/8) & 0xFFFE)) & hscroll_mask; |
3c69319269ef
Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should
Mike Pavone <pavone@retrodev.com>
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38
diff
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|
636 offset = address + ((vscroll * v_mul + hscroll*2) & 0x1FFF); |
3c69319269ef
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38
diff
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|
637 //printf("%s | line: %d, col: %d, x: %d, hs_mask %X, scr reg: %X, tbl addr: %X\n", (vsram_off ? "B" : "A"), line, (column-2+i), hscroll, hscroll_mask, context->regs[REG_SCROLL], offset); |
28 | 638 uint16_t col_val = (context->vdpmem[offset] << 8) | context->vdpmem[offset+1]; |
639 if (i) { | |
640 context->col_2 = col_val; | |
641 } else { | |
642 context->col_1 = col_val; | |
643 } | |
644 } | |
20
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diff
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|
645 } |
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diff
changeset
|
646 |
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diff
changeset
|
647 void read_map_scroll_a(uint16_t column, uint32_t line, vdp_context * context) |
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diff
changeset
|
648 { |
25
4d0c20ad815a
Fix vertical scroll value for plane B
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24
diff
changeset
|
649 read_map_scroll(column, 0, line, (context->regs[REG_SCROLL_A] & 0x38) << 10, context->hscroll_a, context); |
20
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|
650 } |
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diff
changeset
|
651 |
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changeset
|
652 void read_map_scroll_b(uint16_t column, uint32_t line, vdp_context * context) |
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diff
changeset
|
653 { |
25
4d0c20ad815a
Fix vertical scroll value for plane B
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24
diff
changeset
|
654 read_map_scroll(column, 1, line, (context->regs[REG_SCROLL_B] & 0x7) << 13, context->hscroll_b, context); |
20
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diff
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|
655 } |
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diff
changeset
|
656 |
436
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
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427
diff
changeset
|
657 void render_map(uint16_t col, uint8_t * tmp_buf, uint8_t offset, vdp_context * context) |
20
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|
658 { |
413
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|
659 uint16_t address; |
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diff
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|
660 uint8_t shift, add; |
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|
661 if (context->double_res) { |
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diff
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|
662 address = ((col & 0x3FF) << 6); |
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|
663 shift = 1; |
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|
664 add = context->framebuf != context->oddbuf ? 1 : 0; |
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665 } else { |
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|
666 address = ((col & 0x7FF) << 5); |
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|
667 shift = 0; |
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|
668 add = 0; |
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diff
changeset
|
669 } |
20
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Mostly broken VDP core and savestate viewer
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parents:
diff
changeset
|
670 if (col & MAP_BIT_V_FLIP) { |
414
51ee0f117365
Fix vscroll calculation in double resultion interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
413
diff
changeset
|
671 address += 28 - 4 * context->v_offset/*((context->v_offset << shift) + add)*/; |
20
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Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
672 } else { |
414
51ee0f117365
Fix vscroll calculation in double resultion interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
413
diff
changeset
|
673 address += 4 * context->v_offset/*((context->v_offset << shift) + add)*/; |
20
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parents:
diff
changeset
|
674 } |
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parents:
diff
changeset
|
675 uint16_t pal_priority = (col >> 9) & 0x70; |
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parents:
diff
changeset
|
676 int32_t dir; |
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Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
677 if (col & MAP_BIT_H_FLIP) { |
436
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Implement the scroll ring buffer properly without memcpy
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427
diff
changeset
|
678 offset += 7; |
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
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parents:
427
diff
changeset
|
679 offset &= SCROLL_BUFFER_MASK; |
20
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parents:
diff
changeset
|
680 dir = -1; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
681 } else { |
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Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
682 dir = 1; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
683 } |
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Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
684 for (uint32_t i=0; i < 4; i++, address++) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
685 { |
436
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
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427
diff
changeset
|
686 tmp_buf[offset] = pal_priority | (context->vdpmem[address] >> 4); |
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
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parents:
427
diff
changeset
|
687 offset += dir; |
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
688 offset &= SCROLL_BUFFER_MASK; |
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
689 tmp_buf[offset] = pal_priority | (context->vdpmem[address] & 0xF); |
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
690 offset += dir; |
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
691 offset &= SCROLL_BUFFER_MASK; |
20
f664eeb55cb4
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
692 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
693 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
694 |
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Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
695 void render_map_1(vdp_context * context) |
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Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
696 { |
436
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
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427
diff
changeset
|
697 render_map(context->col_1, context->tmp_buf_a, context->buf_a_off, context); |
20
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
698 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
699 |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
700 void render_map_2(vdp_context * context) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
701 { |
436
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
702 render_map(context->col_2, context->tmp_buf_a, context->buf_a_off+8, context); |
20
f664eeb55cb4
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
703 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
704 |
f664eeb55cb4
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
705 void render_map_3(vdp_context * context) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
706 { |
436
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
707 render_map(context->col_1, context->tmp_buf_b, context->buf_b_off, context); |
20
f664eeb55cb4
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
708 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
709 |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
710 void render_map_output(uint32_t line, int32_t col, vdp_context * context) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
711 { |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
712 if (line >= 240) { |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
713 return; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
714 } |
436
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
715 render_map(context->col_2, context->tmp_buf_b, context->buf_b_off+8, context); |
426
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
716 uint16_t *dst; |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
717 uint32_t *dst32; |
436
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
718 uint8_t *sprite_buf, *plane_a, *plane_b; |
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
719 int plane_a_off, plane_b_off; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
720 if (col) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
721 { |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
722 col-=2; |
426
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
723 if (context->b32) { |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
724 dst32 = context->framebuf; |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
725 dst32 += line * 320 + col * 8; |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
726 } else { |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
727 dst = context->framebuf; |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
728 dst += line * 320 + col * 8; |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
729 } |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
730 sprite_buf = context->linebuf + col * 8; |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
731 uint8_t a_src, src; |
40 | 732 if (context->flags & FLAG_WINDOW) { |
436
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
733 plane_a_off = context->buf_a_off; |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
734 a_src = DBG_SRC_W; |
40 | 735 } else { |
436
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
736 plane_a_off = context->buf_a_off - (context->hscroll_a & 0xF); |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
737 a_src = DBG_SRC_A; |
40 | 738 } |
436
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
739 plane_b_off = context->buf_b_off - (context->hscroll_b & 0xF); |
30 | 740 //printf("A | tmp_buf offset: %d\n", 8 - (context->hscroll_a & 0x7)); |
450
3758bcdae5de
Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty
Mike Pavone <pavone@retrodev.com>
parents:
438
diff
changeset
|
741 |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
742 if (context->regs[REG_MODE_4] & BIT_HILIGHT) { |
436
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
743 for (int i = 0; i < 16; ++plane_a_off, ++plane_b_off, ++sprite_buf, ++i) { |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
744 uint8_t pixel; |
436
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
745 plane_a = context->tmp_buf_a + (plane_a_off & SCROLL_BUFFER_MASK); |
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
746 plane_b = context->tmp_buf_b + (plane_b_off & SCROLL_BUFFER_MASK); |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
747 uint32_t * colors = context->colors; |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
748 src = 0; |
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
749 uint8_t sprite_color = *sprite_buf & 0x3F; |
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
750 if (sprite_color == 0x3E || sprite_color == 0x3F) { |
232
54873acb982e
Shadow and higlight operators were switched
Mike Pavone <pavone@retrodev.com>
parents:
230
diff
changeset
|
751 if (sprite_color == 0x3F) { |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
752 colors += CRAM_SIZE; |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
753 src = DBG_SHADOW; |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
754 } else { |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
755 colors += CRAM_SIZE*2; |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
756 src = DBG_HILIGHT; |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
757 } |
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
758 if (*plane_a & BUF_BIT_PRIORITY && *plane_a & 0xF) { |
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
759 pixel = *plane_a; |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
760 src |= a_src; |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
761 } else if (*plane_b & BUF_BIT_PRIORITY && *plane_b & 0xF) { |
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
762 pixel = *plane_b; |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
763 src |= DBG_SRC_B; |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
764 } else if (*plane_a & 0xF) { |
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
765 pixel = *plane_a; |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
766 src |= a_src; |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
767 } else if (*plane_b & 0xF){ |
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
768 pixel = *plane_b; |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
769 src |= DBG_SRC_B; |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
770 } else { |
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
771 pixel = context->regs[REG_BG_COLOR] & 0x3F; |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
772 src |= DBG_SRC_BG; |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
773 } |
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
774 } else { |
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
775 if (*sprite_buf & BUF_BIT_PRIORITY && *sprite_buf & 0xF) { |
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
776 pixel = *sprite_buf; |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
777 src = DBG_SRC_S; |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
778 } else if (*plane_a & BUF_BIT_PRIORITY && *plane_a & 0xF) { |
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
779 pixel = *plane_a; |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
780 src = a_src; |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
781 } else if (*plane_b & BUF_BIT_PRIORITY && *plane_b & 0xF) { |
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
782 pixel = *plane_b; |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
783 src = DBG_SRC_B; |
233
9d10669f2579
Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
parents:
232
diff
changeset
|
784 } else { |
9d10669f2579
Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
parents:
232
diff
changeset
|
785 if (!(*plane_a & BUF_BIT_PRIORITY || *plane_a & BUF_BIT_PRIORITY)) { |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
786 colors += CRAM_SIZE; |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
787 src = DBG_SHADOW; |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
788 } |
233
9d10669f2579
Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
parents:
232
diff
changeset
|
789 if (*sprite_buf & 0xF) { |
9d10669f2579
Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
parents:
232
diff
changeset
|
790 pixel = *sprite_buf; |
9d10669f2579
Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
parents:
232
diff
changeset
|
791 if (*sprite_buf & 0xF == 0xE) { |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
792 colors = context->colors; |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
793 src = DBG_SRC_S; |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
794 } else { |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
795 src |= DBG_SRC_S; |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
796 } |
233
9d10669f2579
Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
parents:
232
diff
changeset
|
797 } else if (*plane_a & 0xF) { |
9d10669f2579
Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
parents:
232
diff
changeset
|
798 pixel = *plane_a; |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
799 src |= a_src; |
233
9d10669f2579
Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
parents:
232
diff
changeset
|
800 } else if (*plane_b & 0xF){ |
9d10669f2579
Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
parents:
232
diff
changeset
|
801 pixel = *plane_b; |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
802 src |= DBG_SRC_B; |
233
9d10669f2579
Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
parents:
232
diff
changeset
|
803 } else { |
9d10669f2579
Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
parents:
232
diff
changeset
|
804 pixel = context->regs[REG_BG_COLOR] & 0x3F; |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
805 src |= DBG_SRC_BG; |
233
9d10669f2579
Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
parents:
232
diff
changeset
|
806 } |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
807 } |
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
808 } |
426
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
809 pixel &= 0x3F; |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
810 uint32_t outpixel; |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
811 if (context->debug) { |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
812 outpixel = context->debugcolors[src]; |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
813 } else { |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
814 outpixel = colors[pixel]; |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
815 } |
426
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
816 if (context->b32) { |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
817 *(dst32++) = outpixel; |
426
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
818 } else { |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
819 *(dst++) = outpixel; |
426
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
820 } |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
821 //*dst = (context->cram[pixel & 0x3F] & 0xEEE) | ((pixel & BUF_BIT_PRIORITY) ? FBUF_BIT_PRIORITY : 0) | src; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
822 } |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
823 } else { |
436
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
824 for (int i = 0; i < 16; ++plane_a_off, ++plane_b_off, ++sprite_buf, ++i) { |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
825 uint8_t pixel; |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
826 src = 0; |
436
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
827 plane_a = context->tmp_buf_a + (plane_a_off & SCROLL_BUFFER_MASK); |
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
828 plane_b = context->tmp_buf_b + (plane_b_off & SCROLL_BUFFER_MASK); |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
829 if (*sprite_buf & BUF_BIT_PRIORITY && *sprite_buf & 0xF) { |
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
830 pixel = *sprite_buf; |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
831 src = DBG_SRC_S; |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
832 } else if (*plane_a & BUF_BIT_PRIORITY && *plane_a & 0xF) { |
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
833 pixel = *plane_a; |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
834 src = a_src; |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
835 } else if (*plane_b & BUF_BIT_PRIORITY && *plane_b & 0xF) { |
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
836 pixel = *plane_b; |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
837 src = DBG_SRC_B; |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
838 } else if (*sprite_buf & 0xF) { |
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
839 pixel = *sprite_buf; |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
840 src = DBG_SRC_S; |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
841 } else if (*plane_a & 0xF) { |
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
842 pixel = *plane_a; |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
843 src = a_src; |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
844 } else if (*plane_b & 0xF){ |
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
845 pixel = *plane_b; |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
846 src = DBG_SRC_B; |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
847 } else { |
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
848 pixel = context->regs[REG_BG_COLOR] & 0x3F; |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
849 src = DBG_SRC_BG; |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
850 } |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
851 uint32_t outpixel; |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
852 if (context->debug) { |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
853 outpixel = context->debugcolors[src]; |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
854 } else { |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
855 outpixel = context->colors[pixel & 0x3F]; |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
856 } |
426
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
857 if (context->b32) { |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
858 *(dst32++) = outpixel; |
426
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
859 } else { |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
860 *(dst++) = outpixel; |
426
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
861 } |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
862 //*dst = (context->cram[pixel & 0x3F] & 0xEEE) | ((pixel & BUF_BIT_PRIORITY) ? FBUF_BIT_PRIORITY : 0) | src; |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
863 } |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
864 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
865 } else { |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
866 //dst = context->framebuf + line * 320; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
867 //sprite_buf = context->linebuf + col * 8; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
868 //plane_a = context->tmp_buf_a + 16 - (context->hscroll_a & 0x7); |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
869 //plane_b = context->tmp_buf_b + 16 - (context->hscroll_b & 0x7); |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
870 //end = dst + 8; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
871 } |
436
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
872 context->buf_a_off = (context->buf_a_off + SCROLL_BUFFER_DRAW) & SCROLL_BUFFER_MASK; |
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
873 context->buf_b_off = (context->buf_b_off + SCROLL_BUFFER_DRAW) & SCROLL_BUFFER_MASK; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
874 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
875 |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
876 #define COLUMN_RENDER_BLOCK(column, startcyc) \ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
877 case startcyc:\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
878 read_map_scroll_a(column, line, context);\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
879 break;\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
880 case (startcyc+1):\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
881 external_slot(context);\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
882 break;\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
883 case (startcyc+2):\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
884 render_map_1(context);\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
885 break;\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
886 case (startcyc+3):\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
887 render_map_2(context);\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
888 break;\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
889 case (startcyc+4):\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
890 read_map_scroll_b(column, line, context);\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
891 break;\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
892 case (startcyc+5):\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
893 read_sprite_x(line, context);\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
894 break;\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
895 case (startcyc+6):\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
896 render_map_3(context);\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
897 break;\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
898 case (startcyc+7):\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
899 render_map_output(line, column, context);\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
900 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
901 |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
902 #define COLUMN_RENDER_BLOCK_REFRESH(column, startcyc) \ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
903 case startcyc:\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
904 read_map_scroll_a(column, line, context);\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
905 break;\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
906 case (startcyc+1):\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
907 break;\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
908 case (startcyc+2):\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
909 render_map_1(context);\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
910 break;\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
911 case (startcyc+3):\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
912 render_map_2(context);\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
913 break;\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
914 case (startcyc+4):\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
915 read_map_scroll_b(column, line, context);\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
916 break;\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
917 case (startcyc+5):\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
918 read_sprite_x(line, context);\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
919 break;\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
920 case (startcyc+6):\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
921 render_map_3(context);\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
922 break;\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
923 case (startcyc+7):\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
924 render_map_output(line, column, context);\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
925 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
926 |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
927 void vdp_h40(uint32_t line, uint32_t linecyc, vdp_context * context) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
928 { |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
929 uint16_t address; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
930 uint32_t mask; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
931 switch(linecyc) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
932 { |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
933 //sprite render to line buffer starts |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
934 case 0: |
26
a7c2b92d8056
Fix management of context->sprite_draws so the sprite layer only draws when it should
Mike Pavone <pavone@retrodev.com>
parents:
25
diff
changeset
|
935 context->cur_slot = MAX_DRAWS-1; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
936 memset(context->linebuf, 0, LINEBUF_SIZE); |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
937 case 1: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
938 case 2: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
939 case 3: |
329
fd5f6577db9b
Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents:
328
diff
changeset
|
940 if (line == 0xFF) { |
fd5f6577db9b
Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents:
328
diff
changeset
|
941 external_slot(context); |
fd5f6577db9b
Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents:
328
diff
changeset
|
942 } else { |
fd5f6577db9b
Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents:
328
diff
changeset
|
943 render_sprite_cells(context); |
fd5f6577db9b
Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents:
328
diff
changeset
|
944 } |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
945 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
946 //sprite attribute table scan starts |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
947 case 4: |
21
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
948 render_sprite_cells( context); |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
949 context->sprite_index = 0x80; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
950 context->slot_counter = MAX_SPRITES_LINE; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
951 scan_sprite_table(line, context); |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
952 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
953 case 5: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
954 case 6: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
955 case 7: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
956 case 8: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
957 case 9: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
958 case 10: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
959 case 11: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
960 case 12: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
961 case 13: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
962 case 14: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
963 case 15: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
964 case 16: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
965 case 17: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
966 case 18: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
967 case 19: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
968 case 20: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
969 //!HSYNC asserted |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
970 case 21: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
971 case 22: |
21
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
972 render_sprite_cells(context); |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
973 scan_sprite_table(line, context); |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
974 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
975 case 23: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
976 external_slot(context); |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
977 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
978 case 24: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
979 case 25: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
980 case 26: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
981 case 27: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
982 case 28: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
983 case 29: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
984 case 30: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
985 case 31: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
986 case 32: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
987 case 33: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
988 case 34: |
21
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
989 render_sprite_cells(context); |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
990 scan_sprite_table(line, context); |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
991 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
992 case 35: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
993 address = (context->regs[REG_HSCROLL] & 0x3F) << 10; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
994 mask = 0; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
995 if (context->regs[REG_MODE_3] & 0x2) { |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
996 mask |= 0xF8; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
997 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
998 if (context->regs[REG_MODE_3] & 0x1) { |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
999 mask |= 0x7; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1000 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1001 line &= mask; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1002 address += line * 4; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1003 context->hscroll_a = context->vdpmem[address] << 8 | context->vdpmem[address+1]; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1004 context->hscroll_b = context->vdpmem[address+2] << 8 | context->vdpmem[address+3]; |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1005 //printf("%d: HScroll A: %d, HScroll B: %d\n", line, context->hscroll_a, context->hscroll_b); |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1006 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1007 case 36: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1008 //!HSYNC high |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1009 case 37: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1010 case 38: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1011 case 39: |
21
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
1012 render_sprite_cells(context); |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1013 scan_sprite_table(line, context); |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1014 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1015 case 40: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1016 read_map_scroll_a(0, line, context); |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1017 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1018 case 41: |
21
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
1019 render_sprite_cells(context); |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1020 scan_sprite_table(line, context); |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1021 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1022 case 42: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1023 render_map_1(context); |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1024 scan_sprite_table(line, context);//Just a guess |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1025 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1026 case 43: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1027 render_map_2(context); |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1028 scan_sprite_table(line, context);//Just a guess |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1029 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1030 case 44: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1031 read_map_scroll_b(0, line, context); |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1032 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1033 case 45: |
21
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
1034 render_sprite_cells(context); |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1035 scan_sprite_table(line, context); |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1036 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1037 case 46: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1038 render_map_3(context); |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1039 scan_sprite_table(line, context);//Just a guess |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1040 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1041 case 47: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1042 render_map_output(line, 0, context); |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1043 scan_sprite_table(line, context);//Just a guess |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1044 //reverse context slot counter so it counts the number of sprite slots |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1045 //filled rather than the number of available slots |
21
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
1046 //context->slot_counter = MAX_SPRITES_LINE - context->slot_counter; |
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
1047 context->cur_slot = MAX_SPRITES_LINE-1; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1048 context->sprite_draws = MAX_DRAWS; |
36
04672c060062
Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents:
35
diff
changeset
|
1049 context->flags &= (~FLAG_CAN_MASK & ~FLAG_MASKED); |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1050 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1051 COLUMN_RENDER_BLOCK(2, 48) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1052 COLUMN_RENDER_BLOCK(4, 56) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1053 COLUMN_RENDER_BLOCK(6, 64) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1054 COLUMN_RENDER_BLOCK_REFRESH(8, 72) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1055 COLUMN_RENDER_BLOCK(10, 80) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1056 COLUMN_RENDER_BLOCK(12, 88) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1057 COLUMN_RENDER_BLOCK(14, 96) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1058 COLUMN_RENDER_BLOCK_REFRESH(16, 104) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1059 COLUMN_RENDER_BLOCK(18, 112) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1060 COLUMN_RENDER_BLOCK(20, 120) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1061 COLUMN_RENDER_BLOCK(22, 128) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1062 COLUMN_RENDER_BLOCK_REFRESH(24, 136) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1063 COLUMN_RENDER_BLOCK(26, 144) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1064 COLUMN_RENDER_BLOCK(28, 152) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1065 COLUMN_RENDER_BLOCK(30, 160) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1066 COLUMN_RENDER_BLOCK_REFRESH(32, 168) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1067 COLUMN_RENDER_BLOCK(34, 176) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1068 COLUMN_RENDER_BLOCK(36, 184) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1069 COLUMN_RENDER_BLOCK(38, 192) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1070 COLUMN_RENDER_BLOCK_REFRESH(40, 200) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1071 case 208: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1072 case 209: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1073 external_slot(context); |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1074 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1075 default: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1076 //leftovers from HSYNC clock change nonsense |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1077 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1078 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1079 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1080 |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1081 void vdp_h32(uint32_t line, uint32_t linecyc, vdp_context * context) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1082 { |
37 | 1083 uint16_t address; |
1084 uint32_t mask; | |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1085 switch(linecyc) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1086 { |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1087 //sprite render to line buffer starts |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1088 case 0: |
37 | 1089 context->cur_slot = MAX_DRAWS_H32-1; |
1090 memset(context->linebuf, 0, LINEBUF_SIZE); | |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1091 case 1: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1092 case 2: |
37 | 1093 case 3: |
329
fd5f6577db9b
Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents:
328
diff
changeset
|
1094 if (line == 0xFF) { |
fd5f6577db9b
Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents:
328
diff
changeset
|
1095 external_slot(context); |
fd5f6577db9b
Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents:
328
diff
changeset
|
1096 } else { |
fd5f6577db9b
Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents:
328
diff
changeset
|
1097 render_sprite_cells(context); |
fd5f6577db9b
Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents:
328
diff
changeset
|
1098 } |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1099 break; |
37 | 1100 //sprite attribute table scan starts |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1101 case 4: |
37 | 1102 render_sprite_cells( context); |
1103 context->sprite_index = 0x80; | |
1104 context->slot_counter = MAX_SPRITES_LINE_H32; | |
1105 scan_sprite_table(line, context); | |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1106 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1107 case 5: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1108 case 6: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1109 case 7: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1110 case 8: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1111 case 9: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1112 case 10: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1113 case 11: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1114 case 12: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1115 case 13: |
37 | 1116 render_sprite_cells(context); |
1117 scan_sprite_table(line, context); | |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1118 case 14: |
37 | 1119 external_slot(context); |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1120 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1121 case 15: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1122 case 16: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1123 case 17: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1124 case 18: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1125 case 19: |
37 | 1126 //HSYNC start |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1127 case 20: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1128 case 21: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1129 case 22: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1130 case 23: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1131 case 24: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1132 case 25: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1133 case 26: |
37 | 1134 render_sprite_cells(context); |
1135 scan_sprite_table(line, context); | |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1136 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1137 case 27: |
37 | 1138 external_slot(context); |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1139 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1140 case 28: |
37 | 1141 address = (context->regs[REG_HSCROLL] & 0x3F) << 10; |
1142 mask = 0; | |
1143 if (context->regs[REG_MODE_3] & 0x2) { | |
1144 mask |= 0xF8; | |
1145 } | |
1146 if (context->regs[REG_MODE_3] & 0x1) { | |
1147 mask |= 0x7; | |
1148 } | |
1149 line &= mask; | |
1150 address += line * 4; | |
1151 context->hscroll_a = context->vdpmem[address] << 8 | context->vdpmem[address+1]; | |
1152 context->hscroll_b = context->vdpmem[address+2] << 8 | context->vdpmem[address+3]; | |
1153 //printf("%d: HScroll A: %d, HScroll B: %d\n", line, context->hscroll_a, context->hscroll_b); | |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1154 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1155 case 29: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1156 case 30: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1157 case 31: |
37 | 1158 case 32: |
1159 render_sprite_cells(context); | |
1160 scan_sprite_table(line, context); | |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1161 break; |
37 | 1162 //!HSYNC high |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1163 case 33: |
37 | 1164 read_map_scroll_a(0, line, context); |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1165 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1166 case 34: |
37 | 1167 render_sprite_cells(context); |
1168 scan_sprite_table(line, context); | |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1169 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1170 case 35: |
37 | 1171 render_map_1(context); |
1172 scan_sprite_table(line, context);//Just a guess | |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1173 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1174 case 36: |
37 | 1175 render_map_2(context); |
1176 scan_sprite_table(line, context);//Just a guess | |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1177 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1178 case 37: |
37 | 1179 read_map_scroll_b(0, line, context); |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1180 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1181 case 38: |
37 | 1182 render_sprite_cells(context); |
1183 scan_sprite_table(line, context); | |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1184 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1185 case 39: |
37 | 1186 render_map_3(context); |
1187 scan_sprite_table(line, context);//Just a guess | |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1188 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1189 case 40: |
37 | 1190 render_map_output(line, 0, context); |
1191 scan_sprite_table(line, context);//Just a guess | |
1192 //reverse context slot counter so it counts the number of sprite slots | |
1193 //filled rather than the number of available slots | |
1194 //context->slot_counter = MAX_SPRITES_LINE - context->slot_counter; | |
1195 context->cur_slot = MAX_SPRITES_LINE_H32-1; | |
1196 context->sprite_draws = MAX_DRAWS_H32; | |
1197 context->flags &= (~FLAG_CAN_MASK & ~FLAG_MASKED); | |
20
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parents:
diff
changeset
|
1198 break; |
37 | 1199 COLUMN_RENDER_BLOCK(2, 41) |
1200 COLUMN_RENDER_BLOCK(4, 49) | |
1201 COLUMN_RENDER_BLOCK(6, 57) | |
1202 COLUMN_RENDER_BLOCK_REFRESH(8, 65) | |
1203 COLUMN_RENDER_BLOCK(10, 73) | |
1204 COLUMN_RENDER_BLOCK(12, 81) | |
1205 COLUMN_RENDER_BLOCK(14, 89) | |
1206 COLUMN_RENDER_BLOCK_REFRESH(16, 97) | |
1207 COLUMN_RENDER_BLOCK(18, 105) | |
1208 COLUMN_RENDER_BLOCK(20, 113) | |
1209 COLUMN_RENDER_BLOCK(22, 121) | |
1210 COLUMN_RENDER_BLOCK_REFRESH(24, 129) | |
1211 COLUMN_RENDER_BLOCK(26, 137) | |
1212 COLUMN_RENDER_BLOCK(28, 145) | |
1213 COLUMN_RENDER_BLOCK(30, 153) | |
1214 COLUMN_RENDER_BLOCK_REFRESH(32, 161) | |
20
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diff
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|
1215 case 169: |
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diff
changeset
|
1216 case 170: |
37 | 1217 external_slot(context); |
20
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|
1218 break; |
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Mike Pavone <pavone@retrodev.com>
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|
1219 } |
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Mostly broken VDP core and savestate viewer
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|
1220 } |
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Mostly broken VDP core and savestate viewer
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|
1221 void latch_mode(vdp_context * context) |
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|
1222 { |
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|
1223 context->latched_mode = (context->regs[REG_MODE_4] & 0x81) | (context->regs[REG_MODE_2] & BIT_PAL); |
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diff
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|
1224 } |
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|
1225 |
330
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1226 void check_render_bg(vdp_context * context, int32_t line, uint32_t slot) |
54
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diff
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|
1227 { |
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43
diff
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|
1228 if (line > 0) { |
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Get Flavio's color bar demo kind of sort of working
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43
diff
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|
1229 line -= 1; |
426
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Mike Pavone <pavone@retrodev.com>
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424
diff
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|
1230 int starti = -1; |
54
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43
diff
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|
1231 if (context->latched_mode & BIT_H40) { |
462
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Fix timing of backdrop rendering when the display is turned off
Mike Pavone <pavone@retrodev.com>
parents:
461
diff
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|
1232 if (slot >= 55 && slot < 210) { |
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Fix timing of backdrop rendering when the display is turned off
Mike Pavone <pavone@retrodev.com>
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461
diff
changeset
|
1233 uint32_t x = (slot-55)*2; |
426
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
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424
diff
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|
1234 starti = line * 320 + x; |
462
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Fix timing of backdrop rendering when the display is turned off
Mike Pavone <pavone@retrodev.com>
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461
diff
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|
1235 } else if (slot < 5) { |
5677c053edd6
Fix timing of backdrop rendering when the display is turned off
Mike Pavone <pavone@retrodev.com>
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461
diff
changeset
|
1236 uint32_t x = (slot + 155)*2; |
5677c053edd6
Fix timing of backdrop rendering when the display is turned off
Mike Pavone <pavone@retrodev.com>
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461
diff
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|
1237 starti = (line-1)*320 + x; |
54
3b79cbcf6846
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Mike Pavone <pavone@retrodev.com>
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43
diff
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|
1238 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
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43
diff
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|
1239 } else { |
462
5677c053edd6
Fix timing of backdrop rendering when the display is turned off
Mike Pavone <pavone@retrodev.com>
parents:
461
diff
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|
1240 if (slot >= 48 && slot < 171) { |
5677c053edd6
Fix timing of backdrop rendering when the display is turned off
Mike Pavone <pavone@retrodev.com>
parents:
461
diff
changeset
|
1241 uint32_t x = (slot-48)*2; |
426
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
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424
diff
changeset
|
1242 starti = line * 320 + x; |
462
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Mike Pavone <pavone@retrodev.com>
parents:
461
diff
changeset
|
1243 } else if (slot < 5) { |
5677c053edd6
Fix timing of backdrop rendering when the display is turned off
Mike Pavone <pavone@retrodev.com>
parents:
461
diff
changeset
|
1244 uint32_t x = (slot + 123)*2; |
5677c053edd6
Fix timing of backdrop rendering when the display is turned off
Mike Pavone <pavone@retrodev.com>
parents:
461
diff
changeset
|
1245 starti = (line-1)*320 + x; |
54
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parents:
43
diff
changeset
|
1246 } |
3b79cbcf6846
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Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1247 } |
426
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
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424
diff
changeset
|
1248 if (starti >= 0) { |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
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424
diff
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|
1249 if (context->b32) { |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
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424
diff
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|
1250 uint32_t color = context->colors[context->regs[REG_BG_COLOR] & 0x3F]; |
add9e2f5c0e3
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Mike Pavone <pavone@retrodev.com>
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424
diff
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|
1251 uint32_t * start = context->framebuf; |
add9e2f5c0e3
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Mike Pavone <pavone@retrodev.com>
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424
diff
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|
1252 start += starti; |
add9e2f5c0e3
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Mike Pavone <pavone@retrodev.com>
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424
diff
changeset
|
1253 for (int i = 0; i < 2; i++) { |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
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424
diff
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|
1254 *(start++) = color; |
add9e2f5c0e3
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Mike Pavone <pavone@retrodev.com>
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424
diff
changeset
|
1255 } |
add9e2f5c0e3
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Mike Pavone <pavone@retrodev.com>
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424
diff
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|
1256 } else { |
add9e2f5c0e3
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Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
1257 uint16_t color = context->colors[context->regs[REG_BG_COLOR] & 0x3F]; |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
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424
diff
changeset
|
1258 uint16_t * start = context->framebuf; |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
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424
diff
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|
1259 start += starti; |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
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424
diff
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|
1260 for (int i = 0; i < 2; i++) { |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
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424
diff
changeset
|
1261 *(start++) = color; |
add9e2f5c0e3
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Mike Pavone <pavone@retrodev.com>
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424
diff
changeset
|
1262 } |
add9e2f5c0e3
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Mike Pavone <pavone@retrodev.com>
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424
diff
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|
1263 } |
54
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43
diff
changeset
|
1264 } |
3b79cbcf6846
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43
diff
changeset
|
1265 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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43
diff
changeset
|
1266 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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43
diff
changeset
|
1267 |
20
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parents:
diff
changeset
|
1268 void vdp_run_context(vdp_context * context, uint32_t target_cycles) |
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parents:
diff
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|
1269 { |
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diff
changeset
|
1270 while(context->cycles < target_cycles) |
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Mostly broken VDP core and savestate viewer
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diff
changeset
|
1271 { |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
1272 context->flags &= ~FLAG_UNUSED_SLOT; |
20
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parents:
diff
changeset
|
1273 uint32_t line = context->cycles / MCLKS_LINE; |
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parents:
diff
changeset
|
1274 uint32_t active_lines = context->latched_mode & BIT_PAL ? PAL_ACTIVE : NTSC_ACTIVE; |
334
4c91470e1a53
Only latch video mode at the very beginning of the frame to avoid problems with the cycle count getting out of sync with what I expect
Mike Pavone <pavone@retrodev.com>
parents:
333
diff
changeset
|
1275 if (!context->cycles) { |
54
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43
diff
changeset
|
1276 latch_mode(context); |
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43
diff
changeset
|
1277 } |
317
e5e8b48ad157
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291
diff
changeset
|
1278 uint32_t linecyc = context->cycles % MCLKS_LINE; |
e5e8b48ad157
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291
diff
changeset
|
1279 if (linecyc == 0) { |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
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291
diff
changeset
|
1280 if (line <= 1 || line >= active_lines) { |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
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291
diff
changeset
|
1281 context->hint_counter = context->regs[REG_HINT]; |
e5e8b48ad157
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diff
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|
1282 } else if (context->hint_counter) { |
e5e8b48ad157
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291
diff
changeset
|
1283 context->hint_counter--; |
e5e8b48ad157
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diff
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|
1284 } else { |
e5e8b48ad157
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291
diff
changeset
|
1285 context->flags2 |= FLAG2_HINT_PENDING; |
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|
1286 context->hint_counter = context->regs[REG_HINT]; |
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diff
changeset
|
1287 } |
e5e8b48ad157
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291
diff
changeset
|
1288 } else if(line == active_lines) { |
331
de17e0352f27
Fixup VINT cycle and HBLANK flag for the previous timing fixes
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330
diff
changeset
|
1289 uint32_t intcyc = context->latched_mode & BIT_H40 ? VINT_CYCLE_H40 : VINT_CYCLE_H32; |
317
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291
diff
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|
1290 if (linecyc == intcyc) { |
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291
diff
changeset
|
1291 context->flags2 |= FLAG2_VINT_PENDING; |
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|
1292 } |
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diff
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|
1293 } |
330
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diff
changeset
|
1294 uint32_t inccycles, slot; |
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|
1295 if (context->latched_mode & BIT_H40){ |
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|
1296 if (linecyc < MCLKS_SLOT_H40*HSYNC_SLOT_H40) { |
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diff
changeset
|
1297 slot = linecyc/MCLKS_SLOT_H40; |
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|
1298 inccycles = MCLKS_SLOT_H40; |
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|
1299 } else if(linecyc < MCLK_WEIRD_END) { |
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diff
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|
1300 switch(linecyc-(MCLKS_SLOT_H40*HSYNC_SLOT_H40)) |
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|
1301 { |
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diff
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|
1302 case 0: |
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|
1303 inccycles = 19; |
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diff
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|
1304 slot = 0; |
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|
1305 break; |
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|
1306 case 19: |
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|
1307 slot = 1; |
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diff
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|
1308 inccycles = 20; |
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diff
changeset
|
1309 break; |
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diff
changeset
|
1310 case 39: |
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|
1311 slot = 2; |
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|
1312 inccycles = 20; |
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|
1313 break; |
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Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1314 case 59: |
332
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1315 slot = 3; |
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1316 inccycles = 20; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1317 break; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1318 case 79: |
332
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1319 slot = 4; |
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1320 inccycles = 18; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1321 break; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1322 case 97: |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1323 slot = 5; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1324 inccycles = 20; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1325 break; |
332
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1326 case 117: |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1327 slot = 6; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1328 inccycles = 20; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1329 break; |
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1330 case 137: |
332
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1331 slot = 7; |
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1332 inccycles = 20; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1333 break; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1334 case 157: |
332
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1335 slot = 8; |
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1336 inccycles = 18; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1337 break; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1338 case 175: |
332
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1339 slot = 9; |
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1340 inccycles = 20; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1341 break; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1342 case 195: |
332
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1343 slot = 10; |
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1344 inccycles = 20; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1345 break; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1346 case 215: |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1347 slot = 11; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1348 inccycles = 20; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1349 break; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1350 case 235: |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1351 slot = 12; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1352 inccycles = 18; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1353 break; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1354 case 253: |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1355 slot = 13; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1356 inccycles = 20; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1357 break; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1358 case 273: |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1359 slot = 14; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1360 inccycles = 20; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1361 break; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1362 case 293: |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1363 slot = 15; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1364 inccycles = 20; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1365 break; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1366 case 313: |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1367 slot = 16; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1368 inccycles = 19; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1369 break; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1370 default: |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1371 fprintf(stderr, "cycles after weirdness %d\n", linecyc-(MCLKS_SLOT_H40*HSYNC_SLOT_H40)); |
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Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1372 exit(1); |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1373 } |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1374 slot += HSYNC_SLOT_H40; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1375 } else { |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1376 slot = (linecyc-MCLK_WEIRD_END)/MCLKS_SLOT_H40 + SLOT_WEIRD_END; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
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parents:
329
diff
changeset
|
1377 inccycles = MCLKS_SLOT_H40; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1378 } |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1379 } else { |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1380 inccycles = MCLKS_SLOT_H32; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1381 slot = linecyc/MCLKS_SLOT_H32; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1382 } |
329
fd5f6577db9b
Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents:
328
diff
changeset
|
1383 if ((line < active_lines || (line == active_lines && linecyc < (context->latched_mode & BIT_H40 ? 64 : 80))) && context->regs[REG_MODE_2] & DISPLAY_ENABLE) { |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1384 //first sort-of active line is treated as 255 internally |
450
3758bcdae5de
Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty
Mike Pavone <pavone@retrodev.com>
parents:
438
diff
changeset
|
1385 //it's used for gathering sprite info for line |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1386 line = (line - 1) & 0xFF; |
450
3758bcdae5de
Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty
Mike Pavone <pavone@retrodev.com>
parents:
438
diff
changeset
|
1387 |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1388 //Convert to slot number |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1389 if (context->latched_mode & BIT_H40){ |
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1390 vdp_h40(line, slot, context); |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1391 } else { |
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1392 vdp_h32(line, slot, context); |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
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parents:
diff
changeset
|
1393 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
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parents:
diff
changeset
|
1394 } else { |
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1395 if (!is_refresh(context, slot)) { |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1396 external_slot(context); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1397 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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parents:
43
diff
changeset
|
1398 if (line < active_lines) { |
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
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parents:
329
diff
changeset
|
1399 check_render_bg(context, line, slot); |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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parents:
43
diff
changeset
|
1400 } |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
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parents:
diff
changeset
|
1401 } |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
1402 if (context->flags & FLAG_DMA_RUN && !is_refresh(context, slot)) { |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
1403 run_dma_src(context, slot); |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
1404 } |
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
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diff
changeset
|
1405 context->cycles += inccycles; |
20
f664eeb55cb4
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1406 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1407 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
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parents:
diff
changeset
|
1408 |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
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parents:
diff
changeset
|
1409 uint32_t vdp_run_to_vblank(vdp_context * context) |
f664eeb55cb4
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parents:
diff
changeset
|
1410 { |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1411 uint32_t target_cycles = ((context->latched_mode & BIT_PAL) ? PAL_ACTIVE : NTSC_ACTIVE) * MCLKS_LINE; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
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parents:
diff
changeset
|
1412 vdp_run_context(context, target_cycles); |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1413 return context->cycles; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1414 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1415 |
75 | 1416 void vdp_run_dma_done(vdp_context * context, uint32_t target_cycles) |
1417 { | |
1418 for(;;) { | |
1419 uint32_t dmalen = (context->regs[REG_DMALEN_H] << 8) | context->regs[REG_DMALEN_L]; | |
1420 if (!dmalen) { | |
1421 dmalen = 0x10000; | |
1422 } | |
1423 uint32_t min_dma_complete = dmalen * (context->latched_mode & BIT_H40 ? 16 : 20); | |
1424 if ((context->regs[REG_DMASRC_H] & 0xC0) == 0xC0 || (context->cd & 0xF) == VRAM_WRITE) { | |
1425 //DMA copies take twice as long to complete since they require a read and a write | |
1426 //DMA Fills and transfers to VRAM also take twice as long as it requires 2 writes for a single word | |
1427 min_dma_complete *= 2; | |
1428 } | |
1429 min_dma_complete += context->cycles; | |
1430 if (target_cycles < min_dma_complete) { | |
1431 vdp_run_context(context, target_cycles); | |
1432 return; | |
1433 } else { | |
1434 vdp_run_context(context, min_dma_complete); | |
1435 if (!(context->flags & FLAG_DMA_RUN)) { | |
1436 return; | |
1437 } | |
1438 } | |
1439 } | |
1440 } | |
1441 | |
1442 int vdp_control_port_write(vdp_context * context, uint16_t value) | |
54
3b79cbcf6846
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parents:
43
diff
changeset
|
1443 { |
471
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1444 //printf("control port write: %X at %d\n", value, context->cycles); |
149
139e5dcd6aa3
Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents:
143
diff
changeset
|
1445 if (context->flags & FLAG_DMA_RUN) { |
139e5dcd6aa3
Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents:
143
diff
changeset
|
1446 return -1; |
139e5dcd6aa3
Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents:
143
diff
changeset
|
1447 } |
54
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parents:
43
diff
changeset
|
1448 if (context->flags & FLAG_PENDING) { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1449 context->address = (context->address & 0x3FFF) | (value << 14); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1450 context->cd = (context->cd & 0x3) | ((value >> 2) & 0x3C); |
75 | 1451 context->flags &= ~FLAG_PENDING; |
453
b491df8bdbc0
Adjust VBLANK flag and refresh timing to be in line with logic analyzer and visual observations of direct color DMA demos. Remove debug print statements.
Mike Pavone <pavone@retrodev.com>
parents:
452
diff
changeset
|
1452 //printf("New Address: %X, New CD: %X\n", context->address, context->cd); |
327
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
1453 if (context->cd & 0x20 && (context->regs[REG_MODE_2] & BIT_DMA_ENABLE)) { |
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
1454 // |
75 | 1455 if((context->regs[REG_DMASRC_H] & 0xC0) != 0x80) { |
1456 //DMA copy or 68K -> VDP, transfer starts immediately | |
1457 context->flags |= FLAG_DMA_RUN; | |
131
8fc8e46be691
Fix bug that was causing DMA fills to lock up under certain circumstances
Mike Pavone <pavone@retrodev.com>
parents:
109
diff
changeset
|
1458 context->dma_cd = context->cd; |
453
b491df8bdbc0
Adjust VBLANK flag and refresh timing to be in line with logic analyzer and visual observations of direct color DMA demos. Remove debug print statements.
Mike Pavone <pavone@retrodev.com>
parents:
452
diff
changeset
|
1459 //printf("DMA start at cycle %d\n", context->cycles); |
75 | 1460 if (!(context->regs[REG_DMASRC_H] & 0x80)) { |
327
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
1461 //printf("DMA Address: %X, New CD: %X, Source: %X, Length: %X\n", context->address, context->cd, (context->regs[REG_DMASRC_H] << 17) | (context->regs[REG_DMASRC_M] << 9) | (context->regs[REG_DMASRC_L] << 1), context->regs[REG_DMALEN_H] << 8 | context->regs[REG_DMALEN_L]); |
75 | 1462 return 1; |
327
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
1463 } else { |
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
1464 //printf("DMA Copy Address: %X, New CD: %X, Source: %X\n", context->address, context->cd, (context->regs[REG_DMASRC_M] << 8) | context->regs[REG_DMASRC_L]); |
75 | 1465 } |
327
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
1466 } else { |
453
b491df8bdbc0
Adjust VBLANK flag and refresh timing to be in line with logic analyzer and visual observations of direct color DMA demos. Remove debug print statements.
Mike Pavone <pavone@retrodev.com>
parents:
452
diff
changeset
|
1467 //printf("DMA Fill Address: %X, New CD: %X\n", context->address, context->cd); |
75 | 1468 } |
63
a6dd5b7a971b
Add FPS counter to console output
Mike Pavone <pavone@retrodev.com>
parents:
58
diff
changeset
|
1469 } |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1470 } else { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1471 if ((value & 0xC000) == 0x8000) { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1472 //Register write |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1473 uint8_t reg = (value >> 8) & 0x1F; |
475
50e0cb475294
Don't allow register writes to regs above when in Mode 4
Mike Pavone <pavone@retrodev.com>
parents:
474
diff
changeset
|
1474 if (reg < (context->regs[REG_MODE_2] & BIT_MODE_5 ? VDP_REGS : 0xA)) { |
453
b491df8bdbc0
Adjust VBLANK flag and refresh timing to be in line with logic analyzer and visual observations of direct color DMA demos. Remove debug print statements.
Mike Pavone <pavone@retrodev.com>
parents:
452
diff
changeset
|
1475 //printf("register %d set to %X\n", reg, value & 0xFF); |
480
0737953132ad
Implement HV counter latch
Mike Pavone <pavone@retrodev.com>
parents:
479
diff
changeset
|
1476 if (reg == REG_MODE_1 && (value & BIT_HVC_LATCH) && !(context->regs[reg] & BIT_HVC_LATCH)) { |
0737953132ad
Implement HV counter latch
Mike Pavone <pavone@retrodev.com>
parents:
479
diff
changeset
|
1477 context->hv_latch = vdp_hv_counter_read(context); |
0737953132ad
Implement HV counter latch
Mike Pavone <pavone@retrodev.com>
parents:
479
diff
changeset
|
1478 } |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1479 context->regs[reg] = value; |
413
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1480 if (reg == REG_MODE_4) { |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1481 context->double_res = (value & (BIT_INTERLACE | BIT_DOUBLE_RES)) == (BIT_INTERLACE | BIT_DOUBLE_RES); |
415
8c60c8c09a0f
Fix sprite y mask in interlace mode. Fix framebuffer selection when switching out of interlace mode.
Mike Pavone <pavone@retrodev.com>
parents:
414
diff
changeset
|
1482 if (!context->double_res) { |
8c60c8c09a0f
Fix sprite y mask in interlace mode. Fix framebuffer selection when switching out of interlace mode.
Mike Pavone <pavone@retrodev.com>
parents:
414
diff
changeset
|
1483 context->framebuf = context->oddbuf; |
8c60c8c09a0f
Fix sprite y mask in interlace mode. Fix framebuffer selection when switching out of interlace mode.
Mike Pavone <pavone@retrodev.com>
parents:
414
diff
changeset
|
1484 } |
413
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1485 } |
476
5d7bc113653b
Clear the low 2 bits of CD when a register is written to
Mike Pavone <pavone@retrodev.com>
parents:
475
diff
changeset
|
1486 context->cd &= 0x3C; |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1487 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1488 } else { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1489 context->flags |= FLAG_PENDING; |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1490 context->address = (context->address &0xC000) | (value & 0x3FFF); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1491 context->cd = (context->cd &0x3C) | (value >> 14); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1492 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1493 } |
75 | 1494 return 0; |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1495 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1496 |
149
139e5dcd6aa3
Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents:
143
diff
changeset
|
1497 int vdp_data_port_write(vdp_context * context, uint16_t value) |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1498 { |
471
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1499 //printf("data port write: %X at %d\n", value, context->cycles); |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
1500 if (context->flags & FLAG_DMA_RUN && (context->regs[REG_DMASRC_H] & 0xC0) != 0x80) { |
149
139e5dcd6aa3
Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents:
143
diff
changeset
|
1501 return -1; |
139e5dcd6aa3
Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents:
143
diff
changeset
|
1502 } |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1503 context->flags &= ~FLAG_PENDING; |
109
004dd46e0a97
COmment out fifo full debug printf
Mike Pavone <pavone@retrodev.com>
parents:
108
diff
changeset
|
1504 /*if (context->fifo_cur == context->fifo_end) { |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1505 printf("FIFO full, waiting for space before next write at cycle %X\n", context->cycles); |
109
004dd46e0a97
COmment out fifo full debug printf
Mike Pavone <pavone@retrodev.com>
parents:
108
diff
changeset
|
1506 }*/ |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
1507 if (context->cd & 0x20 && (context->regs[REG_DMASRC_H] & 0xC0) == 0x80) { |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
1508 context->flags &= ~FLAG_DMA_RUN; |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
1509 } |
471
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1510 while (context->fifo_write == context->fifo_read) { |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1511 vdp_run_context(context, context->cycles + ((context->latched_mode & BIT_H40) ? 16 : 20)); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1512 } |
471
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1513 fifo_entry * cur = context->fifo + context->fifo_write; |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1514 cur->cycle = context->cycles + ((context->latched_mode & BIT_H40) ? 16 : 20)*FIFO_LATENCY; |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1515 cur->address = context->address; |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1516 cur->value = value; |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
1517 if (context->cd & 0x20 && (context->regs[REG_DMASRC_H] & 0xC0) == 0x80) { |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
1518 context->flags |= FLAG_DMA_RUN; |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
1519 } |
471
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1520 cur->cd = context->cd; |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1521 cur->partial = 0; |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1522 if (context->fifo_read < 0) { |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1523 context->fifo_read = context->fifo_write; |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1524 } |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1525 context->fifo_write = (context->fifo_write + 1) & (FIFO_SIZE-1); |
138 | 1526 context->address += context->regs[REG_AUTOINC]; |
149
139e5dcd6aa3
Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents:
143
diff
changeset
|
1527 return 0; |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1528 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1529 |
470
541c1ae8abf3
Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1530 void vdp_test_port_write(vdp_context * context, uint16_t value) |
541c1ae8abf3
Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1531 { |
541c1ae8abf3
Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1532 //TODO: implement test register |
541c1ae8abf3
Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1533 } |
541c1ae8abf3
Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1534 |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1535 uint16_t vdp_control_port_read(vdp_context * context) |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1536 { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1537 context->flags &= ~FLAG_PENDING; |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1538 uint16_t value = 0x3400; |
471
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1539 if (context->fifo_read < 0) { |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1540 value |= 0x200; |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1541 } |
471
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1542 if (context->fifo_read == context->fifo_write) { |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1543 value |= 0x100; |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1544 } |
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1545 if (context->flags2 & FLAG2_VINT_PENDING) { |
413
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1546 value |= 0x80; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1547 } |
494
8ac0eb05642c
Initial implementation of sprite overflow and sprite collision status register flags
Mike Pavone <pavone@retrodev.com>
parents:
481
diff
changeset
|
1548 if (context->flags & FLAG_DOT_OFLOW) { |
8ac0eb05642c
Initial implementation of sprite overflow and sprite collision status register flags
Mike Pavone <pavone@retrodev.com>
parents:
481
diff
changeset
|
1549 value |= 0x40; |
8ac0eb05642c
Initial implementation of sprite overflow and sprite collision status register flags
Mike Pavone <pavone@retrodev.com>
parents:
481
diff
changeset
|
1550 } |
8ac0eb05642c
Initial implementation of sprite overflow and sprite collision status register flags
Mike Pavone <pavone@retrodev.com>
parents:
481
diff
changeset
|
1551 if (context->flags2 & FLAG2_SPRITE_COLLIDE) { |
8ac0eb05642c
Initial implementation of sprite overflow and sprite collision status register flags
Mike Pavone <pavone@retrodev.com>
parents:
481
diff
changeset
|
1552 value |= 0x20; |
8ac0eb05642c
Initial implementation of sprite overflow and sprite collision status register flags
Mike Pavone <pavone@retrodev.com>
parents:
481
diff
changeset
|
1553 //TODO: Test when this is actually cleared |
8ac0eb05642c
Initial implementation of sprite overflow and sprite collision status register flags
Mike Pavone <pavone@retrodev.com>
parents:
481
diff
changeset
|
1554 context->flags2 &= ~FLAG2_SPRITE_COLLIDE; |
8ac0eb05642c
Initial implementation of sprite overflow and sprite collision status register flags
Mike Pavone <pavone@retrodev.com>
parents:
481
diff
changeset
|
1555 } |
413
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1556 if ((context->regs[REG_MODE_4] & BIT_INTERLACE) && context->framebuf == context->oddbuf) { |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1557 value |= 0x10; |
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1558 } |
318
789f2f5f2277
Implement hblank flag in status register
Mike Pavone <pavone@retrodev.com>
parents:
317
diff
changeset
|
1559 uint32_t line= context->cycles / MCLKS_LINE; |
789f2f5f2277
Implement hblank flag in status register
Mike Pavone <pavone@retrodev.com>
parents:
317
diff
changeset
|
1560 uint32_t linecyc = context->cycles % MCLKS_LINE; |
481
1f3450d1129f
Set VBLANK flag in status register when display is disabled
Mike Pavone <pavone@retrodev.com>
parents:
480
diff
changeset
|
1561 if (line >= (context->latched_mode & BIT_PAL ? PAL_ACTIVE : NTSC_ACTIVE) || !(context->regs[REG_MODE_2] & BIT_DISP_EN)) { |
318
789f2f5f2277
Implement hblank flag in status register
Mike Pavone <pavone@retrodev.com>
parents:
317
diff
changeset
|
1562 value |= 0x8; |
789f2f5f2277
Implement hblank flag in status register
Mike Pavone <pavone@retrodev.com>
parents:
317
diff
changeset
|
1563 } |
331
de17e0352f27
Fixup VINT cycle and HBLANK flag for the previous timing fixes
Mike Pavone <pavone@retrodev.com>
parents:
330
diff
changeset
|
1564 if (linecyc < (context->latched_mode & BIT_H40 ? HBLANK_CLEAR_H40 : HBLANK_CLEAR_H32)) { |
318
789f2f5f2277
Implement hblank flag in status register
Mike Pavone <pavone@retrodev.com>
parents:
317
diff
changeset
|
1565 value |= 0x4; |
789f2f5f2277
Implement hblank flag in status register
Mike Pavone <pavone@retrodev.com>
parents:
317
diff
changeset
|
1566 } |
149
139e5dcd6aa3
Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents:
143
diff
changeset
|
1567 if (context->flags & FLAG_DMA_RUN) { |
141
576f55711d8d
Fix DMA in progress flag in VDP status register
Mike Pavone <pavone@retrodev.com>
parents:
138
diff
changeset
|
1568 value |= 0x2; |
75 | 1569 } |
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1570 if (context->latched_mode & BIT_PAL) {//Not sure about this, need to verify |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1571 value |= 0x1; |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1572 } |
459
c49ecf575784
Revert change to VBLANK flag timing based on new direct color DMA test
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
1573 //printf("status read at cycle %d returned %X\n", context->cycles, value); |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1574 return value; |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1575 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1576 |
470
541c1ae8abf3
Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1577 #define CRAM_BITS 0xEEE |
474
e128e55710bd
Remove read pending stuff, that had been added in an attempt to fix CRAM/VSRAM undefined bit results. Set number of bits actually saved in VSRAM to 11
Mike Pavone <pavone@retrodev.com>
parents:
473
diff
changeset
|
1578 #define VSRAM_BITS 0x7FF |
471
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1579 #define VSRAM_DIRTY_BITS 0xF800 |
470
541c1ae8abf3
Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1580 |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1581 uint16_t vdp_data_port_read(vdp_context * context) |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1582 { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1583 context->flags &= ~FLAG_PENDING; |
138 | 1584 if (context->cd & 1) { |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1585 return 0; |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1586 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1587 //Not sure if the FIFO should be drained before processing a read or not, but it would make sense |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1588 context->flags &= ~FLAG_UNUSED_SLOT; |
474
e128e55710bd
Remove read pending stuff, that had been added in an attempt to fix CRAM/VSRAM undefined bit results. Set number of bits actually saved in VSRAM to 11
Mike Pavone <pavone@retrodev.com>
parents:
473
diff
changeset
|
1589 //context->flags2 |= FLAG2_READ_PENDING; |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1590 while (!(context->flags & FLAG_UNUSED_SLOT)) { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1591 vdp_run_context(context, context->cycles + ((context->latched_mode & BIT_H40) ? 16 : 20)); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1592 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1593 uint16_t value = 0; |
138 | 1594 switch (context->cd & 0xF) |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1595 { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1596 case VRAM_READ: |
472 | 1597 value = context->vdpmem[context->address & 0xFFFE] << 8; |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1598 context->flags &= ~FLAG_UNUSED_SLOT; |
470
541c1ae8abf3
Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1599 context->flags2 |= FLAG2_READ_PENDING; |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1600 while (!(context->flags & FLAG_UNUSED_SLOT)) { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1601 vdp_run_context(context, context->cycles + ((context->latched_mode & BIT_H40) ? 16 : 20)); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1602 } |
472 | 1603 value |= context->vdpmem[context->address | 1]; |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1604 break; |
473
1358045c0bdd
Implement undocumented 8-bit VRAM read
Mike Pavone <pavone@retrodev.com>
parents:
472
diff
changeset
|
1605 case VRAM_READ8: |
1358045c0bdd
Implement undocumented 8-bit VRAM read
Mike Pavone <pavone@retrodev.com>
parents:
472
diff
changeset
|
1606 value = context->vdpmem[context->address ^ 1]; |
1358045c0bdd
Implement undocumented 8-bit VRAM read
Mike Pavone <pavone@retrodev.com>
parents:
472
diff
changeset
|
1607 value |= context->fifo[context->fifo_write].value & 0xFF00; |
1358045c0bdd
Implement undocumented 8-bit VRAM read
Mike Pavone <pavone@retrodev.com>
parents:
472
diff
changeset
|
1608 break; |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1609 case CRAM_READ: |
470
541c1ae8abf3
Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1610 value = context->cram[(context->address/2) & (CRAM_SIZE-1)] & CRAM_BITS; |
471
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1611 value |= context->fifo[context->fifo_write].value & ~CRAM_BITS; |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1612 break; |
479
863e868752cf
Implement funny behavior for DMA fill to CRAM and VSRAM. Return VSRAM address 0 for reads to VSRAM at >= 40
Mike Pavone <pavone@retrodev.com>
parents:
478
diff
changeset
|
1613 case VSRAM_READ: { |
863e868752cf
Implement funny behavior for DMA fill to CRAM and VSRAM. Return VSRAM address 0 for reads to VSRAM at >= 40
Mike Pavone <pavone@retrodev.com>
parents:
478
diff
changeset
|
1614 uint16_t address = (context->address /2) & 63; |
863e868752cf
Implement funny behavior for DMA fill to CRAM and VSRAM. Return VSRAM address 0 for reads to VSRAM at >= 40
Mike Pavone <pavone@retrodev.com>
parents:
478
diff
changeset
|
1615 if (address >= VSRAM_SIZE) { |
863e868752cf
Implement funny behavior for DMA fill to CRAM and VSRAM. Return VSRAM address 0 for reads to VSRAM at >= 40
Mike Pavone <pavone@retrodev.com>
parents:
478
diff
changeset
|
1616 address = 0; |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1617 } |
479
863e868752cf
Implement funny behavior for DMA fill to CRAM and VSRAM. Return VSRAM address 0 for reads to VSRAM at >= 40
Mike Pavone <pavone@retrodev.com>
parents:
478
diff
changeset
|
1618 value = context->vsram[address] & VSRAM_BITS; |
863e868752cf
Implement funny behavior for DMA fill to CRAM and VSRAM. Return VSRAM address 0 for reads to VSRAM at >= 40
Mike Pavone <pavone@retrodev.com>
parents:
478
diff
changeset
|
1619 value |= context->fifo[context->fifo_write].value & VSRAM_DIRTY_BITS; |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1620 break; |
479
863e868752cf
Implement funny behavior for DMA fill to CRAM and VSRAM. Return VSRAM address 0 for reads to VSRAM at >= 40
Mike Pavone <pavone@retrodev.com>
parents:
478
diff
changeset
|
1621 } |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1622 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1623 context->address += context->regs[REG_AUTOINC]; |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1624 return value; |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1625 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1626 |
137 | 1627 uint16_t vdp_hv_counter_read(vdp_context * context) |
1628 { | |
480
0737953132ad
Implement HV counter latch
Mike Pavone <pavone@retrodev.com>
parents:
479
diff
changeset
|
1629 if (context->regs[REG_MODE_1] & BIT_HVC_LATCH) { |
0737953132ad
Implement HV counter latch
Mike Pavone <pavone@retrodev.com>
parents:
479
diff
changeset
|
1630 return context->hv_latch; |
0737953132ad
Implement HV counter latch
Mike Pavone <pavone@retrodev.com>
parents:
479
diff
changeset
|
1631 } |
137 | 1632 uint32_t line= context->cycles / MCLKS_LINE; |
1633 if (!line) { | |
1634 line = 0xFF; | |
1635 } else { | |
1636 line--; | |
1637 if (line > 0xEA) { | |
1638 line = (line + 0xFA) & 0xFF; | |
1639 } | |
1640 } | |
1641 uint32_t linecyc = context->cycles % MCLKS_LINE; | |
1642 if (context->latched_mode & BIT_H40) { | |
332
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1643 uint32_t slot; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1644 if (linecyc < MCLKS_SLOT_H40*HSYNC_SLOT_H40) { |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1645 slot = linecyc/MCLKS_SLOT_H40; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1646 } else if(linecyc < MCLK_WEIRD_END) { |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1647 switch(linecyc-(MCLKS_SLOT_H40*HSYNC_SLOT_H40)) |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1648 { |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1649 case 0: |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1650 slot = 0; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1651 break; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1652 case 19: |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1653 slot = 1; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1654 break; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1655 case 39: |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1656 slot = 2; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1657 break; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1658 case 59: |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1659 slot = 2; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1660 break; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1661 case 79: |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1662 slot = 3; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1663 break; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1664 case 97: |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1665 slot = 4; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1666 break; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1667 case 117: |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1668 slot = 5; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1669 break; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1670 case 137: |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1671 slot = 6; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1672 break; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1673 case 157: |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1674 slot = 7; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1675 break; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1676 case 175: |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1677 slot = 8; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1678 break; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1679 case 195: |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1680 slot = 9; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1681 break; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1682 case 215: |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1683 slot = 11; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1684 break; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1685 case 235: |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1686 slot = 12; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1687 break; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1688 case 253: |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1689 slot = 13; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1690 break; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1691 case 273: |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1692 slot = 14; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1693 break; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1694 case 293: |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1695 slot = 15; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1696 break; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1697 case 313: |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1698 slot = 16; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1699 break; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1700 default: |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1701 fprintf(stderr, "cycles after weirdness %d\n", linecyc-(MCLKS_SLOT_H40*HSYNC_SLOT_H40)); |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1702 exit(1); |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1703 } |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1704 slot += HSYNC_SLOT_H40; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1705 } else { |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1706 slot = (linecyc-MCLK_WEIRD_END)/MCLKS_SLOT_H40 + SLOT_WEIRD_END; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1707 } |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1708 linecyc = slot * 2; |
137 | 1709 if (linecyc >= 86) { |
1710 linecyc -= 86; | |
1711 } else { | |
1712 linecyc += 334; | |
1713 } | |
1714 if (linecyc > 0x16C) { | |
1715 linecyc += 92; | |
1716 } | |
1717 } else { | |
1718 linecyc /= 10; | |
1719 if (linecyc >= 74) { | |
1720 linecyc -= 74; | |
1721 } else { | |
1722 linecyc += 268; | |
1723 } | |
1724 if (linecyc > 0x127) { | |
1725 linecyc += 170; | |
1726 } | |
1727 } | |
1728 linecyc &= 0xFF; | |
413
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1729 if (context->double_res) { |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1730 line <<= 1; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1731 if (line & 0x100) { |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1732 line |= 1; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1733 } |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1734 } |
137 | 1735 return (line << 8) | linecyc; |
1736 } | |
1737 | |
470
541c1ae8abf3
Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1738 uint16_t vdp_test_port_read(vdp_context * context) |
541c1ae8abf3
Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1739 { |
541c1ae8abf3
Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1740 //TODO: Find out what actually gets returned here |
541c1ae8abf3
Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1741 return 0xFFFF; |
541c1ae8abf3
Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1742 } |
541c1ae8abf3
Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1743 |
65
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1744 void vdp_adjust_cycles(vdp_context * context, uint32_t deduction) |
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1745 { |
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1746 context->cycles -= deduction; |
471
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1747 if (context->fifo_read >= 0) { |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1748 int32_t idx = context->fifo_read; |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1749 do { |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1750 if (context->fifo[idx].cycle >= deduction) { |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1751 context->fifo[idx].cycle -= deduction; |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1752 } else { |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1753 context->fifo[idx].cycle = 0; |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1754 } |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1755 idx = (idx+1) & (FIFO_SIZE-1); |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1756 } while(idx != context->fifo_write); |
65
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1757 } |
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1758 } |
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1759 |
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1760 uint32_t vdp_next_hint(vdp_context * context) |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1761 { |
327
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
1762 if (!(context->regs[REG_MODE_1] & BIT_HINT_EN)) { |
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1763 return 0xFFFFFFFF; |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1764 } |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1765 if (context->flags2 & FLAG2_HINT_PENDING) { |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1766 return context->cycles; |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1767 } |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1768 uint32_t active_lines = context->latched_mode & BIT_PAL ? PAL_ACTIVE : NTSC_ACTIVE; |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1769 uint32_t line = context->cycles / MCLKS_LINE; |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1770 if (line >= active_lines) { |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1771 return 0xFFFFFFFF; |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1772 } |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1773 uint32_t linecyc = context->cycles % MCLKS_LINE; |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1774 uint32_t hcycle = context->cycles + context->hint_counter * MCLKS_LINE + MCLKS_LINE - linecyc; |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1775 if (!line) { |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1776 hcycle += MCLKS_LINE; |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1777 } |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1778 return hcycle; |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1779 } |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1780 |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1781 uint32_t vdp_next_vint(vdp_context * context) |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1782 { |
327
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
1783 if (!(context->regs[REG_MODE_2] & BIT_VINT_EN)) { |
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1784 return 0xFFFFFFFF; |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1785 } |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1786 if (context->flags2 & FLAG2_VINT_PENDING) { |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1787 return context->cycles; |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1788 } |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1789 uint32_t active_lines = context->latched_mode & BIT_PAL ? PAL_ACTIVE : NTSC_ACTIVE; |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1790 uint32_t vcycle = MCLKS_LINE * active_lines; |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1791 if (context->latched_mode & BIT_H40) { |
331
de17e0352f27
Fixup VINT cycle and HBLANK flag for the previous timing fixes
Mike Pavone <pavone@retrodev.com>
parents:
330
diff
changeset
|
1792 vcycle += VINT_CYCLE_H40; |
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1793 } else { |
331
de17e0352f27
Fixup VINT cycle and HBLANK flag for the previous timing fixes
Mike Pavone <pavone@retrodev.com>
parents:
330
diff
changeset
|
1794 vcycle += VINT_CYCLE_H32; |
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1795 } |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1796 if (vcycle < context->cycles) { |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1797 return 0xFFFFFFFF; |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1798 } |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1799 return vcycle; |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1800 } |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1801 |
333 | 1802 uint32_t vdp_next_vint_z80(vdp_context * context) |
1803 { | |
1804 uint32_t active_lines = context->latched_mode & BIT_PAL ? PAL_ACTIVE : NTSC_ACTIVE; | |
1805 uint32_t vcycle = MCLKS_LINE * active_lines; | |
1806 if (context->latched_mode & BIT_H40) { | |
1807 vcycle += VINT_CYCLE_H40; | |
1808 } else { | |
1809 vcycle += VINT_CYCLE_H32; | |
1810 } | |
1811 return vcycle; | |
1812 } | |
1813 | |
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1814 void vdp_int_ack(vdp_context * context, uint16_t int_num) |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1815 { |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1816 if (int_num == 6) { |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1817 context->flags2 &= ~FLAG2_VINT_PENDING; |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1818 } else if(int_num ==4) { |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1819 context->flags2 &= ~FLAG2_HINT_PENDING; |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1820 } |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1821 } |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1822 |