Mercurial > repos > blastem
annotate gentests.py @ 1135:8506b305e0e8
Update Mode 4 rendering to match logic analyzer captures
author | Michael Pavone <pavone@retrodev.com> |
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date | Sun, 01 Jan 2017 21:06:32 -0800 |
parents | 097c172839d4 |
children | 188a60def81f |
rev | line source |
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1 #!/usr/bin/env python |
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2 |
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3 def split_fields(line): |
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4 parts = [] |
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5 while line: |
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6 field,_,line = line.partition('\t') |
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7 parts.append(field.strip()) |
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8 while line.startswith('\t'): |
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9 line = line[1:] |
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10 return parts |
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11 |
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12 class Program(object): |
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13 def __init__(self, instruction): |
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14 self.avail_dregs = {0,1,2,3,4,5,6,7} |
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15 self.avail_aregs = {0,1,2,3,4,5,6,7} |
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16 instruction.consume_regs(self) |
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17 self.inst = instruction |
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18 |
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19 def dirname(self): |
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20 return self.inst.name + '_' + self.inst.size |
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21 def name(self): |
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22 return str(self.inst).replace('.', '_').replace('#', '_').replace(',', '_').replace(' ', '_').replace('(', '[').replace(')', ']') |
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23 |
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24 def write_rom_test(self, outfile): |
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25 outfile.write('\tdc.l $0, start\n') |
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26 needdivzero = self.inst.name.startswith('div') |
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27 needchk = self.inst.name.startswith('chk') |
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28 for i in xrange(0x8, 0x100, 0x4): |
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29 if needdivzero and i == 0x14: |
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30 outfile.write('\tdc.l div_zero_handler\n') |
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31 elif needchk and i == 0x18: |
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32 outfile.write('\tdc.l chk_handler\n') |
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33 else: |
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34 outfile.write('\tdc.l empty_handler\n') |
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35 outfile.write('\tdc.b "SEGA"\nempty_handler:\n\trte\n') |
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36 if needdivzero: |
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37 outfile.write('div_zero_handler:\n') |
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38 div_zero_count = self.get_dreg() |
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39 outfile.write('\taddq #1, ' + str(div_zero_count) + '\n') |
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40 outfile.write('\trte\n') |
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41 if needchk: |
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42 outfile.write('chk_handler:\n') |
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43 chk_count = self.get_dreg() |
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44 outfile.write('\taddq #1, ' + str(chk_count) + '\n') |
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45 outfile.write('\trte\n') |
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46 outfile.write('start:\n\tmove #0, CCR\n') |
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47 if needdivzero: |
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48 outfile.write('\tmoveq #0, ' + str(div_zero_count) + '\n') |
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49 already = {} |
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50 self.inst.write_init(outfile, already) |
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51 if 'label' in already: |
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52 outfile.write('lbl_' + str(already['label']) + ':\n') |
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53 outfile.write('\t'+str(self.inst)+'\n') |
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54 outfile.write('\t'+self.inst.save_result(self.get_dreg(), True) + '\n') |
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55 save_ccr = self.get_dreg() |
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56 outfile.write('\tmove SR, ' + str(save_ccr) + '\n') |
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57 outfile.write('\tmove #$1F, CCR\n') |
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58 self.inst.invalidate_dest(already) |
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59 self.inst.write_init(outfile, already) |
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60 if 'label' in already: |
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61 outfile.write('lbl_' + str(already['label']) + ':\n') |
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62 outfile.write('\t'+str(self.inst)+'\n') |
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63 outfile.write('\t'+self.inst.save_result(self.get_dreg(), False) + '\n') |
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64 outfile.write('\treset\n') |
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65 |
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66 def consume_dreg(self, num): |
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67 self.avail_dregs.discard(num) |
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68 |
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69 def consume_areg(self, num): |
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70 self.avail_aregs.discard(num) |
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71 |
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72 def get_dreg(self): |
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73 return Register('d', self.avail_dregs.pop()) |
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74 |
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75 class Dummy(object): |
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76 def __str__(self): |
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77 return '' |
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78 def write_init(self, outfile, size, already): |
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79 pass |
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80 def consume_regs(self, program): |
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81 pass |
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82 |
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83 dummy_op = Dummy() |
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84 |
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85 class Register(object): |
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86 def __init__(self, kind, num): |
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87 self.kind = kind |
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88 self.num = num |
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89 |
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90 def __str__(self): |
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91 if self.kind == 'd' or self.kind == 'a': |
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92 return self.kind + str(self.num) |
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93 return self.kind |
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94 |
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95 def write_init(self, outfile, size, already): |
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96 if not str(self) in already: |
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97 minv,maxv = get_size_range(size) |
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98 val = randint(minv,maxv) |
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99 already[str(self)] = val |
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100 outfile.write('\tmove.'+size+' #'+str(val)+', ' + str(self) + '\n') |
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101 |
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102 def consume_regs(self, program): |
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103 if self.kind == 'd': |
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104 program.consume_dreg(self.num) |
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105 elif self.kind == 'a': |
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106 program.consume_areg(self.num) |
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107 |
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108 def valid_ram_address(address, size='b'): |
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109 return address >= 0xE00000 and address <= 0xFFFFFFFC and (address & 0xE00000) == 0xE00000 and (size == 'b' or not address & 1) |
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110 |
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111 def random_ram_address(mina=0xE00000, maxa=0xFFFFFFFC): |
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112 return randint(mina, maxa) | 0xE00000 |
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113 |
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114 class Indexed(object): |
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115 def __init__(self, base, index, index_size, disp): |
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116 self.base = base |
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117 self.index = index |
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118 self.index_size = index_size |
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119 self.disp = disp |
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120 |
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121 def write_init(self, outfile, size, already): |
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122 if self.base.kind == 'pc': |
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123 if str(self.index) in already: |
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124 index = already[str(self.index)] |
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125 if self.index_size == 'w': |
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126 index = index & 0xFFFF |
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127 #sign extend index |
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128 if index & 0x8000: |
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129 index -= 65536 |
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130 if index > -1024: |
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131 index = already[str(self.index)] = randint(-32768, -1024) |
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132 outfile.write('\tmove.l #' + str(index) + ', ' + str(self.index) + '\n') |
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133 else: |
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134 index = already[str(self.index)] = randint(-32768, -1024) |
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135 outfile.write('\tmove.l #' + str(index) + ', ' + str(self.index) + '\n') |
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136 num = already.get('label', 0)+1 |
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137 already['label'] = num |
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138 address = 'lbl_' + str(num) + ' + 2 + ' + str(self.disp) + ' + ' + str(index) |
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139 else: |
217
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140 if self.base == self.index: |
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141 if str(self.base) in already: |
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142 if not valid_ram_address(already[str(self.base)]*2): |
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143 del already[str(self.base)] |
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144 self.write_init(outfile, size, already) |
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145 return |
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146 else: |
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147 base = index = already[str(self.base)] |
214
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148 else: |
217
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149 base = index = already[str(self.base)] = random_ram_address()/2 |
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150 outfile.write('\tmove.l #' + str(base) + ', ' + str(self.base) + '\n') |
214
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151 else: |
217
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152 if str(self.base) in already: |
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153 if not valid_ram_address(already[str(self.base)]): |
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154 del already[str(self.base)] |
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155 self.write_init(outfile, size, already) |
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156 return |
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157 else: |
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158 base = already[str(self.base)] |
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159 else: |
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160 base = already[str(self.base)] = random_ram_address() |
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161 outfile.write('\tmove.l #' + str(base) + ', ' + str(self.base) + '\n') |
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162 if str(self.index) in already: |
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163 index = already[str(self.index)] |
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164 if self.index_size == 'w': |
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165 index = index & 0xFFFF |
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166 #sign extend index |
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167 if index & 0x8000: |
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168 index -= 65536 |
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169 if not valid_ram_address(base + index): |
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170 index = already[str(self.index)] = randint(-64, 63) |
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171 outfile.write('\tmove.l #' + str(index) + ', ' + str(self.index) + '\n') |
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172 else: |
214
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173 index = already[str(self.index)] = randint(-64, 63) |
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174 outfile.write('\tmove.l #' + str(index) + ', ' + str(self.index) + '\n') |
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175 address = base + index + self.disp |
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176 if (address & 0xFFFFFF) < 0xE00000: |
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177 if (address & 0xFFFFFF) < 128: |
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178 self.disp -= (address & 0xFFFFFF) |
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179 else: |
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180 self.disp += 0xE00000-(address & 0xFFFFFF) |
608
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181 if self.disp > 127: |
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182 self.disp = 127 |
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183 elif self.disp < -128: |
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184 self.disp = -128 |
214
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185 address = base + index + self.disp |
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186 elif (address & 0xFFFFFF) > 0xFFFFFC: |
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187 self.disp -= (address & 0xFFFFFF) - 0xFFFFFC |
608
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188 if self.disp > 127: |
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189 self.disp = 127 |
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190 elif self.disp < -128: |
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191 self.disp = -128 |
214
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192 address = base + index + self.disp |
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193 if size != 'b' and address & 1: |
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194 self.disp = self.disp ^ 1 |
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195 address = base + index + self.disp |
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196 minv,maxv = get_size_range(size) |
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197 outfile.write('\tmove.' + size + ' #' + str(randint(minv, maxv)) + ', (' + str(address) + ').l\n') |
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198 |
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199 def __str__(self): |
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200 return '(' + str(self.disp) + ', ' + str(self.base) + ', ' + str(self.index) + '.' + self.index_size + ')' |
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201 |
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202 def consume_regs(self, program): |
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203 self.base.consume_regs(program) |
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204 self.index.consume_regs(program) |
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205 |
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206 class Displacement(object): |
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207 def __init__(self, base, disp): |
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208 self.base = base |
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209 self.disp = disp |
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210 |
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211 def write_init(self, outfile, size, already): |
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212 if self.base.kind == 'pc': |
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213 num = already.get('label', 0)+1 |
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214 already['label'] = num |
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215 address = 'lbl_' + str(num) + ' + 2 + ' + str(self.disp) |
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216 else: |
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217 if str(self.base) in already: |
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218 if not valid_ram_address(already[str(self.base)]): |
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219 del already[str(self.base)] |
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220 self.write_init(outfile, size, already) |
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221 return |
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222 else: |
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223 base = already[str(self.base)] |
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224 else: |
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225 base = already[str(self.base)] = random_ram_address() |
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226 outfile.write('\tmove.l #' + str(base) + ', ' + str(self.base) + '\n') |
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227 address = base + self.disp |
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228 if (address & 0xFFFFFF) < 0xE00000: |
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229 if (address & 0xFFFFFF) < 0x10000: |
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230 self.disp -= (address & 0xFFFFFF) |
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231 else: |
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232 self.disp += 0xE00000-(address & 0xFFFFFF) |
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233 address = base + self.disp |
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234 elif (address & 0xFFFFFF) > 0xFFFFFC: |
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235 self.disp -= (address & 0xFFFFFF) - 0xFFFFFC |
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236 address = base + self.disp |
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237 if size != 'b' and address & 1: |
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238 self.disp = self.disp ^ 1 |
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239 address = base + self.disp |
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240 minv,maxv = get_size_range(size) |
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241 outfile.write('\tmove.' + size + ' #' + str(randint(minv, maxv)) + ', (' + str(address) + ').l\n') |
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242 |
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243 def __str__(self): |
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244 return '(' + str(self.disp) + ', ' + str(self.base) + ')' |
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245 |
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246 def consume_regs(self, program): |
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247 self.base.consume_regs(program) |
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248 |
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249 class Indirect(object): |
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250 def __init__(self, reg): |
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251 self.reg = reg |
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252 |
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253 def __str__(self): |
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254 return '(' + str(self.reg) + ')' |
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255 |
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256 def write_init(self, outfile, size, already): |
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257 if str(self.reg) in already: |
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258 if not valid_ram_address(already[str(self.reg)], size): |
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259 del already[str(self.reg)] |
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260 self.write_init(outfile, size, already) |
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261 return |
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262 else: |
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263 address = already[str(self.reg)] |
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264 else: |
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265 address = random_ram_address() |
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266 if size != 'b': |
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267 address = address & 0xFFFFFFFE |
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268 outfile.write('\tmove.l #' + str(address) + ', ' + str(self.reg) + '\n') |
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269 already[str(self.reg)] = address |
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270 minv,maxv = get_size_range(size) |
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271 outfile.write('\tmove.' + size + ' #' + str(randint(minv, maxv)) + ', (' + str(address) + ').l\n') |
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272 |
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273 def consume_regs(self, program): |
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274 self.reg.consume_regs(program) |
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275 |
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276 class Increment(object): |
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277 def __init__(self, reg): |
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278 self.reg = reg |
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279 |
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280 def __str__(self): |
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281 return '(' + str(self.reg) + ')+' |
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282 |
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283 def write_init(self, outfile, size, already): |
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284 if str(self.reg) in already: |
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285 if not valid_ram_address(already[str(self.reg)], size): |
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286 del already[str(self.reg)] |
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287 self.write_init(outfile, size, already) |
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288 return |
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289 else: |
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290 address = already[str(self.reg)] |
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291 else: |
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292 address = random_ram_address() |
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293 if size != 'b': |
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294 address = address & 0xFFFFFFFE |
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295 outfile.write('\tmove.l #' + str(address) + ', ' + str(self.reg) + '\n') |
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296 already[str(self.reg)] = address |
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297 minv,maxv = get_size_range(size) |
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298 outfile.write('\tmove.' + size + ' #' + str(randint(minv, maxv)) + ', (' + str(address) + ').l\n') |
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299 |
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300 def consume_regs(self, program): |
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301 self.reg.consume_regs(program) |
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302 |
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303 class Decrement(object): |
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304 def __init__(self, reg): |
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305 self.reg = reg |
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306 |
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307 def __str__(self): |
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308 return '-(' + str(self.reg) + ')' |
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309 |
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310 def write_init(self, outfile, size, already): |
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311 if str(self.reg) in already: |
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312 if not valid_ram_address(already[str(self.reg)]- 4 if size == 'l' else 2 if size == 'w' else 1, size): |
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313 del already[str(self.reg)] |
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314 self.write_init(outfile, size, already) |
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315 return |
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316 else: |
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317 address = already[str(self.reg)] |
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318 else: |
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319 address = random_ram_address(mina=0xE00004) |
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320 if size != 'b': |
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321 address = address & 0xFFFFFFFE |
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322 outfile.write('\tmove.l #' + str(address) + ', ' + str(self.reg) + '\n') |
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323 already[str(self.reg)] = address |
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324 minv,maxv = get_size_range(size) |
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325 outfile.write('\tmove.' + size + ' #' + str(randint(minv, maxv)) + ', (' + str(address) + ').l\n') |
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326 |
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327 def consume_regs(self, program): |
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328 self.reg.consume_regs(program) |
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329 |
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330 class Absolute(object): |
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331 def __init__(self, address, size): |
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332 self.address = address |
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333 self.size = size |
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334 |
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335 def __str__(self): |
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336 return '(' + str(self.address) + ').' + self.size |
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337 |
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338 def write_init(self, outfile, size, already): |
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339 minv,maxv = get_size_range(size) |
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340 outfile.write('\tmove.' + size + ' #' + str(randint(minv, maxv)) + ', '+str(self)+'\n') |
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341 |
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342 def consume_regs(self, program): |
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343 pass |
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344 |
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345 class Immediate(object): |
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346 def __init__(self, value): |
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347 self.value = value |
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348 |
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349 def __str__(self): |
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350 return '#' + str(self.value) |
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351 |
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352 def write_init(self, outfile, size, already): |
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353 pass |
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354 |
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355 def consume_regs(self, program): |
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356 pass |
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357 |
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358 all_dregs = [Register('d', i) for i in range(0, 8)] |
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359 all_aregs = [Register('a', i) for i in range(0, 8)] |
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360 all_indirect = [Indirect(reg) for reg in all_aregs] |
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361 all_predec = [Decrement(reg) for reg in all_aregs] |
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362 all_postinc = [Increment(reg) for reg in all_aregs] |
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363 from random import randint |
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364 def all_indexed(): |
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365 return [Indexed(base, index, index_size, randint(-128, 127)) for base in all_aregs for index in all_dregs + all_aregs for index_size in ('w','l')] |
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366 |
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367 def all_disp(): |
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368 return [Displacement(base, randint(-32768, 32767)) for base in all_aregs] |
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369 |
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370 def rand_pc_disp(): |
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371 return [Displacement(Register('pc', 0), randint(-32768, -1024)) for x in xrange(0, 8)] |
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372 |
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373 def all_pc_indexed(): |
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374 return [Indexed(Register('pc', 0), index, index_size, randint(-128, 127)) for index in all_dregs + all_aregs for index_size in ('w','l')] |
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375 |
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376 def rand_abs_short(): |
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377 return [Absolute(0xFFFF8000 + randint(0, 32767), 'w') for x in xrange(0, 8)] |
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378 |
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379 def rand_abs_long(): |
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380 return [Absolute(0xFF0000 + randint(0, 65535), 'l') for x in xrange(0, 8)] |
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381 |
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382 def get_size_range(size): |
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383 if size == 'b': |
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384 return (-128, 127) |
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385 elif size == 'w': |
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386 return (-32768, 32767) |
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387 else: |
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388 return (-2147483648, 2147483647) |
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389 |
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390 def rand_immediate(size): |
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391 minv,maxv = get_size_range(size) |
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392 |
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393 return [Immediate(randint(minv, maxv)) for x in xrange(0,8)] |
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394 |
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395 def get_variations(mode, size): |
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396 mapping = { |
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397 'd':all_dregs, |
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398 'a':all_aregs, |
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399 '(a)':all_indirect, |
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400 '-(a)':all_predec, |
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401 '(a)+':all_postinc, |
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402 '(n,a)':all_disp, |
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403 '(n,a,x)':all_indexed, |
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404 '(n,pc)':rand_pc_disp, |
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405 '(n,pc,x)':all_pc_indexed, |
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406 '(n).w':rand_abs_short, |
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407 '(n).l':rand_abs_long |
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408 } |
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409 if mode in mapping: |
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410 ret = mapping[mode] |
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411 if type(ret) != list: |
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412 ret = ret() |
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413 return ret |
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414 elif mode == '#n': |
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415 return rand_immediate(size) |
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416 elif mode.startswith('#(') and mode.endswith(')'): |
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417 inner = mode[2:-1] |
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418 start,sep,end = inner.rpartition('-') |
220
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419 start,end = int(start),int(end) |
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420 if end-start > 16: |
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421 return [Immediate(randint(start, end)) for x in range(0,8)] |
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422 else: |
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423 return [Immediate(num) for num in range(start, end+1)] |
217
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424 else: |
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425 print "Don't know what to do with source type", mode |
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426 return None |
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427 |
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428 class Inst2Op(object): |
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429 def __init__(self, name, size, src, dst): |
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430 self.name = name |
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431 self.size = size |
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432 self.src = src |
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433 self.dst = dst |
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434 |
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435 def __str__(self): |
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436 return self.name + '.' + self.size + ' ' + str(self.src) + ', ' + str(self.dst) |
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437 |
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438 def write_init(self, outfile, already): |
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439 self.src.write_init(outfile, self.size, already) |
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440 self.dst.write_init(outfile, self.size, already) |
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441 |
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442 def invalidate_dest(self, already): |
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443 if type(self.dst) == Register: |
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444 del already[str(self.dst)] |
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445 |
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446 def save_result(self, reg, always): |
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447 if always or type(self.dst) != Register: |
217
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448 if type(self.dst) == Decrement: |
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449 src = Increment(self.dst.reg) |
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450 elif type(self.dst) == Increment: |
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451 src = Decrement(self.dst.reg) |
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452 else: |
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453 src = self.dst |
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454 return 'move.' + self.size + ' ' + str(src) + ', ' + str(reg) |
214
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455 else: |
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456 return '' |
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457 |
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458 def consume_regs(self, program): |
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459 self.src.consume_regs(program) |
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460 self.dst.consume_regs(program) |
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461 |
439
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462 class Inst1Op(Inst2Op): |
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463 def __init__(self, name, size, dst): |
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464 super(Inst1Op, self).__init__(name, size, dummy_op, dst) |
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465 |
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466 def __str__(self): |
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467 return self.name + '.' + self.size + ' ' + str(self.dst) |
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468 |
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469 class Entry(object): |
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470 def __init__(self, line): |
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471 fields = split_fields(line) |
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472 self.name = fields[0] |
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473 sizes = fields[1] |
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474 sources = fields[2].split(';') |
439
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475 if len(fields) > 3: |
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476 dests = fields[3].split(';') |
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477 else: |
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478 dests = None |
214
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479 combos = [] |
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480 for size in sizes: |
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481 for source in sources: |
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482 if size != 'b' or source != 'a': |
439
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483 if dests: |
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484 for dest in dests: |
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485 if size != 'b' or dest != 'a': |
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486 combos.append((size, source, dest)) |
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487 else: |
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488 combos.append((size, None, source)) |
214
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489 self.cases = combos |
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490 |
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491 def programs(self): |
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492 res = [] |
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493 for (size, src, dst) in self.cases: |
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494 dests = get_variations(dst, size) |
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495 if src: |
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496 sources = get_variations(src, size) |
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497 for source in sources: |
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498 for dest in dests: |
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499 res.append(Program(Inst2Op(self.name, size, source, dest))) |
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500 else: |
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501 for dest in dests: |
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502 res.append(Program(Inst1Op(self.name, size, dest))) |
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503 return res |
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504 |
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505 def process_entries(f): |
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506 entries = [] |
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507 for line in f: |
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508 if not line.startswith('Name') and not line.startswith('#') and len(line.strip()) > 0: |
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509 entries.append(Entry(line)) |
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510 return entries |
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511 |
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512 from os import path, mkdir |
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513 def main(args): |
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514 entries = process_entries(open('testcases.txt')) |
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515 for entry in entries: |
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516 programs = entry.programs() |
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517 for program in programs: |
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518 dname = program.dirname() |
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519 if not path.exists('generated_tests/' + dname): |
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520 mkdir('generated_tests/' + dname) |
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521 f = open('generated_tests/' + dname + '/' + program.name() + '.s68', 'w') |
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522 program.write_rom_test(f) |
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523 f.close() |
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524 |
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525 if __name__ == '__main__': |
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526 import sys |
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527 main(sys.argv) |
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528 |