Mercurial > repos > blastem
annotate m68k.cpu @ 1904:8312e574100a
Implement selectable YM2612/YM3834 invalid status port behavior
author | Michael Pavone <pavone@retrodev.com> |
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date | Wed, 26 Feb 2020 22:40:37 -0800 |
parents | 0c1491818f4b |
children | 84b32010ef8d |
rev | line source |
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1 info |
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2 prefix m68k_ |
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3 opcode_size 16 |
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4 body m68k_run_op |
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5 header m68k.h |
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6 interrupt m68k_interrupt |
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7 include m68k_util.c |
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8 sync_cycle m68k_sync_cycle |
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9 |
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10 declare |
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11 typedef m68k_context *(*m68k_reset_handler)(m68k_context *context); |
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12 void init_m68k_opts(m68k_options *opts, memmap_chunk * memmap, uint32_t num_chunks, uint32_t clock_divider); |
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13 m68k_context *init_68k_context(m68k_options * opts, m68k_reset_handler reset_handler); |
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14 void m68k_reset(m68k_context *context); |
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15 void m68k_print_regs(m68k_context *context); |
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16 |
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17 regs |
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18 dregs 32 d0 d1 d2 d3 d4 d5 d6 d7 |
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19 aregs 32 a0 a1 a2 a3 a4 a5 a6 a7 |
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20 pc 32 |
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21 other_sp 32 |
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22 scratch1 32 |
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23 scratch2 32 |
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24 int_cycle 32 |
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25 prefetch 16 |
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26 int_priority 8 |
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27 int_num 8 |
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28 int_pending 8 |
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29 int_pending_num 8 |
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30 int_ack 8 |
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31 status 8 |
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32 ccr 8 |
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33 xflag 8 |
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34 nflag 8 |
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35 zflag 8 |
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36 vflag 8 |
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37 cflag 8 |
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38 reset_handler ptrvoid |
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39 mem_pointers ptrvoid 8 |
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40 |
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41 flags |
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42 register ccr |
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43 X 4 carry xflag |
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44 N 3 sign nflag |
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45 Z 2 zero zflag |
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46 V 1 overflow vflag |
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47 C 0 carry cflag |
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48 |
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49 m68k_prefetch |
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50 if dynarec |
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51 |
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52 ccall m68k_read16_noinc context pc |
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53 mov result prefetch |
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54 |
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55 end |
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56 |
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57 if interp |
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58 |
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59 mov pc scratch1 |
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60 ocall read_16 |
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61 mov scratch1 prefetch |
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62 |
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63 end |
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64 |
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65 add 2 pc pc |
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66 |
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67 check_user_mode_swap_ssp_usp |
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68 local tmp 8 |
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69 and 0x20 status tmp |
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70 if tmp |
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71 else |
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72 |
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73 xchg other_sp a7 |
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74 |
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75 end |
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76 |
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77 m68k_get_sr |
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78 lsl status 8 scratch1 |
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79 or ccr scratch1 scratch1 |
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80 |
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81 m68k_write32_lowfirst |
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82 arg value 32 |
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83 add 2 scratch2 scratch2 |
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84 mov value scratch1 |
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85 ocall write_16 |
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86 |
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87 sub 2 scratch2 scratch2 |
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88 lsr value 16 scratch1 |
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89 ocall write_16 |
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90 |
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91 m68k_write32 |
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92 arg value 32 |
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93 local tmp 32 |
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94 mov value tmp |
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95 lsr value 16 scratch1 |
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96 ocall write_16 |
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97 |
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98 add 2 scratch2 scratch2 |
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99 mov tmp scratch1 |
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100 ocall write_16 |
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101 |
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102 m68k_read32 |
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103 local tmp 32 |
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104 add 2 scratch1 tmp |
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105 ocall read_16 |
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106 xchg scratch1 tmp |
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107 ocall read_16 |
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108 lsl tmp 16 tmp |
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109 or tmp scratch1 scratch1 |
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110 |
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111 m68k_interrupt |
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112 cmp int_cycle cycles |
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113 if >=U |
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114 |
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115 #INT_PENDING_NONE |
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116 cmp 255 int_pending |
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117 if = |
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118 |
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119 mov int_priority int_pending |
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120 mov int_num int_pending_num |
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121 |
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122 else |
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123 |
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124 #INT_PENDING_SR_CHANGE |
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125 cmp 254 int_pending |
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126 if = |
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127 |
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128 mov int_priority int_pending |
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129 mov int_num int_pending_num |
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130 |
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131 else |
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132 |
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133 check_user_mode_swap_ssp_usp |
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134 |
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135 cycles 6 |
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136 #save status reg |
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137 sub 6 a7 a7 |
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138 m68k_get_sr |
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139 mov a7 scratch2 |
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140 ocall write_16 |
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141 |
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142 #update status register |
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143 and 0x78 status status |
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144 or int_priority status status |
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145 or 0x20 status status |
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146 |
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147 #Interrupt ack cycle |
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148 mov int_pending int_ack |
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149 if int_pending_num |
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150 cycles 4 |
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151 else |
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152 #TODO: do the whole E clock variable latency nonsense |
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153 cycles 13 |
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154 add 24 int_pending int_pending_num |
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155 end |
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156 |
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157 #save pc |
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158 add 2 a7 scratch2 |
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159 m68k_write32_lowfirst pc |
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160 |
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161 lsl int_pending_num 2 scratch1 |
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162 m68k_read32 |
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163 mov scratch1 pc |
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164 update_sync |
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165 end |
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166 |
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167 m68k_run_op |
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168 dispatch prefetch |
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169 |
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170 m68k_mem_src |
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171 arg address 32 |
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172 arg size 16 |
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173 arg isdst 8 |
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174 mov address scratch1 |
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175 if isdst |
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176 mov address scratch2 |
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177 meta ismem 1 |
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178 end |
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179 switch size |
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180 |
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181 case 0 |
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182 ocall read_8 |
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183 |
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184 case 1 |
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185 ocall read_16 |
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186 |
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187 case 2 |
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188 m68k_read32 |
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189 |
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190 end |
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191 meta op scratch1 |
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192 |
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193 m68k_write_size |
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194 arg size 16 |
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195 arg lowfirst 8 |
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196 switch size |
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197 case 0 |
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198 ocall write_8 |
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199 |
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200 case 1 |
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201 ocall write_16 |
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|
202 |
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203 case 2 |
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204 if lowfirst |
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205 m68k_write32_lowfirst scratch1 |
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206 else |
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207 m68k_write32 scratch1 |
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208 end |
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209 end |
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210 |
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211 m68k_index_word |
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212 m68k_prefetch |
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213 local disp 32 |
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|
214 and prefetch 255 disp |
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|
215 sext 16 disp disp |
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|
216 sext 32 disp disp |
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|
217 local index 16 |
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|
218 lsr prefetch 12 index |
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|
219 local isareg 16 |
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|
220 and index 8 isareg |
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|
221 and index 7 index |
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|
222 local islong 16 |
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|
223 and prefetch 2048 islong |
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|
224 |
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|
225 switch isareg |
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|
226 case 0 |
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|
227 switch islong |
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|
228 case 0 |
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|
229 sext 32 dregs.index scratch1 |
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|
230 case 2048 |
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|
231 mov dregs.index scratch1 |
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|
232 end |
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|
233 case 8 |
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|
234 switch islong |
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|
235 case 0 |
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|
236 sext 32 aregs.index scratch1 |
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|
237 case 2048 |
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|
238 mov aregs.index scratch1 |
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|
239 end |
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|
240 end |
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|
241 add disp scratch1 scratch1 |
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|
242 |
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|
243 m68k_fetch_op_ea |
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|
244 arg mode 16 |
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diff
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|
245 arg reg 16 |
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|
246 arg Z 16 |
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|
247 arg isdst 8 |
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|
248 switch mode |
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|
249 |
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|
250 case 0 |
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|
251 #data reg direct |
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|
252 meta op dregs.reg |
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|
253 if isdst |
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diff
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|
254 meta ismem 0 |
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parents:
diff
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|
255 end |
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|
256 |
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|
257 case 1 |
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|
258 #address reg direct |
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|
259 meta op aregs.reg |
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diff
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|
260 if isdst |
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diff
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|
261 meta ismem 0 |
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diff
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|
262 end |
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parents:
diff
changeset
|
263 |
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diff
changeset
|
264 case 2 |
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|
265 #address reg indirect |
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|
266 m68k_mem_src aregs.reg Z isdst |
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diff
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|
267 |
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|
268 case 3 |
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|
269 #postincrement |
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diff
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|
270 m68k_mem_src aregs.reg Z isdst |
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parents:
diff
changeset
|
271 switch reg |
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diff
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|
272 case 7 |
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|
273 if Z |
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parents:
diff
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|
274 addsize Z aregs.reg aregs.reg |
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diff
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|
275 else |
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parents:
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|
276 addsize 1 aregs.reg aregs.reg |
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parents:
diff
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|
277 end |
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parents:
diff
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|
278 default |
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|
279 addsize Z aregs.reg aregs.reg |
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parents:
diff
changeset
|
280 end |
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parents:
diff
changeset
|
281 |
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|
282 case 4 |
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parents:
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|
283 #predecrement |
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parents:
diff
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|
284 switch reg |
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parents:
diff
changeset
|
285 case 7 |
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parents:
diff
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|
286 if Z |
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parents:
diff
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|
287 decsize Z aregs.reg aregs.reg |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
288 else |
0c1491818f4b
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parents:
diff
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|
289 decsize 1 aregs.reg aregs.reg |
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parents:
diff
changeset
|
290 end |
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WIP new 68K core using CPU DSL
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parents:
diff
changeset
|
291 default |
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parents:
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|
292 decsize Z aregs.reg aregs.reg |
0c1491818f4b
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parents:
diff
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|
293 end |
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parents:
diff
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|
294 cycles 2 |
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|
295 m68k_mem_src aregs.reg Z isdst |
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parents:
diff
changeset
|
296 |
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|
297 case 5 |
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parents:
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|
298 #displacement |
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|
299 m68k_prefetch |
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parents:
diff
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|
300 sext 32 prefetch scratch1 |
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Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
301 add scratch1 aregs.reg scratch1 |
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parents:
diff
changeset
|
302 m68k_mem_src scratch1 Z isdst |
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WIP new 68K core using CPU DSL
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parents:
diff
changeset
|
303 |
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parents:
diff
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|
304 case 6 |
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parents:
diff
changeset
|
305 #indexed |
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parents:
diff
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|
306 m68k_index_word |
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parents:
diff
changeset
|
307 add aregs.reg scratch1 scratch1 |
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parents:
diff
changeset
|
308 |
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parents:
diff
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|
309 m68k_mem_src scratch1 Z isdst |
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parents:
diff
changeset
|
310 case 7 |
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parents:
diff
changeset
|
311 #pc-relative and absolute modes |
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Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
312 |
0c1491818f4b
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parents:
diff
changeset
|
313 switch reg |
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Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
314 case 0 |
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Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
315 #absolute short |
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Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
316 m68k_prefetch |
0c1491818f4b
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Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
317 sext 32 prefetch scratch1 |
0c1491818f4b
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Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
318 m68k_mem_src scratch1 Z isdst |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
319 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
320 case 1 |
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Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
321 #absolute long |
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Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
322 local address 32 |
0c1491818f4b
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Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
323 m68k_prefetch |
0c1491818f4b
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Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
324 lsl prefetch 16 address |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
325 m68k_prefetch |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
326 or prefetch address scratch1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
327 m68k_mem_src scratch1 Z isdst |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
328 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
329 case 2 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
330 #pc displaceent |
0c1491818f4b
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Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
331 m68k_prefetch |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
332 sext 32 prefetch scratch1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
333 add scratch1 pc scratch1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
334 sub 2 scratch1 scratch1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
335 m68k_mem_src scratch1 Z isdst |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
336 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
337 case 3 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
338 #pc indexed |
0c1491818f4b
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Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
339 m68k_index_word |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
340 add pc scratch1 scratch1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
341 sub 2 scratch1 scratch1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
342 m68k_mem_src scratch1 Z isdst |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
343 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
344 case 4 |
0c1491818f4b
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Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
345 #immediate |
0c1491818f4b
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Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
346 switch Z |
0c1491818f4b
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Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
347 case 2 |
0c1491818f4b
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Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
348 local tmp32 32 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
349 m68k_prefetch |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
350 lsl prefetch 16 tmp32 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
351 m68k_prefetch |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
352 or prefetch tmp32 scratch1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
353 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
354 default |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
355 m68k_prefetch |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
356 mov prefetch scratch1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
357 end |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
358 meta op scratch1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
359 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
360 end |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
361 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
362 end |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
363 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
364 m68k_fetch_src_ea |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
365 arg mode 16 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
366 arg reg 16 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
367 arg Z 16 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
368 m68k_fetch_op_ea mode reg Z 0 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
369 meta src op |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
370 switch mode |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
371 case 0 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
372 meta src_is_mem 0 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
373 case 1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
374 meta src_is_mem 0 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
375 default |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
376 meta src_is_mem 1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
377 end |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
378 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
379 m68k_fetch_dst_ea |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
380 arg mode 16 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
381 arg reg 16 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
382 arg Z 16 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
383 m68k_fetch_op_ea mode reg Z 1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
384 meta dst op |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
385 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
386 m68k_save_dst |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
387 arg Z 16 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
388 if ismem |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
389 m68k_write_size Z 0 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
390 end |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
391 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
392 1101DDD0ZZMMMRRR add_ea_dn |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
393 invalid M 7 R 5 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
394 invalid M 7 R 6 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
395 invalid M 7 R 7 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
396 invalid Z 3 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
397 m68k_fetch_src_ea M R Z |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
398 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
399 add src dregs.D dregs.D Z |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
400 update_flags XNZVC |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
401 m68k_prefetch |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
402 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
403 1101DDD1ZZMMMRRR add_dn_ea |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
404 invalid M 7 R 2 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
405 invalid M 7 R 3 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
406 invalid M 7 R 4 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
407 invalid M 7 R 5 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
408 invalid M 7 R 6 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
409 invalid M 7 R 7 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
410 invalid Z 3 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
411 m68k_fetch_dst_ea M R Z |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
412 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
413 add dregs.D dst dst Z |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
414 update_flags XNZVC |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
415 m68k_save_dst Z |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
416 m68k_prefetch |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
417 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
418 1101AAAZ11MMMRRR adda |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
419 invalid M 7 R 5 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
420 invalid M 7 R 6 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
421 invalid M 7 R 7 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
422 local size 16 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
423 local ext_src 32 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
424 if Z |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
425 mov 2 size |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
426 else |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
427 mov 1 size |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
428 end |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
429 m68k_fetch_src_ea M R size |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
430 switch size |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
431 case 1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
432 sext 32 src ext_src |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
433 meta src ext_src |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
434 end |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
435 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
436 add src aregs.A aregs.A |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
437 m68k_prefetch |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
438 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
439 00000110ZZMMMRRR addi |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
440 local immed 32 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
441 invalid Z 3 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
442 invalid M 7 R 2 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
443 invalid M 7 R 3 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
444 invalid M 7 R 4 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
445 invalid M 7 R 5 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
446 invalid M 7 R 6 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
447 invalid M 7 R 7 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
448 #fetch immediate operand |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
449 m68k_prefetch |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
450 switch Z |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
451 case 2 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
452 lsl prefetch 16 immed |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
453 m68k_prefetch |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
454 or prefetch immed immed |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
455 default |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
456 mov prefetch immed |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
457 end |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
458 #fetch dst EA |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
459 m68k_fetch_dst_ea M R Z |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
460 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
461 add immed dst dst Z |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
462 update_flags XNZVC |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
463 m68k_save_dst Z |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
464 m68k_prefetch |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
465 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
466 0101III0ZZMMMRRR addq |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
467 invalid Z 3 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
468 invalid M 7 R 2 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
469 invalid M 7 R 3 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
470 invalid M 7 R 4 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
471 invalid M 7 R 5 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
472 invalid M 7 R 6 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
473 invalid M 7 R 7 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
474 local src 32 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
475 switch I |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
476 case 0 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
477 mov 8 src |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
478 default |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
479 mov I src |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
480 end |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
481 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
482 m68k_fetch_dst_ea M R Z |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
483 switch M |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
484 case 1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
485 add src dst dst Z |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
486 default |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
487 add src dst dst Z |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
488 update_flags XNZVC |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
489 end |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
490 m68k_save_dst Z |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
491 m68k_prefetch |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
492 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
493 1101DDD1ZZ000SSS addx_dy_dx |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
494 invalid Z 3 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
495 adc dregs.S dregs.D dregs.D Z |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
496 update_flags XNVC |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
497 switch Z |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
498 case 0 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
499 local tmp8 8 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
500 mov dregs.D tmp8 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
501 if tmp8 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
502 update_flags Z0 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
503 end |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
504 case 1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
505 local tmp16 16 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
506 mov dregs.D tmp16 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
507 if tmp16 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
508 update_flags Z0 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
509 end |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
510 case 2 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
511 if dregs.D |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
512 update_flags Z0 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
513 end |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
514 end |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
515 m68k_prefetch |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
516 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
517 1101DDD1ZZ001SSS addx_ay_ax |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
518 invalid Z 3 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
519 if Z |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
520 decsize Z aregs.S aregs.S |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
521 else |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
522 switch S |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
523 case 7 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
524 sub 2 aregs.S aregs.S |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
525 default |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
526 decsize Z aregs.S aregs.S |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
527 end |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
528 end |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
529 mov aregs.S scratch1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
530 switch Z |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
531 case 0 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
532 ocall read_8 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
533 case 1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
534 ocall read_16 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
535 case 2 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
536 m68k_read32 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
537 end |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
538 mov scratch1 scratch2 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
539 if Z |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
540 decsize Z aregs.D aregs.D |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
541 else |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
542 switch D |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
543 case 7 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
544 sub 2 aregs.D aregs.D |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
545 default |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
546 decsize Z aregs.D aregs.D |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
547 end |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
548 end |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
549 mov aregs.D scratch1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
550 switch Z |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
551 case 0 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
552 ocall read_8 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
553 case 1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
554 ocall read_16 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
555 case 2 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
556 m68k_read32 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
557 end |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
558 adc scratch2 scratch1 scratch1 Z |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
559 update_flags XNVC |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
560 switch Z |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
561 case 0 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
562 local tmp8 8 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
563 mov dregs.D tmp8 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
564 if tmp8 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
565 update_flags Z0 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
566 end |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
567 case 1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
568 local tmp16 16 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
569 mov dregs.D tmp16 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
570 if tmp16 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
571 update_flags Z0 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
572 end |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
573 case 2 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
574 if dregs.D |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
575 update_flags Z0 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
576 end |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
577 end |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
578 mov aregs.D scratch2 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
579 m68k_write_size Z 0 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
580 m68k_prefetch |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
581 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
582 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
583 00ZZRRRMMMEEESSS move |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
584 invalid Z 0 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
585 invalid M 1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
586 invalid M 7 #not actually invalid, but will be handled separately due to DSL limitations |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
587 invalid E 7 S 5 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
588 invalid E 7 S 6 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
589 invalid E 7 S 7 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
590 local size 8 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
591 local memsrc 32 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
592 #move uses a different size format than most instructions |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
593 switch Z |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
594 case 1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
595 mov 0 size |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
596 case 2 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
597 mov 2 size |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
598 case 3 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
599 mov 1 size |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
600 end |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
601 m68k_fetch_src_ea E S size |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
602 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
603 if src_is_mem |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
604 #avoid clobbering src if we need scratch1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
605 mov src memsrc |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
606 meta src memsrc |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
607 end |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
608 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
609 cmp 0 src size |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
610 update_flags NZV0C0 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
611 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
612 switch M |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
613 case 0 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
614 mov src dregs.R size |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
615 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
616 case 2 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
617 mov aregs.R scratch2 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
618 mov src scratch1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
619 m68k_write_size size 0 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
620 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
621 case 3 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
622 mov aregs.R scratch2 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
623 mov src scratch1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
624 switch R |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
625 case 7 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
626 if size |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
627 addsize size aregs.R aregs.R |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
628 else |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
629 addsize 1 aregs.R aregs.R |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
630 end |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
631 default |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
632 addsize size aregs.R aregs.R |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
633 end |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
634 m68k_write_size size 0 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
635 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
636 case 4 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
637 mov src scratch1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
638 switch R |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
639 case 7 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
640 if size |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
641 decsize size aregs.R aregs.R |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
642 else |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
643 decsize 1 aregs.R aregs.R |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
644 end |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
645 default |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
646 decsize size aregs.R aregs.R |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
647 end |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
648 mov aregs.R scratch2 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
649 m68k_write_size size 1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
650 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
651 case 5 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
652 m68k_prefetch |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
653 sext 32 prefetch scratch2 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
654 add aregs.R scratch2 scratch2 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
655 mov src scratch1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
656 m68k_write_size size 0 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
657 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
658 case 6 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
659 m68k_index_word |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
660 add aregs.R scratch1 scratch2 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
661 mov src scratch1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
662 m68k_write_size size 0 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
663 end |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
664 m68k_prefetch |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
665 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
666 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
667 00ZZ00M111EEESSS move_abs |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
668 invalid E 7 S 5 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
669 invalid E 7 S 6 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
670 invalid E 7 S 7 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
671 invalid Z 0 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
672 local size 8 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
673 local memsrc 32 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
674 #move uses a different size format than most instructions |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
675 switch Z |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
676 case 1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
677 mov 0 size |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
678 case 2 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
679 mov 2 size |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
680 case 3 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
681 mov 1 size |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
682 end |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
683 m68k_fetch_src_ea E S size |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
684 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
685 if src_is_mem |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
686 #avoid clobbering src if we need scratch1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
687 mov src memsrc |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
688 meta src memsrc |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
689 end |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
690 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
691 cmp 0 src size |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
692 update_flags NZV0C0 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
693 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
694 switch M |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
695 case 0 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
696 m68k_prefetch |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
697 sext 32 prefetch scratch2 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
698 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
699 case 1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
700 m68k_prefetch |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
701 lsl prefetch 16 scratch2 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
702 m68k_prefetch |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
703 or prefetch scratch2 scratch2 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
704 end |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
705 mov src scratch1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
706 m68k_write_size size 0 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
707 m68k_prefetch |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
708 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
709 00ZZRRR001EEESSS movea |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
710 local size 8 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
711 invalid Z 0 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
712 invalid Z 1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
713 invalid E 7 S 5 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
714 invalid E 7 S 6 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
715 invalid E 7 S 7 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
716 switch Z |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
717 case 2 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
718 mov 2 size |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
719 case 3 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
720 mov 1 size |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
721 end |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
722 m68k_fetch_src_ea E S size |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
723 switch Z |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
724 case 2 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
725 mov src aregs.R |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
726 case 3 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
727 sext 32 src aregs.R |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
728 end |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
729 m68k_prefetch |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
730 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
731 0100010011MMMRRR move_to_ccr |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
732 invalid M 1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
733 invalid M 7 R 5 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
734 invalid M 7 R 6 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
735 invalid M 7 R 7 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
736 m68k_fetch_src_ea M R 1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
737 mov scratch1 ccr |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
738 m68k_prefetch |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
739 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
740 0100011011MMMRRR move_to_sr |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
741 invalid M 1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
742 invalid M 7 R 5 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
743 invalid M 7 R 6 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
744 invalid M 7 R 7 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
745 m68k_fetch_src_ea M R 1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
746 mov scratch1 ccr |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
747 lsr scratch1 8 status |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
748 update_sync |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
749 m68k_prefetch |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
750 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
751 0100000011MMMRRR move_from_sr |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
752 invalid M 1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
753 invalid M 7 R 2 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
754 invalid M 7 R 3 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
755 invalid M 7 R 4 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
756 invalid M 7 R 5 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
757 invalid M 7 R 6 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
758 invalid M 7 R 7 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
759 m68k_fetch_dst_ea M R 1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
760 lsl status 8 scratch1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
761 or ccr scratch1 scratch1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
762 mov scratch1 dst |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
763 m68k_save_dst 1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
764 m68k_prefetch |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
765 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
766 0100111001110000 reset |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
767 cycles 124 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
768 if reset_handler |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
769 pcall reset_handler m68k_reset_handler context |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
770 end |