Mercurial > repos > blastem
annotate z80_to_x86.c @ 626:7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
author | Michael Pavone <pavone@retrodev.com> |
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date | Thu, 19 Jun 2014 19:50:16 -0700 |
parents | 6aa2a8ab9c70 |
children | c5820734a5b6 |
rev | line source |
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1 /* |
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2 Copyright 2013 Michael Pavone |
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The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
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3 This file is part of BlastEm. |
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4 BlastEm is free software distributed under the terms of the GNU General Public License version 3 or greater. See COPYING for full license text. |
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5 */ |
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6 #include "z80inst.h" |
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7 #include "z80_to_x86.h" |
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8 #include "gen_x86.h" |
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9 #include "mem.h" |
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10 #include <stdio.h> |
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11 #include <stdlib.h> |
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12 #include <stddef.h> |
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13 #include <string.h> |
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14 |
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15 #define MODE_UNUSED (MODE_IMMED-1) |
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16 |
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17 #define ZCYCLES RBP |
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18 #define ZLIMIT RDI |
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19 #define SCRATCH1 R13 |
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20 #define SCRATCH2 R14 |
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21 #define CONTEXT RSI |
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22 |
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23 //#define DO_DEBUG_PRINT |
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24 |
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25 #ifdef DO_DEBUG_PRINT |
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26 #define dprintf printf |
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27 #else |
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28 #define dprintf |
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29 #endif |
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30 |
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31 void z80_read_byte(); |
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32 void z80_read_word(); |
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33 void z80_write_byte(); |
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34 void z80_write_word_highfirst(); |
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35 void z80_write_word_lowfirst(); |
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36 void z80_save_context(); |
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37 void z80_native_addr(); |
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38 void z80_do_sync(); |
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39 void z80_handle_cycle_limit_int(); |
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40 void z80_retrans_stub(); |
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41 void z80_io_read(); |
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42 void z80_io_write(); |
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43 void z80_halt(); |
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44 void z80_save_context(); |
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45 void z80_load_context(); |
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46 |
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47 uint8_t * zbreakpoint_patch(z80_context * context, uint16_t address, uint8_t * native); |
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48 |
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49 uint8_t z80_size(z80inst * inst) |
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50 { |
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51 uint8_t reg = (inst->reg & 0x1F); |
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52 if (reg != Z80_UNUSED && reg != Z80_USE_IMMED) { |
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53 return reg < Z80_BC ? SZ_B : SZ_W; |
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54 } |
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55 //TODO: Handle any necessary special cases |
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56 return SZ_B; |
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57 } |
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58 |
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59 uint8_t * zcycles(uint8_t * dst, uint32_t num_cycles) |
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60 { |
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61 return add_ir(dst, num_cycles, ZCYCLES, SZ_D); |
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62 } |
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63 |
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64 uint8_t * z80_check_cycles_int(uint8_t * dst, uint16_t address) |
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65 { |
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66 dst = cmp_rr(dst, ZCYCLES, ZLIMIT, SZ_D); |
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67 uint8_t * jmp_off = dst+1; |
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68 dst = jcc(dst, CC_NC, dst + 7); |
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69 dst = mov_ir(dst, address, SCRATCH1, SZ_W); |
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70 dst = call(dst, (uint8_t *)z80_handle_cycle_limit_int); |
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71 *jmp_off = dst - (jmp_off+1); |
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72 return dst; |
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73 } |
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74 |
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75 uint8_t * translate_z80_reg(z80inst * inst, x86_ea * ea, uint8_t * dst, x86_z80_options * opts) |
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76 { |
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77 if (inst->reg == Z80_USE_IMMED) { |
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78 ea->mode = MODE_IMMED; |
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79 ea->disp = inst->immed; |
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80 } else if ((inst->reg & 0x1F) == Z80_UNUSED) { |
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81 ea->mode = MODE_UNUSED; |
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82 } else { |
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83 ea->mode = MODE_REG_DIRECT; |
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84 if (inst->reg == Z80_IYH) { |
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85 if ((inst->addr_mode & 0x1F) == Z80_REG && inst->ea_reg == Z80_IYL) { |
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86 dst = mov_rr(dst, opts->regs[Z80_IY], SCRATCH1, SZ_W); |
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87 dst = ror_ir(dst, 8, SCRATCH1, SZ_W); |
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88 ea->base = SCRATCH1; |
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89 } else { |
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90 ea->base = opts->regs[Z80_IYL]; |
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91 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W); |
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92 } |
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93 } else if(opts->regs[inst->reg] >= 0) { |
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94 ea->base = opts->regs[inst->reg]; |
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95 if (ea->base >= AH && ea->base <= BH) { |
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96 if ((inst->addr_mode & 0x1F) == Z80_REG) { |
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97 uint8_t other_reg = opts->regs[inst->ea_reg]; |
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98 if (other_reg >= R8 || (other_reg >= RSP && other_reg <= RDI)) { |
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99 //we can't mix an *H reg with a register that requires the REX prefix |
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100 ea->base = opts->regs[z80_low_reg(inst->reg)]; |
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101 dst = ror_ir(dst, 8, ea->base, SZ_W); |
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102 } |
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103 } else if((inst->addr_mode & 0x1F) != Z80_UNUSED && (inst->addr_mode & 0x1F) != Z80_IMMED) { |
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104 //temp regs require REX prefix too |
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105 ea->base = opts->regs[z80_low_reg(inst->reg)]; |
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106 dst = ror_ir(dst, 8, ea->base, SZ_W); |
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107 } |
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108 } |
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109 } else { |
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110 ea->mode = MODE_REG_DISPLACE8; |
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111 ea->base = CONTEXT; |
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112 ea->disp = offsetof(z80_context, regs) + inst->reg; |
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113 } |
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114 } |
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115 return dst; |
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116 } |
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117 |
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118 uint8_t * z80_save_reg(uint8_t * dst, z80inst * inst, x86_z80_options * opts) |
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119 { |
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120 if (inst->reg == Z80_IYH) { |
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121 if ((inst->addr_mode & 0x1F) == Z80_REG && inst->ea_reg == Z80_IYL) { |
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122 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W); |
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123 dst = mov_rr(dst, SCRATCH1, opts->regs[Z80_IYL], SZ_B); |
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124 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W); |
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125 } else { |
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126 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W); |
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127 } |
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128 } else if (opts->regs[inst->reg] >= AH && opts->regs[inst->reg] <= BH) { |
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129 if ((inst->addr_mode & 0x1F) == Z80_REG) { |
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130 uint8_t other_reg = opts->regs[inst->ea_reg]; |
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131 if (other_reg >= R8 || (other_reg >= RSP && other_reg <= RDI)) { |
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132 //we can't mix an *H reg with a register that requires the REX prefix |
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133 dst = ror_ir(dst, 8, opts->regs[z80_low_reg(inst->reg)], SZ_W); |
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134 } |
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135 } else if((inst->addr_mode & 0x1F) != Z80_UNUSED && (inst->addr_mode & 0x1F) != Z80_IMMED) { |
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136 //temp regs require REX prefix too |
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137 dst = ror_ir(dst, 8, opts->regs[z80_low_reg(inst->reg)], SZ_W); |
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138 } |
213
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139 } |
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140 return dst; |
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141 } |
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142 |
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143 uint8_t * translate_z80_ea(z80inst * inst, x86_ea * ea, uint8_t * dst, x86_z80_options * opts, uint8_t read, uint8_t modify) |
213
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144 { |
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145 uint8_t size, reg, areg; |
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146 ea->mode = MODE_REG_DIRECT; |
213
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147 areg = read ? SCRATCH1 : SCRATCH2; |
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148 switch(inst->addr_mode & 0x1F) |
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149 { |
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150 case Z80_REG: |
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151 if (inst->ea_reg == Z80_IYH) { |
312
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152 if (inst->reg == Z80_IYL) { |
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153 dst = mov_rr(dst, opts->regs[Z80_IY], SCRATCH1, SZ_W); |
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154 dst = ror_ir(dst, 8, SCRATCH1, SZ_W); |
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155 ea->base = SCRATCH1; |
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156 } else { |
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157 ea->base = opts->regs[Z80_IYL]; |
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158 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W); |
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159 } |
213
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160 } else { |
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161 ea->base = opts->regs[inst->ea_reg]; |
267
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162 if (ea->base >= AH && ea->base <= BH && inst->reg != Z80_UNUSED && inst->reg != Z80_USE_IMMED) { |
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163 uint8_t other_reg = opts->regs[inst->reg]; |
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164 if (other_reg >= R8 || (other_reg >= RSP && other_reg <= RDI)) { |
267
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165 //we can't mix an *H reg with a register that requires the REX prefix |
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166 ea->base = opts->regs[z80_low_reg(inst->ea_reg)]; |
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167 dst = ror_ir(dst, 8, ea->base, SZ_W); |
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168 } |
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169 } |
213
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170 } |
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171 break; |
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172 case Z80_REG_INDIRECT: |
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173 dst = mov_rr(dst, opts->regs[inst->ea_reg], areg, SZ_W); |
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174 size = z80_size(inst); |
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175 if (read) { |
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176 if (modify) { |
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177 //dst = push_r(dst, SCRATCH1); |
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178 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(z80_context, scratch1), SZ_W); |
213
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179 } |
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180 if (size == SZ_B) { |
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181 dst = call(dst, (uint8_t *)z80_read_byte); |
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182 } else { |
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183 dst = call(dst, (uint8_t *)z80_read_word); |
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184 } |
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185 if (modify) { |
277
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186 //dst = pop_r(dst, SCRATCH2); |
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187 dst = mov_rdisp8r(dst, CONTEXT, offsetof(z80_context, scratch1), SCRATCH2, SZ_W); |
213
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188 } |
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189 } |
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190 ea->base = SCRATCH1; |
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191 break; |
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192 case Z80_IMMED: |
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193 ea->mode = MODE_IMMED; |
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194 ea->disp = inst->immed; |
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195 break; |
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196 case Z80_IMMED_INDIRECT: |
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197 dst = mov_ir(dst, inst->immed, areg, SZ_W); |
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198 size = z80_size(inst); |
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199 if (read) { |
277
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200 /*if (modify) { |
213
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201 dst = push_r(dst, SCRATCH1); |
277
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202 }*/ |
213
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203 if (size == SZ_B) { |
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204 dst = call(dst, (uint8_t *)z80_read_byte); |
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205 } else { |
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206 dst = call(dst, (uint8_t *)z80_read_word); |
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207 } |
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208 if (modify) { |
277
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209 //dst = pop_r(dst, SCRATCH2); |
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210 dst = mov_ir(dst, inst->immed, SCRATCH2, SZ_W); |
213
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211 } |
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212 } |
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213 ea->base = SCRATCH1; |
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214 break; |
235
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215 case Z80_IX_DISPLACE: |
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216 case Z80_IY_DISPLACE: |
300
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217 reg = opts->regs[(inst->addr_mode & 0x1F) == Z80_IX_DISPLACE ? Z80_IX : Z80_IY]; |
213
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218 dst = mov_rr(dst, reg, areg, SZ_W); |
306
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219 dst = add_ir(dst, inst->ea_reg & 0x80 ? inst->ea_reg - 256 : inst->ea_reg, areg, SZ_W); |
213
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220 size = z80_size(inst); |
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221 if (read) { |
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222 if (modify) { |
277
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223 //dst = push_r(dst, SCRATCH1); |
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224 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(z80_context, scratch1), SZ_W); |
213
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225 } |
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226 if (size == SZ_B) { |
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227 dst = call(dst, (uint8_t *)z80_read_byte); |
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228 } else { |
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229 dst = call(dst, (uint8_t *)z80_read_word); |
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230 } |
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231 if (modify) { |
277
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232 //dst = pop_r(dst, SCRATCH2); |
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233 dst = mov_rdisp8r(dst, CONTEXT, offsetof(z80_context, scratch1), SCRATCH2, SZ_W); |
213
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234 } |
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235 } |
269
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236 ea->base = SCRATCH1; |
213
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237 break; |
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238 case Z80_UNUSED: |
235
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239 ea->mode = MODE_UNUSED; |
213
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240 break; |
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241 default: |
300
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242 fprintf(stderr, "Unrecognized Z80 addressing mode %d\n", inst->addr_mode & 0x1F); |
213
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243 exit(1); |
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244 } |
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245 return dst; |
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246 } |
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247 |
235
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248 uint8_t * z80_save_ea(uint8_t * dst, z80inst * inst, x86_z80_options * opts) |
213
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249 { |
267
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250 if ((inst->addr_mode & 0x1F) == Z80_REG) { |
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266
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251 if (inst->ea_reg == Z80_IYH) { |
312
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311
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252 if (inst->reg == Z80_IYL) { |
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253 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W); |
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254 dst = mov_rr(dst, SCRATCH1, opts->regs[Z80_IYL], SZ_B); |
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255 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W); |
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256 } else { |
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257 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W); |
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258 } |
267
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259 } else if (inst->reg != Z80_UNUSED && inst->reg != Z80_USE_IMMED && opts->regs[inst->ea_reg] >= AH && opts->regs[inst->ea_reg] <= BH) { |
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260 uint8_t other_reg = opts->regs[inst->reg]; |
269
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|
261 if (other_reg >= R8 || (other_reg >= RSP && other_reg <= RDI)) { |
267
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262 //we can't mix an *H reg with a register that requires the REX prefix |
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263 dst = ror_ir(dst, 8, opts->regs[z80_low_reg(inst->ea_reg)], SZ_W); |
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|
264 } |
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|
265 } |
213
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266 } |
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267 return dst; |
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268 } |
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269 |
235
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270 uint8_t * z80_save_result(uint8_t * dst, z80inst * inst) |
213
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271 { |
253
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272 switch(inst->addr_mode & 0x1f) |
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273 { |
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274 case Z80_REG_INDIRECT: |
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275 case Z80_IMMED_INDIRECT: |
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276 case Z80_IX_DISPLACE: |
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277 case Z80_IY_DISPLACE: |
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278 if (z80_size(inst) == SZ_B) { |
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279 dst = call(dst, (uint8_t *)z80_write_byte); |
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280 } else { |
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281 dst = call(dst, (uint8_t *)z80_write_word_lowfirst); |
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282 } |
213
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283 } |
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284 return dst; |
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285 } |
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286 |
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287 enum { |
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288 DONT_READ=0, |
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|
289 READ |
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290 }; |
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291 |
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|
292 enum { |
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293 DONT_MODIFY=0, |
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294 MODIFY |
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295 }; |
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296 |
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|
297 uint8_t zf_off(uint8_t flag) |
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298 { |
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299 return offsetof(z80_context, flags) + flag; |
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300 } |
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301 |
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302 uint8_t zaf_off(uint8_t flag) |
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303 { |
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304 return offsetof(z80_context, alt_flags) + flag; |
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305 } |
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306 |
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307 uint8_t zar_off(uint8_t reg) |
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308 { |
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309 return offsetof(z80_context, alt_regs) + reg; |
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310 } |
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311 |
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312 void z80_print_regs_exit(z80_context * context) |
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313 { |
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314 printf("A: %X\nB: %X\nC: %X\nD: %X\nE: %X\nHL: %X\nIX: %X\nIY: %X\nSP: %X\n\nIM: %d, IFF1: %d, IFF2: %d\n", |
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315 context->regs[Z80_A], context->regs[Z80_B], context->regs[Z80_C], |
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316 context->regs[Z80_D], context->regs[Z80_E], |
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317 (context->regs[Z80_H] << 8) | context->regs[Z80_L], |
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318 (context->regs[Z80_IXH] << 8) | context->regs[Z80_IXL], |
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319 (context->regs[Z80_IYH] << 8) | context->regs[Z80_IYL], |
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320 context->sp, context->im, context->iff1, context->iff2); |
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321 puts("--Alternate Regs--"); |
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322 printf("A: %X\nB: %X\nC: %X\nD: %X\nE: %X\nHL: %X\nIX: %X\nIY: %X\n", |
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323 context->alt_regs[Z80_A], context->alt_regs[Z80_B], context->alt_regs[Z80_C], |
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324 context->alt_regs[Z80_D], context->alt_regs[Z80_E], |
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325 (context->alt_regs[Z80_H] << 8) | context->alt_regs[Z80_L], |
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326 (context->alt_regs[Z80_IXH] << 8) | context->alt_regs[Z80_IXL], |
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327 (context->alt_regs[Z80_IYH] << 8) | context->alt_regs[Z80_IYL]); |
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328 exit(0); |
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329 } |
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330 |
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331 uint8_t * translate_z80inst(z80inst * inst, uint8_t * dst, z80_context * context, uint16_t address) |
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332 { |
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333 uint32_t cycles; |
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334 x86_ea src_op, dst_op; |
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335 uint8_t size; |
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336 x86_z80_options *opts = context->options; |
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337 uint8_t * start = dst; |
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338 dst = z80_check_cycles_int(dst, address); |
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339 if (context->breakpoint_flags[address / sizeof(uint8_t)] & (1 << (address % sizeof(uint8_t)))) { |
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340 zbreakpoint_patch(context, address, start); |
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341 } |
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342 switch(inst->op) |
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343 { |
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344 case Z80_LD: |
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345 size = z80_size(inst); |
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346 switch (inst->addr_mode & 0x1F) |
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347 { |
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348 case Z80_REG: |
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349 case Z80_REG_INDIRECT: |
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350 cycles = size == SZ_B ? 4 : 6; |
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351 if (inst->ea_reg == Z80_IX || inst->ea_reg == Z80_IY) { |
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352 cycles += 4; |
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353 } |
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354 if (inst->reg == Z80_I || inst->ea_reg == Z80_I) { |
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355 cycles += 5; |
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356 } |
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357 break; |
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358 case Z80_IMMED: |
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359 cycles = size == SZ_B ? 7 : 10; |
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360 break; |
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361 case Z80_IMMED_INDIRECT: |
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362 cycles = 10; |
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363 break; |
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364 case Z80_IX_DISPLACE: |
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365 case Z80_IY_DISPLACE: |
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366 cycles = 16; |
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367 break; |
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368 } |
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369 if ((inst->reg >= Z80_IXL && inst->reg <= Z80_IYH) || inst->reg == Z80_IX || inst->reg == Z80_IY) { |
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370 cycles += 4; |
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371 } |
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372 dst = zcycles(dst, cycles); |
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373 if (inst->addr_mode & Z80_DIR) { |
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374 dst = translate_z80_ea(inst, &dst_op, dst, opts, DONT_READ, MODIFY); |
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375 dst = translate_z80_reg(inst, &src_op, dst, opts); |
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376 } else { |
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377 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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378 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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379 } |
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380 if (src_op.mode == MODE_REG_DIRECT) { |
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381 if(dst_op.mode == MODE_REG_DISPLACE8) { |
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382 dst = mov_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, size); |
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383 } else { |
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384 dst = mov_rr(dst, src_op.base, dst_op.base, size); |
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385 } |
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386 } else if(src_op.mode == MODE_IMMED) { |
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387 dst = mov_ir(dst, src_op.disp, dst_op.base, size); |
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388 } else { |
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389 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, size); |
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390 } |
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391 dst = z80_save_reg(dst, inst, opts); |
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392 dst = z80_save_ea(dst, inst, opts); |
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393 if (inst->addr_mode & Z80_DIR) { |
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394 dst = z80_save_result(dst, inst); |
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395 } |
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396 break; |
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397 case Z80_PUSH: |
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398 dst = zcycles(dst, (inst->reg == Z80_IX || inst->reg == Z80_IY) ? 9 : 5); |
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399 dst = sub_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
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400 if (inst->reg == Z80_AF) { |
363 | 401 dst = mov_rr(dst, opts->regs[Z80_A], SCRATCH1, SZ_B); |
402 dst = shl_ir(dst, 8, SCRATCH1, SZ_W); | |
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403 dst = mov_rdisp8r(dst, CONTEXT, zf_off(ZF_S), SCRATCH1, SZ_B); |
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404 dst = shl_ir(dst, 1, SCRATCH1, SZ_B); |
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405 dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_Z), SCRATCH1, SZ_B); |
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406 dst = shl_ir(dst, 2, SCRATCH1, SZ_B); |
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407 dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_H), SCRATCH1, SZ_B); |
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408 dst = shl_ir(dst, 2, SCRATCH1, SZ_B); |
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409 dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_PV), SCRATCH1, SZ_B); |
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410 dst = shl_ir(dst, 1, SCRATCH1, SZ_B); |
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411 dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_N), SCRATCH1, SZ_B); |
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412 dst = shl_ir(dst, 1, SCRATCH1, SZ_B); |
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413 dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_C), SCRATCH1, SZ_B); |
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414 } else { |
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415 dst = translate_z80_reg(inst, &src_op, dst, opts); |
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416 dst = mov_rr(dst, src_op.base, SCRATCH1, SZ_W); |
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417 } |
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418 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W); |
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419 dst = call(dst, (uint8_t *)z80_write_word_highfirst); |
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420 //no call to save_z80_reg needed since there's no chance we'll use the only |
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421 //the upper half of a register pair |
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422 break; |
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423 case Z80_POP: |
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424 dst = zcycles(dst, (inst->reg == Z80_IX || inst->reg == Z80_IY) ? 8 : 4); |
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425 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
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426 dst = call(dst, (uint8_t *)z80_read_word); |
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427 dst = add_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
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428 if (inst->reg == Z80_AF) { |
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429 |
294 | 430 dst = bt_ir(dst, 0, SCRATCH1, SZ_W); |
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431 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
294 | 432 dst = bt_ir(dst, 1, SCRATCH1, SZ_W); |
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433 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_N)); |
294 | 434 dst = bt_ir(dst, 2, SCRATCH1, SZ_W); |
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435 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_PV)); |
294 | 436 dst = bt_ir(dst, 4, SCRATCH1, SZ_W); |
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437 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_H)); |
294 | 438 dst = bt_ir(dst, 6, SCRATCH1, SZ_W); |
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439 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_Z)); |
294 | 440 dst = bt_ir(dst, 7, SCRATCH1, SZ_W); |
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441 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_S)); |
294 | 442 dst = shr_ir(dst, 8, SCRATCH1, SZ_W); |
443 dst = mov_rr(dst, SCRATCH1, opts->regs[Z80_A], SZ_B); | |
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444 } else { |
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445 dst = translate_z80_reg(inst, &src_op, dst, opts); |
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446 dst = mov_rr(dst, SCRATCH1, src_op.base, SZ_W); |
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447 } |
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448 //no call to save_z80_reg needed since there's no chance we'll use the only |
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449 //the upper half of a register pair |
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450 break; |
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451 case Z80_EX: |
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452 if (inst->addr_mode == Z80_REG || inst->reg == Z80_HL) { |
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453 cycles = 4; |
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454 } else { |
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455 cycles = 8; |
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456 } |
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457 dst = zcycles(dst, cycles); |
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458 if (inst->addr_mode == Z80_REG) { |
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459 if(inst->reg == Z80_AF) { |
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460 dst = mov_rr(dst, opts->regs[Z80_A], SCRATCH1, SZ_B); |
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461 dst = mov_rdisp8r(dst, CONTEXT, zar_off(Z80_A), opts->regs[Z80_A], SZ_B); |
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462 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, zar_off(Z80_A), SZ_B); |
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463 |
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464 //Flags are currently word aligned, so we can move |
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465 //them efficiently a word at a time |
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466 for (int f = ZF_C; f < ZF_NUM; f+=2) { |
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467 dst = mov_rdisp8r(dst, CONTEXT, zf_off(f), SCRATCH1, SZ_W); |
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468 dst = mov_rdisp8r(dst, CONTEXT, zaf_off(f), SCRATCH2, SZ_W); |
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469 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, zaf_off(f), SZ_W); |
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470 dst = mov_rrdisp8(dst, SCRATCH2, CONTEXT, zf_off(f), SZ_W); |
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471 } |
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472 } else { |
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473 dst = xchg_rr(dst, opts->regs[Z80_DE], opts->regs[Z80_HL], SZ_W); |
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474 } |
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475 } else { |
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476 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
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477 dst = call(dst, (uint8_t *)z80_read_byte); |
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478 dst = xchg_rr(dst, opts->regs[inst->reg], SCRATCH1, SZ_B); |
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479 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W); |
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480 dst = call(dst, (uint8_t *)z80_write_byte); |
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481 dst = zcycles(dst, 1); |
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482 uint8_t high_reg = z80_high_reg(inst->reg); |
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483 uint8_t use_reg; |
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484 //even though some of the upper halves can be used directly |
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485 //the limitations on mixing *H regs with the REX prefix |
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486 //prevent us from taking advantage of it |
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487 use_reg = opts->regs[inst->reg]; |
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488 dst = ror_ir(dst, 8, use_reg, SZ_W); |
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489 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
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490 dst = add_ir(dst, 1, SCRATCH1, SZ_W); |
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491 dst = call(dst, (uint8_t *)z80_read_byte); |
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492 dst = xchg_rr(dst, use_reg, SCRATCH1, SZ_B); |
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493 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W); |
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494 dst = add_ir(dst, 1, SCRATCH2, SZ_W); |
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495 dst = call(dst, (uint8_t *)z80_write_byte); |
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496 //restore reg to normal rotation |
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497 dst = ror_ir(dst, 8, use_reg, SZ_W); |
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498 dst = zcycles(dst, 2); |
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499 } |
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500 break; |
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501 case Z80_EXX: |
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502 dst = zcycles(dst, 4); |
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503 dst = mov_rr(dst, opts->regs[Z80_BC], SCRATCH1, SZ_W); |
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504 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH2, SZ_W); |
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505 dst = mov_rdisp8r(dst, CONTEXT, zar_off(Z80_C), opts->regs[Z80_BC], SZ_W); |
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506 dst = mov_rdisp8r(dst, CONTEXT, zar_off(Z80_L), opts->regs[Z80_HL], SZ_W); |
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507 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, zar_off(Z80_C), SZ_W); |
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508 dst = mov_rrdisp8(dst, SCRATCH2, CONTEXT, zar_off(Z80_L), SZ_W); |
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509 dst = mov_rr(dst, opts->regs[Z80_DE], SCRATCH1, SZ_W); |
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510 dst = mov_rdisp8r(dst, CONTEXT, zar_off(Z80_E), opts->regs[Z80_DE], SZ_W); |
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511 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, zar_off(Z80_E), SZ_W); |
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512 break; |
272 | 513 case Z80_LDI: { |
514 dst = zcycles(dst, 8); | |
515 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH1, SZ_W); | |
516 dst = call(dst, (uint8_t *)z80_read_byte); | |
517 dst = mov_rr(dst, opts->regs[Z80_DE], SCRATCH2, SZ_W); | |
385 | 518 dst = call(dst, (uint8_t *)z80_write_byte); |
272 | 519 dst = zcycles(dst, 2); |
520 dst = add_ir(dst, 1, opts->regs[Z80_DE], SZ_W); | |
521 dst = add_ir(dst, 1, opts->regs[Z80_HL], SZ_W); | |
522 dst = sub_ir(dst, 1, opts->regs[Z80_BC], SZ_W); | |
523 //TODO: Implement half-carry | |
524 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); | |
525 dst = setcc_rdisp8(dst, CC_NZ, CONTEXT, zf_off(ZF_PV)); | |
526 break; | |
527 } | |
261
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528 case Z80_LDIR: { |
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529 dst = zcycles(dst, 8); |
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530 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH1, SZ_W); |
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531 dst = call(dst, (uint8_t *)z80_read_byte); |
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532 dst = mov_rr(dst, opts->regs[Z80_DE], SCRATCH2, SZ_W); |
397 | 533 dst = call(dst, (uint8_t *)z80_write_byte); |
261
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534 dst = add_ir(dst, 1, opts->regs[Z80_DE], SZ_W); |
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535 dst = add_ir(dst, 1, opts->regs[Z80_HL], SZ_W); |
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536 |
261
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537 dst = sub_ir(dst, 1, opts->regs[Z80_BC], SZ_W); |
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538 uint8_t * cont = dst+1; |
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539 dst = jcc(dst, CC_Z, dst+2); |
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540 dst = zcycles(dst, 7); |
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541 //TODO: Figure out what the flag state should be here |
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542 //TODO: Figure out whether an interrupt can interrupt this |
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543 dst = jmp(dst, start); |
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544 *cont = dst - (cont + 1); |
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545 dst = zcycles(dst, 2); |
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546 //TODO: Implement half-carry |
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547 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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548 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_PV), SZ_B); |
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549 break; |
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550 } |
273 | 551 case Z80_LDD: { |
552 dst = zcycles(dst, 8); | |
553 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH1, SZ_W); | |
554 dst = call(dst, (uint8_t *)z80_read_byte); | |
555 dst = mov_rr(dst, opts->regs[Z80_DE], SCRATCH2, SZ_W); | |
388 | 556 dst = call(dst, (uint8_t *)z80_write_byte); |
273 | 557 dst = zcycles(dst, 2); |
558 dst = sub_ir(dst, 1, opts->regs[Z80_DE], SZ_W); | |
559 dst = sub_ir(dst, 1, opts->regs[Z80_HL], SZ_W); | |
560 dst = sub_ir(dst, 1, opts->regs[Z80_BC], SZ_W); | |
561 //TODO: Implement half-carry | |
562 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); | |
563 dst = setcc_rdisp8(dst, CC_NZ, CONTEXT, zf_off(ZF_PV)); | |
564 break; | |
565 } | |
566 case Z80_LDDR: { | |
567 dst = zcycles(dst, 8); | |
568 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH1, SZ_W); | |
569 dst = call(dst, (uint8_t *)z80_read_byte); | |
570 dst = mov_rr(dst, opts->regs[Z80_DE], SCRATCH2, SZ_W); | |
388 | 571 dst = call(dst, (uint8_t *)z80_write_byte); |
273 | 572 dst = sub_ir(dst, 1, opts->regs[Z80_DE], SZ_W); |
573 dst = sub_ir(dst, 1, opts->regs[Z80_HL], SZ_W); | |
505
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574 |
273 | 575 dst = sub_ir(dst, 1, opts->regs[Z80_BC], SZ_W); |
576 uint8_t * cont = dst+1; | |
577 dst = jcc(dst, CC_Z, dst+2); | |
578 dst = zcycles(dst, 7); | |
579 //TODO: Figure out what the flag state should be here | |
580 //TODO: Figure out whether an interrupt can interrupt this | |
581 dst = jmp(dst, start); | |
582 *cont = dst - (cont + 1); | |
583 dst = zcycles(dst, 2); | |
584 //TODO: Implement half-carry | |
585 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); | |
586 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_PV), SZ_B); | |
587 break; | |
588 } | |
589 /*case Z80_CPI: | |
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590 case Z80_CPIR: |
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591 case Z80_CPD: |
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592 case Z80_CPDR: |
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593 break;*/ |
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594 case Z80_ADD: |
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595 cycles = 4; |
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596 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
213
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597 cycles += 12; |
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598 } else if(inst->addr_mode == Z80_IMMED) { |
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599 cycles += 3; |
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600 } else if(z80_size(inst) == SZ_W) { |
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601 cycles += 4; |
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602 } |
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603 dst = zcycles(dst, cycles); |
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604 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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605 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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606 if (src_op.mode == MODE_REG_DIRECT) { |
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607 dst = add_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
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608 } else { |
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609 dst = add_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
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610 } |
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611 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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612 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
213
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613 //TODO: Implement half-carry flag |
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614 if (z80_size(inst) == SZ_B) { |
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615 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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616 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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617 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
213
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618 } |
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619 dst = z80_save_reg(dst, inst, opts); |
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620 dst = z80_save_ea(dst, inst, opts); |
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621 break; |
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622 case Z80_ADC: |
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623 cycles = 4; |
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624 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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625 cycles += 12; |
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626 } else if(inst->addr_mode == Z80_IMMED) { |
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627 cycles += 3; |
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628 } else if(z80_size(inst) == SZ_W) { |
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629 cycles += 4; |
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630 } |
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631 dst = zcycles(dst, cycles); |
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632 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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633 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
399 | 634 dst = bt_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
248
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635 if (src_op.mode == MODE_REG_DIRECT) { |
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636 dst = adc_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
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637 } else { |
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638 dst = adc_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
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639 } |
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640 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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641 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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642 //TODO: Implement half-carry flag |
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643 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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644 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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645 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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646 dst = z80_save_reg(dst, inst, opts); |
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647 dst = z80_save_ea(dst, inst, opts); |
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648 break; |
213
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|
649 case Z80_SUB: |
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650 cycles = 4; |
235
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651 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
213
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652 cycles += 12; |
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653 } else if(inst->addr_mode == Z80_IMMED) { |
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654 cycles += 3; |
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655 } |
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|
656 dst = zcycles(dst, cycles); |
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|
657 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
4d4559b04c59
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658 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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659 if (src_op.mode == MODE_REG_DIRECT) { |
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660 dst = sub_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
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661 } else { |
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662 dst = sub_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
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663 } |
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664 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
235
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665 dst = mov_irdisp8(dst, 1, CONTEXT, zf_off(ZF_N), SZ_B); |
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666 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
213
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667 //TODO: Implement half-carry flag |
235
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668 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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669 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
213
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670 dst = z80_save_reg(dst, inst, opts); |
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671 dst = z80_save_ea(dst, inst, opts); |
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672 break; |
248
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673 case Z80_SBC: |
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674 cycles = 4; |
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675 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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676 cycles += 12; |
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677 } else if(inst->addr_mode == Z80_IMMED) { |
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678 cycles += 3; |
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679 } else if(z80_size(inst) == SZ_W) { |
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680 cycles += 4; |
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681 } |
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682 dst = zcycles(dst, cycles); |
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683 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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684 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
399 | 685 dst = bt_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
248
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686 if (src_op.mode == MODE_REG_DIRECT) { |
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687 dst = sbb_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
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688 } else { |
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689 dst = sbb_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
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690 } |
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691 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
309
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308
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|
692 dst = mov_irdisp8(dst, 1, CONTEXT, zf_off(ZF_N), SZ_B); |
248
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693 //TODO: Implement half-carry flag |
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694 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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695 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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696 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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697 dst = z80_save_reg(dst, inst, opts); |
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698 dst = z80_save_ea(dst, inst, opts); |
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699 break; |
213
4d4559b04c59
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|
700 case Z80_AND: |
236
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|
701 cycles = 4; |
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|
702 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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703 cycles += 12; |
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|
704 } else if(inst->addr_mode == Z80_IMMED) { |
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|
705 cycles += 3; |
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706 } else if(z80_size(inst) == SZ_W) { |
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|
707 cycles += 4; |
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|
708 } |
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|
709 dst = zcycles(dst, cycles); |
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|
710 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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diff
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|
711 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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|
712 if (src_op.mode == MODE_REG_DIRECT) { |
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|
713 dst = and_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
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235
diff
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|
714 } else { |
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diff
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|
715 dst = and_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
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|
716 } |
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|
717 //TODO: Cleanup flags |
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diff
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|
718 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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|
719 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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diff
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|
720 //TODO: Implement half-carry flag |
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235
diff
changeset
|
721 if (z80_size(inst) == SZ_B) { |
305
a57fac5b3d65
Contrary to the official documenation, OR and AND also set PV based on parity instead of overflow
Mike Pavone <pavone@retrodev.com>
parents:
304
diff
changeset
|
722 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
236
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parents:
235
diff
changeset
|
723 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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235
diff
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|
724 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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235
diff
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|
725 } |
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235
diff
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|
726 dst = z80_save_reg(dst, inst, opts); |
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235
diff
changeset
|
727 dst = z80_save_ea(dst, inst, opts); |
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235
diff
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|
728 break; |
213
4d4559b04c59
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
729 case Z80_OR: |
236
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235
diff
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|
730 cycles = 4; |
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235
diff
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|
731 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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235
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|
732 cycles += 12; |
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235
diff
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|
733 } else if(inst->addr_mode == Z80_IMMED) { |
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parents:
235
diff
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|
734 cycles += 3; |
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235
diff
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|
735 } else if(z80_size(inst) == SZ_W) { |
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diff
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|
736 cycles += 4; |
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235
diff
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|
737 } |
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235
diff
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|
738 dst = zcycles(dst, cycles); |
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235
diff
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|
739 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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235
diff
changeset
|
740 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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235
diff
changeset
|
741 if (src_op.mode == MODE_REG_DIRECT) { |
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235
diff
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|
742 dst = or_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
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743 } else { |
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744 dst = or_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
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745 } |
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746 //TODO: Cleanup flags |
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747 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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748 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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749 //TODO: Implement half-carry flag |
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750 if (z80_size(inst) == SZ_B) { |
305
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751 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
236
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752 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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753 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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754 } |
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755 dst = z80_save_reg(dst, inst, opts); |
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756 dst = z80_save_ea(dst, inst, opts); |
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757 break; |
213
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758 case Z80_XOR: |
236
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759 cycles = 4; |
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760 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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761 cycles += 12; |
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762 } else if(inst->addr_mode == Z80_IMMED) { |
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763 cycles += 3; |
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764 } else if(z80_size(inst) == SZ_W) { |
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765 cycles += 4; |
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766 } |
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767 dst = zcycles(dst, cycles); |
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768 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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769 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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770 if (src_op.mode == MODE_REG_DIRECT) { |
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771 dst = xor_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
236
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772 } else { |
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773 dst = xor_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
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774 } |
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775 //TODO: Cleanup flags |
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776 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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777 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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778 //TODO: Implement half-carry flag |
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779 if (z80_size(inst) == SZ_B) { |
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780 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
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781 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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782 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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783 } |
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784 dst = z80_save_reg(dst, inst, opts); |
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785 dst = z80_save_ea(dst, inst, opts); |
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786 break; |
242 | 787 case Z80_CP: |
788 cycles = 4; | |
789 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { | |
790 cycles += 12; | |
791 } else if(inst->addr_mode == Z80_IMMED) { | |
792 cycles += 3; | |
793 } | |
794 dst = zcycles(dst, cycles); | |
795 dst = translate_z80_reg(inst, &dst_op, dst, opts); | |
796 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); | |
797 if (src_op.mode == MODE_REG_DIRECT) { | |
798 dst = cmp_rr(dst, src_op.base, dst_op.base, z80_size(inst)); | |
799 } else { | |
800 dst = cmp_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); | |
801 } | |
802 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); | |
803 dst = mov_irdisp8(dst, 1, CONTEXT, zf_off(ZF_N), SZ_B); | |
804 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); | |
805 //TODO: Implement half-carry flag | |
806 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); | |
807 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); | |
808 dst = z80_save_reg(dst, inst, opts); | |
809 dst = z80_save_ea(dst, inst, opts); | |
810 break; | |
213
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811 case Z80_INC: |
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812 cycles = 4; |
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813 if (inst->reg == Z80_IX || inst->reg == Z80_IY) { |
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814 cycles += 6; |
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815 } else if(z80_size(inst) == SZ_W) { |
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|
816 cycles += 2; |
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817 } else if(inst->reg == Z80_IXH || inst->reg == Z80_IXL || inst->reg == Z80_IYH || inst->reg == Z80_IYL || inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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|
818 cycles += 4; |
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819 } |
373
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|
820 dst = zcycles(dst, cycles); |
213
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|
821 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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|
822 if (dst_op.mode == MODE_UNUSED) { |
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823 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
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|
824 } |
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825 dst = add_ir(dst, 1, dst_op.base, z80_size(inst)); |
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|
826 if (z80_size(inst) == SZ_B) { |
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827 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
213
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|
828 //TODO: Implement half-carry flag |
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829 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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830 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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831 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
213
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changeset
|
832 } |
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diff
changeset
|
833 dst = z80_save_reg(dst, inst, opts); |
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|
834 dst = z80_save_ea(dst, inst, opts); |
387
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|
835 dst = z80_save_result(dst, inst); |
213
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|
836 break; |
236
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837 case Z80_DEC: |
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838 cycles = 4; |
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839 if (inst->reg == Z80_IX || inst->reg == Z80_IY) { |
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840 cycles += 6; |
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841 } else if(z80_size(inst) == SZ_W) { |
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842 cycles += 2; |
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843 } else if(inst->reg == Z80_IXH || inst->reg == Z80_IXL || inst->reg == Z80_IYH || inst->reg == Z80_IYL || inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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844 cycles += 4; |
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845 } |
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|
846 dst = zcycles(dst, cycles); |
236
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847 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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848 if (dst_op.mode == MODE_UNUSED) { |
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849 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
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850 } |
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851 dst = sub_ir(dst, 1, dst_op.base, z80_size(inst)); |
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852 if (z80_size(inst) == SZ_B) { |
311
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310
diff
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|
853 dst = mov_irdisp8(dst, 1, CONTEXT, zf_off(ZF_N), SZ_B); |
236
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854 //TODO: Implement half-carry flag |
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855 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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856 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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857 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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858 } |
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859 dst = z80_save_reg(dst, inst, opts); |
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860 dst = z80_save_ea(dst, inst, opts); |
387
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|
861 dst = z80_save_result(dst, inst); |
213
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|
862 break; |
274
be2b845d3e94
Implement CPL and NEG (untested)
Mike Pavone <pavone@retrodev.com>
parents:
273
diff
changeset
|
863 //case Z80_DAA: |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
864 case Z80_CPL: |
274
be2b845d3e94
Implement CPL and NEG (untested)
Mike Pavone <pavone@retrodev.com>
parents:
273
diff
changeset
|
865 dst = zcycles(dst, 4); |
be2b845d3e94
Implement CPL and NEG (untested)
Mike Pavone <pavone@retrodev.com>
parents:
273
diff
changeset
|
866 dst = not_r(dst, opts->regs[Z80_A], SZ_B); |
be2b845d3e94
Implement CPL and NEG (untested)
Mike Pavone <pavone@retrodev.com>
parents:
273
diff
changeset
|
867 //TODO: Implement half-carry flag |
be2b845d3e94
Implement CPL and NEG (untested)
Mike Pavone <pavone@retrodev.com>
parents:
273
diff
changeset
|
868 dst = mov_irdisp8(dst, 1, CONTEXT, zf_off(ZF_N), SZ_B); |
be2b845d3e94
Implement CPL and NEG (untested)
Mike Pavone <pavone@retrodev.com>
parents:
273
diff
changeset
|
869 break; |
be2b845d3e94
Implement CPL and NEG (untested)
Mike Pavone <pavone@retrodev.com>
parents:
273
diff
changeset
|
870 case Z80_NEG: |
be2b845d3e94
Implement CPL and NEG (untested)
Mike Pavone <pavone@retrodev.com>
parents:
273
diff
changeset
|
871 dst = zcycles(dst, 8); |
be2b845d3e94
Implement CPL and NEG (untested)
Mike Pavone <pavone@retrodev.com>
parents:
273
diff
changeset
|
872 dst = neg_r(dst, opts->regs[Z80_A], SZ_B); |
be2b845d3e94
Implement CPL and NEG (untested)
Mike Pavone <pavone@retrodev.com>
parents:
273
diff
changeset
|
873 //TODO: Implement half-carry flag |
be2b845d3e94
Implement CPL and NEG (untested)
Mike Pavone <pavone@retrodev.com>
parents:
273
diff
changeset
|
874 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
be2b845d3e94
Implement CPL and NEG (untested)
Mike Pavone <pavone@retrodev.com>
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273
diff
changeset
|
875 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
be2b845d3e94
Implement CPL and NEG (untested)
Mike Pavone <pavone@retrodev.com>
parents:
273
diff
changeset
|
876 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
be2b845d3e94
Implement CPL and NEG (untested)
Mike Pavone <pavone@retrodev.com>
parents:
273
diff
changeset
|
877 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
be2b845d3e94
Implement CPL and NEG (untested)
Mike Pavone <pavone@retrodev.com>
parents:
273
diff
changeset
|
878 dst = mov_irdisp8(dst, 1, CONTEXT, zf_off(ZF_N), SZ_B); |
be2b845d3e94
Implement CPL and NEG (untested)
Mike Pavone <pavone@retrodev.com>
parents:
273
diff
changeset
|
879 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
880 case Z80_CCF: |
257 | 881 dst = zcycles(dst, 4); |
882 dst = xor_irdisp8(dst, 1, CONTEXT, zf_off(ZF_C), SZ_B); | |
883 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); | |
884 //TODO: Implement half-carry flag | |
885 break; | |
886 case Z80_SCF: | |
887 dst = zcycles(dst, 4); | |
888 dst = mov_irdisp8(dst, 1, CONTEXT, zf_off(ZF_C), SZ_B); | |
889 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); | |
890 //TODO: Implement half-carry flag | |
891 break; | |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
892 case Z80_NOP: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
893 if (inst->immed == 42) { |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
894 dst = call(dst, (uint8_t *)z80_save_context); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
895 dst = mov_rr(dst, CONTEXT, RDI, SZ_Q); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
896 dst = jmp(dst, (uint8_t *)z80_print_regs_exit); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
897 } else { |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
898 dst = zcycles(dst, 4 * inst->immed); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
899 } |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
900 break; |
285
021aeb6df19b
Implement HALT (sort of tested)
Mike Pavone <pavone@retrodev.com>
parents:
284
diff
changeset
|
901 case Z80_HALT: |
021aeb6df19b
Implement HALT (sort of tested)
Mike Pavone <pavone@retrodev.com>
parents:
284
diff
changeset
|
902 dst = zcycles(dst, 4); |
021aeb6df19b
Implement HALT (sort of tested)
Mike Pavone <pavone@retrodev.com>
parents:
284
diff
changeset
|
903 dst = mov_ir(dst, address, SCRATCH1, SZ_W); |
021aeb6df19b
Implement HALT (sort of tested)
Mike Pavone <pavone@retrodev.com>
parents:
284
diff
changeset
|
904 uint8_t * call_inst = dst; |
021aeb6df19b
Implement HALT (sort of tested)
Mike Pavone <pavone@retrodev.com>
parents:
284
diff
changeset
|
905 dst = call(dst, (uint8_t *)z80_halt); |
021aeb6df19b
Implement HALT (sort of tested)
Mike Pavone <pavone@retrodev.com>
parents:
284
diff
changeset
|
906 dst = jmp(dst, call_inst); |
021aeb6df19b
Implement HALT (sort of tested)
Mike Pavone <pavone@retrodev.com>
parents:
284
diff
changeset
|
907 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
908 case Z80_DI: |
243
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
909 dst = zcycles(dst, 4); |
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
910 dst = mov_irdisp8(dst, 0, CONTEXT, offsetof(z80_context, iff1), SZ_B); |
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
911 dst = mov_irdisp8(dst, 0, CONTEXT, offsetof(z80_context, iff2), SZ_B); |
250
5f1b68cecfc7
Implemented basic interrupt support in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
248
diff
changeset
|
912 dst = mov_rdisp8r(dst, CONTEXT, offsetof(z80_context, sync_cycle), ZLIMIT, SZ_D); |
401 | 913 dst = mov_irdisp8(dst, 0xFFFFFFFF, CONTEXT, offsetof(z80_context, int_cycle), SZ_D); |
243
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
914 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
915 case Z80_EI: |
243
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
916 dst = zcycles(dst, 4); |
420
9fb111b5641f
Fix access to int_enable_cycle in EI
Mike Pavone <pavone@retrodev.com>
parents:
401
diff
changeset
|
917 dst = mov_rrdisp32(dst, ZCYCLES, CONTEXT, offsetof(z80_context, int_enable_cycle), SZ_D); |
243
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
918 dst = mov_irdisp8(dst, 1, CONTEXT, offsetof(z80_context, iff1), SZ_B); |
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
919 dst = mov_irdisp8(dst, 1, CONTEXT, offsetof(z80_context, iff2), SZ_B); |
335 | 920 //interrupt enable has a one-instruction latency, minimum instruction duration is 4 cycles |
420
9fb111b5641f
Fix access to int_enable_cycle in EI
Mike Pavone <pavone@retrodev.com>
parents:
401
diff
changeset
|
921 dst = add_irdisp32(dst, 4, CONTEXT, offsetof(z80_context, int_enable_cycle), SZ_D); |
250
5f1b68cecfc7
Implemented basic interrupt support in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
248
diff
changeset
|
922 dst = call(dst, (uint8_t *)z80_do_sync); |
243
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
923 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
924 case Z80_IM: |
243
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
925 dst = zcycles(dst, 4); |
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
926 dst = mov_irdisp8(dst, inst->immed, CONTEXT, offsetof(z80_context, im), SZ_B); |
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
927 break; |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
928 case Z80_RLC: |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
929 cycles = inst->immed == 0 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8); |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
930 dst = zcycles(dst, cycles); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
931 if (inst->addr_mode != Z80_UNUSED) { |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
932 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
933 dst = translate_z80_reg(inst, &src_op, dst, opts); //For IX/IY variants that also write to a register |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
934 dst = zcycles(dst, 1); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
935 } else { |
302
3b831fe32c15
More fixes for confusion between Z80_UNUSED and MODE_UNUSED
Mike Pavone <pavone@retrodev.com>
parents:
301
diff
changeset
|
936 src_op.mode = MODE_UNUSED; |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
937 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
938 } |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
939 dst = rol_ir(dst, 1, dst_op.base, SZ_B); |
301
6e15509a1257
Compare src_op.mode with the correct constant in shift/rotate instructions
Mike Pavone <pavone@retrodev.com>
parents:
300
diff
changeset
|
940 if (src_op.mode != MODE_UNUSED) { |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
941 dst = mov_rr(dst, dst_op.base, src_op.base, SZ_B); |
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
942 } |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
943 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
944 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
945 //TODO: Implement half-carry flag |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
946 dst = cmp_ir(dst, 0, dst_op.base, SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
947 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
948 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
949 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
950 if (inst->addr_mode != Z80_UNUSED) { |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
951 dst = z80_save_result(dst, inst); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
952 if (src_op.mode != MODE_UNUSED) { |
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
953 dst = z80_save_reg(dst, inst, opts); |
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
954 } |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
955 } else { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
956 dst = z80_save_reg(dst, inst, opts); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
957 } |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
958 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
959 case Z80_RL: |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
960 cycles = inst->immed == 0 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8); |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
961 dst = zcycles(dst, cycles); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
962 if (inst->addr_mode != Z80_UNUSED) { |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
963 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
964 dst = translate_z80_reg(inst, &src_op, dst, opts); //For IX/IY variants that also write to a register |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
965 dst = zcycles(dst, 1); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
966 } else { |
302
3b831fe32c15
More fixes for confusion between Z80_UNUSED and MODE_UNUSED
Mike Pavone <pavone@retrodev.com>
parents:
301
diff
changeset
|
967 src_op.mode = MODE_UNUSED; |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
968 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
969 } |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
970 dst = bt_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
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246
diff
changeset
|
971 dst = rcl_ir(dst, 1, dst_op.base, SZ_B); |
301
6e15509a1257
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Mike Pavone <pavone@retrodev.com>
parents:
300
diff
changeset
|
972 if (src_op.mode != MODE_UNUSED) { |
299
42e1a986f2d0
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Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
973 dst = mov_rr(dst, dst_op.base, src_op.base, SZ_B); |
42e1a986f2d0
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Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
974 } |
247
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Mike Pavone <pavone@retrodev.com>
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246
diff
changeset
|
975 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
682e505f5757
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diff
changeset
|
976 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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246
diff
changeset
|
977 //TODO: Implement half-carry flag |
682e505f5757
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changeset
|
978 dst = cmp_ir(dst, 0, dst_op.base, SZ_B); |
682e505f5757
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parents:
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diff
changeset
|
979 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
682e505f5757
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diff
changeset
|
980 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
682e505f5757
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diff
changeset
|
981 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
982 if (inst->addr_mode != Z80_UNUSED) { |
247
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
983 dst = z80_save_result(dst, inst); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
984 if (src_op.mode != MODE_UNUSED) { |
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
985 dst = z80_save_reg(dst, inst, opts); |
42e1a986f2d0
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Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
986 } |
247
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Mike Pavone <pavone@retrodev.com>
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246
diff
changeset
|
987 } else { |
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Mike Pavone <pavone@retrodev.com>
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246
diff
changeset
|
988 dst = z80_save_reg(dst, inst, opts); |
682e505f5757
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246
diff
changeset
|
989 } |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
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246
diff
changeset
|
990 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
991 case Z80_RRC: |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
992 cycles = inst->immed == 0 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8); |
247
682e505f5757
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Mike Pavone <pavone@retrodev.com>
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246
diff
changeset
|
993 dst = zcycles(dst, cycles); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
994 if (inst->addr_mode != Z80_UNUSED) { |
247
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
995 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
996 dst = translate_z80_reg(inst, &src_op, dst, opts); //For IX/IY variants that also write to a register |
247
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diff
changeset
|
997 dst = zcycles(dst, 1); |
682e505f5757
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246
diff
changeset
|
998 } else { |
302
3b831fe32c15
More fixes for confusion between Z80_UNUSED and MODE_UNUSED
Mike Pavone <pavone@retrodev.com>
parents:
301
diff
changeset
|
999 src_op.mode = MODE_UNUSED; |
247
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parents:
246
diff
changeset
|
1000 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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246
diff
changeset
|
1001 } |
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Mike Pavone <pavone@retrodev.com>
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diff
changeset
|
1002 dst = ror_ir(dst, 1, dst_op.base, SZ_B); |
301
6e15509a1257
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Mike Pavone <pavone@retrodev.com>
parents:
300
diff
changeset
|
1003 if (src_op.mode != MODE_UNUSED) { |
299
42e1a986f2d0
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295
diff
changeset
|
1004 dst = mov_rr(dst, dst_op.base, src_op.base, SZ_B); |
42e1a986f2d0
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295
diff
changeset
|
1005 } |
247
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changeset
|
1006 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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246
diff
changeset
|
1007 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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diff
changeset
|
1008 //TODO: Implement half-carry flag |
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diff
changeset
|
1009 dst = cmp_ir(dst, 0, dst_op.base, SZ_B); |
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changeset
|
1010 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
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diff
changeset
|
1011 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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diff
changeset
|
1012 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1013 if (inst->addr_mode != Z80_UNUSED) { |
247
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parents:
246
diff
changeset
|
1014 dst = z80_save_result(dst, inst); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1015 if (src_op.mode != MODE_UNUSED) { |
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1016 dst = z80_save_reg(dst, inst, opts); |
42e1a986f2d0
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Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1017 } |
247
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diff
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|
1018 } else { |
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246
diff
changeset
|
1019 dst = z80_save_reg(dst, inst, opts); |
682e505f5757
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246
diff
changeset
|
1020 } |
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parents:
246
diff
changeset
|
1021 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1022 case Z80_RR: |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1023 cycles = inst->immed == 0 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8); |
247
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246
diff
changeset
|
1024 dst = zcycles(dst, cycles); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1025 if (inst->addr_mode != Z80_UNUSED) { |
247
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1026 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1027 dst = translate_z80_reg(inst, &src_op, dst, opts); //For IX/IY variants that also write to a register |
247
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parents:
246
diff
changeset
|
1028 dst = zcycles(dst, 1); |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1029 } else { |
302
3b831fe32c15
More fixes for confusion between Z80_UNUSED and MODE_UNUSED
Mike Pavone <pavone@retrodev.com>
parents:
301
diff
changeset
|
1030 src_op.mode = MODE_UNUSED; |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1031 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
682e505f5757
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parents:
246
diff
changeset
|
1032 } |
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1033 dst = bt_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1034 dst = rcr_ir(dst, 1, dst_op.base, SZ_B); |
301
6e15509a1257
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Mike Pavone <pavone@retrodev.com>
parents:
300
diff
changeset
|
1035 if (src_op.mode != MODE_UNUSED) { |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1036 dst = mov_rr(dst, dst_op.base, src_op.base, SZ_B); |
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1037 } |
247
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1038 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1039 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1040 //TODO: Implement half-carry flag |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1041 dst = cmp_ir(dst, 0, dst_op.base, SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1042 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1043 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1044 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1045 if (inst->addr_mode != Z80_UNUSED) { |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1046 dst = z80_save_result(dst, inst); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1047 if (src_op.mode != MODE_UNUSED) { |
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1048 dst = z80_save_reg(dst, inst, opts); |
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1049 } |
247
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1050 } else { |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1051 dst = z80_save_reg(dst, inst, opts); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1052 } |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1053 break; |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1054 case Z80_SLA: |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1055 case Z80_SLL: |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1056 cycles = inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8; |
1a7d0a964ad2
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Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1057 dst = zcycles(dst, cycles); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1058 if (inst->addr_mode != Z80_UNUSED) { |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1059 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1060 dst = translate_z80_reg(inst, &src_op, dst, opts); //For IX/IY variants that also write to a register |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1061 dst = zcycles(dst, 1); |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1062 } else { |
302
3b831fe32c15
More fixes for confusion between Z80_UNUSED and MODE_UNUSED
Mike Pavone <pavone@retrodev.com>
parents:
301
diff
changeset
|
1063 src_op.mode = MODE_UNUSED; |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1064 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1065 } |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1066 dst = shl_ir(dst, 1, dst_op.base, SZ_B); |
310
bf440db64086
Implement carry flag for shift instructions. Implement weird behavior for bit 0 of SLL. Fix missing break statement in SRL.
Mike Pavone <pavone@retrodev.com>
parents:
309
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1067 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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309
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|
1068 if (inst->op == Z80_SLL) { |
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309
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1069 dst = or_ir(dst, 1, dst_op.base, SZ_B); |
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309
diff
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|
1070 } |
301
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300
diff
changeset
|
1071 if (src_op.mode != MODE_UNUSED) { |
299
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295
diff
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|
1072 dst = mov_rr(dst, dst_op.base, src_op.base, SZ_B); |
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295
diff
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|
1073 } |
275
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|
1074 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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diff
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|
1075 //TODO: Implement half-carry flag |
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|
1076 dst = cmp_ir(dst, 0, dst_op.base, SZ_B); |
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1077 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
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1078 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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274
diff
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1079 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
299
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295
diff
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|
1080 if (inst->addr_mode != Z80_UNUSED) { |
275
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|
1081 dst = z80_save_result(dst, inst); |
299
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295
diff
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|
1082 if (src_op.mode != MODE_UNUSED) { |
42e1a986f2d0
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295
diff
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|
1083 dst = z80_save_reg(dst, inst, opts); |
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|
1084 } |
275
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|
1085 } else { |
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1086 dst = z80_save_reg(dst, inst, opts); |
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1087 } |
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1088 break; |
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diff
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|
1089 case Z80_SRA: |
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1090 cycles = inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8; |
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1091 dst = zcycles(dst, cycles); |
299
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|
1092 if (inst->addr_mode != Z80_UNUSED) { |
275
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1093 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
299
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295
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|
1094 dst = translate_z80_reg(inst, &src_op, dst, opts); //For IX/IY variants that also write to a register |
275
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1095 dst = zcycles(dst, 1); |
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diff
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1096 } else { |
302
3b831fe32c15
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301
diff
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|
1097 src_op.mode = MODE_UNUSED; |
275
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1098 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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diff
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|
1099 } |
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1100 dst = sar_ir(dst, 1, dst_op.base, SZ_B); |
301
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|
1101 if (src_op.mode != MODE_UNUSED) { |
299
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diff
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|
1102 dst = mov_rr(dst, dst_op.base, src_op.base, SZ_B); |
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diff
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|
1103 } |
310
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1104 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
275
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diff
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1105 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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1106 //TODO: Implement half-carry flag |
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1107 dst = cmp_ir(dst, 0, dst_op.base, SZ_B); |
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1108 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
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diff
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1109 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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1110 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
299
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diff
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|
1111 if (inst->addr_mode != Z80_UNUSED) { |
275
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1112 dst = z80_save_result(dst, inst); |
299
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295
diff
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|
1113 if (src_op.mode != MODE_UNUSED) { |
42e1a986f2d0
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diff
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|
1114 dst = z80_save_reg(dst, inst, opts); |
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|
1115 } |
275
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|
1116 } else { |
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|
1117 dst = z80_save_reg(dst, inst, opts); |
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1118 } |
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|
1119 break; |
213
4d4559b04c59
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Mike Pavone <pavone@retrodev.com>
parents:
diff
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|
1120 case Z80_SRL: |
275
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1121 cycles = inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8; |
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1122 dst = zcycles(dst, cycles); |
299
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295
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1123 if (inst->addr_mode != Z80_UNUSED) { |
275
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1124 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
299
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295
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|
1125 dst = translate_z80_reg(inst, &src_op, dst, opts); //For IX/IY variants that also write to a register |
275
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1126 dst = zcycles(dst, 1); |
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1127 } else { |
302
3b831fe32c15
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301
diff
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|
1128 src_op.mode = MODE_UNUSED; |
275
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1129 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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|
1130 } |
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1131 dst = shr_ir(dst, 1, dst_op.base, SZ_B); |
301
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|
1132 if (src_op.mode != MODE_UNUSED) { |
299
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295
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|
1133 dst = mov_rr(dst, dst_op.base, src_op.base, SZ_B); |
42e1a986f2d0
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|
1134 } |
310
bf440db64086
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1135 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
275
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1136 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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1137 //TODO: Implement half-carry flag |
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1138 dst = cmp_ir(dst, 0, dst_op.base, SZ_B); |
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1139 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
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1140 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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1141 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
299
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295
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1142 if (inst->addr_mode != Z80_UNUSED) { |
275
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|
1143 dst = z80_save_result(dst, inst); |
299
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|
1144 if (src_op.mode != MODE_UNUSED) { |
42e1a986f2d0
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|
1145 dst = z80_save_reg(dst, inst, opts); |
42e1a986f2d0
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|
1146 } |
275
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|
1147 } else { |
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|
1148 dst = z80_save_reg(dst, inst, opts); |
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|
1149 } |
310
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1150 break; |
286 | 1151 case Z80_RLD: |
1152 dst = zcycles(dst, 8); | |
1153 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH1, SZ_W); | |
1154 dst = call(dst, (uint8_t *)z80_read_byte); | |
1155 //Before: (HL) = 0x12, A = 0x34 | |
1156 //After: (HL) = 0x24, A = 0x31 | |
1157 dst = mov_rr(dst, opts->regs[Z80_A], SCRATCH2, SZ_B); | |
1158 dst = shl_ir(dst, 4, SCRATCH1, SZ_W); | |
1159 dst = and_ir(dst, 0xF, SCRATCH2, SZ_W); | |
1160 dst = and_ir(dst, 0xFFF, SCRATCH1, SZ_W); | |
1161 dst = and_ir(dst, 0xF0, opts->regs[Z80_A], SZ_B); | |
1162 dst = or_rr(dst, SCRATCH2, SCRATCH1, SZ_W); | |
1163 //SCRATCH1 = 0x0124 | |
1164 dst = ror_ir(dst, 8, SCRATCH1, SZ_W); | |
1165 dst = zcycles(dst, 4); | |
1166 dst = or_rr(dst, SCRATCH1, opts->regs[Z80_A], SZ_B); | |
287
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286
diff
changeset
|
1167 //set flags |
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diff
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|
1168 //TODO: Implement half-carry flag |
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changeset
|
1169 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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diff
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|
1170 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
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diff
changeset
|
1171 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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286
diff
changeset
|
1172 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
505
b7b7a1cab44a
The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
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467
diff
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|
1173 |
286 | 1174 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH2, SZ_W); |
1175 dst = ror_ir(dst, 8, SCRATCH1, SZ_W); | |
1176 dst = call(dst, (uint8_t *)z80_write_byte); | |
1177 break; | |
287
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|
1178 case Z80_RRD: |
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diff
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1179 dst = zcycles(dst, 8); |
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1180 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH1, SZ_W); |
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1181 dst = call(dst, (uint8_t *)z80_read_byte); |
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diff
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1182 //Before: (HL) = 0x12, A = 0x34 |
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diff
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1183 //After: (HL) = 0x41, A = 0x32 |
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|
1184 dst = movzx_rr(dst, opts->regs[Z80_A], SCRATCH2, SZ_B, SZ_W); |
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diff
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|
1185 dst = ror_ir(dst, 4, SCRATCH1, SZ_W); |
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diff
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|
1186 dst = shl_ir(dst, 4, SCRATCH2, SZ_W); |
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diff
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|
1187 dst = and_ir(dst, 0xF00F, SCRATCH1, SZ_W); |
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diff
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|
1188 dst = and_ir(dst, 0xF0, opts->regs[Z80_A], SZ_B); |
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diff
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|
1189 //SCRATCH1 = 0x2001 |
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diff
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1190 //SCRATCH2 = 0x0040 |
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diff
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|
1191 dst = or_rr(dst, SCRATCH2, SCRATCH1, SZ_W); |
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diff
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|
1192 //SCRATCH1 = 0x2041 |
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diff
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|
1193 dst = ror_ir(dst, 8, SCRATCH1, SZ_W); |
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diff
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|
1194 dst = zcycles(dst, 4); |
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diff
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|
1195 dst = shr_ir(dst, 4, SCRATCH1, SZ_B); |
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1196 dst = or_rr(dst, SCRATCH1, opts->regs[Z80_A], SZ_B); |
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diff
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|
1197 //set flags |
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diff
changeset
|
1198 //TODO: Implement half-carry flag |
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diff
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|
1199 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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1200 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
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diff
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|
1201 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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diff
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1202 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
505
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The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
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diff
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|
1203 |
287
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1204 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH2, SZ_W); |
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1205 dst = ror_ir(dst, 8, SCRATCH1, SZ_W); |
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diff
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|
1206 dst = call(dst, (uint8_t *)z80_write_byte); |
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diff
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|
1207 break; |
308
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diff
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|
1208 case Z80_BIT: { |
239
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diff
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|
1209 cycles = (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) ? 8 : 16; |
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|
1210 dst = zcycles(dst, cycles); |
308
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diff
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|
1211 uint8_t bit; |
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diff
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|
1212 if ((inst->addr_mode & 0x1F) == Z80_REG && opts->regs[inst->ea_reg] >= AH && opts->regs[inst->ea_reg] <= BH) { |
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diff
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|
1213 src_op.base = opts->regs[z80_word_reg(inst->ea_reg)]; |
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diff
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|
1214 size = SZ_W; |
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307
diff
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|
1215 bit = inst->immed + 8; |
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diff
changeset
|
1216 } else { |
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parents:
307
diff
changeset
|
1217 size = SZ_B; |
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parents:
307
diff
changeset
|
1218 bit = inst->immed; |
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diff
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|
1219 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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parents:
307
diff
changeset
|
1220 } |
239
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parents:
238
diff
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|
1221 if (inst->addr_mode != Z80_REG) { |
a5bea9711a46
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parents:
238
diff
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|
1222 //Reads normally take 3 cycles, but the read at the end of a bit instruction takes 4 |
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parents:
238
diff
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|
1223 dst = zcycles(dst, 1); |
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parents:
238
diff
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|
1224 } |
308
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parents:
307
diff
changeset
|
1225 dst = bt_ir(dst, bit, src_op.base, size); |
303
8290d3086ff0
BIT was setting the zero flag to the opposite of what it should have. This is now fixed.
Mike Pavone <pavone@retrodev.com>
parents:
302
diff
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|
1226 dst = setcc_rdisp8(dst, CC_NC, CONTEXT, zf_off(ZF_Z)); |
307
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parents:
306
diff
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|
1227 dst = setcc_rdisp8(dst, CC_NC, CONTEXT, zf_off(ZF_PV)); |
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parents:
306
diff
changeset
|
1228 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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parents:
306
diff
changeset
|
1229 if (inst->immed == 7) { |
308
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parents:
307
diff
changeset
|
1230 dst = cmp_ir(dst, 0, src_op.base, size); |
307
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parents:
306
diff
changeset
|
1231 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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parents:
306
diff
changeset
|
1232 } else { |
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parents:
306
diff
changeset
|
1233 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_S), SZ_B); |
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parents:
306
diff
changeset
|
1234 } |
239
a5bea9711a46
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parents:
238
diff
changeset
|
1235 break; |
308
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parents:
307
diff
changeset
|
1236 } |
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parents:
307
diff
changeset
|
1237 case Z80_SET: { |
247
682e505f5757
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parents:
246
diff
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|
1238 cycles = (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) ? 8 : 16; |
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parents:
246
diff
changeset
|
1239 dst = zcycles(dst, cycles); |
308
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parents:
307
diff
changeset
|
1240 uint8_t bit; |
e0e81551fd7e
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parents:
307
diff
changeset
|
1241 if ((inst->addr_mode & 0x1F) == Z80_REG && opts->regs[inst->ea_reg] >= AH && opts->regs[inst->ea_reg] <= BH) { |
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parents:
307
diff
changeset
|
1242 src_op.base = opts->regs[z80_word_reg(inst->ea_reg)]; |
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parents:
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diff
changeset
|
1243 size = SZ_W; |
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parents:
307
diff
changeset
|
1244 bit = inst->immed + 8; |
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parents:
307
diff
changeset
|
1245 } else { |
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parents:
307
diff
changeset
|
1246 size = SZ_B; |
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parents:
307
diff
changeset
|
1247 bit = inst->immed; |
384
5500d1d1269e
Fix set/res when the operand is in memory
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parents:
373
diff
changeset
|
1248 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, MODIFY); |
308
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parents:
307
diff
changeset
|
1249 } |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1250 if (inst->reg != Z80_USE_IMMED) { |
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1251 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1252 } |
247
682e505f5757
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parents:
246
diff
changeset
|
1253 if (inst->addr_mode != Z80_REG) { |
682e505f5757
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parents:
246
diff
changeset
|
1254 //Reads normally take 3 cycles, but the read in the middle of a set instruction takes 4 |
682e505f5757
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parents:
246
diff
changeset
|
1255 dst = zcycles(dst, 1); |
682e505f5757
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parents:
246
diff
changeset
|
1256 } |
308
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parents:
307
diff
changeset
|
1257 dst = bts_ir(dst, bit, src_op.base, size); |
299
42e1a986f2d0
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Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1258 if (inst->reg != Z80_USE_IMMED) { |
308
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parents:
307
diff
changeset
|
1259 if (size == SZ_W) { |
e0e81551fd7e
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parents:
307
diff
changeset
|
1260 if (dst_op.base >= R8) { |
e0e81551fd7e
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parents:
307
diff
changeset
|
1261 dst = ror_ir(dst, 8, src_op.base, SZ_W); |
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parents:
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diff
changeset
|
1262 dst = mov_rr(dst, opts->regs[z80_low_reg(inst->ea_reg)], dst_op.base, SZ_B); |
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parents:
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diff
changeset
|
1263 dst = ror_ir(dst, 8, src_op.base, SZ_W); |
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parents:
307
diff
changeset
|
1264 } else { |
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parents:
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diff
changeset
|
1265 dst = mov_rr(dst, opts->regs[inst->ea_reg], dst_op.base, SZ_B); |
505
b7b7a1cab44a
The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1266 } |
308
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parents:
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diff
changeset
|
1267 } else { |
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parents:
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diff
changeset
|
1268 dst = mov_rr(dst, src_op.base, dst_op.base, SZ_B); |
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parents:
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diff
changeset
|
1269 } |
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parents:
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diff
changeset
|
1270 } |
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parents:
307
diff
changeset
|
1271 if ((inst->addr_mode & 0x1F) != Z80_REG) { |
e0e81551fd7e
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parents:
307
diff
changeset
|
1272 dst = z80_save_result(dst, inst); |
e0e81551fd7e
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parents:
307
diff
changeset
|
1273 if (inst->reg != Z80_USE_IMMED) { |
e0e81551fd7e
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parents:
307
diff
changeset
|
1274 dst = z80_save_reg(dst, inst, opts); |
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307
diff
changeset
|
1275 } |
e0e81551fd7e
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parents:
307
diff
changeset
|
1276 } |
e0e81551fd7e
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parents:
307
diff
changeset
|
1277 break; |
e0e81551fd7e
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1278 } |
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1279 case Z80_RES: { |
e0e81551fd7e
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1280 cycles = (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) ? 8 : 16; |
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Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
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|
1281 dst = zcycles(dst, cycles); |
e0e81551fd7e
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1282 uint8_t bit; |
e0e81551fd7e
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parents:
307
diff
changeset
|
1283 if ((inst->addr_mode & 0x1F) == Z80_REG && opts->regs[inst->ea_reg] >= AH && opts->regs[inst->ea_reg] <= BH) { |
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parents:
307
diff
changeset
|
1284 src_op.base = opts->regs[z80_word_reg(inst->ea_reg)]; |
e0e81551fd7e
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1285 size = SZ_W; |
e0e81551fd7e
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1286 bit = inst->immed + 8; |
e0e81551fd7e
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1287 } else { |
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1288 size = SZ_B; |
e0e81551fd7e
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1289 bit = inst->immed; |
384
5500d1d1269e
Fix set/res when the operand is in memory
Mike Pavone <pavone@retrodev.com>
parents:
373
diff
changeset
|
1290 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, MODIFY); |
308
e0e81551fd7e
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307
diff
changeset
|
1291 } |
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parents:
307
diff
changeset
|
1292 if (inst->reg != Z80_USE_IMMED) { |
e0e81551fd7e
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1293 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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parents:
307
diff
changeset
|
1294 } |
e0e81551fd7e
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1295 if (inst->addr_mode != Z80_REG) { |
e0e81551fd7e
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1296 //Reads normally take 3 cycles, but the read in the middle of a set instruction takes 4 |
e0e81551fd7e
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parents:
307
diff
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|
1297 dst = zcycles(dst, 1); |
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parents:
307
diff
changeset
|
1298 } |
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parents:
307
diff
changeset
|
1299 dst = btr_ir(dst, bit, src_op.base, size); |
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parents:
307
diff
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|
1300 if (inst->reg != Z80_USE_IMMED) { |
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307
diff
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|
1301 if (size == SZ_W) { |
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parents:
307
diff
changeset
|
1302 if (dst_op.base >= R8) { |
e0e81551fd7e
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1303 dst = ror_ir(dst, 8, src_op.base, SZ_W); |
e0e81551fd7e
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parents:
307
diff
changeset
|
1304 dst = mov_rr(dst, opts->regs[z80_low_reg(inst->ea_reg)], dst_op.base, SZ_B); |
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307
diff
changeset
|
1305 dst = ror_ir(dst, 8, src_op.base, SZ_W); |
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Mike Pavone <pavone@retrodev.com>
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307
diff
changeset
|
1306 } else { |
e0e81551fd7e
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1307 dst = mov_rr(dst, opts->regs[inst->ea_reg], dst_op.base, SZ_B); |
505
b7b7a1cab44a
The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1308 } |
308
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parents:
307
diff
changeset
|
1309 } else { |
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parents:
307
diff
changeset
|
1310 dst = mov_rr(dst, src_op.base, dst_op.base, SZ_B); |
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parents:
307
diff
changeset
|
1311 } |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1312 } |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1313 if (inst->addr_mode != Z80_REG) { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1314 dst = z80_save_result(dst, inst); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1315 if (inst->reg != Z80_USE_IMMED) { |
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1316 dst = z80_save_reg(dst, inst, opts); |
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1317 } |
247
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1318 } |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1319 break; |
308
e0e81551fd7e
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1320 } |
236
19fb3523a9e5
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parents:
235
diff
changeset
|
1321 case Z80_JP: { |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1322 cycles = 4; |
506
a3b48a57e847
Fix timing of certain ld and jp instructions in the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
505
diff
changeset
|
1323 if (inst->addr_mode != Z80_REG_INDIRECT) { |
236
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parents:
235
diff
changeset
|
1324 cycles += 6; |
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parents:
235
diff
changeset
|
1325 } else if(inst->ea_reg == Z80_IX || inst->ea_reg == Z80_IY) { |
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parents:
235
diff
changeset
|
1326 cycles += 4; |
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parents:
235
diff
changeset
|
1327 } |
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1328 dst = zcycles(dst, cycles); |
239
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
1329 if (inst->addr_mode != Z80_REG_INDIRECT && inst->immed < 0x4000) { |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1330 uint8_t * call_dst = z80_get_native_address(context, inst->immed); |
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1331 if (!call_dst) { |
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Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1332 opts->deferred = defer_address(opts->deferred, inst->immed, dst + 1); |
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Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1333 //fake address to force large displacement |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1334 call_dst = dst + 256; |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1335 } |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1336 dst = jmp(dst, call_dst); |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1337 } else { |
239
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
1338 if (inst->addr_mode == Z80_REG_INDIRECT) { |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1339 dst = mov_rr(dst, opts->regs[inst->ea_reg], SCRATCH1, SZ_W); |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1340 } else { |
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1341 dst = mov_ir(dst, inst->immed, SCRATCH1, SZ_W); |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1342 } |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1343 dst = call(dst, (uint8_t *)z80_native_addr); |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1344 dst = jmp_r(dst, SCRATCH1); |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1345 } |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1346 break; |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1347 } |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1348 case Z80_JPCC: { |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1349 dst = zcycles(dst, 7);//T States: 4,3 |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1350 uint8_t cond = CC_Z; |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1351 switch (inst->reg) |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1352 { |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1353 case Z80_CC_NZ: |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1354 cond = CC_NZ; |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1355 case Z80_CC_Z: |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1356 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_Z), SZ_B); |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1357 break; |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1358 case Z80_CC_NC: |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1359 cond = CC_NZ; |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1360 case Z80_CC_C: |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1361 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1362 break; |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1363 case Z80_CC_PO: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1364 cond = CC_NZ; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1365 case Z80_CC_PE: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1366 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_PV), SZ_B); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1367 break; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1368 case Z80_CC_P: |
367
f20562f2a570
Fix P condition in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
366
diff
changeset
|
1369 cond = CC_NZ; |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1370 case Z80_CC_M: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1371 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_S), SZ_B); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1372 break; |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1373 } |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1374 uint8_t *no_jump_off = dst+1; |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1375 dst = jcc(dst, cond, dst+2); |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1376 dst = zcycles(dst, 5);//T States: 5 |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1377 uint16_t dest_addr = inst->immed; |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1378 if (dest_addr < 0x4000) { |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1379 uint8_t * call_dst = z80_get_native_address(context, dest_addr); |
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1380 if (!call_dst) { |
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|
1381 opts->deferred = defer_address(opts->deferred, dest_addr, dst + 1); |
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|
1382 //fake address to force large displacement |
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|
1383 call_dst = dst + 256; |
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|
1384 } |
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|
1385 dst = jmp(dst, call_dst); |
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|
1386 } else { |
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|
1387 dst = mov_ir(dst, dest_addr, SCRATCH1, SZ_W); |
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|
1388 dst = call(dst, (uint8_t *)z80_native_addr); |
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|
1389 dst = jmp_r(dst, SCRATCH1); |
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235
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|
1390 } |
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|
1391 *no_jump_off = dst - (no_jump_off+1); |
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235
diff
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|
1392 break; |
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|
1393 } |
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|
1394 case Z80_JR: { |
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|
1395 dst = zcycles(dst, 12);//T States: 4,3,5 |
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|
1396 uint16_t dest_addr = address + inst->immed + 2; |
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|
1397 if (dest_addr < 0x4000) { |
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|
1398 uint8_t * call_dst = z80_get_native_address(context, dest_addr); |
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235
diff
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|
1399 if (!call_dst) { |
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|
1400 opts->deferred = defer_address(opts->deferred, dest_addr, dst + 1); |
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diff
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|
1401 //fake address to force large displacement |
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|
1402 call_dst = dst + 256; |
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|
1403 } |
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|
1404 dst = jmp(dst, call_dst); |
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|
1405 } else { |
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|
1406 dst = mov_ir(dst, dest_addr, SCRATCH1, SZ_W); |
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|
1407 dst = call(dst, (uint8_t *)z80_native_addr); |
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235
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|
1408 dst = jmp_r(dst, SCRATCH1); |
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|
1409 } |
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diff
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|
1410 break; |
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diff
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|
1411 } |
235
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1412 case Z80_JRCC: { |
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1413 dst = zcycles(dst, 7);//T States: 4,3 |
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|
1414 uint8_t cond = CC_Z; |
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diff
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|
1415 switch (inst->reg) |
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|
1416 { |
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|
1417 case Z80_CC_NZ: |
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1418 cond = CC_NZ; |
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|
1419 case Z80_CC_Z: |
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1420 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_Z), SZ_B); |
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|
1421 break; |
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diff
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|
1422 case Z80_CC_NC: |
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|
1423 cond = CC_NZ; |
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diff
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|
1424 case Z80_CC_C: |
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1425 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1426 break; |
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diff
changeset
|
1427 } |
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changeset
|
1428 uint8_t *no_jump_off = dst+1; |
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213
diff
changeset
|
1429 dst = jcc(dst, cond, dst+2); |
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|
1430 dst = zcycles(dst, 5);//T States: 5 |
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Get Z80 core working for simple programs
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|
1431 uint16_t dest_addr = address + inst->immed + 2; |
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Get Z80 core working for simple programs
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diff
changeset
|
1432 if (dest_addr < 0x4000) { |
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Get Z80 core working for simple programs
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213
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changeset
|
1433 uint8_t * call_dst = z80_get_native_address(context, dest_addr); |
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Get Z80 core working for simple programs
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diff
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|
1434 if (!call_dst) { |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1435 opts->deferred = defer_address(opts->deferred, dest_addr, dst + 1); |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1436 //fake address to force large displacement |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1437 call_dst = dst + 256; |
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diff
changeset
|
1438 } |
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diff
changeset
|
1439 dst = jmp(dst, call_dst); |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1440 } else { |
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Get Z80 core working for simple programs
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diff
changeset
|
1441 dst = mov_ir(dst, dest_addr, SCRATCH1, SZ_W); |
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Get Z80 core working for simple programs
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diff
changeset
|
1442 dst = call(dst, (uint8_t *)z80_native_addr); |
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Get Z80 core working for simple programs
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changeset
|
1443 dst = jmp_r(dst, SCRATCH1); |
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213
diff
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|
1444 } |
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diff
changeset
|
1445 *no_jump_off = dst - (no_jump_off+1); |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1446 break; |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1447 } |
239
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
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238
diff
changeset
|
1448 case Z80_DJNZ: |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
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238
diff
changeset
|
1449 dst = zcycles(dst, 8);//T States: 5,3 |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
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238
diff
changeset
|
1450 dst = sub_ir(dst, 1, opts->regs[Z80_B], SZ_B); |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
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238
diff
changeset
|
1451 uint8_t *no_jump_off = dst+1; |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
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238
diff
changeset
|
1452 dst = jcc(dst, CC_Z, dst+2); |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
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238
diff
changeset
|
1453 dst = zcycles(dst, 5);//T States: 5 |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
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238
diff
changeset
|
1454 uint16_t dest_addr = address + inst->immed + 2; |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
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238
diff
changeset
|
1455 if (dest_addr < 0x4000) { |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
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238
diff
changeset
|
1456 uint8_t * call_dst = z80_get_native_address(context, dest_addr); |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
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238
diff
changeset
|
1457 if (!call_dst) { |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
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238
diff
changeset
|
1458 opts->deferred = defer_address(opts->deferred, dest_addr, dst + 1); |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
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238
diff
changeset
|
1459 //fake address to force large displacement |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
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238
diff
changeset
|
1460 call_dst = dst + 256; |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
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238
diff
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|
1461 } |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
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238
diff
changeset
|
1462 dst = jmp(dst, call_dst); |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
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238
diff
changeset
|
1463 } else { |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
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238
diff
changeset
|
1464 dst = mov_ir(dst, dest_addr, SCRATCH1, SZ_W); |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
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238
diff
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|
1465 dst = call(dst, (uint8_t *)z80_native_addr); |
a5bea9711a46
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238
diff
changeset
|
1466 dst = jmp_r(dst, SCRATCH1); |
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|
1467 } |
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|
1468 *no_jump_off = dst - (no_jump_off+1); |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
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238
diff
changeset
|
1469 break; |
235
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diff
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|
1470 case Z80_CALL: { |
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|
1471 dst = zcycles(dst, 11);//T States: 4,3,4 |
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|
1472 dst = sub_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
253
3b34deba4ca0
Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
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252
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|
1473 dst = mov_ir(dst, address + 3, SCRATCH1, SZ_W); |
3b34deba4ca0
Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
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|
1474 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W); |
235
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|
1475 dst = call(dst, (uint8_t *)z80_write_word_highfirst);//T States: 3, 3 |
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|
1476 if (inst->immed < 0x4000) { |
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|
1477 uint8_t * call_dst = z80_get_native_address(context, inst->immed); |
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|
1478 if (!call_dst) { |
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changeset
|
1479 opts->deferred = defer_address(opts->deferred, inst->immed, dst + 1); |
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diff
changeset
|
1480 //fake address to force large displacement |
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diff
changeset
|
1481 call_dst = dst + 256; |
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changeset
|
1482 } |
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changeset
|
1483 dst = jmp(dst, call_dst); |
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changeset
|
1484 } else { |
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changeset
|
1485 dst = mov_ir(dst, inst->immed, SCRATCH1, SZ_W); |
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|
1486 dst = call(dst, (uint8_t *)z80_native_addr); |
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changeset
|
1487 dst = jmp_r(dst, SCRATCH1); |
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changeset
|
1488 } |
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changeset
|
1489 break; |
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diff
changeset
|
1490 } |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
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236
diff
changeset
|
1491 case Z80_CALLCC: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1492 dst = zcycles(dst, 10);//T States: 4,3,3 (false case) |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1493 uint8_t cond = CC_Z; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1494 switch (inst->reg) |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1495 { |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1496 case Z80_CC_NZ: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1497 cond = CC_NZ; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1498 case Z80_CC_Z: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1499 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_Z), SZ_B); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1500 break; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1501 case Z80_CC_NC: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1502 cond = CC_NZ; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1503 case Z80_CC_C: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1504 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1505 break; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1506 case Z80_CC_PO: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1507 cond = CC_NZ; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1508 case Z80_CC_PE: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1509 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_PV), SZ_B); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1510 break; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1511 case Z80_CC_P: |
367
f20562f2a570
Fix P condition in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
366
diff
changeset
|
1512 cond = CC_NZ; |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1513 case Z80_CC_M: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1514 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_S), SZ_B); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1515 break; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1516 } |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1517 uint8_t *no_call_off = dst+1; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1518 dst = jcc(dst, cond, dst+2); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1519 dst = zcycles(dst, 1);//Last of the above T states takes an extra cycle in the true case |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1520 dst = sub_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
253
3b34deba4ca0
Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents:
252
diff
changeset
|
1521 dst = mov_ir(dst, address + 3, SCRATCH1, SZ_W); |
3b34deba4ca0
Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents:
252
diff
changeset
|
1522 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W); |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1523 dst = call(dst, (uint8_t *)z80_write_word_highfirst);//T States: 3, 3 |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1524 if (inst->immed < 0x4000) { |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1525 uint8_t * call_dst = z80_get_native_address(context, inst->immed); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1526 if (!call_dst) { |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1527 opts->deferred = defer_address(opts->deferred, inst->immed, dst + 1); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1528 //fake address to force large displacement |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1529 call_dst = dst + 256; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1530 } |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1531 dst = jmp(dst, call_dst); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1532 } else { |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1533 dst = mov_ir(dst, inst->immed, SCRATCH1, SZ_W); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1534 dst = call(dst, (uint8_t *)z80_native_addr); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1535 dst = jmp_r(dst, SCRATCH1); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1536 } |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1537 *no_call_off = dst - (no_call_off+1); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1538 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1539 case Z80_RET: |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1540 dst = zcycles(dst, 4);//T States: 4 |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1541 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1542 dst = call(dst, (uint8_t *)z80_read_word);//T STates: 3, 3 |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1543 dst = add_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1544 dst = call(dst, (uint8_t *)z80_native_addr); |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1545 dst = jmp_r(dst, SCRATCH1); |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1546 break; |
246
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1547 case Z80_RETCC: { |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1548 dst = zcycles(dst, 5);//T States: 5 |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1549 uint8_t cond = CC_Z; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1550 switch (inst->reg) |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1551 { |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1552 case Z80_CC_NZ: |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1553 cond = CC_NZ; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1554 case Z80_CC_Z: |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1555 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_Z), SZ_B); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1556 break; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1557 case Z80_CC_NC: |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1558 cond = CC_NZ; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1559 case Z80_CC_C: |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1560 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1561 break; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1562 case Z80_CC_PO: |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1563 cond = CC_NZ; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1564 case Z80_CC_PE: |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1565 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_PV), SZ_B); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1566 break; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1567 case Z80_CC_P: |
367
f20562f2a570
Fix P condition in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
366
diff
changeset
|
1568 cond = CC_NZ; |
246
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1569 case Z80_CC_M: |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1570 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_S), SZ_B); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1571 break; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1572 } |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1573 uint8_t *no_call_off = dst+1; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1574 dst = jcc(dst, cond, dst+2); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1575 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1576 dst = call(dst, (uint8_t *)z80_read_word);//T STates: 3, 3 |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1577 dst = add_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1578 dst = call(dst, (uint8_t *)z80_native_addr); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1579 dst = jmp_r(dst, SCRATCH1); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1580 *no_call_off = dst - (no_call_off+1); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1581 break; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1582 } |
283
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1583 case Z80_RETI: |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1584 //For some systems, this may need a callback for signalling interrupt routine completion |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1585 dst = zcycles(dst, 8);//T States: 4, 4 |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1586 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1587 dst = call(dst, (uint8_t *)z80_read_word);//T STates: 3, 3 |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1588 dst = add_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1589 dst = call(dst, (uint8_t *)z80_native_addr); |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1590 dst = jmp_r(dst, SCRATCH1); |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1591 break; |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1592 case Z80_RETN: |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1593 dst = zcycles(dst, 8);//T States: 4, 4 |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1594 dst = mov_rdisp8r(dst, CONTEXT, offsetof(z80_context, iff2), SCRATCH2, SZ_B); |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1595 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1596 dst = mov_rrdisp8(dst, SCRATCH2, CONTEXT, offsetof(z80_context, iff1), SZ_B); |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1597 dst = call(dst, (uint8_t *)z80_read_word);//T STates: 3, 3 |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
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diff
changeset
|
1598 dst = add_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1599 dst = call(dst, (uint8_t *)z80_native_addr); |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1600 dst = jmp_r(dst, SCRATCH1); |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1601 break; |
241
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1602 case Z80_RST: { |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
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parents:
239
diff
changeset
|
1603 //RST is basically CALL to an address in page 0 |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1604 dst = zcycles(dst, 5);//T States: 5 |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1605 dst = sub_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
315
684e71e9f0d0
Fix return address for RST
Mike Pavone <pavone@retrodev.com>
parents:
314
diff
changeset
|
1606 dst = mov_ir(dst, address + 1, SCRATCH1, SZ_W); |
253
3b34deba4ca0
Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents:
252
diff
changeset
|
1607 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W); |
241
2586d49ddd46
Implement EX, EXX and RST in Z80 core
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parents:
239
diff
changeset
|
1608 dst = call(dst, (uint8_t *)z80_write_word_highfirst);//T States: 3, 3 |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
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239
diff
changeset
|
1609 uint8_t * call_dst = z80_get_native_address(context, inst->immed); |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
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239
diff
changeset
|
1610 if (!call_dst) { |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1611 opts->deferred = defer_address(opts->deferred, inst->immed, dst + 1); |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
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parents:
239
diff
changeset
|
1612 //fake address to force large displacement |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1613 call_dst = dst + 256; |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1614 } |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1615 dst = jmp(dst, call_dst); |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1616 break; |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1617 } |
284
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
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283
diff
changeset
|
1618 case Z80_IN: |
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Implement IN and OUT (untested)
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283
diff
changeset
|
1619 dst = zcycles(dst, inst->reg == Z80_A ? 7 : 8);//T States: 4 3/4 |
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Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1620 if (inst->addr_mode == Z80_IMMED_INDIRECT) { |
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Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
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283
diff
changeset
|
1621 dst = mov_ir(dst, inst->immed, SCRATCH1, SZ_B); |
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Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
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283
diff
changeset
|
1622 } else { |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
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283
diff
changeset
|
1623 dst = mov_rr(dst, opts->regs[Z80_C], SCRATCH1, SZ_B); |
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Implement IN and OUT (untested)
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283
diff
changeset
|
1624 } |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1625 dst = call(dst, (uint8_t *)z80_io_read); |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1626 translate_z80_reg(inst, &dst_op, dst, opts); |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
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283
diff
changeset
|
1627 dst = mov_rr(dst, SCRATCH1, dst_op.base, SZ_B); |
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Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1628 dst = z80_save_reg(dst, inst, opts); |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1629 break; |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1630 /*case Z80_INI: |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1631 case Z80_INIR: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1632 case Z80_IND: |
284
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1633 case Z80_INDR:*/ |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1634 case Z80_OUT: |
284
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1635 dst = zcycles(dst, inst->reg == Z80_A ? 7 : 8);//T States: 4 3/4 |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1636 if ((inst->addr_mode & 0x1F) == Z80_IMMED_INDIRECT) { |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1637 dst = mov_ir(dst, inst->immed, SCRATCH2, SZ_B); |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1638 } else { |
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Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1639 dst = mov_rr(dst, opts->regs[Z80_C], SCRATCH2, SZ_B); |
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Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1640 } |
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Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1641 translate_z80_reg(inst, &src_op, dst, opts); |
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Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1642 dst = mov_rr(dst, dst_op.base, SCRATCH1, SZ_B); |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1643 dst = call(dst, (uint8_t *)z80_io_write); |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1644 dst = z80_save_reg(dst, inst, opts); |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1645 break; |
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Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
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283
diff
changeset
|
1646 /*case Z80_OUTI: |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1647 case Z80_OTIR: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1648 case Z80_OUTD: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1649 case Z80_OTDR:*/ |
235
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1650 default: { |
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1651 char disbuf[80]; |
314
54c0e5f22198
Show absolute addresses for JR, JRCC and DJNZ in Z80 disassembler
Mike Pavone <pavone@retrodev.com>
parents:
313
diff
changeset
|
1652 z80_disasm(inst, disbuf, address); |
424
7e8e179116af
Add support for loading GST format savestates
Mike Pavone <pavone@retrodev.com>
parents:
420
diff
changeset
|
1653 fprintf(stderr, "unimplemented instruction: %s at %X\n", disbuf, address); |
259
d9417261366f
Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called.
Mike Pavone <pavone@retrodev.com>
parents:
257
diff
changeset
|
1654 FILE * f = fopen("zram.bin", "wb"); |
d9417261366f
Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called.
Mike Pavone <pavone@retrodev.com>
parents:
257
diff
changeset
|
1655 fwrite(context->mem_pointers[0], 1, 8 * 1024, f); |
d9417261366f
Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called.
Mike Pavone <pavone@retrodev.com>
parents:
257
diff
changeset
|
1656 fclose(f); |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1657 exit(1); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1658 } |
235
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1659 } |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1660 return dst; |
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1661 } |
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1662 |
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1663 uint8_t * z80_get_native_address(z80_context * context, uint32_t address) |
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1664 { |
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1665 native_map_slot *map; |
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1666 if (address < 0x4000) { |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1667 address &= 0x1FFF; |
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1668 map = context->static_code_map; |
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Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1669 } else if (address >= 0x8000) { |
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1670 address &= 0x7FFF; |
279
6be6056735a9
Fix native address lookup in bannked memory area
Mike Pavone <pavone@retrodev.com>
parents:
277
diff
changeset
|
1671 map = context->banked_code_map + context->bank_reg; |
235
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1672 } else { |
313
a13329645ea3
Fix terminal instruction detection in disassembler
Mike Pavone <pavone@retrodev.com>
parents:
312
diff
changeset
|
1673 //dprintf("z80_get_native_address: %X NULL\n", address); |
235
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1674 return NULL; |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1675 } |
268
6c2d7e003a55
Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents:
267
diff
changeset
|
1676 if (!map->base || !map->offsets || map->offsets[address] == INVALID_OFFSET || map->offsets[address] == EXTENSION_WORD) { |
313
a13329645ea3
Fix terminal instruction detection in disassembler
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parents:
312
diff
changeset
|
1677 //dprintf("z80_get_native_address: %X NULL\n", address); |
235
d9bf8e61c33c
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213
diff
changeset
|
1678 return NULL; |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1679 } |
313
a13329645ea3
Fix terminal instruction detection in disassembler
Mike Pavone <pavone@retrodev.com>
parents:
312
diff
changeset
|
1680 //dprintf("z80_get_native_address: %X %p\n", address, map->base + map->offsets[address]); |
235
d9bf8e61c33c
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diff
changeset
|
1681 return map->base + map->offsets[address]; |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1682 } |
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213
diff
changeset
|
1683 |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1684 uint8_t z80_get_native_inst_size(x86_z80_options * opts, uint32_t address) |
235
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213
diff
changeset
|
1685 { |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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250
diff
changeset
|
1686 if (address >= 0x4000) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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250
diff
changeset
|
1687 return 0; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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250
diff
changeset
|
1688 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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250
diff
changeset
|
1689 return opts->ram_inst_sizes[address & 0x1FFF]; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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250
diff
changeset
|
1690 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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250
diff
changeset
|
1691 |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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changeset
|
1692 void z80_map_native_address(z80_context * context, uint32_t address, uint8_t * native_address, uint8_t size, uint8_t native_size) |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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diff
changeset
|
1693 { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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diff
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|
1694 uint32_t orig_address = address; |
235
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213
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|
1695 native_map_slot *map; |
252
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|
1696 x86_z80_options * opts = context->options; |
235
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|
1697 if (address < 0x4000) { |
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changeset
|
1698 address &= 0x1FFF; |
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diff
changeset
|
1699 map = context->static_code_map; |
252
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changeset
|
1700 opts->ram_inst_sizes[address] = native_size; |
63b9a500a00b
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changeset
|
1701 context->ram_code_flags[(address & 0x1C00) >> 10] |= 1 << ((address & 0x380) >> 7); |
63b9a500a00b
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|
1702 context->ram_code_flags[((address + size) & 0x1C00) >> 10] |= 1 << (((address + size) & 0x380) >> 7); |
235
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213
diff
changeset
|
1703 } else if (address >= 0x8000) { |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1704 address &= 0x7FFF; |
279
6be6056735a9
Fix native address lookup in bannked memory area
Mike Pavone <pavone@retrodev.com>
parents:
277
diff
changeset
|
1705 map = context->banked_code_map + context->bank_reg; |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1706 if (!map->offsets) { |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1707 map->offsets = malloc(sizeof(int32_t) * 0x8000); |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1708 memset(map->offsets, 0xFF, sizeof(int32_t) * 0x8000); |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1709 } |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1710 } else { |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1711 return; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1712 } |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1713 if (!map->base) { |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1714 map->base = native_address; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1715 } |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1716 map->offsets[address] = native_address - map->base; |
253
3b34deba4ca0
Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents:
252
diff
changeset
|
1717 for(--size, orig_address++; size; --size, orig_address++) { |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1718 address = orig_address; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1719 if (address < 0x4000) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1720 address &= 0x1FFF; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1721 map = context->static_code_map; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1722 } else if (address >= 0x8000) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1723 address &= 0x7FFF; |
279
6be6056735a9
Fix native address lookup in bannked memory area
Mike Pavone <pavone@retrodev.com>
parents:
277
diff
changeset
|
1724 map = context->banked_code_map + context->bank_reg; |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1725 } else { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1726 return; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1727 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1728 if (!map->offsets) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1729 map->offsets = malloc(sizeof(int32_t) * 0x8000); |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1730 memset(map->offsets, 0xFF, sizeof(int32_t) * 0x8000); |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1731 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1732 map->offsets[address] = EXTENSION_WORD; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1733 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1734 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1735 |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1736 #define INVALID_INSTRUCTION_START 0xFEEDFEED |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1737 |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1738 uint32_t z80_get_instruction_start(native_map_slot * static_code_map, uint32_t address) |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1739 { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1740 if (!static_code_map->base || address >= 0x4000) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1741 return INVALID_INSTRUCTION_START; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1742 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1743 address &= 0x1FFF; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1744 if (static_code_map->offsets[address] == INVALID_OFFSET) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1745 return INVALID_INSTRUCTION_START; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1746 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1747 while (static_code_map->offsets[address] == EXTENSION_WORD) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1748 --address; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1749 address &= 0x1FFF; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1750 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1751 return address; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1752 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1753 |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1754 z80_context * z80_handle_code_write(uint32_t address, z80_context * context) |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1755 { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1756 uint32_t inst_start = z80_get_instruction_start(context->static_code_map, address); |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1757 if (inst_start != INVALID_INSTRUCTION_START) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1758 uint8_t * dst = z80_get_native_address(context, inst_start); |
268
6c2d7e003a55
Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents:
267
diff
changeset
|
1759 dprintf("patching code at %p for Z80 instruction at %X due to write to %X\n", dst, inst_start, address); |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1760 dst = mov_ir(dst, inst_start, SCRATCH1, SZ_D); |
390
561fe3ea3fc8
Use a call instruction to figure out the original native address when retranslating so that it does not get lost when the byte transforms from a instruction word to extension word
Mike Pavone <pavone@retrodev.com>
parents:
389
diff
changeset
|
1761 dst = call(dst, (uint8_t *)z80_retrans_stub); |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1762 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1763 return context; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1764 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1765 |
264
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1766 uint8_t * z80_get_native_address_trans(z80_context * context, uint32_t address) |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1767 { |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1768 uint8_t * addr = z80_get_native_address(context, address); |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1769 if (!addr) { |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1770 translate_z80_stream(context, address); |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1771 addr = z80_get_native_address(context, address); |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1772 if (!addr) { |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1773 printf("Failed to translate %X to native code\n", address); |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1774 } |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1775 } |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1776 return addr; |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1777 } |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1778 |
266
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1779 void z80_handle_deferred(z80_context * context) |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1780 { |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1781 x86_z80_options * opts = context->options; |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1782 process_deferred(&opts->deferred, context, (native_addr_func)z80_get_native_address); |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1783 if (opts->deferred) { |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1784 translate_z80_stream(context, opts->deferred->address); |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1785 } |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1786 } |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1787 |
390
561fe3ea3fc8
Use a call instruction to figure out the original native address when retranslating so that it does not get lost when the byte transforms from a instruction word to extension word
Mike Pavone <pavone@retrodev.com>
parents:
389
diff
changeset
|
1788 void * z80_retranslate_inst(uint32_t address, z80_context * context, uint8_t * orig_start) |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1789 { |
266
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1790 char disbuf[80]; |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1791 x86_z80_options * opts = context->options; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1792 uint8_t orig_size = z80_get_native_inst_size(opts, address); |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1793 uint32_t orig = address; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1794 address &= 0x1FFF; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1795 uint8_t * dst = opts->cur_code; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1796 uint8_t * dst_end = opts->code_end; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1797 uint8_t *after, *inst = context->mem_pointers[0] + address; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1798 z80inst instbuf; |
268
6c2d7e003a55
Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents:
267
diff
changeset
|
1799 dprintf("Retranslating code at Z80 address %X, native address %p\n", address, orig_start); |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1800 after = z80_decode(inst, &instbuf); |
268
6c2d7e003a55
Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents:
267
diff
changeset
|
1801 #ifdef DO_DEBUG_PRINT |
314
54c0e5f22198
Show absolute addresses for JR, JRCC and DJNZ in Z80 disassembler
Mike Pavone <pavone@retrodev.com>
parents:
313
diff
changeset
|
1802 z80_disasm(&instbuf, disbuf, address); |
266
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1803 if (instbuf.op == Z80_NOP) { |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1804 printf("%X\t%s(%d)\n", address, disbuf, instbuf.immed); |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1805 } else { |
376df762ddf5
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|
1806 printf("%X\t%s\n", address, disbuf); |
267
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Don't mix *H regs with the REX prefix
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|
1807 } |
268
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Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
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267
diff
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|
1808 #endif |
252
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|
1809 if (orig_size != ZMAX_NATIVE_SIZE) { |
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diff
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|
1810 if (dst_end - dst < ZMAX_NATIVE_SIZE) { |
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diff
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|
1811 size_t size = 1024*1024; |
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Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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diff
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|
1812 dst = alloc_code(&size); |
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diff
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|
1813 opts->code_end = dst_end = dst + size; |
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|
1814 opts->cur_code = dst; |
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|
1815 } |
282
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Remove deferred address entries from abandoned translations inside z80_retrans_inst
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279
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|
1816 deferred_addr * orig_deferred = opts->deferred; |
252
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|
1817 uint8_t * native_end = translate_z80inst(&instbuf, dst, context, address); |
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|
1818 if ((native_end - dst) <= orig_size) { |
264
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|
1819 uint8_t * native_next = z80_get_native_address(context, address + after-inst); |
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|
1820 if (native_next && ((native_next == orig_start + orig_size) || (orig_size - (native_end - dst)) > 5)) { |
282
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diff
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|
1821 remove_deferred_until(&opts->deferred, orig_deferred); |
264
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|
1822 native_end = translate_z80inst(&instbuf, orig_start, context, address); |
266
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|
1823 if (native_next == orig_start + orig_size && (native_next-native_end) < 2) { |
264
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1824 while (native_end < orig_start + orig_size) { |
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diff
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|
1825 *(native_end++) = 0x90; //NOP |
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262
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|
1826 } |
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|
1827 } else { |
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|
1828 jmp(native_end, native_next); |
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|
1829 } |
266
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|
1830 z80_handle_deferred(context); |
264
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|
1831 return orig_start; |
252
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|
1832 } |
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|
1833 } |
264
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|
1834 z80_map_native_address(context, address, dst, after-inst, ZMAX_NATIVE_SIZE); |
266
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|
1835 opts->cur_code = dst+ZMAX_NATIVE_SIZE; |
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Fix some more retranslation bugs in the Z80 core
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264
diff
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|
1836 jmp(orig_start, dst); |
283
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Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
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diff
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|
1837 if (!z80_is_terminal(&instbuf)) { |
264
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|
1838 jmp(native_end, z80_get_native_address_trans(context, address + after-inst)); |
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|
1839 } |
266
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|
1840 z80_handle_deferred(context); |
264
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|
1841 return dst; |
252
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|
1842 } else { |
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Mike Pavone <pavone@retrodev.com>
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|
1843 dst = translate_z80inst(&instbuf, orig_start, context, address); |
283
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|
1844 if (!z80_is_terminal(&instbuf)) { |
264
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|
1845 dst = jmp(dst, z80_get_native_address_trans(context, address + after-inst)); |
252
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|
1846 } |
266
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|
1847 z80_handle_deferred(context); |
252
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1848 return orig_start; |
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1849 } |
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1850 } |
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1851 |
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1852 void translate_z80_stream(z80_context * context, uint32_t address) |
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1853 { |
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1854 char disbuf[80]; |
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1855 if (z80_get_native_address(context, address)) { |
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|
1856 return; |
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|
1857 } |
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|
1858 x86_z80_options * opts = context->options; |
505
b7b7a1cab44a
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|
1859 uint32_t start_address = address; |
235
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1860 uint8_t * encoded = NULL, *next; |
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1861 if (address < 0x4000) { |
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1862 encoded = context->mem_pointers[0] + (address & 0x1FFF); |
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1863 } else if(address >= 0x8000 && context->mem_pointers[1]) { |
394
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Mike Pavone <pavone@retrodev.com>
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diff
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|
1864 printf("attempt to translate Z80 code from banked area at address %X\n", address); |
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|
1865 exit(1); |
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|
1866 //encoded = context->mem_pointers[1] + (address & 0x7FFF); |
235
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1867 } |
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1868 while (encoded != NULL) |
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1869 { |
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1870 z80inst inst; |
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1871 dprintf("translating Z80 code at address %X\n", address); |
235
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1872 do { |
252
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1873 if (opts->code_end-opts->cur_code < ZMAX_NATIVE_SIZE) { |
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1874 if (opts->code_end-opts->cur_code < 5) { |
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1875 puts("out of code memory, not enough space for jmp to next chunk"); |
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|
1876 exit(1); |
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|
1877 } |
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1878 size_t size = 1024*1024; |
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1879 opts->cur_code = alloc_code(&size); |
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1880 opts->code_end = opts->cur_code + size; |
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1881 jmp(opts->cur_code, opts->cur_code); |
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1882 } |
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1883 if (address > 0x4000 && address < 0x8000) { |
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1884 opts->cur_code = xor_rr(opts->cur_code, RDI, RDI, SZ_D); |
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1885 opts->cur_code = call(opts->cur_code, (uint8_t *)exit); |
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1886 break; |
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1887 } |
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1888 uint8_t * existing = z80_get_native_address(context, address); |
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1889 if (existing) { |
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1890 opts->cur_code = jmp(opts->cur_code, existing); |
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1891 break; |
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1892 } |
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1893 next = z80_decode(encoded, &inst); |
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1894 #ifdef DO_DEBUG_PRINT |
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1895 z80_disasm(&inst, disbuf, address); |
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1896 if (inst.op == Z80_NOP) { |
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1897 printf("%X\t%s(%d)\n", address, disbuf, inst.immed); |
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1898 } else { |
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1899 printf("%X\t%s\n", address, disbuf); |
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1900 } |
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1901 #endif |
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1902 uint8_t *after = translate_z80inst(&inst, opts->cur_code, context, address); |
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1903 z80_map_native_address(context, address, opts->cur_code, next-encoded, after - opts->cur_code); |
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1904 opts->cur_code = after; |
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1905 address += next-encoded; |
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1906 if (address > 0xFFFF) { |
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1907 address &= 0xFFFF; |
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1908 |
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1909 } else { |
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1910 encoded = next; |
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1911 } |
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1912 } while (!z80_is_terminal(&inst)); |
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1913 process_deferred(&opts->deferred, context, (native_addr_func)z80_get_native_address); |
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1914 if (opts->deferred) { |
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1915 address = opts->deferred->address; |
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1916 dprintf("defferred address: %X\n", address); |
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1917 if (address < 0x4000) { |
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1918 encoded = context->mem_pointers[0] + (address & 0x1FFF); |
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1919 } else if (address > 0x8000 && context->mem_pointers[1]) { |
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1920 encoded = context->mem_pointers[1] + (address & 0x7FFF); |
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1921 } else { |
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1922 printf("attempt to translate non-memory address: %X\n", address); |
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1923 exit(1); |
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1924 } |
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1925 } else { |
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1926 encoded = NULL; |
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1927 } |
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1928 } |
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1929 } |
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1930 |
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1931 void init_x86_z80_opts(x86_z80_options * options) |
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1932 { |
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1933 options->flags = 0; |
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1934 options->regs[Z80_B] = BH; |
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1935 options->regs[Z80_C] = RBX; |
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1936 options->regs[Z80_D] = CH; |
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1937 options->regs[Z80_E] = RCX; |
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1938 options->regs[Z80_H] = AH; |
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1939 options->regs[Z80_L] = RAX; |
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1940 options->regs[Z80_IXH] = DH; |
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1941 options->regs[Z80_IXL] = RDX; |
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1942 options->regs[Z80_IYH] = -1; |
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1943 options->regs[Z80_IYL] = R8; |
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1944 options->regs[Z80_I] = -1; |
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1945 options->regs[Z80_R] = -1; |
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1946 options->regs[Z80_A] = R10; |
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1947 options->regs[Z80_BC] = RBX; |
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1948 options->regs[Z80_DE] = RCX; |
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1949 options->regs[Z80_HL] = RAX; |
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1950 options->regs[Z80_SP] = R9; |
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1951 options->regs[Z80_AF] = -1; |
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1952 options->regs[Z80_IX] = RDX; |
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1953 options->regs[Z80_IY] = R8; |
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1954 size_t size = 1024 * 1024; |
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1955 options->cur_code = alloc_code(&size); |
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1956 options->code_end = options->cur_code + size; |
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1957 options->ram_inst_sizes = malloc(sizeof(uint8_t) * 0x2000); |
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1958 memset(options->ram_inst_sizes, 0, sizeof(uint8_t) * 0x2000); |
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1959 options->deferred = NULL; |
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1960 } |
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1961 |
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1962 void init_z80_context(z80_context * context, x86_z80_options * options) |
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1963 { |
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1964 memset(context, 0, sizeof(*context)); |
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1965 context->static_code_map = malloc(sizeof(*context->static_code_map)); |
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1966 context->static_code_map->base = NULL; |
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1967 context->static_code_map->offsets = malloc(sizeof(int32_t) * 0x2000); |
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1968 memset(context->static_code_map->offsets, 0xFF, sizeof(int32_t) * 0x2000); |
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1969 context->banked_code_map = malloc(sizeof(native_map_slot) * (1 << 9)); |
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1970 memset(context->banked_code_map, 0, sizeof(native_map_slot) * (1 << 9)); |
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1971 context->options = options; |
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1972 context->int_cycle = 0xFFFFFFFF; |
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1973 } |
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1974 |
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1975 void z80_reset(z80_context * context) |
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1976 { |
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1977 context->im = 0; |
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1978 context->iff1 = context->iff2 = 0; |
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1979 context->native_pc = z80_get_native_address_trans(context, 0); |
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1980 context->extra_pc = NULL; |
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1981 } |
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1982 |
626
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1983 uint8_t * zbreakpoint_patch(z80_context * context, uint16_t address, uint8_t * native) |
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1984 { |
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1985 native = mov_ir(native, address, SCRATCH1, SZ_W); |
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1986 native = call(native, context->bp_stub); |
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1987 return native; |
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1988 } |
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1989 |
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1990 void zcreate_stub(z80_context * context) |
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1991 { |
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1992 x86_z80_options * opts = context->options; |
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1993 uint8_t * dst = opts->cur_code; |
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1994 uint8_t * dst_end = opts->code_end; |
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1995 if (dst_end - dst < 128) { |
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1996 size_t size = 1024*1024; |
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1997 dst = alloc_code(&size); |
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1998 opts->code_end = dst_end = dst + size; |
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1999 } |
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2000 context->bp_stub = dst; |
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2001 |
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2002 //Calculate length of prologue |
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2003 int check_int_size = z80_check_cycles_int(dst, 0) - dst; |
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2004 |
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2005 //Calculate length of patch |
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2006 int patch_size = zbreakpoint_patch(context, 0, dst) - dst; |
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2007 |
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2008 //Save context and call breakpoint handler |
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2009 dst = call(dst, (uint8_t *)z80_save_context); |
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2010 dst = push_r(dst, SCRATCH1); |
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2011 dst = mov_rr(dst, CONTEXT, RDI, SZ_Q); |
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2012 dst = mov_rr(dst, SCRATCH1, RSI, SZ_W); |
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2013 dst = call(dst, context->bp_handler); |
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2014 dst = mov_rr(dst, RAX, CONTEXT, SZ_Q); |
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2015 //Restore context |
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|
2016 dst = call(dst, (uint8_t *)z80_load_context); |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
2017 dst = pop_r(dst, SCRATCH1); |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
2018 //do prologue stuff |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
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2019 dst = cmp_rr(dst, ZCYCLES, ZLIMIT, SZ_D); |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
2020 uint8_t * jmp_off = dst+1; |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
2021 dst = jcc(dst, CC_NC, dst + 7); |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
2022 dst = pop_r(dst, SCRATCH1); |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
2023 dst = add_ir(dst, check_int_size - patch_size, SCRATCH1, SZ_Q); |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
2024 dst = push_r(dst, SCRATCH1); |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
2025 dst = jmp(dst, (uint8_t *)z80_handle_cycle_limit_int); |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
2026 *jmp_off = dst - (jmp_off+1); |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
2027 //jump back to body of translated instruction |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
2028 dst = pop_r(dst, SCRATCH1); |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
2029 dst = add_ir(dst, check_int_size - patch_size, SCRATCH1, SZ_Q); |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
2030 dst = jmp_r(dst, SCRATCH1); |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
2031 opts->cur_code = dst; |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
2032 } |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
2033 |
366
836585d389b8
Partial implementation of Z80 debugger
Mike Pavone <pavone@retrodev.com>
parents:
363
diff
changeset
|
2034 void zinsert_breakpoint(z80_context * context, uint16_t address, uint8_t * bp_handler) |
836585d389b8
Partial implementation of Z80 debugger
Mike Pavone <pavone@retrodev.com>
parents:
363
diff
changeset
|
2035 { |
626
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
2036 context->bp_handler = bp_handler; |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
2037 uint8_t bit = 1 << (address % sizeof(uint8_t)); |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
2038 if (!(bit & context->breakpoint_flags[address / sizeof(uint8_t)])) { |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
2039 context->breakpoint_flags[address / sizeof(uint8_t)] |= bit; |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
2040 if (!context->bp_stub) { |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
2041 zcreate_stub(context); |
366
836585d389b8
Partial implementation of Z80 debugger
Mike Pavone <pavone@retrodev.com>
parents:
363
diff
changeset
|
2042 } |
626
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
2043 uint8_t * native = z80_get_native_address(context, address); |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
2044 if (native) { |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
2045 zbreakpoint_patch(context, address, native); |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
2046 } |
366
836585d389b8
Partial implementation of Z80 debugger
Mike Pavone <pavone@retrodev.com>
parents:
363
diff
changeset
|
2047 } |
836585d389b8
Partial implementation of Z80 debugger
Mike Pavone <pavone@retrodev.com>
parents:
363
diff
changeset
|
2048 } |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2049 |
366
836585d389b8
Partial implementation of Z80 debugger
Mike Pavone <pavone@retrodev.com>
parents:
363
diff
changeset
|
2050 void zremove_breakpoint(z80_context * context, uint16_t address) |
836585d389b8
Partial implementation of Z80 debugger
Mike Pavone <pavone@retrodev.com>
parents:
363
diff
changeset
|
2051 { |
626
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
2052 context->breakpoint_flags[address / sizeof(uint8_t)] &= 1 << (address % sizeof(uint8_t)); |
366
836585d389b8
Partial implementation of Z80 debugger
Mike Pavone <pavone@retrodev.com>
parents:
363
diff
changeset
|
2053 uint8_t * native = z80_get_native_address(context, address); |
626
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
2054 if (native) { |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
2055 z80_check_cycles_int(native, address); |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
2056 } |
366
836585d389b8
Partial implementation of Z80 debugger
Mike Pavone <pavone@retrodev.com>
parents:
363
diff
changeset
|
2057 } |
836585d389b8
Partial implementation of Z80 debugger
Mike Pavone <pavone@retrodev.com>
parents:
363
diff
changeset
|
2058 |
836585d389b8
Partial implementation of Z80 debugger
Mike Pavone <pavone@retrodev.com>
parents:
363
diff
changeset
|
2059 |