Mercurial > repos > blastem
annotate z80_to_x86.c @ 663:7a5461001242
Sync Z80 when taking an interrupt so that int_cycle gets updated
author | Michael Pavone <pavone@retrodev.com> |
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date | Fri, 02 Jan 2015 00:19:10 -0800 |
parents | 66388360f873 |
children | bca748422bf0 |
rev | line source |
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1 /* |
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2 Copyright 2013 Michael Pavone |
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The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
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3 This file is part of BlastEm. |
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4 BlastEm is free software distributed under the terms of the GNU General Public License version 3 or greater. See COPYING for full license text. |
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5 */ |
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6 #include "z80inst.h" |
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7 #include "z80_to_x86.h" |
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8 #include "gen_x86.h" |
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9 #include "mem.h" |
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10 #include <stdio.h> |
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11 #include <stdlib.h> |
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12 #include <stddef.h> |
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13 #include <string.h> |
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14 |
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15 #define MODE_UNUSED (MODE_IMMED-1) |
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16 |
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17 //#define DO_DEBUG_PRINT |
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18 |
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19 #ifdef DO_DEBUG_PRINT |
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20 #define dprintf printf |
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21 #else |
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22 #define dprintf |
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23 #endif |
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24 |
652 | 25 uint32_t zbreakpoint_patch(z80_context * context, uint16_t address, code_ptr dst); |
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26 |
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27 uint8_t z80_size(z80inst * inst) |
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28 { |
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29 uint8_t reg = (inst->reg & 0x1F); |
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30 if (reg != Z80_UNUSED && reg != Z80_USE_IMMED) { |
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31 return reg < Z80_BC ? SZ_B : SZ_W; |
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32 } |
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33 //TODO: Handle any necessary special cases |
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34 return SZ_B; |
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35 } |
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36 |
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37 void translate_z80_reg(z80inst * inst, host_ea * ea, z80_options * opts) |
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38 { |
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39 code_info *code = &opts->gen.code; |
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40 if (inst->reg == Z80_USE_IMMED) { |
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41 ea->mode = MODE_IMMED; |
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42 ea->disp = inst->immed; |
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43 } else if ((inst->reg & 0x1F) == Z80_UNUSED) { |
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44 ea->mode = MODE_UNUSED; |
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45 } else { |
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46 ea->mode = MODE_REG_DIRECT; |
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47 if (inst->reg == Z80_IYH) { |
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48 if ((inst->addr_mode & 0x1F) == Z80_REG && inst->ea_reg == Z80_IYL) { |
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49 mov_rr(code, opts->regs[Z80_IY], opts->gen.scratch1, SZ_W); |
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50 ror_ir(code, 8, opts->gen.scratch1, SZ_W); |
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51 ea->base = opts->gen.scratch1; |
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52 } else { |
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53 ea->base = opts->regs[Z80_IYL]; |
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54 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W); |
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55 } |
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56 } else if(opts->regs[inst->reg] >= 0) { |
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57 ea->base = opts->regs[inst->reg]; |
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58 if (ea->base >= AH && ea->base <= BH) { |
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59 if ((inst->addr_mode & 0x1F) == Z80_REG) { |
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60 uint8_t other_reg = opts->regs[inst->ea_reg]; |
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61 if (other_reg >= R8 || (other_reg >= RSP && other_reg <= RDI)) { |
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62 //we can't mix an *H reg with a register that requires the REX prefix |
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63 ea->base = opts->regs[z80_low_reg(inst->reg)]; |
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64 ror_ir(code, 8, ea->base, SZ_W); |
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65 } |
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66 } else if((inst->addr_mode & 0x1F) != Z80_UNUSED && (inst->addr_mode & 0x1F) != Z80_IMMED) { |
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67 //temp regs require REX prefix too |
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68 ea->base = opts->regs[z80_low_reg(inst->reg)]; |
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69 ror_ir(code, 8, ea->base, SZ_W); |
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70 } |
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71 } |
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72 } else { |
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73 ea->mode = MODE_REG_DISPLACE8; |
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74 ea->base = opts->gen.context_reg; |
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75 ea->disp = offsetof(z80_context, regs) + inst->reg; |
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76 } |
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77 } |
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78 } |
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79 |
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80 void z80_save_reg(z80inst * inst, z80_options * opts) |
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81 { |
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82 code_info *code = &opts->gen.code; |
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83 if (inst->reg == Z80_IYH) { |
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84 if ((inst->addr_mode & 0x1F) == Z80_REG && inst->ea_reg == Z80_IYL) { |
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85 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W); |
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86 mov_rr(code, opts->gen.scratch1, opts->regs[Z80_IYL], SZ_B); |
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87 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W); |
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88 } else { |
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89 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W); |
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90 } |
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91 } else if (opts->regs[inst->reg] >= AH && opts->regs[inst->reg] <= BH) { |
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92 if ((inst->addr_mode & 0x1F) == Z80_REG) { |
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93 uint8_t other_reg = opts->regs[inst->ea_reg]; |
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94 if (other_reg >= R8 || (other_reg >= RSP && other_reg <= RDI)) { |
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95 //we can't mix an *H reg with a register that requires the REX prefix |
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96 ror_ir(code, 8, opts->regs[z80_low_reg(inst->reg)], SZ_W); |
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97 } |
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98 } else if((inst->addr_mode & 0x1F) != Z80_UNUSED && (inst->addr_mode & 0x1F) != Z80_IMMED) { |
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99 //temp regs require REX prefix too |
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100 ror_ir(code, 8, opts->regs[z80_low_reg(inst->reg)], SZ_W); |
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101 } |
213
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102 } |
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103 } |
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104 |
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105 void translate_z80_ea(z80inst * inst, host_ea * ea, z80_options * opts, uint8_t read, uint8_t modify) |
213
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106 { |
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107 code_info *code = &opts->gen.code; |
213
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108 uint8_t size, reg, areg; |
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109 ea->mode = MODE_REG_DIRECT; |
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110 areg = read ? opts->gen.scratch1 : opts->gen.scratch2; |
213
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111 switch(inst->addr_mode & 0x1F) |
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112 { |
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113 case Z80_REG: |
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114 if (inst->ea_reg == Z80_IYH) { |
312
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115 if (inst->reg == Z80_IYL) { |
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116 mov_rr(code, opts->regs[Z80_IY], opts->gen.scratch1, SZ_W); |
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117 ror_ir(code, 8, opts->gen.scratch1, SZ_W); |
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118 ea->base = opts->gen.scratch1; |
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119 } else { |
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120 ea->base = opts->regs[Z80_IYL]; |
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121 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W); |
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122 } |
651
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123 } else if(opts->regs[inst->ea_reg] >= 0) { |
213
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124 ea->base = opts->regs[inst->ea_reg]; |
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125 if (ea->base >= AH && ea->base <= BH && inst->reg != Z80_UNUSED && inst->reg != Z80_USE_IMMED) { |
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126 uint8_t other_reg = opts->regs[inst->reg]; |
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268
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127 if (other_reg >= R8 || (other_reg >= RSP && other_reg <= RDI)) { |
267
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128 //we can't mix an *H reg with a register that requires the REX prefix |
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129 ea->base = opts->regs[z80_low_reg(inst->ea_reg)]; |
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130 ror_ir(code, 8, ea->base, SZ_W); |
267
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131 } |
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132 } |
651
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133 } else { |
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134 ea->mode = MODE_REG_DISPLACE8; |
659
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135 ea->base = opts->gen.context_reg; |
651
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136 ea->disp = offsetof(z80_context, regs) + inst->ea_reg; |
213
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137 } |
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138 break; |
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139 case Z80_REG_INDIRECT: |
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140 mov_rr(code, opts->regs[inst->ea_reg], areg, SZ_W); |
213
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141 size = z80_size(inst); |
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142 if (read) { |
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143 if (modify) { |
590
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144 //push_r(code, opts->gen.scratch1); |
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145 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, offsetof(z80_context, scratch1), SZ_W); |
213
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146 } |
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147 if (size == SZ_B) { |
590
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148 call(code, opts->read_8); |
213
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149 } else { |
591
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150 call(code, opts->read_16); |
213
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151 } |
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152 if (modify) { |
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153 //pop_r(code, opts->gen.scratch2); |
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154 mov_rdispr(code, opts->gen.context_reg, offsetof(z80_context, scratch1), opts->gen.scratch2, SZ_W); |
213
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155 } |
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156 } |
590
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157 ea->base = opts->gen.scratch1; |
213
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158 break; |
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159 case Z80_IMMED: |
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160 ea->mode = MODE_IMMED; |
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161 ea->disp = inst->immed; |
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162 break; |
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163 case Z80_IMMED_INDIRECT: |
591
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164 mov_ir(code, inst->immed, areg, SZ_W); |
213
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165 size = z80_size(inst); |
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166 if (read) { |
277
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167 /*if (modify) { |
591
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168 push_r(code, opts->gen.scratch1); |
277
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169 }*/ |
213
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170 if (size == SZ_B) { |
593
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171 call(code, opts->read_8); |
213
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172 } else { |
593
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173 call(code, opts->read_16); |
213
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174 } |
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175 if (modify) { |
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176 //pop_r(code, opts->gen.scratch2); |
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177 mov_ir(code, inst->immed, opts->gen.scratch2, SZ_W); |
213
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178 } |
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179 } |
590
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180 ea->base = opts->gen.scratch1; |
213
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181 break; |
235
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182 case Z80_IX_DISPLACE: |
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183 case Z80_IY_DISPLACE: |
300
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299
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|
184 reg = opts->regs[(inst->addr_mode & 0x1F) == Z80_IX_DISPLACE ? Z80_IX : Z80_IY]; |
591
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185 mov_rr(code, reg, areg, SZ_W); |
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186 add_ir(code, inst->ea_reg & 0x80 ? inst->ea_reg - 256 : inst->ea_reg, areg, SZ_W); |
213
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187 size = z80_size(inst); |
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188 if (read) { |
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189 if (modify) { |
591
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190 //push_r(code, opts->gen.scratch1); |
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191 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, offsetof(z80_context, scratch1), SZ_W); |
213
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192 } |
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193 if (size == SZ_B) { |
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194 call(code, opts->read_8); |
213
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195 } else { |
593
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196 call(code, opts->read_16); |
213
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197 } |
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198 if (modify) { |
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199 //pop_r(code, opts->gen.scratch2); |
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200 mov_rdispr(code, opts->gen.context_reg, offsetof(z80_context, scratch1), opts->gen.scratch2, SZ_W); |
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201 } |
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202 } |
590
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203 ea->base = opts->gen.scratch1; |
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204 break; |
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205 case Z80_UNUSED: |
235
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206 ea->mode = MODE_UNUSED; |
213
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207 break; |
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208 default: |
300
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209 fprintf(stderr, "Unrecognized Z80 addressing mode %d\n", inst->addr_mode & 0x1F); |
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210 exit(1); |
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211 } |
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212 } |
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213 |
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214 void z80_save_ea(code_info *code, z80inst * inst, z80_options * opts) |
213
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215 { |
267
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216 if ((inst->addr_mode & 0x1F) == Z80_REG) { |
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217 if (inst->ea_reg == Z80_IYH) { |
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218 if (inst->reg == Z80_IYL) { |
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219 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W); |
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220 mov_rr(code, opts->gen.scratch1, opts->regs[Z80_IYL], SZ_B); |
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221 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W); |
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222 } else { |
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223 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W); |
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224 } |
267
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225 } else if (inst->reg != Z80_UNUSED && inst->reg != Z80_USE_IMMED && opts->regs[inst->ea_reg] >= AH && opts->regs[inst->ea_reg] <= BH) { |
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226 uint8_t other_reg = opts->regs[inst->reg]; |
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227 if (other_reg >= R8 || (other_reg >= RSP && other_reg <= RDI)) { |
267
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228 //we can't mix an *H reg with a register that requires the REX prefix |
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229 ror_ir(code, 8, opts->regs[z80_low_reg(inst->ea_reg)], SZ_W); |
267
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230 } |
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231 } |
213
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232 } |
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233 } |
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234 |
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235 void z80_save_result(z80_options *opts, z80inst * inst) |
213
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236 { |
253
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237 switch(inst->addr_mode & 0x1f) |
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238 { |
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239 case Z80_REG_INDIRECT: |
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240 case Z80_IMMED_INDIRECT: |
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241 case Z80_IX_DISPLACE: |
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242 case Z80_IY_DISPLACE: |
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243 if (z80_size(inst) == SZ_B) { |
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244 call(&opts->gen.code, opts->write_8); |
253
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245 } else { |
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246 call(&opts->gen.code, opts->write_16_lowfirst); |
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247 } |
213
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248 } |
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249 } |
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250 |
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251 enum { |
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252 DONT_READ=0, |
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253 READ |
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254 }; |
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255 |
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256 enum { |
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257 DONT_MODIFY=0, |
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258 MODIFY |
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259 }; |
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260 |
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261 uint8_t zf_off(uint8_t flag) |
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262 { |
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263 return offsetof(z80_context, flags) + flag; |
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264 } |
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265 |
241
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266 uint8_t zaf_off(uint8_t flag) |
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267 { |
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268 return offsetof(z80_context, alt_flags) + flag; |
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269 } |
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270 |
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271 uint8_t zar_off(uint8_t reg) |
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272 { |
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273 return offsetof(z80_context, alt_regs) + reg; |
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274 } |
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275 |
235
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276 void z80_print_regs_exit(z80_context * context) |
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277 { |
505
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278 printf("A: %X\nB: %X\nC: %X\nD: %X\nE: %X\nHL: %X\nIX: %X\nIY: %X\nSP: %X\n\nIM: %d, IFF1: %d, IFF2: %d\n", |
235
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279 context->regs[Z80_A], context->regs[Z80_B], context->regs[Z80_C], |
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280 context->regs[Z80_D], context->regs[Z80_E], |
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281 (context->regs[Z80_H] << 8) | context->regs[Z80_L], |
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282 (context->regs[Z80_IXH] << 8) | context->regs[Z80_IXL], |
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283 (context->regs[Z80_IYH] << 8) | context->regs[Z80_IYL], |
243
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284 context->sp, context->im, context->iff1, context->iff2); |
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285 puts("--Alternate Regs--"); |
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286 printf("A: %X\nB: %X\nC: %X\nD: %X\nE: %X\nHL: %X\nIX: %X\nIY: %X\n", |
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287 context->alt_regs[Z80_A], context->alt_regs[Z80_B], context->alt_regs[Z80_C], |
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288 context->alt_regs[Z80_D], context->alt_regs[Z80_E], |
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289 (context->alt_regs[Z80_H] << 8) | context->alt_regs[Z80_L], |
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290 (context->alt_regs[Z80_IXH] << 8) | context->alt_regs[Z80_IXL], |
241
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291 (context->alt_regs[Z80_IYH] << 8) | context->alt_regs[Z80_IYL]); |
235
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292 exit(0); |
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293 } |
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294 |
652 | 295 void translate_z80inst(z80inst * inst, z80_context * context, uint16_t address, uint8_t interp) |
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296 { |
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297 uint32_t num_cycles; |
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298 host_ea src_op, dst_op; |
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299 uint8_t size; |
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300 z80_options *opts = context->options; |
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301 uint8_t * start = opts->gen.code.cur; |
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302 code_info *code = &opts->gen.code; |
627
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303 if (!interp) { |
652 | 304 check_cycles_int(&opts->gen, address); |
627
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305 if (context->breakpoint_flags[address / sizeof(uint8_t)] & (1 << (address % sizeof(uint8_t)))) { |
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306 zbreakpoint_patch(context, address, start); |
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307 } |
626
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308 } |
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309 switch(inst->op) |
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310 { |
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311 case Z80_LD: |
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312 size = z80_size(inst); |
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313 switch (inst->addr_mode & 0x1F) |
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314 { |
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315 case Z80_REG: |
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316 case Z80_REG_INDIRECT: |
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317 num_cycles = size == SZ_B ? 4 : 6; |
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318 if (inst->ea_reg == Z80_IX || inst->ea_reg == Z80_IY) { |
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319 num_cycles += 4; |
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320 } |
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321 if (inst->reg == Z80_I || inst->ea_reg == Z80_I) { |
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322 num_cycles += 5; |
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323 } |
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324 break; |
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325 case Z80_IMMED: |
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326 num_cycles = size == SZ_B ? 7 : 10; |
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327 break; |
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328 case Z80_IMMED_INDIRECT: |
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329 num_cycles = 10; |
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330 break; |
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331 case Z80_IX_DISPLACE: |
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332 case Z80_IY_DISPLACE: |
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333 num_cycles = 16; |
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334 break; |
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335 } |
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336 if ((inst->reg >= Z80_IXL && inst->reg <= Z80_IYH) || inst->reg == Z80_IX || inst->reg == Z80_IY) { |
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337 num_cycles += 4; |
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338 } |
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339 cycles(&opts->gen, num_cycles); |
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340 if (inst->addr_mode & Z80_DIR) { |
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341 translate_z80_ea(inst, &dst_op, opts, DONT_READ, MODIFY); |
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342 translate_z80_reg(inst, &src_op, opts); |
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343 } else { |
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344 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY); |
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345 translate_z80_reg(inst, &dst_op, opts); |
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346 } |
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347 if (src_op.mode == MODE_REG_DIRECT) { |
262
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348 if(dst_op.mode == MODE_REG_DISPLACE8) { |
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349 mov_rrdisp(code, src_op.base, dst_op.base, dst_op.disp, size); |
262
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350 } else { |
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351 mov_rr(code, src_op.base, dst_op.base, size); |
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352 } |
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353 } else if(src_op.mode == MODE_IMMED) { |
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354 mov_ir(code, src_op.disp, dst_op.base, size); |
213
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355 } else { |
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356 mov_rdispr(code, src_op.base, src_op.disp, dst_op.base, size); |
213
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357 } |
651
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358 if (inst->ea_reg == Z80_I && inst->addr_mode == Z80_REG) { |
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359 //ld a, i sets some flags |
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360 //TODO: Implement half-carry flag |
652 | 361 cmp_ir(code, 0, dst_op.base, SZ_B); |
362 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); | |
363 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); | |
364 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);; | |
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365 mov_rdispr(code, opts->gen.context_reg, offsetof(z80_context, iff2), opts->gen.scratch1, SZ_B); |
652 | 366 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_PV), SZ_B); |
651
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367 } |
591
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368 z80_save_reg(inst, opts); |
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369 z80_save_ea(code, inst, opts); |
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370 if (inst->addr_mode & Z80_DIR) { |
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371 z80_save_result(opts, inst); |
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372 } |
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373 break; |
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374 case Z80_PUSH: |
591
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375 cycles(&opts->gen, (inst->reg == Z80_IX || inst->reg == Z80_IY) ? 9 : 5); |
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376 sub_ir(code, 2, opts->regs[Z80_SP], SZ_W); |
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377 if (inst->reg == Z80_AF) { |
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378 mov_rr(code, opts->regs[Z80_A], opts->gen.scratch1, SZ_B); |
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379 shl_ir(code, 8, opts->gen.scratch1, SZ_W); |
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380 mov_rdispr(code, opts->gen.context_reg, zf_off(ZF_S), opts->gen.scratch1, SZ_B); |
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381 shl_ir(code, 1, opts->gen.scratch1, SZ_B); |
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382 or_rdispr(code, opts->gen.context_reg, zf_off(ZF_Z), opts->gen.scratch1, SZ_B); |
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383 shl_ir(code, 2, opts->gen.scratch1, SZ_B); |
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384 or_rdispr(code, opts->gen.context_reg, zf_off(ZF_H), opts->gen.scratch1, SZ_B); |
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385 shl_ir(code, 2, opts->gen.scratch1, SZ_B); |
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386 or_rdispr(code, opts->gen.context_reg, zf_off(ZF_PV), opts->gen.scratch1, SZ_B); |
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387 shl_ir(code, 1, opts->gen.scratch1, SZ_B); |
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388 or_rdispr(code, opts->gen.context_reg, zf_off(ZF_N), opts->gen.scratch1, SZ_B); |
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389 shl_ir(code, 1, opts->gen.scratch1, SZ_B); |
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390 or_rdispr(code, opts->gen.context_reg, zf_off(ZF_C), opts->gen.scratch1, SZ_B); |
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391 } else { |
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392 translate_z80_reg(inst, &src_op, opts); |
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393 mov_rr(code, src_op.base, opts->gen.scratch1, SZ_W); |
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394 } |
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395 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch2, SZ_W); |
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396 call(code, opts->write_16_highfirst); |
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397 //no call to save_z80_reg needed since there's no chance we'll use the only |
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398 //the upper half of a register pair |
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399 break; |
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400 case Z80_POP: |
591
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401 cycles(&opts->gen, (inst->reg == Z80_IX || inst->reg == Z80_IY) ? 8 : 4); |
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402 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W); |
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403 call(code, opts->read_16); |
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404 add_ir(code, 2, opts->regs[Z80_SP], SZ_W); |
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405 if (inst->reg == Z80_AF) { |
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406 |
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407 bt_ir(code, 0, opts->gen.scratch1, SZ_W); |
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408 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
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409 bt_ir(code, 1, opts->gen.scratch1, SZ_W); |
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410 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_N)); |
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411 bt_ir(code, 2, opts->gen.scratch1, SZ_W); |
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412 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_PV)); |
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413 bt_ir(code, 4, opts->gen.scratch1, SZ_W); |
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414 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H)); |
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415 bt_ir(code, 6, opts->gen.scratch1, SZ_W); |
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416 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_Z)); |
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417 bt_ir(code, 7, opts->gen.scratch1, SZ_W); |
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418 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_S)); |
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419 shr_ir(code, 8, opts->gen.scratch1, SZ_W); |
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420 mov_rr(code, opts->gen.scratch1, opts->regs[Z80_A], SZ_B); |
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421 } else { |
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422 translate_z80_reg(inst, &src_op, opts); |
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423 mov_rr(code, opts->gen.scratch1, src_op.base, SZ_W); |
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424 } |
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425 //no call to save_z80_reg needed since there's no chance we'll use the only |
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426 //the upper half of a register pair |
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427 break; |
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428 case Z80_EX: |
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429 if (inst->addr_mode == Z80_REG || inst->reg == Z80_HL) { |
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430 num_cycles = 4; |
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431 } else { |
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432 num_cycles = 8; |
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433 } |
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434 cycles(&opts->gen, num_cycles); |
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435 if (inst->addr_mode == Z80_REG) { |
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436 if(inst->reg == Z80_AF) { |
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437 mov_rr(code, opts->regs[Z80_A], opts->gen.scratch1, SZ_B); |
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438 mov_rdispr(code, opts->gen.context_reg, zar_off(Z80_A), opts->regs[Z80_A], SZ_B); |
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439 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zar_off(Z80_A), SZ_B); |
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440 |
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441 //Flags are currently word aligned, so we can move |
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442 //them efficiently a word at a time |
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443 for (int f = ZF_C; f < ZF_NUM; f+=2) { |
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444 mov_rdispr(code, opts->gen.context_reg, zf_off(f), opts->gen.scratch1, SZ_W); |
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445 mov_rdispr(code, opts->gen.context_reg, zaf_off(f), opts->gen.scratch2, SZ_W); |
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446 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zaf_off(f), SZ_W); |
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447 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(f), SZ_W); |
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448 } |
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449 } else { |
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450 xchg_rr(code, opts->regs[Z80_DE], opts->regs[Z80_HL], SZ_W); |
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451 } |
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452 } else { |
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453 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W); |
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454 call(code, opts->read_8); |
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455 xchg_rr(code, opts->regs[inst->reg], opts->gen.scratch1, SZ_B); |
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456 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch2, SZ_W); |
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457 call(code, opts->write_8); |
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458 cycles(&opts->gen, 1); |
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459 uint8_t high_reg = z80_high_reg(inst->reg); |
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460 uint8_t use_reg; |
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461 //even though some of the upper halves can be used directly |
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462 //the limitations on mixing *H regs with the REX prefix |
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463 //prevent us from taking advantage of it |
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464 use_reg = opts->regs[inst->reg]; |
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465 ror_ir(code, 8, use_reg, SZ_W); |
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466 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W); |
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467 add_ir(code, 1, opts->gen.scratch1, SZ_W); |
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468 call(code, opts->read_8); |
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469 xchg_rr(code, use_reg, opts->gen.scratch1, SZ_B); |
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470 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch2, SZ_W); |
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471 add_ir(code, 1, opts->gen.scratch2, SZ_W); |
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472 call(code, opts->write_8); |
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473 //restore reg to normal rotation |
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474 ror_ir(code, 8, use_reg, SZ_W); |
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475 cycles(&opts->gen, 2); |
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476 } |
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477 break; |
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478 case Z80_EXX: |
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479 cycles(&opts->gen, 4); |
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480 mov_rr(code, opts->regs[Z80_BC], opts->gen.scratch1, SZ_W); |
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481 mov_rr(code, opts->regs[Z80_HL], opts->gen.scratch2, SZ_W); |
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482 mov_rdispr(code, opts->gen.context_reg, zar_off(Z80_C), opts->regs[Z80_BC], SZ_W); |
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483 mov_rdispr(code, opts->gen.context_reg, zar_off(Z80_L), opts->regs[Z80_HL], SZ_W); |
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484 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zar_off(Z80_C), SZ_W); |
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485 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zar_off(Z80_L), SZ_W); |
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486 mov_rr(code, opts->regs[Z80_DE], opts->gen.scratch1, SZ_W); |
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487 mov_rdispr(code, opts->gen.context_reg, zar_off(Z80_E), opts->regs[Z80_DE], SZ_W); |
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488 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zar_off(Z80_E), SZ_W); |
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489 break; |
272 | 490 case Z80_LDI: { |
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491 cycles(&opts->gen, 8); |
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492 mov_rr(code, opts->regs[Z80_HL], opts->gen.scratch1, SZ_W); |
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493 call(code, opts->read_8); |
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494 mov_rr(code, opts->regs[Z80_DE], opts->gen.scratch2, SZ_W); |
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495 call(code, opts->write_8); |
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496 cycles(&opts->gen, 2); |
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497 add_ir(code, 1, opts->regs[Z80_DE], SZ_W); |
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498 add_ir(code, 1, opts->regs[Z80_HL], SZ_W); |
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499 sub_ir(code, 1, opts->regs[Z80_BC], SZ_W); |
272 | 500 //TODO: Implement half-carry |
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501 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
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502 setcc_rdisp(code, CC_NZ, opts->gen.context_reg, zf_off(ZF_PV)); |
272 | 503 break; |
504 } | |
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505 case Z80_LDIR: { |
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506 cycles(&opts->gen, 8); |
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507 mov_rr(code, opts->regs[Z80_HL], opts->gen.scratch1, SZ_W); |
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508 call(code, opts->read_8); |
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509 mov_rr(code, opts->regs[Z80_DE], opts->gen.scratch2, SZ_W); |
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510 call(code, opts->write_8); |
591
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511 add_ir(code, 1, opts->regs[Z80_DE], SZ_W); |
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512 add_ir(code, 1, opts->regs[Z80_HL], SZ_W); |
505
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The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
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513 |
591
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514 sub_ir(code, 1, opts->regs[Z80_BC], SZ_W); |
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515 uint8_t * cont = code->cur+1; |
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516 jcc(code, CC_Z, code->cur+2); |
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517 cycles(&opts->gen, 7); |
261
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518 //TODO: Figure out what the flag state should be here |
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519 //TODO: Figure out whether an interrupt can interrupt this |
591
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520 jmp(code, start); |
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521 *cont = code->cur - (cont + 1); |
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522 cycles(&opts->gen, 2); |
261
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523 //TODO: Implement half-carry |
591
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524 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
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525 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_PV), SZ_B); |
261
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526 break; |
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527 } |
273 | 528 case Z80_LDD: { |
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529 cycles(&opts->gen, 8); |
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530 mov_rr(code, opts->regs[Z80_HL], opts->gen.scratch1, SZ_W); |
593
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531 call(code, opts->read_8); |
591
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532 mov_rr(code, opts->regs[Z80_DE], opts->gen.scratch2, SZ_W); |
593
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533 call(code, opts->write_8); |
591
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534 cycles(&opts->gen, 2); |
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535 sub_ir(code, 1, opts->regs[Z80_DE], SZ_W); |
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536 sub_ir(code, 1, opts->regs[Z80_HL], SZ_W); |
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537 sub_ir(code, 1, opts->regs[Z80_BC], SZ_W); |
273 | 538 //TODO: Implement half-carry |
591
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539 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
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540 setcc_rdisp(code, CC_NZ, opts->gen.context_reg, zf_off(ZF_PV)); |
273 | 541 break; |
542 } | |
543 case Z80_LDDR: { | |
591
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544 cycles(&opts->gen, 8); |
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545 mov_rr(code, opts->regs[Z80_HL], opts->gen.scratch1, SZ_W); |
593
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546 call(code, opts->read_8); |
591
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547 mov_rr(code, opts->regs[Z80_DE], opts->gen.scratch2, SZ_W); |
593
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548 call(code, opts->write_8); |
591
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549 sub_ir(code, 1, opts->regs[Z80_DE], SZ_W); |
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550 sub_ir(code, 1, opts->regs[Z80_HL], SZ_W); |
505
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The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
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551 |
591
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552 sub_ir(code, 1, opts->regs[Z80_BC], SZ_W); |
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553 uint8_t * cont = code->cur+1; |
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554 jcc(code, CC_Z, code->cur+2); |
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555 cycles(&opts->gen, 7); |
273 | 556 //TODO: Figure out what the flag state should be here |
557 //TODO: Figure out whether an interrupt can interrupt this | |
591
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558 jmp(code, start); |
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559 *cont = code->cur - (cont + 1); |
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560 cycles(&opts->gen, 2); |
273 | 561 //TODO: Implement half-carry |
591
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562 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
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563 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_PV), SZ_B); |
273 | 564 break; |
565 } | |
566 /*case Z80_CPI: | |
213
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567 case Z80_CPIR: |
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568 case Z80_CPD: |
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569 case Z80_CPDR: |
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570 break;*/ |
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571 case Z80_ADD: |
591
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572 num_cycles = 4; |
235
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573 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
591
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574 num_cycles += 12; |
213
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575 } else if(inst->addr_mode == Z80_IMMED) { |
591
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576 num_cycles += 3; |
213
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577 } else if(z80_size(inst) == SZ_W) { |
591
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578 num_cycles += 4; |
213
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579 } |
591
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580 cycles(&opts->gen, num_cycles); |
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581 translate_z80_reg(inst, &dst_op, opts); |
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582 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY); |
213
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583 if (src_op.mode == MODE_REG_DIRECT) { |
591
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584 add_rr(code, src_op.base, dst_op.base, z80_size(inst)); |
213
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585 } else { |
591
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586 add_ir(code, src_op.disp, dst_op.base, z80_size(inst)); |
213
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587 } |
591
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588 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
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589 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
213
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590 //TODO: Implement half-carry flag |
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591 if (z80_size(inst) == SZ_B) { |
591
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592 setcc_rdisp(code, CC_O, opts->gen.context_reg, zf_off(ZF_PV)); |
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593 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
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594 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
213
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595 } |
591
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596 z80_save_reg(inst, opts); |
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597 z80_save_ea(code, inst, opts); |
213
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598 break; |
248
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599 case Z80_ADC: |
591
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600 num_cycles = 4; |
248
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601 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
591
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602 num_cycles += 12; |
248
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603 } else if(inst->addr_mode == Z80_IMMED) { |
591
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604 num_cycles += 3; |
248
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605 } else if(z80_size(inst) == SZ_W) { |
591
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606 num_cycles += 4; |
248
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607 } |
591
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608 cycles(&opts->gen, num_cycles); |
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609 translate_z80_reg(inst, &dst_op, opts); |
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610 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY); |
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611 bt_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B); |
248
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612 if (src_op.mode == MODE_REG_DIRECT) { |
591
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613 adc_rr(code, src_op.base, dst_op.base, z80_size(inst)); |
248
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614 } else { |
591
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615 adc_ir(code, src_op.disp, dst_op.base, z80_size(inst)); |
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616 } |
591
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617 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
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618 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
248
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619 //TODO: Implement half-carry flag |
591
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620 setcc_rdisp(code, CC_O, opts->gen.context_reg, zf_off(ZF_PV)); |
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621 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
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622 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
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623 z80_save_reg(inst, opts); |
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624 z80_save_ea(code, inst, opts); |
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625 break; |
213
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626 case Z80_SUB: |
591
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627 num_cycles = 4; |
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628 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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629 num_cycles += 12; |
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630 } else if(inst->addr_mode == Z80_IMMED) { |
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631 num_cycles += 3; |
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632 } |
591
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633 cycles(&opts->gen, num_cycles); |
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634 translate_z80_reg(inst, &dst_op, opts); |
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635 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY); |
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636 if (src_op.mode == MODE_REG_DIRECT) { |
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637 sub_rr(code, src_op.base, dst_op.base, z80_size(inst)); |
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638 } else { |
591
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639 sub_ir(code, src_op.disp, dst_op.base, z80_size(inst)); |
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640 } |
591
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641 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
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642 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
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643 setcc_rdisp(code, CC_O, opts->gen.context_reg, zf_off(ZF_PV)); |
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644 //TODO: Implement half-carry flag |
591
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645 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
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646 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
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647 z80_save_reg(inst, opts); |
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648 z80_save_ea(code, inst, opts); |
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649 break; |
248
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650 case Z80_SBC: |
591
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651 num_cycles = 4; |
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652 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
591
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653 num_cycles += 12; |
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654 } else if(inst->addr_mode == Z80_IMMED) { |
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655 num_cycles += 3; |
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656 } else if(z80_size(inst) == SZ_W) { |
591
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657 num_cycles += 4; |
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658 } |
591
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659 cycles(&opts->gen, num_cycles); |
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660 translate_z80_reg(inst, &dst_op, opts); |
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661 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY); |
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662 bt_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B); |
248
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663 if (src_op.mode == MODE_REG_DIRECT) { |
591
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664 sbb_rr(code, src_op.base, dst_op.base, z80_size(inst)); |
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665 } else { |
591
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666 sbb_ir(code, src_op.disp, dst_op.base, z80_size(inst)); |
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667 } |
591
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668 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
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669 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
248
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670 //TODO: Implement half-carry flag |
591
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671 setcc_rdisp(code, CC_O, opts->gen.context_reg, zf_off(ZF_PV)); |
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672 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
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673 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
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674 z80_save_reg(inst, opts); |
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675 z80_save_ea(code, inst, opts); |
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676 break; |
213
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677 case Z80_AND: |
591
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678 num_cycles = 4; |
236
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679 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
591
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680 num_cycles += 12; |
236
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681 } else if(inst->addr_mode == Z80_IMMED) { |
591
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682 num_cycles += 3; |
236
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683 } else if(z80_size(inst) == SZ_W) { |
591
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684 num_cycles += 4; |
236
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685 } |
591
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686 cycles(&opts->gen, num_cycles); |
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687 translate_z80_reg(inst, &dst_op, opts); |
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688 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY); |
236
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689 if (src_op.mode == MODE_REG_DIRECT) { |
591
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690 and_rr(code, src_op.base, dst_op.base, z80_size(inst)); |
236
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691 } else { |
591
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692 and_ir(code, src_op.disp, dst_op.base, z80_size(inst)); |
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693 } |
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694 //TODO: Cleanup flags |
591
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695 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
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696 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
236
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697 //TODO: Implement half-carry flag |
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698 if (z80_size(inst) == SZ_B) { |
591
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699 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV)); |
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700 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
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701 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
236
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702 } |
591
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703 z80_save_reg(inst, opts); |
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704 z80_save_ea(code, inst, opts); |
236
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705 break; |
213
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|
706 case Z80_OR: |
591
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707 num_cycles = 4; |
236
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708 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
591
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709 num_cycles += 12; |
236
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710 } else if(inst->addr_mode == Z80_IMMED) { |
591
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711 num_cycles += 3; |
236
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712 } else if(z80_size(inst) == SZ_W) { |
591
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713 num_cycles += 4; |
236
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714 } |
591
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715 cycles(&opts->gen, num_cycles); |
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716 translate_z80_reg(inst, &dst_op, opts); |
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717 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY); |
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718 if (src_op.mode == MODE_REG_DIRECT) { |
591
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719 or_rr(code, src_op.base, dst_op.base, z80_size(inst)); |
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720 } else { |
591
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721 or_ir(code, src_op.disp, dst_op.base, z80_size(inst)); |
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722 } |
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723 //TODO: Cleanup flags |
591
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|
724 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
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725 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
236
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726 //TODO: Implement half-carry flag |
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727 if (z80_size(inst) == SZ_B) { |
591
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728 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV)); |
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729 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
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diff
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730 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
236
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731 } |
591
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|
732 z80_save_reg(inst, opts); |
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733 z80_save_ea(code, inst, opts); |
236
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734 break; |
213
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|
735 case Z80_XOR: |
591
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|
736 num_cycles = 4; |
236
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737 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
591
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738 num_cycles += 12; |
236
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739 } else if(inst->addr_mode == Z80_IMMED) { |
591
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740 num_cycles += 3; |
236
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741 } else if(z80_size(inst) == SZ_W) { |
591
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742 num_cycles += 4; |
236
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|
743 } |
591
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744 cycles(&opts->gen, num_cycles); |
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diff
changeset
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745 translate_z80_reg(inst, &dst_op, opts); |
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746 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY); |
236
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747 if (src_op.mode == MODE_REG_DIRECT) { |
591
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748 xor_rr(code, src_op.base, dst_op.base, z80_size(inst)); |
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749 } else { |
591
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750 xor_ir(code, src_op.disp, dst_op.base, z80_size(inst)); |
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751 } |
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752 //TODO: Cleanup flags |
591
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|
753 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
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754 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
236
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755 //TODO: Implement half-carry flag |
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756 if (z80_size(inst) == SZ_B) { |
591
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|
757 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV)); |
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758 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
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759 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
236
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760 } |
591
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|
761 z80_save_reg(inst, opts); |
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762 z80_save_ea(code, inst, opts); |
236
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763 break; |
242 | 764 case Z80_CP: |
591
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diff
changeset
|
765 num_cycles = 4; |
242 | 766 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
591
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767 num_cycles += 12; |
242 | 768 } else if(inst->addr_mode == Z80_IMMED) { |
591
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|
769 num_cycles += 3; |
242 | 770 } |
591
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diff
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771 cycles(&opts->gen, num_cycles); |
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|
772 translate_z80_reg(inst, &dst_op, opts); |
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Get Z80 core back into compileable state
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|
773 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY); |
242 | 774 if (src_op.mode == MODE_REG_DIRECT) { |
591
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775 cmp_rr(code, src_op.base, dst_op.base, z80_size(inst)); |
242 | 776 } else { |
591
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777 cmp_ir(code, src_op.disp, dst_op.base, z80_size(inst)); |
242 | 778 } |
591
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779 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
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780 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
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781 setcc_rdisp(code, CC_O, opts->gen.context_reg, zf_off(ZF_PV)); |
242 | 782 //TODO: Implement half-carry flag |
591
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783 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
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784 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
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785 z80_save_reg(inst, opts); |
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|
786 z80_save_ea(code, inst, opts); |
242 | 787 break; |
213
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788 case Z80_INC: |
591
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789 num_cycles = 4; |
213
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|
790 if (inst->reg == Z80_IX || inst->reg == Z80_IY) { |
591
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791 num_cycles += 6; |
213
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|
792 } else if(z80_size(inst) == SZ_W) { |
591
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|
793 num_cycles += 2; |
213
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794 } else if(inst->reg == Z80_IXH || inst->reg == Z80_IXL || inst->reg == Z80_IYH || inst->reg == Z80_IYL || inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
591
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|
795 num_cycles += 4; |
213
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|
796 } |
591
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|
797 cycles(&opts->gen, num_cycles); |
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|
798 translate_z80_reg(inst, &dst_op, opts); |
213
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diff
changeset
|
799 if (dst_op.mode == MODE_UNUSED) { |
591
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800 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY); |
213
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|
801 } |
591
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diff
changeset
|
802 add_ir(code, 1, dst_op.base, z80_size(inst)); |
213
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changeset
|
803 if (z80_size(inst) == SZ_B) { |
591
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changeset
|
804 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
213
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diff
changeset
|
805 //TODO: Implement half-carry flag |
591
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diff
changeset
|
806 setcc_rdisp(code, CC_O, opts->gen.context_reg, zf_off(ZF_PV)); |
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|
807 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
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|
808 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
213
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|
809 } |
591
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diff
changeset
|
810 z80_save_reg(inst, opts); |
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|
811 z80_save_ea(code, inst, opts); |
593
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diff
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|
812 z80_save_result(opts, inst); |
213
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|
813 break; |
236
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814 case Z80_DEC: |
591
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|
815 num_cycles = 4; |
236
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816 if (inst->reg == Z80_IX || inst->reg == Z80_IY) { |
591
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|
817 num_cycles += 6; |
236
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818 } else if(z80_size(inst) == SZ_W) { |
591
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|
819 num_cycles += 2; |
236
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820 } else if(inst->reg == Z80_IXH || inst->reg == Z80_IXL || inst->reg == Z80_IYH || inst->reg == Z80_IYL || inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
591
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|
821 num_cycles += 4; |
236
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822 } |
591
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changeset
|
823 cycles(&opts->gen, num_cycles); |
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|
824 translate_z80_reg(inst, &dst_op, opts); |
236
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|
825 if (dst_op.mode == MODE_UNUSED) { |
591
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changeset
|
826 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY); |
236
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|
827 } |
591
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changeset
|
828 sub_ir(code, 1, dst_op.base, z80_size(inst)); |
236
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|
829 if (z80_size(inst) == SZ_B) { |
591
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changeset
|
830 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
236
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|
831 //TODO: Implement half-carry flag |
591
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diff
changeset
|
832 setcc_rdisp(code, CC_O, opts->gen.context_reg, zf_off(ZF_PV)); |
966b46c68942
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diff
changeset
|
833 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
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diff
changeset
|
834 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
236
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|
835 } |
591
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diff
changeset
|
836 z80_save_reg(inst, opts); |
966b46c68942
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diff
changeset
|
837 z80_save_ea(code, inst, opts); |
593
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diff
changeset
|
838 z80_save_result(opts, inst); |
213
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|
839 break; |
274
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840 //case Z80_DAA: |
213
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diff
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|
841 case Z80_CPL: |
591
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842 cycles(&opts->gen, 4); |
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|
843 not_r(code, opts->regs[Z80_A], SZ_B); |
274
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844 //TODO: Implement half-carry flag |
591
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|
845 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
274
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846 break; |
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|
847 case Z80_NEG: |
591
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|
848 cycles(&opts->gen, 8); |
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|
849 neg_r(code, opts->regs[Z80_A], SZ_B); |
274
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850 //TODO: Implement half-carry flag |
591
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diff
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851 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
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852 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
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|
853 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
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diff
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|
854 setcc_rdisp(code, CC_O, opts->gen.context_reg, zf_off(ZF_PV)); |
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|
855 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
274
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856 break; |
213
4d4559b04c59
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diff
changeset
|
857 case Z80_CCF: |
591
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|
858 cycles(&opts->gen, 4); |
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|
859 xor_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_C), SZ_B); |
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|
860 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
257 | 861 //TODO: Implement half-carry flag |
862 break; | |
863 case Z80_SCF: | |
591
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864 cycles(&opts->gen, 4); |
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|
865 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_C), SZ_B); |
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changeset
|
866 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
257 | 867 //TODO: Implement half-carry flag |
868 break; | |
213
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Mike Pavone <pavone@retrodev.com>
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diff
changeset
|
869 case Z80_NOP: |
4d4559b04c59
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Mike Pavone <pavone@retrodev.com>
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|
870 if (inst->immed == 42) { |
593
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diff
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|
871 call(code, opts->gen.save_context); |
657
92ce5ea5ffc9
Use call_args and call_args_abi in Z80 core
Michael Pavone <pavone@retrodev.com>
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653
diff
changeset
|
872 call_args(code, (code_ptr)z80_print_regs_exit, 1, opts->gen.context_reg); |
213
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diff
changeset
|
873 } else { |
591
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|
874 cycles(&opts->gen, 4 * inst->immed); |
213
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diff
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|
875 } |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
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diff
changeset
|
876 break; |
593
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diff
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|
877 case Z80_HALT: { |
591
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diff
changeset
|
878 cycles(&opts->gen, 4); |
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diff
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|
879 mov_ir(code, address, opts->gen.scratch1, SZ_W); |
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diff
changeset
|
880 uint8_t * call_inst = code->cur; |
593
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diff
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|
881 mov_rr(code, opts->gen.limit, opts->gen.scratch2, SZ_D); |
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diff
changeset
|
882 sub_rr(code, opts->gen.cycles, opts->gen.scratch2, SZ_D); |
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diff
changeset
|
883 and_ir(code, 0xFFFFFFFC, opts->gen.scratch2, SZ_D); |
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diff
changeset
|
884 add_rr(code, opts->gen.scratch2, opts->gen.cycles, SZ_D); |
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diff
changeset
|
885 cmp_rr(code, opts->gen.limit, opts->gen.cycles, SZ_D); |
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592
diff
changeset
|
886 code_ptr skip_last = code->cur+1; |
594
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
887 jcc(code, CC_NB, code->cur+2); |
593
5ef3fe516da9
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diff
changeset
|
888 cycles(&opts->gen, 4); |
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diff
changeset
|
889 *skip_last = code->cur - (skip_last+1); |
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diff
changeset
|
890 call(code, opts->gen.handle_cycle_limit_int); |
591
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590
diff
changeset
|
891 jmp(code, call_inst); |
285
021aeb6df19b
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284
diff
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|
892 break; |
593
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diff
changeset
|
893 } |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff
changeset
|
894 case Z80_DI: |
591
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diff
changeset
|
895 cycles(&opts->gen, 4); |
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Get Z80 core back into compileable state
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diff
changeset
|
896 mov_irdisp(code, 0, opts->gen.context_reg, offsetof(z80_context, iff1), SZ_B); |
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Get Z80 core back into compileable state
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diff
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|
897 mov_irdisp(code, 0, opts->gen.context_reg, offsetof(z80_context, iff2), SZ_B); |
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Get Z80 core back into compileable state
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diff
changeset
|
898 mov_rdispr(code, opts->gen.context_reg, offsetof(z80_context, sync_cycle), opts->gen.limit, SZ_D); |
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Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
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590
diff
changeset
|
899 mov_irdisp(code, 0xFFFFFFFF, opts->gen.context_reg, offsetof(z80_context, int_cycle), SZ_D); |
243
2f069a0b487e
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242
diff
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|
900 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
901 case Z80_EI: |
591
966b46c68942
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diff
changeset
|
902 cycles(&opts->gen, 4); |
966b46c68942
Get Z80 core back into compileable state
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590
diff
changeset
|
903 mov_rrdisp(code, opts->gen.cycles, opts->gen.context_reg, offsetof(z80_context, int_enable_cycle), SZ_D); |
966b46c68942
Get Z80 core back into compileable state
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590
diff
changeset
|
904 mov_irdisp(code, 1, opts->gen.context_reg, offsetof(z80_context, iff1), SZ_B); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
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590
diff
changeset
|
905 mov_irdisp(code, 1, opts->gen.context_reg, offsetof(z80_context, iff2), SZ_B); |
335 | 906 //interrupt enable has a one-instruction latency, minimum instruction duration is 4 cycles |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
907 add_irdisp(code, 4, opts->gen.context_reg, offsetof(z80_context, int_enable_cycle), SZ_D); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
908 call(code, opts->do_sync); |
243
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
909 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
910 case Z80_IM: |
591
966b46c68942
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590
diff
changeset
|
911 cycles(&opts->gen, 4); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
912 mov_irdisp(code, inst->immed, opts->gen.context_reg, offsetof(z80_context, im), SZ_B); |
243
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
913 break; |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
914 case Z80_RLC: |
591
966b46c68942
Get Z80 core back into compileable state
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590
diff
changeset
|
915 num_cycles = inst->immed == 0 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
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590
diff
changeset
|
916 cycles(&opts->gen, num_cycles); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
917 if (inst->addr_mode != Z80_UNUSED) { |
591
966b46c68942
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Michael Pavone <pavone@retrodev.com>
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590
diff
changeset
|
918 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
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590
diff
changeset
|
919 translate_z80_reg(inst, &src_op, opts); //For IX/IY variants that also write to a register |
966b46c68942
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Michael Pavone <pavone@retrodev.com>
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590
diff
changeset
|
920 cycles(&opts->gen, 1); |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
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246
diff
changeset
|
921 } else { |
302
3b831fe32c15
More fixes for confusion between Z80_UNUSED and MODE_UNUSED
Mike Pavone <pavone@retrodev.com>
parents:
301
diff
changeset
|
922 src_op.mode = MODE_UNUSED; |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
923 translate_z80_reg(inst, &dst_op, opts); |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
924 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
925 rol_ir(code, 1, dst_op.base, SZ_B); |
301
6e15509a1257
Compare src_op.mode with the correct constant in shift/rotate instructions
Mike Pavone <pavone@retrodev.com>
parents:
300
diff
changeset
|
926 if (src_op.mode != MODE_UNUSED) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
927 mov_rr(code, dst_op.base, src_op.base, SZ_B); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
928 } |
591
966b46c68942
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Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
929 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
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590
diff
changeset
|
930 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
247
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
931 //TODO: Implement half-carry flag |
651
103d5cabbe14
Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents:
644
diff
changeset
|
932 if (inst->immed) { |
103d5cabbe14
Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents:
644
diff
changeset
|
933 //rlca does not set these flags |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
934 cmp_ir(code, 0, dst_op.base, SZ_B); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
935 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
936 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
937 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
651
103d5cabbe14
Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents:
644
diff
changeset
|
938 } |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
939 if (inst->addr_mode != Z80_UNUSED) { |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
940 z80_save_result(opts, inst); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
941 if (src_op.mode != MODE_UNUSED) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
942 z80_save_reg(inst, opts); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
943 } |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
944 } else { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
945 z80_save_reg(inst, opts); |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
946 } |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
947 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
948 case Z80_RL: |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
949 num_cycles = inst->immed == 0 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
950 cycles(&opts->gen, num_cycles); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
951 if (inst->addr_mode != Z80_UNUSED) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
952 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
953 translate_z80_reg(inst, &src_op, opts); //For IX/IY variants that also write to a register |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
954 cycles(&opts->gen, 1); |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
955 } else { |
302
3b831fe32c15
More fixes for confusion between Z80_UNUSED and MODE_UNUSED
Mike Pavone <pavone@retrodev.com>
parents:
301
diff
changeset
|
956 src_op.mode = MODE_UNUSED; |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
957 translate_z80_reg(inst, &dst_op, opts); |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
958 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
959 bt_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
960 rcl_ir(code, 1, dst_op.base, SZ_B); |
301
6e15509a1257
Compare src_op.mode with the correct constant in shift/rotate instructions
Mike Pavone <pavone@retrodev.com>
parents:
300
diff
changeset
|
961 if (src_op.mode != MODE_UNUSED) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
962 mov_rr(code, dst_op.base, src_op.base, SZ_B); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
963 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
964 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
965 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
966 //TODO: Implement half-carry flag |
651
103d5cabbe14
Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents:
644
diff
changeset
|
967 if (inst->immed) { |
103d5cabbe14
Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents:
644
diff
changeset
|
968 //rla does not set these flags |
591
966b46c68942
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Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
969 cmp_ir(code, 0, dst_op.base, SZ_B); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
970 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV)); |
966b46c68942
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Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
971 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
972 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
651
103d5cabbe14
Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents:
644
diff
changeset
|
973 } |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
974 if (inst->addr_mode != Z80_UNUSED) { |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
975 z80_save_result(opts, inst); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
976 if (src_op.mode != MODE_UNUSED) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
977 z80_save_reg(inst, opts); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
978 } |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
979 } else { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
980 z80_save_reg(inst, opts); |
247
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
981 } |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
982 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
983 case Z80_RRC: |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
984 num_cycles = inst->immed == 0 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
985 cycles(&opts->gen, num_cycles); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
986 if (inst->addr_mode != Z80_UNUSED) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
987 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
988 translate_z80_reg(inst, &src_op, opts); //For IX/IY variants that also write to a register |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
989 cycles(&opts->gen, 1); |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
990 } else { |
302
3b831fe32c15
More fixes for confusion between Z80_UNUSED and MODE_UNUSED
Mike Pavone <pavone@retrodev.com>
parents:
301
diff
changeset
|
991 src_op.mode = MODE_UNUSED; |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
992 translate_z80_reg(inst, &dst_op, opts); |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
993 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
994 ror_ir(code, 1, dst_op.base, SZ_B); |
301
6e15509a1257
Compare src_op.mode with the correct constant in shift/rotate instructions
Mike Pavone <pavone@retrodev.com>
parents:
300
diff
changeset
|
995 if (src_op.mode != MODE_UNUSED) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
996 mov_rr(code, dst_op.base, src_op.base, SZ_B); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
997 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
998 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
999 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1000 //TODO: Implement half-carry flag |
651
103d5cabbe14
Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents:
644
diff
changeset
|
1001 if (inst->immed) { |
103d5cabbe14
Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents:
644
diff
changeset
|
1002 //rrca does not set these flags |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1003 cmp_ir(code, 0, dst_op.base, SZ_B); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1004 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV)); |
966b46c68942
Get Z80 core back into compileable state
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parents:
590
diff
changeset
|
1005 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1006 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
651
103d5cabbe14
Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents:
644
diff
changeset
|
1007 } |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1008 if (inst->addr_mode != Z80_UNUSED) { |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
1009 z80_save_result(opts, inst); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1010 if (src_op.mode != MODE_UNUSED) { |
591
966b46c68942
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parents:
590
diff
changeset
|
1011 z80_save_reg(inst, opts); |
299
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Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1012 } |
247
682e505f5757
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246
diff
changeset
|
1013 } else { |
591
966b46c68942
Get Z80 core back into compileable state
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parents:
590
diff
changeset
|
1014 z80_save_reg(inst, opts); |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
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parents:
246
diff
changeset
|
1015 } |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1016 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1017 case Z80_RR: |
591
966b46c68942
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parents:
590
diff
changeset
|
1018 num_cycles = inst->immed == 0 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1019 cycles(&opts->gen, num_cycles); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1020 if (inst->addr_mode != Z80_UNUSED) { |
591
966b46c68942
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parents:
590
diff
changeset
|
1021 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1022 translate_z80_reg(inst, &src_op, opts); //For IX/IY variants that also write to a register |
966b46c68942
Get Z80 core back into compileable state
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parents:
590
diff
changeset
|
1023 cycles(&opts->gen, 1); |
247
682e505f5757
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246
diff
changeset
|
1024 } else { |
302
3b831fe32c15
More fixes for confusion between Z80_UNUSED and MODE_UNUSED
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301
diff
changeset
|
1025 src_op.mode = MODE_UNUSED; |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1026 translate_z80_reg(inst, &dst_op, opts); |
247
682e505f5757
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246
diff
changeset
|
1027 } |
591
966b46c68942
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Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1028 bt_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B); |
966b46c68942
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590
diff
changeset
|
1029 rcr_ir(code, 1, dst_op.base, SZ_B); |
301
6e15509a1257
Compare src_op.mode with the correct constant in shift/rotate instructions
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300
diff
changeset
|
1030 if (src_op.mode != MODE_UNUSED) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1031 mov_rr(code, dst_op.base, src_op.base, SZ_B); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
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295
diff
changeset
|
1032 } |
591
966b46c68942
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Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1033 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1034 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
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246
diff
changeset
|
1035 //TODO: Implement half-carry flag |
651
103d5cabbe14
Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents:
644
diff
changeset
|
1036 if (inst->immed) { |
103d5cabbe14
Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents:
644
diff
changeset
|
1037 //rra does not set these flags |
591
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1038 cmp_ir(code, 0, dst_op.base, SZ_B); |
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1039 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV)); |
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|
1040 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
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diff
changeset
|
1041 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
651
103d5cabbe14
Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents:
644
diff
changeset
|
1042 } |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
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295
diff
changeset
|
1043 if (inst->addr_mode != Z80_UNUSED) { |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
1044 z80_save_result(opts, inst); |
299
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Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
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295
diff
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|
1045 if (src_op.mode != MODE_UNUSED) { |
591
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diff
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|
1046 z80_save_reg(inst, opts); |
299
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|
1047 } |
247
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Implement rotation and bit set/reset instructions (untested).
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246
diff
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|
1048 } else { |
591
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|
1049 z80_save_reg(inst, opts); |
247
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|
1050 } |
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1051 break; |
275
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|
1052 case Z80_SLA: |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1053 case Z80_SLL: |
591
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|
1054 num_cycles = inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8; |
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|
1055 cycles(&opts->gen, num_cycles); |
299
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295
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1056 if (inst->addr_mode != Z80_UNUSED) { |
591
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diff
changeset
|
1057 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY); |
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|
1058 translate_z80_reg(inst, &src_op, opts); //For IX/IY variants that also write to a register |
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diff
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|
1059 cycles(&opts->gen, 1); |
275
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1060 } else { |
302
3b831fe32c15
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301
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|
1061 src_op.mode = MODE_UNUSED; |
591
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|
1062 translate_z80_reg(inst, &dst_op, opts); |
275
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1063 } |
591
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|
1064 shl_ir(code, 1, dst_op.base, SZ_B); |
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changeset
|
1065 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
310
bf440db64086
Implement carry flag for shift instructions. Implement weird behavior for bit 0 of SLL. Fix missing break statement in SRL.
Mike Pavone <pavone@retrodev.com>
parents:
309
diff
changeset
|
1066 if (inst->op == Z80_SLL) { |
591
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|
1067 or_ir(code, 1, dst_op.base, SZ_B); |
310
bf440db64086
Implement carry flag for shift instructions. Implement weird behavior for bit 0 of SLL. Fix missing break statement in SRL.
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309
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1068 } |
301
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|
1069 if (src_op.mode != MODE_UNUSED) { |
591
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|
1070 mov_rr(code, dst_op.base, src_op.base, SZ_B); |
299
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1071 } |
591
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|
1072 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
275
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1073 //TODO: Implement half-carry flag |
591
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|
1074 cmp_ir(code, 0, dst_op.base, SZ_B); |
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|
1075 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV)); |
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|
1076 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
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|
1077 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
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295
diff
changeset
|
1078 if (inst->addr_mode != Z80_UNUSED) { |
593
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parents:
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diff
changeset
|
1079 z80_save_result(opts, inst); |
299
42e1a986f2d0
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295
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|
1080 if (src_op.mode != MODE_UNUSED) { |
591
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changeset
|
1081 z80_save_reg(inst, opts); |
299
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295
diff
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|
1082 } |
275
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|
1083 } else { |
591
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changeset
|
1084 z80_save_reg(inst, opts); |
275
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1085 } |
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changeset
|
1086 break; |
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|
1087 case Z80_SRA: |
591
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|
1088 num_cycles = inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8; |
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changeset
|
1089 cycles(&opts->gen, num_cycles); |
299
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Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
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295
diff
changeset
|
1090 if (inst->addr_mode != Z80_UNUSED) { |
591
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changeset
|
1091 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY); |
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diff
changeset
|
1092 translate_z80_reg(inst, &src_op, opts); //For IX/IY variants that also write to a register |
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diff
changeset
|
1093 cycles(&opts->gen, 1); |
275
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274
diff
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|
1094 } else { |
302
3b831fe32c15
More fixes for confusion between Z80_UNUSED and MODE_UNUSED
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301
diff
changeset
|
1095 src_op.mode = MODE_UNUSED; |
591
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diff
changeset
|
1096 translate_z80_reg(inst, &dst_op, opts); |
275
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274
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|
1097 } |
591
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diff
changeset
|
1098 sar_ir(code, 1, dst_op.base, SZ_B); |
301
6e15509a1257
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300
diff
changeset
|
1099 if (src_op.mode != MODE_UNUSED) { |
591
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diff
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|
1100 mov_rr(code, dst_op.base, src_op.base, SZ_B); |
299
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295
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|
1101 } |
591
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changeset
|
1102 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
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diff
changeset
|
1103 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
275
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changeset
|
1104 //TODO: Implement half-carry flag |
591
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diff
changeset
|
1105 cmp_ir(code, 0, dst_op.base, SZ_B); |
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diff
changeset
|
1106 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV)); |
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diff
changeset
|
1107 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
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diff
changeset
|
1108 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
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295
diff
changeset
|
1109 if (inst->addr_mode != Z80_UNUSED) { |
593
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diff
changeset
|
1110 z80_save_result(opts, inst); |
299
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295
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changeset
|
1111 if (src_op.mode != MODE_UNUSED) { |
591
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diff
changeset
|
1112 z80_save_reg(inst, opts); |
299
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|
1113 } |
275
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|
1114 } else { |
591
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diff
changeset
|
1115 z80_save_reg(inst, opts); |
275
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1116 } |
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|
1117 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1118 case Z80_SRL: |
591
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diff
changeset
|
1119 num_cycles = inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8; |
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changeset
|
1120 cycles(&opts->gen, num_cycles); |
299
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295
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changeset
|
1121 if (inst->addr_mode != Z80_UNUSED) { |
591
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diff
changeset
|
1122 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY); |
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diff
changeset
|
1123 translate_z80_reg(inst, &src_op, opts); //For IX/IY variants that also write to a register |
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diff
changeset
|
1124 cycles(&opts->gen, 1); |
275
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|
1125 } else { |
302
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|
1126 src_op.mode = MODE_UNUSED; |
591
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diff
changeset
|
1127 translate_z80_reg(inst, &dst_op, opts); |
275
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|
1128 } |
591
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diff
changeset
|
1129 shr_ir(code, 1, dst_op.base, SZ_B); |
301
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|
1130 if (src_op.mode != MODE_UNUSED) { |
591
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changeset
|
1131 mov_rr(code, dst_op.base, src_op.base, SZ_B); |
299
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|
1132 } |
591
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changeset
|
1133 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
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changeset
|
1134 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
275
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changeset
|
1135 //TODO: Implement half-carry flag |
591
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diff
changeset
|
1136 cmp_ir(code, 0, dst_op.base, SZ_B); |
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diff
changeset
|
1137 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV)); |
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1138 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
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1139 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
299
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1140 if (inst->addr_mode != Z80_UNUSED) { |
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1141 z80_save_result(opts, inst); |
299
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1142 if (src_op.mode != MODE_UNUSED) { |
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1143 z80_save_reg(inst, opts); |
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1144 } |
275
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1145 } else { |
591
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1146 z80_save_reg(inst, opts); |
275
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1147 } |
310
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Implement carry flag for shift instructions. Implement weird behavior for bit 0 of SLL. Fix missing break statement in SRL.
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1148 break; |
286 | 1149 case Z80_RLD: |
591
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1150 cycles(&opts->gen, 8); |
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1151 mov_rr(code, opts->regs[Z80_HL], opts->gen.scratch1, SZ_W); |
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1152 call(code, opts->read_8); |
286 | 1153 //Before: (HL) = 0x12, A = 0x34 |
1154 //After: (HL) = 0x24, A = 0x31 | |
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1155 mov_rr(code, opts->regs[Z80_A], opts->gen.scratch2, SZ_B); |
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1156 shl_ir(code, 4, opts->gen.scratch1, SZ_W); |
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1157 and_ir(code, 0xF, opts->gen.scratch2, SZ_W); |
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1158 and_ir(code, 0xFFF, opts->gen.scratch1, SZ_W); |
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1159 and_ir(code, 0xF0, opts->regs[Z80_A], SZ_B); |
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1160 or_rr(code, opts->gen.scratch2, opts->gen.scratch1, SZ_W); |
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1161 //opts->gen.scratch1 = 0x0124 |
591
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1162 ror_ir(code, 8, opts->gen.scratch1, SZ_W); |
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1163 cycles(&opts->gen, 4); |
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1164 or_rr(code, opts->gen.scratch1, opts->regs[Z80_A], SZ_B); |
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1165 //set flags |
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1166 //TODO: Implement half-carry flag |
591
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1167 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
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1168 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV)); |
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1169 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
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1170 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
505
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1171 |
591
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1172 mov_rr(code, opts->regs[Z80_HL], opts->gen.scratch2, SZ_W); |
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1173 ror_ir(code, 8, opts->gen.scratch1, SZ_W); |
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1174 call(code, opts->write_8); |
286 | 1175 break; |
287
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1176 case Z80_RRD: |
591
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1177 cycles(&opts->gen, 8); |
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1178 mov_rr(code, opts->regs[Z80_HL], opts->gen.scratch1, SZ_W); |
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1179 call(code, opts->read_8); |
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1180 //Before: (HL) = 0x12, A = 0x34 |
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1181 //After: (HL) = 0x41, A = 0x32 |
591
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1182 movzx_rr(code, opts->regs[Z80_A], opts->gen.scratch2, SZ_B, SZ_W); |
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1183 ror_ir(code, 4, opts->gen.scratch1, SZ_W); |
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1184 shl_ir(code, 4, opts->gen.scratch2, SZ_W); |
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1185 and_ir(code, 0xF00F, opts->gen.scratch1, SZ_W); |
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1186 and_ir(code, 0xF0, opts->regs[Z80_A], SZ_B); |
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1187 //opts->gen.scratch1 = 0x2001 |
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1188 //opts->gen.scratch2 = 0x0040 |
591
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1189 or_rr(code, opts->gen.scratch2, opts->gen.scratch1, SZ_W); |
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1190 //opts->gen.scratch1 = 0x2041 |
591
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1191 ror_ir(code, 8, opts->gen.scratch1, SZ_W); |
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1192 cycles(&opts->gen, 4); |
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1193 shr_ir(code, 4, opts->gen.scratch1, SZ_B); |
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1194 or_rr(code, opts->gen.scratch1, opts->regs[Z80_A], SZ_B); |
287
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1195 //set flags |
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1196 //TODO: Implement half-carry flag |
591
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1197 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
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1198 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV)); |
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1199 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
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1200 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
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1201 |
591
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1202 mov_rr(code, opts->regs[Z80_HL], opts->gen.scratch2, SZ_W); |
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1203 ror_ir(code, 8, opts->gen.scratch1, SZ_W); |
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1204 call(code, opts->write_8); |
287
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1205 break; |
308
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1206 case Z80_BIT: { |
591
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1207 num_cycles = (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) ? 8 : 16; |
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1208 cycles(&opts->gen, num_cycles); |
308
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1209 uint8_t bit; |
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1210 if ((inst->addr_mode & 0x1F) == Z80_REG && opts->regs[inst->ea_reg] >= AH && opts->regs[inst->ea_reg] <= BH) { |
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1211 src_op.base = opts->regs[z80_word_reg(inst->ea_reg)]; |
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1212 size = SZ_W; |
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1213 bit = inst->immed + 8; |
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1214 } else { |
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1215 size = SZ_B; |
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1216 bit = inst->immed; |
591
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1217 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY); |
308
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1218 } |
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1219 if (inst->addr_mode != Z80_REG) { |
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1220 //Reads normally take 3 cycles, but the read at the end of a bit instruction takes 4 |
591
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1221 cycles(&opts->gen, 1); |
239
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1222 } |
591
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1223 bt_ir(code, bit, src_op.base, size); |
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1224 setcc_rdisp(code, CC_NC, opts->gen.context_reg, zf_off(ZF_Z)); |
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1225 setcc_rdisp(code, CC_NC, opts->gen.context_reg, zf_off(ZF_PV)); |
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1226 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
307
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1227 if (inst->immed == 7) { |
591
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1228 cmp_ir(code, 0, src_op.base, size); |
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1229 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
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1230 } else { |
591
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1231 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_S), SZ_B); |
307
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1232 } |
239
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1233 break; |
308
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1234 } |
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1235 case Z80_SET: { |
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1236 num_cycles = (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) ? 8 : 16; |
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1237 cycles(&opts->gen, num_cycles); |
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1238 uint8_t bit; |
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1239 if ((inst->addr_mode & 0x1F) == Z80_REG && opts->regs[inst->ea_reg] >= AH && opts->regs[inst->ea_reg] <= BH) { |
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1240 src_op.base = opts->regs[z80_word_reg(inst->ea_reg)]; |
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1241 size = SZ_W; |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1242 bit = inst->immed + 8; |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1243 } else { |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1244 size = SZ_B; |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1245 bit = inst->immed; |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1246 translate_z80_ea(inst, &src_op, opts, READ, MODIFY); |
308
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1247 } |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1248 if (inst->reg != Z80_USE_IMMED) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1249 translate_z80_reg(inst, &dst_op, opts); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1250 } |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1251 if (inst->addr_mode != Z80_REG) { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1252 //Reads normally take 3 cycles, but the read in the middle of a set instruction takes 4 |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1253 cycles(&opts->gen, 1); |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1254 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1255 bts_ir(code, bit, src_op.base, size); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1256 if (inst->reg != Z80_USE_IMMED) { |
308
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1257 if (size == SZ_W) { |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1258 if (dst_op.base >= R8) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1259 ror_ir(code, 8, src_op.base, SZ_W); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1260 mov_rr(code, opts->regs[z80_low_reg(inst->ea_reg)], dst_op.base, SZ_B); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1261 ror_ir(code, 8, src_op.base, SZ_W); |
308
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1262 } else { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1263 mov_rr(code, opts->regs[inst->ea_reg], dst_op.base, SZ_B); |
505
b7b7a1cab44a
The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1264 } |
308
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1265 } else { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1266 mov_rr(code, src_op.base, dst_op.base, SZ_B); |
308
e0e81551fd7e
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1267 } |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1268 } |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1269 if ((inst->addr_mode & 0x1F) != Z80_REG) { |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
1270 z80_save_result(opts, inst); |
308
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1271 if (inst->reg != Z80_USE_IMMED) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1272 z80_save_reg(inst, opts); |
308
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Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1273 } |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1274 } |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1275 break; |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1276 } |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1277 case Z80_RES: { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1278 num_cycles = (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) ? 8 : 16; |
966b46c68942
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Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1279 cycles(&opts->gen, num_cycles); |
308
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Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1280 uint8_t bit; |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1281 if ((inst->addr_mode & 0x1F) == Z80_REG && opts->regs[inst->ea_reg] >= AH && opts->regs[inst->ea_reg] <= BH) { |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1282 src_op.base = opts->regs[z80_word_reg(inst->ea_reg)]; |
e0e81551fd7e
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1283 size = SZ_W; |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1284 bit = inst->immed + 8; |
e0e81551fd7e
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1285 } else { |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1286 size = SZ_B; |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1287 bit = inst->immed; |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1288 translate_z80_ea(inst, &src_op, opts, READ, MODIFY); |
308
e0e81551fd7e
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1289 } |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1290 if (inst->reg != Z80_USE_IMMED) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1291 translate_z80_reg(inst, &dst_op, opts); |
308
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parents:
307
diff
changeset
|
1292 } |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
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parents:
307
diff
changeset
|
1293 if (inst->addr_mode != Z80_REG) { |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1294 //Reads normally take 3 cycles, but the read in the middle of a set instruction takes 4 |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1295 cycles(&opts->gen, 1); |
308
e0e81551fd7e
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1296 } |
591
966b46c68942
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Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1297 btr_ir(code, bit, src_op.base, size); |
308
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1298 if (inst->reg != Z80_USE_IMMED) { |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1299 if (size == SZ_W) { |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1300 if (dst_op.base >= R8) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1301 ror_ir(code, 8, src_op.base, SZ_W); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1302 mov_rr(code, opts->regs[z80_low_reg(inst->ea_reg)], dst_op.base, SZ_B); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1303 ror_ir(code, 8, src_op.base, SZ_W); |
308
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Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1304 } else { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1305 mov_rr(code, opts->regs[inst->ea_reg], dst_op.base, SZ_B); |
505
b7b7a1cab44a
The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1306 } |
308
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Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1307 } else { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1308 mov_rr(code, src_op.base, dst_op.base, SZ_B); |
308
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
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parents:
307
diff
changeset
|
1309 } |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1310 } |
247
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parents:
246
diff
changeset
|
1311 if (inst->addr_mode != Z80_REG) { |
593
5ef3fe516da9
Z80 core is sort of working again
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parents:
592
diff
changeset
|
1312 z80_save_result(opts, inst); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1313 if (inst->reg != Z80_USE_IMMED) { |
591
966b46c68942
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Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1314 z80_save_reg(inst, opts); |
299
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Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1315 } |
247
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parents:
246
diff
changeset
|
1316 } |
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246
diff
changeset
|
1317 break; |
308
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307
diff
changeset
|
1318 } |
236
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diff
changeset
|
1319 case Z80_JP: { |
591
966b46c68942
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parents:
590
diff
changeset
|
1320 num_cycles = 4; |
506
a3b48a57e847
Fix timing of certain ld and jp instructions in the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
505
diff
changeset
|
1321 if (inst->addr_mode != Z80_REG_INDIRECT) { |
591
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parents:
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diff
changeset
|
1322 num_cycles += 6; |
236
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diff
changeset
|
1323 } else if(inst->ea_reg == Z80_IX || inst->ea_reg == Z80_IY) { |
591
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parents:
590
diff
changeset
|
1324 num_cycles += 4; |
236
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235
diff
changeset
|
1325 } |
591
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parents:
590
diff
changeset
|
1326 cycles(&opts->gen, num_cycles); |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1327 if (inst->addr_mode != Z80_REG_INDIRECT) { |
591
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parents:
590
diff
changeset
|
1328 code_ptr call_dst = z80_get_native_address(context, inst->immed); |
236
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diff
changeset
|
1329 if (!call_dst) { |
591
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parents:
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diff
changeset
|
1330 opts->gen.deferred = defer_address(opts->gen.deferred, inst->immed, code->cur + 1); |
236
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diff
changeset
|
1331 //fake address to force large displacement |
601
f0061e3d2ad9
Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor
Michael Pavone <pavone@retrodev.com>
parents:
598
diff
changeset
|
1332 call_dst = code->cur + 256; |
236
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diff
changeset
|
1333 } |
591
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parents:
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diff
changeset
|
1334 jmp(code, call_dst); |
236
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235
diff
changeset
|
1335 } else { |
239
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
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parents:
238
diff
changeset
|
1336 if (inst->addr_mode == Z80_REG_INDIRECT) { |
591
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parents:
590
diff
changeset
|
1337 mov_rr(code, opts->regs[inst->ea_reg], opts->gen.scratch1, SZ_W); |
236
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parents:
235
diff
changeset
|
1338 } else { |
591
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Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
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diff
changeset
|
1339 mov_ir(code, inst->immed, opts->gen.scratch1, SZ_W); |
236
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diff
changeset
|
1340 } |
593
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parents:
592
diff
changeset
|
1341 call(code, opts->native_addr); |
591
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Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1342 jmp_r(code, opts->gen.scratch1); |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1343 } |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1344 break; |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1345 } |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1346 case Z80_JPCC: { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1347 cycles(&opts->gen, 7);//T States: 4,3 |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1348 uint8_t cond = CC_Z; |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1349 switch (inst->reg) |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1350 { |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1351 case Z80_CC_NZ: |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1352 cond = CC_NZ; |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1353 case Z80_CC_Z: |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1354 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_Z), SZ_B); |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1355 break; |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1356 case Z80_CC_NC: |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1357 cond = CC_NZ; |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1358 case Z80_CC_C: |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1359 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B); |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1360 break; |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1361 case Z80_CC_PO: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1362 cond = CC_NZ; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1363 case Z80_CC_PE: |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1364 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_PV), SZ_B); |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1365 break; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1366 case Z80_CC_P: |
367
f20562f2a570
Fix P condition in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
366
diff
changeset
|
1367 cond = CC_NZ; |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1368 case Z80_CC_M: |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1369 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_S), SZ_B); |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1370 break; |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1371 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1372 uint8_t *no_jump_off = code->cur+1; |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1373 jcc(code, cond, code->cur+2); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1374 cycles(&opts->gen, 5);//T States: 5 |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1375 uint16_t dest_addr = inst->immed; |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1376 code_ptr call_dst = z80_get_native_address(context, dest_addr); |
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1377 if (!call_dst) { |
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1378 opts->gen.deferred = defer_address(opts->gen.deferred, dest_addr, code->cur + 1); |
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1379 //fake address to force large displacement |
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1380 call_dst = code->cur + 256; |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1381 } |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1382 jmp(code, call_dst); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1383 *no_jump_off = code->cur - (no_jump_off+1); |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1384 break; |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1385 } |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1386 case Z80_JR: { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1387 cycles(&opts->gen, 12);//T States: 4,3,5 |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1388 uint16_t dest_addr = address + inst->immed + 2; |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1389 code_ptr call_dst = z80_get_native_address(context, dest_addr); |
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1390 if (!call_dst) { |
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1391 opts->gen.deferred = defer_address(opts->gen.deferred, dest_addr, code->cur + 1); |
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1392 //fake address to force large displacement |
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1393 call_dst = code->cur + 256; |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1394 } |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1395 jmp(code, call_dst); |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1396 break; |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1397 } |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1398 case Z80_JRCC: { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1399 cycles(&opts->gen, 7);//T States: 4,3 |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1400 uint8_t cond = CC_Z; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1401 switch (inst->reg) |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1402 { |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1403 case Z80_CC_NZ: |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1404 cond = CC_NZ; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1405 case Z80_CC_Z: |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1406 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_Z), SZ_B); |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1407 break; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1408 case Z80_CC_NC: |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1409 cond = CC_NZ; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1410 case Z80_CC_C: |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1411 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B); |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1412 break; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1413 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1414 uint8_t *no_jump_off = code->cur+1; |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1415 jcc(code, cond, code->cur+2); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1416 cycles(&opts->gen, 5);//T States: 5 |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1417 uint16_t dest_addr = address + inst->immed + 2; |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1418 code_ptr call_dst = z80_get_native_address(context, dest_addr); |
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1419 if (!call_dst) { |
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1420 opts->gen.deferred = defer_address(opts->gen.deferred, dest_addr, code->cur + 1); |
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1421 //fake address to force large displacement |
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1422 call_dst = code->cur + 256; |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1423 } |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1424 jmp(code, call_dst); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1425 *no_jump_off = code->cur - (no_jump_off+1); |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1426 break; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1427 } |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1428 case Z80_DJNZ: { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1429 cycles(&opts->gen, 8);//T States: 5,3 |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1430 sub_ir(code, 1, opts->regs[Z80_B], SZ_B); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1431 uint8_t *no_jump_off = code->cur+1; |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1432 jcc(code, CC_Z, code->cur+2); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1433 cycles(&opts->gen, 5);//T States: 5 |
239
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
1434 uint16_t dest_addr = address + inst->immed + 2; |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1435 code_ptr call_dst = z80_get_native_address(context, dest_addr); |
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1436 if (!call_dst) { |
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1437 opts->gen.deferred = defer_address(opts->gen.deferred, dest_addr, code->cur + 1); |
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1438 //fake address to force large displacement |
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1439 call_dst = code->cur + 256; |
239
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
1440 } |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1441 jmp(code, call_dst); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1442 *no_jump_off = code->cur - (no_jump_off+1); |
239
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
1443 break; |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1444 } |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1445 case Z80_CALL: { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1446 cycles(&opts->gen, 11);//T States: 4,3,4 |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1447 sub_ir(code, 2, opts->regs[Z80_SP], SZ_W); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1448 mov_ir(code, address + 3, opts->gen.scratch1, SZ_W); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1449 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch2, SZ_W); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
1450 call(code, opts->write_16_highfirst);//T States: 3, 3 |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1451 code_ptr call_dst = z80_get_native_address(context, inst->immed); |
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1452 if (!call_dst) { |
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1453 opts->gen.deferred = defer_address(opts->gen.deferred, inst->immed, code->cur + 1); |
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1454 //fake address to force large displacement |
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1455 call_dst = code->cur + 256; |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1456 } |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1457 jmp(code, call_dst); |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1458 break; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1459 } |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1460 case Z80_CALLCC: { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1461 cycles(&opts->gen, 10);//T States: 4,3,3 (false case) |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1462 uint8_t cond = CC_Z; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1463 switch (inst->reg) |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1464 { |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1465 case Z80_CC_NZ: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1466 cond = CC_NZ; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1467 case Z80_CC_Z: |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1468 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_Z), SZ_B); |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1469 break; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1470 case Z80_CC_NC: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1471 cond = CC_NZ; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1472 case Z80_CC_C: |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1473 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B); |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1474 break; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1475 case Z80_CC_PO: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1476 cond = CC_NZ; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1477 case Z80_CC_PE: |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1478 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_PV), SZ_B); |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1479 break; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1480 case Z80_CC_P: |
367
f20562f2a570
Fix P condition in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
366
diff
changeset
|
1481 cond = CC_NZ; |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1482 case Z80_CC_M: |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1483 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_S), SZ_B); |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1484 break; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1485 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1486 uint8_t *no_call_off = code->cur+1; |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1487 jcc(code, cond, code->cur+2); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1488 cycles(&opts->gen, 1);//Last of the above T states takes an extra cycle in the true case |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1489 sub_ir(code, 2, opts->regs[Z80_SP], SZ_W); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1490 mov_ir(code, address + 3, opts->gen.scratch1, SZ_W); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1491 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch2, SZ_W); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
1492 call(code, opts->write_16_highfirst);//T States: 3, 3 |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1493 code_ptr call_dst = z80_get_native_address(context, inst->immed); |
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1494 if (!call_dst) { |
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1495 opts->gen.deferred = defer_address(opts->gen.deferred, inst->immed, code->cur + 1); |
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1496 //fake address to force large displacement |
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1497 call_dst = code->cur + 256; |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1498 } |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1499 jmp(code, call_dst); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1500 *no_call_off = code->cur - (no_call_off+1); |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1501 break; |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1502 } |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1503 case Z80_RET: |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1504 cycles(&opts->gen, 4);//T States: 4 |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1505 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
1506 call(code, opts->read_16);//T STates: 3, 3 |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1507 add_ir(code, 2, opts->regs[Z80_SP], SZ_W); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
1508 call(code, opts->native_addr); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1509 jmp_r(code, opts->gen.scratch1); |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1510 break; |
246
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1511 case Z80_RETCC: { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1512 cycles(&opts->gen, 5);//T States: 5 |
246
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1513 uint8_t cond = CC_Z; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1514 switch (inst->reg) |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1515 { |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1516 case Z80_CC_NZ: |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1517 cond = CC_NZ; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1518 case Z80_CC_Z: |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1519 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_Z), SZ_B); |
246
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1520 break; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1521 case Z80_CC_NC: |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1522 cond = CC_NZ; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1523 case Z80_CC_C: |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1524 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B); |
246
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1525 break; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1526 case Z80_CC_PO: |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1527 cond = CC_NZ; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1528 case Z80_CC_PE: |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1529 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_PV), SZ_B); |
246
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1530 break; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1531 case Z80_CC_P: |
367
f20562f2a570
Fix P condition in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
366
diff
changeset
|
1532 cond = CC_NZ; |
246
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1533 case Z80_CC_M: |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1534 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_S), SZ_B); |
246
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1535 break; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1536 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1537 uint8_t *no_call_off = code->cur+1; |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1538 jcc(code, cond, code->cur+2); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1539 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
1540 call(code, opts->read_16);//T STates: 3, 3 |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1541 add_ir(code, 2, opts->regs[Z80_SP], SZ_W); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
1542 call(code, opts->native_addr); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1543 jmp_r(code, opts->gen.scratch1); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1544 *no_call_off = code->cur - (no_call_off+1); |
246
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1545 break; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1546 } |
283
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1547 case Z80_RETI: |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1548 //For some systems, this may need a callback for signalling interrupt routine completion |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1549 cycles(&opts->gen, 8);//T States: 4, 4 |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1550 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
1551 call(code, opts->read_16);//T STates: 3, 3 |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1552 add_ir(code, 2, opts->regs[Z80_SP], SZ_W); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
1553 call(code, opts->native_addr); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1554 jmp_r(code, opts->gen.scratch1); |
283
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1555 break; |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1556 case Z80_RETN: |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1557 cycles(&opts->gen, 8);//T States: 4, 4 |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1558 mov_rdispr(code, opts->gen.context_reg, offsetof(z80_context, iff2), opts->gen.scratch2, SZ_B); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1559 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1560 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, offsetof(z80_context, iff1), SZ_B); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
1561 call(code, opts->read_16);//T STates: 3, 3 |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1562 add_ir(code, 2, opts->regs[Z80_SP], SZ_W); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
1563 call(code, opts->native_addr); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1564 jmp_r(code, opts->gen.scratch1); |
283
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1565 break; |
241
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1566 case Z80_RST: { |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1567 //RST is basically CALL to an address in page 0 |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1568 cycles(&opts->gen, 5);//T States: 5 |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1569 sub_ir(code, 2, opts->regs[Z80_SP], SZ_W); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1570 mov_ir(code, address + 1, opts->gen.scratch1, SZ_W); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1571 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch2, SZ_W); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
1572 call(code, opts->write_16_highfirst);//T States: 3, 3 |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1573 code_ptr call_dst = z80_get_native_address(context, inst->immed); |
241
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1574 if (!call_dst) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1575 opts->gen.deferred = defer_address(opts->gen.deferred, inst->immed, code->cur + 1); |
241
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1576 //fake address to force large displacement |
601
f0061e3d2ad9
Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor
Michael Pavone <pavone@retrodev.com>
parents:
598
diff
changeset
|
1577 call_dst = code->cur + 256; |
241
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1578 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1579 jmp(code, call_dst); |
241
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1580 break; |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1581 } |
284
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1582 case Z80_IN: |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1583 cycles(&opts->gen, inst->reg == Z80_A ? 7 : 8);//T States: 4 3/4 |
284
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1584 if (inst->addr_mode == Z80_IMMED_INDIRECT) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1585 mov_ir(code, inst->immed, opts->gen.scratch1, SZ_B); |
284
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1586 } else { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1587 mov_rr(code, opts->regs[Z80_C], opts->gen.scratch1, SZ_B); |
284
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1588 } |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
1589 call(code, opts->read_io); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1590 translate_z80_reg(inst, &dst_op, opts); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1591 mov_rr(code, opts->gen.scratch1, dst_op.base, SZ_B); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1592 z80_save_reg(inst, opts); |
284
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1593 break; |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1594 /*case Z80_INI: |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1595 case Z80_INIR: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1596 case Z80_IND: |
284
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1597 case Z80_INDR:*/ |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1598 case Z80_OUT: |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1599 cycles(&opts->gen, inst->reg == Z80_A ? 7 : 8);//T States: 4 3/4 |
284
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1600 if ((inst->addr_mode & 0x1F) == Z80_IMMED_INDIRECT) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1601 mov_ir(code, inst->immed, opts->gen.scratch2, SZ_B); |
284
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1602 } else { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1603 mov_rr(code, opts->regs[Z80_C], opts->gen.scratch2, SZ_B); |
284
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1604 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1605 translate_z80_reg(inst, &src_op, opts); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1606 mov_rr(code, dst_op.base, opts->gen.scratch1, SZ_B); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
1607 call(code, opts->write_io); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1608 z80_save_reg(inst, opts); |
284
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1609 break; |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1610 /*case Z80_OUTI: |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1611 case Z80_OTIR: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1612 case Z80_OUTD: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1613 case Z80_OTDR:*/ |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1614 default: { |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1615 char disbuf[80]; |
314
54c0e5f22198
Show absolute addresses for JR, JRCC and DJNZ in Z80 disassembler
Mike Pavone <pavone@retrodev.com>
parents:
313
diff
changeset
|
1616 z80_disasm(inst, disbuf, address); |
424
7e8e179116af
Add support for loading GST format savestates
Mike Pavone <pavone@retrodev.com>
parents:
420
diff
changeset
|
1617 fprintf(stderr, "unimplemented instruction: %s at %X\n", disbuf, address); |
259
d9417261366f
Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called.
Mike Pavone <pavone@retrodev.com>
parents:
257
diff
changeset
|
1618 FILE * f = fopen("zram.bin", "wb"); |
d9417261366f
Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called.
Mike Pavone <pavone@retrodev.com>
parents:
257
diff
changeset
|
1619 fwrite(context->mem_pointers[0], 1, 8 * 1024, f); |
d9417261366f
Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called.
Mike Pavone <pavone@retrodev.com>
parents:
257
diff
changeset
|
1620 fclose(f); |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1621 exit(1); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1622 } |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1623 } |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1624 } |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
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213
diff
changeset
|
1625 |
627
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1626 uint8_t * z80_interp_handler(uint8_t opcode, z80_context * context) |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1627 { |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1628 if (!context->interp_code[opcode]) { |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1629 if (opcode == 0xCB || (opcode >= 0xDD && opcode & 0xF == 0xD)) { |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1630 fprintf(stderr, "Encountered prefix byte %X at address %X. Z80 interpeter doesn't support those yet.", opcode, context->pc); |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1631 exit(1); |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1632 } |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1633 uint8_t codebuf[8]; |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1634 memset(codebuf, 0, sizeof(codebuf)); |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1635 codebuf[0] = opcode; |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1636 z80inst inst; |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1637 uint8_t * after = z80_decode(codebuf, &inst); |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1638 if (after - codebuf > 1) { |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1639 fprintf(stderr, "Encountered multi-byte Z80 instruction at %X. Z80 interpeter doesn't support those yet.", context->pc); |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1640 exit(1); |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1641 } |
652 | 1642 |
1643 z80_options * opts = context->options; | |
1644 code_info *code = &opts->gen.code; | |
1645 check_alloc_code(code, ZMAX_NATIVE_SIZE); | |
1646 context->interp_code[opcode] = code->cur; | |
1647 translate_z80inst(&inst, context, 0, 1); | |
1648 mov_rdispr(code, opts->gen.context_reg, offsetof(z80_context, pc), opts->gen.scratch1, SZ_W); | |
1649 add_ir(code, after - codebuf, opts->gen.scratch1, SZ_W); | |
1650 call(code, opts->native_addr); | |
1651 jmp_r(code, opts->gen.scratch1); | |
627
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1652 } |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1653 return context->interp_code[opcode]; |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1654 } |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1655 |
652 | 1656 code_info z80_make_interp_stub(z80_context * context, uint16_t address) |
627
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1657 { |
652 | 1658 z80_options *opts = context->options; |
1659 code_info * code = &opts->gen.code; | |
1660 check_alloc_code(code, 32); | |
1661 code_info stub = {code->cur, NULL}; | |
627
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1662 //TODO: make this play well with the breakpoint code |
652 | 1663 mov_ir(code, address, opts->gen.scratch1, SZ_W); |
1664 call(code, opts->read_8); | |
627
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1665 //normal opcode fetch is already factored into instruction timing |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1666 //back out the base 3 cycles from a read here |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1667 //not quite perfect, but it will have to do for now |
652 | 1668 cycles(&opts->gen, -3); |
1669 check_cycles_int(&opts->gen, address); | |
1670 call(code, opts->gen.save_context); | |
1671 mov_irdisp(code, address, opts->gen.context_reg, offsetof(z80_context, pc), SZ_W); | |
1672 push_r(code, opts->gen.context_reg); | |
657
92ce5ea5ffc9
Use call_args and call_args_abi in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
653
diff
changeset
|
1673 call_args(code, (code_ptr)z80_interp_handler, 2, opts->gen.scratch1, opts->gen.scratch2); |
652 | 1674 mov_rr(code, RAX, opts->gen.scratch1, SZ_Q); |
1675 pop_r(code, opts->gen.context_reg); | |
1676 call(code, opts->gen.load_context); | |
1677 jmp_r(code, opts->gen.scratch1); | |
1678 stub.last = code->cur; | |
1679 return stub; | |
627
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1680 } |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1681 |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1682 |
235
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1683 uint8_t * z80_get_native_address(z80_context * context, uint32_t address) |
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1684 { |
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1685 native_map_slot *map; |
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1686 if (address < 0x4000) { |
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1687 address &= 0x1FFF; |
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1688 map = context->static_code_map; |
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1689 } else { |
627
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1690 address -= 0x4000; |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1691 map = context->banked_code_map; |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1692 } |
268
6c2d7e003a55
Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents:
267
diff
changeset
|
1693 if (!map->base || !map->offsets || map->offsets[address] == INVALID_OFFSET || map->offsets[address] == EXTENSION_WORD) { |
313
a13329645ea3
Fix terminal instruction detection in disassembler
Mike Pavone <pavone@retrodev.com>
parents:
312
diff
changeset
|
1694 //dprintf("z80_get_native_address: %X NULL\n", address); |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1695 return NULL; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1696 } |
313
a13329645ea3
Fix terminal instruction detection in disassembler
Mike Pavone <pavone@retrodev.com>
parents:
312
diff
changeset
|
1697 //dprintf("z80_get_native_address: %X %p\n", address, map->base + map->offsets[address]); |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1698 return map->base + map->offsets[address]; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1699 } |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1700 |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
1701 uint8_t z80_get_native_inst_size(z80_options * opts, uint32_t address) |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1702 { |
627
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1703 //TODO: Fix for addresses >= 0x4000 |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1704 if (address >= 0x4000) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1705 return 0; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1706 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1707 return opts->gen.ram_inst_sizes[0][address & 0x1FFF]; |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1708 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1709 |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1710 void z80_map_native_address(z80_context * context, uint32_t address, uint8_t * native_address, uint8_t size, uint8_t native_size) |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1711 { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1712 uint32_t orig_address = address; |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1713 native_map_slot *map; |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
1714 z80_options * opts = context->options; |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1715 if (address < 0x4000) { |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1716 address &= 0x1FFF; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1717 map = context->static_code_map; |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1718 opts->gen.ram_inst_sizes[0][address] = native_size; |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1719 context->ram_code_flags[(address & 0x1C00) >> 10] |= 1 << ((address & 0x380) >> 7); |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1720 context->ram_code_flags[((address + size) & 0x1C00) >> 10] |= 1 << (((address + size) & 0x380) >> 7); |
627
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1721 } else { |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1722 //HERE |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1723 address -= 0x4000; |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1724 map = context->banked_code_map; |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1725 if (!map->offsets) { |
627
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1726 map->offsets = malloc(sizeof(int32_t) * 0xC000); |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1727 memset(map->offsets, 0xFF, sizeof(int32_t) * 0xC000); |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1728 } |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1729 } |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1730 if (!map->base) { |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1731 map->base = native_address; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1732 } |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1733 map->offsets[address] = native_address - map->base; |
253
3b34deba4ca0
Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents:
252
diff
changeset
|
1734 for(--size, orig_address++; size; --size, orig_address++) { |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1735 address = orig_address; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1736 if (address < 0x4000) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1737 address &= 0x1FFF; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1738 map = context->static_code_map; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1739 } else { |
627
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1740 address -= 0x4000; |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1741 map = context->banked_code_map; |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1742 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1743 if (!map->offsets) { |
627
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1744 map->offsets = malloc(sizeof(int32_t) * 0xC000); |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1745 memset(map->offsets, 0xFF, sizeof(int32_t) * 0xC000); |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1746 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1747 map->offsets[address] = EXTENSION_WORD; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1748 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1749 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1750 |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1751 #define INVALID_INSTRUCTION_START 0xFEEDFEED |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1752 |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1753 uint32_t z80_get_instruction_start(native_map_slot * static_code_map, uint32_t address) |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1754 { |
627
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1755 //TODO: Fixme for address >= 0x4000 |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1756 if (!static_code_map->base || address >= 0x4000) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1757 return INVALID_INSTRUCTION_START; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1758 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1759 address &= 0x1FFF; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1760 if (static_code_map->offsets[address] == INVALID_OFFSET) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1761 return INVALID_INSTRUCTION_START; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1762 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1763 while (static_code_map->offsets[address] == EXTENSION_WORD) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1764 --address; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1765 address &= 0x1FFF; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1766 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1767 return address; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1768 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1769 |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1770 z80_context * z80_handle_code_write(uint32_t address, z80_context * context) |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1771 { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1772 uint32_t inst_start = z80_get_instruction_start(context->static_code_map, address); |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1773 if (inst_start != INVALID_INSTRUCTION_START) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1774 code_ptr dst = z80_get_native_address(context, inst_start); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1775 code_info code = {dst, dst+16}; |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1776 z80_options * opts = context->options; |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1777 dprintf("patching code at %p for Z80 instruction at %X due to write to %X\n", code, inst_start, address); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1778 mov_ir(&code, inst_start, opts->gen.scratch1, SZ_D); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
1779 call(&code, opts->retrans_stub); |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1780 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1781 return context; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1782 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1783 |
264
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1784 uint8_t * z80_get_native_address_trans(z80_context * context, uint32_t address) |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1785 { |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1786 uint8_t * addr = z80_get_native_address(context, address); |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1787 if (!addr) { |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1788 translate_z80_stream(context, address); |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1789 addr = z80_get_native_address(context, address); |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1790 if (!addr) { |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1791 printf("Failed to translate %X to native code\n", address); |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1792 } |
8fd6652e56f8
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262
diff
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|
1793 } |
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Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
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262
diff
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|
1794 return addr; |
8fd6652e56f8
Fix a crash bug in instruction retranslation
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262
diff
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|
1795 } |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1796 |
266
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Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1797 void z80_handle_deferred(z80_context * context) |
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Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
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264
diff
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|
1798 { |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
1799 z80_options * opts = context->options; |
591
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Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
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590
diff
changeset
|
1800 process_deferred(&opts->gen.deferred, context, (native_addr_func)z80_get_native_address); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
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590
diff
changeset
|
1801 if (opts->gen.deferred) { |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
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diff
changeset
|
1802 translate_z80_stream(context, opts->gen.deferred->address); |
266
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264
diff
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|
1803 } |
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Mike Pavone <pavone@retrodev.com>
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264
diff
changeset
|
1804 } |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1805 |
390
561fe3ea3fc8
Use a call instruction to figure out the original native address when retranslating so that it does not get lost when the byte transforms from a instruction word to extension word
Mike Pavone <pavone@retrodev.com>
parents:
389
diff
changeset
|
1806 void * z80_retranslate_inst(uint32_t address, z80_context * context, uint8_t * orig_start) |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
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250
diff
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|
1807 { |
266
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Fix some more retranslation bugs in the Z80 core
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264
diff
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|
1808 char disbuf[80]; |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
1809 z80_options * opts = context->options; |
252
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Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
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250
diff
changeset
|
1810 uint8_t orig_size = z80_get_native_inst_size(opts, address); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
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590
diff
changeset
|
1811 code_info *code = &opts->gen.code; |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1812 uint8_t *after, *inst = get_native_pointer(address, (void **)context->mem_pointers, &opts->gen); |
252
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Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
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250
diff
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|
1813 z80inst instbuf; |
268
6c2d7e003a55
Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents:
267
diff
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|
1814 dprintf("Retranslating code at Z80 address %X, native address %p\n", address, orig_start); |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
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250
diff
changeset
|
1815 after = z80_decode(inst, &instbuf); |
268
6c2d7e003a55
Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents:
267
diff
changeset
|
1816 #ifdef DO_DEBUG_PRINT |
314
54c0e5f22198
Show absolute addresses for JR, JRCC and DJNZ in Z80 disassembler
Mike Pavone <pavone@retrodev.com>
parents:
313
diff
changeset
|
1817 z80_disasm(&instbuf, disbuf, address); |
266
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
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|
1818 if (instbuf.op == Z80_NOP) { |
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Mike Pavone <pavone@retrodev.com>
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264
diff
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|
1819 printf("%X\t%s(%d)\n", address, disbuf, instbuf.immed); |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
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264
diff
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|
1820 } else { |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
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264
diff
changeset
|
1821 printf("%X\t%s\n", address, disbuf); |
267
1788e3f29c28
Don't mix *H regs with the REX prefix
Mike Pavone <pavone@retrodev.com>
parents:
266
diff
changeset
|
1822 } |
268
6c2d7e003a55
Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
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267
diff
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|
1823 #endif |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
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250
diff
changeset
|
1824 if (orig_size != ZMAX_NATIVE_SIZE) { |
597
8d6ae5b3b87b
Update code->cur before calling z80_get_address_trans in z80_retranslate_inst to avoid any newly translated instructions from being placed in the "buffer zone". Save the current value of the code_info struct for placing the final jmp instruction in the correct place
Michael Pavone <pavone@retrodev.com>
parents:
594
diff
changeset
|
1825 check_alloc_code(code, ZMAX_NATIVE_SIZE); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1826 code_ptr start = code->cur; |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1827 deferred_addr * orig_deferred = opts->gen.deferred; |
652 | 1828 translate_z80inst(&instbuf, context, address, 0); |
644
2d7e84ae818c
Temporarily comment out code to translate Z80 instructions in place as in rare cases it can stomp the next instruction if a branch goes from a short from to a long one
Michael Pavone <pavone@retrodev.com>
parents:
628
diff
changeset
|
1829 /* |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
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250
diff
changeset
|
1830 if ((native_end - dst) <= orig_size) { |
264
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Mike Pavone <pavone@retrodev.com>
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262
diff
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|
1831 uint8_t * native_next = z80_get_native_address(context, address + after-inst); |
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Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
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262
diff
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|
1832 if (native_next && ((native_next == orig_start + orig_size) || (orig_size - (native_end - dst)) > 5)) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1833 remove_deferred_until(&opts->gen.deferred, orig_deferred); |
627
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1834 native_end = translate_z80inst(&instbuf, orig_start, context, address, 0); |
266
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Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1835 if (native_next == orig_start + orig_size && (native_next-native_end) < 2) { |
264
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Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1836 while (native_end < orig_start + orig_size) { |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1837 *(native_end++) = 0x90; //NOP |
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Mike Pavone <pavone@retrodev.com>
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262
diff
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|
1838 } |
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Mike Pavone <pavone@retrodev.com>
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262
diff
changeset
|
1839 } else { |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
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262
diff
changeset
|
1840 jmp(native_end, native_next); |
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Mike Pavone <pavone@retrodev.com>
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262
diff
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|
1841 } |
266
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parents:
264
diff
changeset
|
1842 z80_handle_deferred(context); |
264
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
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262
diff
changeset
|
1843 return orig_start; |
252
63b9a500a00b
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Mike Pavone <pavone@retrodev.com>
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250
diff
changeset
|
1844 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1845 }*/ |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
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diff
changeset
|
1846 z80_map_native_address(context, address, start, after-inst, ZMAX_NATIVE_SIZE); |
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Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
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590
diff
changeset
|
1847 code_info tmp_code = {orig_start, orig_start + 16}; |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1848 jmp(&tmp_code, start); |
597
8d6ae5b3b87b
Update code->cur before calling z80_get_address_trans in z80_retranslate_inst to avoid any newly translated instructions from being placed in the "buffer zone". Save the current value of the code_info struct for placing the final jmp instruction in the correct place
Michael Pavone <pavone@retrodev.com>
parents:
594
diff
changeset
|
1849 tmp_code = *code; |
8d6ae5b3b87b
Update code->cur before calling z80_get_address_trans in z80_retranslate_inst to avoid any newly translated instructions from being placed in the "buffer zone". Save the current value of the code_info struct for placing the final jmp instruction in the correct place
Michael Pavone <pavone@retrodev.com>
parents:
594
diff
changeset
|
1850 code->cur = start + ZMAX_NATIVE_SIZE; |
283
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1851 if (!z80_is_terminal(&instbuf)) { |
597
8d6ae5b3b87b
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Michael Pavone <pavone@retrodev.com>
parents:
594
diff
changeset
|
1852 jmp(&tmp_code, z80_get_native_address_trans(context, address + after-inst)); |
264
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Mike Pavone <pavone@retrodev.com>
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262
diff
changeset
|
1853 } |
266
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264
diff
changeset
|
1854 z80_handle_deferred(context); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1855 return start; |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
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250
diff
changeset
|
1856 } else { |
591
966b46c68942
Get Z80 core back into compileable state
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590
diff
changeset
|
1857 code_info tmp_code = *code; |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
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590
diff
changeset
|
1858 code->cur = orig_start; |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1859 code->last = orig_start + ZMAX_NATIVE_SIZE; |
652 | 1860 translate_z80inst(&instbuf, context, address, 0); |
601
f0061e3d2ad9
Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor
Michael Pavone <pavone@retrodev.com>
parents:
598
diff
changeset
|
1861 code_info tmp2 = *code; |
f0061e3d2ad9
Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor
Michael Pavone <pavone@retrodev.com>
parents:
598
diff
changeset
|
1862 *code = tmp_code; |
283
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1863 if (!z80_is_terminal(&instbuf)) { |
652 | 1864 |
601
f0061e3d2ad9
Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor
Michael Pavone <pavone@retrodev.com>
parents:
598
diff
changeset
|
1865 jmp(&tmp2, z80_get_native_address_trans(context, address + after-inst)); |
252
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250
diff
changeset
|
1866 } |
266
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diff
changeset
|
1867 z80_handle_deferred(context); |
252
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diff
changeset
|
1868 return orig_start; |
63b9a500a00b
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diff
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|
1869 } |
235
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213
diff
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|
1870 } |
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213
diff
changeset
|
1871 |
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diff
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|
1872 void translate_z80_stream(z80_context * context, uint32_t address) |
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diff
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|
1873 { |
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diff
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|
1874 char disbuf[80]; |
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|
1875 if (z80_get_native_address(context, address)) { |
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diff
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|
1876 return; |
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213
diff
changeset
|
1877 } |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
1878 z80_options * opts = context->options; |
505
b7b7a1cab44a
The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1879 uint32_t start_address = address; |
627
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1880 |
653
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diff
changeset
|
1881 do |
235
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diff
changeset
|
1882 { |
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diff
changeset
|
1883 z80inst inst; |
268
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Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
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diff
changeset
|
1884 dprintf("translating Z80 code at address %X\n", address); |
235
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213
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changeset
|
1885 do { |
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213
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changeset
|
1886 uint8_t * existing = z80_get_native_address(context, address); |
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|
1887 if (existing) { |
591
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diff
changeset
|
1888 jmp(&opts->gen.code, existing); |
235
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diff
changeset
|
1889 break; |
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diff
changeset
|
1890 } |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1891 uint8_t * encoded, *next; |
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1892 encoded = get_native_pointer(address, (void **)context->mem_pointers, &opts->gen); |
a18e3923481e
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Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1893 if (!encoded) { |
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1894 code_info stub = z80_make_interp_stub(context, address); |
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Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1895 z80_map_native_address(context, address, stub.cur, 1, stub.last - stub.cur); |
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1896 break; |
a18e3923481e
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Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
1897 } |
601
f0061e3d2ad9
Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor
Michael Pavone <pavone@retrodev.com>
parents:
598
diff
changeset
|
1898 //make sure prologue is in a contiguous chunk of code |
f0061e3d2ad9
Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor
Michael Pavone <pavone@retrodev.com>
parents:
598
diff
changeset
|
1899 check_code_prologue(&opts->gen.code); |
235
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1900 next = z80_decode(encoded, &inst); |
268
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1901 #ifdef DO_DEBUG_PRINT |
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1902 z80_disasm(&inst, disbuf, address); |
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1903 if (inst.op == Z80_NOP) { |
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1904 printf("%X\t%s(%d)\n", address, disbuf, inst.immed); |
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1905 } else { |
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1906 printf("%X\t%s\n", address, disbuf); |
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1907 } |
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1908 #endif |
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1909 code_ptr start = opts->gen.code.cur; |
652 | 1910 translate_z80inst(&inst, context, address, 0); |
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1911 z80_map_native_address(context, address, start, next-encoded, opts->gen.code.cur - start); |
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1912 address += next-encoded; |
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1913 address &= 0xFFFF; |
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1914 } while (!z80_is_terminal(&inst)); |
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1915 process_deferred(&opts->gen.deferred, context, (native_addr_func)z80_get_native_address); |
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1916 if (opts->gen.deferred) { |
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1917 address = opts->gen.deferred->address; |
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1918 dprintf("defferred address: %X\n", address); |
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1919 } |
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1920 } while (opts->gen.deferred); |
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1921 } |
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1922 |
659
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1923 void init_z80_opts(z80_options * options, memmap_chunk const * chunks, uint32_t num_chunks) |
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1924 { |
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1925 memset(options, 0, sizeof(*options)); |
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1926 |
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1927 options->gen.memmap = chunks; |
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1928 options->gen.memmap_chunks = num_chunks; |
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1929 options->gen.address_size = SZ_W; |
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1930 options->gen.address_mask = 0xFFFF; |
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1931 options->gen.max_address = 0x10000; |
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1932 options->gen.bus_cycles = 3; |
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1933 options->gen.mem_ptr_off = offsetof(z80_context, mem_pointers); |
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1934 options->gen.ram_flags_off = offsetof(z80_context, ram_code_flags); |
620
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1935 options->gen.ram_flags_shift = 7; |
590
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1936 |
235
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1937 options->flags = 0; |
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1938 options->regs[Z80_B] = BH; |
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1939 options->regs[Z80_C] = RBX; |
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1940 options->regs[Z80_D] = CH; |
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1941 options->regs[Z80_E] = RCX; |
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1942 options->regs[Z80_H] = AH; |
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1943 options->regs[Z80_L] = RAX; |
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1944 options->regs[Z80_IXH] = DH; |
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1945 options->regs[Z80_IXL] = RDX; |
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1946 options->regs[Z80_IYH] = -1; |
239
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1947 options->regs[Z80_IYL] = R8; |
235
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1948 options->regs[Z80_I] = -1; |
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1949 options->regs[Z80_R] = -1; |
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1950 options->regs[Z80_A] = R10; |
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1951 options->regs[Z80_BC] = RBX; |
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1952 options->regs[Z80_DE] = RCX; |
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1953 options->regs[Z80_HL] = RAX; |
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1954 options->regs[Z80_SP] = R9; |
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1955 options->regs[Z80_AF] = -1; |
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1956 options->regs[Z80_IX] = RDX; |
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1957 options->regs[Z80_IY] = R8; |
590
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1958 |
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1959 options->gen.context_reg = RSI; |
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1960 options->gen.cycles = RBP; |
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1961 options->gen.limit = RDI; |
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1962 options->gen.scratch1 = R13; |
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1963 options->gen.scratch2 = R14; |
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1964 |
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1965 options->gen.native_code_map = malloc(sizeof(native_map_slot)); |
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1966 memset(options->gen.native_code_map, 0, sizeof(native_map_slot)); |
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1967 options->gen.deferred = NULL; |
591
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1968 options->gen.ram_inst_sizes = malloc(sizeof(uint8_t) * 0x2000 + sizeof(uint8_t *)); |
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1969 options->gen.ram_inst_sizes[0] = (uint8_t *)(options->gen.ram_inst_sizes + 1); |
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1970 memset(options->gen.ram_inst_sizes[0], 0, sizeof(uint8_t) * 0x2000); |
590
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1971 |
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1972 code_info *code = &options->gen.code; |
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1973 init_code_info(code); |
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1974 |
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1975 options->save_context_scratch = code->cur; |
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1976 mov_rrdisp(code, options->gen.scratch1, options->gen.context_reg, offsetof(z80_context, scratch1), SZ_W); |
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1977 mov_rrdisp(code, options->gen.scratch2, options->gen.context_reg, offsetof(z80_context, scratch2), SZ_W); |
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1978 |
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1979 options->gen.save_context = code->cur; |
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1980 for (int i = 0; i <= Z80_A; i++) |
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1981 { |
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1982 int reg; |
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1983 uint8_t size; |
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1984 if (i < Z80_I) { |
594
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1985 reg = i /2 + Z80_BC + (i > Z80_H ? 2 : 0); |
590
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1986 size = SZ_W; |
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1987 } else { |
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1988 reg = i; |
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1989 size = SZ_B; |
652 | 1990 } |
590
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1991 if (options->regs[reg] >= 0) { |
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1992 mov_rrdisp(code, options->regs[reg], options->gen.context_reg, offsetof(z80_context, regs) + i, size); |
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1993 } |
594
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1994 if (size == SZ_W) { |
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|
1995 i++; |
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1996 } |
590
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1997 } |
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1998 if (options->regs[Z80_SP] >= 0) { |
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1999 mov_rrdisp(code, options->regs[Z80_SP], options->gen.context_reg, offsetof(z80_context, sp), SZ_W); |
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2000 } |
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2001 mov_rrdisp(code, options->gen.limit, options->gen.context_reg, offsetof(z80_context, target_cycle), SZ_D); |
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2002 mov_rrdisp(code, options->gen.cycles, options->gen.context_reg, offsetof(z80_context, current_cycle), SZ_D); |
593
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2003 retn(code); |
590
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2004 |
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2005 options->load_context_scratch = code->cur; |
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2006 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, scratch1), options->gen.scratch1, SZ_W); |
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2007 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, scratch2), options->gen.scratch2, SZ_W); |
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2008 options->gen.load_context = code->cur; |
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2009 for (int i = 0; i <= Z80_A; i++) |
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2010 { |
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WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2011 int reg; |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2012 uint8_t size; |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2013 if (i < Z80_I) { |
594
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2014 reg = i /2 + Z80_BC + (i > Z80_H ? 2 : 0); |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2015 size = SZ_W; |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2016 } else { |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2017 reg = i; |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2018 size = SZ_B; |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2019 } |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2020 if (options->regs[reg] >= 0) { |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2021 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, regs) + i, options->regs[reg], size); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2022 } |
594
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2023 if (size == SZ_W) { |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2024 i++; |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2025 } |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2026 } |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2027 if (options->regs[Z80_SP] >= 0) { |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2028 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, sp), options->regs[Z80_SP], SZ_W); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2029 } |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2030 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, target_cycle), options->gen.limit, SZ_D); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2031 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, current_cycle), options->gen.cycles, SZ_D); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2032 retn(code); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2033 |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2034 options->native_addr = code->cur; |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2035 call(code, options->gen.save_context); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2036 push_r(code, options->gen.context_reg); |
657
92ce5ea5ffc9
Use call_args and call_args_abi in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
653
diff
changeset
|
2037 movzx_rr(code, options->gen.scratch1, options->gen.scratch1, SZ_W, SZ_D); |
92ce5ea5ffc9
Use call_args and call_args_abi in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
653
diff
changeset
|
2038 call_args(code, (code_ptr)z80_get_native_address_trans, 2, options->gen.context_reg, options->gen.scratch1); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2039 mov_rr(code, RAX, options->gen.scratch1, SZ_PTR); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2040 pop_r(code, options->gen.context_reg); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2041 call(code, options->gen.load_context); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2042 retn(code); |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2043 |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2044 options->gen.handle_cycle_limit = code->cur; |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2045 cmp_rdispr(code, options->gen.context_reg, offsetof(z80_context, sync_cycle), options->gen.cycles, SZ_D); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2046 code_ptr no_sync = code->cur+1; |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2047 jcc(code, CC_B, no_sync); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2048 mov_irdisp(code, 0, options->gen.context_reg, offsetof(z80_context, pc), SZ_W); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2049 call(code, options->save_context_scratch); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2050 pop_r(code, RAX); //return address in read/write func |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2051 pop_r(code, RBX); //return address in translated code |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2052 sub_ir(code, 5, RAX, SZ_PTR); //adjust return address to point to the call that got us here |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2053 mov_rrdisp(code, RBX, options->gen.context_reg, offsetof(z80_context, extra_pc), SZ_PTR); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2054 mov_rrind(code, RAX, options->gen.context_reg, SZ_PTR); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2055 //restore callee saved registers |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2056 pop_r(code, R15); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2057 pop_r(code, R14); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2058 pop_r(code, R13); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2059 pop_r(code, R12); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2060 pop_r(code, RBP); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2061 pop_r(code, RBX); |
598
faad1927d836
Fix an off-by-one error in a branch destination in the generation of handle_cycle_limit for the Z80
Michael Pavone <pavone@retrodev.com>
parents:
597
diff
changeset
|
2062 *no_sync = code->cur - (no_sync + 1); |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2063 //return to caller of z80_run |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2064 retn(code); |
652 | 2065 |
594
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2066 options->gen.handle_code_write = (code_ptr)z80_handle_code_write; |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2067 |
594
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2068 options->read_8 = gen_mem_fun(&options->gen, chunks, num_chunks, READ_8, &options->read_8_noinc); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2069 options->write_8 = gen_mem_fun(&options->gen, chunks, num_chunks, WRITE_8, &options->write_8_noinc); |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2070 |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2071 options->gen.handle_cycle_limit_int = code->cur; |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2072 cmp_rdispr(code, options->gen.context_reg, offsetof(z80_context, int_cycle), options->gen.cycles, SZ_D); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2073 code_ptr skip_int = code->cur+1; |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2074 jcc(code, CC_B, skip_int); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2075 //set limit to the cycle limit |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2076 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, sync_cycle), options->gen.limit, SZ_D); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2077 //disable interrupts |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2078 mov_irdisp(code, 0, options->gen.context_reg, offsetof(z80_context, iff1), SZ_B); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2079 mov_irdisp(code, 0, options->gen.context_reg, offsetof(z80_context, iff2), SZ_B); |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2080 cycles(&options->gen, 7); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2081 //save return address (in scratch1) to Z80 stack |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2082 sub_ir(code, 2, options->regs[Z80_SP], SZ_W); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2083 mov_rr(code, options->regs[Z80_SP], options->gen.scratch2, SZ_W); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2084 //we need to do check_cycles and cycles outside of the write_8 call |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2085 //so that the stack has the correct depth if we need to return to C |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2086 //for a synchronization |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2087 check_cycles(&options->gen); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2088 cycles(&options->gen, 3); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2089 //save word to write before call to write_8_noinc |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2090 push_r(code, options->gen.scratch1); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2091 call(code, options->write_8_noinc); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2092 //restore word to write |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2093 pop_r(code, options->gen.scratch1); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2094 //write high byte to SP+1 |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2095 mov_rr(code, options->regs[Z80_SP], options->gen.scratch2, SZ_W); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2096 add_ir(code, 1, options->gen.scratch2, SZ_W); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2097 shr_ir(code, 8, options->gen.scratch1, SZ_W); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2098 check_cycles(&options->gen); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2099 cycles(&options->gen, 3); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2100 call(code, options->write_8_noinc); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2101 //dispose of return address as we'll be jumping somewhere else |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2102 pop_r(code, options->gen.scratch2); |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2103 //TODO: Support interrupt mode 0 and 2 |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2104 mov_ir(code, 0x38, options->gen.scratch1, SZ_W); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2105 call(code, options->native_addr); |
663
7a5461001242
Sync Z80 when taking an interrupt so that int_cycle gets updated
Michael Pavone <pavone@retrodev.com>
parents:
662
diff
changeset
|
2106 mov_rrind(code, options->gen.scratch1, options->gen.context_reg, SZ_PTR); |
7a5461001242
Sync Z80 when taking an interrupt so that int_cycle gets updated
Michael Pavone <pavone@retrodev.com>
parents:
662
diff
changeset
|
2107 //restore callee saved registers |
7a5461001242
Sync Z80 when taking an interrupt so that int_cycle gets updated
Michael Pavone <pavone@retrodev.com>
parents:
662
diff
changeset
|
2108 pop_r(code, R15); |
7a5461001242
Sync Z80 when taking an interrupt so that int_cycle gets updated
Michael Pavone <pavone@retrodev.com>
parents:
662
diff
changeset
|
2109 pop_r(code, R14); |
7a5461001242
Sync Z80 when taking an interrupt so that int_cycle gets updated
Michael Pavone <pavone@retrodev.com>
parents:
662
diff
changeset
|
2110 pop_r(code, R13); |
7a5461001242
Sync Z80 when taking an interrupt so that int_cycle gets updated
Michael Pavone <pavone@retrodev.com>
parents:
662
diff
changeset
|
2111 pop_r(code, R12); |
7a5461001242
Sync Z80 when taking an interrupt so that int_cycle gets updated
Michael Pavone <pavone@retrodev.com>
parents:
662
diff
changeset
|
2112 pop_r(code, RBP); |
7a5461001242
Sync Z80 when taking an interrupt so that int_cycle gets updated
Michael Pavone <pavone@retrodev.com>
parents:
662
diff
changeset
|
2113 pop_r(code, RBX); |
7a5461001242
Sync Z80 when taking an interrupt so that int_cycle gets updated
Michael Pavone <pavone@retrodev.com>
parents:
662
diff
changeset
|
2114 //return to caller of z80_run to sync |
7a5461001242
Sync Z80 when taking an interrupt so that int_cycle gets updated
Michael Pavone <pavone@retrodev.com>
parents:
662
diff
changeset
|
2115 retn(code); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2116 *skip_int = code->cur - (skip_int+1); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2117 cmp_rdispr(code, options->gen.context_reg, offsetof(z80_context, sync_cycle), options->gen.cycles, SZ_D); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2118 code_ptr skip_sync = code->cur + 1; |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2119 jcc(code, CC_B, skip_sync); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2120 options->do_sync = code->cur; |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2121 call(code, options->gen.save_context); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2122 pop_rind(code, options->gen.context_reg); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2123 //restore callee saved registers |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2124 pop_r(code, R15); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2125 pop_r(code, R14); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2126 pop_r(code, R13); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2127 pop_r(code, R12); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2128 pop_r(code, RBP); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2129 pop_r(code, RBX); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2130 //return to caller of z80_run |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2131 *skip_sync = code->cur - (skip_sync+1); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2132 retn(code); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2133 |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2134 options->read_io = code->cur; |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2135 check_cycles(&options->gen); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2136 cycles(&options->gen, 4); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2137 //Genesis has no IO hardware and always returns FF |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2138 //eventually this should use a second memory map array |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2139 mov_ir(code, 0xFF, options->gen.scratch1, SZ_B); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2140 retn(code); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2141 |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2142 options->write_io = code->cur; |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2143 check_cycles(&options->gen); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2144 cycles(&options->gen, 4); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2145 retn(code); |
652 | 2146 |
594
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2147 options->read_16 = code->cur; |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2148 cycles(&options->gen, 3); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2149 check_cycles(&options->gen); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2150 //TODO: figure out how to handle the extra wait state for word reads to bank area |
657
92ce5ea5ffc9
Use call_args and call_args_abi in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
653
diff
changeset
|
2151 //may also need special handling to avoid too much stack depth when access is blocked |
594
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2152 push_r(code, options->gen.scratch1); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2153 call(code, options->read_8_noinc); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2154 mov_rr(code, options->gen.scratch1, options->gen.scratch2, SZ_B); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2155 pop_r(code, options->gen.scratch1); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2156 add_ir(code, 1, options->gen.scratch1, SZ_W); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2157 cycles(&options->gen, 3); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2158 check_cycles(&options->gen); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2159 call(code, options->read_8_noinc); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2160 shl_ir(code, 8, options->gen.scratch1, SZ_W); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2161 mov_rr(code, options->gen.scratch2, options->gen.scratch1, SZ_B); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2162 retn(code); |
652 | 2163 |
594
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2164 options->write_16_highfirst = code->cur; |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2165 cycles(&options->gen, 3); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2166 check_cycles(&options->gen); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2167 push_r(code, options->gen.scratch2); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2168 push_r(code, options->gen.scratch1); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2169 add_ir(code, 1, options->gen.scratch2, SZ_W); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2170 shr_ir(code, 8, options->gen.scratch1, SZ_W); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2171 call(code, options->write_8_noinc); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2172 pop_r(code, options->gen.scratch1); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2173 pop_r(code, options->gen.scratch2); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2174 cycles(&options->gen, 3); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2175 check_cycles(&options->gen); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2176 //TODO: Check if we can get away with TCO here |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2177 call(code, options->write_8_noinc); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2178 retn(code); |
652 | 2179 |
594
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2180 options->write_16_lowfirst = code->cur; |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2181 cycles(&options->gen, 3); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2182 check_cycles(&options->gen); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2183 push_r(code, options->gen.scratch2); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2184 push_r(code, options->gen.scratch1); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2185 call(code, options->write_8_noinc); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2186 pop_r(code, options->gen.scratch1); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2187 pop_r(code, options->gen.scratch2); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2188 add_ir(code, 1, options->gen.scratch2, SZ_W); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2189 shr_ir(code, 8, options->gen.scratch1, SZ_W); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2190 cycles(&options->gen, 3); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2191 check_cycles(&options->gen); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2192 //TODO: Check if we can get away with TCO here |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2193 call(code, options->write_8_noinc); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2194 retn(code); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2195 |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2196 options->retrans_stub = code->cur; |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2197 //pop return address |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2198 pop_r(code, options->gen.scratch2); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2199 call(code, options->gen.save_context); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2200 //adjust pointer before move and call instructions that got us here |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2201 sub_ir(code, 11, options->gen.scratch2, SZ_PTR); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2202 push_r(code, options->gen.context_reg); |
657
92ce5ea5ffc9
Use call_args and call_args_abi in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
653
diff
changeset
|
2203 call_args(code, (code_ptr)z80_retranslate_inst, 3, options->gen.scratch1, options->gen.context_reg, options->gen.scratch2); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2204 pop_r(code, options->gen.context_reg); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2205 mov_rr(code, RAX, options->gen.scratch1, SZ_PTR); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2206 call(code, options->gen.load_context); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2207 jmp_r(code, options->gen.scratch1); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2208 |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2209 options->run = (z80_run_fun)code->cur; |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2210 //save callee save registers |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2211 push_r(code, RBX); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2212 push_r(code, RBP); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2213 push_r(code, R12); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2214 push_r(code, R13); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2215 push_r(code, R14); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2216 push_r(code, R15); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2217 mov_rr(code, RDI, options->gen.context_reg, SZ_PTR); |
594
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2218 call(code, options->load_context_scratch); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2219 cmp_irdisp(code, 0, options->gen.context_reg, offsetof(z80_context, extra_pc), SZ_PTR); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2220 code_ptr no_extra = code->cur+1; |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2221 jcc(code, CC_Z, no_extra); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2222 push_rdisp(code, options->gen.context_reg, offsetof(z80_context, extra_pc)); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2223 mov_irdisp(code, 0, options->gen.context_reg, offsetof(z80_context, extra_pc), SZ_PTR); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
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592
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2224 *no_extra = code->cur - (no_extra + 1); |
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2225 jmp_rind(code, options->gen.context_reg); |
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2226 } |
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2227 |
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2228 void init_z80_context(z80_context * context, z80_options * options) |
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2229 { |
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2230 memset(context, 0, sizeof(*context)); |
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2231 context->static_code_map = malloc(sizeof(*context->static_code_map)); |
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2232 context->static_code_map->base = NULL; |
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2233 context->static_code_map->offsets = malloc(sizeof(int32_t) * 0x2000); |
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2234 memset(context->static_code_map->offsets, 0xFF, sizeof(int32_t) * 0x2000); |
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2235 context->banked_code_map = malloc(sizeof(native_map_slot)); |
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2236 memset(context->banked_code_map, 0, sizeof(native_map_slot)); |
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2237 context->options = options; |
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2238 context->int_cycle = 0xFFFFFFFF; |
628 | 2239 context->int_pulse_start = 0xFFFFFFFF; |
2240 context->int_pulse_end = 0xFFFFFFFF; | |
593
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2241 context->run = options->run; |
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2242 } |
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2243 |
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2244 void z80_reset(z80_context * context) |
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2245 { |
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2246 context->im = 0; |
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2247 context->iff1 = context->iff2 = 0; |
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2248 context->native_pc = z80_get_native_address_trans(context, 0); |
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2249 context->extra_pc = NULL; |
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2250 } |
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2251 |
652 | 2252 uint32_t zbreakpoint_patch(z80_context * context, uint16_t address, code_ptr dst) |
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2253 { |
652 | 2254 code_info code = {dst, dst+16}; |
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2255 mov_ir(&code, address, context->options->gen.scratch1, SZ_W); |
652 | 2256 call(&code, context->bp_stub); |
2257 return code.cur-dst; | |
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2258 } |
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2259 |
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2260 void zcreate_stub(z80_context * context) |
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2261 { |
652 | 2262 z80_options * opts = context->options; |
2263 code_info *code = &opts->gen.code; | |
2264 check_code_prologue(code); | |
2265 context->bp_stub = code->cur; | |
626
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2266 |
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2267 //Calculate length of prologue |
652 | 2268 check_cycles_int(&opts->gen, 0); |
2269 int check_int_size = code->cur-context->bp_stub; | |
2270 code->cur = context->bp_stub; | |
626
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2271 |
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2272 //Calculate length of patch |
652 | 2273 int patch_size = zbreakpoint_patch(context, 0, code->cur); |
626
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2274 |
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2275 //Save context and call breakpoint handler |
652 | 2276 call(code, opts->gen.save_context); |
2277 push_r(code, opts->gen.scratch1); | |
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2278 call_args_abi(code, context->bp_handler, 2, opts->gen.context_reg, opts->gen.scratch1); |
652 | 2279 mov_rr(code, RAX, opts->gen.context_reg, SZ_Q); |
626
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2280 //Restore context |
652 | 2281 call(code, opts->gen.load_context); |
2282 pop_r(code, opts->gen.scratch1); | |
626
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2283 //do prologue stuff |
652 | 2284 cmp_rr(code, opts->gen.cycles, opts->gen.limit, SZ_D); |
2285 uint8_t * jmp_off = code->cur+1; | |
2286 jcc(code, CC_NC, code->cur + 7); | |
2287 pop_r(code, opts->gen.scratch1); | |
2288 add_ir(code, check_int_size - patch_size, opts->gen.scratch1, SZ_Q); | |
2289 push_r(code, opts->gen.scratch1); | |
2290 jmp(code, opts->gen.handle_cycle_limit_int); | |
2291 *jmp_off = code->cur - (jmp_off+1); | |
626
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2292 //jump back to body of translated instruction |
652 | 2293 pop_r(code, opts->gen.scratch1); |
2294 add_ir(code, check_int_size - patch_size, opts->gen.scratch1, SZ_Q); | |
2295 jmp_r(code, opts->gen.scratch1); | |
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2296 } |
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2297 |
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2298 void zinsert_breakpoint(z80_context * context, uint16_t address, uint8_t * bp_handler) |
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2299 { |
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2300 context->bp_handler = bp_handler; |
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2301 uint8_t bit = 1 << (address % sizeof(uint8_t)); |
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2302 if (!(bit & context->breakpoint_flags[address / sizeof(uint8_t)])) { |
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2303 context->breakpoint_flags[address / sizeof(uint8_t)] |= bit; |
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2304 if (!context->bp_stub) { |
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2305 zcreate_stub(context); |
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2306 } |
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2307 uint8_t * native = z80_get_native_address(context, address); |
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2308 if (native) { |
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2309 zbreakpoint_patch(context, address, native); |
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2310 } |
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2311 } |
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2312 } |
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2313 |
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2314 void zremove_breakpoint(z80_context * context, uint16_t address) |
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2315 { |
651
103d5cabbe14
Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
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2316 context->breakpoint_flags[address / sizeof(uint8_t)] &= ~(1 << (address % sizeof(uint8_t))); |
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2317 uint8_t * native = z80_get_native_address(context, address); |
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2318 if (native) { |
652 | 2319 z80_options * opts = context->options; |
2320 code_info tmp_code = opts->gen.code; | |
2321 opts->gen.code.cur = native; | |
2322 opts->gen.code.last = native + 16; | |
2323 check_cycles_int(&opts->gen, address); | |
2324 opts->gen.code = tmp_code; | |
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2325 } |
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2326 } |
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2327 |