Mercurial > repos > blastem
annotate m68k_to_x86.c @ 81:6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
author | Mike Pavone <pavone@retrodev.com> |
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date | Sat, 22 Dec 2012 21:37:25 -0800 |
parents | 463641032588 |
children | 6331ddec228f |
rev | line source |
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1 #include "gen_x86.h" |
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2 #include "m68k_to_x86.h" |
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3 #include <stdio.h> |
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4 #include <stddef.h> |
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5 #include <stdlib.h> |
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6 #include <string.h> |
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7 |
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8 #define BUS 4 |
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9 #define PREDEC_PENALTY 2 |
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10 #define CYCLES RAX |
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11 #define LIMIT RBP |
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12 #define SCRATCH1 RCX |
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13 #define SCRATCH2 RDI |
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14 #define CONTEXT RSI |
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15 |
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16 #define FLAG_N RBX |
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17 #define FLAG_V BH |
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18 #define FLAG_Z RDX |
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19 #define FLAG_C DH |
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20 |
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21 typedef struct { |
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22 int32_t disp; |
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23 uint8_t mode; |
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24 uint8_t base; |
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25 uint8_t index; |
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26 uint8_t cycles; |
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27 } x86_ea; |
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28 |
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29 void handle_cycle_limit(); |
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30 void m68k_read_word_scratch1(); |
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31 void m68k_read_long_scratch1(); |
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32 void m68k_read_byte_scratch1(); |
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33 void m68k_write_word(); |
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34 void m68k_write_long_lowfirst(); |
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35 void m68k_write_long_highfirst(); |
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36 void m68k_write_byte(); |
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37 void m68k_save_context(); |
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38 void m68k_modified_ret_addr(); |
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39 void m68k_native_addr(); |
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40 void m68k_start_context(uint8_t * addr, m68k_context * context); |
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41 |
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42 uint8_t * cycles(uint8_t * dst, uint32_t num) |
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43 { |
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44 dst = add_ir(dst, num, CYCLES, SZ_D); |
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45 } |
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46 |
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47 int8_t native_reg(m68k_op_info * op, x86_68k_options * opts) |
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48 { |
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49 if (op->addr_mode == MODE_REG) { |
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50 return opts->dregs[op->params.regs.pri]; |
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51 } |
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52 if (op->addr_mode == MODE_AREG) { |
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53 return opts->aregs[op->params.regs.pri]; |
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54 } |
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55 return -1; |
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56 } |
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57 |
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58 //must be called with an m68k_op_info that uses a register |
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59 size_t reg_offset(m68k_op_info *op) |
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60 { |
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61 if (op->addr_mode == MODE_REG) { |
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62 return offsetof(m68k_context, dregs) + sizeof(uint32_t) * op->params.regs.pri; |
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63 } |
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64 return offsetof(m68k_context, aregs) + sizeof(uint32_t) * op->params.regs.pri; |
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65 } |
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66 |
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67 void print_regs_exit(m68k_context * context) |
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68 { |
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69 printf("XNVZC\n%d%d%d%d%d\n", context->flags[0], context->flags[1], context->flags[2], context->flags[3], context->flags[4]); |
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70 for (int i = 0; i < 8; i++) { |
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71 printf("d%d: %X\n", i, context->dregs[i]); |
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72 } |
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73 for (int i = 0; i < 8; i++) { |
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74 printf("a%d: %X\n", i, context->aregs[i]); |
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75 } |
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76 exit(0); |
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77 } |
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78 |
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79 uint8_t * translate_m68k_src(m68kinst * inst, x86_ea * ea, uint8_t * out, x86_68k_options * opts) |
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80 { |
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81 int8_t reg = native_reg(&(inst->src), opts); |
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82 uint8_t sec_reg; |
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83 int32_t dec_amount,inc_amount; |
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84 if (reg >= 0) { |
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85 ea->mode = MODE_REG_DIRECT; |
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86 ea->base = reg; |
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87 return out; |
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88 } |
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89 switch (inst->src.addr_mode) |
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90 { |
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91 case MODE_REG: |
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92 case MODE_AREG: |
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93 //We only get one memory parameter, so if the dst operand is a register in memory, |
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94 //we need to copy this to a temp register first |
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95 reg = native_reg(&(inst->dst), opts); |
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96 if (reg >= 0 || inst->dst.addr_mode == MODE_UNUSED || (inst->dst.addr_mode != MODE_REG && inst->dst.addr_mode == MODE_AREG) |
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97 || inst->op == M68K_EXG) { |
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98 |
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99 ea->mode = MODE_REG_DISPLACE8; |
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100 ea->base = CONTEXT; |
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101 ea->disp = reg_offset(&(inst->src)); |
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102 } else { |
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103 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, inst->extra.size); |
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104 ea->mode = MODE_REG_DIRECT; |
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105 ea->base = SCRATCH1; |
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106 } |
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107 break; |
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108 case MODE_AREG_PREDEC: |
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109 dec_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : 1); |
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110 out = cycles(out, PREDEC_PENALTY); |
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111 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
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112 out = sub_ir(out, inc_amount, opts->aregs[inst->src.params.regs.pri], SZ_D); |
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113 } else { |
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114 out = sub_irdisp8(out, inc_amount, CONTEXT, reg_offset(&(inst->src)), SZ_D); |
18
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115 } |
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116 case MODE_AREG_INDIRECT: |
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117 case MODE_AREG_POSTINC: |
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118 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
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119 out = mov_rr(out, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
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120 } else { |
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121 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); |
18
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122 } |
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123 switch (inst->extra.size) |
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124 { |
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125 case OPSIZE_BYTE: |
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126 out = call(out, (char *)m68k_read_byte_scratch1); |
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127 break; |
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128 case OPSIZE_WORD: |
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129 out = call(out, (char *)m68k_read_word_scratch1); |
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130 break; |
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131 case OPSIZE_LONG: |
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132 out = call(out, (char *)m68k_read_long_scratch1); |
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133 break; |
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134 } |
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135 |
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136 if (inst->src.addr_mode == MODE_AREG_POSTINC) { |
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137 inc_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : 1); |
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138 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
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139 out = add_ir(out, inc_amount, opts->aregs[inst->src.params.regs.pri], SZ_D); |
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140 } else { |
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141 out = add_irdisp8(out, inc_amount, CONTEXT, reg_offset(&(inst->src)), SZ_D); |
18
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142 } |
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143 } |
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144 ea->mode = MODE_REG_DIRECT; |
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145 ea->base = SCRATCH1; |
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146 break; |
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147 case MODE_AREG_DISPLACE: |
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148 out = cycles(out, BUS); |
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149 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
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150 out = mov_rr(out, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
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151 } else { |
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152 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); |
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153 } |
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154 out = add_ir(out, inst->src.params.regs.displacement, SCRATCH1, SZ_D); |
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155 switch (inst->extra.size) |
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156 { |
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157 case OPSIZE_BYTE: |
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158 out = call(out, (char *)m68k_read_byte_scratch1); |
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159 break; |
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160 case OPSIZE_WORD: |
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161 out = call(out, (char *)m68k_read_word_scratch1); |
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162 break; |
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163 case OPSIZE_LONG: |
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164 out = call(out, (char *)m68k_read_long_scratch1); |
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165 break; |
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166 } |
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167 ea->mode = MODE_REG_DIRECT; |
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168 ea->base = SCRATCH1; |
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169 break; |
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170 case MODE_AREG_INDEX_DISP8: |
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171 out = cycles(out, 6); |
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172 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
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173 out = mov_rr(out, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
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174 } else { |
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175 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); |
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176 } |
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177 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7; |
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178 if (inst->src.params.regs.sec & 1) { |
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179 if (inst->src.params.regs.sec & 0x10) { |
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180 if (opts->aregs[sec_reg] >= 0) { |
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181 out = add_rr(out, opts->aregs[sec_reg], SCRATCH1, SZ_D); |
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182 } else { |
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183 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
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184 } |
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185 } else { |
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186 if (opts->dregs[sec_reg] >= 0) { |
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187 out = add_rr(out, opts->dregs[sec_reg], SCRATCH1, SZ_D); |
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188 } else { |
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189 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
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190 } |
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191 } |
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192 } else { |
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193 if (inst->src.params.regs.sec & 0x10) { |
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194 if (opts->aregs[sec_reg] >= 0) { |
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195 out = movsx_rr(out, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
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196 } else { |
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197 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
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198 } |
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199 } else { |
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200 if (opts->dregs[sec_reg] >= 0) { |
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201 out = movsx_rr(out, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
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202 } else { |
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203 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
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204 } |
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205 } |
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206 out = add_rr(out, SCRATCH2, SCRATCH1, SZ_D); |
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207 } |
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208 if (inst->src.params.regs.displacement) { |
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209 out = add_ir(out, inst->src.params.regs.displacement, SCRATCH1, SZ_D); |
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210 } |
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211 break; |
71
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212 case MODE_PC_DISPLACE: |
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213 out = cycles(out, BUS); |
74
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|
214 out = mov_ir(out, inst->src.params.regs.displacement + inst->address+2, SCRATCH1, SZ_D); |
71
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215 switch (inst->extra.size) |
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216 { |
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217 case OPSIZE_BYTE: |
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218 out = call(out, (char *)m68k_read_byte_scratch1); |
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219 break; |
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220 case OPSIZE_WORD: |
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221 out = call(out, (char *)m68k_read_word_scratch1); |
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222 break; |
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223 case OPSIZE_LONG: |
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224 out = call(out, (char *)m68k_read_long_scratch1); |
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225 break; |
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226 } |
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227 ea->mode = MODE_REG_DIRECT; |
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228 ea->base = SCRATCH1; |
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229 break; |
81
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230 case MODE_PC_INDEX_DISP8: |
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231 out = cycles(out, 6); |
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232 out = mov_ir(out, inst->address, SCRATCH1, SZ_D); |
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233 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7; |
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234 if (inst->src.params.regs.sec & 1) { |
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235 if (inst->src.params.regs.sec & 0x10) { |
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236 if (opts->aregs[sec_reg] >= 0) { |
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237 out = add_rr(out, opts->aregs[sec_reg], SCRATCH1, SZ_D); |
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238 } else { |
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239 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
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240 } |
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241 } else { |
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242 if (opts->dregs[sec_reg] >= 0) { |
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243 out = add_rr(out, opts->dregs[sec_reg], SCRATCH1, SZ_D); |
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244 } else { |
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245 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
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246 } |
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247 } |
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248 } else { |
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249 if (inst->src.params.regs.sec & 0x10) { |
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250 if (opts->aregs[sec_reg] >= 0) { |
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251 out = movsx_rr(out, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
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252 } else { |
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253 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
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254 } |
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255 } else { |
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256 if (opts->dregs[sec_reg] >= 0) { |
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257 out = movsx_rr(out, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
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258 } else { |
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259 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
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260 } |
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261 } |
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262 out = add_rr(out, SCRATCH2, SCRATCH1, SZ_D); |
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263 } |
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264 if (inst->src.params.regs.displacement) { |
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265 out = add_ir(out, inst->src.params.regs.displacement, SCRATCH1, SZ_D); |
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266 } |
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267 break; |
54
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|
268 case MODE_ABSOLUTE: |
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269 case MODE_ABSOLUTE_SHORT: |
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270 if (inst->src.addr_mode == MODE_ABSOLUTE) { |
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|
271 out = cycles(out, BUS*2); |
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|
272 } else { |
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|
273 out = cycles(out, BUS); |
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|
274 } |
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|
275 out = mov_ir(out, inst->src.params.immed, SCRATCH1, SZ_D); |
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|
276 switch (inst->extra.size) |
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|
277 { |
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|
278 case OPSIZE_BYTE: |
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279 out = call(out, (char *)m68k_read_byte_scratch1); |
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|
280 break; |
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|
281 case OPSIZE_WORD: |
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|
282 out = call(out, (char *)m68k_read_word_scratch1); |
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|
283 break; |
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|
284 case OPSIZE_LONG: |
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|
285 out = call(out, (char *)m68k_read_long_scratch1); |
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|
286 break; |
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|
287 } |
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|
288 ea->mode = MODE_REG_DIRECT; |
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|
289 ea->base = SCRATCH1; |
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|
290 break; |
18
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diff
changeset
|
291 case MODE_IMMEDIATE: |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
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59
diff
changeset
|
292 case MODE_IMMEDIATE_WORD: |
18
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|
293 if (inst->variant != VAR_QUICK) { |
64
2b1a65f4b85d
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
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61
diff
changeset
|
294 out = cycles(out, (inst->extra.size == OPSIZE_LONG && inst->src.addr_mode == MODE_IMMEDIATE) ? BUS*2 : BUS); |
18
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|
295 } |
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|
296 ea->mode = MODE_IMMED; |
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297 ea->disp = inst->src.params.immed; |
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|
298 break; |
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|
299 default: |
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300 printf("address mode %d not implemented (src)\n", inst->src.addr_mode); |
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|
301 exit(1); |
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|
302 } |
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|
303 return out; |
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|
304 } |
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|
305 |
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|
306 uint8_t * translate_m68k_dst(m68kinst * inst, x86_ea * ea, uint8_t * out, x86_68k_options * opts) |
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|
307 { |
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|
308 int8_t reg = native_reg(&(inst->dst), opts); |
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|
309 int32_t dec_amount, inc_amount; |
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|
310 if (reg >= 0) { |
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diff
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|
311 ea->mode = MODE_REG_DIRECT; |
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|
312 ea->base = reg; |
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|
313 return out; |
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|
314 } |
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changeset
|
315 switch (inst->dst.addr_mode) |
14
2bdad0f52f42
x86 code gen, initial work on translator
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diff
changeset
|
316 { |
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|
317 case MODE_REG: |
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changeset
|
318 case MODE_AREG: |
18
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diff
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|
319 ea->mode = MODE_REG_DISPLACE8; |
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diff
changeset
|
320 ea->base = CONTEXT; |
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
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51
diff
changeset
|
321 ea->disp = reg_offset(&(inst->dst)); |
18
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|
322 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
323 case MODE_AREG_PREDEC: |
3e7bfde7606e
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Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
324 dec_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : 1); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
325 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
326 out = sub_ir(out, dec_amount, opts->aregs[inst->dst.params.regs.pri], SZ_D); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
327 } else { |
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
328 out = sub_irdisp8(out, dec_amount, CONTEXT, reg_offset(&(inst->dst)), SZ_D); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
329 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
330 case MODE_AREG_INDIRECT: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
331 case MODE_AREG_POSTINC: |
3e7bfde7606e
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parents:
14
diff
changeset
|
332 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
333 out = mov_rr(out, opts->aregs[inst->dst.params.regs.pri], SCRATCH1, SZ_D); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
334 } else { |
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
335 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->dst)), SCRATCH1, SZ_D); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
336 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
337 switch (inst->extra.size) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
338 { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
339 case OPSIZE_BYTE: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
340 out = call(out, (char *)m68k_read_byte_scratch1); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
341 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
342 case OPSIZE_WORD: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
diff
changeset
|
343 out = call(out, (char *)m68k_read_word_scratch1); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
344 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
345 case OPSIZE_LONG: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
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14
diff
changeset
|
346 out = call(out, (char *)m68k_read_long_scratch1); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
347 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
348 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
349 //save reg value in SCRATCH2 so we can use it to save the result in memory later |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
350 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
351 out = mov_rr(out, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
352 } else { |
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
353 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
354 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
355 |
71
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Mike Pavone <pavone@retrodev.com>
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70
diff
changeset
|
356 if (inst->dst.addr_mode == MODE_AREG_POSTINC) { |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
357 inc_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : 1); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
358 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
359 out = add_ir(out, inc_amount, opts->aregs[inst->dst.params.regs.pri], SZ_D); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
360 } else { |
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
361 out = add_irdisp8(out, inc_amount, CONTEXT, reg_offset(&(inst->dst)), SZ_D); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
362 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
363 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
364 ea->mode = MODE_REG_DIRECT; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
365 ea->base = SCRATCH1; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
366 break; |
71
f80fa1776507
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parents:
70
diff
changeset
|
367 case MODE_AREG_DISPLACE: |
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70
diff
changeset
|
368 out = cycles(out, BUS); |
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diff
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|
369 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
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70
diff
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|
370 out = mov_rr(out, opts->aregs[inst->dst.params.regs.pri], SCRATCH1, SZ_D); |
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70
diff
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|
371 } else { |
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diff
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|
372 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->dst)), SCRATCH1, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
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70
diff
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|
373 } |
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70
diff
changeset
|
374 out = add_ir(out, inst->dst.params.regs.displacement, SCRATCH1, SZ_D); |
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Implement more instructions and address modes
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70
diff
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|
375 out = push_r(out, SCRATCH1); |
f80fa1776507
Implement more instructions and address modes
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70
diff
changeset
|
376 switch (inst->extra.size) |
f80fa1776507
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Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
377 { |
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Mike Pavone <pavone@retrodev.com>
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70
diff
changeset
|
378 case OPSIZE_BYTE: |
f80fa1776507
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Mike Pavone <pavone@retrodev.com>
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70
diff
changeset
|
379 out = call(out, (char *)m68k_read_byte_scratch1); |
f80fa1776507
Implement more instructions and address modes
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parents:
70
diff
changeset
|
380 break; |
f80fa1776507
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parents:
70
diff
changeset
|
381 case OPSIZE_WORD: |
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70
diff
changeset
|
382 out = call(out, (char *)m68k_read_word_scratch1); |
f80fa1776507
Implement more instructions and address modes
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parents:
70
diff
changeset
|
383 break; |
f80fa1776507
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Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
384 case OPSIZE_LONG: |
f80fa1776507
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Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
385 out = call(out, (char *)m68k_read_long_scratch1); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
386 break; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
387 } |
f80fa1776507
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parents:
70
diff
changeset
|
388 out = pop_r(out, SCRATCH2); |
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Implement more instructions and address modes
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70
diff
changeset
|
389 ea->mode = MODE_REG_DIRECT; |
f80fa1776507
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parents:
70
diff
changeset
|
390 ea->base = SCRATCH1; |
f80fa1776507
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parents:
70
diff
changeset
|
391 break; |
f80fa1776507
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parents:
70
diff
changeset
|
392 case MODE_PC_DISPLACE: |
f80fa1776507
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Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
393 out = cycles(out, BUS); |
74
6396dc91f61e
Fix some bugs in movem with a register list destination
Mike Pavone <pavone@retrodev.com>
parents:
73
diff
changeset
|
394 out = mov_ir(out, inst->dst.params.regs.displacement + inst->address+2, SCRATCH1, SZ_D); |
71
f80fa1776507
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parents:
70
diff
changeset
|
395 out = push_r(out, SCRATCH1); |
f80fa1776507
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parents:
70
diff
changeset
|
396 switch (inst->extra.size) |
f80fa1776507
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Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
397 { |
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parents:
70
diff
changeset
|
398 case OPSIZE_BYTE: |
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parents:
70
diff
changeset
|
399 out = call(out, (char *)m68k_read_byte_scratch1); |
f80fa1776507
Implement more instructions and address modes
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parents:
70
diff
changeset
|
400 break; |
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parents:
70
diff
changeset
|
401 case OPSIZE_WORD: |
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parents:
70
diff
changeset
|
402 out = call(out, (char *)m68k_read_word_scratch1); |
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Implement more instructions and address modes
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parents:
70
diff
changeset
|
403 break; |
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Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
404 case OPSIZE_LONG: |
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Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
405 out = call(out, (char *)m68k_read_long_scratch1); |
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Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
406 break; |
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Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
407 } |
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70
diff
changeset
|
408 out = pop_r(out, SCRATCH2); |
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Implement more instructions and address modes
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parents:
70
diff
changeset
|
409 ea->mode = MODE_REG_DIRECT; |
f80fa1776507
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parents:
70
diff
changeset
|
410 ea->base = SCRATCH1; |
f80fa1776507
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Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
411 break; |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
412 case MODE_ABSOLUTE: |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
413 case MODE_ABSOLUTE_SHORT: |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
414 //Add cycles for reading address from instruction stream |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
415 if (inst->dst.addr_mode == MODE_ABSOLUTE) { |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
416 out = cycles(out, BUS*2); |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
417 } else { |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
418 out = cycles(out, BUS); |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
419 } |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
420 out = mov_ir(out, inst->dst.params.immed, SCRATCH1, SZ_D); |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
421 out = push_r(out, SCRATCH1); |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
422 switch (inst->extra.size) |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
423 { |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
424 case OPSIZE_BYTE: |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
425 out = call(out, (char *)m68k_read_byte_scratch1); |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
426 break; |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
427 case OPSIZE_WORD: |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
428 out = call(out, (char *)m68k_read_word_scratch1); |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
429 break; |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
430 case OPSIZE_LONG: |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
431 out = call(out, (char *)m68k_read_long_scratch1); |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
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|
432 break; |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
433 } |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
434 out = pop_r(out, SCRATCH2); |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
435 ea->mode = MODE_REG_DIRECT; |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
436 ea->base = SCRATCH1; |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
437 break; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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14
diff
changeset
|
438 default: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
diff
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|
439 printf("address mode %d not implemented (dst)\n", inst->dst.addr_mode); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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|
440 exit(1); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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|
441 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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|
442 return out; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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14
diff
changeset
|
443 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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14
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|
444 |
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M68K to x86 translation works for a limited subset of instructions and addressing modes
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changeset
|
445 uint8_t * m68k_save_result(m68kinst * inst, uint8_t * out, x86_68k_options * opts) |
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parents:
14
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changeset
|
446 { |
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M68K to x86 translation works for a limited subset of instructions and addressing modes
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14
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changeset
|
447 if (inst->dst.addr_mode != MODE_REG && inst->dst.addr_mode != MODE_AREG) { |
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M68K to x86 translation works for a limited subset of instructions and addressing modes
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|
448 switch (inst->extra.size) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
diff
changeset
|
449 { |
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M68K to x86 translation works for a limited subset of instructions and addressing modes
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14
diff
changeset
|
450 case OPSIZE_BYTE: |
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|
451 out = call(out, (char *)m68k_write_byte); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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14
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|
452 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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14
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|
453 case OPSIZE_WORD: |
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14
diff
changeset
|
454 out = call(out, (char *)m68k_write_word); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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14
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changeset
|
455 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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14
diff
changeset
|
456 case OPSIZE_LONG: |
3e7bfde7606e
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14
diff
changeset
|
457 out = call(out, (char *)m68k_write_long_lowfirst); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
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14
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changeset
|
458 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
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changeset
|
459 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
diff
changeset
|
460 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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14
diff
changeset
|
461 return out; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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14
diff
changeset
|
462 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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14
diff
changeset
|
463 |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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14
diff
changeset
|
464 uint8_t * get_native_address(native_map_slot * native_code_map, uint32_t address) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
diff
changeset
|
465 { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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14
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|
466 address &= 0xFFFFFF; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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14
diff
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|
467 uint32_t chunk = address / NATIVE_CHUNK_SIZE; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
diff
changeset
|
468 if (!native_code_map[chunk].base) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
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|
469 return NULL; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
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|
470 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
diff
changeset
|
471 uint32_t offset = address % NATIVE_CHUNK_SIZE; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
diff
changeset
|
472 if (native_code_map[chunk].offsets[offset] == INVALID_OFFSET) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
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changeset
|
473 return NULL; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
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14
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changeset
|
474 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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14
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|
475 return native_code_map[chunk].base + native_code_map[chunk].offsets[offset]; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
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changeset
|
476 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
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changeset
|
477 |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
diff
changeset
|
478 deferred_addr * defer_address(deferred_addr * old_head, uint32_t address, uint8_t *dest) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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14
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changeset
|
479 { |
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M68K to x86 translation works for a limited subset of instructions and addressing modes
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14
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|
480 deferred_addr * new_head = malloc(sizeof(deferred_addr)); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
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changeset
|
481 new_head->next = old_head; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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14
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|
482 new_head->address = address & 0xFFFFFF; |
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M68K to x86 translation works for a limited subset of instructions and addressing modes
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14
diff
changeset
|
483 new_head->dest = dest; |
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M68K to x86 translation works for a limited subset of instructions and addressing modes
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14
diff
changeset
|
484 return new_head; |
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M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
diff
changeset
|
485 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
486 |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
diff
changeset
|
487 void process_deferred(x86_68k_options * opts) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
diff
changeset
|
488 { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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changeset
|
489 deferred_addr * cur = opts->deferred; |
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14
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|
490 deferred_addr **last_next = &(opts->deferred); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
diff
changeset
|
491 while(cur) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
diff
changeset
|
492 { |
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M68K to x86 translation works for a limited subset of instructions and addressing modes
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14
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changeset
|
493 uint8_t * native = get_native_address(opts->native_code_map, cur->address); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
diff
changeset
|
494 if (native) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
diff
changeset
|
495 int32_t disp = native - (cur->dest + 4); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
496 uint8_t * out = cur->dest; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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14
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|
497 *(out++) = disp; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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14
diff
changeset
|
498 disp >>= 8; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
diff
changeset
|
499 *(out++) = disp; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
diff
changeset
|
500 disp >>= 8; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
501 *(out++) = disp; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
diff
changeset
|
502 disp >>= 8; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
diff
changeset
|
503 *out = disp; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
504 *last_next = cur->next; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
505 free(cur); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
506 cur = *last_next; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
diff
changeset
|
507 } else { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
diff
changeset
|
508 last_next = &(cur->next); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
diff
changeset
|
509 cur = cur->next; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
510 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
511 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
512 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
513 |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
514 void map_native_address(native_map_slot * native_code_map, uint32_t address, uint8_t * native_addr) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
diff
changeset
|
515 { |
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M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
diff
changeset
|
516 //FIXME: This probably isn't going to work with real code in a lot of cases, no guarantee that |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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14
diff
changeset
|
517 //all the code in 1KB block is going to be translated at the same time |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
diff
changeset
|
518 address &= 0xFFFFFF; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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14
diff
changeset
|
519 uint32_t chunk = address / NATIVE_CHUNK_SIZE; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
diff
changeset
|
520 if (!native_code_map[chunk].base) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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14
diff
changeset
|
521 native_code_map[chunk].base = native_addr; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
diff
changeset
|
522 native_code_map[chunk].offsets = malloc(sizeof(uint16_t) * NATIVE_CHUNK_SIZE); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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14
diff
changeset
|
523 memset(native_code_map[chunk].offsets, 0xFF, sizeof(uint16_t) * NATIVE_CHUNK_SIZE); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
diff
changeset
|
524 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
diff
changeset
|
525 uint32_t offset = address % NATIVE_CHUNK_SIZE; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
diff
changeset
|
526 native_code_map[chunk].offsets[offset] = native_addr-native_code_map[chunk].base; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
527 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
528 |
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M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
diff
changeset
|
529 uint8_t * translate_m68k_move(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
530 { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
diff
changeset
|
531 int8_t reg, flags_reg; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
diff
changeset
|
532 uint8_t dir = 0; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
diff
changeset
|
533 int32_t offset; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
534 int32_t inc_amount, dec_amount; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
535 x86_ea src; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
536 dst = translate_m68k_src(inst, &src, dst, opts); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
537 reg = native_reg(&(inst->dst), opts); |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
538 //update statically set flags |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
539 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
540 dst = mov_ir(dst, 0, FLAG_C, SZ_B); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
541 |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
542 if (src.mode == MODE_REG_DIRECT) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
543 flags_reg = src.base; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
544 } else { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
545 if (reg >= 0) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
546 flags_reg = reg; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
547 } else { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
548 dst = mov_ir(dst, src.disp, SCRATCH1, SZ_D); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
549 src.mode = MODE_REG_DIRECT; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
550 flags_reg = src.base = SCRATCH1; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
551 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
552 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
553 switch(inst->dst.addr_mode) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
554 { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
555 case MODE_REG: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
556 case MODE_AREG: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
557 if (reg >= 0) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
558 if (src.mode == MODE_REG_DIRECT) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
559 dst = mov_rr(dst, src.base, reg, inst->extra.size); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
560 } else if (src.mode == MODE_REG_DISPLACE8) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
561 dst = mov_rdisp8r(dst, src.base, src.disp, reg, inst->extra.size); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
562 } else { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
563 dst = mov_ir(dst, src.disp, reg, inst->extra.size); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
564 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
565 } else if(src.mode == MODE_REG_DIRECT) { |
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
566 dst = mov_rrdisp8(dst, src.base, CONTEXT, reg_offset(&(inst->dst)), inst->extra.size); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
567 } else { |
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
568 dst = mov_irdisp8(dst, src.disp, CONTEXT, reg_offset(&(inst->dst)), inst->extra.size); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
569 } |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
570 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
571 dst = setcc_r(dst, CC_Z, FLAG_Z); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
572 dst = setcc_r(dst, CC_S, FLAG_N); |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
573 break; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
574 case MODE_AREG_PREDEC: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
575 dec_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : 1); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
576 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
577 dst = sub_ir(dst, dec_amount, opts->aregs[inst->dst.params.regs.pri], SZ_D); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
578 } else { |
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
579 dst = sub_irdisp8(dst, dec_amount, CONTEXT, reg_offset(&(inst->dst)), SZ_D); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
580 } |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
581 case MODE_AREG_INDIRECT: |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
582 case MODE_AREG_POSTINC: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
583 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
584 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
585 } else { |
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
586 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
587 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
588 if (src.mode == MODE_REG_DIRECT) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
589 if (src.base != SCRATCH1) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
590 dst = mov_rr(dst, src.base, SCRATCH1, inst->extra.size); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
591 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
592 } else if (src.mode == MODE_REG_DISPLACE8) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
593 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
594 } else { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
595 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
596 } |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
597 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
598 dst = setcc_r(dst, CC_Z, FLAG_Z); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
599 dst = setcc_r(dst, CC_S, FLAG_N); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
600 switch (inst->extra.size) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
601 { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
602 case OPSIZE_BYTE: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
603 dst = call(dst, (char *)m68k_write_byte); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
604 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
605 case OPSIZE_WORD: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
606 dst = call(dst, (char *)m68k_write_word); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
607 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
608 case OPSIZE_LONG: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
609 dst = call(dst, (char *)m68k_write_long_highfirst); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
610 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
611 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
612 if (inst->dst.addr_mode == MODE_AREG_POSTINC) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
613 inc_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : 1); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
614 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
615 dst = add_ir(dst, inc_amount, opts->aregs[inst->dst.params.regs.pri], SZ_D); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
616 } else { |
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
617 dst = add_irdisp8(dst, inc_amount, CONTEXT, reg_offset(&(inst->dst)), SZ_D); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
618 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
619 } |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
620 break; |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
621 case MODE_AREG_DISPLACE: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
622 dst = cycles(dst, BUS); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
623 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
624 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
625 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
626 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
627 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
628 dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH2, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
629 if (src.mode == MODE_REG_DIRECT) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
630 if (src.base != SCRATCH1) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
631 dst = mov_rr(dst, src.base, SCRATCH1, inst->extra.size); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
632 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
633 } else if (src.mode == MODE_REG_DISPLACE8) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
634 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
635 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
636 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
637 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
638 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
639 dst = setcc_r(dst, CC_Z, FLAG_Z); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
640 dst = setcc_r(dst, CC_S, FLAG_N); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
641 switch (inst->extra.size) |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
642 { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
643 case OPSIZE_BYTE: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
644 dst = call(dst, (char *)m68k_write_byte); |
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diff
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645 break; |
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|
646 case OPSIZE_WORD: |
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diff
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|
647 dst = call(dst, (char *)m68k_write_word); |
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diff
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648 break; |
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diff
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|
649 case OPSIZE_LONG: |
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diff
changeset
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650 dst = call(dst, (char *)m68k_write_long_highfirst); |
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651 break; |
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|
652 } |
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diff
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|
653 break; |
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Mike Pavone <pavone@retrodev.com>
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diff
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|
654 case MODE_PC_DISPLACE: |
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70
diff
changeset
|
655 dst = cycles(dst, BUS); |
74
6396dc91f61e
Fix some bugs in movem with a register list destination
Mike Pavone <pavone@retrodev.com>
parents:
73
diff
changeset
|
656 dst = mov_ir(dst, inst->dst.params.regs.displacement + inst->address+2, SCRATCH2, SZ_D); |
71
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70
diff
changeset
|
657 if (src.mode == MODE_REG_DIRECT) { |
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diff
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|
658 if (src.base != SCRATCH1) { |
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Mike Pavone <pavone@retrodev.com>
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diff
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|
659 dst = mov_rr(dst, src.base, SCRATCH1, inst->extra.size); |
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660 } |
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diff
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661 } else if (src.mode == MODE_REG_DISPLACE8) { |
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diff
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|
662 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size); |
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70
diff
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663 } else { |
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70
diff
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664 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size); |
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665 } |
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666 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size); |
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667 dst = setcc_r(dst, CC_Z, FLAG_Z); |
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diff
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|
668 dst = setcc_r(dst, CC_S, FLAG_N); |
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70
diff
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|
669 switch (inst->extra.size) |
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diff
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|
670 { |
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diff
changeset
|
671 case OPSIZE_BYTE: |
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70
diff
changeset
|
672 dst = call(dst, (char *)m68k_write_byte); |
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diff
changeset
|
673 break; |
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70
diff
changeset
|
674 case OPSIZE_WORD: |
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70
diff
changeset
|
675 dst = call(dst, (char *)m68k_write_word); |
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70
diff
changeset
|
676 break; |
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70
diff
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|
677 case OPSIZE_LONG: |
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70
diff
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|
678 dst = call(dst, (char *)m68k_write_long_highfirst); |
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70
diff
changeset
|
679 break; |
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70
diff
changeset
|
680 } |
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Mike Pavone <pavone@retrodev.com>
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diff
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|
681 break; |
54
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parents:
53
diff
changeset
|
682 case MODE_ABSOLUTE: |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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53
diff
changeset
|
683 case MODE_ABSOLUTE_SHORT: |
3b79cbcf6846
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parents:
53
diff
changeset
|
684 if (src.mode == MODE_REG_DIRECT) { |
3b79cbcf6846
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Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
685 if (src.base != SCRATCH1) { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
686 dst = mov_rr(dst, src.base, SCRATCH1, inst->extra.size); |
3b79cbcf6846
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Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
687 } |
3b79cbcf6846
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parents:
53
diff
changeset
|
688 } else if (src.mode == MODE_REG_DISPLACE8) { |
3b79cbcf6846
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Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
689 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size); |
3b79cbcf6846
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Mike Pavone <pavone@retrodev.com>
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53
diff
changeset
|
690 } else { |
3b79cbcf6846
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53
diff
changeset
|
691 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size); |
3b79cbcf6846
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Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
692 } |
3b79cbcf6846
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parents:
53
diff
changeset
|
693 if (inst->dst.addr_mode == MODE_ABSOLUTE) { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
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53
diff
changeset
|
694 dst = cycles(dst, BUS*2); |
3b79cbcf6846
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Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
695 } else { |
3b79cbcf6846
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parents:
53
diff
changeset
|
696 dst = cycles(dst, BUS); |
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parents:
53
diff
changeset
|
697 } |
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53
diff
changeset
|
698 dst = mov_ir(dst, inst->dst.params.immed, SCRATCH2, SZ_D); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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53
diff
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|
699 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
700 dst = setcc_r(dst, CC_Z, FLAG_Z); |
3b79cbcf6846
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Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
701 dst = setcc_r(dst, CC_S, FLAG_N); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
702 switch (inst->extra.size) |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
703 { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
704 case OPSIZE_BYTE: |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
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53
diff
changeset
|
705 dst = call(dst, (char *)m68k_write_byte); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
706 break; |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
707 case OPSIZE_WORD: |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
708 dst = call(dst, (char *)m68k_write_word); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
709 break; |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
710 case OPSIZE_LONG: |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
711 dst = call(dst, (char *)m68k_write_long_highfirst); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
712 break; |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
713 } |
3b79cbcf6846
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Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
714 break; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
715 default: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
716 printf("address mode %d not implemented (move dst)\n", inst->dst.addr_mode); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
717 exit(1); |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
718 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
719 |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
720 //add cycles for prefetch |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
721 dst = cycles(dst, BUS); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
722 return dst; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
723 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
724 |
71
f80fa1776507
Implement more instructions and address modes
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parents:
70
diff
changeset
|
725 uint8_t * translate_m68k_movem(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
f80fa1776507
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Mike Pavone <pavone@retrodev.com>
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70
diff
changeset
|
726 { |
f80fa1776507
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Mike Pavone <pavone@retrodev.com>
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70
diff
changeset
|
727 int8_t bit,reg; |
f80fa1776507
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Mike Pavone <pavone@retrodev.com>
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70
diff
changeset
|
728 uint8_t early_cycles; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
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70
diff
changeset
|
729 if(inst->src.addr_mode == MODE_REG) { |
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70
diff
changeset
|
730 //reg to mem |
f80fa1776507
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70
diff
changeset
|
731 early_cycles = 8; |
f80fa1776507
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70
diff
changeset
|
732 int8_t dir; |
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Mike Pavone <pavone@retrodev.com>
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70
diff
changeset
|
733 if (inst->dst.addr_mode == MODE_AREG_PREDEC) { |
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parents:
70
diff
changeset
|
734 reg = 15; |
f80fa1776507
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70
diff
changeset
|
735 dir = -1; |
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Mike Pavone <pavone@retrodev.com>
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70
diff
changeset
|
736 } else { |
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70
diff
changeset
|
737 reg = 0; |
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70
diff
changeset
|
738 } |
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parents:
70
diff
changeset
|
739 switch (inst->dst.addr_mode) |
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70
diff
changeset
|
740 { |
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parents:
70
diff
changeset
|
741 case MODE_AREG_INDIRECT: |
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70
diff
changeset
|
742 case MODE_AREG_PREDEC: |
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70
diff
changeset
|
743 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
f80fa1776507
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70
diff
changeset
|
744 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D); |
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parents:
70
diff
changeset
|
745 } else { |
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70
diff
changeset
|
746 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D); |
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diff
changeset
|
747 } |
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parents:
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diff
changeset
|
748 break; |
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diff
changeset
|
749 case MODE_ABSOLUTE: |
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70
diff
changeset
|
750 early_cycles += 4; |
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70
diff
changeset
|
751 case MODE_ABSOLUTE_SHORT: |
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70
diff
changeset
|
752 early_cycles += 4; |
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70
diff
changeset
|
753 dst = mov_ir(dst, inst->dst.params.immed, SCRATCH2, SZ_D); |
f80fa1776507
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parents:
70
diff
changeset
|
754 break; |
f80fa1776507
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parents:
70
diff
changeset
|
755 default: |
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70
diff
changeset
|
756 printf("address mode %d not implemented (movem dst)\n", inst->dst.addr_mode); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
757 exit(1); |
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parents:
70
diff
changeset
|
758 } |
f80fa1776507
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parents:
70
diff
changeset
|
759 dst = cycles(dst, early_cycles); |
f80fa1776507
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parents:
70
diff
changeset
|
760 for(bit=0; reg < 16 && reg >= 0; reg += dir, bit++) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
761 if (inst->src.params.immed & (1 << bit)) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
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70
diff
changeset
|
762 if (inst->dst.addr_mode == MODE_AREG_PREDEC) { |
f80fa1776507
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Mike Pavone <pavone@retrodev.com>
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70
diff
changeset
|
763 dst = sub_ir(dst, (inst->extra.size == OPSIZE_LONG) ? 4 : 2, SCRATCH2, SZ_D); |
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parents:
70
diff
changeset
|
764 } |
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parents:
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diff
changeset
|
765 dst = push_r(dst, SCRATCH2); |
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766 if (reg > 7) { |
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767 if (opts->aregs[reg-8] >= 0) { |
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768 dst = mov_rr(dst, opts->aregs[reg-8], SCRATCH1, inst->extra.size); |
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769 } else { |
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770 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * (reg-8), SCRATCH1, inst->extra.size); |
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771 } |
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772 } else { |
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773 if (opts->dregs[reg] >= 0) { |
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774 dst = mov_rr(dst, opts->dregs[reg], SCRATCH1, inst->extra.size); |
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|
775 } else { |
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|
776 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t) * (reg), SCRATCH1, inst->extra.size); |
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777 } |
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778 } |
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|
779 if (inst->extra.size == OPSIZE_LONG) { |
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780 dst = call(dst, (uint8_t *)m68k_write_long_lowfirst); |
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781 } else { |
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782 dst = call(dst, (uint8_t *)m68k_write_word); |
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783 } |
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|
784 dst = pop_r(dst, SCRATCH2); |
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785 if (inst->dst.addr_mode != MODE_AREG_PREDEC) { |
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786 dst = add_ir(dst, (inst->extra.size == OPSIZE_LONG) ? 4 : 2, SCRATCH2, SZ_D); |
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787 } |
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788 } |
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789 } |
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790 if (inst->dst.addr_mode == MODE_AREG_PREDEC) { |
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791 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
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792 dst = mov_rr(dst, SCRATCH2, opts->aregs[inst->dst.params.regs.pri], SZ_D); |
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793 } else { |
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794 dst = mov_rrdisp8(dst, SCRATCH2, CONTEXT, reg_offset(&(inst->dst)), SZ_D); |
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795 } |
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796 } |
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797 } else { |
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798 //mem to reg |
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|
799 early_cycles = 4; |
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|
800 switch (inst->src.addr_mode) |
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801 { |
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802 case MODE_AREG_INDIRECT: |
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803 case MODE_AREG_POSTINC: |
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804 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
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805 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
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806 } else { |
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807 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); |
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808 } |
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809 break; |
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810 case MODE_ABSOLUTE: |
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811 early_cycles += 4; |
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812 case MODE_ABSOLUTE_SHORT: |
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813 early_cycles += 4; |
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814 dst = mov_ir(dst, inst->src.params.immed, SCRATCH1, SZ_D); |
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815 break; |
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|
816 default: |
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817 printf("address mode %d not implemented (movem src)\n", inst->src.addr_mode); |
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818 exit(1); |
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819 } |
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820 dst = cycles(dst, early_cycles); |
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821 for(reg = 0; reg < 16; reg ++) { |
74
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diff
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822 if (inst->dst.params.immed & (1 << reg)) { |
71
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823 dst = push_r(dst, SCRATCH1); |
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824 if (inst->extra.size == OPSIZE_LONG) { |
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825 dst = call(dst, (uint8_t *)m68k_read_long_scratch1); |
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826 } else { |
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827 dst = call(dst, (uint8_t *)m68k_read_word_scratch1); |
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828 } |
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829 if (reg > 7) { |
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830 if (opts->aregs[reg-8] >= 0) { |
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831 dst = mov_rr(dst, SCRATCH1, opts->aregs[reg-8], inst->extra.size); |
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832 } else { |
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833 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * (reg-8), inst->extra.size); |
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834 } |
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835 } else { |
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836 if (opts->dregs[reg] >= 0) { |
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837 dst = mov_rr(dst, SCRATCH1, opts->dregs[reg], inst->extra.size); |
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838 } else { |
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839 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t) * (reg), inst->extra.size); |
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840 } |
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841 } |
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842 dst = pop_r(dst, SCRATCH1); |
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843 dst = add_ir(dst, (inst->extra.size == OPSIZE_LONG) ? 4 : 2, SCRATCH1, SZ_D); |
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844 } |
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845 } |
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846 if (inst->src.addr_mode == MODE_AREG_POSTINC) { |
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847 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
74
6396dc91f61e
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73
diff
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|
848 dst = mov_rr(dst, SCRATCH1, opts->aregs[inst->src.params.regs.pri], SZ_D); |
71
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849 } else { |
74
6396dc91f61e
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|
850 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, reg_offset(&(inst->src)), SZ_D); |
71
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|
851 } |
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|
852 } |
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|
853 } |
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|
854 //prefetch |
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|
855 dst = cycles(dst, 4); |
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|
856 return dst; |
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857 } |
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|
858 |
52
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diff
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|
859 uint8_t * translate_m68k_clr(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
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|
860 { |
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diff
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|
861 dst = mov_ir(dst, 0, FLAG_N, SZ_B); |
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diff
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862 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
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diff
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|
863 dst = mov_ir(dst, 0, FLAG_C, SZ_B); |
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|
864 dst = mov_ir(dst, 1, FLAG_Z, SZ_B); |
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|
865 uint8_t reg = native_reg(&(inst->dst), opts); |
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|
866 if (reg >= 0) { |
64
2b1a65f4b85d
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61
diff
changeset
|
867 dst = cycles(dst, (inst->extra.size == OPSIZE_LONG ? 6 : 4)); |
2b1a65f4b85d
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61
diff
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|
868 return xor_rr(dst, reg, reg, inst->extra.size); |
52
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diff
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|
869 } |
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diff
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|
870 int32_t dec_amount,inc_amount; |
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diff
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871 switch (inst->dst.addr_mode) |
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diff
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|
872 { |
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|
873 case MODE_REG: |
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|
874 case MODE_AREG: |
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diff
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|
875 dst = cycles(dst, (inst->extra.size == OPSIZE_LONG ? 6 : 4)); |
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|
876 dst = mov_irdisp8(dst, 0, CONTEXT, reg_offset(&(inst->dst)), inst->extra.size); |
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diff
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|
877 break; |
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diff
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|
878 case MODE_AREG_PREDEC: |
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diff
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|
879 dst = cycles(dst, PREDEC_PENALTY); |
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diff
changeset
|
880 dec_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : 1); |
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|
881 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
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diff
changeset
|
882 dst = sub_ir(dst, dec_amount, opts->aregs[inst->dst.params.regs.pri], SZ_D); |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
883 } else { |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
884 dst = sub_irdisp8(dst, dec_amount, CONTEXT, reg_offset(&(inst->dst)), SZ_D); |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
885 } |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
886 case MODE_AREG_INDIRECT: |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
887 case MODE_AREG_POSTINC: |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
888 //add cycles for prefetch and wasted read |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
889 dst = cycles(dst, (inst->extra.size == OPSIZE_LONG ? 12 : 8)); |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
890 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
891 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D); |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
892 } else { |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
893 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D); |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
894 } |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
895 dst = xor_rr(dst, SCRATCH1, SCRATCH1, SZ_D); |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
896 switch (inst->extra.size) |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
897 { |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
898 case OPSIZE_BYTE: |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
899 dst = call(dst, (char *)m68k_write_byte); |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
900 break; |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
901 case OPSIZE_WORD: |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
902 dst = call(dst, (char *)m68k_write_word); |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
903 break; |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
904 case OPSIZE_LONG: |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
905 dst = call(dst, (char *)m68k_write_long_highfirst); |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
906 break; |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
907 } |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
908 if (inst->dst.addr_mode == MODE_AREG_POSTINC) { |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
909 inc_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : 1); |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
910 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
911 dst = add_ir(dst, inc_amount, opts->aregs[inst->dst.params.regs.pri], SZ_D); |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
912 } else { |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
913 dst = add_irdisp8(dst, inc_amount, CONTEXT, reg_offset(&(inst->dst)), SZ_D); |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
914 } |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
915 } |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
916 break; |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
917 default: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
918 printf("address mode %d not implemented (clr dst)\n", inst->dst.addr_mode); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
919 exit(1); |
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
920 } |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
921 return dst; |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
922 } |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
923 |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
924 uint8_t * translate_m68k_lea(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
925 { |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
926 int8_t dst_reg = native_reg(&(inst->dst), opts); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
927 switch(inst->src.addr_mode) |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
928 { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
929 case MODE_AREG_INDIRECT: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
930 dst = cycles(dst, BUS); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
931 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
932 if (dst_reg >= 0) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
933 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], dst_reg, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
934 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
935 dst = mov_rrdisp8(dst, opts->aregs[inst->src.params.regs.pri], CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->dst.params.regs.pri, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
936 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
937 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
938 if (dst_reg >= 0) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
939 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, dst_reg, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
940 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
941 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, SCRATCH1, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
942 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->dst.params.regs.pri, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
943 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
944 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
945 break; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
946 case MODE_AREG_DISPLACE: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
947 dst = cycles(dst, 8); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
948 if (dst_reg >= 0) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
949 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
950 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], dst_reg, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
951 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
952 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), dst_reg, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
953 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
954 dst = add_ir(dst, inst->src.params.regs.displacement, dst_reg, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
955 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
956 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
957 dst = mov_rrdisp8(dst, opts->aregs[inst->src.params.regs.pri], CONTEXT, reg_offset(&(inst->dst)), SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
958 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
959 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
960 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, reg_offset(&(inst->dst)), SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
961 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
962 dst = add_irdisp8(dst, inst->src.params.regs.displacement, CONTEXT, reg_offset(&(inst->src)), SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
963 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
964 break; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
965 case MODE_PC_DISPLACE: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
966 dst = cycles(dst, 8); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
967 if (dst_reg >= 0) { |
74
6396dc91f61e
Fix some bugs in movem with a register list destination
Mike Pavone <pavone@retrodev.com>
parents:
73
diff
changeset
|
968 dst = mov_ir(dst, inst->src.params.regs.displacement + inst->address+2, dst_reg, SZ_D); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
969 } else { |
74
6396dc91f61e
Fix some bugs in movem with a register list destination
Mike Pavone <pavone@retrodev.com>
parents:
73
diff
changeset
|
970 dst = mov_irdisp8(dst, inst->src.params.regs.displacement + inst->address+2, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->dst.params.regs.pri, SZ_D); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
971 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
972 break; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
973 case MODE_ABSOLUTE: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
974 case MODE_ABSOLUTE_SHORT: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
975 dst = cycles(dst, (inst->src.addr_mode == MODE_ABSOLUTE) ? BUS * 3 : BUS * 2); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
976 if (dst_reg >= 0) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
977 dst = mov_ir(dst, inst->src.params.immed, dst_reg, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
978 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
979 dst = mov_irdisp8(dst, inst->src.params.immed, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->dst.params.regs.pri, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
980 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
981 break; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
982 default: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
983 printf("address mode %d not implemented (lea src)\n", inst->src.addr_mode); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
984 exit(1); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
985 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
986 return dst; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
987 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
988 |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
989 uint8_t * translate_m68k_bsr(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
990 { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
991 int32_t disp = inst->src.params.immed; |
46
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
992 uint32_t after = inst->address + 2; |
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
993 //TODO: Add cycles in the right place relative to pushing the return address on the stack |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
994 dst = cycles(dst, 10); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
995 dst = mov_ir(dst, after, SCRATCH1, SZ_D); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
996 dst = push_r(dst, SCRATCH1); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
997 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
998 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
999 dst = call(dst, (char *)m68k_write_long_highfirst); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1000 uint8_t * dest_addr = get_native_address(opts->native_code_map, after + disp); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1001 if (!dest_addr) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1002 opts->deferred = defer_address(opts->deferred, after + disp, dst + 1); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1003 //dummy address to be replaced later |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1004 dest_addr = dst + 5; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1005 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1006 dst = call(dst, (char *)dest_addr); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1007 //would add_ir(dst, 8, RSP, SZ_Q) be faster here? |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1008 dst = pop_r(dst, SCRATCH1); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1009 return dst; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1010 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1011 |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1012 uint8_t * translate_m68k_bcc(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1013 { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1014 //TODO: Add cycles |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1015 int32_t disp = inst->src.params.immed; |
46
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1016 uint32_t after = inst->address + 2; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1017 uint8_t * dest_addr = get_native_address(opts->native_code_map, after + disp); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1018 if (inst->extra.cond == COND_TRUE) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1019 if (!dest_addr) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1020 opts->deferred = defer_address(opts->deferred, after + disp, dst + 1); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1021 //dummy address to be replaced later, make sure it generates a 4-byte displacement |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1022 dest_addr = dst + 256; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1023 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1024 dst = jmp(dst, dest_addr); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1025 } else { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1026 uint8_t cond = CC_NZ; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1027 switch (inst->extra.cond) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1028 { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1029 case COND_HIGH: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1030 cond = CC_Z; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1031 case COND_LOW_SAME: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1032 dst = mov_rr(dst, FLAG_Z, SCRATCH1, SZ_B); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1033 dst = or_rr(dst, FLAG_C, SCRATCH1, SZ_B); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1034 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1035 case COND_CARRY_CLR: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1036 cond = CC_Z; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1037 case COND_CARRY_SET: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1038 dst = cmp_ir(dst, 0, FLAG_C, SZ_B); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1039 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1040 case COND_NOT_EQ: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1041 cond = CC_Z; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1042 case COND_EQ: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1043 dst = cmp_ir(dst, 0, FLAG_Z, SZ_B); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1044 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1045 case COND_OVERF_CLR: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1046 cond = CC_Z; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1047 case COND_OVERF_SET: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1048 dst = cmp_ir(dst, 0, FLAG_V, SZ_B); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1049 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1050 case COND_PLUS: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1051 cond = CC_Z; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1052 case COND_MINUS: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1053 dst = cmp_ir(dst, 0, FLAG_N, SZ_B); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1054 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1055 case COND_GREATER_EQ: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1056 cond = CC_Z; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1057 case COND_LESS: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1058 dst = cmp_rr(dst, FLAG_N, FLAG_V, SZ_B); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1059 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1060 case COND_GREATER: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1061 cond = CC_Z; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1062 case COND_LESS_EQ: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1063 dst = mov_rr(dst, FLAG_V, SCRATCH1, SZ_B); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1064 dst = xor_rr(dst, FLAG_N, SCRATCH1, SZ_B); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1065 dst = or_rr(dst, FLAG_Z, SCRATCH1, SZ_B); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1066 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1067 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1068 if (!dest_addr) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1069 opts->deferred = defer_address(opts->deferred, after + disp, dst + 2); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1070 //dummy address to be replaced later, make sure it generates a 4-byte displacement |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1071 dest_addr = dst + 256; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1072 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1073 dst = jcc(dst, cond, dest_addr); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1074 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1075 return dst; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1076 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1077 |
53
44e661913a51
Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents:
52
diff
changeset
|
1078 uint8_t * translate_m68k_jmp(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
44e661913a51
Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents:
52
diff
changeset
|
1079 { |
44e661913a51
Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents:
52
diff
changeset
|
1080 uint8_t * dest_addr; |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1081 switch(inst->src.addr_mode) |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1082 { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1083 case MODE_AREG_INDIRECT: |
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1084 dst = cycles(dst, BUS*2); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1085 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1086 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1087 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1088 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, SCRATCH1, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1089 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1090 dst = call(dst, (uint8_t *)m68k_native_addr); |
81
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
1091 dst = jmp_r(dst, SCRATCH1); |
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1092 break; |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1093 case MODE_PC_DISPLACE: |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1094 dst = cycles(dst, 10); |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1095 dest_addr = get_native_address(opts->native_code_map, inst->src.params.regs.displacement + inst->address + 2); |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1096 if (!dest_addr) { |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1097 opts->deferred = defer_address(opts->deferred, inst->src.params.immed, dst + 1); |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1098 //dummy address to be replaced later, make sure it generates a 4-byte displacement |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1099 dest_addr = dst + 256; |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1100 } |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1101 dst = jmp(dst, dest_addr); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1102 break; |
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Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1103 case MODE_ABSOLUTE: |
f80fa1776507
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Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1104 case MODE_ABSOLUTE_SHORT: |
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Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1105 dst = cycles(dst, inst->src.addr_mode == MODE_ABSOLUTE ? 12 : 10); |
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Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1106 dest_addr = get_native_address(opts->native_code_map, inst->src.params.immed); |
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Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1107 if (!dest_addr) { |
f80fa1776507
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Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1108 opts->deferred = defer_address(opts->deferred, inst->src.params.immed, dst + 1); |
53
44e661913a51
Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents:
52
diff
changeset
|
1109 //dummy address to be replaced later, make sure it generates a 4-byte displacement |
44e661913a51
Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents:
52
diff
changeset
|
1110 dest_addr = dst + 256; |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1111 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
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|
1112 dst = jmp(dst, dest_addr); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1113 break; |
76
187c65f40a64
Implement JSR for some addressing modes
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parents:
74
diff
changeset
|
1114 default: |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
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|
1115 printf("address mode %d not yet supported (jmp)\n", inst->src.addr_mode); |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1116 } |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1117 return dst; |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1118 } |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1119 |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1120 uint8_t * translate_m68k_jsr(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1121 { |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
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|
1122 uint8_t * dest_addr; |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1123 uint32_t after; |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1124 switch(inst->src.addr_mode) |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1125 { |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1126 case MODE_AREG_INDIRECT: |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1127 dst = cycles(dst, BUS*2); |
81
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
1128 dst = mov_ir(dst, inst->address + 8, SCRATCH1, SZ_D); |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
1129 dst = push_r(dst, SCRATCH1); |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
1130 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D); |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
1131 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D); |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
1132 dst = call(dst, (char *)m68k_write_long_highfirst); |
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1133 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
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|
1134 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1135 } else { |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1136 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, SCRATCH1, SZ_D); |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1137 } |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1138 dst = call(dst, (uint8_t *)m68k_native_addr); |
81
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
1139 dst = call_r(dst, SCRATCH1); |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
1140 //would add_ir(dst, 8, RSP, SZ_Q) be faster here? |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
1141 dst = pop_r(dst, SCRATCH1); |
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1142 break; |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1143 case MODE_PC_DISPLACE: |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1144 //TODO: Add cycles in the right place relative to pushing the return address on the stack |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1145 dst = cycles(dst, 10); |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1146 dst = mov_ir(dst, inst->address + 8, SCRATCH1, SZ_D); |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1147 dst = push_r(dst, SCRATCH1); |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1148 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D); |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1149 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D); |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1150 dst = call(dst, (char *)m68k_write_long_highfirst); |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1151 dest_addr = get_native_address(opts->native_code_map, inst->src.params.regs.displacement + inst->address + 2); |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1152 if (!dest_addr) { |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1153 opts->deferred = defer_address(opts->deferred, inst->src.params.immed, dst + 1); |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1154 //dummy address to be replaced later, make sure it generates a 4-byte displacement |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1155 dest_addr = dst + 5; |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1156 } |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1157 dst = call(dst, (char *)dest_addr); |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1158 //would add_ir(dst, 8, RSP, SZ_Q) be faster here? |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1159 dst = pop_r(dst, SCRATCH1); |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1160 break; |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1161 case MODE_ABSOLUTE: |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1162 case MODE_ABSOLUTE_SHORT: |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1163 //TODO: Add cycles in the right place relative to pushing the return address on the stack |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1164 dst = cycles(dst, inst->src.addr_mode == MODE_ABSOLUTE ? 12 : 10); |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1165 dst = mov_ir(dst, inst->address + 8, SCRATCH1, SZ_D); |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1166 dst = push_r(dst, SCRATCH1); |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1167 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D); |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1168 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D); |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1169 dst = call(dst, (char *)m68k_write_long_highfirst); |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1170 dest_addr = get_native_address(opts->native_code_map, inst->src.params.immed); |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1171 if (!dest_addr) { |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1172 opts->deferred = defer_address(opts->deferred, inst->src.params.immed, dst + 1); |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1173 //dummy address to be replaced later, make sure it generates a 4-byte displacement |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1174 dest_addr = dst + 5; |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1175 } |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1176 dst = call(dst, (char *)dest_addr); |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1177 //would add_ir(dst, 8, RSP, SZ_Q) be faster here? |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1178 dst = pop_r(dst, SCRATCH1); |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1179 break; |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1180 default: |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1181 printf("address mode %d not yet supported (jsr)\n", inst->src.addr_mode); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1182 } |
53
44e661913a51
Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents:
52
diff
changeset
|
1183 return dst; |
44e661913a51
Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents:
52
diff
changeset
|
1184 } |
44e661913a51
Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents:
52
diff
changeset
|
1185 |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1186 uint8_t * translate_m68k_rts(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1187 { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1188 //TODO: Add cycles |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1189 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1190 dst = add_ir(dst, 4, opts->aregs[7], SZ_D); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1191 dst = call(dst, (char *)m68k_read_long_scratch1); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1192 dst = cmp_rdisp8r(dst, RSP, 8, SCRATCH1, SZ_D); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1193 dst = jcc(dst, CC_NZ, dst+3); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1194 dst = retn(dst); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1195 dst = jmp(dst, (char *)m68k_modified_ret_addr); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1196 return dst; |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1197 } |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1198 |
46
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1199 uint8_t * translate_m68k_dbcc(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1200 { |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1201 //best case duration |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1202 dst = cycles(dst, 10); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1203 uint8_t * skip_loc = NULL; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1204 //TODO: Check if COND_TRUE technically valid here even though |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1205 //it's basically a slow NOP |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1206 if (inst->extra.cond != COND_FALSE) { |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1207 uint8_t cond = CC_NZ; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1208 switch (inst->extra.cond) |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1209 { |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1210 case COND_HIGH: |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1211 cond = CC_Z; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1212 case COND_LOW_SAME: |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1213 dst = mov_rr(dst, FLAG_Z, SCRATCH1, SZ_B); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1214 dst = or_rr(dst, FLAG_C, SCRATCH1, SZ_B); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1215 break; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1216 case COND_CARRY_CLR: |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1217 cond = CC_Z; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1218 case COND_CARRY_SET: |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1219 dst = cmp_ir(dst, 0, FLAG_C, SZ_B); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1220 break; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1221 case COND_NOT_EQ: |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1222 cond = CC_Z; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1223 case COND_EQ: |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1224 dst = cmp_ir(dst, 0, FLAG_Z, SZ_B); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1225 break; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1226 case COND_OVERF_CLR: |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1227 cond = CC_Z; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1228 case COND_OVERF_SET: |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1229 dst = cmp_ir(dst, 0, FLAG_V, SZ_B); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1230 break; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1231 case COND_PLUS: |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1232 cond = CC_Z; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1233 case COND_MINUS: |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1234 dst = cmp_ir(dst, 0, FLAG_N, SZ_B); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1235 break; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1236 case COND_GREATER_EQ: |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1237 cond = CC_Z; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1238 case COND_LESS: |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1239 dst = cmp_rr(dst, FLAG_N, FLAG_V, SZ_B); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1240 break; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1241 case COND_GREATER: |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1242 cond = CC_Z; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1243 case COND_LESS_EQ: |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1244 dst = mov_rr(dst, FLAG_V, SCRATCH1, SZ_B); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1245 dst = xor_rr(dst, FLAG_N, SCRATCH1, SZ_B); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1246 dst = or_rr(dst, FLAG_Z, SCRATCH1, SZ_B); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1247 break; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1248 } |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1249 skip_loc = dst + 1; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1250 dst = jcc(dst, cond, dst + 2); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1251 } |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1252 if (opts->dregs[inst->dst.params.regs.pri] >= 0) { |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1253 dst = sub_ir(dst, 1, opts->dregs[inst->dst.params.regs.pri], SZ_W); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1254 dst = cmp_ir(dst, -1, opts->dregs[inst->dst.params.regs.pri], SZ_W); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1255 } else { |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1256 dst = sub_irdisp8(dst, 1, CONTEXT, offsetof(m68k_context, dregs) + 4 * inst->dst.params.regs.pri, SZ_W); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1257 dst = cmp_irdisp8(dst, -1, CONTEXT, offsetof(m68k_context, dregs) + 4 * inst->dst.params.regs.pri, SZ_W); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1258 } |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1259 uint8_t *loop_end_loc = dst+1; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1260 dst = jcc(dst, CC_Z, dst+2); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1261 uint32_t after = inst->address + 2; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1262 uint8_t * dest_addr = get_native_address(opts->native_code_map, after + inst->src.params.immed); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1263 if (!dest_addr) { |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1264 opts->deferred = defer_address(opts->deferred, after + inst->src.params.immed, dst + 1); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1265 //dummy address to be replaced later, make sure it generates a 4-byte displacement |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1266 dest_addr = dst + 256; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1267 } |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1268 dst = jmp(dst, dest_addr); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1269 *loop_end_loc = dst - (loop_end_loc+1); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1270 if (skip_loc) { |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1271 dst = cycles(dst, 2); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1272 *skip_loc = dst - (skip_loc+1); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1273 dst = cycles(dst, 2); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1274 } else { |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1275 dst = cycles(dst, 4); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1276 } |
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
1277 return dst; |
46
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1278 } |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1279 |
78
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
1280 uint8_t * translate_m68k_link(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
1281 { |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
1282 int8_t reg = native_reg(&(inst->src), opts); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
1283 //compensate for displacement word |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
1284 dst = cycles(dst, BUS); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
1285 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
1286 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
1287 if (reg >= 0) { |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
1288 dst = mov_rr(dst, reg, SCRATCH1, SZ_D); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
1289 } else { |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
1290 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
1291 } |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
1292 dst = call(dst, (char *)m68k_write_long_highfirst); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
1293 if (reg >= 0) { |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
1294 dst = mov_rr(dst, opts->aregs[7], reg, SZ_D); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
1295 } else { |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
1296 dst = mov_rrdisp8(dst, opts->aregs[7], CONTEXT, reg_offset(&(inst->src)), SZ_D); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
1297 } |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
1298 dst = add_ir(dst, inst->dst.params.immed, opts->aregs[7], SZ_D); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
1299 //prefetch |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
1300 dst = cycles(dst, BUS); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
1301 return dst; |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
1302 } |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
1303 |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1304 typedef uint8_t * (*shift_ir_t)(uint8_t * out, uint8_t val, uint8_t dst, uint8_t size); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1305 typedef uint8_t * (*shift_irdisp8_t)(uint8_t * out, uint8_t val, uint8_t dst_base, int8_t disp, uint8_t size); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1306 typedef uint8_t * (*shift_clr_t)(uint8_t * out, uint8_t dst, uint8_t size); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1307 typedef uint8_t * (*shift_clrdisp8_t)(uint8_t * out, uint8_t dst_base, int8_t disp, uint8_t size); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1308 |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1309 uint8_t * translate_shift(uint8_t * dst, m68kinst * inst, x86_ea *src_op, x86_ea * dst_op, x86_68k_options * opts, shift_ir_t shift_ir, shift_irdisp8_t shift_irdisp8, shift_clr_t shift_clr, shift_clrdisp8_t shift_clrdisp8, shift_ir_t special, shift_irdisp8_t special_disp8) |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1310 { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1311 uint8_t * end_off = NULL; |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1312 if (inst->src.addr_mode == MODE_UNUSED) { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1313 dst = cycles(dst, BUS); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1314 //Memory shift |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1315 dst = shift_ir(dst, 1, dst_op->base, SZ_W); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1316 } else { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1317 dst = cycles(dst, inst->extra.size == OPSIZE_LONG ? 8 : 6); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1318 if (src_op->mode == MODE_IMMED) { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1319 if (dst_op->mode == MODE_REG_DIRECT) { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1320 dst = shift_ir(dst, src_op->disp, dst_op->base, inst->extra.size); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1321 } else { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1322 dst = shift_irdisp8(dst, src_op->disp, dst_op->base, dst_op->disp, inst->extra.size); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1323 } |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1324 } else { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1325 if (src_op->base != RCX) { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1326 if (src_op->mode == MODE_REG_DIRECT) { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1327 dst = mov_rr(dst, src_op->base, RCX, SZ_B); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1328 } else { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1329 dst = mov_rdisp8r(dst, src_op->base, src_op->disp, RCX, SZ_B); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1330 } |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1331 } |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1332 dst = and_ir(dst, 63, RCX, SZ_D); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1333 //add 2 cycles for every bit shifted |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1334 dst = add_rr(dst, RCX, CYCLES, SZ_D); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1335 dst = add_rr(dst, RCX, CYCLES, SZ_D); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1336 //x86 shifts modulo 32 for operand sizes less than 64-bits |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1337 //but M68K shifts modulo 64, so we need to check for large shifts here |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1338 dst = cmp_ir(dst, 32, RCX, SZ_B); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1339 uint8_t * norm_shift_off = dst + 1; |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1340 dst = jcc(dst, CC_L, dst+2); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1341 if (special) { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1342 if (inst->extra.size == OPSIZE_LONG) { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1343 uint8_t * neq_32_off = dst + 1; |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1344 dst = jcc(dst, CC_NZ, dst+2); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1345 |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1346 //set the carry bit to the lsb |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1347 if (dst_op->mode == MODE_REG_DIRECT) { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1348 dst = special(dst, 1, dst_op->base, SZ_D); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1349 } else { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1350 dst = special_disp8(dst, 1, dst_op->base, dst_op->disp, SZ_D); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1351 } |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1352 dst = setcc_r(dst, CC_C, FLAG_C); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1353 dst = jmp(dst, dst+4); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1354 *neq_32_off = dst - (neq_32_off+1); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1355 } |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1356 dst = mov_ir(dst, 0, FLAG_C, SZ_B); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1357 dst = mov_ir(dst, 1, FLAG_Z, SZ_B); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1358 dst = mov_ir(dst, 0, FLAG_N, SZ_B); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1359 if (dst_op->mode == MODE_REG_DIRECT) { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1360 dst = xor_rr(dst, dst_op->base, dst_op->base, inst->extra.size); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1361 } else { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1362 dst = mov_irdisp8(dst, 0, dst_op->base, dst_op->disp, inst->extra.size); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1363 } |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1364 } else { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1365 if (dst_op->mode == MODE_REG_DIRECT) { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1366 dst = shift_ir(dst, 31, dst_op->base, inst->extra.size); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1367 dst = shift_ir(dst, 1, dst_op->base, inst->extra.size); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1368 } else { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1369 dst = shift_irdisp8(dst, 31, dst_op->base, dst_op->disp, inst->extra.size); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1370 dst = shift_irdisp8(dst, 1, dst_op->base, dst_op->disp, inst->extra.size); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1371 } |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1372 |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1373 } |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1374 end_off = dst+1; |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1375 dst = jmp(dst, dst+2); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1376 *norm_shift_off = dst - (norm_shift_off+1); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1377 if (dst_op->mode == MODE_REG_DIRECT) { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1378 dst = shift_clr(dst, dst_op->base, inst->extra.size); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1379 } else { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1380 dst = shift_clrdisp8(dst, dst_op->base, dst_op->disp, inst->extra.size); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1381 } |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1382 |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1383 } |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1384 |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1385 } |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1386 if (!special && end_off) { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1387 *end_off = dst - (end_off + 1); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1388 } |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1389 dst = setcc_r(dst, CC_C, FLAG_C); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1390 dst = setcc_r(dst, CC_Z, FLAG_Z); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1391 dst = setcc_r(dst, CC_S, FLAG_N); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1392 if (special && end_off) { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1393 *end_off = dst - (end_off + 1); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1394 } |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1395 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1396 //set X flag to same as C flag |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1397 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1398 if (inst->src.addr_mode == MODE_UNUSED) { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1399 dst = m68k_save_result(inst, dst, opts); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1400 } |
66 | 1401 return dst; |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1402 } |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1403 |
73
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1404 #define BIT_SUPERVISOR 5 |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1405 |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1406 uint8_t * translate_m68k(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1407 { |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1408 uint8_t * end_off; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1409 map_native_address(opts->native_code_map, inst->address, dst); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1410 if (inst->op == M68K_MOVE) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1411 return translate_m68k_move(dst, inst, opts); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1412 } else if(inst->op == M68K_LEA) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1413 return translate_m68k_lea(dst, inst, opts); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1414 } else if(inst->op == M68K_BSR) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1415 return translate_m68k_bsr(dst, inst, opts); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1416 } else if(inst->op == M68K_BCC) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1417 return translate_m68k_bcc(dst, inst, opts); |
53
44e661913a51
Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents:
52
diff
changeset
|
1418 } else if(inst->op == M68K_JMP) { |
44e661913a51
Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents:
52
diff
changeset
|
1419 return translate_m68k_jmp(dst, inst, opts); |
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1420 } else if(inst->op == M68K_JSR) { |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1421 return translate_m68k_jsr(dst, inst, opts); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1422 } else if(inst->op == M68K_RTS) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1423 return translate_m68k_rts(dst, inst, opts); |
46
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1424 } else if(inst->op == M68K_DBCC) { |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1425 return translate_m68k_dbcc(dst, inst, opts); |
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
1426 } else if(inst->op == M68K_CLR) { |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
1427 return translate_m68k_clr(dst, inst, opts); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1428 } else if(inst->op == M68K_MOVEM) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1429 return translate_m68k_movem(dst, inst, opts); |
78
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
1430 } else if(inst->op == M68K_LINK) { |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
1431 return translate_m68k_link(dst, inst, opts); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1432 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1433 x86_ea src_op, dst_op; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1434 if (inst->src.addr_mode != MODE_UNUSED) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1435 dst = translate_m68k_src(inst, &src_op, dst, opts); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1436 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1437 if (inst->dst.addr_mode != MODE_UNUSED) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1438 dst = translate_m68k_dst(inst, &dst_op, dst, opts); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1439 } |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1440 switch(inst->op) |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1441 { |
70
cebd0b5ac7f0
Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents:
67
diff
changeset
|
1442 //case M68K_ABCD: |
cebd0b5ac7f0
Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents:
67
diff
changeset
|
1443 // break; |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1444 case M68K_ADD: |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1445 dst = cycles(dst, BUS); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1446 if (src_op.mode == MODE_REG_DIRECT) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1447 if (dst_op.mode == MODE_REG_DIRECT) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1448 dst = add_rr(dst, src_op.base, dst_op.base, inst->extra.size); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1449 } else { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1450 dst = add_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1451 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1452 } else if (src_op.mode == MODE_REG_DISPLACE8) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1453 dst = add_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1454 } else { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1455 if (dst_op.mode == MODE_REG_DIRECT) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1456 dst = add_ir(dst, src_op.disp, dst_op.base, inst->extra.size); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1457 } else { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1458 dst = add_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1459 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1460 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1461 dst = setcc_r(dst, CC_C, FLAG_C); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1462 dst = setcc_r(dst, CC_Z, FLAG_Z); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1463 dst = setcc_r(dst, CC_S, FLAG_N); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1464 dst = setcc_r(dst, CC_O, FLAG_V); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1465 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B); |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1466 dst = m68k_save_result(inst, dst, opts); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1467 break; |
70
cebd0b5ac7f0
Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents:
67
diff
changeset
|
1468 //case M68K_ADDX: |
cebd0b5ac7f0
Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents:
67
diff
changeset
|
1469 // break; |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1470 case M68K_AND: |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1471 dst = cycles(dst, BUS); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1472 if (src_op.mode == MODE_REG_DIRECT) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1473 if (dst_op.mode == MODE_REG_DIRECT) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1474 dst = and_rr(dst, src_op.base, dst_op.base, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1475 } else { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1476 dst = and_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1477 } |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1478 } else if (src_op.mode == MODE_REG_DISPLACE8) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1479 dst = and_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1480 } else { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1481 if (dst_op.mode == MODE_REG_DIRECT) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1482 dst = and_ir(dst, src_op.disp, dst_op.base, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1483 } else { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1484 dst = and_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1485 } |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1486 } |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1487 dst = mov_ir(dst, 0, FLAG_C, SZ_B); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1488 dst = setcc_r(dst, CC_Z, FLAG_Z); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1489 dst = setcc_r(dst, CC_S, FLAG_N); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1490 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1491 dst = m68k_save_result(inst, dst, opts); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1492 break; |
73
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1493 case M68K_ANDI_CCR: |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1494 case M68K_ANDI_SR: |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1495 dst = cycles(dst, 20); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1496 //TODO: If ANDI to SR, trap if not in supervisor mode |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1497 if (!(inst->src.params.immed & 0x1)) { |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1498 dst = mov_ir(dst, 0, FLAG_C, SZ_B); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1499 } |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1500 if (!(inst->src.params.immed & 0x2)) { |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1501 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1502 } |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1503 if (!(inst->src.params.immed & 0x4)) { |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1504 dst = mov_ir(dst, 0, FLAG_Z, SZ_B); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1505 } |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1506 if (!(inst->src.params.immed & 0x8)) { |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1507 dst = mov_ir(dst, 0, FLAG_N, SZ_B); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1508 } |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1509 if (!(inst->src.params.immed & 0x10)) { |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1510 dst = mov_irind(dst, 0, CONTEXT, SZ_B); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1511 } |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1512 if (inst->op == M68K_ANDI_SR) { |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1513 dst = and_irdisp8(dst, inst->src.params.immed >> 8, CONTEXT, offsetof(m68k_context, status), SZ_B); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1514 if (!((inst->src.params.immed >> 8) & (1 << BIT_SUPERVISOR))) { |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1515 //leave supervisor mode |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1516 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_B); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1517 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, opts->aregs[7], SZ_B); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1518 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_B); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1519 } |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1520 } |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1521 break; |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1522 case M68K_ASL: |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1523 case M68K_LSL: |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1524 dst = translate_shift(dst, inst, &src_op, &dst_op, opts, shl_ir, shl_irdisp8, shl_clr, shl_clrdisp8, shr_ir, shr_irdisp8); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1525 break; |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1526 case M68K_ASR: |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1527 dst = translate_shift(dst, inst, &src_op, &dst_op, opts, sar_ir, sar_irdisp8, sar_clr, sar_clrdisp8, NULL, NULL); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1528 break; |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1529 case M68K_LSR: |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1530 dst = translate_shift(dst, inst, &src_op, &dst_op, opts, shr_ir, shr_irdisp8, shr_clr, shr_clrdisp8, shl_ir, shl_irdisp8); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1531 break; |
70
cebd0b5ac7f0
Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents:
67
diff
changeset
|
1532 /*case M68K_BCHG: |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1533 case M68K_BCLR: |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1534 case M68K_BSET: |
70
cebd0b5ac7f0
Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents:
67
diff
changeset
|
1535 break;*/ |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1536 case M68K_BTST: |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1537 dst = cycles(dst, inst->extra.size == OPSIZE_BYTE ? 4 : 6); |
67 | 1538 if (src_op.mode == MODE_IMMED) { |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1539 if (inst->extra.size == OPSIZE_BYTE) { |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1540 src_op.disp &= 0x7; |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1541 } |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1542 if (dst_op.mode == MODE_REG_DIRECT) { |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1543 dst = bt_ir(dst, src_op.disp, dst_op.base, SZ_D); |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1544 } else { |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1545 dst = bt_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, SZ_D); |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1546 } |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1547 } else { |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1548 if (src_op.mode == MODE_REG_DISPLACE8) { |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1549 if (dst_op.base == SCRATCH1) { |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1550 dst = push_r(dst, SCRATCH2); |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1551 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH2, SZ_B); |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1552 src_op.base = SCRATCH1; |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1553 } else { |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1554 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_B); |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1555 src_op.base = SCRATCH1; |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1556 } |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1557 } |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1558 if (inst->extra.size == OPSIZE_BYTE) { |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1559 dst = and_ir(dst, 0x7, src_op.base, SZ_B); |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1560 } |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1561 if (dst_op.mode == MODE_REG_DIRECT) { |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1562 dst = bt_rr(dst, src_op.base, dst_op.base, SZ_D); |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1563 } else { |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1564 dst = bt_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, SZ_D); |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1565 } |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1566 } |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1567 //x86 sets the carry flag to the value of the bit tested |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1568 //68K sets the zero flag to the complement of the bit tested |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1569 dst = setcc_r(dst, CC_NC, FLAG_Z); |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1570 if (src_op.base == SCRATCH2) { |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1571 dst = pop_r(dst, SCRATCH2); |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1572 } |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1573 break; |
70
cebd0b5ac7f0
Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents:
67
diff
changeset
|
1574 /*case M68K_CHK: |
cebd0b5ac7f0
Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents:
67
diff
changeset
|
1575 break;*/ |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1576 case M68K_CMP: |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1577 dst = cycles(dst, BUS); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1578 if (src_op.mode == MODE_REG_DIRECT) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1579 if (dst_op.mode == MODE_REG_DIRECT) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1580 dst = cmp_rr(dst, src_op.base, dst_op.base, inst->extra.size); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1581 } else { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1582 dst = cmp_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1583 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1584 } else if (src_op.mode == MODE_REG_DISPLACE8) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1585 dst = cmp_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1586 } else { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1587 if (dst_op.mode == MODE_REG_DIRECT) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1588 dst = cmp_ir(dst, src_op.disp, dst_op.base, inst->extra.size); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1589 } else { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1590 dst = cmp_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1591 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1592 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1593 dst = setcc_r(dst, CC_C, FLAG_C); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1594 dst = setcc_r(dst, CC_Z, FLAG_Z); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1595 dst = setcc_r(dst, CC_S, FLAG_N); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1596 dst = setcc_r(dst, CC_O, FLAG_V); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1597 break; |
70
cebd0b5ac7f0
Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents:
67
diff
changeset
|
1598 /*case M68K_DIVS: |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1599 case M68K_DIVU: |
70
cebd0b5ac7f0
Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents:
67
diff
changeset
|
1600 break;*/ |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1601 case M68K_EOR: |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1602 dst = cycles(dst, BUS); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1603 if (src_op.mode == MODE_REG_DIRECT) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1604 if (dst_op.mode == MODE_REG_DIRECT) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1605 dst = xor_rr(dst, src_op.base, dst_op.base, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1606 } else { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1607 dst = xor_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1608 } |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1609 } else if (src_op.mode == MODE_REG_DISPLACE8) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1610 dst = xor_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1611 } else { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1612 if (dst_op.mode == MODE_REG_DIRECT) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1613 dst = xor_ir(dst, src_op.disp, dst_op.base, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1614 } else { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1615 dst = xor_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1616 } |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1617 } |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1618 dst = mov_ir(dst, 0, FLAG_C, SZ_B); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1619 dst = setcc_r(dst, CC_Z, FLAG_Z); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1620 dst = setcc_r(dst, CC_S, FLAG_N); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1621 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1622 dst = m68k_save_result(inst, dst, opts); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1623 break; |
70
cebd0b5ac7f0
Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents:
67
diff
changeset
|
1624 /*case M68K_EORI_CCR: |
cebd0b5ac7f0
Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents:
67
diff
changeset
|
1625 case M68K_EORI_SR:*/ |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1626 case M68K_EXG: |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1627 dst = cycles(dst, 6); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1628 if (dst_op.mode == MODE_REG_DIRECT) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1629 dst = mov_rr(dst, dst_op.base, SCRATCH2, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1630 if (src_op.mode == MODE_REG_DIRECT) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1631 dst = mov_rr(dst, src_op.base, dst_op.base, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1632 dst = mov_rr(dst, SCRATCH2, src_op.base, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1633 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1634 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1635 dst = mov_rrdisp8(dst, SCRATCH2, src_op.base, src_op.disp, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1636 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1637 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1638 dst = mov_rdisp8r(dst, dst_op.base, dst_op.disp, SCRATCH2, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1639 if (src_op.mode == MODE_REG_DIRECT) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1640 dst = mov_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1641 dst = mov_rr(dst, SCRATCH2, src_op.base, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1642 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1643 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1644 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1645 dst = mov_rrdisp8(dst, SCRATCH2, src_op.base, src_op.disp, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1646 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1647 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1648 break; |
73
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1649 //case M68K_EXT: |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1650 // break; |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1651 case M68K_ILLEGAL: |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1652 dst = call(dst, (uint8_t *)m68k_save_context); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1653 dst = mov_rr(dst, CONTEXT, RDI, SZ_Q); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1654 dst = call(dst, (uint8_t *)print_regs_exit); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1655 break; |
70
cebd0b5ac7f0
Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents:
67
diff
changeset
|
1656 /*case M68K_JSR: |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1657 case M68K_LEA: |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1658 case M68K_MOVE_FROM_SR: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1659 break;*/ |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1660 case M68K_MOVE_CCR: |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1661 case M68K_MOVE_SR: |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1662 //TODO: Privilege check for MOVE to SR |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1663 if (src_op.mode == MODE_IMMED) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1664 dst = mov_ir(dst, src_op.disp & 0x1, FLAG_C, SZ_B); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1665 dst = mov_ir(dst, (src_op.disp >> 1) & 0x1, FLAG_V, SZ_B); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1666 dst = mov_ir(dst, (src_op.disp >> 2) & 0x1, FLAG_Z, SZ_B); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1667 dst = mov_ir(dst, (src_op.disp >> 3) & 0x1, FLAG_N, SZ_B); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1668 dst = mov_irind(dst, (src_op.disp >> 4) & 0x1, CONTEXT, SZ_B); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1669 if (inst->op == M68K_MOVE_SR) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1670 dst = mov_irdisp8(dst, (src_op.disp >> 8), CONTEXT, offsetof(m68k_context, status), SZ_B); |
73
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1671 if (!((inst->src.params.immed >> 8) & (1 << BIT_SUPERVISOR))) { |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1672 //leave supervisor mode |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1673 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1674 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, opts->aregs[7], SZ_D); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1675 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_D); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1676 } |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1677 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1678 dst = cycles(dst, 12); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1679 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1680 if (src_op.mode == MODE_REG_DIRECT) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1681 dst = mov_rr(dst, src_op.base, FLAG_C, SZ_B); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1682 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1683 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, FLAG_C, SZ_B); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1684 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1685 dst = mov_rr(dst, FLAG_C, FLAG_V, SZ_B); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1686 dst = and_ir(dst, 1, FLAG_C, SZ_B); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1687 dst = shr_ir(dst, 1, FLAG_V, SZ_B); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1688 dst = mov_rr(dst, FLAG_V, FLAG_Z, SZ_B); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1689 dst = and_ir(dst, 1, FLAG_V, SZ_B); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1690 dst = shr_ir(dst, 1, FLAG_Z, SZ_B); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1691 dst = mov_rr(dst, FLAG_Z, FLAG_N, SZ_B); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1692 dst = and_ir(dst, 1, FLAG_Z, SZ_B); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1693 dst = shr_ir(dst, 1, FLAG_N, SZ_B); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1694 dst = mov_rr(dst, 1, SCRATCH2, SZ_B); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1695 dst = shr_ir(dst, 1, SCRATCH2, SZ_B); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1696 dst = and_ir(dst, 1, SCRATCH2, SZ_B); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1697 dst = mov_rrind(dst, SCRATCH2, CONTEXT, SZ_B); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1698 dst = cycles(dst, 12); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1699 if (inst->op == M68K_MOVE_SR) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1700 if (src_op.mode == MODE_REG_DIRECT) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1701 dst = mov_rr(dst, src_op.base, SCRATCH2, SZ_W); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1702 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1703 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH2, SZ_W); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1704 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1705 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1706 dst = shr_ir(dst, 8, SCRATCH2, SZ_B); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1707 dst = mov_rrdisp8(dst, SCRATCH2, CONTEXT, offsetof(m68k_context, status), SZ_B); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1708 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1709 break; |
73
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1710 case M68K_MOVE_USP: |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1711 dst = cycles(dst, BUS); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1712 //TODO: Trap if not in supervisor mode |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1713 //dst = bt_irdisp8(dst, BIT_SUPERVISOR, CONTEXT, offsetof(m68k_context, status), SZ_B); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1714 if (inst->src.addr_mode == MODE_UNUSED) { |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1715 if (dst_op.mode == MODE_REG_DIRECT) { |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1716 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, dst_op.base, SZ_D); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1717 } else { |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1718 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SCRATCH1, SZ_D); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1719 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, SZ_D); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1720 } |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1721 } else { |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1722 if (src_op.mode == MODE_REG_DIRECT) { |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1723 dst = mov_rrdisp8(dst, src_op.base, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_D); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1724 } else { |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1725 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_D); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1726 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_D); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1727 } |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1728 } |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1729 break; |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1730 /*case M68K_MOVEP: |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1731 case M68K_MULS: |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1732 case M68K_MULU: |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1733 case M68K_NBCD: |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1734 case M68K_NEG: |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1735 case M68K_NEGX: |
70
cebd0b5ac7f0
Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents:
67
diff
changeset
|
1736 break;*/ |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1737 case M68K_NOP: |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1738 dst = cycles(dst, BUS); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1739 break; |
73
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1740 //case M68K_NOT: |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1741 // break; |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1742 case M68K_OR: |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1743 dst = cycles(dst, BUS); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1744 if (src_op.mode == MODE_REG_DIRECT) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1745 if (dst_op.mode == MODE_REG_DIRECT) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1746 dst = or_rr(dst, src_op.base, dst_op.base, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1747 } else { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1748 dst = or_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1749 } |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1750 } else if (src_op.mode == MODE_REG_DISPLACE8) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1751 dst = or_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1752 } else { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1753 if (dst_op.mode == MODE_REG_DIRECT) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1754 dst = or_ir(dst, src_op.disp, dst_op.base, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1755 } else { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1756 dst = or_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1757 } |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1758 } |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1759 dst = mov_ir(dst, 0, FLAG_C, SZ_B); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1760 dst = setcc_r(dst, CC_Z, FLAG_Z); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1761 dst = setcc_r(dst, CC_S, FLAG_N); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1762 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1763 dst = m68k_save_result(inst, dst, opts); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1764 break; |
70
cebd0b5ac7f0
Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents:
67
diff
changeset
|
1765 /*case M68K_ORI_CCR: |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1766 case M68K_ORI_SR: |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1767 case M68K_PEA: |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1768 case M68K_RESET: |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1769 case M68K_ROL: |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1770 case M68K_ROR: |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1771 case M68K_ROXL: |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1772 case M68K_ROXR: |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1773 case M68K_RTE: |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1774 case M68K_RTR: |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1775 case M68K_SBCD: |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1776 case M68K_SCC: |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1777 case M68K_STOP: |
70
cebd0b5ac7f0
Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents:
67
diff
changeset
|
1778 break;*/ |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1779 case M68K_SUB: |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1780 dst = cycles(dst, BUS); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1781 if (src_op.mode == MODE_REG_DIRECT) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1782 if (dst_op.mode == MODE_REG_DIRECT) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1783 dst = sub_rr(dst, src_op.base, dst_op.base, inst->extra.size); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1784 } else { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1785 dst = sub_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1786 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1787 } else if (src_op.mode == MODE_REG_DISPLACE8) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1788 dst = sub_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1789 } else { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1790 if (dst_op.mode == MODE_REG_DIRECT) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1791 dst = sub_ir(dst, src_op.disp, dst_op.base, inst->extra.size); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1792 } else { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1793 dst = sub_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1794 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1795 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1796 dst = setcc_r(dst, CC_C, FLAG_C); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1797 dst = setcc_r(dst, CC_Z, FLAG_Z); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1798 dst = setcc_r(dst, CC_S, FLAG_N); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1799 dst = setcc_r(dst, CC_O, FLAG_V); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1800 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B); |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1801 dst = m68k_save_result(inst, dst, opts); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1802 break; |
70
cebd0b5ac7f0
Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents:
67
diff
changeset
|
1803 //case M68K_SUBX: |
cebd0b5ac7f0
Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents:
67
diff
changeset
|
1804 // break; |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1805 case M68K_SWAP: |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1806 dst = cycles(dst, BUS); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1807 if (src_op.mode == MODE_REG_DIRECT) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1808 dst = rol_ir(dst, 16, src_op.base, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1809 } else{ |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1810 dst = rol_irdisp8(dst, 16, src_op.base, src_op.disp, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1811 } |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1812 dst = mov_ir(dst, 0, FLAG_C, SZ_B); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1813 dst = setcc_r(dst, CC_Z, FLAG_Z); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1814 dst = setcc_r(dst, CC_S, FLAG_N); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1815 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1816 break; |
70
cebd0b5ac7f0
Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents:
67
diff
changeset
|
1817 /*case M68K_TAS: |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1818 case M68K_TRAP: |
70
cebd0b5ac7f0
Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents:
67
diff
changeset
|
1819 case M68K_TRAPV:*/ |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1820 case M68K_TST: |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1821 dst = cycles(dst, BUS); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1822 if (src_op.mode == MODE_REG_DIRECT) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1823 dst = cmp_ir(dst, 0, src_op.base, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1824 } else { //M68000 doesn't support immedate operand for tst, so this must be MODE_REG_DISPLACE8 |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1825 dst = cmp_irdisp8(dst, 0, src_op.base, src_op.disp, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1826 } |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1827 dst = setcc_r(dst, CC_C, FLAG_C); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1828 dst = setcc_r(dst, CC_Z, FLAG_Z); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1829 dst = setcc_r(dst, CC_S, FLAG_N); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1830 dst = setcc_r(dst, CC_O, FLAG_V); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1831 break; |
78
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
1832 case M68K_UNLK: |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
1833 dst = cycles(dst, BUS); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
1834 if (dst_op.mode == MODE_REG_DIRECT) { |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
1835 dst = mov_rr(dst, dst_op.base, opts->aregs[7], SZ_D); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
1836 } else { |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
1837 dst = mov_rdisp8r(dst, dst_op.base, dst_op.disp, opts->aregs[7], SZ_D); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
1838 } |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
1839 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
1840 dst = call(dst, (uint8_t *)m68k_read_long_scratch1); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
1841 if (dst_op.mode == MODE_REG_DIRECT) { |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
1842 dst = mov_rr(dst, SCRATCH1, dst_op.base, SZ_D); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
1843 } else { |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
1844 dst = mov_rdisp8r(dst, SCRATCH1, dst_op.base, dst_op.disp, SZ_D); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
1845 } |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
1846 break; |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
1847 /*case M68K_INVALID: |
70
cebd0b5ac7f0
Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents:
67
diff
changeset
|
1848 break;*/ |
cebd0b5ac7f0
Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents:
67
diff
changeset
|
1849 default: |
cebd0b5ac7f0
Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents:
67
diff
changeset
|
1850 printf("instruction %d not yet implemented\n", inst->op); |
cebd0b5ac7f0
Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents:
67
diff
changeset
|
1851 exit(1); |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1852 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1853 return dst; |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1854 } |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1855 |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1856 uint8_t * translate_m68k_stream(uint8_t * dst, uint8_t * dst_end, uint32_t address, m68k_context * context) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1857 { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1858 m68kinst instbuf; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1859 x86_68k_options * opts = context->options; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1860 char disbuf[1024]; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1861 uint16_t *encoded = context->mem_pointers[0] + address/2, *next; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1862 do { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1863 do { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1864 if (dst_end-dst < 128) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1865 puts("out of code memory"); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1866 exit(1); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1867 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1868 next = m68k_decode(encoded, &instbuf, address); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1869 address += (next-encoded)*2; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1870 encoded = next; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1871 m68k_disasm(&instbuf, disbuf); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1872 printf("%X: %s\n", instbuf.address, disbuf); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1873 dst = translate_m68k(dst, &instbuf, opts); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1874 } while(instbuf.op != M68K_ILLEGAL && instbuf.op != M68K_RTS && instbuf.op != M68K_RTE && !(instbuf.op == M68K_BCC && instbuf.extra.cond == COND_TRUE) && instbuf.op != M68K_JMP); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1875 process_deferred(opts); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1876 if (opts->deferred) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1877 address = opts->deferred->address; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1878 encoded = context->mem_pointers[0] + address/2; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1879 } else { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1880 encoded = NULL; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1881 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1882 } while(encoded != NULL); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1883 return dst; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1884 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1885 |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1886 void start_68k_context(m68k_context * context, uint32_t address) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1887 { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1888 uint8_t * addr = get_native_address(context->native_code_map, address); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1889 m68k_start_context(addr, context); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1890 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1891 |
19
4717146a7606
Initial support for M68k reset vector, rather than starting at an arbitrary address
Mike Pavone <pavone@retrodev.com>
parents:
18
diff
changeset
|
1892 void m68k_reset(m68k_context * context) |
4717146a7606
Initial support for M68k reset vector, rather than starting at an arbitrary address
Mike Pavone <pavone@retrodev.com>
parents:
18
diff
changeset
|
1893 { |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1894 //TODO: Make this actually use the normal read functions |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1895 context->aregs[7] = context->mem_pointers[0][0] << 16 | context->mem_pointers[0][1]; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1896 uint32_t address = context->mem_pointers[0][2] << 16 | context->mem_pointers[0][3]; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1897 start_68k_context(context, address); |
19
4717146a7606
Initial support for M68k reset vector, rather than starting at an arbitrary address
Mike Pavone <pavone@retrodev.com>
parents:
18
diff
changeset
|
1898 } |
4717146a7606
Initial support for M68k reset vector, rather than starting at an arbitrary address
Mike Pavone <pavone@retrodev.com>
parents:
18
diff
changeset
|
1899 |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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1900 void init_x86_68k_opts(x86_68k_options * opts) |
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1901 { |
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1902 opts->flags = 0; |
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1903 for (int i = 0; i < 8; i++) |
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1904 opts->dregs[i] = opts->aregs[i] = -1; |
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1905 opts->dregs[0] = R10; |
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1906 opts->dregs[1] = R11; |
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1907 opts->dregs[2] = R12; |
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1908 opts->aregs[0] = R13; |
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1909 opts->aregs[1] = R14; |
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1910 opts->aregs[7] = R15; |
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1911 opts->native_code_map = malloc(sizeof(native_map_slot) * NATIVE_MAP_CHUNKS); |
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1912 memset(opts->native_code_map, 0, sizeof(native_map_slot) * NATIVE_MAP_CHUNKS); |
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1913 opts->deferred = NULL; |
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1914 } |
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1915 |
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1916 void init_68k_context(m68k_context * context, native_map_slot * native_code_map, void * opts) |
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1917 { |
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1918 memset(context, 0, sizeof(m68k_context)); |
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1919 context->native_code_map = native_code_map; |
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1920 context->options = opts; |
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1921 } |
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1922 |