Mercurial > repos > blastem
annotate backend_x86.c @ 2305:6aca1734d573
Merge
author | Michael Pavone <pavone@retrodev.com> |
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date | Wed, 15 Mar 2023 19:28:11 -0700 |
parents | 6677afe78a6f |
children | 8990c2f431b1 |
rev | line source |
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567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
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1 #include "backend.h" |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
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2 #include "gen_x86.h" |
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3 #include <string.h> |
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4 |
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Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
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5 void cycles(cpu_options *opts, uint32_t num) |
8e395210f50f
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6 { |
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7 if (opts->limit < 0) { |
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8 sub_ir(&opts->code, num*opts->clock_divider, opts->cycles, SZ_D); |
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9 } else { |
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10 add_ir(&opts->code, num*opts->clock_divider, opts->cycles, SZ_D); |
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11 } |
567
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Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
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12 } |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
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13 |
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Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
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14 void check_cycles_int(cpu_options *opts, uint32_t address) |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
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15 { |
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16 code_info *code = &opts->code; |
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Fix a subtle bug in interrupt handling introduced with the move to a single cycle register in the Z80 core. Fixes regression in Puyo Puyo 2
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17 uint8_t cc; |
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18 if (opts->limit < 0) { |
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Fix a subtle bug in interrupt handling introduced with the move to a single cycle register in the Z80 core. Fixes regression in Puyo Puyo 2
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19 cmp_ir(code, 1, opts->cycles, SZ_D); |
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20 cc = CC_NS; |
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21 } else { |
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22 cmp_rr(code, opts->cycles, opts->limit, SZ_D); |
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23 cc = CC_A; |
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24 } |
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Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
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25 code_ptr jmp_off = code->cur+1; |
1109
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Fix a subtle bug in interrupt handling introduced with the move to a single cycle register in the Z80 core. Fixes regression in Puyo Puyo 2
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26 jcc(code, cc, jmp_off+1); |
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Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
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27 mov_ir(code, address, opts->scratch1, SZ_D); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
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28 call(code, opts->handle_cycle_limit_int); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
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29 *jmp_off = code->cur - (jmp_off+1); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
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30 } |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
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31 |
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32 void retranslate_calc(cpu_options *opts) |
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33 { |
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34 code_info *code = &opts->code; |
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35 code_info tmp = *code; |
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36 uint8_t cc; |
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37 if (opts->limit < 0) { |
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38 cmp_ir(code, 1, opts->cycles, SZ_D); |
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39 cc = CC_NS; |
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40 } else { |
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41 cmp_rr(code, opts->cycles, opts->limit, SZ_D); |
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42 cc = CC_A; |
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43 } |
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44 jcc(code, cc, code->cur+2); |
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45 opts->move_pc_off = code->cur - tmp.cur; |
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46 mov_ir(code, 0x1234, opts->scratch1, SZ_D); |
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47 opts->move_pc_size = code->cur - tmp.cur - opts->move_pc_off; |
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48 *code = tmp; |
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49 } |
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50 |
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51 void patch_for_retranslate(cpu_options *opts, code_ptr native_address, code_ptr handler) |
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52 { |
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53 if (!is_mov_ir(native_address)) { |
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54 //instruction is not already patched for either retranslation or a breakpoint |
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55 //copy original mov_ir instruction containing PC to beginning of native code area |
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56 memmove(native_address, native_address + opts->move_pc_off, opts->move_pc_size); |
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57 } |
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58 //jump to the retranslation handler |
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59 code_info tmp = { |
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60 .cur = native_address + opts->move_pc_size, |
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61 .last = native_address + 256, |
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62 .stack_off = 0 |
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63 }; |
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64 jmp(&tmp, handler); |
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65 } |
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66 |
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67 void defer_translation(cpu_options *opts, uint32_t address, code_ptr handler) |
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68 { |
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69 mov_ir(&opts->code, address, opts->scratch1, SZ_D); |
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70 jmp(&opts->code, handler); |
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71 } |
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72 |
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73 void check_cycles(cpu_options * opts) |
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74 { |
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Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
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75 code_info *code = &opts->code; |
1109
4bc27caa6e20
Fix a subtle bug in interrupt handling introduced with the move to a single cycle register in the Z80 core. Fixes regression in Puyo Puyo 2
Michael Pavone <pavone@retrodev.com>
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1107
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76 uint8_t cc; |
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parents:
987
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77 if (opts->limit < 0) { |
1109
4bc27caa6e20
Fix a subtle bug in interrupt handling introduced with the move to a single cycle register in the Z80 core. Fixes regression in Puyo Puyo 2
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78 cmp_ir(code, 1, opts->cycles, SZ_D); |
4bc27caa6e20
Fix a subtle bug in interrupt handling introduced with the move to a single cycle register in the Z80 core. Fixes regression in Puyo Puyo 2
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1107
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79 cc = CC_NS; |
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80 } else { |
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81 cmp_rr(code, opts->cycles, opts->limit, SZ_D); |
1109
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Fix a subtle bug in interrupt handling introduced with the move to a single cycle register in the Z80 core. Fixes regression in Puyo Puyo 2
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82 cc = CC_A; |
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83 } |
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84 code_ptr jmp_off; |
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85 ALLOC_CODE_RETRY_POINT |
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86 jmp_off = code->cur+1; |
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87 jcc(code, cc, jmp_off+1); |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
88 call(code, opts->handle_cycle_limit); |
2268
5b308c7b098c
Avoid code mem allocation bomb when a div instruction gets rewritten
Michael Pavone <pavone@retrodev.com>
parents:
2237
diff
changeset
|
89 CHECK_BRANCH_DEST(jmp_off); |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
90 } |
589
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
567
diff
changeset
|
91 |
697
7f96bd1cb1be
Sync fixes and logging to fix more sync issues
Michael Pavone <pavone@retrodev.com>
parents:
692
diff
changeset
|
92 void log_address(cpu_options *opts, uint32_t address, char * format) |
7f96bd1cb1be
Sync fixes and logging to fix more sync issues
Michael Pavone <pavone@retrodev.com>
parents:
692
diff
changeset
|
93 { |
7f96bd1cb1be
Sync fixes and logging to fix more sync issues
Michael Pavone <pavone@retrodev.com>
parents:
692
diff
changeset
|
94 code_info *code = &opts->code; |
7f96bd1cb1be
Sync fixes and logging to fix more sync issues
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parents:
692
diff
changeset
|
95 call(code, opts->save_context); |
7f96bd1cb1be
Sync fixes and logging to fix more sync issues
Michael Pavone <pavone@retrodev.com>
parents:
692
diff
changeset
|
96 push_r(code, opts->context_reg); |
7f96bd1cb1be
Sync fixes and logging to fix more sync issues
Michael Pavone <pavone@retrodev.com>
parents:
692
diff
changeset
|
97 mov_rr(code, opts->cycles, RDX, SZ_D); |
7f96bd1cb1be
Sync fixes and logging to fix more sync issues
Michael Pavone <pavone@retrodev.com>
parents:
692
diff
changeset
|
98 mov_ir(code, (int64_t)format, RDI, SZ_PTR); |
7f96bd1cb1be
Sync fixes and logging to fix more sync issues
Michael Pavone <pavone@retrodev.com>
parents:
692
diff
changeset
|
99 mov_ir(code, address, RSI, SZ_D); |
7f96bd1cb1be
Sync fixes and logging to fix more sync issues
Michael Pavone <pavone@retrodev.com>
parents:
692
diff
changeset
|
100 call_args_abi(code, (code_ptr)printf, 3, RDI, RSI, RDX); |
7f96bd1cb1be
Sync fixes and logging to fix more sync issues
Michael Pavone <pavone@retrodev.com>
parents:
692
diff
changeset
|
101 pop_r(code, opts->context_reg); |
7f96bd1cb1be
Sync fixes and logging to fix more sync issues
Michael Pavone <pavone@retrodev.com>
parents:
692
diff
changeset
|
102 call(code, opts->load_context); |
7f96bd1cb1be
Sync fixes and logging to fix more sync issues
Michael Pavone <pavone@retrodev.com>
parents:
692
diff
changeset
|
103 } |
7f96bd1cb1be
Sync fixes and logging to fix more sync issues
Michael Pavone <pavone@retrodev.com>
parents:
692
diff
changeset
|
104 |
601
f0061e3d2ad9
Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor
Michael Pavone <pavone@retrodev.com>
parents:
595
diff
changeset
|
105 void check_code_prologue(code_info *code) |
f0061e3d2ad9
Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor
Michael Pavone <pavone@retrodev.com>
parents:
595
diff
changeset
|
106 { |
f0061e3d2ad9
Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor
Michael Pavone <pavone@retrodev.com>
parents:
595
diff
changeset
|
107 check_alloc_code(code, MAX_INST_LEN*4); |
f0061e3d2ad9
Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor
Michael Pavone <pavone@retrodev.com>
parents:
595
diff
changeset
|
108 } |
f0061e3d2ad9
Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor
Michael Pavone <pavone@retrodev.com>
parents:
595
diff
changeset
|
109 |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
110 code_ptr gen_mem_fun(cpu_options * opts, memmap_chunk const * memmap, uint32_t num_chunks, ftype fun_type, code_ptr *after_inc) |
589
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
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diff
changeset
|
111 { |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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parents:
567
diff
changeset
|
112 code_info *code = &opts->code; |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
567
diff
changeset
|
113 code_ptr start = code->cur; |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
567
diff
changeset
|
114 check_cycles(opts); |
987
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
115 uint8_t is_write = fun_type == WRITE_16 || fun_type == WRITE_8; |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
116 uint8_t adr_reg = is_write ? opts->scratch2 : opts->scratch1; |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
117 uint8_t size = (fun_type == READ_16 || fun_type == WRITE_16) ? SZ_W : SZ_B; |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
118 if (size != SZ_B && opts->align_error_mask) { |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
119 test_ir(code, opts->align_error_mask, adr_reg, SZ_D); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
120 jcc(code, CC_NZ, is_write ? opts->handle_align_error_write : opts->handle_align_error_read); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
121 } |
589
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
567
diff
changeset
|
122 cycles(opts, opts->bus_cycles); |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
589
diff
changeset
|
123 if (after_inc) { |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
589
diff
changeset
|
124 *after_inc = code->cur; |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
589
diff
changeset
|
125 } |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
2036
diff
changeset
|
126 |
750
59b499f6b24f
Fix handling of address mask in gen_mem_fun
Michael Pavone <pavone@retrodev.com>
parents:
697
diff
changeset
|
127 if (opts->address_size == SZ_D && opts->address_mask != 0xFFFFFFFF) { |
59b499f6b24f
Fix handling of address mask in gen_mem_fun
Michael Pavone <pavone@retrodev.com>
parents:
697
diff
changeset
|
128 and_ir(code, opts->address_mask, adr_reg, SZ_D); |
1116
fe8c79f82c22
More cleanup in preparation for SMS/Mark III support
Michael Pavone <pavone@retrodev.com>
parents:
1109
diff
changeset
|
129 } else if (opts->address_size == SZ_W && opts->address_mask != 0xFFFF) { |
fe8c79f82c22
More cleanup in preparation for SMS/Mark III support
Michael Pavone <pavone@retrodev.com>
parents:
1109
diff
changeset
|
130 and_ir(code, opts->address_mask, adr_reg, SZ_W); |
589
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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parents:
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diff
changeset
|
131 } |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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parents:
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diff
changeset
|
132 code_ptr lb_jcc = NULL, ub_jcc = NULL; |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
567
diff
changeset
|
133 uint16_t access_flag = is_write ? MMAP_WRITE : MMAP_READ; |
690
fc04781f4d28
Removed hardcoded assumptions in M68K core about which parts of the memory map are RAM
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
134 uint32_t ram_flags_off = opts->ram_flags_off; |
1086
f0a1e0a2263c
Made some optimizations to gen_mem_fun to keep the size of chunk handler sections within range of a single byte displacement
Michael Pavone <pavone@retrodev.com>
parents:
1084
diff
changeset
|
135 uint32_t min_address = 0; |
f0a1e0a2263c
Made some optimizations to gen_mem_fun to keep the size of chunk handler sections within range of a single byte displacement
Michael Pavone <pavone@retrodev.com>
parents:
1084
diff
changeset
|
136 uint32_t max_address = opts->max_address; |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
2036
diff
changeset
|
137 uint8_t need_wide_jcc = 0; |
589
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
567
diff
changeset
|
138 for (uint32_t chunk = 0; chunk < num_chunks; chunk++) |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
567
diff
changeset
|
139 { |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
2036
diff
changeset
|
140 code_info chunk_start = *code; |
1086
f0a1e0a2263c
Made some optimizations to gen_mem_fun to keep the size of chunk handler sections within range of a single byte displacement
Michael Pavone <pavone@retrodev.com>
parents:
1084
diff
changeset
|
141 if (memmap[chunk].start > min_address) { |
589
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
567
diff
changeset
|
142 cmp_ir(code, memmap[chunk].start, adr_reg, opts->address_size); |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
567
diff
changeset
|
143 lb_jcc = code->cur + 1; |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
2036
diff
changeset
|
144 if (need_wide_jcc) { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
2036
diff
changeset
|
145 jcc(code, CC_C, code->cur + 130); |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
2036
diff
changeset
|
146 lb_jcc++; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
2036
diff
changeset
|
147 } else { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
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parents:
2036
diff
changeset
|
148 jcc(code, CC_C, code->cur + 2); |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
2036
diff
changeset
|
149 } |
1086
f0a1e0a2263c
Made some optimizations to gen_mem_fun to keep the size of chunk handler sections within range of a single byte displacement
Michael Pavone <pavone@retrodev.com>
parents:
1084
diff
changeset
|
150 } else { |
f0a1e0a2263c
Made some optimizations to gen_mem_fun to keep the size of chunk handler sections within range of a single byte displacement
Michael Pavone <pavone@retrodev.com>
parents:
1084
diff
changeset
|
151 min_address = memmap[chunk].end; |
589
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
567
diff
changeset
|
152 } |
1086
f0a1e0a2263c
Made some optimizations to gen_mem_fun to keep the size of chunk handler sections within range of a single byte displacement
Michael Pavone <pavone@retrodev.com>
parents:
1084
diff
changeset
|
153 if (memmap[chunk].end < max_address) { |
589
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
567
diff
changeset
|
154 cmp_ir(code, memmap[chunk].end, adr_reg, opts->address_size); |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
567
diff
changeset
|
155 ub_jcc = code->cur + 1; |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
2036
diff
changeset
|
156 if (need_wide_jcc) { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
2036
diff
changeset
|
157 jcc(code, CC_NC, code->cur + 130); |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
2036
diff
changeset
|
158 ub_jcc++; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
2036
diff
changeset
|
159 } else { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
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parents:
2036
diff
changeset
|
160 jcc(code, CC_NC, code->cur + 2); |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
2036
diff
changeset
|
161 } |
1086
f0a1e0a2263c
Made some optimizations to gen_mem_fun to keep the size of chunk handler sections within range of a single byte displacement
Michael Pavone <pavone@retrodev.com>
parents:
1084
diff
changeset
|
162 } else { |
f0a1e0a2263c
Made some optimizations to gen_mem_fun to keep the size of chunk handler sections within range of a single byte displacement
Michael Pavone <pavone@retrodev.com>
parents:
1084
diff
changeset
|
163 max_address = memmap[chunk].start; |
589
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
567
diff
changeset
|
164 } |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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parents:
567
diff
changeset
|
165 |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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parents:
567
diff
changeset
|
166 if (memmap[chunk].mask != opts->address_mask) { |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
567
diff
changeset
|
167 and_ir(code, memmap[chunk].mask, adr_reg, opts->address_size); |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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parents:
567
diff
changeset
|
168 } |
2134
9caebcfeac72
Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents:
2133
diff
changeset
|
169 code_ptr after_normal = NULL; |
2138
b6338e18787e
Fix some dynarec code invalidation issues
Michael Pavone <pavone@retrodev.com>
parents:
2134
diff
changeset
|
170 uint8_t need_addr_pop = 0; |
2134
9caebcfeac72
Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
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parents:
2133
diff
changeset
|
171 if (size == SZ_B && memmap[chunk].shift != 0) { |
2138
b6338e18787e
Fix some dynarec code invalidation issues
Michael Pavone <pavone@retrodev.com>
parents:
2134
diff
changeset
|
172 if (is_write && (memmap[chunk].flags & MMAP_CODE)) { |
b6338e18787e
Fix some dynarec code invalidation issues
Michael Pavone <pavone@retrodev.com>
parents:
2134
diff
changeset
|
173 push_r(code, adr_reg); |
b6338e18787e
Fix some dynarec code invalidation issues
Michael Pavone <pavone@retrodev.com>
parents:
2134
diff
changeset
|
174 need_addr_pop = 1; |
b6338e18787e
Fix some dynarec code invalidation issues
Michael Pavone <pavone@retrodev.com>
parents:
2134
diff
changeset
|
175 } |
2134
9caebcfeac72
Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents:
2133
diff
changeset
|
176 btr_ir(code, 0, adr_reg, opts->address_size); |
9caebcfeac72
Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
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parents:
2133
diff
changeset
|
177 code_ptr normal = code->cur+1; |
9caebcfeac72
Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
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parents:
2133
diff
changeset
|
178 jcc(code, CC_NC, normal); |
9caebcfeac72
Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
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parents:
2133
diff
changeset
|
179 if (memmap[chunk].shift > 0) { |
9caebcfeac72
Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
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parents:
2133
diff
changeset
|
180 shl_ir(code, memmap[chunk].shift, adr_reg, opts->address_size); |
9caebcfeac72
Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
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parents:
2133
diff
changeset
|
181 } else { |
9caebcfeac72
Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
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parents:
2133
diff
changeset
|
182 shr_ir(code, -memmap[chunk].shift, adr_reg, opts->address_size); |
9caebcfeac72
Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents:
2133
diff
changeset
|
183 } |
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184 or_ir(code, 1, adr_reg, opts->address_size); |
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185 after_normal = code->cur + 1; |
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186 jmp(code, after_normal); |
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187 *normal = code->cur - (normal + 1); |
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188 } |
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189 if (memmap[chunk].shift > 0) { |
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190 if (!need_addr_pop && is_write && (memmap[chunk].flags & MMAP_CODE)) { |
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191 push_r(code, adr_reg); |
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192 need_addr_pop = 1; |
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193 } |
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194 shl_ir(code, memmap[chunk].shift, adr_reg, opts->address_size); |
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195 } else if (memmap[chunk].shift < 0) { |
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196 if (!need_addr_pop && is_write && (memmap[chunk].flags & MMAP_CODE)) { |
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197 push_r(code, adr_reg); |
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198 need_addr_pop = 1; |
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199 } |
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200 shr_ir(code, -memmap[chunk].shift, adr_reg, opts->address_size); |
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201 } |
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202 if (after_normal) { |
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203 *after_normal = code->cur - (after_normal + 1); |
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204 } |
589
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205 void * cfun; |
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206 switch (fun_type) |
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207 { |
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208 case READ_16: |
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209 cfun = memmap[chunk].read_16; |
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210 break; |
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211 case READ_8: |
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212 cfun = memmap[chunk].read_8; |
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213 break; |
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214 case WRITE_16: |
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215 cfun = memmap[chunk].write_16; |
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216 break; |
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217 case WRITE_8: |
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218 cfun = memmap[chunk].write_8; |
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219 break; |
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220 default: |
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221 cfun = NULL; |
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222 } |
604
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223 if(memmap[chunk].flags & access_flag) { |
2237
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224 uint8_t tmp_size = size; |
589
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225 if (memmap[chunk].flags & MMAP_PTR_IDX) { |
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226 if (memmap[chunk].flags & MMAP_FUNC_NULL) { |
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227 cmp_irdisp(code, 0, opts->context_reg, opts->mem_ptr_off + sizeof(void*) * memmap[chunk].ptr_index, SZ_PTR); |
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228 code_ptr not_null = code->cur + 1; |
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229 jcc(code, CC_NZ, code->cur + 2); |
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230 call(code, opts->save_context); |
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231 if (is_write) { |
658
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232 call_args_abi(code, cfun, 3, opts->scratch2, opts->context_reg, opts->scratch1); |
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233 mov_rr(code, RAX, opts->context_reg, SZ_PTR); |
589
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234 } else { |
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235 push_r(code, opts->context_reg); |
658
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236 call_args_abi(code, cfun, 2, opts->scratch1, opts->context_reg); |
589
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237 pop_r(code, opts->context_reg); |
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238 mov_rr(code, RAX, opts->scratch1, size); |
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239 } |
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240 jmp(code, opts->load_context); |
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241 |
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242 *not_null = code->cur - (not_null + 1); |
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243 } |
2237
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244 if (size == SZ_B) { |
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245 if ((memmap[chunk].flags & MMAP_ONLY_ODD) || (memmap[chunk].flags & MMAP_ONLY_EVEN)) { |
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246 bt_ir(code, 0, adr_reg, opts->address_size); |
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247 code_ptr good_addr = code->cur + 1; |
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248 jcc(code, (memmap[chunk].flags & MMAP_ONLY_ODD) ? CC_C : CC_NC, code->cur + 2); |
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249 if (!is_write) { |
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250 mov_ir(code, 0xFF, opts->scratch1, SZ_B); |
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251 } |
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252 retn(code); |
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253 *good_addr = code->cur - (good_addr + 1); |
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254 shr_ir(code, 1, adr_reg, opts->address_size); |
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255 } else if (opts->byte_swap || memmap[chunk].flags & MMAP_BYTESWAP) { |
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256 xor_ir(code, 1, adr_reg, opts->address_size); |
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257 } |
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258 } else if ((memmap[chunk].flags & MMAP_ONLY_ODD) || (memmap[chunk].flags & MMAP_ONLY_EVEN)) { |
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259 tmp_size = SZ_B; |
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260 shr_ir(code, 1, adr_reg, opts->address_size); |
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261 if ((memmap[chunk].flags & MMAP_ONLY_EVEN) && is_write) { |
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|
262 shr_ir(code, 8, opts->scratch1, SZ_W); |
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263 } |
589
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264 } |
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|
265 if (opts->address_size != SZ_D) { |
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|
266 movzx_rr(code, adr_reg, adr_reg, opts->address_size, SZ_D); |
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|
267 } |
2138
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|
268 if (!need_addr_pop && is_write && (memmap[chunk].flags & MMAP_CODE)) { |
1081
89cc20cf1ad3
Fix handling of MMAP_CODE chunks that also have MMAP_PTR_IDX set
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changeset
|
269 push_r(code, adr_reg); |
2138
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|
270 need_addr_pop = 1; |
1081
89cc20cf1ad3
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|
271 } |
589
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changeset
|
272 add_rdispr(code, opts->context_reg, opts->mem_ptr_off + sizeof(void*) * memmap[chunk].ptr_index, adr_reg, SZ_PTR); |
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changeset
|
273 if (is_write) { |
2237
f82c090c1e89
Implement MMAP_ONLY_ODD/EVEN in combination with MMAP_PTR_IDX. Fixes games that have SRAM when a system with TMSS is selected
Michael Pavone <pavone@retrodev.com>
parents:
2138
diff
changeset
|
274 mov_rrind(code, opts->scratch1, opts->scratch2, tmp_size); |
589
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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diff
changeset
|
275 } else { |
2237
f82c090c1e89
Implement MMAP_ONLY_ODD/EVEN in combination with MMAP_PTR_IDX. Fixes games that have SRAM when a system with TMSS is selected
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parents:
2138
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|
276 mov_rindr(code, opts->scratch1, opts->scratch1, tmp_size); |
f82c090c1e89
Implement MMAP_ONLY_ODD/EVEN in combination with MMAP_PTR_IDX. Fixes games that have SRAM when a system with TMSS is selected
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parents:
2138
diff
changeset
|
277 } |
f82c090c1e89
Implement MMAP_ONLY_ODD/EVEN in combination with MMAP_PTR_IDX. Fixes games that have SRAM when a system with TMSS is selected
Michael Pavone <pavone@retrodev.com>
parents:
2138
diff
changeset
|
278 if (size != tmp_size && !is_write) { |
f82c090c1e89
Implement MMAP_ONLY_ODD/EVEN in combination with MMAP_PTR_IDX. Fixes games that have SRAM when a system with TMSS is selected
Michael Pavone <pavone@retrodev.com>
parents:
2138
diff
changeset
|
279 if (memmap[chunk].flags & MMAP_ONLY_EVEN) { |
f82c090c1e89
Implement MMAP_ONLY_ODD/EVEN in combination with MMAP_PTR_IDX. Fixes games that have SRAM when a system with TMSS is selected
Michael Pavone <pavone@retrodev.com>
parents:
2138
diff
changeset
|
280 shl_ir(code, 8, opts->scratch1, SZ_W); |
f82c090c1e89
Implement MMAP_ONLY_ODD/EVEN in combination with MMAP_PTR_IDX. Fixes games that have SRAM when a system with TMSS is selected
Michael Pavone <pavone@retrodev.com>
parents:
2138
diff
changeset
|
281 mov_ir(code, 0xFF, opts->scratch1, SZ_B); |
f82c090c1e89
Implement MMAP_ONLY_ODD/EVEN in combination with MMAP_PTR_IDX. Fixes games that have SRAM when a system with TMSS is selected
Michael Pavone <pavone@retrodev.com>
parents:
2138
diff
changeset
|
282 } else { |
f82c090c1e89
Implement MMAP_ONLY_ODD/EVEN in combination with MMAP_PTR_IDX. Fixes games that have SRAM when a system with TMSS is selected
Michael Pavone <pavone@retrodev.com>
parents:
2138
diff
changeset
|
283 or_ir(code, 0xFF00, opts->scratch1, SZ_W); |
f82c090c1e89
Implement MMAP_ONLY_ODD/EVEN in combination with MMAP_PTR_IDX. Fixes games that have SRAM when a system with TMSS is selected
Michael Pavone <pavone@retrodev.com>
parents:
2138
diff
changeset
|
284 } |
589
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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parents:
567
diff
changeset
|
285 } |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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parents:
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diff
changeset
|
286 } else { |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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parents:
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diff
changeset
|
287 if (size == SZ_B) { |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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diff
changeset
|
288 if ((memmap[chunk].flags & MMAP_ONLY_ODD) || (memmap[chunk].flags & MMAP_ONLY_EVEN)) { |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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diff
changeset
|
289 bt_ir(code, 0, adr_reg, opts->address_size); |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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parents:
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diff
changeset
|
290 code_ptr good_addr = code->cur + 1; |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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parents:
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diff
changeset
|
291 jcc(code, (memmap[chunk].flags & MMAP_ONLY_ODD) ? CC_C : CC_NC, code->cur + 2); |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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parents:
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diff
changeset
|
292 if (!is_write) { |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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diff
changeset
|
293 mov_ir(code, 0xFF, opts->scratch1, SZ_B); |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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parents:
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diff
changeset
|
294 } |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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diff
changeset
|
295 retn(code); |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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diff
changeset
|
296 *good_addr = code->cur - (good_addr + 1); |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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parents:
567
diff
changeset
|
297 shr_ir(code, 1, adr_reg, opts->address_size); |
604
39d7d463ed5b
Get Z80 banked access sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
601
diff
changeset
|
298 } else if (opts->byte_swap || memmap[chunk].flags & MMAP_BYTESWAP) { |
589
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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parents:
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diff
changeset
|
299 xor_ir(code, 1, adr_reg, opts->address_size); |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
Michael Pavone <pavone@retrodev.com>
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567
diff
changeset
|
300 } |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
567
diff
changeset
|
301 } else if ((memmap[chunk].flags & MMAP_ONLY_ODD) || (memmap[chunk].flags & MMAP_ONLY_EVEN)) { |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
567
diff
changeset
|
302 tmp_size = SZ_B; |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
567
diff
changeset
|
303 shr_ir(code, 1, adr_reg, opts->address_size); |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
567
diff
changeset
|
304 if ((memmap[chunk].flags & MMAP_ONLY_EVEN) && is_write) { |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
567
diff
changeset
|
305 shr_ir(code, 8, opts->scratch1, SZ_W); |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
567
diff
changeset
|
306 } |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
567
diff
changeset
|
307 } |
595
68f86ca4bb32
Add a couple of missing checks for the byte_swap and address_size parameters in gen_mem_fun
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
308 if (opts->address_size != SZ_D) { |
68f86ca4bb32
Add a couple of missing checks for the byte_swap and address_size parameters in gen_mem_fun
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
309 movzx_rr(code, adr_reg, adr_reg, opts->address_size, SZ_D); |
68f86ca4bb32
Add a couple of missing checks for the byte_swap and address_size parameters in gen_mem_fun
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
310 } |
589
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
567
diff
changeset
|
311 if ((intptr_t)memmap[chunk].buffer <= 0x7FFFFFFF && (intptr_t)memmap[chunk].buffer >= -2147483648) { |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
567
diff
changeset
|
312 if (is_write) { |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
Michael Pavone <pavone@retrodev.com>
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diff
changeset
|
313 mov_rrdisp(code, opts->scratch1, opts->scratch2, (intptr_t)memmap[chunk].buffer, tmp_size); |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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parents:
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diff
changeset
|
314 } else { |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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parents:
567
diff
changeset
|
315 mov_rdispr(code, opts->scratch1, (intptr_t)memmap[chunk].buffer, opts->scratch1, tmp_size); |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
567
diff
changeset
|
316 } |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
567
diff
changeset
|
317 } else { |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
567
diff
changeset
|
318 if (is_write) { |
760
656b1fded67f
Fix self modifying code checks on platforms like OS X on which guest RAM ends up at an address unreachable with a 32-bit displacement
Michael Pavone <pavone@retrodev.com>
parents:
756
diff
changeset
|
319 push_r(code, opts->scratch2); |
656b1fded67f
Fix self modifying code checks on platforms like OS X on which guest RAM ends up at an address unreachable with a 32-bit displacement
Michael Pavone <pavone@retrodev.com>
parents:
756
diff
changeset
|
320 mov_ir(code, (intptr_t)memmap[chunk].buffer, opts->scratch2, SZ_PTR); |
656b1fded67f
Fix self modifying code checks on platforms like OS X on which guest RAM ends up at an address unreachable with a 32-bit displacement
Michael Pavone <pavone@retrodev.com>
parents:
756
diff
changeset
|
321 add_rdispr(code, RSP, 0, opts->scratch2, SZ_PTR); |
589
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
567
diff
changeset
|
322 mov_rrind(code, opts->scratch1, opts->scratch2, tmp_size); |
760
656b1fded67f
Fix self modifying code checks on platforms like OS X on which guest RAM ends up at an address unreachable with a 32-bit displacement
Michael Pavone <pavone@retrodev.com>
parents:
756
diff
changeset
|
323 if (is_write && (memmap[chunk].flags & MMAP_CODE)) { |
2138
b6338e18787e
Fix some dynarec code invalidation issues
Michael Pavone <pavone@retrodev.com>
parents:
2134
diff
changeset
|
324 need_addr_pop = 1; |
760
656b1fded67f
Fix self modifying code checks on platforms like OS X on which guest RAM ends up at an address unreachable with a 32-bit displacement
Michael Pavone <pavone@retrodev.com>
parents:
756
diff
changeset
|
325 } else { |
1511
2a5649a767e7
Fix accidental add to RSP with SZ_D and SZ_PTR. Using SZ_D breakse when the stack is located outside of the 32-bit addressable range
Michael Pavone <pavone@retrodev.com>
parents:
1465
diff
changeset
|
326 add_ir(code, sizeof(void*), RSP, SZ_PTR); |
894
a7774fc2de4b
Partially working change to do proper stack alignment rather than doing a lame alignment check when calling a C compile dfunction. 68K core seems okay, but Z80 is busted.
Michael Pavone <pavone@retrodev.com>
parents:
892
diff
changeset
|
327 code->stack_off -= sizeof(void *); |
760
656b1fded67f
Fix self modifying code checks on platforms like OS X on which guest RAM ends up at an address unreachable with a 32-bit displacement
Michael Pavone <pavone@retrodev.com>
parents:
756
diff
changeset
|
328 } |
589
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
567
diff
changeset
|
329 } else { |
756
e1dc98f7ed9f
Preserve scratch2 when using it as a temporary in memory read functions. This fixes a bunch of issues with the Z80 core and possibly some issues with the 68K core as well
Michael Pavone <pavone@retrodev.com>
parents:
750
diff
changeset
|
330 push_r(code, opts->scratch2); |
589
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
567
diff
changeset
|
331 mov_ir(code, (intptr_t)memmap[chunk].buffer, opts->scratch2, SZ_PTR); |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
567
diff
changeset
|
332 mov_rindexr(code, opts->scratch2, opts->scratch1, 1, opts->scratch1, tmp_size); |
756
e1dc98f7ed9f
Preserve scratch2 when using it as a temporary in memory read functions. This fixes a bunch of issues with the Z80 core and possibly some issues with the 68K core as well
Michael Pavone <pavone@retrodev.com>
parents:
750
diff
changeset
|
333 pop_r(code, opts->scratch2); |
589
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
567
diff
changeset
|
334 } |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
567
diff
changeset
|
335 } |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
567
diff
changeset
|
336 if (size != tmp_size && !is_write) { |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
567
diff
changeset
|
337 if (memmap[chunk].flags & MMAP_ONLY_EVEN) { |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
567
diff
changeset
|
338 shl_ir(code, 8, opts->scratch1, SZ_W); |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
567
diff
changeset
|
339 mov_ir(code, 0xFF, opts->scratch1, SZ_B); |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
567
diff
changeset
|
340 } else { |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
567
diff
changeset
|
341 or_ir(code, 0xFF00, opts->scratch1, SZ_W); |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
567
diff
changeset
|
342 } |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
567
diff
changeset
|
343 } |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
567
diff
changeset
|
344 } |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
567
diff
changeset
|
345 if (is_write && (memmap[chunk].flags & MMAP_CODE)) { |
2138
b6338e18787e
Fix some dynarec code invalidation issues
Michael Pavone <pavone@retrodev.com>
parents:
2134
diff
changeset
|
346 if (need_addr_pop) { |
b6338e18787e
Fix some dynarec code invalidation issues
Michael Pavone <pavone@retrodev.com>
parents:
2134
diff
changeset
|
347 pop_r(code, adr_reg); |
b6338e18787e
Fix some dynarec code invalidation issues
Michael Pavone <pavone@retrodev.com>
parents:
2134
diff
changeset
|
348 } |
589
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
567
diff
changeset
|
349 mov_rr(code, opts->scratch2, opts->scratch1, opts->address_size); |
620
9d6fed6501ba
Fix handling of code writes for Z80 core. This seems to get things close to being back to where they were before the big refactor that broke the Z80 core. Some problems remain. Notably the sound driver in Sonic 2 is still quite broken.
Michael Pavone <pavone@retrodev.com>
parents:
604
diff
changeset
|
350 shr_ir(code, opts->ram_flags_shift, opts->scratch1, opts->address_size); |
690
fc04781f4d28
Removed hardcoded assumptions in M68K core about which parts of the memory map are RAM
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
351 bt_rrdisp(code, opts->scratch1, opts->context_reg, ram_flags_off, opts->address_size); |
589
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
567
diff
changeset
|
352 code_ptr not_code = code->cur + 1; |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
567
diff
changeset
|
353 jcc(code, CC_NC, code->cur + 2); |
1084
193db42e702b
Remove hacky assumption about Genesis memory map in M68K core
Michael Pavone <pavone@retrodev.com>
parents:
1081
diff
changeset
|
354 if (memmap[chunk].mask != opts->address_mask) { |
1107
fc125af5e4f1
Fix to the fix of handling of self modifying code. Was ORing the base address with the wrong register before calling the modified code handler
Michael Pavone <pavone@retrodev.com>
parents:
1086
diff
changeset
|
355 or_ir(code, memmap[chunk].start, opts->scratch2, opts->address_size); |
1084
193db42e702b
Remove hacky assumption about Genesis memory map in M68K core
Michael Pavone <pavone@retrodev.com>
parents:
1081
diff
changeset
|
356 } |
589
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
567
diff
changeset
|
357 call(code, opts->save_context); |
658
6aa29ac33f1a
Use call_args and call_args_abi inside gen_mem_fun
Michael Pavone <pavone@retrodev.com>
parents:
620
diff
changeset
|
358 call_args(code, opts->handle_code_write, 2, opts->scratch2, opts->context_reg); |
589
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
567
diff
changeset
|
359 mov_rr(code, RAX, opts->context_reg, SZ_PTR); |
1086
f0a1e0a2263c
Made some optimizations to gen_mem_fun to keep the size of chunk handler sections within range of a single byte displacement
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360 jmp(code, opts->load_context); |
589
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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361 *not_code = code->cur - (not_code+1); |
2dde38c1744f
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362 } |
2dde38c1744f
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363 retn(code); |
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364 } else if (cfun) { |
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365 call(code, opts->save_context); |
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366 if (is_write) { |
658
6aa29ac33f1a
Use call_args and call_args_abi inside gen_mem_fun
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367 call_args_abi(code, cfun, 3, opts->scratch2, opts->context_reg, opts->scratch1); |
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368 mov_rr(code, RAX, opts->context_reg, SZ_PTR); |
589
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369 } else { |
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370 push_r(code, opts->context_reg); |
658
6aa29ac33f1a
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371 call_args_abi(code, cfun, 2, opts->scratch1, opts->context_reg); |
589
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Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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372 pop_r(code, opts->context_reg); |
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Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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373 mov_rr(code, RAX, opts->scratch1, size); |
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374 } |
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375 jmp(code, opts->load_context); |
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376 } else { |
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377 //Not sure the best course of action here |
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378 if (!is_write) { |
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Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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379 mov_ir(code, size == SZ_B ? 0xFF : 0xFFFF, opts->scratch1, size); |
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380 } |
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381 retn(code); |
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382 } |
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383 if (lb_jcc) { |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
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384 if (need_wide_jcc) { |
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385 *((int32_t*)lb_jcc) = code->cur - (lb_jcc+4); |
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386 } else if (code->cur - (lb_jcc+1) > 0x7f) { |
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387 need_wide_jcc = 1; |
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388 chunk--; |
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389 *code = chunk_start; |
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Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
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390 continue; |
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391 } else { |
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Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
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392 *lb_jcc = code->cur - (lb_jcc+1); |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
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393 } |
589
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394 lb_jcc = NULL; |
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395 } |
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Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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396 if (ub_jcc) { |
2054
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397 if (need_wide_jcc) { |
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398 *((int32_t*)ub_jcc) = code->cur - (ub_jcc+4); |
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399 } else if (code->cur - (ub_jcc+1) > 0x7f) { |
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Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
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400 need_wide_jcc = 1; |
8ee7ecbf3f21
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401 chunk--; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
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402 *code = chunk_start; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
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403 continue; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
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404 } else { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
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405 *ub_jcc = code->cur - (ub_jcc+1); |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
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parents:
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406 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
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parents:
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|
407 |
589
2dde38c1744f
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408 ub_jcc = NULL; |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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parents:
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|
409 } |
2070
afc54649ebed
Fix error in code write detection introduced from "wide" jcc change
Michael Pavone <pavone@retrodev.com>
parents:
2054
diff
changeset
|
410 if (memmap[chunk].flags & MMAP_CODE) { |
2113
0013362c320c
Fix handling of ram code flag offset calculation for ranges that are not an even multiple of the code flag page size
Michael Pavone <pavone@retrodev.com>
parents:
2070
diff
changeset
|
411 uint32_t size = chunk_size(opts, memmap + chunk); |
0013362c320c
Fix handling of ram code flag offset calculation for ranges that are not an even multiple of the code flag page size
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diff
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412 uint32_t size_round_mask = (1 << (opts->ram_flags_shift + 3)) - 1; |
0013362c320c
Fix handling of ram code flag offset calculation for ranges that are not an even multiple of the code flag page size
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diff
changeset
|
413 if (size & size_round_mask) { |
0013362c320c
Fix handling of ram code flag offset calculation for ranges that are not an even multiple of the code flag page size
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parents:
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diff
changeset
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414 size &= ~size_round_mask; |
0013362c320c
Fix handling of ram code flag offset calculation for ranges that are not an even multiple of the code flag page size
Michael Pavone <pavone@retrodev.com>
parents:
2070
diff
changeset
|
415 size += size_round_mask + 1; |
2070
afc54649ebed
Fix error in code write detection introduced from "wide" jcc change
Michael Pavone <pavone@retrodev.com>
parents:
2054
diff
changeset
|
416 } |
2113
0013362c320c
Fix handling of ram code flag offset calculation for ranges that are not an even multiple of the code flag page size
Michael Pavone <pavone@retrodev.com>
parents:
2070
diff
changeset
|
417 ram_flags_off += size >> (opts->ram_flags_shift + 3); |
2070
afc54649ebed
Fix error in code write detection introduced from "wide" jcc change
Michael Pavone <pavone@retrodev.com>
parents:
2054
diff
changeset
|
418 } |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
2036
diff
changeset
|
419 if (need_wide_jcc) { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
2036
diff
changeset
|
420 need_wide_jcc = 0; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
2036
diff
changeset
|
421 } |
589
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
567
diff
changeset
|
422 } |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
567
diff
changeset
|
423 if (!is_write) { |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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parents:
567
diff
changeset
|
424 mov_ir(code, size == SZ_B ? 0xFF : 0xFFFF, opts->scratch1, size); |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
567
diff
changeset
|
425 } |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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parents:
567
diff
changeset
|
426 retn(code); |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
567
diff
changeset
|
427 return start; |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
567
diff
changeset
|
428 } |