Mercurial > repos > blastem
annotate analyze.py @ 161:6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
author | Mike Pavone <pavone@retrodev.com> |
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date | Sat, 05 Jan 2013 01:55:11 -0800 |
parents | b231162c8fdd |
children | 006008a3f370 |
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1 #!/usr/bin/env python |
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2 |
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3 #0 - !SE |
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4 #1 - !CAS |
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5 #2 - A0 |
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6 #3 - A1 |
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7 #------ |
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8 #4 - A2 |
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9 #5 - A3 |
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10 #6 - A7 |
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11 #7 - EDCLK |
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12 #------ |
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13 #8 - !HSYNC |
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14 #9 - A4 |
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15 #A - A5 |
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16 #B - A6 |
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17 #------ |
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18 #C - !RAS |
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19 #D - !WB/!WE |
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20 #E - !DT/!OE |
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21 #F - SC |
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22 |
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23 |
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24 #VRAM swizzling |
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25 #A0 = V0 |
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26 #A1 = V1 |
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27 #A8 = V2 |
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28 #A9 = V3 |
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29 #A10 = V4 |
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30 #A11 = V5 |
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31 #A12 = V6 |
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32 #A13 = V7 |
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33 #A14 = V8 |
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34 #A15 = V9 |
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35 #--guesses follow-- |
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36 #A2 = V10 |
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37 #A3 = V11 |
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38 #A4 = V12 |
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39 #A5 = V13 |
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40 #A6 = V14 |
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41 #A7 = V15 |
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42 |
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43 |
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44 def get_addr(sample): |
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45 return ((sample >> 2) & 0xF) | ((sample >> 5) & 0x70) | ((sample << 1) & 0x80) |
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46 |
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47 def swizzle_addr(addr): |
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48 return (addr & 0x0003) | ((addr >> 6) & 0x03FC) | ((addr << 8) & 0xFC00) |
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49 |
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50 def print_addr_op(addr, addr_format, mode, samplenum, triggerpos, rate): |
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51 print '{0:{1}} ({2:{1}}) {3}@{4} ns'.format(swizzle_addr(addr), addr_format, addr, mode, (samplenum - triggerpos)*rate) |
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52 |
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53 def detect_rise(last, sample, bit): |
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54 mask = 1 << bit |
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55 return (not last & mask) and (sample & mask) |
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56 |
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57 def detect_fall(last, sample, bit): |
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58 mask = 1 << bit |
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59 return (last & mask) and (not sample & mask) |
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60 |
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61 def detect_high(sample, bit): |
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62 mask = 1 << bit |
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63 return sample & mask |
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64 |
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65 |
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66 cas = 0x1 |
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67 ras = 0xC |
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68 edclk = 0x7 |
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69 hsync = 0x8 |
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70 wewb = 0xD |
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71 oedt = 0xE |
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72 sc = 0xF |
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73 |
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74 last = False |
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75 state = 'begin' |
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76 triggerpos = 0 |
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77 readcounter = 0 |
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78 sillyread = 0 |
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79 lastaddr = -1 |
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80 edclk_ticks = 0 |
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81 sc_ticks = 0 |
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82 tick_start = False |
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83 #f = open('street_fighter_vram_100mhz_hsync_trig_2.ols') |
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84 #f = open('street_fighter_vram_50mhz_hsync_trig.ols') |
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85 from sys import argv,exit |
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86 if len(argv) < 2: |
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87 print 'usage: analyze.py filename' |
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88 exit(1) |
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89 if '-b' in argv: |
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90 addr_format = '016b' |
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91 else: |
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92 addr_format = '04X' |
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93 f = open(argv[1]) |
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94 for line in f: |
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95 if line.startswith(';TriggerPosition'): |
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96 _,_,triggerpos = line.partition(':') |
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97 triggerpos = int(triggerpos.strip()) |
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98 elif line.startswith(';Rate'): |
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99 _,_,rate = line.partition(':') |
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100 #convert to nanoseconds between samples |
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101 rate = (1.0/float(rate.strip())) * 1000000000.0 |
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102 elif not line.startswith(';'): |
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103 sample,_,samplenum = line.partition('@') |
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104 samplenum = int(samplenum.strip()) |
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105 sample = int(sample, 16) |
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106 if detect_rise(last, sample, edclk): |
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107 edclk_ticks += 1 |
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108 if detect_rise(last, sample, sc): |
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109 sc_ticks += 1 |
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110 if not (last is False): |
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111 #detect falling edge of !HSYNC |
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112 if detect_fall(last, sample, hsync): |
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113 if readcounter: |
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114 print readcounter, 'reads,', sillyread, 'redundant reads' |
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115 readcounter = sillyread = 0 |
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116 if not tick_start is False: |
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117 float(edclk_ticks)/((rate * (samplenum-tick_start)) / 1000.0) |
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118 print 'EDCLK:', edclk_ticks, ' ticks, {0}MHz'.format(float(edclk_ticks)/((rate * (samplenum-tick_start)) / 1000.0)) |
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119 print 'SC:', sc_ticks, ' ticks, {0}MHz'.format(float(sc_ticks)/((rate * (samplenum-tick_start)) / 1000.0)) |
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120 tick_start = samplenum |
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121 edclk_ticks = sc_ticks = 0 |
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122 print 'HSYNC Start' |
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123 #detect rising edge of !HSYNC |
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124 elif detect_rise(last, sample, hsync): |
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125 if not tick_start is False: |
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126 float(edclk_ticks)/((rate * (samplenum-tick_start)) / 1000.0) |
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127 print 'EDCLK:', edclk_ticks, ' ticks, {0}MHz'.format(float(edclk_ticks)/((rate * (samplenum-tick_start)) / 1000.0)) |
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128 print 'SC:', sc_ticks, ' ticks, {0}MHz'.format(float(sc_ticks)/((rate * (samplenum-tick_start)) / 1000.0)) |
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129 tick_start = samplenum |
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130 edclk_ticks = sc_ticks = 0 |
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131 print 'HSYNC End' |
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132 if state == 'begin': |
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133 #detect falling edge of !RAS |
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134 if detect_fall(last, sample, ras): |
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135 state = 'ras' |
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136 row = get_addr(sample) |
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137 mode = 'ram' if detect_high(sample, oedt) else 'read transfer' |
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138 elif detect_fall(last, sample, cas): |
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139 state = 'cas' |
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140 elif state == 'ras': |
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141 if detect_fall(last, sample, cas): |
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142 state = 'begin' |
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143 col = get_addr(sample) |
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144 addr = (row << 8) | col |
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145 if mode == 'ram': |
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146 state = 'ras_cas' |
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147 else: |
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148 print_addr_op(addr, addr_format, mode, samplenum, triggerpos, rate) |
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149 lastaddr = addr |
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150 #print '{0:04X} {1} - {2:02X}:{3:02X} - {0:016b}'.format(addr, mode, row, col) |
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151 elif state == 'cas': |
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152 if detect_fall(last, sample, ras): |
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153 state = 'begin' |
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154 print 'refresh@{0} ns'.format((samplenum - triggerpos)*rate) |
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155 elif state == 'ras_cas': |
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156 if detect_fall(last, sample, oedt): |
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157 readcounter += 1 |
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158 if addr == lastaddr: |
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159 sillyread += 1 |
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160 print_addr_op(addr, addr_format, 'read', samplenum, triggerpos, rate) |
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161 state = 'begin' |
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162 elif detect_fall(last, sample, wewb): |
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163 print_addr_op(addr, addr_format, 'write', samplenum, triggerpos, rate) |
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164 state = 'begin' |
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165 last = sample |