Mercurial > repos > blastem
annotate 68kinst.c @ 641:66857bd2df0b
Fix decoding of movec
author | Michael Pavone <pavone@retrodev.com> |
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date | Wed, 15 Oct 2014 00:26:57 -0700 |
parents | 8a3198c17207 |
children | 08d0e3e7d0d8 |
rev | line source |
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1 /* |
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2 Copyright 2013 Michael Pavone |
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3 This file is part of BlastEm. |
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4 BlastEm is free software distributed under the terms of the GNU General Public License version 3 or greater. See COPYING for full license text. |
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5 */ |
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6 #include "68kinst.h" |
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7 #include <string.h> |
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8 #include <stdio.h> |
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9 |
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10 uint32_t sign_extend16(uint32_t val) |
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11 { |
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12 return (val & 0x8000) ? val | 0xFFFF0000 : val; |
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13 } |
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14 |
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15 uint32_t sign_extend8(uint32_t val) |
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16 { |
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17 return (val & 0x80) ? val | 0xFFFFFF00 : val; |
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18 } |
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19 |
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20 uint16_t *m68k_decode_op_ex(uint16_t *cur, uint8_t mode, uint8_t reg, uint8_t size, m68k_op_info *dst) |
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21 { |
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22 uint16_t ext, tmp; |
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23 dst->addr_mode = mode; |
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24 switch(mode) |
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25 { |
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26 case MODE_REG: |
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27 case MODE_AREG: |
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28 case MODE_AREG_INDIRECT: |
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29 case MODE_AREG_POSTINC: |
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30 case MODE_AREG_PREDEC: |
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31 dst->params.regs.pri = reg; |
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32 break; |
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33 case MODE_AREG_DISPLACE: |
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34 ext = *(++cur); |
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35 dst->params.regs.pri = reg; |
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36 dst->params.regs.displacement = sign_extend16(ext); |
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37 break; |
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38 case MODE_AREG_INDEX_MEM: |
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39 dst->params.regs.pri = reg; |
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40 ext = *(++cur); |
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41 dst->params.regs.sec = ext >> 11;//includes areg/dreg bit, reg num and word/long bit |
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42 #ifdef M68020 |
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43 dst->params.regs.scale = ext >> 9 & 3; |
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44 if (ext & 0x100) |
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45 { |
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46 dst->params.regs.disp_sizes = ext >> 4 & 3; |
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47 switch (dst->params.regs.disp_sizes) |
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48 { |
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49 case 0: |
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50 //reserved |
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51 return NULL; |
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52 case 1: |
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53 dst->params.regs.displacement = 0; |
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54 break; |
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55 case 2: |
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56 dst->params.regs.displacement = sign_extend16(*(cur++)); |
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57 break; |
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58 case 3: |
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59 tmp = *(cur++); |
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60 dst->params.regs.displacement = tmp << 16 | *(cur++); |
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61 break; |
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62 } |
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63 if (ext & 0x3) |
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64 { |
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65 //memory indirect |
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66 switch (ext & 0xC4) |
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67 { |
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68 case 0x00: |
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69 dst->addr_mode = MODE_AREG_PREINDEX; |
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70 break; |
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71 case 0x04: |
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72 dst->addr_mode = MODE_AREG_POSTINDEX; |
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73 break; |
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74 case 0x40: |
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75 dst->addr_mode = MODE_AREG_MEM_INDIRECT; |
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76 break; |
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77 case 0x80: |
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78 dst->addr_mode = MODE_PREINDEX; |
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79 break; |
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80 case 0x84: |
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81 dst->addr_mode = MODE_POSTINDEX; |
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82 break; |
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83 case 0xC0: |
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84 dst->addr_mode = MODE_MEM_INDIRECT; |
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85 break; |
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86 } |
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87 dst->params.regs.disp_sizes |= ext << 4 & 0x30; |
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88 switch (ext & 0x3) |
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89 { |
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90 case 0: |
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91 //reserved |
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92 return NULL; |
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93 case 1: |
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94 dst->params.regs.outer_disp = 0; |
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95 break; |
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96 case 2: |
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97 dst->params.regs.outer_disp = sign_extend16(*(cur++)); |
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98 break; |
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99 case 3: |
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100 tmp = *(cur++); |
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101 dst->params.regs.outer_disp = tmp << 16 | *(cur++); |
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102 break; |
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103 } |
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104 } else { |
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105 switch (ext >> 6 & 3) |
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106 { |
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107 case 0: |
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108 dst->addr_mode = MODE_AREG_INDEX_BASE_DISP; |
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109 break; |
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110 case 1: |
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111 dst->addr_mode = MODE_AREG_BASE_DISP; |
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112 break; |
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113 case 2: |
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114 dst->addr_mode = MODE_INDEX_BASE_DISP; |
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115 break; |
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116 case 3: |
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117 dst->addr_mode = MODE_BASE_DISP; |
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118 break; |
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119 } |
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120 } |
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121 } else { |
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122 #endif |
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123 dst->addr_mode = MODE_AREG_INDEX_DISP8; |
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124 dst->params.regs.displacement = sign_extend8(ext&0xFF); |
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125 #ifdef M68020 |
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126 } |
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127 #endif |
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128 break; |
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129 case MODE_PC_INDIRECT_ABS_IMMED: |
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130 switch(reg) |
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131 { |
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132 case 0: |
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133 dst->addr_mode = MODE_ABSOLUTE_SHORT; |
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134 ext = *(++cur); |
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135 dst->params.immed = sign_extend16(ext); |
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136 break; |
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137 case 1: |
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138 dst->addr_mode = MODE_ABSOLUTE; |
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139 ext = *(++cur); |
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140 dst->params.immed = ext << 16 | *(++cur); |
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141 break; |
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142 case 3: |
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143 #ifdef M68020 |
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144 //TODO: Implement me for M68020+ support; |
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145 #else |
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146 dst->addr_mode = MODE_PC_INDEX_DISP8; |
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147 ext = *(++cur); |
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148 dst->params.regs.sec = ext >> 11;//includes areg/dreg bit, reg num and word/long bit |
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149 dst->params.regs.displacement = sign_extend8(ext&0xFF); |
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150 #endif |
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151 |
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152 ext = *(++cur); |
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153 dst->params.regs.sec = ext >> 11;//includes areg/dreg bit, reg num and word/long bit |
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154 #ifdef M68020 |
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155 dst->params.regs.scale = ext >> 9 & 3; |
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156 if (ext & 0x100) |
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157 { |
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158 dst->params.regs.disp_sizes = ext >> 4 & 3; |
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159 switch (dst->params.regs.disp_sizes) |
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160 { |
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161 case 0: |
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162 //reserved |
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163 return NULL; |
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164 case 1: |
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165 dst->params.regs.displacement = 0; |
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166 break; |
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167 case 2: |
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168 dst->params.regs.displacement = sign_extend16(*(cur++)); |
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169 break; |
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170 case 3: |
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171 tmp = *(cur++); |
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172 dst->params.regs.displacement = tmp << 16 | *(cur++); |
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173 break; |
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174 } |
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175 if (ext & 0x3) |
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176 { |
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177 //memory indirect |
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178 switch (ext & 0xC4) |
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179 { |
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180 case 0x00: |
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181 dst->addr_mode = MODE_PC_PREINDEX; |
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182 break; |
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183 case 0x04: |
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184 dst->addr_mode = MODE_PC_POSTINDEX; |
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185 break; |
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186 case 0x40: |
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187 dst->addr_mode = MODE_PC_MEM_INDIRECT; |
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188 break; |
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189 case 0x80: |
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190 dst->addr_mode = MODE_ZPC_PREINDEX; |
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191 break; |
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192 case 0x84: |
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193 dst->addr_mode = MODE_ZPC_POSTINDEX; |
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194 break; |
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195 case 0xC0: |
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196 dst->addr_mode = MODE_ZPC_MEM_INDIRECT; |
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197 break; |
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198 } |
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199 dst->params.regs.disp_sizes |= ext << 4 & 0x30; |
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200 switch (ext & 0x3) |
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201 { |
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202 case 0: |
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203 //reserved |
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204 return NULL; |
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205 case 1: |
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206 dst->params.regs.outer_disp = 0; |
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207 break; |
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208 case 2: |
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209 dst->params.regs.outer_disp = sign_extend16(*(cur++)); |
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210 break; |
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211 case 3: |
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212 tmp = *(cur++); |
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213 dst->params.regs.outer_disp = tmp << 16 | *(cur++); |
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214 break; |
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215 } |
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216 } else { |
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217 switch (ext >> 6 & 3) |
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218 { |
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219 case 0: |
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220 dst->addr_mode = MODE_PC_INDEX_BASE_DISP; |
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221 break; |
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222 case 1: |
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223 dst->addr_mode = MODE_PC_BASE_DISP; |
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224 break; |
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225 case 2: |
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226 dst->addr_mode = MODE_ZPC_INDEX_BASE_DISP; |
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227 break; |
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228 case 3: |
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229 dst->addr_mode = MODE_ZPC_BASE_DISP; |
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230 break; |
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231 } |
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232 } |
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233 } else { |
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234 #endif |
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235 dst->addr_mode = MODE_PC_INDEX_DISP8; |
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236 dst->params.regs.displacement = sign_extend8(ext&0xFF); |
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237 #ifdef M68020 |
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238 } |
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239 #endif |
95
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240 break; |
2
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241 case 2: |
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242 dst->addr_mode = MODE_PC_DISPLACE; |
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243 ext = *(++cur); |
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244 dst->params.regs.displacement = sign_extend16(ext); |
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245 break; |
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246 case 4: |
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247 dst->addr_mode = MODE_IMMEDIATE; |
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248 ext = *(++cur); |
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249 switch (size) |
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250 { |
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251 case OPSIZE_BYTE: |
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252 dst->params.immed = ext & 0xFF; |
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253 break; |
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254 case OPSIZE_WORD: |
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255 dst->params.immed = ext; |
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256 break; |
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257 case OPSIZE_LONG: |
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258 dst->params.immed = ext << 16 | *(++cur); |
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259 break; |
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260 } |
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261 break; |
176
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262 default: |
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263 return NULL; |
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264 } |
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265 break; |
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266 } |
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267 return cur; |
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268 } |
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269 |
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270 uint16_t *m68k_decode_op(uint16_t *cur, uint8_t size, m68k_op_info *dst) |
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271 { |
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272 uint8_t mode = (*cur >> 3) & 0x7; |
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273 uint8_t reg = *cur & 0x7; |
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274 return m68k_decode_op_ex(cur, mode, reg, size, dst); |
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275 } |
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276 |
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277 void m68k_decode_cond(uint16_t op, m68kinst * decoded) |
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278 { |
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279 decoded->extra.cond = (op >> 0x8) & 0xF; |
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280 } |
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281 |
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282 uint8_t m68k_reg_quick_field(uint16_t op) |
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283 { |
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284 return (op >> 9) & 0x7; |
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285 } |
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286 |
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287 uint16_t * m68k_decode(uint16_t * istream, m68kinst * decoded, uint32_t address) |
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288 { |
176
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289 uint16_t *start = istream; |
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290 uint8_t optype = *istream >> 12; |
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291 uint8_t size; |
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292 uint8_t reg; |
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293 uint8_t opmode; |
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294 uint32_t immed; |
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295 decoded->op = M68K_INVALID; |
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296 decoded->src.addr_mode = decoded->dst.addr_mode = MODE_UNUSED; |
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297 decoded->variant = VAR_NORMAL; |
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298 decoded->address = address; |
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299 switch(optype) |
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300 { |
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301 case BIT_MOVEP_IMMED: |
163 | 302 if ((*istream & 0x138) == 0x108) { |
303 //MOVEP | |
304 decoded->op = M68K_MOVEP; | |
305 decoded->extra.size = *istream & 0x40 ? OPSIZE_LONG : OPSIZE_WORD; | |
306 if (*istream & 0x80) { | |
307 //memory dest | |
308 decoded->src.addr_mode = MODE_REG; | |
309 decoded->src.params.regs.pri = m68k_reg_quick_field(*istream); | |
310 decoded->dst.addr_mode = MODE_AREG_DISPLACE; | |
311 decoded->dst.params.regs.pri = *istream & 0x7; | |
312 decoded->dst.params.regs.displacement = *(++istream); | |
313 } else { | |
314 //memory source | |
315 decoded->dst.addr_mode = MODE_REG; | |
316 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream); | |
317 decoded->src.addr_mode = MODE_AREG_DISPLACE; | |
318 decoded->src.params.regs.pri = *istream & 0x7; | |
319 decoded->src.params.regs.displacement = *(++istream); | |
320 } | |
321 } else if (*istream & 0x100) { | |
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322 //BTST, BCHG, BCLR, BSET |
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323 switch ((*istream >> 6) & 0x3) |
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324 { |
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325 case 0: |
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326 decoded->op = M68K_BTST; |
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327 break; |
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328 case 1: |
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329 decoded->op = M68K_BCHG; |
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330 break; |
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331 case 2: |
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332 decoded->op = M68K_BCLR; |
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333 break; |
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334 case 3: |
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335 decoded->op = M68K_BSET; |
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336 break; |
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337 } |
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338 decoded->src.addr_mode = MODE_REG; |
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339 decoded->src.params.regs.pri = m68k_reg_quick_field(*istream); |
61
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340 decoded->extra.size = OPSIZE_BYTE; |
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341 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->dst)); |
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342 if (!istream) { |
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343 decoded->op = M68K_INVALID; |
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344 break; |
176
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345 } |
61
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346 if (decoded->dst.addr_mode == MODE_REG) { |
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347 decoded->extra.size = OPSIZE_LONG; |
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348 } |
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349 } else if ((*istream & 0xF00) == 0x800) { |
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350 //BTST, BCHG, BCLR, BSET |
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351 switch ((*istream >> 6) & 0x3) |
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352 { |
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353 case 0: |
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354 decoded->op = M68K_BTST; |
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355 break; |
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356 case 1: |
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357 decoded->op = M68K_BCHG; |
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358 break; |
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359 case 2: |
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360 decoded->op = M68K_BCLR; |
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361 break; |
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362 case 3: |
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parents:
11
diff
changeset
|
363 decoded->op = M68K_BSET; |
db60ed283d8d
Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents:
11
diff
changeset
|
364 break; |
db60ed283d8d
Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents:
11
diff
changeset
|
365 } |
db60ed283d8d
Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents:
11
diff
changeset
|
366 opmode = (*istream >> 3) & 0x7; |
db60ed283d8d
Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents:
11
diff
changeset
|
367 reg = *istream & 0x7; |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
60
diff
changeset
|
368 decoded->src.addr_mode = MODE_IMMEDIATE_WORD; |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
369 decoded->src.params.immed = *(++istream) & 0xFF; |
12
db60ed283d8d
Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents:
11
diff
changeset
|
370 decoded->extra.size = OPSIZE_BYTE; |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
60
diff
changeset
|
371 istream = m68k_decode_op_ex(istream, opmode, reg, decoded->extra.size, &(decoded->dst)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
372 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
373 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
374 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
375 } |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
60
diff
changeset
|
376 if (decoded->dst.addr_mode == MODE_REG) { |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
60
diff
changeset
|
377 decoded->extra.size = OPSIZE_LONG; |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
60
diff
changeset
|
378 } |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
379 } else if ((*istream & 0xC0) == 0xC0) { |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
380 #ifdef M68020 |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
381 //CMP2, CHK2, CAS, CAS2, RTM, CALLM |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
382 #endif |
4
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
383 } else { |
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
384 switch ((*istream >> 9) & 0x7) |
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
385 { |
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
386 case 0: |
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
387 if ((*istream & 0xFF) == 0x3C) { |
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
388 decoded->op = M68K_ORI_CCR; |
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
389 decoded->extra.size = OPSIZE_BYTE; |
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
390 decoded->src.addr_mode = MODE_IMMEDIATE; |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
391 decoded->src.params.immed = *(++istream) & 0xFF; |
4
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
392 } else if((*istream & 0xFF) == 0x7C) { |
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
393 decoded->op = M68K_ORI_SR; |
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
394 decoded->extra.size = OPSIZE_WORD; |
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
395 decoded->src.addr_mode = MODE_IMMEDIATE; |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
396 decoded->src.params.immed = *(++istream); |
4
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
397 } else { |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
398 decoded->op = M68K_OR; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
399 decoded->variant = VAR_IMMEDIATE; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
400 decoded->src.addr_mode = MODE_IMMEDIATE; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
401 decoded->extra.size = size = (*istream >> 6) & 3; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
402 reg = *istream & 0x7; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
403 opmode = (*istream >> 3) & 0x7; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
404 switch (size) |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
405 { |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
406 case OPSIZE_BYTE: |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
407 decoded->src.params.immed = *(++istream) & 0xFF; |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
408 break; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
409 case OPSIZE_WORD: |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
410 decoded->src.params.immed = *(++istream); |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
411 break; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
412 case OPSIZE_LONG: |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
413 immed = *(++istream); |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
414 decoded->src.params.immed = immed << 16 | *(++istream); |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
415 break; |
4
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
416 } |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
417 istream = m68k_decode_op_ex(istream, opmode, reg, size, &(decoded->dst)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
418 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
419 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
420 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
421 } |
4
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
422 } |
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
423 break; |
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
424 case 1: |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
425 //ANDI, ANDI to CCR, ANDI to SR |
5
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
426 if ((*istream & 0xFF) == 0x3C) { |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
427 decoded->op = M68K_ANDI_CCR; |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
428 decoded->extra.size = OPSIZE_BYTE; |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
429 decoded->src.addr_mode = MODE_IMMEDIATE; |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
430 decoded->src.params.immed = *(++istream) & 0xFF; |
5
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
431 } else if((*istream & 0xFF) == 0x7C) { |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
432 decoded->op = M68K_ANDI_SR; |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
433 decoded->extra.size = OPSIZE_WORD; |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
434 decoded->src.addr_mode = MODE_IMMEDIATE; |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
435 decoded->src.params.immed = *(++istream); |
5
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
436 } else { |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
437 decoded->op = M68K_AND; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
438 decoded->variant = VAR_IMMEDIATE; |
5
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
439 decoded->src.addr_mode = MODE_IMMEDIATE; |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
440 decoded->extra.size = size = (*istream >> 6) & 3; |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
441 reg = *istream & 0x7; |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
442 opmode = (*istream >> 3) & 0x7; |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
443 switch (size) |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
444 { |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
445 case OPSIZE_BYTE: |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
446 decoded->src.params.immed = *(++istream) & 0xFF; |
5
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
447 break; |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
448 case OPSIZE_WORD: |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
449 decoded->src.params.immed = *(++istream); |
5
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
450 break; |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
451 case OPSIZE_LONG: |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
452 immed = *(++istream); |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
453 decoded->src.params.immed = immed << 16 | *(++istream); |
5
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
454 break; |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
455 } |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
456 istream = m68k_decode_op_ex(istream, opmode, reg, size, &(decoded->dst)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
457 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
458 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
459 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
460 } |
5
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
461 } |
4
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
462 break; |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
463 case 2: |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
464 decoded->op = M68K_SUB; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
465 decoded->variant = VAR_IMMEDIATE; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
466 decoded->src.addr_mode = MODE_IMMEDIATE; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
467 decoded->extra.size = size = (*istream >> 6) & 3; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
468 reg = *istream & 0x7; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
469 opmode = (*istream >> 3) & 0x7; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
470 switch (size) |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
471 { |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
472 case OPSIZE_BYTE: |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
473 decoded->src.params.immed = *(++istream) & 0xFF; |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
474 break; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
475 case OPSIZE_WORD: |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
476 decoded->src.params.immed = *(++istream); |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
477 break; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
478 case OPSIZE_LONG: |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
479 immed = *(++istream); |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
480 decoded->src.params.immed = immed << 16 | *(++istream); |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
481 break; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
482 } |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
483 istream = m68k_decode_op_ex(istream, opmode, reg, size, &(decoded->dst)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
484 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
485 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
486 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
487 } |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
488 break; |
4
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
489 case 3: |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
490 decoded->op = M68K_ADD; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
491 decoded->variant = VAR_IMMEDIATE; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
492 decoded->src.addr_mode = MODE_IMMEDIATE; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
493 decoded->extra.size = size = (*istream >> 6) & 3; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
494 reg = *istream & 0x7; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
495 opmode = (*istream >> 3) & 0x7; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
496 switch (size) |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
497 { |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
498 case OPSIZE_BYTE: |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
499 decoded->src.params.immed = *(++istream) & 0xFF; |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
500 break; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
501 case OPSIZE_WORD: |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
502 decoded->src.params.immed = *(++istream); |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
503 break; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
504 case OPSIZE_LONG: |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
505 immed = *(++istream); |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
506 decoded->src.params.immed = immed << 16 | *(++istream); |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
507 break; |
5
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
508 } |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
509 istream = m68k_decode_op_ex(istream, opmode, reg, size, &(decoded->dst)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
510 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
511 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
512 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
513 } |
4
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
514 break; |
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
515 case 4: |
5
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
516 //BTST, BCHG, BCLR, BSET |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
517 switch ((*istream >> 6) & 0x3) |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
518 { |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
519 case 0: |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
520 decoded->op = M68K_BTST; |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
521 break; |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
522 case 1: |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
523 decoded->op = M68K_BCHG; |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
524 break; |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
525 case 2: |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
526 decoded->op = M68K_BCLR; |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
527 break; |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
528 case 3: |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
529 decoded->op = M68K_BSET; |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
530 break; |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
531 } |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
532 decoded->src.addr_mode = MODE_IMMEDIATE; |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
533 decoded->src.params.immed = *(++istream) & 0xFF; |
5
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
534 istream = m68k_decode_op(istream, OPSIZE_BYTE, &(decoded->dst)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
535 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
536 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
537 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
538 } |
4
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
539 break; |
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
540 case 5: |
5
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
541 //EORI, EORI to CCR, EORI to SR |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
542 if ((*istream & 0xFF) == 0x3C) { |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
543 decoded->op = M68K_EORI_CCR; |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
544 decoded->extra.size = OPSIZE_BYTE; |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
545 decoded->src.addr_mode = MODE_IMMEDIATE; |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
546 decoded->src.params.immed = *(++istream) & 0xFF; |
5
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
547 } else if((*istream & 0xFF) == 0x7C) { |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
548 decoded->op = M68K_EORI_SR; |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
549 decoded->extra.size = OPSIZE_WORD; |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
550 decoded->src.addr_mode = MODE_IMMEDIATE; |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
551 decoded->src.params.immed = *(++istream); |
5
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
552 } else { |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
553 decoded->op = M68K_EOR; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
554 decoded->variant = VAR_IMMEDIATE; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
555 decoded->src.addr_mode = MODE_IMMEDIATE; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
556 decoded->extra.size = size = (*istream >> 6) & 3; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
557 reg = *istream & 0x7; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
558 opmode = (*istream >> 3) & 0x7; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
559 switch (size) |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
560 { |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
561 case OPSIZE_BYTE: |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
562 decoded->src.params.immed = *(++istream) & 0xFF; |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
563 break; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
564 case OPSIZE_WORD: |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
565 decoded->src.params.immed = *(++istream); |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
566 break; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
567 case OPSIZE_LONG: |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
568 immed = *(++istream); |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
569 decoded->src.params.immed = immed << 16 | *(++istream); |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
570 break; |
5
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
571 } |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
572 istream = m68k_decode_op_ex(istream, opmode, reg, size, &(decoded->dst)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
573 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
574 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
575 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
576 } |
5
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
577 } |
4
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
578 break; |
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
579 case 6: |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
580 decoded->op = M68K_CMP; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
581 decoded->variant = VAR_IMMEDIATE; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
582 decoded->extra.size = (*istream >> 6) & 0x3; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
583 decoded->src.addr_mode = MODE_IMMEDIATE; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
584 reg = *istream & 0x7; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
585 opmode = (*istream >> 3) & 0x7; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
586 switch (decoded->extra.size) |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
587 { |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
588 case OPSIZE_BYTE: |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
589 decoded->src.params.immed = *(++istream) & 0xFF; |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
590 break; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
591 case OPSIZE_WORD: |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
592 decoded->src.params.immed = *(++istream); |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
593 break; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
594 case OPSIZE_LONG: |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
595 immed = *(++istream); |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
596 decoded->src.params.immed = (immed << 16) | *(++istream); |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
597 break; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
598 } |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
599 istream = m68k_decode_op_ex(istream, opmode, reg, decoded->extra.size, &(decoded->dst)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
600 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
601 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
602 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
603 } |
4
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
604 break; |
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
605 case 7: |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
606 #ifdef M68010 |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
607 decoded->op = M68K_MOVES; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
608 decoded->extra.size = *istream >> 6 & 0x3; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
609 immed = *(++istream); |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
610 reg = immed >> 12 & 0x7; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
611 opmode = immed & 0x8000 ? MODE_AREG : MODE_REG; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
612 if (immed & 0x800) { |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
613 m68k_decode_op_ex(istream, *start >> 3 & 0x7, *start & 0x7, decoded->extra.size, &(decoded->src)); |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
614 decoded->dst.addr_mode = opmode; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
615 decoded->dst.params.regs.pri = reg; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
616 } else { |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
617 decoded->src.addr_mode = opmode; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
618 decoded->src.params.regs.pri = reg; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
619 m68k_decode_op_ex(istream, *start >> 3 & 0x7, *start & 0x7, decoded->extra.size, &(decoded->dst)); |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
620 } |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
621 #endif |
4
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
622 break; |
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
623 } |
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
624 } |
0
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
625 break; |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
626 case MOVE_BYTE: |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
627 case MOVE_LONG: |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
628 case MOVE_WORD: |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
629 decoded->op = M68K_MOVE; |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
630 decoded->extra.size = optype == MOVE_BYTE ? OPSIZE_BYTE : (optype == MOVE_WORD ? OPSIZE_WORD : OPSIZE_LONG); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
631 opmode = (*istream >> 6) & 0x7; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
632 reg = m68k_reg_quick_field(*istream); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
633 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
634 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
635 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
636 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
637 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
638 istream = m68k_decode_op_ex(istream, opmode, reg, decoded->extra.size, &(decoded->dst)); |
197
7c227a8ec53d
Add instruction address logging to translator and support for reading an address log to the disassembler
Mike Pavone <pavone@retrodev.com>
parents:
184
diff
changeset
|
639 if (!istream || decoded->dst.addr_mode == MODE_IMMEDIATE) { |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
640 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
641 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
642 } |
0
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
643 break; |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
644 case MISC: |
518
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
645 |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
646 if ((*istream & 0x1C0) == 0x1C0) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
647 decoded->op = M68K_LEA; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
648 decoded->extra.size = OPSIZE_LONG; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
649 decoded->dst.addr_mode = MODE_AREG; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
650 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
651 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
652 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
653 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
654 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
655 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
656 } else { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
657 if (*istream & 0x100) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
658 decoded->op = M68K_CHK; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
659 if ((*istream & 0x180) == 0x180) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
660 decoded->extra.size = OPSIZE_WORD; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
661 } else { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
662 //only on M68020+ |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
663 #ifdef M68020 |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
664 decoded->extra.size = OPSIZE_LONG; |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
665 #else |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
666 decoded->op = M68K_INVALID; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
667 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
668 #endif |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
669 } |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
670 decoded->dst.addr_mode = MODE_REG; |
325
8db584faac4b
Fixed decoding of CHK destination
Mike Pavone <pavone@retrodev.com>
parents:
208
diff
changeset
|
671 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
672 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
673 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
674 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
675 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
676 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
677 } else { |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
678 opmode = (*istream >> 3) & 0x7; |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
60
diff
changeset
|
679 if ((*istream & 0xB80) == 0x880 && opmode != MODE_REG && opmode != MODE_AREG) { |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
60
diff
changeset
|
680 //TODO: Check for invalid modes that are dependent on direction |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
681 decoded->op = M68K_MOVEM; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
682 decoded->extra.size = *istream & 0x40 ? OPSIZE_LONG : OPSIZE_WORD; |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
683 reg = *istream & 0x7; |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
684 if(*istream & 0x400) { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
685 decoded->dst.addr_mode = MODE_REG; |
68
1c9a4052a2c0
Fix decoding and disassembly of MOVEM
Mike Pavone <pavone@retrodev.com>
parents:
62
diff
changeset
|
686 decoded->dst.params.immed = *(++istream); |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
687 istream = m68k_decode_op_ex(istream, opmode, reg, decoded->extra.size, &(decoded->src)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
688 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
689 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
690 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
691 } |
412
00d5a2b532f4
Fix movem with pc displacement or pc indexed source
Mike Pavone <pavone@retrodev.com>
parents:
325
diff
changeset
|
692 if (decoded->src.addr_mode == MODE_PC_DISPLACE || decoded->src.addr_mode == MODE_PC_INDEX_DISP8) { |
00d5a2b532f4
Fix movem with pc displacement or pc indexed source
Mike Pavone <pavone@retrodev.com>
parents:
325
diff
changeset
|
693 //adjust displacement to account for extra instruction word |
00d5a2b532f4
Fix movem with pc displacement or pc indexed source
Mike Pavone <pavone@retrodev.com>
parents:
325
diff
changeset
|
694 decoded->src.params.regs.displacement += 2; |
00d5a2b532f4
Fix movem with pc displacement or pc indexed source
Mike Pavone <pavone@retrodev.com>
parents:
325
diff
changeset
|
695 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
696 } else { |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
697 decoded->src.addr_mode = MODE_REG; |
68
1c9a4052a2c0
Fix decoding and disassembly of MOVEM
Mike Pavone <pavone@retrodev.com>
parents:
62
diff
changeset
|
698 decoded->src.params.immed = *(++istream); |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
699 istream = m68k_decode_op_ex(istream, opmode, reg, decoded->extra.size, &(decoded->dst)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
700 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
701 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
702 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
703 } |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
704 } |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
705 } else { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
706 optype = (*istream >> 9) & 0x7; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
707 size = (*istream >> 6) & 0x3; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
708 switch(optype) |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
709 { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
710 case 0: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
711 //Move from SR or NEGX |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
712 if (size == OPSIZE_INVALID) { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
713 decoded->op = M68K_MOVE_FROM_SR; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
714 size = OPSIZE_WORD; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
715 } else { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
716 decoded->op = M68K_NEGX; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
717 } |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
718 decoded->extra.size = size; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
719 istream= m68k_decode_op(istream, size, &(decoded->dst)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
720 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
721 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
722 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
723 } |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
724 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
725 case 1: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
726 //MOVE from CCR or CLR |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
727 if (size == OPSIZE_INVALID) { |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
728 #ifdef M68010 |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
729 decoded->op = M68K_MOVE_FROM_CCR; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
730 size = OPSIZE_WORD; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
731 #else |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
732 break; |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
733 #endif |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
734 } else { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
735 decoded->op = M68K_CLR; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
736 } |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
737 decoded->extra.size = size; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
738 istream= m68k_decode_op(istream, size, &(decoded->dst)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
739 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
740 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
741 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
742 } |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
743 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
744 case 2: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
745 //MOVE to CCR or NEG |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
746 if (size == OPSIZE_INVALID) { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
747 decoded->op = M68K_MOVE_CCR; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
748 size = OPSIZE_WORD; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
749 istream= m68k_decode_op(istream, size, &(decoded->src)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
750 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
751 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
752 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
753 } |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
754 } else { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
755 decoded->op = M68K_NEG; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
756 istream= m68k_decode_op(istream, size, &(decoded->dst)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
757 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
758 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
759 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
760 } |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
761 } |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
762 decoded->extra.size = size; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
763 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
764 case 3: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
765 //MOVE to SR or NOT |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
766 if (size == OPSIZE_INVALID) { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
767 decoded->op = M68K_MOVE_SR; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
768 size = OPSIZE_WORD; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
769 istream= m68k_decode_op(istream, size, &(decoded->src)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
770 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
771 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
772 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
773 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
774 } else { |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
775 decoded->op = M68K_NOT; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
776 istream= m68k_decode_op(istream, size, &(decoded->dst)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
777 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
778 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
779 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
780 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
781 } |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
782 decoded->extra.size = size; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
783 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
784 case 4: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
785 //EXT, EXTB, LINK.l, NBCD, SWAP, BKPT, PEA |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
786 switch((*istream >> 3) & 0x3F) |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
787 { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
788 case 1: |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
789 #ifdef M68020 |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
790 decoded->op = M68K_LINK; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
791 decoded->extra.size = OPSIZE_LONG; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
792 reg = *istream & 0x7; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
793 immed = *(++istream) << 16; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
794 immed |= *(++istream); |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
795 #endif |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
796 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
797 case 8: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
798 decoded->op = M68K_SWAP; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
799 decoded->src.addr_mode = MODE_REG; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
800 decoded->src.params.regs.pri = *istream & 0x7; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
801 decoded->extra.size = OPSIZE_WORD; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
802 break; |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
803 case 9: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
804 #ifdef M68010 |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
805 decoded->op = M68K_BKPT; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
806 decoded->src.addr_mode = MODE_IMMEDIATE; |
10
4553fc97b15e
Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special cases
Mike Pavone <pavone@retrodev.com>
parents:
9
diff
changeset
|
807 decoded->extra.size = OPSIZE_UNSIZED; |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
808 decoded->src.params.immed = *istream & 0x7; |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
809 #endif |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
810 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
811 case 0x10: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
812 decoded->op = M68K_EXT; |
93
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
91
diff
changeset
|
813 decoded->dst.addr_mode = MODE_REG; |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
91
diff
changeset
|
814 decoded->dst.params.regs.pri = *istream & 0x7; |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
815 decoded->extra.size = OPSIZE_WORD; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
816 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
817 case 0x18: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
818 decoded->op = M68K_EXT; |
93
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
91
diff
changeset
|
819 decoded->dst.addr_mode = MODE_REG; |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
91
diff
changeset
|
820 decoded->dst.params.regs.pri = *istream & 0x7; |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
821 decoded->extra.size = OPSIZE_LONG; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
822 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
823 case 0x38: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
824 #ifdef M68020 |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
825 #endif |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
826 break; |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
827 default: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
828 if (!(*istream & 0x1C0)) { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
829 decoded->op = M68K_NBCD; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
830 decoded->extra.size = OPSIZE_BYTE; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
831 istream = m68k_decode_op(istream, OPSIZE_BYTE, &(decoded->dst)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
832 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
833 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
834 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
835 } |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
836 } else if((*istream & 0x1C0) == 0x40) { |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
837 decoded->op = M68K_PEA; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
838 decoded->extra.size = OPSIZE_LONG; |
116
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
111
diff
changeset
|
839 istream = m68k_decode_op(istream, OPSIZE_LONG, &(decoded->src)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
840 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
841 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
842 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
843 } |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
844 } |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
845 } |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
846 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
847 case 5: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
848 //BGND, ILLEGAL, TAS, TST |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
849 optype = *istream & 0xFF; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
850 if (optype == 0xFA) { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
851 //BGND - CPU32 only |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
852 } else if (optype == 0xFC) { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
853 decoded->op = M68K_ILLEGAL; |
10
4553fc97b15e
Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special cases
Mike Pavone <pavone@retrodev.com>
parents:
9
diff
changeset
|
854 decoded->extra.size = OPSIZE_UNSIZED; |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
855 } else { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
856 if (size == OPSIZE_INVALID) { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
857 decoded->op = M68K_TAS; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
858 } else { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
859 decoded->op = M68K_TST; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
860 decoded->extra.size = size; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
861 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
862 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
863 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
864 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
865 } |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
866 } |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
867 } |
518
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
868 break; |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
869 case 6: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
870 //MULU, MULS, DIVU, DIVUL, DIVS, DIVSL |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
871 #ifdef M68020 |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
872 //TODO: Implement these for 68020+ support |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
873 #endif |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
874 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
875 case 7: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
876 //TRAP, LINK.w, UNLNK, MOVE USP, RESET, NOP, STOP, RTE, RTD, RTS, TRAPV, RTR, MOVEC, JSR, JMP |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
877 if (*istream & 0x80) { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
878 //JSR, JMP |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
879 if (*istream & 0x40) { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
880 decoded->op = M68K_JMP; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
881 } else { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
882 decoded->op = M68K_JSR; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
883 } |
10
4553fc97b15e
Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special cases
Mike Pavone <pavone@retrodev.com>
parents:
9
diff
changeset
|
884 decoded->extra.size = OPSIZE_UNSIZED; |
4553fc97b15e
Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special cases
Mike Pavone <pavone@retrodev.com>
parents:
9
diff
changeset
|
885 istream = m68k_decode_op(istream, OPSIZE_UNSIZED, &(decoded->src)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
886 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
887 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
888 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
889 } |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
890 } else { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
891 //it would appear bit 6 needs to be set for it to be a valid instruction here |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
892 switch((*istream >> 3) & 0x7) |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
893 { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
894 case 0: |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
895 case 1: |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
896 //TRAP |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
897 decoded->op = M68K_TRAP; |
10
4553fc97b15e
Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special cases
Mike Pavone <pavone@retrodev.com>
parents:
9
diff
changeset
|
898 decoded->extra.size = OPSIZE_UNSIZED; |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
899 decoded->src.addr_mode = MODE_IMMEDIATE; |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
900 decoded->src.params.immed = *istream & 0xF; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
901 break; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
902 case 2: |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
903 //LINK.w |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
904 decoded->op = M68K_LINK; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
905 decoded->extra.size = OPSIZE_WORD; |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
906 decoded->src.addr_mode = MODE_AREG; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
907 decoded->src.params.regs.pri = *istream & 0x7; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
908 decoded->dst.addr_mode = MODE_IMMEDIATE; |
93
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
91
diff
changeset
|
909 decoded->dst.params.immed = sign_extend16(*(++istream)); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
910 break; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
911 case 3: |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
912 //UNLK |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
913 decoded->op = M68K_UNLK; |
10
4553fc97b15e
Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special cases
Mike Pavone <pavone@retrodev.com>
parents:
9
diff
changeset
|
914 decoded->extra.size = OPSIZE_UNSIZED; |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
915 decoded->dst.addr_mode = MODE_AREG; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
916 decoded->dst.params.regs.pri = *istream & 0x7; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
917 break; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
918 case 4: |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
919 case 5: |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
920 //MOVE USP |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
921 decoded->op = M68K_MOVE_USP; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
922 if (*istream & 0x8) { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
923 decoded->dst.addr_mode = MODE_AREG; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
924 decoded->dst.params.regs.pri = *istream & 0x7; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
925 } else { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
926 decoded->src.addr_mode = MODE_AREG; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
927 decoded->src.params.regs.pri = *istream & 0x7; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
928 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
929 break; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
930 case 6: |
10
4553fc97b15e
Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special cases
Mike Pavone <pavone@retrodev.com>
parents:
9
diff
changeset
|
931 decoded->extra.size = OPSIZE_UNSIZED; |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
932 switch(*istream & 0x7) |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
933 { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
934 case 0: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
935 decoded->op = M68K_RESET; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
936 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
937 case 1: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
938 decoded->op = M68K_NOP; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
939 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
940 case 2: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
941 decoded->op = M68K_STOP; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
942 decoded->src.addr_mode = MODE_IMMEDIATE; |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
943 decoded->src.params.immed =*(++istream); |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
944 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
945 case 3: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
946 decoded->op = M68K_RTE; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
947 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
948 case 4: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
949 #ifdef M68010 |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
950 decoded->op = M68K_RTD; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
951 decoded->src.addr_mode = MODE_IMMEDIATE; |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
952 decoded->src.params.immed =*(++istream); |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
953 #endif |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
954 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
955 case 5: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
956 decoded->op = M68K_RTS; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
957 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
958 case 6: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
959 decoded->op = M68K_TRAPV; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
960 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
961 case 7: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
962 decoded->op = M68K_RTR; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
963 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
964 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
965 break; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
966 case 7: |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
967 //MOVEC |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
968 #ifdef M68010 |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
969 decoded->op = M68K_MOVEC; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
970 immed = *(++istream); |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
971 reg = immed >> 12 & 0x7; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
972 opmode = immed & 0x8000 ? MODE_AREG : MODE_REG; |
641 | 973 immed &= 0xFFF; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
974 if (immed & 0x800) { |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
975 if (immed > MAX_HIGH_CR) { |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
976 decoded->op = M68K_INVALID; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
977 break; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
978 } else { |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
979 immed = immed - 0x800 + CR_USP; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
980 } |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
981 } else { |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
982 if (immed > MAX_LOW_CR) { |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
983 decoded->op = M68K_INVALID; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
984 break; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
985 } |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
986 } |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
987 if (*start & 1) { |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
988 decoded->src.addr_mode = opmode; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
989 decoded->src.params.regs.pri = reg; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
990 decoded->dst.params.immed = immed; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
991 } else { |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
992 decoded->dst.addr_mode = opmode; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
993 decoded->dst.params.regs.pri = reg; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
994 decoded->src.params.immed = immed; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
995 } |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
996 #endif |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
997 break; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
998 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
999 } |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1000 break; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1001 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1002 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1003 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1004 } |
0
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1005 break; |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1006 case QUICK_ARITH_LOOP: |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1007 size = (*istream >> 6) & 3; |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1008 if (size == 0x3) { |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1009 //DBcc, TRAPcc or Scc |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1010 m68k_decode_cond(*istream, decoded); |
111 | 1011 if (((*istream >> 3) & 0x7) == 1) { |
0
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1012 decoded->op = M68K_DBCC; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1013 decoded->src.addr_mode = MODE_IMMEDIATE; |
0
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1014 decoded->dst.addr_mode = MODE_REG; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1015 decoded->dst.params.regs.pri = *istream & 0x7; |
46
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
18
diff
changeset
|
1016 decoded->src.params.immed = sign_extend16(*(++istream)); |
111 | 1017 } else if(((*istream >> 3) & 0x7) == 1 && (*istream & 0x7) > 1 && (*istream & 0x7) < 5) { |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1018 #ifdef M68020 |
0
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1019 decoded->op = M68K_TRAPCC; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1020 decoded->src.addr_mode = MODE_IMMEDIATE; |
0
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1021 //TODO: Figure out what to do with OPMODE and optional extention words |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1022 #endif |
111 | 1023 } else { |
0
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1024 decoded->op = M68K_SCC; |
111 | 1025 decoded->extra.cond = (*istream >> 8) & 0xF; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1026 istream = m68k_decode_op(istream, OPSIZE_BYTE, &(decoded->dst)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1027 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1028 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1029 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1030 } |
0
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1031 } |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1032 } else { |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1033 //ADDQ, SUBQ |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1034 decoded->variant = VAR_QUICK; |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1035 decoded->extra.size = size; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1036 decoded->src.addr_mode = MODE_IMMEDIATE; |
91
8c446fc19cc0
Fix decoding bug in addq/subq
Mike Pavone <pavone@retrodev.com>
parents:
90
diff
changeset
|
1037 immed = m68k_reg_quick_field(*istream); |
0
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1038 if (!immed) { |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1039 immed = 8; |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1040 } |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
1041 decoded->src.params.immed = immed; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1042 if (*istream & 0x100) { |
0
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1043 decoded->op = M68K_SUB; |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1044 } else { |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1045 decoded->op = M68K_ADD; |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1046 } |
94
a668a35a3463
Fix decoding bug for addq/subq
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
1047 istream = m68k_decode_op(istream, size, &(decoded->dst)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1048 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1049 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1050 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1051 } |
0
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1052 } |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1053 break; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1054 case BRANCH: |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1055 m68k_decode_cond(*istream, decoded); |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1056 decoded->op = decoded->extra.cond == COND_FALSE ? M68K_BSR : M68K_BCC; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1057 decoded->src.addr_mode = MODE_IMMEDIATE; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1058 immed = *istream & 0xFF; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1059 if (immed == 0) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1060 decoded->variant = VAR_WORD; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1061 immed = *(++istream); |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1062 immed = sign_extend16(immed); |
154
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
140
diff
changeset
|
1063 #ifdef M68020 |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1064 } else if (immed == 0xFF) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1065 decoded->variant = VAR_LONG; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1066 immed = *(++istream) << 16; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1067 immed |= *(++istream); |
154
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
140
diff
changeset
|
1068 #endif |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1069 } else { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1070 decoded->variant = VAR_BYTE; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1071 immed = sign_extend8(immed); |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1072 } |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
1073 decoded->src.params.immed = immed; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1074 break; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1075 case MOVEQ: |
208
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
197
diff
changeset
|
1076 if (*istream & 0x100) { |
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
197
diff
changeset
|
1077 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1078 break; |
208
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
197
diff
changeset
|
1079 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1080 decoded->op = M68K_MOVE; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1081 decoded->variant = VAR_QUICK; |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
1082 decoded->extra.size = OPSIZE_LONG; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1083 decoded->src.addr_mode = MODE_IMMEDIATE; |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
1084 decoded->src.params.immed = sign_extend8(*istream & 0xFF); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1085 decoded->dst.addr_mode = MODE_REG; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
1086 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1087 immed = *istream & 0xFF; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1088 break; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1089 case OR_DIV_SBCD: |
11
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1090 //for OR, if opmode bit 2 is 1, then src = Dn, dst = <ea> |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1091 opmode = (*istream >> 6) & 0x7; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1092 size = opmode & 0x3; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1093 if (size == OPSIZE_INVALID || (opmode & 0x4 && !(*istream & 0x30))) { |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1094 switch(opmode) |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1095 { |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1096 case 3: |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1097 decoded->op = M68K_DIVU; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1098 decoded->extra.size = OPSIZE_WORD; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1099 decoded->dst.addr_mode = MODE_REG; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1100 decoded->dst.params.regs.pri = (*istream >> 9) & 0x7; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1101 istream = m68k_decode_op(istream, OPSIZE_WORD, &(decoded->src)); |
183
2f08d9e90a4c
Fix (a7)+ src when size is byte, fix trap return address, make div with areg src decoded to invalid
Mike Pavone <pavone@retrodev.com>
parents:
181
diff
changeset
|
1102 if (!istream || decoded->src.addr_mode == MODE_AREG) { |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1103 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1104 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1105 } |
11
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1106 break; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1107 case 4: |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1108 decoded->op = M68K_SBCD; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1109 decoded->dst.addr_mode = decoded->src.addr_mode = *istream & 0x8 ? MODE_AREG_PREDEC : MODE_REG; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1110 decoded->src.params.regs.pri = *istream & 0x7; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1111 decoded->dst.params.regs.pri = (*istream >> 9) & 0x7; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1112 break; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1113 case 5: |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1114 #ifdef M68020 |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1115 #endif |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1116 break; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1117 case 6: |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1118 #ifdef M68020 |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1119 #endif |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1120 break; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1121 case 7: |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1122 decoded->op = M68K_DIVS; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1123 decoded->extra.size = OPSIZE_WORD; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1124 decoded->dst.addr_mode = MODE_REG; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1125 decoded->dst.params.regs.pri = (*istream >> 9) & 0x7; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1126 istream = m68k_decode_op(istream, OPSIZE_WORD, &(decoded->src)); |
183
2f08d9e90a4c
Fix (a7)+ src when size is byte, fix trap return address, make div with areg src decoded to invalid
Mike Pavone <pavone@retrodev.com>
parents:
181
diff
changeset
|
1127 if (!istream || decoded->src.addr_mode == MODE_AREG) { |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1128 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1129 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1130 } |
518
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1131 break; |
11
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1132 } |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1133 } else { |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1134 decoded->op = M68K_OR; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1135 decoded->extra.size = size; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1136 if (opmode & 0x4) { |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1137 decoded->src.addr_mode = MODE_REG; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1138 decoded->src.params.regs.pri = (*istream >> 9) & 0x7; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1139 istream = m68k_decode_op(istream, size, &(decoded->dst)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1140 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1141 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1142 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1143 } |
11
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1144 } else { |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1145 decoded->dst.addr_mode = MODE_REG; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1146 decoded->dst.params.regs.pri = (*istream >> 9) & 0x7; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1147 istream = m68k_decode_op(istream, size, &(decoded->src)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1148 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1149 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1150 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1151 } |
11
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1152 } |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1153 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1154 break; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1155 case SUB_SUBX: |
101
d7789186ba5e
Some fixes to add/addx sub/subx decoding
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
1156 size = (*istream >> 6) & 0x3; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1157 decoded->op = M68K_SUB; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1158 if (*istream & 0x100) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1159 //<ea> destination, SUBA.l or SUBX |
101
d7789186ba5e
Some fixes to add/addx sub/subx decoding
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
1160 if (*istream & 0x30 || size == OPSIZE_INVALID) { |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1161 if (size == OPSIZE_INVALID) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1162 //SUBA.l |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1163 decoded->extra.size = OPSIZE_LONG; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1164 decoded->dst.addr_mode = MODE_AREG; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
1165 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1166 istream = m68k_decode_op(istream, OPSIZE_LONG, &(decoded->src)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1167 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1168 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1169 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1170 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1171 } else { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1172 decoded->extra.size = size; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1173 decoded->src.addr_mode = MODE_REG; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
1174 decoded->src.params.regs.pri = m68k_reg_quick_field(*istream); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1175 istream = m68k_decode_op(istream, size, &(decoded->dst)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1176 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1177 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1178 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1179 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1180 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1181 } else { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1182 //SUBX |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1183 decoded->op = M68K_SUBX; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1184 decoded->extra.size = size; |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1185 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1186 decoded->src.params.regs.pri = *istream & 0x7; |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1187 if (*istream & 0x8) { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1188 decoded->dst.addr_mode = decoded->src.addr_mode = MODE_AREG_PREDEC; |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1189 } else { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1190 decoded->dst.addr_mode = decoded->src.addr_mode = MODE_REG; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1191 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1192 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1193 } else { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1194 if (size == OPSIZE_INVALID) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1195 //SUBA.w |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1196 decoded->extra.size = OPSIZE_WORD; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1197 decoded->dst.addr_mode = MODE_AREG; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1198 } else { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1199 decoded->extra.size = size; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1200 decoded->dst.addr_mode = MODE_REG; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1201 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
1202 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1203 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1204 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1205 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1206 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1207 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1208 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1209 break; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1210 case RESERVED: |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1211 break; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1212 case CMP_XOR: |
120 | 1213 size = (*istream >> 6) & 0x3; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1214 decoded->op = M68K_CMP; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1215 if (*istream & 0x100) { |
120 | 1216 //CMPM or CMPA.l or EOR |
1217 if (size == OPSIZE_INVALID) { | |
1218 decoded->extra.size = OPSIZE_LONG; | |
1219 decoded->dst.addr_mode = MODE_AREG; | |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
1220 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream); |
136
e64554246d11
Fix some bugs in decoding cmp
Mike Pavone <pavone@retrodev.com>
parents:
134
diff
changeset
|
1221 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1222 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1223 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1224 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1225 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1226 } else { |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1227 reg = m68k_reg_quick_field(*istream); |
120 | 1228 istream = m68k_decode_op(istream, size, &(decoded->dst)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1229 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1230 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1231 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1232 } |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
176
diff
changeset
|
1233 decoded->extra.size = size; |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
176
diff
changeset
|
1234 if (decoded->dst.addr_mode == MODE_AREG) { |
120 | 1235 //CMPM |
1236 decoded->src.addr_mode = decoded->dst.addr_mode = MODE_AREG_POSTINC; | |
1237 decoded->src.params.regs.pri = decoded->dst.params.regs.pri; | |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1238 decoded->dst.params.regs.pri = reg; |
120 | 1239 } else { |
1240 //EOR | |
1241 decoded->op = M68K_EOR; | |
1242 decoded->src.addr_mode = MODE_REG; | |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1243 decoded->src.params.regs.pri = reg; |
120 | 1244 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1245 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1246 } else { |
120 | 1247 //CMP or CMPA.w |
1248 if (size == OPSIZE_INVALID) { | |
1249 decoded->extra.size = OPSIZE_WORD; | |
1250 decoded->dst.addr_mode = MODE_AREG; | |
1251 } else { | |
1252 decoded->extra.size = size; | |
1253 decoded->dst.addr_mode = MODE_REG; | |
1254 } | |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
1255 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream); |
136
e64554246d11
Fix some bugs in decoding cmp
Mike Pavone <pavone@retrodev.com>
parents:
134
diff
changeset
|
1256 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1257 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1258 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1259 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1260 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1261 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1262 break; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1263 case AND_MUL_ABCD_EXG: |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1264 //page 575 for summary |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1265 //EXG opmodes: |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1266 //01000 -data regs |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1267 //01001 -addr regs |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1268 //10001 -one of each |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1269 //AND opmodes: |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1270 //operand order bit + 2 size bits (00 - 10) |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1271 //no address register direct addressing |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1272 //data register direct not allowed when <ea> is the source (operand order bit of 1) |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1273 if (*istream & 0x100) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1274 if ((*istream & 0xC0) == 0xC0) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1275 decoded->op = M68K_MULS; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1276 decoded->extra.size = OPSIZE_WORD; |
3
a4ad0e3e3e0e
Finish mulu.w, muls.w and abcd parameter decoding
Mike Pavone <pavone@retrodev.com>
parents:
2
diff
changeset
|
1277 decoded->dst.addr_mode = MODE_REG; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
1278 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1279 istream = m68k_decode_op(istream, OPSIZE_WORD, &(decoded->src)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1280 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1281 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1282 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1283 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1284 } else if(!(*istream & 0xF0)) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1285 decoded->op = M68K_ABCD; |
3
a4ad0e3e3e0e
Finish mulu.w, muls.w and abcd parameter decoding
Mike Pavone <pavone@retrodev.com>
parents:
2
diff
changeset
|
1286 decoded->extra.size = OPSIZE_BYTE; |
a4ad0e3e3e0e
Finish mulu.w, muls.w and abcd parameter decoding
Mike Pavone <pavone@retrodev.com>
parents:
2
diff
changeset
|
1287 decoded->src.params.regs.pri = *istream & 0x7; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
1288 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream); |
3
a4ad0e3e3e0e
Finish mulu.w, muls.w and abcd parameter decoding
Mike Pavone <pavone@retrodev.com>
parents:
2
diff
changeset
|
1289 decoded->dst.addr_mode = decoded->src.addr_mode = (*istream & 8) ? MODE_AREG_PREDEC : MODE_REG; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1290 } else if(!(*istream & 0x30)) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1291 decoded->op = M68K_EXG; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1292 decoded->extra.size = OPSIZE_LONG; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
1293 decoded->src.params.regs.pri = m68k_reg_quick_field(*istream); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1294 decoded->dst.params.regs.pri = *istream & 0x7; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1295 if (*istream & 0x8) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1296 if (*istream & 0x80) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1297 decoded->src.addr_mode = MODE_REG; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1298 decoded->dst.addr_mode = MODE_AREG; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1299 } else { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1300 decoded->src.addr_mode = decoded->dst.addr_mode = MODE_AREG; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1301 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1302 } else { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1303 decoded->src.addr_mode = decoded->dst.addr_mode = MODE_REG; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1304 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1305 } else { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1306 decoded->op = M68K_AND; |
90 | 1307 decoded->extra.size = (*istream >> 6) & 0x3; |
60
6ffea8607730
Fix operand order for AND instructions
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1308 decoded->src.addr_mode = MODE_REG; |
6ffea8607730
Fix operand order for AND instructions
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1309 decoded->src.params.regs.pri = m68k_reg_quick_field(*istream); |
6ffea8607730
Fix operand order for AND instructions
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1310 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->dst)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1311 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1312 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1313 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1314 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1315 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1316 } else { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1317 if ((*istream & 0xC0) == 0xC0) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1318 decoded->op = M68K_MULU; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1319 decoded->extra.size = OPSIZE_WORD; |
3
a4ad0e3e3e0e
Finish mulu.w, muls.w and abcd parameter decoding
Mike Pavone <pavone@retrodev.com>
parents:
2
diff
changeset
|
1320 decoded->dst.addr_mode = MODE_REG; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
1321 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1322 istream = m68k_decode_op(istream, OPSIZE_WORD, &(decoded->src)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1323 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1324 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1325 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1326 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1327 } else { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1328 decoded->op = M68K_AND; |
90 | 1329 decoded->extra.size = (*istream >> 6) & 0x3; |
60
6ffea8607730
Fix operand order for AND instructions
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1330 decoded->dst.addr_mode = MODE_REG; |
6ffea8607730
Fix operand order for AND instructions
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1331 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream); |
6ffea8607730
Fix operand order for AND instructions
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1332 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1333 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1334 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1335 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1336 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1337 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1338 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1339 break; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1340 case ADD_ADDX: |
101
d7789186ba5e
Some fixes to add/addx sub/subx decoding
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
1341 size = (*istream >> 6) & 0x3; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1342 decoded->op = M68K_ADD; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1343 if (*istream & 0x100) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1344 //<ea> destination, ADDA.l or ADDX |
101
d7789186ba5e
Some fixes to add/addx sub/subx decoding
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
1345 if (*istream & 0x30 || size == OPSIZE_INVALID) { |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1346 if (size == OPSIZE_INVALID) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1347 //ADDA.l |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1348 decoded->extra.size = OPSIZE_LONG; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1349 decoded->dst.addr_mode = MODE_AREG; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
1350 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1351 istream = m68k_decode_op(istream, OPSIZE_LONG, &(decoded->src)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1352 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1353 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1354 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1355 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1356 } else { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1357 decoded->extra.size = size; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1358 decoded->src.addr_mode = MODE_REG; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
1359 decoded->src.params.regs.pri = m68k_reg_quick_field(*istream); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1360 istream = m68k_decode_op(istream, size, &(decoded->dst)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1361 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1362 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1363 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1364 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1365 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1366 } else { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1367 //ADDX |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1368 decoded->op = M68K_ADDX; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1369 decoded->extra.size = size; |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1370 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1371 decoded->src.params.regs.pri = *istream & 0x7; |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1372 if (*istream & 0x8) { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1373 decoded->dst.addr_mode = decoded->src.addr_mode = MODE_AREG_PREDEC; |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1374 } else { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1375 decoded->dst.addr_mode = decoded->src.addr_mode = MODE_REG; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1376 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1377 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1378 } else { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1379 if (size == OPSIZE_INVALID) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1380 //ADDA.w |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1381 decoded->extra.size = OPSIZE_WORD; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1382 decoded->dst.addr_mode = MODE_AREG; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1383 } else { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1384 decoded->extra.size = size; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1385 decoded->dst.addr_mode = MODE_REG; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1386 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
1387 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1388 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1389 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1390 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1391 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1392 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1393 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1394 break; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1395 case SHIFT_ROTATE: |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1396 if ((*istream & 0x8C0) == 0xC0) { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1397 switch((*istream >> 8) & 0x7) |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1398 { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1399 case 0: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1400 decoded->op = M68K_ASR; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1401 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1402 case 1: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1403 decoded->op = M68K_ASL; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1404 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1405 case 2: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1406 decoded->op = M68K_LSR; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1407 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1408 case 3: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1409 decoded->op = M68K_LSL; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1410 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1411 case 4: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1412 decoded->op = M68K_ROXR; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1413 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1414 case 5: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1415 decoded->op = M68K_ROXL; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1416 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1417 case 6: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1418 decoded->op = M68K_ROR; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1419 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1420 case 7: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1421 decoded->op = M68K_ROL; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1422 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1423 } |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1424 decoded->extra.size = OPSIZE_WORD; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1425 istream = m68k_decode_op(istream, OPSIZE_WORD, &(decoded->dst)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1426 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1427 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1428 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1429 } |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1430 } else if((*istream & 0xC0) != 0xC0) { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1431 switch(((*istream >> 2) & 0x6) | ((*istream >> 8) & 1)) |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1432 { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1433 case 0: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1434 decoded->op = M68K_ASR; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1435 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1436 case 1: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1437 decoded->op = M68K_ASL; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1438 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1439 case 2: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1440 decoded->op = M68K_LSR; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1441 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1442 case 3: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1443 decoded->op = M68K_LSL; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1444 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1445 case 4: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1446 decoded->op = M68K_ROXR; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1447 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1448 case 5: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1449 decoded->op = M68K_ROXL; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1450 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1451 case 6: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1452 decoded->op = M68K_ROR; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1453 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1454 case 7: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1455 decoded->op = M68K_ROL; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1456 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1457 } |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1458 decoded->extra.size = (*istream >> 6) & 0x3; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1459 immed = (*istream >> 9) & 0x7; |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
50
diff
changeset
|
1460 if (*istream & 0x20) { |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1461 decoded->src.addr_mode = MODE_REG; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1462 decoded->src.params.regs.pri = immed; |
50
4836d1f3841a
Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1463 } else { |
4836d1f3841a
Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1464 decoded->src.addr_mode = MODE_IMMEDIATE; |
4836d1f3841a
Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1465 if (!immed) { |
4836d1f3841a
Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1466 immed = 8; |
4836d1f3841a
Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1467 } |
4836d1f3841a
Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1468 decoded->src.params.immed = immed; |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1469 } |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1470 decoded->dst.addr_mode = MODE_REG; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1471 decoded->dst.params.regs.pri = *istream & 0x7; |
518
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1472 |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1473 } else { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1474 #ifdef M68020 |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1475 //TODO: Implement bitfield instructions for M68020+ support |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1476 switch (*istream >> 8 & 7) |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1477 { |
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Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1478 case 0: |
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Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1479 decoded->op = M68K_BFTST; //<ea> |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1480 break; |
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Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1481 case 1: |
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Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1482 decoded->op = M68K_BFEXTU; //<ea>, Dn |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1483 break; |
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Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1484 case 2: |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1485 decoded->op = M68K_BFCHG; //<ea> |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1486 break; |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1487 case 3: |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1488 decoded->op = M68K_BFEXTS; //<ea>, Dn |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1489 break; |
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Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1490 case 4: |
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Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1491 decoded->op = M68K_BFCLR; //<ea> |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1492 break; |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1493 case 5: |
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Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1494 decoded->op = M68K_BFFFO; //<ea>, Dn |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1495 break; |
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Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1496 case 6: |
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Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1497 decoded->op = M68K_BFSET; //<ea> |
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Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1498 break; |
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Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1499 case 7: |
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Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1500 decoded->op = M68K_BFINS; //Dn, <ea> |
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Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1501 break; |
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Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1502 } |
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Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1503 opmode = *istream >> 3 & 0x7; |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1504 reg = *istream & 0x7; |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1505 m68k_op_info *ea, *other; |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1506 if (decoded->op == M68K_BFEXTU || decoded->op == M68K_BFEXTS || decoded->op == M68K_BFFFO) |
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Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1507 { |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1508 ea = &(decoded->src); |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1509 other = &(decoded->dst); |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1510 } else { |
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Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1511 ea = &(decoded->dst); |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1512 other = &(decoded->dst); |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1513 } |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1514 if (*istream & 0x100) |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1515 { |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1516 immed = *(istream++); |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1517 other->addr_mode = MODE_REG; |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1518 other->params.regs.pri = immed >> 12 & 0x7; |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1519 } else { |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1520 immed = *(istream++); |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1521 } |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1522 decoded->extra.size = OPSIZE_UNSIZED; |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1523 istream = m68k_decode_op_ex(istream, opmode, reg, decoded->extra.size, ea); |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1524 ea->addr_mode |= M68K_FLAG_BITFIELD; |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1525 ea->bitfield = immed & 0xFFF; |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1526 #endif |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1527 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1528 break; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1529 case COPROC: |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1530 //TODO: Implement me |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1531 break; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1532 } |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1533 if (decoded->op == M68K_INVALID) { |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1534 decoded->src.params.immed = *start; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1535 return start + 1; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1536 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1537 return istream+1; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1538 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1539 |
518
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1540 uint32_t m68k_branch_target(m68kinst * inst, uint32_t *dregs, uint32_t *aregs) |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1541 { |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1542 if(inst->op == M68K_BCC || inst->op == M68K_BSR || inst->op == M68K_DBCC) { |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1543 return inst->address + 2 + inst->src.params.immed; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1544 } else if(inst->op == M68K_JMP || inst->op == M68K_JSR) { |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1545 uint32_t ret = 0; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1546 switch(inst->src.addr_mode) |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1547 { |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1548 case MODE_AREG_INDIRECT: |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1549 ret = aregs[inst->src.params.regs.pri]; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1550 break; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1551 case MODE_AREG_INDEX_DISP8: { |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1552 uint8_t sec_reg = inst->src.params.regs.sec >> 1 & 0x7; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1553 ret = aregs[inst->src.params.regs.pri]; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1554 uint32_t * regfile = inst->src.params.regs.sec & 0x10 ? aregs : dregs; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1555 if (inst->src.params.regs.sec & 1) { |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1556 //32-bit index register |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1557 ret += regfile[sec_reg]; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1558 } else { |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1559 //16-bit index register |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1560 if (regfile[sec_reg] & 0x8000) { |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1561 ret += (0xFFFF0000 | regfile[sec_reg]); |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1562 } else { |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1563 ret += regfile[sec_reg]; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1564 } |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1565 } |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1566 ret += inst->src.params.regs.displacement; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1567 break; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1568 } |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1569 case MODE_PC_DISPLACE: |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1570 ret = inst->src.params.regs.displacement + inst->address + 2; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1571 break; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1572 case MODE_PC_INDEX_DISP8: { |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1573 uint8_t sec_reg = inst->src.params.regs.sec >> 1 & 0x7; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1574 ret = inst->address + 2; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1575 uint32_t * regfile = inst->src.params.regs.sec & 0x10 ? aregs : dregs; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1576 if (inst->src.params.regs.sec & 1) { |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1577 //32-bit index register |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1578 ret += regfile[sec_reg]; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1579 } else { |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1580 //16-bit index register |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1581 if (regfile[sec_reg] & 0x8000) { |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1582 ret += (0xFFFF0000 | regfile[sec_reg]); |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1583 } else { |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1584 ret += regfile[sec_reg]; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1585 } |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1586 } |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1587 ret += inst->src.params.regs.displacement; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1588 break; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1589 } |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1590 case MODE_ABSOLUTE: |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1591 case MODE_ABSOLUTE_SHORT: |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1592 ret = inst->src.params.immed; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1593 break; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1594 } |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1595 return ret; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1596 } |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1597 return 0; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1598 } |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1599 |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1600 uint8_t m68k_is_branch(m68kinst * inst) |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1601 { |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1602 return (inst->op == M68K_BCC && inst->extra.cond != COND_FALSE) |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1603 || (inst->op == M68K_DBCC && inst->extra.cond != COND_TRUE) |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1604 || inst->op == M68K_BSR || inst->op == M68K_JMP || inst->op == M68K_JSR; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1605 } |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1606 |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1607 uint8_t m68k_is_noncall_branch(m68kinst * inst) |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1608 { |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1609 return m68k_is_branch(inst) && inst->op != M68K_BSR && inst->op != M68K_JSR; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1610 } |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1611 |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1612 |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1613 char * mnemonics[] = { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1614 "abcd", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1615 "add", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1616 "addx", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1617 "and", |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1618 "andi",//ccr |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1619 "andi",//sr |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1620 "asl", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1621 "asr", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1622 "bcc", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1623 "bchg", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1624 "bclr", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1625 "bset", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1626 "bsr", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1627 "btst", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1628 "chk", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1629 "clr", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1630 "cmp", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1631 "dbcc", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1632 "divs", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1633 "divu", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1634 "eor", |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1635 "eori",//ccr |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1636 "eori",//sr |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1637 "exg", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1638 "ext", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1639 "illegal", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1640 "jmp", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1641 "jsr", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1642 "lea", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1643 "link", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1644 "lsl", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1645 "lsr", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1646 "move", |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1647 "move",//ccr |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1648 "move",//from_sr |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1649 "move",//sr |
50
4836d1f3841a
Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1650 "move",//usp |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1651 "movem", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1652 "movep", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1653 "muls", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1654 "mulu", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1655 "nbcd", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1656 "neg", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1657 "negx", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1658 "nop", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1659 "not", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1660 "or", |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1661 "ori",//ccr |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1662 "ori",//sr |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1663 "pea", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1664 "reset", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1665 "rol", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1666 "ror", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1667 "roxl", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1668 "roxr", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1669 "rte", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1670 "rtr", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1671 "rts", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1672 "sbcd", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1673 "scc", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1674 "stop", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1675 "sub", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1676 "subx", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1677 "swap", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1678 "tas", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1679 "trap", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1680 "trapv", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1681 "tst", |
12
db60ed283d8d
Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents:
11
diff
changeset
|
1682 "unlk", |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1683 "invalid", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1684 #ifdef M68010 |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1685 "bkpt", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1686 "move", //from ccr |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1687 "movec", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1688 "moves", |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1689 "rtd", |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1690 #endif |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1691 #ifdef M68020 |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1692 "bfchg", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1693 "bfclr", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1694 "bfexts", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1695 "bfextu", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1696 "bfffo", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1697 "bfins", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1698 "bfset", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1699 "bftst", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1700 "callm", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1701 "cas", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1702 "cas2", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1703 "chk2", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1704 "cmp2", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1705 "cpbcc", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1706 "cpdbcc", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1707 "cpgen", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1708 "cprestore", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1709 "cpsave", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1710 "cpscc", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1711 "cptrapcc", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1712 "divsl", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1713 "divul", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1714 "extb", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1715 "pack", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1716 "rtm", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1717 "trapcc", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1718 "unpk" |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1719 #endif |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1720 }; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1721 |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1722 char * cond_mnem[] = { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1723 "ra", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1724 "f", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1725 "hi", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1726 "ls", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1727 "cc", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1728 "cs", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1729 "ne", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1730 "eq", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1731 "vc", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1732 "vs", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1733 "pl", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1734 "mi", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1735 "ge", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1736 "lt", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1737 "gt", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1738 "le" |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1739 }; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1740 #ifdef M68010 |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1741 char * cr_mnem[] = { |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1742 "SFC", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1743 "DFC", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1744 #ifdef M68020 |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1745 "CACR", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1746 #endif |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1747 "USP", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1748 "VBR", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1749 #ifdef M68020 |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1750 "CAAR", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1751 "MSP", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1752 "ISP" |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1753 #endif |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1754 }; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1755 #endif |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1756 |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
1757 int m68k_disasm_op(m68k_op_info *decoded, char *dst, int need_comma, uint8_t labels, uint32_t address, format_label_fun label_fun, void * data) |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1758 { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1759 char * c = need_comma ? "," : ""; |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1760 int ret = 0; |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1761 #ifdef M68020 |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1762 uint8_t addr_mode = decoded->addr_mode & (~M68K_FLAG_BITFIELD); |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1763 #else |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1764 uint8_t addr_mode = decoded->addr_mode; |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1765 #endif |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1766 switch(addr_mode) |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1767 { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1768 case MODE_REG: |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1769 ret = sprintf(dst, "%s d%d", c, decoded->params.regs.pri); |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1770 break; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1771 case MODE_AREG: |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1772 ret = sprintf(dst, "%s a%d", c, decoded->params.regs.pri); |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1773 break; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1774 case MODE_AREG_INDIRECT: |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1775 ret = sprintf(dst, "%s (a%d)", c, decoded->params.regs.pri); |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1776 break; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1777 case MODE_AREG_POSTINC: |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1778 ret = sprintf(dst, "%s (a%d)+", c, decoded->params.regs.pri); |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1779 break; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1780 case MODE_AREG_PREDEC: |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1781 ret = sprintf(dst, "%s -(a%d)", c, decoded->params.regs.pri); |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1782 break; |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1783 case MODE_AREG_DISPLACE: |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1784 ret = sprintf(dst, "%s (%d, a%d)", c, decoded->params.regs.displacement, decoded->params.regs.pri); |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1785 break; |
79
d212e0cd0b7e
Implement indexed with 8-bit displacement addressing modes in decoder and disassembler
Mike Pavone <pavone@retrodev.com>
parents:
69
diff
changeset
|
1786 case MODE_AREG_INDEX_DISP8: |
638
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1787 #ifdef M68020 |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1788 if (decoded->params.regs.scale) |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1789 { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1790 ret = sprintf(dst, "%s (%d, a%d, %c%d.%c*%d)", c, decoded->params.regs.displacement, decoded->params.regs.pri, (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1791 } else { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1792 #endif |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1793 ret = sprintf(dst, "%s (%d, a%d, %c%d.%c)", c, decoded->params.regs.displacement, decoded->params.regs.pri, (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1794 #ifdef M68020 |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1795 } |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1796 #endif |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1797 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1798 #ifdef M68020 |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1799 case MODE_AREG_INDEX_BASE_DISP: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1800 if (decoded->params.regs.disp_sizes > 1) |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1801 { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1802 ret = sprintf(dst, "%s (%d.%c, a%d, %c%d.%c*%d)", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1803 decoded->params.regs.disp_sizes == 2 ? 'w' : 'l', decoded->params.regs.pri, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1804 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1805 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1806 } else { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1807 ret = sprintf(dst, "%s (a%d, %c%d.%c*%d)", c, decoded->params.regs.pri, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1808 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1809 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1810 } |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1811 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1812 case MODE_AREG_PREINDEX: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1813 switch (decoded->params.regs.disp_sizes) |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1814 { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1815 case 0x11: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1816 //no base displacement or outer displacement |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1817 ret = sprintf(dst, "%s ([a%d, %c%d.%c*%d])", c, decoded->params.regs.pri, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1818 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1819 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1820 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1821 case 0x12: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1822 case 0x13: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1823 //base displacement only |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1824 ret = sprintf(dst, "%s ([%d.%c, a%d, %c%d.%c*%d])", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1825 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', decoded->params.regs.pri, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1826 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1827 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1828 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1829 case 0x21: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1830 case 0x31: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1831 //outer displacement only |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1832 ret = sprintf(dst, "%s ([a%d, %c%d.%c*%d], %d.%c)", c, decoded->params.regs.pri, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1833 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1834 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1835 decoded->params.regs.outer_disp, decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1836 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1837 case 0x22: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1838 case 0x23: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1839 case 0x32: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1840 case 0x33: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1841 //both outer and inner displacement |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1842 ret = sprintf(dst, "%s ([%d.%c, a%d, %c%d.%c*%d], %d.%c)", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1843 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', decoded->params.regs.pri, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1844 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1845 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1846 decoded->params.regs.outer_disp, decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1847 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1848 } |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1849 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1850 case MODE_AREG_POSTINDEX: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1851 switch (decoded->params.regs.disp_sizes) |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1852 { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1853 case 0x11: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1854 //no base displacement or outer displacement |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1855 ret = sprintf(dst, "%s ([a%d], %c%d.%c*%d)", c, decoded->params.regs.pri, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1856 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1857 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1858 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1859 case 0x12: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1860 case 0x13: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1861 //base displacement only |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1862 ret = sprintf(dst, "%s ([%d.%c, a%d], %c%d.%c*%d)", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1863 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', decoded->params.regs.pri, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1864 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1865 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1866 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1867 case 0x21: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1868 case 0x31: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1869 //outer displacement only |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1870 ret = sprintf(dst, "%s ([a%d], %c%d.%c*%d, %d.%c)", c, decoded->params.regs.pri, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1871 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1872 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1873 decoded->params.regs.outer_disp, decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1874 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1875 case 0x22: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1876 case 0x23: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1877 case 0x32: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1878 case 0x33: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1879 //both outer and inner displacement |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1880 ret = sprintf(dst, "%s ([%d.%c, a%d], %c%d.%c*%d, %d.%c)", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1881 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', decoded->params.regs.pri, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1882 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1883 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1884 decoded->params.regs.outer_disp, decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1885 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1886 } |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1887 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1888 case MODE_AREG_MEM_INDIRECT: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1889 switch (decoded->params.regs.disp_sizes) |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1890 { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1891 case 0x11: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1892 //no base displacement or outer displacement |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1893 ret = sprintf(dst, "%s ([a%d])", c, decoded->params.regs.pri); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1894 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1895 case 0x12: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1896 case 0x13: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1897 //base displacement only |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1898 ret = sprintf(dst, "%s ([%d.%c, a%d])", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1899 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', decoded->params.regs.pri); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1900 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1901 case 0x21: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1902 case 0x31: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1903 //outer displacement only |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1904 ret = sprintf(dst, "%s ([a%d], %d.%c)", c, decoded->params.regs.pri, decoded->params.regs.outer_disp, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1905 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1906 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1907 case 0x22: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1908 case 0x23: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1909 case 0x32: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1910 case 0x33: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1911 //both outer and inner displacement |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1912 ret = sprintf(dst, "%s ([%d.%c, a%d], %d.%c)", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1913 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', decoded->params.regs.pri, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1914 decoded->params.regs.outer_disp, decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1915 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1916 } |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1917 break; |
638
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1918 case MODE_AREG_BASE_DISP: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1919 if (decoded->params.regs.disp_sizes > 1) |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1920 { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1921 ret = sprintf(dst, "%s (%d.%c, a%d)", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1922 decoded->params.regs.disp_sizes == 2 ? 'w' : 'l', decoded->params.regs.pri); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1923 } else { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1924 //this is a lossy representation of the encoded instruction |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1925 //not sure if there's a better way to print it though |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1926 ret = sprintf(dst, "%s (a%d)", c, decoded->params.regs.pri); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1927 } |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1928 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1929 case MODE_INDEX_BASE_DISP: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1930 if (decoded->params.regs.disp_sizes > 1) |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1931 { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1932 ret = sprintf(dst, "%s (%d.%c, %c%d.%c*%d)", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1933 decoded->params.regs.disp_sizes == 2 ? 'w' : 'l', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1934 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1935 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1936 } else { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1937 ret = sprintf(dst, "%s (%c%d.%c*%d)", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1938 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1939 1 << decoded->params.regs.scale); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1940 } |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1941 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1942 case MODE_PREINDEX: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1943 switch (decoded->params.regs.disp_sizes) |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1944 { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1945 case 0x11: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1946 //no base displacement or outer displacement |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1947 ret = sprintf(dst, "%s ([%c%d.%c*%d])", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1948 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1949 1 << decoded->params.regs.scale); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1950 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1951 case 0x12: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1952 case 0x13: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1953 //base displacement only |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1954 ret = sprintf(dst, "%s ([%d.%c, %c%d.%c*%d])", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1955 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1956 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1957 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1958 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1959 case 0x21: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1960 case 0x31: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1961 //outer displacement only |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1962 ret = sprintf(dst, "%s ([%c%d.%c*%d], %d.%c)", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1963 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1964 1 << decoded->params.regs.scale, decoded->params.regs.outer_disp, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1965 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1966 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1967 case 0x22: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1968 case 0x23: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1969 case 0x32: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1970 case 0x33: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1971 //both outer and inner displacement |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1972 ret = sprintf(dst, "%s ([%d.%c, %c%d.%c*%d], %d.%c)", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1973 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1974 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1975 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1976 decoded->params.regs.outer_disp, decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1977 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1978 } |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1979 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1980 case MODE_POSTINDEX: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1981 switch (decoded->params.regs.disp_sizes) |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1982 { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1983 case 0x11: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1984 //no base displacement or outer displacement |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1985 ret = sprintf(dst, "%s ([], %c%d.%c*%d)", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1986 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1987 1 << decoded->params.regs.scale); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1988 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1989 case 0x12: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1990 case 0x13: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1991 //base displacement only |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1992 ret = sprintf(dst, "%s ([%d.%c], %c%d.%c*%d)", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1993 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1994 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1995 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1996 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1997 case 0x21: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1998 case 0x31: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1999 //outer displacement only |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2000 ret = sprintf(dst, "%s ([], %c%d.%c*%d, %d.%c)", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2001 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2002 1 << decoded->params.regs.scale, decoded->params.regs.outer_disp, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2003 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2004 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2005 case 0x22: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2006 case 0x23: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2007 case 0x32: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2008 case 0x33: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2009 //both outer and inner displacement |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2010 ret = sprintf(dst, "%s ([%d.%c], %c%d.%c*%d, %d.%c)", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2011 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2012 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2013 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2014 decoded->params.regs.outer_disp, decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2015 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2016 } |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2017 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2018 case MODE_MEM_INDIRECT: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2019 switch (decoded->params.regs.disp_sizes) |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2020 { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2021 case 0x11: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2022 //no base displacement or outer displacement |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2023 ret = sprintf(dst, "%s ([])", c); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2024 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2025 case 0x12: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2026 case 0x13: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2027 //base displacement only |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2028 ret = sprintf(dst, "%s ([%d.%c])", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2029 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2030 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2031 case 0x21: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2032 case 0x31: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2033 //outer displacement only |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2034 ret = sprintf(dst, "%s ([], %d.%c)", c, decoded->params.regs.outer_disp, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2035 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2036 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2037 case 0x22: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2038 case 0x23: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2039 case 0x32: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2040 case 0x33: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2041 //both outer and inner displacement |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2042 ret = sprintf(dst, "%s ([%d.%c], %d.%c)", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2043 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', decoded->params.regs.outer_disp, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2044 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2045 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2046 } |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2047 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2048 case MODE_BASE_DISP: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2049 if (decoded->params.regs.disp_sizes > 1) |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2050 { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2051 ret = sprintf(dst, "%s (%d.%c)", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2052 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2053 } else { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2054 ret = sprintf(dst, "%s ()", c); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2055 } |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2056 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2057 #endif |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
2058 case MODE_IMMEDIATE: |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
60
diff
changeset
|
2059 case MODE_IMMEDIATE_WORD: |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2060 ret = sprintf(dst, (decoded->params.immed <= 128 ? "%s #%d" : "%s #$%X"), c, decoded->params.immed); |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2061 break; |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2062 case MODE_ABSOLUTE_SHORT: |
638
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2063 if (labels) { |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2064 ret = sprintf(dst, "%s ", c); |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2065 ret += label_fun(dst+ret, decoded->params.immed, data); |
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2066 strcat(dst+ret, ".w"); |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2067 ret = ret + 2; |
134 | 2068 } else { |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2069 ret = sprintf(dst, "%s $%X.w", c, decoded->params.immed); |
134 | 2070 } |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2071 break; |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2072 case MODE_ABSOLUTE: |
134 | 2073 if (labels) { |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2074 ret = sprintf(dst, "%s ", c); |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2075 ret += label_fun(dst+ret, decoded->params.immed, data); |
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2076 strcat(dst+ret, ".l"); |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2077 ret = ret + 2; |
134 | 2078 } else { |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2079 ret = sprintf(dst, "%s $%X", c, decoded->params.immed); |
134 | 2080 } |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2081 break; |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2082 case MODE_PC_DISPLACE: |
134 | 2083 if (labels) { |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2084 ret = sprintf(dst, "%s ", c); |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2085 ret += label_fun(dst+ret, address + 2 + decoded->params.regs.displacement, data); |
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2086 strcat(dst+ret, "(pc)"); |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2087 ret = ret + 4; |
134 | 2088 } else { |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2089 ret = sprintf(dst, "%s (%d, pc)", c, decoded->params.regs.displacement); |
134 | 2090 } |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2091 break; |
79
d212e0cd0b7e
Implement indexed with 8-bit displacement addressing modes in decoder and disassembler
Mike Pavone <pavone@retrodev.com>
parents:
69
diff
changeset
|
2092 case MODE_PC_INDEX_DISP8: |
638
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2093 #ifdef M68020 |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2094 if (decoded->params.regs.scale) |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2095 { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2096 ret = sprintf(dst, "%s (%d, pc, %c%d.%c*%d)", c, decoded->params.regs.displacement, (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2097 } else { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2098 #endif |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2099 ret = sprintf(dst, "%s (%d, pc, %c%d.%c)", c, decoded->params.regs.displacement, (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2100 #ifdef M68020 |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2101 } |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2102 #endif |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2103 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2104 #ifdef M68020 |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2105 case MODE_PC_INDEX_BASE_DISP: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2106 if (decoded->params.regs.disp_sizes > 1) |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2107 { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2108 ret = sprintf(dst, "%s (%d.%c, pc, %c%d.%c*%d)", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2109 decoded->params.regs.disp_sizes == 2 ? 'w' : 'l', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2110 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2111 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2112 } else { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2113 ret = sprintf(dst, "%s (pc, %c%d.%c*%d)", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2114 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2115 1 << decoded->params.regs.scale); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2116 } |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2117 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2118 case MODE_PC_PREINDEX: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2119 switch (decoded->params.regs.disp_sizes) |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2120 { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2121 case 0x11: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2122 //no base displacement or outer displacement |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2123 ret = sprintf(dst, "%s ([pc, %c%d.%c*%d])", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2124 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2125 1 << decoded->params.regs.scale); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2126 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2127 case 0x12: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2128 case 0x13: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2129 //base displacement only |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2130 ret = sprintf(dst, "%s ([%d.%c, pc, %c%d.%c*%d])", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2131 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2132 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2133 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2134 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2135 case 0x21: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2136 case 0x31: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2137 //outer displacement only |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2138 ret = sprintf(dst, "%s ([pc, %c%d.%c*%d], %d.%c)", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2139 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2140 1 << decoded->params.regs.scale, decoded->params.regs.outer_disp, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2141 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2142 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2143 case 0x22: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2144 case 0x23: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2145 case 0x32: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2146 case 0x33: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2147 //both outer and inner displacement |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2148 ret = sprintf(dst, "%s ([%d.%c, pc, %c%d.%c*%d], %d.%c)", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2149 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2150 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2151 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2152 decoded->params.regs.outer_disp, decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2153 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2154 } |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2155 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2156 case MODE_PC_POSTINDEX: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2157 switch (decoded->params.regs.disp_sizes) |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2158 { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2159 case 0x11: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2160 //no base displacement or outer displacement |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2161 ret = sprintf(dst, "%s ([pc], %c%d.%c*%d)", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2162 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2163 1 << decoded->params.regs.scale); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2164 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2165 case 0x12: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2166 case 0x13: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2167 //base displacement only |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2168 ret = sprintf(dst, "%s ([%d.%c, pc], %c%d.%c*%d)", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2169 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2170 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2171 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2172 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2173 case 0x21: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2174 case 0x31: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2175 //outer displacement only |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2176 ret = sprintf(dst, "%s ([pc], %c%d.%c*%d, %d.%c)", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2177 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2178 1 << decoded->params.regs.scale, decoded->params.regs.outer_disp, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2179 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2180 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2181 case 0x22: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2182 case 0x23: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2183 case 0x32: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2184 case 0x33: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2185 //both outer and inner displacement |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2186 ret = sprintf(dst, "%s ([%d.%c, pc], %c%d.%c*%d, %d.%c)", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2187 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2188 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2189 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2190 decoded->params.regs.outer_disp, decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2191 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2192 } |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2193 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2194 case MODE_PC_MEM_INDIRECT: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2195 switch (decoded->params.regs.disp_sizes) |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2196 { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2197 case 0x11: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2198 //no base displacement or outer displacement |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2199 ret = sprintf(dst, "%s ([pc])", c); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2200 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2201 case 0x12: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2202 case 0x13: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2203 //base displacement only |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2204 ret = sprintf(dst, "%s ([%d.%c, pc])", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2205 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2206 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2207 case 0x21: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2208 case 0x31: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2209 //outer displacement only |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2210 ret = sprintf(dst, "%s ([pc], %d.%c)", c, decoded->params.regs.outer_disp, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2211 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2212 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2213 case 0x22: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2214 case 0x23: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2215 case 0x32: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2216 case 0x33: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2217 //both outer and inner displacement |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2218 ret = sprintf(dst, "%s ([%d.%c, pc], %d.%c)", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2219 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', decoded->params.regs.outer_disp, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2220 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2221 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2222 } |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2223 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2224 case MODE_PC_BASE_DISP: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2225 if (decoded->params.regs.disp_sizes > 1) |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2226 { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2227 ret = sprintf(dst, "%s (%d.%c, pc)", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2228 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2229 } else { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2230 ret = sprintf(dst, "%s (pc)", c); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2231 } |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2232 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2233 case MODE_ZPC_INDEX_BASE_DISP: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2234 if (decoded->params.regs.disp_sizes > 1) |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2235 { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2236 ret = sprintf(dst, "%s (%d.%c, zpc, %c%d.%c*%d)", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2237 decoded->params.regs.disp_sizes == 2 ? 'w' : 'l', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2238 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2239 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2240 } else { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2241 ret = sprintf(dst, "%s (zpc, %c%d.%c*%d)", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2242 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2243 1 << decoded->params.regs.scale); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2244 } |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2245 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2246 case MODE_ZPC_PREINDEX: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2247 switch (decoded->params.regs.disp_sizes) |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2248 { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2249 case 0x11: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2250 //no base displacement or outer displacement |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2251 ret = sprintf(dst, "%s ([zpc, %c%d.%c*%d])", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2252 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2253 1 << decoded->params.regs.scale); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2254 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2255 case 0x12: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2256 case 0x13: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2257 //base displacement only |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2258 ret = sprintf(dst, "%s ([%d.%c, zpc, %c%d.%c*%d])", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2259 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2260 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2261 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2262 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2263 case 0x21: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2264 case 0x31: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2265 //outer displacement only |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2266 ret = sprintf(dst, "%s ([zpc, %c%d.%c*%d], %d.%c)", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2267 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2268 1 << decoded->params.regs.scale, decoded->params.regs.outer_disp, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2269 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2270 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2271 case 0x22: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2272 case 0x23: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2273 case 0x32: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2274 case 0x33: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2275 //both outer and inner displacement |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2276 ret = sprintf(dst, "%s ([%d.%c, zpc, %c%d.%c*%d], %d.%c)", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2277 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2278 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2279 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2280 decoded->params.regs.outer_disp, decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2281 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2282 } |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2283 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2284 case MODE_ZPC_POSTINDEX: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2285 switch (decoded->params.regs.disp_sizes) |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2286 { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2287 case 0x11: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2288 //no base displacement or outer displacement |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2289 ret = sprintf(dst, "%s ([zpc], %c%d.%c*%d)", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2290 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2291 1 << decoded->params.regs.scale); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2292 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2293 case 0x12: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2294 case 0x13: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2295 //base displacement only |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2296 ret = sprintf(dst, "%s ([%d.%c, zpc], %c%d.%c*%d)", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2297 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2298 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2299 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2300 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2301 case 0x21: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2302 case 0x31: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2303 //outer displacement only |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2304 ret = sprintf(dst, "%s ([zpc], %c%d.%c*%d, %d.%c)", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2305 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2306 1 << decoded->params.regs.scale, decoded->params.regs.outer_disp, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2307 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2308 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2309 case 0x22: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2310 case 0x23: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2311 case 0x32: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2312 case 0x33: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2313 //both outer and inner displacement |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2314 ret = sprintf(dst, "%s ([%d.%c, zpc], %c%d.%c*%d, %d.%c)", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2315 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2316 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2317 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2318 decoded->params.regs.outer_disp, decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2319 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2320 } |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2321 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2322 case MODE_ZPC_MEM_INDIRECT: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2323 switch (decoded->params.regs.disp_sizes) |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2324 { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2325 case 0x11: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2326 //no base displacement or outer displacement |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2327 ret = sprintf(dst, "%s ([zpc])", c); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2328 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2329 case 0x12: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2330 case 0x13: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2331 //base displacement only |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2332 ret = sprintf(dst, "%s ([%d.%c, zpc])", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2333 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2334 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2335 case 0x21: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2336 case 0x31: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2337 //outer displacement only |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2338 ret = sprintf(dst, "%s ([zpc], %d.%c)", c, decoded->params.regs.outer_disp, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2339 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2340 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2341 case 0x22: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2342 case 0x23: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2343 case 0x32: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2344 case 0x33: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2345 //both outer and inner displacement |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2346 ret = sprintf(dst, "%s ([%d.%c, zpc], %d.%c)", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2347 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', decoded->params.regs.outer_disp, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2348 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2349 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2350 } |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2351 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2352 case MODE_ZPC_BASE_DISP: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2353 if (decoded->params.regs.disp_sizes > 1) |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2354 { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2355 ret = sprintf(dst, "%s (%d.%c, zpc)", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2356 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2357 } else { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2358 ret = sprintf(dst, "%s (zpc)", c); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2359 } |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2360 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2361 #endif |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
2362 default: |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2363 ret = 0; |
0
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2364 } |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2365 #ifdef M68020 |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2366 if (decoded->addr_mode & M68K_FLAG_BITFIELD) |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2367 { |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2368 switch (decoded->bitfield & 0x820) |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2369 { |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2370 case 0: |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2371 return ret + sprintf(dst+ret, " {$%X:%d}", decoded->bitfield >> 6 & 0x1F, decoded->bitfield & 0x1F ? decoded->bitfield & 0x1F : 32); |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2372 case 0x20: |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2373 return ret + sprintf(dst+ret, " {$%X:d%d}", decoded->bitfield >> 6 & 0x1F, decoded->bitfield & 0x7); |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2374 case 0x800: |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2375 return ret + sprintf(dst+ret, " {d%d:%d}", decoded->bitfield >> 6 & 0x7, decoded->bitfield & 0x1F ? decoded->bitfield & 0x1F : 32); |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2376 case 0x820: |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2377 return ret + sprintf(dst+ret, " {d%d:d%d}", decoded->bitfield >> 6 & 0x7, decoded->bitfield & 0x7); |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2378 } |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2379 } |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2380 #endif |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2381 return ret; |
0
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2382 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
2383 |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2384 int m68k_disasm_movem_op(m68k_op_info *decoded, m68k_op_info *other, char *dst, int need_comma, uint8_t labels, uint32_t address, format_label_fun label_fun, void * data) |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2385 { |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2386 int8_t dir, reg, bit, regnum, last=-1, lastreg, first=-1; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2387 char *rtype, *last_rtype; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2388 int oplen; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2389 if (decoded->addr_mode == MODE_REG) { |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2390 if (other->addr_mode == MODE_AREG_PREDEC) { |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2391 bit = 15; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2392 dir = -1; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2393 } else { |
69
36f1133837d0
Fix disassembly of reg list in MOVEM when the reg list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
68
diff
changeset
|
2394 dir = 1; |
36f1133837d0
Fix disassembly of reg list in MOVEM when the reg list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
68
diff
changeset
|
2395 bit = 0; |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2396 } |
68
1c9a4052a2c0
Fix decoding and disassembly of MOVEM
Mike Pavone <pavone@retrodev.com>
parents:
62
diff
changeset
|
2397 if (need_comma) { |
1c9a4052a2c0
Fix decoding and disassembly of MOVEM
Mike Pavone <pavone@retrodev.com>
parents:
62
diff
changeset
|
2398 strcat(dst, ", "); |
1c9a4052a2c0
Fix decoding and disassembly of MOVEM
Mike Pavone <pavone@retrodev.com>
parents:
62
diff
changeset
|
2399 oplen = 2; |
1c9a4052a2c0
Fix decoding and disassembly of MOVEM
Mike Pavone <pavone@retrodev.com>
parents:
62
diff
changeset
|
2400 } else { |
1c9a4052a2c0
Fix decoding and disassembly of MOVEM
Mike Pavone <pavone@retrodev.com>
parents:
62
diff
changeset
|
2401 strcat(dst, " "); |
1c9a4052a2c0
Fix decoding and disassembly of MOVEM
Mike Pavone <pavone@retrodev.com>
parents:
62
diff
changeset
|
2402 oplen = 1; |
1c9a4052a2c0
Fix decoding and disassembly of MOVEM
Mike Pavone <pavone@retrodev.com>
parents:
62
diff
changeset
|
2403 } |
1c9a4052a2c0
Fix decoding and disassembly of MOVEM
Mike Pavone <pavone@retrodev.com>
parents:
62
diff
changeset
|
2404 for (reg=0; bit < 16 && bit > -1; bit += dir, reg++) { |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
2405 if (decoded->params.immed & (1 << bit)) { |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2406 if (reg > 7) { |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2407 rtype = "a"; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2408 regnum = reg - 8; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2409 } else { |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2410 rtype = "d"; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2411 regnum = reg; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2412 } |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2413 if (last >= 0 && last == regnum - 1 && lastreg == reg - 1) { |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2414 last = regnum; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2415 lastreg = reg; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2416 } else if(last >= 0) { |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2417 if (first != last) { |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2418 oplen += sprintf(dst + oplen, "-%s%d/%s%d",last_rtype, last, rtype, regnum); |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2419 } else { |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2420 oplen += sprintf(dst + oplen, "/%s%d", rtype, regnum); |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2421 } |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2422 first = last = regnum; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2423 last_rtype = rtype; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2424 lastreg = reg; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2425 } else { |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2426 oplen += sprintf(dst + oplen, "%s%d", rtype, regnum); |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2427 first = last = regnum; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2428 last_rtype = rtype; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2429 lastreg = reg; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2430 } |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2431 } |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2432 } |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2433 if (last >= 0 && last != first) { |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2434 oplen += sprintf(dst + oplen, "-%s%d", last_rtype, last); |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2435 } |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2436 return oplen; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2437 } else { |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2438 return m68k_disasm_op(decoded, dst, need_comma, labels, address, label_fun, data); |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2439 } |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2440 } |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2441 |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2442 int m68k_default_label_fun(char * dst, uint32_t address, void * data) |
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2443 { |
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2444 return sprintf(dst, "ADR_%X", address); |
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2445 } |
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2446 |
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2447 int m68k_disasm_ex(m68kinst * decoded, char * dst, uint8_t labels, format_label_fun label_fun, void * data) |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
2448 { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
2449 int ret,op1len; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
2450 uint8_t size; |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2451 char * special_op = "CCR"; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2452 switch (decoded->op) |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2453 { |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2454 case M68K_BCC: |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2455 case M68K_DBCC: |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2456 case M68K_SCC: |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
2457 ret = strlen(mnemonics[decoded->op]) - 2; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
2458 memcpy(dst, mnemonics[decoded->op], ret); |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
2459 dst[ret] = 0; |
50
4836d1f3841a
Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2460 strcpy(dst+ret, cond_mnem[decoded->extra.cond]); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
2461 ret = strlen(dst); |
50
4836d1f3841a
Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2462 if (decoded->op != M68K_SCC) { |
134 | 2463 if (labels) { |
2464 if (decoded->op == M68K_DBCC) { | |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2465 ret += sprintf(dst+ret, " d%d, ", decoded->dst.params.regs.pri); |
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2466 ret += label_fun(dst+ret, decoded->address + 2 + decoded->src.params.immed, data); |
134 | 2467 } else { |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2468 dst[ret++] = ' '; |
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2469 ret += label_fun(dst+ret, decoded->address + 2 + decoded->src.params.immed, data); |
134 | 2470 } |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
2471 } else { |
134 | 2472 if (decoded->op == M68K_DBCC) { |
2473 ret += sprintf(dst+ret, " d%d, #%d <%X>", decoded->dst.params.regs.pri, decoded->src.params.immed, decoded->address + 2 + decoded->src.params.immed); | |
2474 } else { | |
2475 ret += sprintf(dst+ret, " #%d <%X>", decoded->src.params.immed, decoded->address + 2 + decoded->src.params.immed); | |
2476 } | |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
2477 } |
50
4836d1f3841a
Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2478 return ret; |
4836d1f3841a
Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2479 } |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2480 break; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2481 case M68K_BSR: |
134 | 2482 if (labels) { |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2483 ret = sprintf(dst, "bsr%s ", decoded->variant == VAR_BYTE ? ".s" : ""); |
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2484 ret += label_fun(dst+ret, decoded->address + 2 + decoded->src.params.immed, data); |
134 | 2485 } else { |
2486 ret = sprintf(dst, "bsr%s #%d <%X>", decoded->variant == VAR_BYTE ? ".s" : "", decoded->src.params.immed, decoded->address + 2 + decoded->src.params.immed); | |
2487 } | |
50
4836d1f3841a
Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2488 return ret; |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2489 case M68K_MOVE_FROM_SR: |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2490 ret = sprintf(dst, "%s", mnemonics[decoded->op]); |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2491 ret += sprintf(dst + ret, " SR"); |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2492 ret += m68k_disasm_op(&(decoded->dst), dst + ret, 1, labels, decoded->address, label_fun, data); |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2493 return ret; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2494 case M68K_ANDI_SR: |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2495 case M68K_EORI_SR: |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2496 case M68K_MOVE_SR: |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2497 case M68K_ORI_SR: |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2498 special_op = "SR"; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2499 case M68K_ANDI_CCR: |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2500 case M68K_EORI_CCR: |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2501 case M68K_MOVE_CCR: |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2502 case M68K_ORI_CCR: |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2503 ret = sprintf(dst, "%s", mnemonics[decoded->op]); |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2504 ret += m68k_disasm_op(&(decoded->src), dst + ret, 0, labels, decoded->address, label_fun, data); |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2505 ret += sprintf(dst + ret, ", %s", special_op); |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2506 return ret; |
50
4836d1f3841a
Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2507 case M68K_MOVE_USP: |
4836d1f3841a
Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2508 ret = sprintf(dst, "%s", mnemonics[decoded->op]); |
4836d1f3841a
Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2509 if (decoded->src.addr_mode != MODE_UNUSED) { |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2510 ret += m68k_disasm_op(&(decoded->src), dst + ret, 0, labels, decoded->address, label_fun, data); |
50
4836d1f3841a
Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2511 ret += sprintf(dst + ret, ", USP"); |
4836d1f3841a
Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2512 } else { |
4836d1f3841a
Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2513 ret += sprintf(dst + ret, "USP, "); |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2514 ret += m68k_disasm_op(&(decoded->dst), dst + ret, 0, labels, decoded->address, label_fun, data); |
50
4836d1f3841a
Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2515 } |
4836d1f3841a
Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2516 return ret; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
2517 case M68K_INVALID: |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
2518 ret = sprintf(dst, "dc.w $%X", decoded->src.params.immed); |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
2519 return ret; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
2520 #ifdef M68010 |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
2521 case M68K_MOVEC: |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
2522 ret = sprintf(dst, "%s ", mnemonics[decoded->op]); |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
2523 if (decoded->src.addr_mode == MODE_UNUSED) { |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
2524 ret += sprintf(dst + ret, "%s, ", cr_mnem[decoded->src.params.immed]); |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2525 ret += m68k_disasm_op(&(decoded->dst), dst + ret, 0, labels, decoded->address, label_fun, data); |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
2526 } else { |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2527 ret += m68k_disasm_op(&(decoded->src), dst + ret, 0, labels, decoded->address, label_fun, data); |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
2528 ret += sprintf(dst + ret, ", %s", cr_mnem[decoded->dst.params.immed]); |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
2529 } |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
2530 return ret; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
2531 #endif |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2532 default: |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
2533 size = decoded->extra.size; |
518
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
2534 ret = sprintf(dst, "%s%s%s", |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
2535 mnemonics[decoded->op], |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
2536 decoded->variant == VAR_QUICK ? "q" : (decoded->variant == VAR_IMMEDIATE ? "i" : ""), |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2537 size == OPSIZE_BYTE ? ".b" : (size == OPSIZE_WORD ? ".w" : (size == OPSIZE_LONG ? ".l" : ""))); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
2538 } |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2539 if (decoded->op == M68K_MOVEM) { |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2540 op1len = m68k_disasm_movem_op(&(decoded->src), &(decoded->dst), dst + ret, 0, labels, decoded->address, label_fun, data); |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2541 ret += op1len; |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2542 ret += m68k_disasm_movem_op(&(decoded->dst), &(decoded->src), dst + ret, op1len, labels, decoded->address, label_fun, data); |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2543 } else { |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2544 op1len = m68k_disasm_op(&(decoded->src), dst + ret, 0, labels, decoded->address, label_fun, data); |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2545 ret += op1len; |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2546 ret += m68k_disasm_op(&(decoded->dst), dst + ret, op1len, labels, decoded->address, label_fun, data); |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2547 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
2548 return ret; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
2549 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
2550 |
134 | 2551 int m68k_disasm(m68kinst * decoded, char * dst) |
2552 { | |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2553 return m68k_disasm_ex(decoded, dst, 0, NULL, NULL); |
134 | 2554 } |
2555 | |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2556 int m68k_disasm_labels(m68kinst * decoded, char * dst, format_label_fun label_fun, void * data) |
134 | 2557 { |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2558 if (!label_fun) |
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2559 { |
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2560 label_fun = m68k_default_label_fun; |
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2561 } |
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2562 return m68k_disasm_ex(decoded, dst, 1, label_fun, data); |
134 | 2563 } |