Mercurial > repos > blastem
annotate fib.s68 @ 561:666adeba5a61
Save and restore guest address in the write function for a code memory chunk in the "slow" path for inconvenient host addresses. This fixes an intermittent crash on OSX in the code that checks whether the memory written may contain code
author | Mike Pavone <pavone@retrodev.com> |
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date | Mon, 23 Jun 2014 11:46:56 -0400 |
parents | f664eeb55cb4 |
children | 2455662378ed f7fe240a7da6 |
rev | line source |
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19
4717146a7606
Initial support for M68k reset vector, rather than starting at an arbitrary address
Mike Pavone <pavone@retrodev.com>
parents:
1
diff
changeset
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1 dc.l $0, start |
4717146a7606
Initial support for M68k reset vector, rather than starting at an arbitrary address
Mike Pavone <pavone@retrodev.com>
parents:
1
diff
changeset
|
2 start: |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
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3 moveq #36, d0 |
0
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
4 bsr fib |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
5 illegal |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
6 fib: |
1
5a2c1da6dd0f
Make sure all operations are long-word length on fib example.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
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7 cmp.l #2, d0 |
0
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
8 blt base |
1
5a2c1da6dd0f
Make sure all operations are long-word length on fib example.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
9 subq.l #1, d0 |
0
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
10 move.l d0, -(a7) |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
11 bsr fib |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
12 move.l (a7), d1 |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
13 exg d0, d1 |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
14 move.l d1, (a7) |
1
5a2c1da6dd0f
Make sure all operations are long-word length on fib example.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
15 subq.l #1, d0 |
0
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
16 bsr fib |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
17 move.l (a7)+, d1 |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
18 add.l d1, d0 |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
19 rts |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
20 base: |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
21 moveq #1, d0 |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
22 rts |