Mercurial > repos > blastem
annotate z80_to_x86.c @ 250:5f1b68cecfc7
Implemented basic interrupt support in Z80 core.
author | Mike Pavone <pavone@retrodev.com> |
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date | Mon, 29 Apr 2013 00:59:50 -0700 |
parents | 9c7a3db7bcd0 |
children | 63b9a500a00b |
rev | line source |
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1 #include "z80inst.h" |
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2 #include "z80_to_x86.h" |
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3 #include "gen_x86.h" |
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4 #include "mem.h" |
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5 #include <stdio.h> |
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6 #include <stdlib.h> |
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7 #include <stddef.h> |
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8 #include <string.h> |
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9 |
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10 #define MODE_UNUSED (MODE_IMMED-1) |
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11 |
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12 #define ZCYCLES RBP |
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13 #define ZLIMIT RDI |
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14 #define SCRATCH1 R13 |
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15 #define SCRATCH2 R14 |
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16 #define CONTEXT RSI |
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17 |
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18 //TODO: Find out the actual value for this |
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19 #define MAX_NATIVE_SIZE 128 |
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20 |
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21 void z80_read_byte(); |
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22 void z80_read_word(); |
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23 void z80_write_byte(); |
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24 void z80_write_word_highfirst(); |
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25 void z80_write_word_lowfirst(); |
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26 void z80_save_context(); |
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27 void z80_native_addr(); |
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28 void z80_do_sync(); |
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29 void z80_handle_cycle_limit_int(); |
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30 |
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31 uint8_t z80_size(z80inst * inst) |
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32 { |
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33 uint8_t reg = (inst->reg & 0x1F); |
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34 if (reg != Z80_UNUSED && reg != Z80_USE_IMMED) { |
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35 return reg < Z80_BC ? SZ_B : SZ_W; |
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36 } |
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37 //TODO: Handle any necessary special cases |
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38 return SZ_B; |
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39 } |
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40 |
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41 uint8_t z80_high_reg(uint8_t reg) |
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42 { |
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43 switch(reg) |
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44 { |
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45 case Z80_C: |
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46 case Z80_BC: |
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47 return Z80_B; |
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48 case Z80_E: |
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49 case Z80_DE: |
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50 return Z80_D; |
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51 case Z80_L: |
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52 case Z80_HL: |
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53 return Z80_H; |
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54 case Z80_IXL: |
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55 case Z80_IX: |
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56 return Z80_IXH; |
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57 case Z80_IYL: |
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58 case Z80_IY: |
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59 return Z80_IYH; |
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60 default: |
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61 return Z80_UNUSED; |
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62 } |
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63 } |
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64 |
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65 uint8_t * zcycles(uint8_t * dst, uint32_t num_cycles) |
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66 { |
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67 return add_ir(dst, num_cycles, ZCYCLES, SZ_D); |
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68 } |
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69 |
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70 uint8_t * z80_check_cycles_int(uint8_t * dst, uint16_t address) |
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71 { |
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72 dst = cmp_rr(dst, ZCYCLES, ZLIMIT, SZ_D); |
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73 uint8_t * jmp_off = dst+1; |
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74 dst = jcc(dst, CC_NC, dst + 7); |
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75 dst = mov_ir(dst, address, SCRATCH2, SZ_W); |
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76 dst = call(dst, (uint8_t *)z80_handle_cycle_limit_int); |
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77 *jmp_off = dst - (jmp_off+1); |
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78 return dst; |
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79 } |
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80 |
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81 uint8_t * translate_z80_reg(z80inst * inst, x86_ea * ea, uint8_t * dst, x86_z80_options * opts) |
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82 { |
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83 if (inst->reg == Z80_USE_IMMED) { |
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84 ea->mode = MODE_IMMED; |
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85 ea->disp = inst->immed; |
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86 } else if ((inst->reg & 0x1F) == Z80_UNUSED) { |
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87 ea->mode = MODE_UNUSED; |
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88 } else { |
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89 ea->mode = MODE_REG_DIRECT; |
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90 if (inst->reg == Z80_IYH) { |
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91 ea->base = opts->regs[Z80_IYL]; |
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92 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W); |
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93 } else { |
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94 ea->base = opts->regs[inst->reg]; |
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95 } |
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96 } |
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97 return dst; |
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98 } |
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99 |
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100 uint8_t * z80_save_reg(uint8_t * dst, z80inst * inst, x86_z80_options * opts) |
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101 { |
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102 if (inst->reg == Z80_IYH) { |
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103 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W); |
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104 } |
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105 return dst; |
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106 } |
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107 |
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108 uint8_t * translate_z80_ea(z80inst * inst, x86_ea * ea, uint8_t * dst, x86_z80_options * opts, uint8_t read, uint8_t modify) |
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109 { |
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110 uint8_t size, reg, areg; |
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111 ea->mode = MODE_REG_DIRECT; |
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112 areg = read ? SCRATCH1 : SCRATCH2; |
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113 switch(inst->addr_mode & 0x1F) |
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114 { |
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115 case Z80_REG: |
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116 if (inst->ea_reg == Z80_IYH) { |
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117 ea->base = opts->regs[Z80_IYL]; |
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118 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W); |
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119 } else { |
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120 ea->base = opts->regs[inst->ea_reg]; |
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121 } |
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122 break; |
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123 case Z80_REG_INDIRECT: |
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124 dst = mov_rr(dst, opts->regs[inst->ea_reg], areg, SZ_W); |
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125 size = z80_size(inst); |
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126 if (read) { |
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127 if (modify) { |
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128 dst = push_r(dst, SCRATCH1); |
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129 } |
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130 if (size == SZ_B) { |
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131 dst = call(dst, (uint8_t *)z80_read_byte); |
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132 } else { |
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133 dst = call(dst, (uint8_t *)z80_read_word); |
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134 } |
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135 if (modify) { |
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136 dst = pop_r(dst, SCRATCH2); |
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137 } |
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138 } |
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139 ea->base = SCRATCH1; |
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140 break; |
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141 case Z80_IMMED: |
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142 ea->mode = MODE_IMMED; |
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143 ea->disp = inst->immed; |
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144 break; |
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145 case Z80_IMMED_INDIRECT: |
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146 dst = mov_ir(dst, inst->immed, areg, SZ_W); |
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147 size = z80_size(inst); |
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148 if (read) { |
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149 if (modify) { |
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150 dst = push_r(dst, SCRATCH1); |
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151 } |
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152 if (size == SZ_B) { |
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153 dst = call(dst, (uint8_t *)z80_read_byte); |
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154 } else { |
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155 dst = call(dst, (uint8_t *)z80_read_word); |
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156 } |
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157 if (modify) { |
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158 dst = pop_r(dst, SCRATCH2); |
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159 } |
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160 } |
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161 ea->base = SCRATCH1; |
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162 break; |
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163 case Z80_IX_DISPLACE: |
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164 case Z80_IY_DISPLACE: |
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165 reg = opts->regs[inst->addr_mode == Z80_IX_DISPLACE ? Z80_IX : Z80_IY]; |
213
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166 dst = mov_rr(dst, reg, areg, SZ_W); |
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167 dst = add_ir(dst, inst->immed, areg, SZ_W); |
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168 size = z80_size(inst); |
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169 if (read) { |
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170 if (modify) { |
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171 dst = push_r(dst, SCRATCH1); |
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172 } |
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173 if (size == SZ_B) { |
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174 dst = call(dst, (uint8_t *)z80_read_byte); |
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175 } else { |
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176 dst = call(dst, (uint8_t *)z80_read_word); |
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177 } |
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178 if (modify) { |
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179 dst = pop_r(dst, SCRATCH2); |
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180 } |
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181 } |
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182 break; |
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183 case Z80_UNUSED: |
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184 ea->mode = MODE_UNUSED; |
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185 break; |
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186 default: |
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187 fprintf(stderr, "Unrecognized Z80 addressing mode %d\n", inst->addr_mode); |
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188 exit(1); |
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189 } |
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190 return dst; |
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191 } |
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192 |
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193 uint8_t * z80_save_ea(uint8_t * dst, z80inst * inst, x86_z80_options * opts) |
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194 { |
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195 if (inst->addr_mode == Z80_REG && inst->ea_reg == Z80_IYH) { |
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196 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W); |
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197 } |
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198 return dst; |
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199 } |
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200 |
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201 uint8_t * z80_save_result(uint8_t * dst, z80inst * inst) |
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202 { |
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203 if (z80_size(inst) == SZ_B) { |
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204 dst = call(dst, (uint8_t *)z80_write_byte); |
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205 } else { |
235
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206 dst = call(dst, (uint8_t *)z80_write_word_lowfirst); |
213
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207 } |
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208 return dst; |
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209 } |
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210 |
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211 enum { |
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212 DONT_READ=0, |
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213 READ |
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214 }; |
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215 |
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216 enum { |
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217 DONT_MODIFY=0, |
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218 MODIFY |
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219 }; |
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220 |
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221 uint8_t zf_off(uint8_t flag) |
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222 { |
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223 return offsetof(z80_context, flags) + flag; |
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224 } |
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225 |
241
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226 uint8_t zaf_off(uint8_t flag) |
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227 { |
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228 return offsetof(z80_context, alt_flags) + flag; |
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229 } |
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230 |
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231 uint8_t zar_off(uint8_t reg) |
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232 { |
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233 return offsetof(z80_context, alt_regs) + reg; |
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234 } |
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235 |
235
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236 void z80_print_regs_exit(z80_context * context) |
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237 { |
243
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238 printf("A: %X\nB: %X\nC: %X\nD: %X\nE: %X\nHL: %X\nIX: %X\nIY: %X\nSP: %X\n\nIM: %d, IFF1: %d, IFF2: %d\n", |
235
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239 context->regs[Z80_A], context->regs[Z80_B], context->regs[Z80_C], |
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240 context->regs[Z80_D], context->regs[Z80_E], |
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241 (context->regs[Z80_H] << 8) | context->regs[Z80_L], |
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242 (context->regs[Z80_IXH] << 8) | context->regs[Z80_IXL], |
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243 (context->regs[Z80_IYH] << 8) | context->regs[Z80_IYL], |
243
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244 context->sp, context->im, context->iff1, context->iff2); |
241
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245 puts("--Alternate Regs--"); |
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246 printf("A: %X\nB: %X\nC: %X\nD: %X\nE: %X\nHL: %X\nIX: %X\nIY: %X\n", |
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247 context->alt_regs[Z80_A], context->alt_regs[Z80_B], context->alt_regs[Z80_C], |
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248 context->alt_regs[Z80_D], context->alt_regs[Z80_E], |
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249 (context->alt_regs[Z80_H] << 8) | context->alt_regs[Z80_L], |
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250 (context->alt_regs[Z80_IXH] << 8) | context->alt_regs[Z80_IXL], |
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251 (context->alt_regs[Z80_IYH] << 8) | context->alt_regs[Z80_IYL]); |
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252 exit(0); |
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253 } |
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254 |
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255 uint8_t * translate_z80inst(z80inst * inst, uint8_t * dst, z80_context * context, uint16_t address) |
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256 { |
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257 uint32_t cycles; |
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258 x86_ea src_op, dst_op; |
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259 uint8_t size; |
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260 x86_z80_options *opts = context->options; |
250
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261 dst = z80_check_cycles_int(dst, address); |
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262 switch(inst->op) |
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263 { |
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264 case Z80_LD: |
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265 size = z80_size(inst); |
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266 switch (inst->addr_mode & 0x1F) |
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267 { |
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268 case Z80_REG: |
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269 case Z80_REG_INDIRECT: |
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270 cycles = size == SZ_B ? 4 : 6; |
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271 if (inst->ea_reg == Z80_IX || inst->ea_reg == Z80_IY) { |
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272 cycles += 4; |
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273 } |
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274 break; |
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275 case Z80_IMMED: |
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276 cycles = size == SZ_B ? 7 : 10; |
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277 break; |
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278 case Z80_IMMED_INDIRECT: |
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279 cycles = 10; |
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280 break; |
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281 case Z80_IX_DISPLACE: |
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282 case Z80_IY_DISPLACE: |
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283 cycles = 12; |
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284 break; |
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285 } |
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286 if ((inst->reg >= Z80_IXL && inst->reg <= Z80_IYH) || inst->reg == Z80_IX || inst->reg == Z80_IY) { |
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287 cycles += 4; |
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288 } |
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289 dst = zcycles(dst, cycles); |
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290 if (inst->addr_mode & Z80_DIR) { |
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291 dst = translate_z80_reg(inst, &src_op, dst, opts); |
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292 dst = translate_z80_ea(inst, &dst_op, dst, opts, DONT_READ, MODIFY); |
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293 } else { |
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294 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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295 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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296 } |
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297 if (src_op.mode == MODE_REG_DIRECT) { |
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298 dst = mov_rr(dst, src_op.base, dst_op.base, size); |
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299 } else { |
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300 dst = mov_ir(dst, src_op.disp, dst_op.base, size); |
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301 } |
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302 dst = z80_save_reg(dst, inst, opts); |
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303 dst = z80_save_ea(dst, inst, opts); |
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304 if (inst->addr_mode & Z80_DIR) { |
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305 dst = z80_save_result(dst, inst); |
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306 } |
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307 break; |
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308 case Z80_PUSH: |
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309 dst = zcycles(dst, (inst->reg == Z80_IX || inst->reg == Z80_IY) ? 9 : 5); |
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310 dst = sub_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
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311 if (inst->reg == Z80_AF) { |
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312 dst = mov_rdisp8r(dst, CONTEXT, zf_off(ZF_S), SCRATCH2, SZ_B); |
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313 dst = shl_ir(dst, 1, SCRATCH2, SZ_B); |
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314 dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_Z), SCRATCH2, SZ_B); |
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315 dst = shl_ir(dst, 2, SCRATCH2, SZ_B); |
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316 dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_H), SCRATCH2, SZ_B); |
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317 dst = shl_ir(dst, 2, SCRATCH2, SZ_B); |
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318 dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_PV), SCRATCH2, SZ_B); |
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319 dst = shl_ir(dst, 1, SCRATCH2, SZ_B); |
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320 dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_N), SCRATCH2, SZ_B); |
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321 dst = shl_ir(dst, 1, SCRATCH2, SZ_B); |
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322 dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_C), SCRATCH2, SZ_B); |
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323 dst = shl_ir(dst, 8, SCRATCH2, SZ_W); |
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324 dst = mov_rr(dst, opts->regs[Z80_A], SCRATCH2, SZ_B); |
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325 } else { |
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326 dst = translate_z80_reg(inst, &src_op, dst, opts); |
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327 dst = mov_rr(dst, src_op.base, SCRATCH2, SZ_W); |
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328 } |
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329 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
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330 dst = call(dst, (uint8_t *)z80_write_word_highfirst); |
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331 //no call to save_z80_reg needed since there's no chance we'll use the only |
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332 //the upper half of a register pair |
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333 break; |
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334 case Z80_POP: |
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335 dst = zcycles(dst, (inst->reg == Z80_IX || inst->reg == Z80_IY) ? 8 : 4); |
235
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336 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
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337 dst = call(dst, (uint8_t *)z80_read_word); |
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338 dst = add_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
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339 if (inst->reg == Z80_AF) { |
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340 dst = mov_rr(dst, SCRATCH1, opts->regs[Z80_A], SZ_B); |
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341 dst = bt_ir(dst, 8, SCRATCH1, SZ_W); |
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342 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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343 dst = bt_ir(dst, 9, SCRATCH1, SZ_W); |
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344 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_N)); |
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345 dst = bt_ir(dst, 10, SCRATCH1, SZ_W); |
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346 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_PV)); |
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347 dst = bt_ir(dst, 12, SCRATCH1, SZ_W); |
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348 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_H)); |
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349 dst = bt_ir(dst, 14, SCRATCH1, SZ_W); |
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350 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_Z)); |
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351 dst = bt_ir(dst, 15, SCRATCH1, SZ_W); |
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352 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_S)); |
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353 } else { |
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354 dst = translate_z80_reg(inst, &src_op, dst, opts); |
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355 dst = mov_rr(dst, SCRATCH1, src_op.base, SZ_W); |
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356 } |
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357 //no call to save_z80_reg needed since there's no chance we'll use the only |
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358 //the upper half of a register pair |
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359 break; |
241
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360 case Z80_EX: |
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361 if (inst->addr_mode == Z80_REG || inst->reg == Z80_HL) { |
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362 cycles = 4; |
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363 } else { |
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364 cycles = 8; |
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365 } |
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366 dst = zcycles(dst, cycles); |
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367 if (inst->addr_mode == Z80_REG) { |
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368 if(inst->reg == Z80_AF) { |
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369 dst = mov_rr(dst, opts->regs[Z80_A], SCRATCH1, SZ_B); |
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370 dst = mov_rdisp8r(dst, CONTEXT, zar_off(Z80_A), opts->regs[Z80_A], SZ_B); |
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371 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, zar_off(Z80_A), SZ_B); |
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372 |
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373 //Flags are currently word aligned, so we can move |
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374 //them efficiently a word at a time |
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375 for (int f = ZF_C; f < ZF_NUM; f+=2) { |
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376 dst = mov_rdisp8r(dst, CONTEXT, zf_off(f), SCRATCH1, SZ_W); |
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377 dst = mov_rdisp8r(dst, CONTEXT, zaf_off(f), SCRATCH2, SZ_W); |
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378 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, zaf_off(f), SZ_W); |
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379 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, zf_off(f), SZ_W); |
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380 } |
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381 } else { |
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382 dst = xchg_rr(dst, opts->regs[Z80_DE], opts->regs[Z80_HL], SZ_W); |
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383 } |
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384 } else { |
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385 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
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386 dst = call(dst, (uint8_t *)z80_read_byte); |
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387 dst = mov_rr(dst, opts->regs[inst->reg], SCRATCH2, SZ_B); |
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388 dst = mov_rr(dst, SCRATCH1, opts->regs[inst->reg], SZ_B); |
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389 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
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390 dst = call(dst, (uint8_t *)z80_write_byte); |
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391 dst = zcycles(dst, 1); |
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392 uint8_t high_reg = z80_high_reg(inst->reg); |
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393 uint8_t use_reg; |
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394 //even though some of the upper halves can be used directly |
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395 //the limitations on mixing *H regs with the REX prefix |
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396 //prevent us from taking advantage of it |
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397 use_reg = opts->regs[inst->reg]; |
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398 dst = ror_ir(dst, 8, use_reg, SZ_W); |
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399 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
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400 dst = add_ir(dst, 1, SCRATCH1, SZ_W); |
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401 dst = call(dst, (uint8_t *)z80_read_byte); |
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402 dst = mov_rr(dst, use_reg, SCRATCH2, SZ_B); |
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403 dst = mov_rr(dst, SCRATCH1, use_reg, SZ_B); |
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404 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
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405 dst = add_ir(dst, 1, SCRATCH1, SZ_W); |
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406 dst = call(dst, (uint8_t *)z80_write_byte); |
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407 //restore reg to normal rotation |
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408 dst = ror_ir(dst, 8, use_reg, SZ_W); |
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409 dst = zcycles(dst, 2); |
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410 } |
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411 break; |
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412 case Z80_EXX: |
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413 dst = zcycles(dst, 4); |
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414 dst = mov_rr(dst, opts->regs[Z80_BC], SCRATCH1, SZ_W); |
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415 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH2, SZ_W); |
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416 dst = mov_rdisp8r(dst, CONTEXT, zar_off(Z80_C), opts->regs[Z80_BC], SZ_W); |
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417 dst = mov_rdisp8r(dst, CONTEXT, zar_off(Z80_L), opts->regs[Z80_HL], SZ_W); |
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418 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, zar_off(Z80_C), SZ_W); |
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419 dst = mov_rrdisp8(dst, SCRATCH2, CONTEXT, zar_off(Z80_L), SZ_W); |
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420 dst = mov_rr(dst, opts->regs[Z80_DE], SCRATCH1, SZ_W); |
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421 dst = mov_rdisp8r(dst, CONTEXT, zar_off(Z80_E), opts->regs[Z80_DE], SZ_W); |
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422 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, zar_off(Z80_E), SZ_W); |
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423 break; |
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|
424 /*case Z80_LDI: |
213
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425 case Z80_LDIR: |
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|
426 case Z80_LDD: |
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|
427 case Z80_LDDR: |
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changeset
|
428 case Z80_CPI: |
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|
429 case Z80_CPIR: |
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|
430 case Z80_CPD: |
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|
431 case Z80_CPDR: |
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|
432 break;*/ |
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433 case Z80_ADD: |
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434 cycles = 4; |
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435 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
213
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436 cycles += 12; |
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437 } else if(inst->addr_mode == Z80_IMMED) { |
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438 cycles += 3; |
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439 } else if(z80_size(inst) == SZ_W) { |
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440 cycles += 4; |
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|
441 } |
4d4559b04c59
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changeset
|
442 dst = zcycles(dst, cycles); |
4d4559b04c59
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changeset
|
443 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
4d4559b04c59
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changeset
|
444 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
4d4559b04c59
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changeset
|
445 if (src_op.mode == MODE_REG_DIRECT) { |
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446 dst = add_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
4d4559b04c59
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changeset
|
447 } else { |
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changeset
|
448 dst = add_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
4d4559b04c59
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449 } |
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450 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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451 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
213
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|
452 //TODO: Implement half-carry flag |
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453 if (z80_size(inst) == SZ_B) { |
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454 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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455 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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456 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
213
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changeset
|
457 } |
4d4559b04c59
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changeset
|
458 dst = z80_save_reg(dst, inst, opts); |
4d4559b04c59
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changeset
|
459 dst = z80_save_ea(dst, inst, opts); |
4d4559b04c59
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changeset
|
460 break; |
248
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461 case Z80_ADC: |
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462 cycles = 4; |
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463 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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464 cycles += 12; |
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465 } else if(inst->addr_mode == Z80_IMMED) { |
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466 cycles += 3; |
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467 } else if(z80_size(inst) == SZ_W) { |
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468 cycles += 4; |
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|
469 } |
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changeset
|
470 dst = zcycles(dst, cycles); |
9c7a3db7bcd0
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471 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
9c7a3db7bcd0
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changeset
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472 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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|
473 if (src_op.mode == MODE_REG_DIRECT) { |
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changeset
|
474 dst = adc_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
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changeset
|
475 } else { |
9c7a3db7bcd0
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changeset
|
476 dst = adc_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
9c7a3db7bcd0
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|
477 } |
9c7a3db7bcd0
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changeset
|
478 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
9c7a3db7bcd0
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changeset
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479 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
9c7a3db7bcd0
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|
480 //TODO: Implement half-carry flag |
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changeset
|
481 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
9c7a3db7bcd0
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482 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
9c7a3db7bcd0
Implement ADC and SBC in Z80 core (untested)
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changeset
|
483 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
9c7a3db7bcd0
Implement ADC and SBC in Z80 core (untested)
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changeset
|
484 dst = z80_save_reg(dst, inst, opts); |
9c7a3db7bcd0
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|
485 dst = z80_save_ea(dst, inst, opts); |
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|
486 break; |
213
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Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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diff
changeset
|
487 case Z80_SUB: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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diff
changeset
|
488 cycles = 4; |
235
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|
489 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
213
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diff
changeset
|
490 cycles += 12; |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff
changeset
|
491 } else if(inst->addr_mode == Z80_IMMED) { |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff
changeset
|
492 cycles += 3; |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff
changeset
|
493 } |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff
changeset
|
494 dst = zcycles(dst, cycles); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
495 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
496 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff
changeset
|
497 if (src_op.mode == MODE_REG_DIRECT) { |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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diff
changeset
|
498 dst = sub_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
499 } else { |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
500 dst = sub_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
501 } |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
502 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
235
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|
503 dst = mov_irdisp8(dst, 1, CONTEXT, zf_off(ZF_N), SZ_B); |
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changeset
|
504 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff
changeset
|
505 //TODO: Implement half-carry flag |
235
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changeset
|
506 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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213
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changeset
|
507 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
508 dst = z80_save_reg(dst, inst, opts); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
509 dst = z80_save_ea(dst, inst, opts); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
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|
510 break; |
248
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247
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511 case Z80_SBC: |
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512 cycles = 4; |
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513 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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514 cycles += 12; |
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515 } else if(inst->addr_mode == Z80_IMMED) { |
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516 cycles += 3; |
9c7a3db7bcd0
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517 } else if(z80_size(inst) == SZ_W) { |
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518 cycles += 4; |
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519 } |
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520 dst = zcycles(dst, cycles); |
9c7a3db7bcd0
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|
521 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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522 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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523 if (src_op.mode == MODE_REG_DIRECT) { |
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524 dst = sbb_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
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525 } else { |
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526 dst = sbb_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
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527 } |
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247
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528 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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529 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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530 //TODO: Implement half-carry flag |
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531 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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247
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532 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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533 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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534 dst = z80_save_reg(dst, inst, opts); |
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535 dst = z80_save_ea(dst, inst, opts); |
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536 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
537 case Z80_AND: |
236
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538 cycles = 4; |
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diff
changeset
|
539 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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540 cycles += 12; |
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541 } else if(inst->addr_mode == Z80_IMMED) { |
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235
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|
542 cycles += 3; |
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543 } else if(z80_size(inst) == SZ_W) { |
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544 cycles += 4; |
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|
545 } |
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546 dst = zcycles(dst, cycles); |
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547 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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changeset
|
548 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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549 if (src_op.mode == MODE_REG_DIRECT) { |
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550 dst = and_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
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235
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|
551 } else { |
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235
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552 dst = and_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
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235
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553 } |
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|
554 //TODO: Cleanup flags |
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|
555 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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235
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changeset
|
556 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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235
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|
557 //TODO: Implement half-carry flag |
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235
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|
558 if (z80_size(inst) == SZ_B) { |
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235
diff
changeset
|
559 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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235
diff
changeset
|
560 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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235
diff
changeset
|
561 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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235
diff
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|
562 } |
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Mike Pavone <pavone@retrodev.com>
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235
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|
563 dst = z80_save_reg(dst, inst, opts); |
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235
diff
changeset
|
564 dst = z80_save_ea(dst, inst, opts); |
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235
diff
changeset
|
565 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
566 case Z80_OR: |
236
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Mike Pavone <pavone@retrodev.com>
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235
diff
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|
567 cycles = 4; |
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Mike Pavone <pavone@retrodev.com>
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235
diff
changeset
|
568 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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parents:
235
diff
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|
569 cycles += 12; |
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235
diff
changeset
|
570 } else if(inst->addr_mode == Z80_IMMED) { |
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
571 cycles += 3; |
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Mike Pavone <pavone@retrodev.com>
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235
diff
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|
572 } else if(z80_size(inst) == SZ_W) { |
19fb3523a9e5
Implement more Z80 instructions (untested)
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235
diff
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|
573 cycles += 4; |
19fb3523a9e5
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235
diff
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|
574 } |
19fb3523a9e5
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235
diff
changeset
|
575 dst = zcycles(dst, cycles); |
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235
diff
changeset
|
576 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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235
diff
changeset
|
577 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
19fb3523a9e5
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235
diff
changeset
|
578 if (src_op.mode == MODE_REG_DIRECT) { |
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235
diff
changeset
|
579 dst = or_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
19fb3523a9e5
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235
diff
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|
580 } else { |
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Mike Pavone <pavone@retrodev.com>
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235
diff
changeset
|
581 dst = or_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
19fb3523a9e5
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235
diff
changeset
|
582 } |
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parents:
235
diff
changeset
|
583 //TODO: Cleanup flags |
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235
diff
changeset
|
584 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
19fb3523a9e5
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235
diff
changeset
|
585 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
19fb3523a9e5
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parents:
235
diff
changeset
|
586 //TODO: Implement half-carry flag |
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Mike Pavone <pavone@retrodev.com>
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235
diff
changeset
|
587 if (z80_size(inst) == SZ_B) { |
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
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235
diff
changeset
|
588 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
19fb3523a9e5
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parents:
235
diff
changeset
|
589 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
19fb3523a9e5
Implement more Z80 instructions (untested)
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235
diff
changeset
|
590 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
19fb3523a9e5
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parents:
235
diff
changeset
|
591 } |
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235
diff
changeset
|
592 dst = z80_save_reg(dst, inst, opts); |
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
593 dst = z80_save_ea(dst, inst, opts); |
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
594 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
595 case Z80_XOR: |
236
19fb3523a9e5
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parents:
235
diff
changeset
|
596 cycles = 4; |
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parents:
235
diff
changeset
|
597 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
19fb3523a9e5
Implement more Z80 instructions (untested)
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235
diff
changeset
|
598 cycles += 12; |
19fb3523a9e5
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235
diff
changeset
|
599 } else if(inst->addr_mode == Z80_IMMED) { |
19fb3523a9e5
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parents:
235
diff
changeset
|
600 cycles += 3; |
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parents:
235
diff
changeset
|
601 } else if(z80_size(inst) == SZ_W) { |
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
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235
diff
changeset
|
602 cycles += 4; |
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
603 } |
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Mike Pavone <pavone@retrodev.com>
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235
diff
changeset
|
604 dst = zcycles(dst, cycles); |
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235
diff
changeset
|
605 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
19fb3523a9e5
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235
diff
changeset
|
606 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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235
diff
changeset
|
607 if (src_op.mode == MODE_REG_DIRECT) { |
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Mike Pavone <pavone@retrodev.com>
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235
diff
changeset
|
608 dst = add_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
19fb3523a9e5
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235
diff
changeset
|
609 } else { |
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parents:
235
diff
changeset
|
610 dst = add_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
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235
diff
changeset
|
611 } |
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235
diff
changeset
|
612 //TODO: Cleanup flags |
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235
diff
changeset
|
613 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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235
diff
changeset
|
614 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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parents:
235
diff
changeset
|
615 //TODO: Implement half-carry flag |
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235
diff
changeset
|
616 if (z80_size(inst) == SZ_B) { |
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617 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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618 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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619 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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620 } |
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621 dst = z80_save_reg(dst, inst, opts); |
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622 dst = z80_save_ea(dst, inst, opts); |
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623 break; |
242 | 624 case Z80_CP: |
625 cycles = 4; | |
626 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { | |
627 cycles += 12; | |
628 } else if(inst->addr_mode == Z80_IMMED) { | |
629 cycles += 3; | |
630 } | |
631 dst = zcycles(dst, cycles); | |
632 dst = translate_z80_reg(inst, &dst_op, dst, opts); | |
633 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); | |
634 if (src_op.mode == MODE_REG_DIRECT) { | |
635 dst = cmp_rr(dst, src_op.base, dst_op.base, z80_size(inst)); | |
636 } else { | |
637 dst = cmp_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); | |
638 } | |
639 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); | |
640 dst = mov_irdisp8(dst, 1, CONTEXT, zf_off(ZF_N), SZ_B); | |
641 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); | |
642 //TODO: Implement half-carry flag | |
643 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); | |
644 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); | |
645 dst = z80_save_reg(dst, inst, opts); | |
646 dst = z80_save_ea(dst, inst, opts); | |
647 break; | |
213
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648 case Z80_INC: |
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649 cycles = 4; |
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650 if (inst->reg == Z80_IX || inst->reg == Z80_IY) { |
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651 cycles += 6; |
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652 } else if(z80_size(inst) == SZ_W) { |
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653 cycles += 2; |
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654 } else if(inst->reg == Z80_IXH || inst->reg == Z80_IXL || inst->reg == Z80_IYH || inst->reg == Z80_IYL || inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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655 cycles += 4; |
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656 } |
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657 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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658 if (dst_op.mode == MODE_UNUSED) { |
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659 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
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660 } |
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661 dst = add_ir(dst, 1, dst_op.base, z80_size(inst)); |
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662 if (z80_size(inst) == SZ_B) { |
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663 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
213
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664 //TODO: Implement half-carry flag |
235
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665 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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666 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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667 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
213
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668 } |
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669 dst = z80_save_reg(dst, inst, opts); |
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670 dst = z80_save_ea(dst, inst, opts); |
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671 break; |
236
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672 case Z80_DEC: |
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673 cycles = 4; |
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674 if (inst->reg == Z80_IX || inst->reg == Z80_IY) { |
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675 cycles += 6; |
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676 } else if(z80_size(inst) == SZ_W) { |
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677 cycles += 2; |
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678 } else if(inst->reg == Z80_IXH || inst->reg == Z80_IXL || inst->reg == Z80_IYH || inst->reg == Z80_IYL || inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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679 cycles += 4; |
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680 } |
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681 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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682 if (dst_op.mode == MODE_UNUSED) { |
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683 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
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684 } |
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685 dst = sub_ir(dst, 1, dst_op.base, z80_size(inst)); |
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686 if (z80_size(inst) == SZ_B) { |
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687 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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688 //TODO: Implement half-carry flag |
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689 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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690 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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691 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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692 } |
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693 dst = z80_save_reg(dst, inst, opts); |
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694 dst = z80_save_ea(dst, inst, opts); |
213
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695 break; |
236
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696 /*case Z80_DAA: |
213
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697 case Z80_CPL: |
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698 case Z80_NEG: |
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699 case Z80_CCF: |
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700 case Z80_SCF:*/ |
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701 case Z80_NOP: |
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702 if (inst->immed == 42) { |
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703 dst = call(dst, (uint8_t *)z80_save_context); |
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704 dst = mov_rr(dst, CONTEXT, RDI, SZ_Q); |
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705 dst = jmp(dst, (uint8_t *)z80_print_regs_exit); |
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706 } else { |
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707 dst = zcycles(dst, 4 * inst->immed); |
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|
708 } |
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|
709 break; |
243
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710 //case Z80_HALT: |
213
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|
711 case Z80_DI: |
243
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712 dst = zcycles(dst, 4); |
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713 dst = mov_irdisp8(dst, 0, CONTEXT, offsetof(z80_context, iff1), SZ_B); |
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714 dst = mov_irdisp8(dst, 0, CONTEXT, offsetof(z80_context, iff2), SZ_B); |
250
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715 dst = mov_rdisp8r(dst, CONTEXT, offsetof(z80_context, sync_cycle), ZLIMIT, SZ_D); |
243
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242
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|
716 break; |
213
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|
717 case Z80_EI: |
243
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718 //TODO: Implement interrupt enable latency of 1 instruction afer EI |
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719 dst = zcycles(dst, 4); |
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|
720 dst = mov_irdisp8(dst, 1, CONTEXT, offsetof(z80_context, iff1), SZ_B); |
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721 dst = mov_irdisp8(dst, 1, CONTEXT, offsetof(z80_context, iff2), SZ_B); |
250
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722 dst = call(dst, (uint8_t *)z80_do_sync); |
243
2f069a0b487e
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|
723 break; |
213
4d4559b04c59
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|
724 case Z80_IM: |
243
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725 dst = zcycles(dst, 4); |
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|
726 dst = mov_irdisp8(dst, inst->immed, CONTEXT, offsetof(z80_context, im), SZ_B); |
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|
727 break; |
247
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|
728 case Z80_RLC: |
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|
729 cycles = inst->immed == 1 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8); |
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|
730 dst = zcycles(dst, cycles); |
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|
731 if (inst->reg == Z80_UNUSED) { |
682e505f5757
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diff
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|
732 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
682e505f5757
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|
733 dst = zcycles(dst, 1); |
682e505f5757
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parents:
246
diff
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|
734 } else { |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
735 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
736 } |
682e505f5757
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246
diff
changeset
|
737 dst = rol_ir(dst, 1, dst_op.base, SZ_B); |
682e505f5757
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246
diff
changeset
|
738 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
682e505f5757
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246
diff
changeset
|
739 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
682e505f5757
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parents:
246
diff
changeset
|
740 //TODO: Implement half-carry flag |
682e505f5757
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246
diff
changeset
|
741 dst = cmp_ir(dst, 0, dst_op.base, SZ_B); |
682e505f5757
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246
diff
changeset
|
742 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
682e505f5757
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parents:
246
diff
changeset
|
743 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
682e505f5757
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246
diff
changeset
|
744 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
682e505f5757
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246
diff
changeset
|
745 if (inst->reg == Z80_UNUSED) { |
682e505f5757
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246
diff
changeset
|
746 dst = z80_save_result(dst, inst); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
747 } else { |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
748 dst = z80_save_reg(dst, inst, opts); |
682e505f5757
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parents:
246
diff
changeset
|
749 } |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
750 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
751 case Z80_RL: |
247
682e505f5757
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246
diff
changeset
|
752 cycles = inst->immed == 1 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8); |
682e505f5757
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246
diff
changeset
|
753 dst = zcycles(dst, cycles); |
682e505f5757
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246
diff
changeset
|
754 if (inst->reg == Z80_UNUSED) { |
682e505f5757
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246
diff
changeset
|
755 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
682e505f5757
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246
diff
changeset
|
756 dst = zcycles(dst, 1); |
682e505f5757
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parents:
246
diff
changeset
|
757 } else { |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
758 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
759 } |
682e505f5757
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246
diff
changeset
|
760 dst = bt_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
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246
diff
changeset
|
761 dst = rcl_ir(dst, 1, dst_op.base, SZ_B); |
682e505f5757
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246
diff
changeset
|
762 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
682e505f5757
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246
diff
changeset
|
763 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
682e505f5757
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246
diff
changeset
|
764 //TODO: Implement half-carry flag |
682e505f5757
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246
diff
changeset
|
765 dst = cmp_ir(dst, 0, dst_op.base, SZ_B); |
682e505f5757
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246
diff
changeset
|
766 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
682e505f5757
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246
diff
changeset
|
767 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
682e505f5757
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246
diff
changeset
|
768 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
682e505f5757
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246
diff
changeset
|
769 if (inst->reg == Z80_UNUSED) { |
682e505f5757
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246
diff
changeset
|
770 dst = z80_save_result(dst, inst); |
682e505f5757
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parents:
246
diff
changeset
|
771 } else { |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
772 dst = z80_save_reg(dst, inst, opts); |
682e505f5757
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parents:
246
diff
changeset
|
773 } |
682e505f5757
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246
diff
changeset
|
774 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
775 case Z80_RRC: |
247
682e505f5757
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parents:
246
diff
changeset
|
776 cycles = inst->immed == 1 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8); |
682e505f5757
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246
diff
changeset
|
777 dst = zcycles(dst, cycles); |
682e505f5757
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246
diff
changeset
|
778 if (inst->reg == Z80_UNUSED) { |
682e505f5757
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246
diff
changeset
|
779 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
682e505f5757
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246
diff
changeset
|
780 dst = zcycles(dst, 1); |
682e505f5757
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parents:
246
diff
changeset
|
781 } else { |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
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246
diff
changeset
|
782 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
682e505f5757
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parents:
246
diff
changeset
|
783 } |
682e505f5757
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246
diff
changeset
|
784 dst = ror_ir(dst, 1, dst_op.base, SZ_B); |
682e505f5757
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246
diff
changeset
|
785 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
682e505f5757
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parents:
246
diff
changeset
|
786 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
682e505f5757
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parents:
246
diff
changeset
|
787 //TODO: Implement half-carry flag |
682e505f5757
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246
diff
changeset
|
788 dst = cmp_ir(dst, 0, dst_op.base, SZ_B); |
682e505f5757
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parents:
246
diff
changeset
|
789 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
682e505f5757
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246
diff
changeset
|
790 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
682e505f5757
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246
diff
changeset
|
791 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
682e505f5757
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246
diff
changeset
|
792 if (inst->reg == Z80_UNUSED) { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
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parents:
246
diff
changeset
|
793 dst = z80_save_result(dst, inst); |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
794 } else { |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
795 dst = z80_save_reg(dst, inst, opts); |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
796 } |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
797 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
798 case Z80_RR: |
247
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
799 cycles = inst->immed == 1 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8); |
682e505f5757
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parents:
246
diff
changeset
|
800 dst = zcycles(dst, cycles); |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
801 if (inst->reg == Z80_UNUSED) { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
802 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
682e505f5757
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parents:
246
diff
changeset
|
803 dst = zcycles(dst, 1); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
804 } else { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
805 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
806 } |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
807 dst = bt_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
808 dst = rcr_ir(dst, 1, dst_op.base, SZ_B); |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
809 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
810 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
811 //TODO: Implement half-carry flag |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
812 dst = cmp_ir(dst, 0, dst_op.base, SZ_B); |
682e505f5757
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parents:
246
diff
changeset
|
813 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
814 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
815 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
816 if (inst->reg == Z80_UNUSED) { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
817 dst = z80_save_result(dst, inst); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
818 } else { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
819 dst = z80_save_reg(dst, inst, opts); |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
820 } |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
821 break; |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
822 /*case Z80_SLA: |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
823 case Z80_SRA: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
824 case Z80_SLL: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
825 case Z80_SRL: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
826 case Z80_RLD: |
239
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
827 case Z80_RRD:*/ |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
828 case Z80_BIT: |
239
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
829 cycles = (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) ? 8 : 16; |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
830 dst = zcycles(dst, cycles); |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
831 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
832 if (inst->addr_mode != Z80_REG) { |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
833 //Reads normally take 3 cycles, but the read at the end of a bit instruction takes 4 |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
834 dst = zcycles(dst, 1); |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
835 } |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
836 dst = bt_ir(dst, inst->immed, src_op.base, SZ_B); |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
837 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_Z)); |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
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238
diff
changeset
|
838 break; |
247
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
839 case Z80_SET: |
682e505f5757
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246
diff
changeset
|
840 cycles = (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) ? 8 : 16; |
682e505f5757
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246
diff
changeset
|
841 dst = zcycles(dst, cycles); |
682e505f5757
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parents:
246
diff
changeset
|
842 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
682e505f5757
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246
diff
changeset
|
843 if (inst->addr_mode != Z80_REG) { |
682e505f5757
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246
diff
changeset
|
844 //Reads normally take 3 cycles, but the read in the middle of a set instruction takes 4 |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
845 dst = zcycles(dst, 1); |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
846 } |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
847 dst = bts_ir(dst, inst->immed, src_op.base, SZ_B); |
682e505f5757
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246
diff
changeset
|
848 if (inst->addr_mode != Z80_REG) { |
682e505f5757
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246
diff
changeset
|
849 dst = z80_save_result(dst, inst); |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
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246
diff
changeset
|
850 } |
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
851 break; |
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Mike Pavone <pavone@retrodev.com>
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246
diff
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|
852 case Z80_RES: |
682e505f5757
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246
diff
changeset
|
853 cycles = (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) ? 8 : 16; |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
854 dst = zcycles(dst, cycles); |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
855 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
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246
diff
changeset
|
856 if (inst->addr_mode != Z80_REG) { |
682e505f5757
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parents:
246
diff
changeset
|
857 //Reads normally take 3 cycles, but the read in the middle of a set instruction takes 4 |
682e505f5757
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diff
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|
858 dst = zcycles(dst, 1); |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
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246
diff
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|
859 } |
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246
diff
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|
860 dst = btr_ir(dst, inst->immed, src_op.base, SZ_B); |
682e505f5757
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246
diff
changeset
|
861 if (inst->addr_mode != Z80_REG) { |
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246
diff
changeset
|
862 dst = z80_save_result(dst, inst); |
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246
diff
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|
863 } |
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246
diff
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|
864 break; |
236
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235
diff
changeset
|
865 case Z80_JP: { |
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235
diff
changeset
|
866 cycles = 4; |
239
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
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parents:
238
diff
changeset
|
867 if (inst->addr_mode != Z80_REG) { |
236
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235
diff
changeset
|
868 cycles += 6; |
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|
869 } else if(inst->ea_reg == Z80_IX || inst->ea_reg == Z80_IY) { |
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235
diff
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|
870 cycles += 4; |
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235
diff
changeset
|
871 } |
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|
872 dst = zcycles(dst, cycles); |
239
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
873 if (inst->addr_mode != Z80_REG_INDIRECT && inst->immed < 0x4000) { |
236
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235
diff
changeset
|
874 uint8_t * call_dst = z80_get_native_address(context, inst->immed); |
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|
875 if (!call_dst) { |
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235
diff
changeset
|
876 opts->deferred = defer_address(opts->deferred, inst->immed, dst + 1); |
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235
diff
changeset
|
877 //fake address to force large displacement |
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235
diff
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|
878 call_dst = dst + 256; |
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235
diff
changeset
|
879 } |
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Mike Pavone <pavone@retrodev.com>
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diff
changeset
|
880 dst = jmp(dst, call_dst); |
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235
diff
changeset
|
881 } else { |
239
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
882 if (inst->addr_mode == Z80_REG_INDIRECT) { |
236
19fb3523a9e5
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235
diff
changeset
|
883 dst = mov_rr(dst, opts->regs[inst->ea_reg], SCRATCH1, SZ_W); |
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Mike Pavone <pavone@retrodev.com>
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235
diff
changeset
|
884 } else { |
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235
diff
changeset
|
885 dst = mov_ir(dst, inst->immed, SCRATCH1, SZ_W); |
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235
diff
changeset
|
886 } |
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235
diff
changeset
|
887 dst = call(dst, (uint8_t *)z80_native_addr); |
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235
diff
changeset
|
888 dst = jmp_r(dst, SCRATCH1); |
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parents:
235
diff
changeset
|
889 } |
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235
diff
changeset
|
890 break; |
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235
diff
changeset
|
891 } |
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235
diff
changeset
|
892 case Z80_JPCC: { |
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Implement more Z80 instructions (untested)
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235
diff
changeset
|
893 dst = zcycles(dst, 7);//T States: 4,3 |
19fb3523a9e5
Implement more Z80 instructions (untested)
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235
diff
changeset
|
894 uint8_t cond = CC_Z; |
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235
diff
changeset
|
895 switch (inst->reg) |
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
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235
diff
changeset
|
896 { |
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parents:
235
diff
changeset
|
897 case Z80_CC_NZ: |
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Implement more Z80 instructions (untested)
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235
diff
changeset
|
898 cond = CC_NZ; |
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235
diff
changeset
|
899 case Z80_CC_Z: |
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Implement more Z80 instructions (untested)
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235
diff
changeset
|
900 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_Z), SZ_B); |
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parents:
235
diff
changeset
|
901 break; |
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235
diff
changeset
|
902 case Z80_CC_NC: |
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Implement more Z80 instructions (untested)
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235
diff
changeset
|
903 cond = CC_NZ; |
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Implement more Z80 instructions (untested)
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235
diff
changeset
|
904 case Z80_CC_C: |
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Implement more Z80 instructions (untested)
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235
diff
changeset
|
905 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
906 break; |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
907 case Z80_CC_PO: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
908 cond = CC_NZ; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
909 case Z80_CC_PE: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
910 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_PV), SZ_B); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
911 break; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
912 case Z80_CC_P: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
913 case Z80_CC_M: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
914 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_S), SZ_B); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
915 break; |
236
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
916 } |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
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235
diff
changeset
|
917 uint8_t *no_jump_off = dst+1; |
19fb3523a9e5
Implement more Z80 instructions (untested)
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parents:
235
diff
changeset
|
918 dst = jcc(dst, cond, dst+2); |
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
919 dst = zcycles(dst, 5);//T States: 5 |
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
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235
diff
changeset
|
920 uint16_t dest_addr = inst->immed; |
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parents:
235
diff
changeset
|
921 if (dest_addr < 0x4000) { |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
922 uint8_t * call_dst = z80_get_native_address(context, dest_addr); |
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
923 if (!call_dst) { |
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
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235
diff
changeset
|
924 opts->deferred = defer_address(opts->deferred, dest_addr, dst + 1); |
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
925 //fake address to force large displacement |
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
926 call_dst = dst + 256; |
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
927 } |
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Mike Pavone <pavone@retrodev.com>
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235
diff
changeset
|
928 dst = jmp(dst, call_dst); |
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
929 } else { |
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
930 dst = mov_ir(dst, dest_addr, SCRATCH1, SZ_W); |
19fb3523a9e5
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235
diff
changeset
|
931 dst = call(dst, (uint8_t *)z80_native_addr); |
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235
diff
changeset
|
932 dst = jmp_r(dst, SCRATCH1); |
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
933 } |
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
934 *no_jump_off = dst - (no_jump_off+1); |
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
935 break; |
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parents:
235
diff
changeset
|
936 } |
19fb3523a9e5
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235
diff
changeset
|
937 case Z80_JR: { |
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235
diff
changeset
|
938 dst = zcycles(dst, 12);//T States: 4,3,5 |
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
939 uint16_t dest_addr = address + inst->immed + 2; |
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
940 if (dest_addr < 0x4000) { |
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235
diff
changeset
|
941 uint8_t * call_dst = z80_get_native_address(context, dest_addr); |
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235
diff
changeset
|
942 if (!call_dst) { |
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
943 opts->deferred = defer_address(opts->deferred, dest_addr, dst + 1); |
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
944 //fake address to force large displacement |
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
945 call_dst = dst + 256; |
19fb3523a9e5
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parents:
235
diff
changeset
|
946 } |
19fb3523a9e5
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235
diff
changeset
|
947 dst = jmp(dst, call_dst); |
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
948 } else { |
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
949 dst = mov_ir(dst, dest_addr, SCRATCH1, SZ_W); |
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
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235
diff
changeset
|
950 dst = call(dst, (uint8_t *)z80_native_addr); |
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951 dst = jmp_r(dst, SCRATCH1); |
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952 } |
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953 break; |
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954 } |
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955 case Z80_JRCC: { |
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956 dst = zcycles(dst, 7);//T States: 4,3 |
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957 uint8_t cond = CC_Z; |
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958 switch (inst->reg) |
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959 { |
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960 case Z80_CC_NZ: |
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961 cond = CC_NZ; |
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962 case Z80_CC_Z: |
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963 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_Z), SZ_B); |
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964 break; |
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965 case Z80_CC_NC: |
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966 cond = CC_NZ; |
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967 case Z80_CC_C: |
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968 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
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969 break; |
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970 } |
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971 uint8_t *no_jump_off = dst+1; |
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972 dst = jcc(dst, cond, dst+2); |
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973 dst = zcycles(dst, 5);//T States: 5 |
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974 uint16_t dest_addr = address + inst->immed + 2; |
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975 if (dest_addr < 0x4000) { |
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976 uint8_t * call_dst = z80_get_native_address(context, dest_addr); |
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977 if (!call_dst) { |
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978 opts->deferred = defer_address(opts->deferred, dest_addr, dst + 1); |
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979 //fake address to force large displacement |
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980 call_dst = dst + 256; |
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981 } |
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982 dst = jmp(dst, call_dst); |
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983 } else { |
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984 dst = mov_ir(dst, dest_addr, SCRATCH1, SZ_W); |
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985 dst = call(dst, (uint8_t *)z80_native_addr); |
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986 dst = jmp_r(dst, SCRATCH1); |
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987 } |
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988 *no_jump_off = dst - (no_jump_off+1); |
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989 break; |
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990 } |
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991 case Z80_DJNZ: |
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992 dst = zcycles(dst, 8);//T States: 5,3 |
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993 dst = sub_ir(dst, 1, opts->regs[Z80_B], SZ_B); |
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994 uint8_t *no_jump_off = dst+1; |
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995 dst = jcc(dst, CC_Z, dst+2); |
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996 dst = zcycles(dst, 5);//T States: 5 |
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997 uint16_t dest_addr = address + inst->immed + 2; |
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998 if (dest_addr < 0x4000) { |
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999 uint8_t * call_dst = z80_get_native_address(context, dest_addr); |
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1000 if (!call_dst) { |
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1001 opts->deferred = defer_address(opts->deferred, dest_addr, dst + 1); |
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1002 //fake address to force large displacement |
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1003 call_dst = dst + 256; |
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1004 } |
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1005 dst = jmp(dst, call_dst); |
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1006 } else { |
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1007 dst = mov_ir(dst, dest_addr, SCRATCH1, SZ_W); |
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1008 dst = call(dst, (uint8_t *)z80_native_addr); |
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1009 dst = jmp_r(dst, SCRATCH1); |
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1010 } |
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1011 *no_jump_off = dst - (no_jump_off+1); |
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1012 break; |
235
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1013 case Z80_CALL: { |
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1014 dst = zcycles(dst, 11);//T States: 4,3,4 |
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1015 dst = sub_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
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1016 dst = mov_ir(dst, address + 3, SCRATCH2, SZ_W); |
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1017 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
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1018 dst = call(dst, (uint8_t *)z80_write_word_highfirst);//T States: 3, 3 |
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1019 if (inst->immed < 0x4000) { |
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1020 uint8_t * call_dst = z80_get_native_address(context, inst->immed); |
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1021 if (!call_dst) { |
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1022 opts->deferred = defer_address(opts->deferred, inst->immed, dst + 1); |
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1023 //fake address to force large displacement |
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1024 call_dst = dst + 256; |
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1025 } |
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1026 dst = jmp(dst, call_dst); |
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1027 } else { |
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1028 dst = mov_ir(dst, inst->immed, SCRATCH1, SZ_W); |
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1029 dst = call(dst, (uint8_t *)z80_native_addr); |
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1030 dst = jmp_r(dst, SCRATCH1); |
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1031 } |
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|
1032 break; |
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|
1033 } |
238
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1034 case Z80_CALLCC: |
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1035 dst = zcycles(dst, 10);//T States: 4,3,3 (false case) |
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1036 uint8_t cond = CC_Z; |
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1037 switch (inst->reg) |
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1038 { |
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1039 case Z80_CC_NZ: |
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1040 cond = CC_NZ; |
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|
1041 case Z80_CC_Z: |
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1042 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_Z), SZ_B); |
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|
1043 break; |
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|
1044 case Z80_CC_NC: |
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|
1045 cond = CC_NZ; |
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1046 case Z80_CC_C: |
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|
1047 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
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1048 break; |
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|
1049 case Z80_CC_PO: |
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|
1050 cond = CC_NZ; |
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1051 case Z80_CC_PE: |
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|
1052 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_PV), SZ_B); |
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|
1053 break; |
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|
1054 case Z80_CC_P: |
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|
1055 case Z80_CC_M: |
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|
1056 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_S), SZ_B); |
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|
1057 break; |
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|
1058 } |
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|
1059 uint8_t *no_call_off = dst+1; |
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|
1060 dst = jcc(dst, cond, dst+2); |
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|
1061 dst = zcycles(dst, 1);//Last of the above T states takes an extra cycle in the true case |
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236
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|
1062 dst = sub_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
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236
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|
1063 dst = mov_ir(dst, address + 3, SCRATCH2, SZ_W); |
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236
diff
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|
1064 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
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236
diff
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|
1065 dst = call(dst, (uint8_t *)z80_write_word_highfirst);//T States: 3, 3 |
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236
diff
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|
1066 if (inst->immed < 0x4000) { |
827ebce557bf
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236
diff
changeset
|
1067 uint8_t * call_dst = z80_get_native_address(context, inst->immed); |
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236
diff
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|
1068 if (!call_dst) { |
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236
diff
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|
1069 opts->deferred = defer_address(opts->deferred, inst->immed, dst + 1); |
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236
diff
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|
1070 //fake address to force large displacement |
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236
diff
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|
1071 call_dst = dst + 256; |
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236
diff
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|
1072 } |
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236
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|
1073 dst = jmp(dst, call_dst); |
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236
diff
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|
1074 } else { |
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Added the rest of the conditions to JPCC, implemented CALLCC (untested)
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236
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|
1075 dst = mov_ir(dst, inst->immed, SCRATCH1, SZ_W); |
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|
1076 dst = call(dst, (uint8_t *)z80_native_addr); |
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236
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|
1077 dst = jmp_r(dst, SCRATCH1); |
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|
1078 } |
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236
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|
1079 *no_call_off = dst - (no_call_off+1); |
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236
diff
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|
1080 break; |
213
4d4559b04c59
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diff
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|
1081 case Z80_RET: |
235
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|
1082 dst = zcycles(dst, 4);//T States: 4 |
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Get Z80 core working for simple programs
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1083 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
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1084 dst = call(dst, (uint8_t *)z80_read_word);//T STates: 3, 3 |
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1085 dst = add_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
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|
1086 dst = call(dst, (uint8_t *)z80_native_addr); |
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1087 dst = jmp_r(dst, SCRATCH1); |
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|
1088 break; |
246
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Implement RETCC in Z80 core.
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243
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|
1089 case Z80_RETCC: { |
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Implement RETCC in Z80 core.
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|
1090 dst = zcycles(dst, 5);//T States: 5 |
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Implement RETCC in Z80 core.
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1091 uint8_t cond = CC_Z; |
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Implement RETCC in Z80 core.
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1092 switch (inst->reg) |
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Implement RETCC in Z80 core.
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|
1093 { |
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|
1094 case Z80_CC_NZ: |
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Implement RETCC in Z80 core.
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|
1095 cond = CC_NZ; |
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Implement RETCC in Z80 core.
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1096 case Z80_CC_Z: |
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1097 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_Z), SZ_B); |
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|
1098 break; |
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Implement RETCC in Z80 core.
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|
1099 case Z80_CC_NC: |
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1100 cond = CC_NZ; |
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|
1101 case Z80_CC_C: |
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1102 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
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|
1103 break; |
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|
1104 case Z80_CC_PO: |
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Implement RETCC in Z80 core.
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1105 cond = CC_NZ; |
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|
1106 case Z80_CC_PE: |
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Implement RETCC in Z80 core.
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|
1107 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_PV), SZ_B); |
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243
diff
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|
1108 break; |
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|
1109 case Z80_CC_P: |
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Implement RETCC in Z80 core.
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|
1110 case Z80_CC_M: |
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|
1111 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_S), SZ_B); |
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243
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changeset
|
1112 break; |
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243
diff
changeset
|
1113 } |
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Implement RETCC in Z80 core.
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243
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|
1114 uint8_t *no_call_off = dst+1; |
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Implement RETCC in Z80 core.
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243
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|
1115 dst = jcc(dst, cond, dst+2); |
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243
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|
1116 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
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243
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|
1117 dst = call(dst, (uint8_t *)z80_read_word);//T STates: 3, 3 |
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243
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|
1118 dst = add_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
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|
1119 dst = call(dst, (uint8_t *)z80_native_addr); |
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Implement RETCC in Z80 core.
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243
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|
1120 dst = jmp_r(dst, SCRATCH1); |
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Implement RETCC in Z80 core.
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243
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|
1121 *no_call_off = dst - (no_call_off+1); |
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243
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|
1122 break; |
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243
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|
1123 } |
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243
diff
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|
1124 /*case Z80_RETI: |
241
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Implement EX, EXX and RST in Z80 core
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239
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|
1125 case Z80_RETN:*/ |
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|
1126 case Z80_RST: { |
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239
diff
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|
1127 //RST is basically CALL to an address in page 0 |
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239
diff
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|
1128 dst = zcycles(dst, 5);//T States: 5 |
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Implement EX, EXX and RST in Z80 core
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239
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|
1129 dst = sub_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
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239
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|
1130 dst = mov_ir(dst, address + 3, SCRATCH2, SZ_W); |
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239
diff
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|
1131 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
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239
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|
1132 dst = call(dst, (uint8_t *)z80_write_word_highfirst);//T States: 3, 3 |
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239
diff
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|
1133 uint8_t * call_dst = z80_get_native_address(context, inst->immed); |
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239
diff
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|
1134 if (!call_dst) { |
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239
diff
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|
1135 opts->deferred = defer_address(opts->deferred, inst->immed, dst + 1); |
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239
diff
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|
1136 //fake address to force large displacement |
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Implement EX, EXX and RST in Z80 core
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239
diff
changeset
|
1137 call_dst = dst + 256; |
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239
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|
1138 } |
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Implement EX, EXX and RST in Z80 core
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|
1139 dst = jmp(dst, call_dst); |
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Implement EX, EXX and RST in Z80 core
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239
diff
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|
1140 break; |
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239
diff
changeset
|
1141 } |
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239
diff
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|
1142 /*case Z80_IN: |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
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diff
changeset
|
1143 case Z80_INI: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1144 case Z80_INIR: |
4d4559b04c59
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1145 case Z80_IND: |
4d4559b04c59
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1146 case Z80_INDR: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1147 case Z80_OUT: |
4d4559b04c59
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1148 case Z80_OUTI: |
4d4559b04c59
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1149 case Z80_OTIR: |
4d4559b04c59
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1150 case Z80_OUTD: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
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|
1151 case Z80_OTDR:*/ |
235
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213
diff
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|
1152 default: { |
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diff
changeset
|
1153 char disbuf[80]; |
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213
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|
1154 z80_disasm(inst, disbuf); |
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213
diff
changeset
|
1155 fprintf(stderr, "unimplemented instruction: %s\n", disbuf); |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1156 exit(1); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1157 } |
235
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213
diff
changeset
|
1158 } |
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213
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|
1159 return dst; |
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213
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changeset
|
1160 } |
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|
1161 |
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|
1162 uint8_t * z80_get_native_address(z80_context * context, uint32_t address) |
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|
1163 { |
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|
1164 native_map_slot *map; |
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|
1165 if (address < 0x4000) { |
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|
1166 address &= 0x1FFF; |
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|
1167 map = context->static_code_map; |
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changeset
|
1168 } else if (address >= 0x8000) { |
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|
1169 address &= 0x7FFF; |
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|
1170 map = context->banked_code_map + context->bank_reg; |
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|
1171 } else { |
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|
1172 return NULL; |
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1173 } |
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1174 if (!map->base || !map->offsets || map->offsets[address] == INVALID_OFFSET) { |
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1175 return NULL; |
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1176 } |
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1177 return map->base + map->offsets[address]; |
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1178 } |
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1179 |
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1180 //TODO: Record z80 instruction size and code size for addresses to support modification of translated code |
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1181 void z80_map_native_address(z80_context * context, uint32_t address, uint8_t * native_address) |
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1182 { |
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1183 native_map_slot *map; |
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1184 if (address < 0x4000) { |
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1185 address &= 0x1FFF; |
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1186 map = context->static_code_map; |
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1187 } else if (address >= 0x8000) { |
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1188 address &= 0x7FFF; |
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1189 map = context->banked_code_map + context->bank_reg; |
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1190 if (!map->offsets) { |
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1191 map->offsets = malloc(sizeof(int32_t) * 0x8000); |
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1192 memset(map->offsets, 0xFF, sizeof(int32_t) * 0x8000); |
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1193 } |
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1194 } else { |
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1195 return; |
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1196 } |
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1197 if (!map->base) { |
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1198 map->base = native_address; |
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1199 } |
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1200 map->offsets[address] = native_address - map->base; |
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1201 } |
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1202 |
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1203 uint8_t * z80_get_native_address_trans(z80_context * context, uint32_t address) |
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1204 { |
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1205 uint8_t * addr = z80_get_native_address(context, address); |
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1206 if (!addr) { |
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1207 translate_z80_stream(context, address); |
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1208 addr = z80_get_native_address(context, address); |
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1209 if (!addr) { |
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1210 printf("Failed to translate %X to native code\n", address); |
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1211 } |
235
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1212 } |
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1213 return addr; |
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1214 } |
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1215 |
248
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1216 //uint32_t max_size = 0; |
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1217 |
235
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1218 void translate_z80_stream(z80_context * context, uint32_t address) |
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1219 { |
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1220 char disbuf[80]; |
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1221 if (z80_get_native_address(context, address)) { |
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1222 return; |
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1223 } |
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1224 x86_z80_options * opts = context->options; |
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1225 uint8_t * encoded = NULL, *next; |
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1226 if (address < 0x4000) { |
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1227 encoded = context->mem_pointers[0] + (address & 0x1FFF); |
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1228 } else if(address >= 0x8000 && context->mem_pointers[1]) { |
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1229 encoded = context->mem_pointers[1] + (address & 0x7FFF); |
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1230 } |
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1231 while (encoded != NULL) |
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1232 { |
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1233 z80inst inst; |
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1234 printf("translating Z80 code at address %X\n", address); |
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1235 do { |
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1236 if (opts->code_end-opts->cur_code < MAX_NATIVE_SIZE) { |
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1237 if (opts->code_end-opts->cur_code < 5) { |
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1238 puts("out of code memory, not enough space for jmp to next chunk"); |
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1239 exit(1); |
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1240 } |
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1241 size_t size = 1024*1024; |
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1242 opts->cur_code = alloc_code(&size); |
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1243 opts->code_end = opts->cur_code + size; |
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1244 jmp(opts->cur_code, opts->cur_code); |
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1245 } |
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1246 if (address > 0x4000 & address < 0x8000) { |
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1247 opts->cur_code = xor_rr(opts->cur_code, RDI, RDI, SZ_D); |
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1248 opts->cur_code = call(opts->cur_code, (uint8_t *)exit); |
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1249 break; |
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1250 } |
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1251 uint8_t * existing = z80_get_native_address(context, address); |
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1252 if (existing) { |
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1253 opts->cur_code = jmp(opts->cur_code, existing); |
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|
1254 break; |
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1255 } |
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1256 next = z80_decode(encoded, &inst); |
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1257 z80_disasm(&inst, disbuf); |
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1258 if (inst.op == Z80_NOP) { |
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1259 printf("%X\t%s(%d)\n", address, disbuf, inst.immed); |
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1260 } else { |
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1261 printf("%X\t%s\n", address, disbuf); |
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1262 } |
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1263 z80_map_native_address(context, address, opts->cur_code); |
248
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1264 uint8_t *after = translate_z80inst(&inst, opts->cur_code, context, address); |
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1265 //max_size = (after - opts->cur_code) > max_size ? (after - opts->cur_code) : max_size; |
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1266 opts->cur_code = after; |
235
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1267 address += next-encoded; |
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1268 encoded = next; |
246
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Implement RETCC in Z80 core.
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1269 } while (!(inst.op == Z80_RET || inst.op == Z80_RETI || inst.op == Z80_RETN || inst.op == Z80_JP || (inst.op = Z80_NOP && inst.immed == 42))); |
235
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1270 process_deferred(&opts->deferred, context, (native_addr_func)z80_get_native_address); |
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1271 if (opts->deferred) { |
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1272 address = opts->deferred->address; |
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1273 printf("defferred address: %X\n", address); |
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1274 if (address < 0x4000) { |
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1275 encoded = context->mem_pointers[0] + (address & 0x1FFF); |
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1276 } else if (address > 0x8000 && context->mem_pointers[1]) { |
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1277 encoded = context->mem_pointers[1] + (address & 0x7FFF); |
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1278 } else { |
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1279 printf("attempt to translate non-memory address: %X\n", address); |
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1280 exit(1); |
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1281 } |
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|
1282 } else { |
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|
1283 encoded = NULL; |
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1284 } |
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1285 } |
213
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|
1286 } |
4d4559b04c59
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1287 |
235
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1288 void init_x86_z80_opts(x86_z80_options * options) |
213
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1289 { |
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1290 options->flags = 0; |
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1291 options->regs[Z80_B] = BH; |
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1292 options->regs[Z80_C] = RBX; |
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1293 options->regs[Z80_D] = CH; |
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1294 options->regs[Z80_E] = RCX; |
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1295 options->regs[Z80_H] = AH; |
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1296 options->regs[Z80_L] = RAX; |
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1297 options->regs[Z80_IXH] = DH; |
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1298 options->regs[Z80_IXL] = RDX; |
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1299 options->regs[Z80_IYH] = -1; |
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1300 options->regs[Z80_IYL] = R8; |
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1301 options->regs[Z80_I] = -1; |
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1302 options->regs[Z80_R] = -1; |
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1303 options->regs[Z80_A] = R10; |
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1304 options->regs[Z80_BC] = RBX; |
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1305 options->regs[Z80_DE] = RCX; |
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1306 options->regs[Z80_HL] = RAX; |
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1307 options->regs[Z80_SP] = R9; |
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1308 options->regs[Z80_AF] = -1; |
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1309 options->regs[Z80_IX] = RDX; |
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1310 options->regs[Z80_IY] = R8; |
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1311 size_t size = 1024 * 1024; |
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1312 options->cur_code = alloc_code(&size); |
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1313 options->code_end = options->cur_code + size; |
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1314 options->deferred = NULL; |
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1315 } |
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1316 |
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1317 void init_z80_context(z80_context * context, x86_z80_options * options) |
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1318 { |
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1319 memset(context, 0, sizeof(*context)); |
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1320 context->static_code_map = malloc(sizeof(context->static_code_map)); |
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1321 context->static_code_map->offsets = malloc(sizeof(int32_t) * 0x2000); |
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1322 memset(context->static_code_map->offsets, 0xFF, sizeof(int32_t) * 0x2000); |
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1323 context->banked_code_map = malloc(sizeof(native_map_slot) * (1 << 9)); |
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1324 context->options = options; |
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1325 } |
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1326 |
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1327 void z80_reset(z80_context * context) |
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1328 { |
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1329 context->native_pc = z80_get_native_address_trans(context, 0); |
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1330 } |
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1331 |
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1332 |