Mercurial > repos > blastem
annotate segacd.c @ 2119:5ec2f97365a2
More accurate RET/DMNA implementation
author | Michael Pavone <pavone@retrodev.com> |
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date | Tue, 08 Mar 2022 23:28:06 -0800 |
parents | cd057d6fe030 |
children | 91ed3c4cdfd9 |
rev | line source |
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1502
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Initial skeleton of Sega CD memory handlers
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1 #include <stdlib.h> |
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2 #include <string.h> |
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3 #include "cd_graphics.h" |
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4 #include "genesis.h" |
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5 #include "util.h" |
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6 #include "debug.h" |
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7 #include "gdb_remote.h" |
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8 |
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9 #define SCD_MCLKS 50000000 |
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10 #define SCD_PERIPH_RESET_CLKS (SCD_MCLKS / 10) |
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11 #define TIMER_TICK_CLKS 1536 |
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12 |
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13 enum { |
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14 GA_SUB_CPU_CTRL, |
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15 GA_MEM_MODE, |
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16 GA_CDC_CTRL, |
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17 GA_CDC_REG_DATA, |
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18 GA_CDC_HOST_DATA, |
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19 GA_CDC_DMA_ADDR, |
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20 GA_STOP_WATCH, |
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21 GA_COMM_FLAG, |
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22 GA_COMM_CMD0, |
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23 GA_COMM_CMD1, |
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24 GA_COMM_CMD2, |
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25 GA_COMM_CMD3, |
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26 GA_COMM_CMD4, |
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27 GA_COMM_CMD5, |
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28 GA_COMM_CMD6, |
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29 GA_COMM_CMD7, |
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30 GA_COMM_STATUS0, |
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31 GA_COMM_STATUS1, |
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32 GA_COMM_STATUS2, |
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33 GA_COMM_STATUS3, |
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34 GA_COMM_STATUS4, |
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35 GA_COMM_STATUS5, |
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36 GA_COMM_STATUS6, |
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37 GA_COMM_STATUS7, |
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38 GA_TIMER, |
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39 GA_INT_MASK, |
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40 GA_CDD_FADER, |
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41 GA_CDD_CTRL, |
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42 GA_CDD_STATUS0, |
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43 GA_CDD_STATUS1, |
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44 GA_CDD_STATUS2, |
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45 GA_CDD_STATUS3, |
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46 GA_CDD_STATUS4, |
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47 GA_CDD_CMD0, |
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48 GA_CDD_CMD1, |
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49 GA_CDD_CMD2, |
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50 GA_CDD_CMD3, |
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51 GA_CDD_CMD4, |
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52 GA_FONT_COLOR, |
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53 GA_FONT_BITS, |
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54 GA_FONT_DATA0, |
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55 GA_FONT_DATA1, |
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56 GA_FONT_DATA2, |
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57 GA_FONT_DATA3, |
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58 GA_SUBCODE_START = 0x80, |
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59 GA_SUBCODE_MIRROR = 0xC0, |
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60 |
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61 GA_HINT_VECTOR = GA_CDC_REG_DATA |
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62 }; |
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63 //GA_SUB_CPU_CTRL |
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64 #define BIT_IEN2 0x8000 |
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65 #define BIT_IFL2 0x0100 |
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66 #define BIT_LEDG 0x0200 |
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67 #define BIT_LEDR 0x0100 |
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68 #define BIT_SBRQ 0x0002 |
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69 #define BIT_SRES 0x0001 |
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70 #define BIT_PRES 0x0001 |
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71 //GA_MEM_MODE |
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72 #define MASK_PROG_BANK 0x00C0 |
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73 #define BIT_OVERWRITE 0x0010 |
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74 #define BIT_UNDERWRITE 0x0008 |
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75 #define MASK_PRIORITY (BIT_OVERWRITE|BIT_UNDERWRITE) |
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76 #define BIT_MEM_MODE 0x0004 |
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77 #define BIT_DMNA 0x0002 |
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78 #define BIT_RET 0x0001 |
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79 |
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80 //GA_CDC_CTRL |
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81 #define BIT_EDT 0x8000 |
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82 #define BIT_DSR 0x4000 |
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83 |
2080 | 84 //GA_CDD_CTRL |
85 #define BIT_MUTE 0x0100 | |
86 | |
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87 enum { |
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88 DST_MAIN_CPU = 2, |
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89 DST_SUB_CPU, |
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90 DST_PCM_RAM, |
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91 DST_PROG_RAM, |
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92 DST_WORD_RAM = 7 |
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93 }; |
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94 |
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95 //GA_INT_MASK |
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96 #define BIT_MASK_IEN1 0x0002 |
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97 #define BIT_MASK_IEN2 0x0004 |
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98 #define BIT_MASK_IEN3 0x0008 |
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99 #define BIT_MASK_IEN4 0x0010 |
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100 #define BIT_MASK_IEN5 0x0020 |
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101 #define BIT_MASK_IEN6 0x0040 |
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102 |
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103 //GA_CDD_CTRL |
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104 #define BIT_HOCK 0x0004 |
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105 |
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106 static void *prog_ram_wp_write16(uint32_t address, void *vcontext, uint16_t value) |
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107 { |
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108 m68k_context *m68k = vcontext; |
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109 segacd_context *cd = m68k->system; |
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110 //if (!(cd->gate_array[GA_MEM_MODE] & (1 << ((address >> 9) + 8)))) { |
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111 if (address >= ((cd->gate_array[GA_MEM_MODE] & 0xFF00) << 1)) { |
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112 cd->prog_ram[address >> 1] = value; |
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113 m68k_invalidate_code_range(m68k, address, address + 2); |
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114 } |
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115 return vcontext; |
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116 } |
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117 |
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118 static void *prog_ram_wp_write8(uint32_t address, void *vcontext, uint8_t value) |
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119 { |
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120 m68k_context *m68k = vcontext; |
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121 segacd_context *cd = m68k->system; |
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122 if (address >= ((cd->gate_array[GA_MEM_MODE] & 0xFF00) << 1)) { |
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123 ((uint8_t *)cd->prog_ram)[address ^ 1] = value; |
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124 m68k_invalidate_code_range(m68k, address, address + 1); |
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125 } |
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126 return vcontext; |
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127 } |
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128 |
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129 static uint16_t word_ram_2M_read16(uint32_t address, void *vcontext) |
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130 { |
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131 m68k_context *m68k = vcontext; |
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132 //TODO: fixme for interleaving |
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133 uint16_t* bank = m68k->mem_pointers[1]; |
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134 if (!bank) { |
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135 return 0xFFFF; |
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136 } |
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137 uint16_t raw = bank[address >> 2]; |
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138 if (address & 2) { |
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139 return (raw & 0xF) | (raw << 4 & 0xF00); |
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140 } else { |
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141 return (raw >> 4 & 0xF00) | (raw >> 8 & 0xF); |
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142 } |
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143 } |
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144 |
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145 static uint8_t word_ram_2M_read8(uint32_t address, void *vcontext) |
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146 { |
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147 uint16_t word = word_ram_2M_read16(address, vcontext); |
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148 if (address & 1) { |
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149 return word; |
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150 } |
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151 return word >> 8; |
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152 } |
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153 |
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154 static void *word_ram_2M_write8(uint32_t address, void *vcontext, uint8_t value) |
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155 { |
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156 m68k_context *m68k = vcontext; |
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157 segacd_context *cd = m68k->system; |
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158 value &= 0xF; |
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159 uint16_t priority = cd->gate_array[GA_MEM_MODE] & MASK_PRIORITY; |
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160 |
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161 if (priority == BIT_OVERWRITE && !value) { |
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162 return vcontext; |
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163 } |
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164 if (priority == BIT_UNDERWRITE) { |
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165 if (!value) { |
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166 return vcontext; |
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167 } |
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168 uint8_t old = word_ram_2M_read8(address, vcontext); |
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169 if (old) { |
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170 return vcontext; |
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171 } |
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172 } |
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173 uint16_t* bank = m68k->mem_pointers[1]; |
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174 if (!bank) { |
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175 return vcontext; |
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176 } |
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177 uint16_t raw = bank[address >> 2]; |
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178 uint16_t shift = ((address & 3) * 4); |
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179 raw &= ~(0xF000 >> shift); |
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180 raw |= value << (12 - shift); |
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181 bank[address >> 2] = raw; |
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182 return vcontext; |
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183 } |
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184 |
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185 |
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186 static void *word_ram_2M_write16(uint32_t address, void *vcontext, uint16_t value) |
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187 { |
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188 word_ram_2M_write8(address, vcontext, value >> 8); |
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189 return word_ram_2M_write8(address + 1, vcontext, value); |
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190 } |
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191 |
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192 static uint16_t word_ram_1M_read16(uint32_t address, void *vcontext) |
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193 { |
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194 return 0; |
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195 } |
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196 |
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197 static uint8_t word_ram_1M_read8(uint32_t address, void *vcontext) |
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198 { |
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199 return 0; |
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200 } |
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201 |
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202 static void *word_ram_1M_write16(uint32_t address, void *vcontext, uint16_t value) |
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203 { |
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204 return vcontext; |
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205 } |
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206 |
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207 static void *word_ram_1M_write8(uint32_t address, void *vcontext, uint8_t value) |
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208 { |
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209 return vcontext; |
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210 } |
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211 |
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212 |
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213 static uint16_t unmapped_prog_read16(uint32_t address, void *vcontext) |
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214 { |
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215 return 0xFFFF; |
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216 } |
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217 |
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218 static uint8_t unmapped_prog_read8(uint32_t address, void *vcontext) |
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219 { |
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220 return 0xFF; |
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221 } |
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222 |
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223 static void *unmapped_prog_write16(uint32_t address, void *vcontext, uint16_t value) |
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224 { |
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225 return vcontext; |
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226 } |
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227 |
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228 static void *unmapped_prog_write8(uint32_t address, void *vcontext, uint8_t value) |
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229 { |
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230 return vcontext; |
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231 } |
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232 |
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233 static uint16_t unmapped_word_read16(uint32_t address, void *vcontext) |
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234 { |
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235 return 0xFFFF; |
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236 } |
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237 |
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238 static uint8_t unmapped_word_read8(uint32_t address, void *vcontext) |
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239 { |
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240 return 0xFF; |
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241 } |
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242 |
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243 static void *unmapped_word_write16(uint32_t address, void *vcontext, uint16_t value) |
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244 { |
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245 return vcontext; |
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246 } |
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247 |
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248 static void *unmapped_word_write8(uint32_t address, void *vcontext, uint8_t value) |
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249 { |
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250 return vcontext; |
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251 } |
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252 |
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253 static uint16_t cell_image_read16(uint32_t address, void *vcontext) |
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254 { |
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255 uint32_t word_of_cell = address & 2; |
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256 if (address < 0x10000) { |
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257 //64x32 cell view |
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258 uint32_t line_of_column = address & 0x3FC; |
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259 uint32_t column = address & 0xFC00; |
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260 address = (line_of_column << 6) | (column >> 8) | word_of_cell; |
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261 } else if (address < 0x18000) { |
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262 //64x16 cell view |
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263 uint32_t line_of_column = address & 0x1FC; |
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264 uint32_t column = address & 0x7E00; |
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265 address = 0x10000 | (line_of_column << 6) | (column >> 7) | word_of_cell; |
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266 } else if (address < 0x1C000) { |
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267 //64x8 cell view |
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268 uint32_t line_of_column = address & 0x00FC; |
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269 uint32_t column = address & 0x3F00; |
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270 address = 0x18000 | (line_of_column << 6) | (column >> 6) | word_of_cell; |
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271 } else { |
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272 //64x4 cell view |
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273 uint32_t line_of_column = address & 0x007C; |
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274 uint32_t column = address & 0x1F80; |
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275 address &= 0x1E000; |
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276 address |= (line_of_column << 6) | (column >> 5) | word_of_cell; |
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277 } |
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278 m68k_context *m68k = vcontext; |
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279 genesis_context *gen = m68k->system; |
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280 segacd_context *cd = gen->expansion; |
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281 if (!m68k->mem_pointers[cd->memptr_start_index + 1]) { |
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282 return 0xFFFF; |
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283 } |
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284 return m68k->mem_pointers[cd->memptr_start_index + 1][address>>1]; |
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285 } |
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286 |
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287 static uint8_t cell_image_read8(uint32_t address, void *vcontext) |
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288 { |
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289 uint16_t word = cell_image_read16(address & 0xFFFFFE, vcontext); |
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290 if (address & 1) { |
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291 return word; |
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292 } |
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293 return word >> 8; |
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294 } |
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295 |
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296 static void *cell_image_write16(uint32_t address, void *vcontext, uint16_t value) |
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297 { |
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298 return vcontext; |
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299 } |
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300 |
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301 static void *cell_image_write8(uint32_t address, void *vcontext, uint8_t value) |
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302 { |
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303 return vcontext; |
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304 } |
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305 |
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306 static uint8_t pcm_read8(uint32_t address, void *vcontext) |
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307 { |
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308 m68k_context *m68k = vcontext; |
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309 segacd_context *cd = m68k->system; |
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310 if (address & 1) { |
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311 rf5c164_run(&cd->pcm, m68k->current_cycle); |
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312 return rf5c164_read(&cd->pcm, address >> 1); |
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313 } else { |
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314 return 0xFF; |
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315 } |
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316 } |
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317 |
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318 static uint16_t pcm_read16(uint32_t address, void *vcontext) |
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319 { |
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320 return 0xFF00 | pcm_read8(address+1, vcontext); |
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321 } |
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322 |
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323 static void *pcm_write8(uint32_t address, void *vcontext, uint8_t value) |
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324 { |
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325 m68k_context *m68k = vcontext; |
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326 segacd_context *cd = m68k->system; |
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327 if (address & 1) { |
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328 rf5c164_run(&cd->pcm, m68k->current_cycle); |
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329 rf5c164_write(&cd->pcm, address >> 1, value); |
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330 } |
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331 return vcontext; |
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332 } |
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333 |
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Initial skeleton of Sega CD memory handlers
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parents:
1467
diff
changeset
|
334 static void *pcm_write16(uint32_t address, void *vcontext, uint16_t value) |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
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parents:
1467
diff
changeset
|
335 { |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
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parents:
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diff
changeset
|
336 return pcm_write8(address+1, vcontext, value); |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
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parents:
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diff
changeset
|
337 } |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
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parents:
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diff
changeset
|
338 |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
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parents:
1504
diff
changeset
|
339 |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
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parents:
1504
diff
changeset
|
340 static void timers_run(segacd_context *cd, uint32_t cycle) |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
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parents:
1504
diff
changeset
|
341 { |
2057
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
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parents:
2056
diff
changeset
|
342 if (cycle <= cd->stopwatch_cycle) { |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
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parents:
2056
diff
changeset
|
343 return; |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
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parents:
2056
diff
changeset
|
344 } |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
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parents:
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diff
changeset
|
345 uint32_t ticks = (cycle - cd->stopwatch_cycle) / TIMER_TICK_CLKS; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
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parents:
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diff
changeset
|
346 cd->stopwatch_cycle += ticks * TIMER_TICK_CLKS; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
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parents:
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diff
changeset
|
347 cd->gate_array[GA_STOP_WATCH] += ticks; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
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diff
changeset
|
348 cd->gate_array[GA_STOP_WATCH] &= 0xFFF; |
2057
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
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parents:
2056
diff
changeset
|
349 if (ticks && !cd->timer_value) { |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
350 --ticks; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
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parents:
1504
diff
changeset
|
351 cd->timer_value = cd->gate_array[GA_TIMER]; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
352 } |
2057
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
353 if (ticks && cd->timer_value) { |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
354 while (ticks >= (cd->timer_value + 1)) { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
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parents:
1504
diff
changeset
|
355 ticks -= cd->timer_value + 1; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
356 cd->timer_value = cd->gate_array[GA_TIMER]; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
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parents:
1504
diff
changeset
|
357 cd->timer_pending = 1; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
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parents:
1504
diff
changeset
|
358 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
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parents:
1504
diff
changeset
|
359 cd->timer_value -= ticks; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
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parents:
1504
diff
changeset
|
360 if (!cd->timer_value) { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
361 cd->timer_pending = 1; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
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parents:
1504
diff
changeset
|
362 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
363 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
364 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
365 |
2062
07ed42bd7b4c
Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2061
diff
changeset
|
366 static void cdd_run(segacd_context *cd, uint32_t cycle) |
07ed42bd7b4c
Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2061
diff
changeset
|
367 { |
2080 | 368 cdd_mcu_run(&cd->cdd, cycle, cd->gate_array + GA_CDD_CTRL, &cd->cdc, &cd->fader); |
2062
07ed42bd7b4c
Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2061
diff
changeset
|
369 lc8951_run(&cd->cdc, cycle); |
07ed42bd7b4c
Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2061
diff
changeset
|
370 } |
07ed42bd7b4c
Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2061
diff
changeset
|
371 |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
372 static uint32_t next_timer_int(segacd_context *cd) |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
373 { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
374 if (cd->timer_pending) { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
375 return cd->stopwatch_cycle; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
376 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
377 if (cd->timer_value) { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
378 return cd->stopwatch_cycle + TIMER_TICK_CLKS * cd->timer_value; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
379 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
380 if (cd->gate_array[GA_TIMER]) { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
381 return cd->stopwatch_cycle + TIMER_TICK_CLKS * (cd->gate_array[GA_TIMER] + 1); |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
382 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
383 return CYCLE_NEVER; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
384 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
385 |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
386 static void calculate_target_cycle(m68k_context * context) |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
387 { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
388 segacd_context *cd = context->system; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
389 context->int_cycle = CYCLE_NEVER; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
390 uint8_t mask = context->status & 0x7; |
2094
ca6fc8c8dc60
Pass some more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2087
diff
changeset
|
391 uint32_t cdc_cycle = CYCLE_NEVER; |
2116
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
392 if (mask < 6) { |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
393 if (cd->gate_array[GA_INT_MASK] & BIT_MASK_IEN6) { |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
394 uint32_t subcode_cycle = cd->cdd.subcode_int_pending ? context->current_cycle : cd->cdd.next_subcode_int_cycle; |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
395 if (subcode_cycle != CYCLE_NEVER) { |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
396 context->int_cycle = subcode_cycle; |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
397 context->int_num = 6; |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
398 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
399 } |
2116
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
400 if (mask < 5) { |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
401 if (cd->gate_array[GA_INT_MASK] & BIT_MASK_IEN5) { |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
402 cdc_cycle = lc8951_next_interrupt(&cd->cdc); |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
403 //CDC interrupts only generated on falling edge of !INT signal |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
404 if (cd->cdc_int_ack) { |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
405 if (cdc_cycle > cd->cdc.cycle) { |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
406 cd->cdc_int_ack = 0; |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
407 } else { |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
408 cdc_cycle = CYCLE_NEVER; |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
409 } |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
410 } |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
411 if (cdc_cycle < context->int_cycle) { |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
412 context->int_cycle = cdc_cycle; |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
413 context->int_num = 5; |
2061
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
414 } |
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
415 } |
2116
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
416 if (mask < 4) { |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
417 if (cd->gate_array[GA_INT_MASK] & BIT_MASK_IEN4) { |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
418 uint32_t cdd_cycle = cd->cdd.int_pending ? context->current_cycle : cd->cdd.next_int_cycle; |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
419 if (cdd_cycle < context->int_cycle) { |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
420 context->int_cycle = cdd_cycle; |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
421 context->int_num = 4; |
2062
07ed42bd7b4c
Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2061
diff
changeset
|
422 } |
07ed42bd7b4c
Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2061
diff
changeset
|
423 } |
2116
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
424 if (mask < 3) { |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
425 uint32_t next_timer; |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
426 if (cd->gate_array[GA_INT_MASK] & BIT_MASK_IEN3) { |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
427 uint32_t next_timer_cycle = next_timer_int(cd); |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
428 if (next_timer_cycle < context->int_cycle) { |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
429 context->int_cycle = next_timer_cycle; |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
430 context->int_num = 3; |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
431 } |
2062
07ed42bd7b4c
Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2061
diff
changeset
|
432 } |
2116
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
433 if (mask < 2) { |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
434 if (cd->int2_cycle < context->int_cycle && (cd->gate_array[GA_INT_MASK] & BIT_MASK_IEN2)) { |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
435 context->int_cycle = cd->int2_cycle; |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
436 context->int_num = 2; |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
437 } |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
438 if (mask < 1) { |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
439 if (cd->graphics_int_cycle < context->int_cycle && (cd->gate_array[GA_INT_MASK] & BIT_MASK_IEN1)) { |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
440 context->int_cycle = cd->graphics_int_cycle; |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
441 context->int_num = 1; |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
442 } |
2069
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
443 } |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
444 } |
2061
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
445 } |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
446 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
447 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
448 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
449 if (context->int_cycle > context->current_cycle && context->int_pending == INT_PENDING_SR_CHANGE) { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
450 context->int_pending = INT_PENDING_NONE; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
451 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
452 if (context->current_cycle >= context->sync_cycle) { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
453 context->should_return = 1; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
454 context->target_cycle = context->current_cycle; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
455 return; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
456 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
457 if (context->status & M68K_STATUS_TRACE || context->trace_pending) { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
458 context->target_cycle = context->current_cycle; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
459 return; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
460 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
461 context->target_cycle = context->sync_cycle < context->int_cycle ? context->sync_cycle : context->int_cycle; |
2094
ca6fc8c8dc60
Pass some more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2087
diff
changeset
|
462 if (context->target_cycle == cdc_cycle && context->int_num == 5) { |
ca6fc8c8dc60
Pass some more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2087
diff
changeset
|
463 uint32_t before = context->target_cycle - 2 * cd->cdc.clock_step; |
ca6fc8c8dc60
Pass some more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2087
diff
changeset
|
464 if (before > context->current_cycle) { |
ca6fc8c8dc60
Pass some more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2087
diff
changeset
|
465 context->target_cycle = context->sync_cycle = before; |
ca6fc8c8dc60
Pass some more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2087
diff
changeset
|
466 } |
ca6fc8c8dc60
Pass some more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2087
diff
changeset
|
467 } |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
468 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
469 |
1502
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
470 static uint16_t sub_gate_read16(uint32_t address, void *vcontext) |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
471 { |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
472 m68k_context *m68k = vcontext; |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
473 segacd_context *cd = m68k->system; |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
474 uint32_t reg = address >> 1; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
475 switch (reg) |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
476 { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
477 case GA_SUB_CPU_CTRL: { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
478 uint16_t value = cd->gate_array[reg] & 0xFFFE; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
479 if (cd->periph_reset_cycle == CYCLE_NEVER || (m68k->current_cycle - cd->periph_reset_cycle) > SCD_PERIPH_RESET_CLKS) { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
480 value |= BIT_PRES; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
481 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
482 return value; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
483 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
484 case GA_MEM_MODE: |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
485 return cd->gate_array[reg] & 0xFF1F; |
2058
70260f6051dd
Initial work on CDC emulation
Michael Pavone <pavone@retrodev.com>
parents:
2057
diff
changeset
|
486 case GA_CDC_CTRL: |
2065
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
487 cdd_run(cd, m68k->current_cycle); |
2058
70260f6051dd
Initial work on CDC emulation
Michael Pavone <pavone@retrodev.com>
parents:
2057
diff
changeset
|
488 return cd->gate_array[reg] | cd->cdc.ar; |
70260f6051dd
Initial work on CDC emulation
Michael Pavone <pavone@retrodev.com>
parents:
2057
diff
changeset
|
489 case GA_CDC_REG_DATA: |
2062
07ed42bd7b4c
Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2061
diff
changeset
|
490 cdd_run(cd, m68k->current_cycle); |
2058
70260f6051dd
Initial work on CDC emulation
Michael Pavone <pavone@retrodev.com>
parents:
2057
diff
changeset
|
491 return lc8951_reg_read(&cd->cdc); |
2065
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
492 case GA_CDC_HOST_DATA: { |
2066
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
493 cdd_run(cd, m68k->current_cycle); |
2065
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
494 uint16_t dst = cd->gate_array[GA_CDC_CTRL] >> 8 & 0x7; |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
495 if (dst == DST_SUB_CPU) { |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
496 if (cd->gate_array[GA_CDC_CTRL] & BIT_DSR) { |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
497 cd->gate_array[GA_CDC_CTRL] &= ~BIT_DSR; |
2066
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
498 lc8951_resume_transfer(&cd->cdc, cd->cdc.cycle); |
2065
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
499 } |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
500 calculate_target_cycle(cd->m68k); |
2068
f573f2c31bc9
Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents:
2066
diff
changeset
|
501 |
2065
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
502 } |
2066
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
503 return cd->gate_array[reg]; |
2065
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
504 } |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
505 case GA_STOP_WATCH: |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
506 case GA_TIMER: |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
507 timers_run(cd, m68k->current_cycle); |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
508 return cd->gate_array[reg]; |
2061
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
509 case GA_CDD_STATUS0: |
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
510 case GA_CDD_STATUS1: |
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
511 case GA_CDD_STATUS2: |
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
512 case GA_CDD_STATUS3: |
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
513 case GA_CDD_STATUS4: |
2062
07ed42bd7b4c
Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2061
diff
changeset
|
514 cdd_run(cd, m68k->current_cycle); |
2061
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
515 return cd->gate_array[reg]; |
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
516 break; |
2057
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
517 case GA_FONT_DATA0: |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
518 case GA_FONT_DATA1: |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
519 case GA_FONT_DATA2: |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
520 case GA_FONT_DATA3: { |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
521 uint16_t shift = 4 * (3 - (reg - GA_FONT_DATA0)); |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
522 uint16_t value = 0; |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
523 uint16_t fg = cd->gate_array[GA_FONT_COLOR] >> 4; |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
524 uint16_t bg = cd->gate_array[GA_FONT_COLOR] & 0xF; |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
525 for (int i = 0; i < 4; i++) { |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
526 uint16_t pixel = 0; |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
527 if (cd->gate_array[GA_FONT_BITS] & 1 << (shift + i)) { |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
528 pixel = fg; |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
529 } else { |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
530 pixel = bg; |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
531 } |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
532 value |= pixel << (i * 4); |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
533 } |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
534 return value; |
2116
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
535 } |
2069
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
536 case GA_STAMP_SIZE: |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
537 case GA_IMAGE_BUFFER_LINES: |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
538 //these two have bits that change based on graphics operations |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
539 cd_graphics_run(cd, m68k->current_cycle); |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
540 return cd->gate_array[reg]; |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
541 case GA_TRACE_VECTOR_BASE: |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
542 //write only |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
543 return 0xFFFF; |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
544 default: |
2116
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
545 if (reg >= GA_SUBCODE_MIRROR) { |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
546 return cd->gate_array[GA_SUBCODE_START + (reg & 0x3F)]; |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
547 } |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
548 return cd->gate_array[reg]; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
549 } |
1502
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
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550 } |
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|
551 |
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Initial skeleton of Sega CD memory handlers
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552 static uint8_t sub_gate_read8(uint32_t address, void *vcontext) |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
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diff
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|
553 { |
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8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
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diff
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|
554 uint16_t val = sub_gate_read16(address, vcontext); |
1502
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
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|
555 return address & 1 ? val : val >> 8; |
2564b6ba2e12
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diff
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|
556 } |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
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|
557 |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
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parents:
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558 static void *sub_gate_write16(uint32_t address, void *vcontext, uint16_t value) |
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559 { |
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Initial skeleton of Sega CD memory handlers
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parents:
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560 m68k_context *m68k = vcontext; |
2564b6ba2e12
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561 segacd_context *cd = m68k->system; |
2054
8ee7ecbf3f21
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562 uint32_t reg = address >> 1; |
1502
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
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|
563 switch (reg) |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
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|
564 { |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
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parents:
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diff
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|
565 case GA_SUB_CPU_CTRL: |
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parents:
1504
diff
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|
566 cd->gate_array[reg] &= 0xF0; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
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parents:
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diff
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567 cd->gate_array[reg] |= value & (BIT_LEDG|BIT_LEDR); |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
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diff
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|
568 if (value & BIT_PRES) { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
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diff
changeset
|
569 cd->periph_reset_cycle = m68k->current_cycle; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
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diff
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|
570 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
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parents:
1504
diff
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571 break; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
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diff
changeset
|
572 case GA_MEM_MODE: { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
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diff
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|
573 uint16_t changed = value ^ cd->gate_array[reg]; |
2119
5ec2f97365a2
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parents:
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diff
changeset
|
574 uint8_t old_main_has_word2m = cd->main_has_word2m; |
5ec2f97365a2
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diff
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575 if (value & BIT_RET) { |
5ec2f97365a2
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2116
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changeset
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576 cd->main_has_word2m = 1; |
5ec2f97365a2
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diff
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577 } |
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parents:
2116
diff
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578 uint8_t old_bank_toggle = cd->bank_toggle; |
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diff
changeset
|
579 cd->bank_toggle = value & BIT_RET; |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
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parents:
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diff
changeset
|
580 genesis_context *gen = cd->genesis; |
2119
5ec2f97365a2
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parents:
2116
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|
581 cd->gate_array[reg] &= 0xFFC0; |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
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diff
changeset
|
582 if (changed & BIT_MEM_MODE) { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
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parents:
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diff
changeset
|
583 //FIXME: ram banks are supposed to be interleaved when in 2M mode |
2119
5ec2f97365a2
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parents:
2116
diff
changeset
|
584 cd->main_swap_request = old_bank_toggle != cd->bank_toggle; |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
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diff
changeset
|
585 if (value & BIT_MEM_MODE) { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
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diff
changeset
|
586 //switch to 1M mode |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
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parents:
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diff
changeset
|
587 gen->m68k->mem_pointers[cd->memptr_start_index + 1] = (value & BIT_RET) ? cd->word_ram + 0x10000 : cd->word_ram; |
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Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
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parents:
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diff
changeset
|
588 gen->m68k->mem_pointers[cd->memptr_start_index + 2] = NULL; |
8ee7ecbf3f21
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Michael Pavone <pavone@retrodev.com>
parents:
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diff
changeset
|
589 m68k->mem_pointers[0] = NULL; |
2119
5ec2f97365a2
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Michael Pavone <pavone@retrodev.com>
parents:
2116
diff
changeset
|
590 m68k->mem_pointers[1] = cd->bank_toggle ? cd->word_ram : cd->word_ram + 0x10000; |
5ec2f97365a2
More accurate RET/DMNA implementation
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parents:
2116
diff
changeset
|
591 cd->gate_array[reg] |= value & (MASK_PRIORITY|BIT_RET|BIT_MEM_MODE); |
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parents:
2116
diff
changeset
|
592 if (cd->main_swap_request) { |
5ec2f97365a2
More accurate RET/DMNA implementation
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parents:
2116
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changeset
|
593 cd->gate_array[reg] |= BIT_DMNA; |
5ec2f97365a2
More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
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diff
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|
594 } |
2054
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Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
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diff
changeset
|
595 } else { |
8ee7ecbf3f21
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Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
596 //switch to 2M mode |
2119
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Michael Pavone <pavone@retrodev.com>
parents:
2116
diff
changeset
|
597 if (cd->main_has_word2m) { |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
598 //Main CPU will have word ram |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
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diff
changeset
|
599 gen->m68k->mem_pointers[cd->memptr_start_index + 1] = cd->word_ram; |
8ee7ecbf3f21
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Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
600 gen->m68k->mem_pointers[cd->memptr_start_index + 2] = cd->word_ram + 0x10000; |
8ee7ecbf3f21
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Michael Pavone <pavone@retrodev.com>
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diff
changeset
|
601 m68k->mem_pointers[0] = NULL; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
602 m68k->mem_pointers[1] = NULL; |
8ee7ecbf3f21
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Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
603 } else { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
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diff
changeset
|
604 //sub cpu will have word ram |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
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parents:
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diff
changeset
|
605 gen->m68k->mem_pointers[cd->memptr_start_index + 1] = NULL; |
8ee7ecbf3f21
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diff
changeset
|
606 gen->m68k->mem_pointers[cd->memptr_start_index + 2] = NULL; |
8ee7ecbf3f21
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diff
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|
607 m68k->mem_pointers[0] = cd->word_ram; |
8ee7ecbf3f21
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diff
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|
608 m68k->mem_pointers[1] = NULL; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
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parents:
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diff
changeset
|
609 } |
2119
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More accurate RET/DMNA implementation
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diff
changeset
|
610 cd->gate_array[reg] |= value & (MASK_PRIORITY|BIT_MEM_MODE); |
5ec2f97365a2
More accurate RET/DMNA implementation
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diff
changeset
|
611 cd->gate_array[reg] |= cd->main_has_word2m ? BIT_RET : BIT_DMNA; |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
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parents:
1504
diff
changeset
|
612 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
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diff
changeset
|
613 m68k_invalidate_code_range(gen->m68k, cd->base + 0x200000, cd->base + 0x240000); |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
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diff
changeset
|
614 m68k_invalidate_code_range(m68k, 0x080000, 0x0E0000); |
2119
5ec2f97365a2
More accurate RET/DMNA implementation
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2116
diff
changeset
|
615 } else if (value & BIT_MEM_MODE) { |
5ec2f97365a2
More accurate RET/DMNA implementation
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parents:
2116
diff
changeset
|
616 //1M mode |
5ec2f97365a2
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diff
changeset
|
617 if (old_bank_toggle != cd->bank_toggle) { |
2054
8ee7ecbf3f21
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diff
changeset
|
618 gen->m68k->mem_pointers[cd->memptr_start_index + 1] = (value & BIT_RET) ? cd->word_ram + 0x10000 : cd->word_ram; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
619 m68k->mem_pointers[1] = (value & BIT_RET) ? cd->word_ram : cd->word_ram + 0x10000; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
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parents:
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diff
changeset
|
620 m68k_invalidate_code_range(gen->m68k, cd->base + 0x200000, cd->base + 0x240000); |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
621 m68k_invalidate_code_range(m68k, 0x080000, 0x0E0000); |
2119
5ec2f97365a2
More accurate RET/DMNA implementation
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diff
changeset
|
622 cd->main_swap_request = 0; |
5ec2f97365a2
More accurate RET/DMNA implementation
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diff
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|
623 } |
5ec2f97365a2
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2116
diff
changeset
|
624 cd->gate_array[reg] |= value & (MASK_PRIORITY|BIT_RET|BIT_MEM_MODE); |
5ec2f97365a2
More accurate RET/DMNA implementation
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2116
diff
changeset
|
625 if (cd->main_swap_request) { |
5ec2f97365a2
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diff
changeset
|
626 cd->gate_array[reg] |= BIT_DMNA; |
5ec2f97365a2
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diff
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|
627 } |
5ec2f97365a2
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diff
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|
628 } else { |
5ec2f97365a2
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2116
diff
changeset
|
629 //2M mode |
5ec2f97365a2
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2116
diff
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|
630 if (old_main_has_word2m != cd->main_has_word2m) { |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
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parents:
1504
diff
changeset
|
631 gen->m68k->mem_pointers[cd->memptr_start_index + 1] = cd->word_ram; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
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1504
diff
changeset
|
632 gen->m68k->mem_pointers[cd->memptr_start_index + 2] = cd->word_ram + 0x10000; |
8ee7ecbf3f21
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Michael Pavone <pavone@retrodev.com>
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1504
diff
changeset
|
633 m68k->mem_pointers[0] = NULL; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
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parents:
1504
diff
changeset
|
634 m68k_invalidate_code_range(gen->m68k, cd->base + 0x200000, cd->base + 0x240000); |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
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diff
changeset
|
635 m68k_invalidate_code_range(m68k, 0x080000, 0x0E0000); |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
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1504
diff
changeset
|
636 } |
2119
5ec2f97365a2
More accurate RET/DMNA implementation
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2116
diff
changeset
|
637 cd->gate_array[reg] |= value & MASK_PRIORITY; |
5ec2f97365a2
More accurate RET/DMNA implementation
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2116
diff
changeset
|
638 cd->gate_array[reg] |= cd->main_has_word2m ? BIT_RET : BIT_DMNA; |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
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1504
diff
changeset
|
639 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
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diff
changeset
|
640 break; |
8ee7ecbf3f21
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diff
changeset
|
641 } |
2058
70260f6051dd
Initial work on CDC emulation
Michael Pavone <pavone@retrodev.com>
parents:
2057
diff
changeset
|
642 case GA_CDC_CTRL: |
2062
07ed42bd7b4c
Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2061
diff
changeset
|
643 cdd_run(cd, m68k->current_cycle); |
2058
70260f6051dd
Initial work on CDC emulation
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parents:
2057
diff
changeset
|
644 lc8951_ar_write(&cd->cdc, value); |
2066
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
645 //cd->gate_array[reg] &= 0xC000; |
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
646 //apparently this clears EDT, should it also clear DSR? |
2058
70260f6051dd
Initial work on CDC emulation
Michael Pavone <pavone@retrodev.com>
parents:
2057
diff
changeset
|
647 cd->gate_array[reg] = value & 0x0700; |
2066
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
648 cd->cdc_dst_low = 0; |
2058
70260f6051dd
Initial work on CDC emulation
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parents:
2057
diff
changeset
|
649 break; |
70260f6051dd
Initial work on CDC emulation
Michael Pavone <pavone@retrodev.com>
parents:
2057
diff
changeset
|
650 case GA_CDC_REG_DATA: |
2062
07ed42bd7b4c
Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2061
diff
changeset
|
651 cdd_run(cd, m68k->current_cycle); |
2066
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
652 printf("CDC write %X: %X @ %u\n", cd->cdc.ar, value, m68k->current_cycle); |
2058
70260f6051dd
Initial work on CDC emulation
Michael Pavone <pavone@retrodev.com>
parents:
2057
diff
changeset
|
653 lc8951_reg_write(&cd->cdc, value); |
2062
07ed42bd7b4c
Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2061
diff
changeset
|
654 calculate_target_cycle(m68k); |
2058
70260f6051dd
Initial work on CDC emulation
Michael Pavone <pavone@retrodev.com>
parents:
2057
diff
changeset
|
655 break; |
2065
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
656 case GA_CDC_DMA_ADDR: |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
657 cdd_run(cd, m68k->current_cycle); |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
658 cd->gate_array[reg] = value; |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
659 cd->cdc_dst_low = 0; |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
660 break; |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
661 case GA_STOP_WATCH: |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
662 //docs say you should only write zero to reset |
2057
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
663 //mcd-verificator comments suggest any value will reset |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
664 timers_run(cd, m68k->current_cycle); |
2057
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
665 cd->gate_array[reg] = 0; |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
666 break; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
667 case GA_COMM_FLAG: |
1502
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
668 cd->gate_array[reg] &= 0xFF00; |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
669 cd->gate_array[reg] |= value & 0xFF; |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
670 break; |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
671 case GA_COMM_STATUS0: |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
672 case GA_COMM_STATUS1: |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
673 case GA_COMM_STATUS2: |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
674 case GA_COMM_STATUS3: |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
675 case GA_COMM_STATUS4: |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
676 case GA_COMM_STATUS5: |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
677 case GA_COMM_STATUS6: |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
678 case GA_COMM_STATUS7: |
1502
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
679 //no effects for these other than saving the value |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
680 cd->gate_array[reg] = value; |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
681 break; |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
682 case GA_TIMER: |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
683 timers_run(cd, m68k->current_cycle); |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
684 cd->gate_array[reg] = value & 0xFF; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
685 calculate_target_cycle(m68k); |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
686 break; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
687 case GA_INT_MASK: |
2116
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
688 if (!(cd->gate_array[reg] & BIT_MASK_IEN6)) { |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
689 //subcode interrupts can't be made pending when they are disabled in this reg |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
690 cd->cdd.subcode_int_pending = 0; |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
691 } |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
692 cd->gate_array[reg] = value & (BIT_MASK_IEN6|BIT_MASK_IEN5|BIT_MASK_IEN4|BIT_MASK_IEN3|BIT_MASK_IEN2|BIT_MASK_IEN1); |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
693 calculate_target_cycle(m68k); |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
694 break; |
2080 | 695 case GA_CDD_FADER: |
696 cdd_run(cd, m68k->current_cycle); | |
697 value &= 0x7FFF; | |
698 cdd_fader_attenuation_write(&cd->fader, value); | |
699 cd->gate_array[reg] &= 0x8000; | |
700 cd->gate_array[reg] |= value; | |
701 break; | |
2061
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
702 case GA_CDD_CTRL: { |
2062
07ed42bd7b4c
Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2061
diff
changeset
|
703 cdd_run(cd, m68k->current_cycle); |
2061
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
704 uint16_t changed = cd->gate_array[reg] ^ value; |
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
705 if (changed & BIT_HOCK) { |
2073
c69e42444f96
Fix some cycle adjustment stuff and an off-by one on hte TOCT response
Michael Pavone <pavone@retrodev.com>
parents:
2069
diff
changeset
|
706 cd->gate_array[reg] &= ~BIT_HOCK; |
c69e42444f96
Fix some cycle adjustment stuff and an off-by one on hte TOCT response
Michael Pavone <pavone@retrodev.com>
parents:
2069
diff
changeset
|
707 cd->gate_array[reg] |= value & BIT_HOCK; |
2061
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
708 if (value & BIT_HOCK) { |
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
709 cdd_hock_enabled(&cd->cdd); |
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
710 } else { |
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
711 cdd_hock_disabled(&cd->cdd); |
2080 | 712 cd->gate_array[reg] |= BIT_MUTE; |
2061
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
713 } |
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
714 calculate_target_cycle(m68k); |
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
715 } |
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
716 break; |
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
717 } |
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
718 case GA_CDD_CMD0: |
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
719 case GA_CDD_CMD1: |
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
720 case GA_CDD_CMD2: |
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
721 case GA_CDD_CMD3: |
2062
07ed42bd7b4c
Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2061
diff
changeset
|
722 cdd_run(cd, m68k->current_cycle); |
2061
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
723 cd->gate_array[reg] = value & 0x0F0F; |
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
724 break; |
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
725 case GA_CDD_CMD4: |
2062
07ed42bd7b4c
Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2061
diff
changeset
|
726 cdd_run(cd, m68k->current_cycle); |
2061
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
727 cd->gate_array[reg] = value & 0x0F0F; |
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
728 cdd_mcu_start_cmd_recv(&cd->cdd, cd->gate_array + GA_CDD_CTRL); |
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
729 break; |
2057
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
730 case GA_FONT_COLOR: |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
731 cd->gate_array[reg] = value & 0xFF; |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
732 break; |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
733 case GA_FONT_BITS: |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
734 cd->gate_array[reg] = value; |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
735 break; |
2069
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
736 case GA_STAMP_SIZE: |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
737 cd_graphics_run(cd, m68k->current_cycle); |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
738 cd->gate_array[reg] &= BIT_GRON; |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
739 cd->gate_array[reg] |= value & (BIT_SMS|BIT_STS|BIT_RPT); |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
740 break; |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
741 case GA_STAMP_MAP_BASE: |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
742 cd_graphics_run(cd, m68k->current_cycle); |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
743 cd->gate_array[reg] = value & 0xFFE0; |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
744 break; |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
745 case GA_IMAGE_BUFFER_VCELLS: |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
746 cd_graphics_run(cd, m68k->current_cycle); |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
747 cd->gate_array[reg] = value & 0x1F; |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
748 break; |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
749 case GA_IMAGE_BUFFER_START: |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
750 cd_graphics_run(cd, m68k->current_cycle); |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
751 cd->gate_array[reg] = value & 0xFFF8; |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
752 break; |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
753 case GA_IMAGE_BUFFER_OFFSET: |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
754 cd_graphics_run(cd, m68k->current_cycle); |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
755 cd->gate_array[reg] = value & 0x3F; |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
756 break; |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
757 case GA_IMAGE_BUFFER_HDOTS: |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
758 cd_graphics_run(cd, m68k->current_cycle); |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
759 cd->gate_array[reg] = value & 0x1FF; |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
760 break; |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
761 case GA_IMAGE_BUFFER_LINES: |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
762 cd_graphics_run(cd, m68k->current_cycle); |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
763 cd->gate_array[reg] = value & 0xFF; |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
764 break; |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
765 case GA_TRACE_VECTOR_BASE: |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
766 cd_graphics_run(cd, m68k->current_cycle); |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
767 cd->gate_array[reg] = value & 0xFFFE; |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
768 cd_graphics_start(cd); |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
769 break; |
1502
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
770 default: |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
771 printf("Unhandled gate array write %X:%X\n", address, value); |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
772 } |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
773 return vcontext; |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
774 } |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
775 |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
776 static void *sub_gate_write8(uint32_t address, void *vcontext, uint8_t value) |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
777 { |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
778 m68k_context *m68k = vcontext; |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
779 segacd_context *cd = m68k->system; |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
780 uint32_t reg = (address & 0x1FF) >> 1; |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
781 uint16_t value16; |
2056
27bbfcb7850a
Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2055
diff
changeset
|
782 switch (address >> 1) |
27bbfcb7850a
Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2055
diff
changeset
|
783 { |
2119
5ec2f97365a2
More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents:
2116
diff
changeset
|
784 case GA_MEM_MODE: |
2056
27bbfcb7850a
Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2055
diff
changeset
|
785 case GA_CDC_HOST_DATA: |
27bbfcb7850a
Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2055
diff
changeset
|
786 case GA_CDC_DMA_ADDR: |
27bbfcb7850a
Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2055
diff
changeset
|
787 case GA_STOP_WATCH: |
27bbfcb7850a
Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2055
diff
changeset
|
788 case GA_COMM_FLAG: |
2057
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
789 case GA_TIMER: |
2056
27bbfcb7850a
Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2055
diff
changeset
|
790 case GA_CDD_FADER: |
2057
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
791 case GA_FONT_COLOR: |
2056
27bbfcb7850a
Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2055
diff
changeset
|
792 //these registers treat all writes as word-wide |
27bbfcb7850a
Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2055
diff
changeset
|
793 value16 = value | (value << 8); |
27bbfcb7850a
Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2055
diff
changeset
|
794 break; |
2058
70260f6051dd
Initial work on CDC emulation
Michael Pavone <pavone@retrodev.com>
parents:
2057
diff
changeset
|
795 case GA_CDC_CTRL: |
70260f6051dd
Initial work on CDC emulation
Michael Pavone <pavone@retrodev.com>
parents:
2057
diff
changeset
|
796 if (address & 1) { |
70260f6051dd
Initial work on CDC emulation
Michael Pavone <pavone@retrodev.com>
parents:
2057
diff
changeset
|
797 lc8951_ar_write(&cd->cdc, value); |
2066
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
798 return vcontext; |
2058
70260f6051dd
Initial work on CDC emulation
Michael Pavone <pavone@retrodev.com>
parents:
2057
diff
changeset
|
799 } else { |
2066
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
800 value16 = cd->cdc.ar | (value << 8); |
2058
70260f6051dd
Initial work on CDC emulation
Michael Pavone <pavone@retrodev.com>
parents:
2057
diff
changeset
|
801 } |
2066
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
802 break; |
2061
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
803 case GA_CDD_CMD4: |
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
804 if (!address) { |
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
805 //byte write to $FF804A should not trigger transfer |
2062
07ed42bd7b4c
Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2061
diff
changeset
|
806 cdd_run(cd, m68k->current_cycle); |
2061
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
807 cd->gate_array[reg] &= 0x0F; |
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
808 cd->gate_array[reg] |= (value << 8 & 0x0F00); |
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
809 return vcontext; |
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
810 } |
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
811 //intentional fallthrough for $FF804B |
2056
27bbfcb7850a
Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2055
diff
changeset
|
812 default: |
27bbfcb7850a
Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2055
diff
changeset
|
813 if (address & 1) { |
27bbfcb7850a
Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2055
diff
changeset
|
814 value16 = cd->gate_array[reg] & 0xFF00 | value; |
27bbfcb7850a
Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2055
diff
changeset
|
815 } else { |
27bbfcb7850a
Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2055
diff
changeset
|
816 value16 = cd->gate_array[reg] & 0xFF | (value << 8); |
27bbfcb7850a
Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2055
diff
changeset
|
817 } |
1502
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
818 } |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
819 return sub_gate_write16(address, vcontext, value16); |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
820 } |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
821 |
2065
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
822 static uint8_t handle_cdc_byte(void *vsys, uint8_t value) |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
823 { |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
824 segacd_context *cd = vsys; |
2066
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
825 if (cd->gate_array[GA_CDC_CTRL] & BIT_DSR) { |
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
826 //host reg is already full, pause transfer |
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
827 return 0; |
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
828 } |
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
829 if (cd->cdc.cycle == cd->cdc.transfer_end) { |
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
830 cd->gate_array[GA_CDC_CTRL] |= BIT_EDT; |
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
831 printf("EDT set at %u\n", cd->cdc.cycle); |
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
832 } |
2065
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
833 uint16_t dest = cd->gate_array[GA_CDC_CTRL] >> 8 & 0x7; |
2066
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
834 if (!(cd->cdc_dst_low & 1)) { |
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
835 cd->gate_array[GA_CDC_HOST_DATA] &= 0xFF; |
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
836 cd->gate_array[GA_CDC_HOST_DATA] |= value << 8; |
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
837 cd->cdc_dst_low++; |
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
838 if (dest != DST_PCM_RAM) { |
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
839 //PCM RAM writes a byte at a time |
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
840 return 1; |
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
841 } |
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
842 } else { |
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
843 cd->gate_array[GA_CDC_HOST_DATA] &= 0xFF00; |
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
844 cd->gate_array[GA_CDC_HOST_DATA] |= value; |
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
845 } |
2068
f573f2c31bc9
Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents:
2066
diff
changeset
|
846 |
2065
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
847 uint32_t dma_addr = cd->gate_array[GA_CDC_DMA_ADDR] << 3; |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
848 dma_addr |= cd->cdc_dst_low; |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
849 switch (dest) |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
850 { |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
851 case DST_MAIN_CPU: |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
852 case DST_SUB_CPU: |
2066
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
853 cd->cdc_dst_low = 0; |
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
854 cd->gate_array[GA_CDC_CTRL] |= BIT_DSR; |
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
855 printf("DSR set at %u, (transfer_end %u, dbcl %X, dbch %X)\n", cd->cdc.cycle, cd->cdc.transfer_end, cd->cdc.regs[2], cd->cdc.regs[3]); |
2065
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
856 break; |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
857 case DST_PCM_RAM: |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
858 dma_addr &= (1 << 13) - 1; |
2094
ca6fc8c8dc60
Pass some more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2087
diff
changeset
|
859 rf5c164_run(&cd->pcm, cd->cdc.cycle); |
2081
cfd53c94fffb
Initial stab at RF5C164 emulation
Michael Pavone <pavone@retrodev.com>
parents:
2080
diff
changeset
|
860 rf5c164_write(&cd->pcm, 0x1000 | (dma_addr >> 1), value); |
2066
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
861 dma_addr += 2; |
2065
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
862 cd->cdc_dst_low = dma_addr & 7; |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
863 cd->gate_array[GA_CDC_DMA_ADDR] = dma_addr >> 3; |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
864 break; |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
865 case DST_PROG_RAM: |
2066
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
866 cd->prog_ram[dma_addr >> 1] = cd->gate_array[GA_CDC_HOST_DATA]; |
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
867 m68k_invalidate_code_range(cd->m68k, dma_addr - 1, dma_addr + 1); |
2065
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
868 dma_addr++; |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
869 cd->cdc_dst_low = dma_addr & 7; |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
870 cd->gate_array[GA_CDC_DMA_ADDR] = dma_addr >> 3; |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
871 break; |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
872 case DST_WORD_RAM: |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
873 if (cd->gate_array[GA_MEM_MODE] & BIT_MEM_MODE) { |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
874 //1M mode, write to bank assigned to Sub CPU |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
875 dma_addr &= (1 << 17) - 1; |
2066
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
876 cd->m68k->mem_pointers[1][dma_addr >> 1] = cd->gate_array[GA_CDC_HOST_DATA]; |
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
877 m68k_invalidate_code_range(cd->m68k, 0x0C0000 + dma_addr - 1, 0x0C0000 + dma_addr + 1); |
2065
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
878 } else { |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
879 //2M mode, check if Sub CPU has access |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
880 if (!(cd->gate_array[GA_MEM_MODE] & BIT_RET)) { |
2094
ca6fc8c8dc60
Pass some more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2087
diff
changeset
|
881 cd_graphics_run(cd, cd->cdc.cycle); |
2065
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
882 dma_addr &= (1 << 18) - 1; |
2066
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
883 cd->word_ram[dma_addr >> 1] = cd->gate_array[GA_CDC_HOST_DATA]; |
2065
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
884 m68k_invalidate_code_range(cd->m68k, 0x080000 + dma_addr, 0x080000 + dma_addr + 1); |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
885 } |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
886 } |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
887 dma_addr++; |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
888 cd->cdc_dst_low = dma_addr & 7; |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
889 cd->gate_array[GA_CDC_DMA_ADDR] = dma_addr >> 3; |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
890 break; |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
891 default: |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
892 printf("Invalid CDC transfer destination %d\n", dest); |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
893 } |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
894 return 1; |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
895 } |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
896 |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
897 static uint8_t can_main_access_prog(segacd_context *cd) |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
898 { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
899 //TODO: use actual busack |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
900 return cd->busreq || !cd->reset; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
901 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
902 |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
903 static void scd_peripherals_run(segacd_context *cd, uint32_t cycle) |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
904 { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
905 timers_run(cd, cycle); |
2062
07ed42bd7b4c
Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2061
diff
changeset
|
906 cdd_run(cd, cycle); |
2069
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
907 cd_graphics_run(cd, cycle); |
2081
cfd53c94fffb
Initial stab at RF5C164 emulation
Michael Pavone <pavone@retrodev.com>
parents:
2080
diff
changeset
|
908 rf5c164_run(&cd->pcm, cycle); |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
909 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
910 |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
911 static m68k_context *sync_components(m68k_context * context, uint32_t address) |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
912 { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
913 segacd_context *cd = context->system; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
914 scd_peripherals_run(cd, context->current_cycle); |
2104
ff32a90260c9
Initial support for using debugger on sub CPU
Michael Pavone <pavone@retrodev.com>
parents:
2099
diff
changeset
|
915 if (address && cd->enter_debugger) { |
ff32a90260c9
Initial support for using debugger on sub CPU
Michael Pavone <pavone@retrodev.com>
parents:
2099
diff
changeset
|
916 genesis_context *gen = cd->genesis; |
2106
d2989e32c026
Fix bug in Sub CPU debugger suport
Michael Pavone <pavone@retrodev.com>
parents:
2104
diff
changeset
|
917 cd->enter_debugger = 0; |
2104
ff32a90260c9
Initial support for using debugger on sub CPU
Michael Pavone <pavone@retrodev.com>
parents:
2099
diff
changeset
|
918 if (gen->header.debugger_type == DEBUGGER_NATIVE) { |
ff32a90260c9
Initial support for using debugger on sub CPU
Michael Pavone <pavone@retrodev.com>
parents:
2099
diff
changeset
|
919 debugger(context, address); |
ff32a90260c9
Initial support for using debugger on sub CPU
Michael Pavone <pavone@retrodev.com>
parents:
2099
diff
changeset
|
920 } else { |
ff32a90260c9
Initial support for using debugger on sub CPU
Michael Pavone <pavone@retrodev.com>
parents:
2099
diff
changeset
|
921 gdb_debug_enter(context, address); |
ff32a90260c9
Initial support for using debugger on sub CPU
Michael Pavone <pavone@retrodev.com>
parents:
2099
diff
changeset
|
922 } |
2080 | 923 } |
2057
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
924 switch (context->int_ack) |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
925 { |
2069
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
926 case 1: |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
927 cd->graphics_int_cycle = CYCLE_NEVER; |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
928 break; |
2057
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
929 case 2: |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
930 cd->int2_cycle = CYCLE_NEVER; |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
931 break; |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
932 case 3: |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
933 cd->timer_pending = 0; |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
934 break; |
2061
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
935 case 4: |
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
936 cd->cdd.int_pending = 0; |
2066
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
937 break; |
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
938 case 5: |
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
939 cd->cdc_int_ack = 1; |
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
940 break; |
2116
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
941 case 6: |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
942 cd->cdd.subcode_int_pending = 0; |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
943 break; |
2057
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
944 } |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
945 context->int_ack = 0; |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
946 calculate_target_cycle(context); |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
947 return context; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
948 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
949 |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
950 void scd_run(segacd_context *cd, uint32_t cycle) |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
951 { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
952 uint8_t m68k_run = !can_main_access_prog(cd); |
2094
ca6fc8c8dc60
Pass some more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2087
diff
changeset
|
953 while (cycle > cd->m68k->current_cycle) { |
2066
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
954 if (m68k_run) { |
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
955 uint32_t start = cd->m68k->current_cycle; |
2104
ff32a90260c9
Initial support for using debugger on sub CPU
Michael Pavone <pavone@retrodev.com>
parents:
2099
diff
changeset
|
956 cd->m68k->sync_cycle = cd->enter_debugger ? cd->m68k->current_cycle + 1 : cycle; |
2066
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
957 if (cd->need_reset) { |
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
958 cd->need_reset = 0; |
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
959 m68k_reset(cd->m68k); |
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
960 } else { |
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
961 calculate_target_cycle(cd->m68k); |
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
962 resume_68k(cd->m68k); |
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
963 } |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
964 } else { |
2066
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
965 cd->m68k->current_cycle = cycle; |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
966 } |
2094
ca6fc8c8dc60
Pass some more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2087
diff
changeset
|
967 scd_peripherals_run(cd, cd->m68k->current_cycle); |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
968 } |
2094
ca6fc8c8dc60
Pass some more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2087
diff
changeset
|
969 |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
970 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
971 |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
972 uint32_t gen_cycle_to_scd(uint32_t cycle, genesis_context *gen) |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
973 { |
2055
c4d066d798c4
Fix prog RAM banking and Genesis to SCD cycle conversion. Arkagis Escape demo now works
Michael Pavone <pavone@retrodev.com>
parents:
2054
diff
changeset
|
974 return ((uint64_t)cycle) * ((uint64_t)SCD_MCLKS) / ((uint64_t)gen->normal_clock); |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
975 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
976 |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
977 void scd_adjust_cycle(segacd_context *cd, uint32_t deduction) |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
978 { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
979 deduction = gen_cycle_to_scd(deduction, cd->genesis); |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
980 cd->m68k->current_cycle -= deduction; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
981 cd->stopwatch_cycle -= deduction; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
982 if (deduction >= cd->int2_cycle) { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
983 cd->int2_cycle = 0; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
984 } else if (cd->int2_cycle != CYCLE_NEVER) { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
985 cd->int2_cycle -= deduction; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
986 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
987 if (deduction >= cd->periph_reset_cycle) { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
988 cd->periph_reset_cycle = CYCLE_NEVER; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
989 } else if (cd->periph_reset_cycle != CYCLE_NEVER) { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
990 cd->periph_reset_cycle -= deduction; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
991 } |
2061
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
992 cdd_mcu_adjust_cycle(&cd->cdd, deduction); |
2066
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
993 lc8951_adjust_cycles(&cd->cdc, deduction); |
2069
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
994 cd->graphics_cycle -= deduction; |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
995 if (cd->graphics_int_cycle != CYCLE_NEVER) { |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
996 if (cd->graphics_int_cycle > deduction) { |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
997 cd->graphics_int_cycle -= deduction; |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
998 } else { |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
999 cd->graphics_int_cycle = 0; |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
1000 } |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
1001 } |
2081
cfd53c94fffb
Initial stab at RF5C164 emulation
Michael Pavone <pavone@retrodev.com>
parents:
2080
diff
changeset
|
1002 cd->pcm.cycle -= deduction; |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1003 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1004 |
1502
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1005 static uint16_t main_gate_read16(uint32_t address, void *vcontext) |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1006 { |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1007 m68k_context *m68k = vcontext; |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1008 genesis_context *gen = m68k->system; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1009 segacd_context *cd = gen->expansion; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1010 uint32_t scd_cycle = gen_cycle_to_scd(m68k->current_cycle, gen); |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1011 scd_run(cd, scd_cycle); |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1012 uint32_t offset = (address & 0x1FF) >> 1; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1013 switch (offset) |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1014 { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1015 case GA_SUB_CPU_CTRL: { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1016 uint16_t value = 0; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1017 if (cd->gate_array[GA_INT_MASK] & BIT_MASK_IEN2) { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1018 value |= BIT_IEN2; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1019 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1020 if (cd->int2_cycle != CYCLE_NEVER) { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1021 value |= BIT_IFL2; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1022 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1023 if (can_main_access_prog(cd)) { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1024 value |= BIT_SBRQ; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1025 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1026 if (cd->reset) { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1027 value |= BIT_SRES; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1028 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1029 return value; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1030 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1031 case GA_MEM_MODE: |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1032 //Main CPU can't read priority mode bits |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1033 return cd->gate_array[offset] & 0xFFE7; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1034 case GA_HINT_VECTOR: |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1035 return cd->rom_mut[0x72/2]; |
2065
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
1036 case GA_CDC_HOST_DATA: { |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
1037 uint16_t dst = cd->gate_array[GA_CDC_CTRL] >> 8 & 0x7; |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
1038 if (dst == DST_MAIN_CPU) { |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
1039 if (cd->gate_array[GA_CDC_CTRL] & BIT_DSR) { |
2066
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
1040 printf("DSR cleared at %u (%u)\n", scd_cycle, cd->cdc.cycle); |
2065
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
1041 cd->gate_array[GA_CDC_CTRL] &= ~BIT_DSR; |
2066
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
1042 lc8951_resume_transfer(&cd->cdc, scd_cycle); |
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
1043 } else { |
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
1044 printf("Read of CDC host data with DSR clear at %u\n", scd_cycle); |
2065
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
1045 } |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
1046 calculate_target_cycle(cd->m68k); |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
1047 } |
2066
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
1048 return cd->gate_array[offset]; |
2065
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
1049 } |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1050 case GA_CDC_DMA_ADDR: |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1051 //TODO: open bus maybe? |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1052 return 0xFFFF; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1053 default: |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1054 if (offset < GA_TIMER) { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1055 return cd->gate_array[offset]; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1056 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1057 //TODO: open bus maybe? |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1058 return 0xFFFF; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1059 } |
1502
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1060 } |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1061 |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1062 static uint8_t main_gate_read8(uint32_t address, void *vcontext) |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1063 { |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1064 uint16_t val = main_gate_read16(address & 0xFE, vcontext); |
1502
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1065 return address & 1 ? val : val >> 8; |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1066 } |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1067 |
2068
f573f2c31bc9
Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents:
2066
diff
changeset
|
1068 static void dump_prog_ram(segacd_context *cd) |
f573f2c31bc9
Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents:
2066
diff
changeset
|
1069 { |
f573f2c31bc9
Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents:
2066
diff
changeset
|
1070 static int dump_count; |
f573f2c31bc9
Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents:
2066
diff
changeset
|
1071 char fname[256]; |
f573f2c31bc9
Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents:
2066
diff
changeset
|
1072 sprintf(fname, "prog_ram_%d.bin", dump_count++); |
f573f2c31bc9
Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents:
2066
diff
changeset
|
1073 FILE *f = fopen(fname, "wb"); |
f573f2c31bc9
Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents:
2066
diff
changeset
|
1074 if (f) { |
f573f2c31bc9
Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents:
2066
diff
changeset
|
1075 uint32_t last = 256*1024-1; |
f573f2c31bc9
Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents:
2066
diff
changeset
|
1076 for(; last > 0; --last) |
f573f2c31bc9
Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents:
2066
diff
changeset
|
1077 { |
f573f2c31bc9
Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents:
2066
diff
changeset
|
1078 if (cd->prog_ram[last]) { |
f573f2c31bc9
Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents:
2066
diff
changeset
|
1079 break; |
f573f2c31bc9
Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents:
2066
diff
changeset
|
1080 } |
f573f2c31bc9
Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents:
2066
diff
changeset
|
1081 } |
f573f2c31bc9
Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents:
2066
diff
changeset
|
1082 for (uint32_t i = 0; i <= last; i++) |
f573f2c31bc9
Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents:
2066
diff
changeset
|
1083 { |
f573f2c31bc9
Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents:
2066
diff
changeset
|
1084 uint8_t pair[2]; |
f573f2c31bc9
Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents:
2066
diff
changeset
|
1085 pair[0] = cd->prog_ram[i] >> 8; |
f573f2c31bc9
Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents:
2066
diff
changeset
|
1086 pair[1] = cd->prog_ram[i]; |
f573f2c31bc9
Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents:
2066
diff
changeset
|
1087 fwrite(pair, 1, sizeof(pair), f); |
f573f2c31bc9
Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents:
2066
diff
changeset
|
1088 } |
f573f2c31bc9
Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents:
2066
diff
changeset
|
1089 |
f573f2c31bc9
Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents:
2066
diff
changeset
|
1090 fclose(f); |
f573f2c31bc9
Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents:
2066
diff
changeset
|
1091 } |
f573f2c31bc9
Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents:
2066
diff
changeset
|
1092 } |
f573f2c31bc9
Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents:
2066
diff
changeset
|
1093 |
1502
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1094 static void *main_gate_write16(uint32_t address, void *vcontext, uint16_t value) |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1095 { |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1096 m68k_context *m68k = vcontext; |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1097 genesis_context *gen = m68k->system; |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1098 segacd_context *cd = gen->expansion; |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1099 uint32_t scd_cycle = gen_cycle_to_scd(m68k->current_cycle, gen); |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1100 scd_run(cd, scd_cycle); |
1502
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1101 uint32_t reg = (address & 0x1FF) >> 1; |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1102 switch (reg) |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1103 { |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1104 case GA_SUB_CPU_CTRL: { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1105 uint8_t old_access = can_main_access_prog(cd); |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1106 cd->busreq = value & BIT_SBRQ; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1107 uint8_t old_reset = cd->reset; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1108 cd->reset = value & BIT_SRES; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1109 if (cd->reset && !old_reset) { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1110 cd->need_reset = 1; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1111 } |
2057
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
1112 if (value & BIT_IFL2) { |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
1113 cd->int2_cycle = scd_cycle; |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
1114 } |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
1115 /*cd->gate_array[reg] &= 0x7FFF; |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
1116 cd->gate_array[reg] |= value & 0x8000;*/ |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1117 uint8_t new_access = can_main_access_prog(cd); |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1118 uint32_t bank = cd->gate_array[GA_MEM_MODE] >> 6 & 0x3; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1119 if (new_access) { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1120 if (!old_access) { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1121 m68k->mem_pointers[cd->memptr_start_index] = cd->prog_ram + bank * 0x10000; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1122 m68k_invalidate_code_range(m68k, cd->base + 0x220000, cd->base + 0x240000); |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1123 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1124 } else if (old_access) { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1125 m68k->mem_pointers[cd->memptr_start_index] = NULL; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1126 m68k_invalidate_code_range(m68k, cd->base + 0x220000, cd->base + 0x240000); |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1127 m68k_invalidate_code_range(cd->m68k, bank * 0x20000, (bank + 1) * 0x20000); |
2068
f573f2c31bc9
Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents:
2066
diff
changeset
|
1128 if (!new_access) { |
f573f2c31bc9
Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents:
2066
diff
changeset
|
1129 dump_prog_ram(cd); |
f573f2c31bc9
Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents:
2066
diff
changeset
|
1130 } |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1131 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1132 break; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1133 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1134 case GA_MEM_MODE: { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1135 uint16_t changed = cd->gate_array[reg] ^ value; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1136 //Main CPU can't write priority mode bits, MODE or RET |
2057
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
1137 cd->gate_array[reg] &= 0x001F; |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1138 cd->gate_array[reg] |= value & 0xFFC0; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1139 if ((cd->gate_array[reg] & BIT_MEM_MODE)) { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1140 //1M mode |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1141 if (!(value & BIT_DMNA)) { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1142 cd->gate_array[reg] |= BIT_DMNA; |
2119
5ec2f97365a2
More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents:
2116
diff
changeset
|
1143 cd->main_swap_request = 1; |
5ec2f97365a2
More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents:
2116
diff
changeset
|
1144 } else { |
5ec2f97365a2
More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents:
2116
diff
changeset
|
1145 cd->main_has_word2m = 0; |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1146 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1147 } else { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1148 //2M mode |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1149 if (changed & value & BIT_DMNA) { |
2057
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
1150 cd->gate_array[reg] |= BIT_DMNA; |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1151 m68k->mem_pointers[cd->memptr_start_index + 1] = NULL; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1152 m68k->mem_pointers[cd->memptr_start_index + 2] = NULL; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1153 cd->m68k->mem_pointers[0] = cd->word_ram; |
2057
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
1154 cd->gate_array[reg] &= ~BIT_RET; |
2119
5ec2f97365a2
More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents:
2116
diff
changeset
|
1155 cd->main_has_word2m = 0; |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1156 |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1157 m68k_invalidate_code_range(m68k, cd->base + 0x200000, cd->base + 0x240000); |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1158 m68k_invalidate_code_range(cd->m68k, 0x080000, 0x0C0000); |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1159 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1160 } |
2057
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
1161 if (changed & MASK_PROG_BANK && can_main_access_prog(cd)) { |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1162 uint32_t bank = cd->gate_array[GA_MEM_MODE] >> 6 & 0x3; |
2055
c4d066d798c4
Fix prog RAM banking and Genesis to SCD cycle conversion. Arkagis Escape demo now works
Michael Pavone <pavone@retrodev.com>
parents:
2054
diff
changeset
|
1163 m68k->mem_pointers[cd->memptr_start_index] = cd->prog_ram + bank * 0x10000; |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1164 m68k_invalidate_code_range(m68k, cd->base + 0x220000, cd->base + 0x240000); |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1165 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1166 break; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1167 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1168 case GA_HINT_VECTOR: |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1169 cd->rom_mut[0x72/2] = value; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1170 break; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1171 case GA_COMM_FLAG: |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1172 //Main CPU can only write the upper byte; |
1502
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1173 cd->gate_array[reg] &= 0xFF; |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1174 cd->gate_array[reg] |= value & 0xFF00; |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1175 break; |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1176 case GA_COMM_CMD0: |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1177 case GA_COMM_CMD1: |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1178 case GA_COMM_CMD2: |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1179 case GA_COMM_CMD3: |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1180 case GA_COMM_CMD4: |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1181 case GA_COMM_CMD5: |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1182 case GA_COMM_CMD6: |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1183 case GA_COMM_CMD7: |
1502
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
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diff
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|
1184 //no effects for these other than saving the value |
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diff
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|
1185 cd->gate_array[reg] = value; |
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diff
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|
1186 break; |
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diff
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|
1187 default: |
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1188 printf("Unhandled gate array write %X:%X\n", address, value); |
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diff
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1189 } |
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|
1190 return vcontext; |
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Initial skeleton of Sega CD memory handlers
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diff
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|
1191 } |
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diff
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|
1192 |
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diff
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1193 static void *main_gate_write8(uint32_t address, void *vcontext, uint8_t value) |
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diff
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1194 { |
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Initial skeleton of Sega CD memory handlers
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diff
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|
1195 m68k_context *m68k = vcontext; |
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Initial skeleton of Sega CD memory handlers
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diff
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1196 genesis_context *gen = m68k->system; |
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diff
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1197 segacd_context *cd = gen->expansion; |
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1198 uint32_t reg = (address & 0x1FF) >> 1; |
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|
1199 uint16_t value16; |
2108
68d61ba1b762
Fix handling of byte writes to gate array regs from main CPU
Michael Pavone <pavone@retrodev.com>
parents:
2106
diff
changeset
|
1200 switch (reg) |
2056
27bbfcb7850a
Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2055
diff
changeset
|
1201 { |
2057
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
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diff
changeset
|
1202 case GA_SUB_CPU_CTRL: |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
1203 if (address & 1) { |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
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diff
changeset
|
1204 value16 = value; |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
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diff
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|
1205 } else { |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
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diff
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|
1206 value16 = value << 8; |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
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diff
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|
1207 if (cd->reset) { |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
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|
1208 value16 |= BIT_SRES; |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
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parents:
2056
diff
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|
1209 } |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
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diff
changeset
|
1210 if (cd->busreq) { |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
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|
1211 value16 |= BIT_SBRQ; |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
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|
1212 } |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
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|
1213 } |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
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|
1214 break; |
2056
27bbfcb7850a
Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2055
diff
changeset
|
1215 case GA_HINT_VECTOR: |
27bbfcb7850a
Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2055
diff
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|
1216 case GA_COMM_FLAG: |
27bbfcb7850a
Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2055
diff
changeset
|
1217 //writes to these regs are always treated as word wide |
27bbfcb7850a
Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2055
diff
changeset
|
1218 value16 = value | (value << 8); |
27bbfcb7850a
Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2055
diff
changeset
|
1219 break; |
27bbfcb7850a
Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2055
diff
changeset
|
1220 default: |
27bbfcb7850a
Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
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diff
changeset
|
1221 if (address & 1) { |
27bbfcb7850a
Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2055
diff
changeset
|
1222 value16 = cd->gate_array[reg] & 0xFF00 | value; |
27bbfcb7850a
Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
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diff
changeset
|
1223 } else { |
27bbfcb7850a
Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2055
diff
changeset
|
1224 value16 = cd->gate_array[reg] & 0xFF | (value << 8); |
27bbfcb7850a
Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
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diff
changeset
|
1225 } |
1502
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Initial skeleton of Sega CD memory handlers
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diff
changeset
|
1226 } |
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Initial skeleton of Sega CD memory handlers
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diff
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|
1227 return main_gate_write16(address, vcontext, value16); |
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Initial skeleton of Sega CD memory handlers
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diff
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|
1228 } |
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Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
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diff
changeset
|
1229 |
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Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
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1467
diff
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|
1230 segacd_context *alloc_configure_segacd(system_media *media, uint32_t opts, uint8_t force_region, rom_info *info) |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
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diff
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|
1231 { |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
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1467
diff
changeset
|
1232 static memmap_chunk sub_cpu_map[] = { |
2111
4be496489eda
Fix some off-by-ones in the address map definition for Sega CD hardware
Michael Pavone <pavone@retrodev.com>
parents:
2108
diff
changeset
|
1233 {0x000000, 0x01FF00, 0xFFFFFF, .flags=MMAP_READ | MMAP_CODE, .write_16 = prog_ram_wp_write16, .write_8 = prog_ram_wp_write8}, |
4be496489eda
Fix some off-by-ones in the address map definition for Sega CD hardware
Michael Pavone <pavone@retrodev.com>
parents:
2108
diff
changeset
|
1234 {0x01FF00, 0x080000, 0xFFFFFF, .flags=MMAP_READ | MMAP_WRITE | MMAP_CODE}, |
4be496489eda
Fix some off-by-ones in the address map definition for Sega CD hardware
Michael Pavone <pavone@retrodev.com>
parents:
2108
diff
changeset
|
1235 {0x080000, 0x0C0000, 0x03FFFF, .flags=MMAP_READ | MMAP_WRITE | MMAP_CODE | MMAP_PTR_IDX | MMAP_FUNC_NULL, .ptr_index = 0, |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1236 .read_16 = word_ram_2M_read16, .write_16 = word_ram_2M_write16, .read_8 = word_ram_2M_read8, .write_8 = word_ram_2M_write8}, |
2111
4be496489eda
Fix some off-by-ones in the address map definition for Sega CD hardware
Michael Pavone <pavone@retrodev.com>
parents:
2108
diff
changeset
|
1237 {0x0C0000, 0x0E0000, 0x01FFFF, .flags=MMAP_READ | MMAP_WRITE | MMAP_CODE | MMAP_PTR_IDX | MMAP_FUNC_NULL, .ptr_index = 1, |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1238 .read_16 = word_ram_1M_read16, .write_16 = word_ram_1M_write16, .read_8 = word_ram_1M_read8, .write_8 = word_ram_1M_write8}, |
2111
4be496489eda
Fix some off-by-ones in the address map definition for Sega CD hardware
Michael Pavone <pavone@retrodev.com>
parents:
2108
diff
changeset
|
1239 {0xFE0000, 0xFF0000, 0x003FFF, .flags=MMAP_READ | MMAP_WRITE | MMAP_ONLY_ODD}, |
4be496489eda
Fix some off-by-ones in the address map definition for Sega CD hardware
Michael Pavone <pavone@retrodev.com>
parents:
2108
diff
changeset
|
1240 {0xFF0000, 0xFF8000, 0x003FFF, .read_16 = pcm_read16, .write_16 = pcm_write16, .read_8 = pcm_read8, .write_8 = pcm_write8}, |
4be496489eda
Fix some off-by-ones in the address map definition for Sega CD hardware
Michael Pavone <pavone@retrodev.com>
parents:
2108
diff
changeset
|
1241 {0xFF8000, 0xFF8200, 0x0001FF, .read_16 = sub_gate_read16, .write_16 = sub_gate_write16, .read_8 = sub_gate_read8, .write_8 = sub_gate_write8} |
1502
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1242 }; |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1243 |
1502
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1244 segacd_context *cd = calloc(sizeof(segacd_context), 1); |
2083
372625dd9590
Persist BRAM to file. Load BIOS relative to blastem directory
Michael Pavone <pavone@retrodev.com>
parents:
2081
diff
changeset
|
1245 uint32_t firmware_size; |
372625dd9590
Persist BRAM to file. Load BIOS relative to blastem directory
Michael Pavone <pavone@retrodev.com>
parents:
2081
diff
changeset
|
1246 cd->rom = (uint16_t *)read_bundled_file("cdbios.bin", &firmware_size); |
1502
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1247 uint32_t adjusted_size = nearest_pow2(firmware_size); |
2083
372625dd9590
Persist BRAM to file. Load BIOS relative to blastem directory
Michael Pavone <pavone@retrodev.com>
parents:
2081
diff
changeset
|
1248 if (adjusted_size != firmware_size) { |
372625dd9590
Persist BRAM to file. Load BIOS relative to blastem directory
Michael Pavone <pavone@retrodev.com>
parents:
2081
diff
changeset
|
1249 cd->rom = realloc(cd->rom, adjusted_size); |
1502
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1250 } |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1251 cd->rom_mut = malloc(adjusted_size); |
1503
a763523dadf4
Added code for initializing a combined Genesis + Sega CD system when a Sega CD ISO is loaded
Michael Pavone <pavone@retrodev.com>
parents:
1502
diff
changeset
|
1252 byteswap_rom(adjusted_size, cd->rom); |
1502
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1253 memcpy(cd->rom_mut, cd->rom, adjusted_size); |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1254 cd->rom_mut[0x72/2] = 0xFFFF; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1255 |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1256 //memset(info, 0, sizeof(*info)); |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1257 //tern_node *db = get_rom_db(); |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1258 //*info = configure_rom(db, media->buffer, media->size, media->chain ? media->chain->buffer : NULL, media->chain ? media->chain->size : 0, NULL, 0); |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1259 |
2083
372625dd9590
Persist BRAM to file. Load BIOS relative to blastem directory
Michael Pavone <pavone@retrodev.com>
parents:
2081
diff
changeset
|
1260 cd->prog_ram = calloc(512*1024, 1); |
372625dd9590
Persist BRAM to file. Load BIOS relative to blastem directory
Michael Pavone <pavone@retrodev.com>
parents:
2081
diff
changeset
|
1261 cd->word_ram = calloc(256*1024, 1); |
372625dd9590
Persist BRAM to file. Load BIOS relative to blastem directory
Michael Pavone <pavone@retrodev.com>
parents:
2081
diff
changeset
|
1262 cd->pcm_ram = calloc(64*1024, 1); |
1502
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1263 //TODO: Load state from file |
2083
372625dd9590
Persist BRAM to file. Load BIOS relative to blastem directory
Michael Pavone <pavone@retrodev.com>
parents:
2081
diff
changeset
|
1264 cd->bram = calloc(8*1024, 1); |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1265 |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1266 |
1502
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1267 sub_cpu_map[0].buffer = sub_cpu_map[1].buffer = cd->prog_ram; |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1268 sub_cpu_map[4].buffer = cd->bram; |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1269 m68k_options *mopts = malloc(sizeof(m68k_options)); |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1270 init_m68k_opts(mopts, sub_cpu_map, sizeof(sub_cpu_map) / sizeof(*sub_cpu_map), 4, sync_components); |
1502
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1271 cd->m68k = init_68k_context(mopts, NULL); |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1272 cd->m68k->system = cd; |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1273 cd->int2_cycle = CYCLE_NEVER; |
1502
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1274 cd->busreq = 1; |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1275 cd->busack = 1; |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1276 cd->need_reset = 1; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1277 cd->reset = 1; //active low, so reset is not active on start |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1278 cd->memptr_start_index = 0; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1279 cd->gate_array[1] = 1; |
2080 | 1280 cd->gate_array[GA_CDD_CTRL] = BIT_MUTE; //Data/mute flag is set on start |
2119
5ec2f97365a2
More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents:
2116
diff
changeset
|
1281 cd->main_has_word2m = 1; |
2065
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
1282 lc8951_init(&cd->cdc, handle_cdc_byte, cd); |
2061
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
1283 if (media->chain && media->type != MEDIA_CDROM) { |
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
1284 media = media->chain; |
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
1285 } |
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
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1286 cdd_mcu_init(&cd->cdd, media); |
2069
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1287 cd_graphics_init(cd); |
2080 | 1288 cdd_fader_init(&cd->fader); |
2081
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Initial stab at RF5C164 emulation
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1289 rf5c164_init(&cd->pcm, SCD_MCLKS, 4); |
1502
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1290 return cd; |
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1291 } |
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1292 |
2054
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1293 memmap_chunk *segacd_main_cpu_map(segacd_context *cd, uint8_t cart_boot, uint32_t *num_chunks) |
1502
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1294 { |
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1295 static memmap_chunk main_cpu_map[] = { |
2111
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1296 {0x000000, 0x020000, 0x01FFFF, .flags=MMAP_READ}, |
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1297 {0x020000, 0x040000, 0x01FFFF, .flags=MMAP_READ|MMAP_WRITE|MMAP_PTR_IDX|MMAP_FUNC_NULL|MMAP_CODE, .ptr_index = 0, |
2054
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1298 .read_16 = unmapped_prog_read16, .write_16 = unmapped_prog_write16, .read_8 = unmapped_prog_read8, .write_8 = unmapped_prog_write8}, |
2111
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1299 {0x040000, 0x060000, 0x01FFFF, .flags=MMAP_READ}, //first ROM alias |
1502
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1300 //TODO: additional ROM/prog RAM aliases |
2111
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1301 {0x200000, 0x220000, 0x01FFFF, .flags=MMAP_READ|MMAP_WRITE|MMAP_PTR_IDX|MMAP_FUNC_NULL|MMAP_CODE, .ptr_index = 1, |
2057
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1302 .read_16 = unmapped_word_read16, .write_16 = unmapped_word_write16, .read_8 = unmapped_word_read8, .write_8 = unmapped_word_write8}, |
2111
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1303 {0x220000, 0x240000, 0x01FFFF, .flags=MMAP_READ|MMAP_WRITE|MMAP_PTR_IDX|MMAP_FUNC_NULL|MMAP_CODE, .ptr_index = 2, |
2057
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1304 .read_16 = cell_image_read16, .write_16 = cell_image_write16, .read_8 = cell_image_read8, .write_8 = cell_image_write8}, |
2111
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1305 {0xA12000, 0xA13000, 0xFFFFFF, .read_16 = main_gate_read16, .write_16 = main_gate_write16, .read_8 = main_gate_read8, .write_8 = main_gate_write8} |
1502
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1306 }; |
2054
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1307 for (int i = 0; i < sizeof(main_cpu_map) / sizeof(*main_cpu_map); i++) |
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1308 { |
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1309 if (main_cpu_map[i].start < 0x800000) { |
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1310 if (cart_boot) { |
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1311 main_cpu_map[i].start |= 0x400000; |
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1312 main_cpu_map[i].end |= 0x400000; |
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1313 } else { |
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1314 main_cpu_map[i].start &= 0x3FFFFF; |
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1315 main_cpu_map[i].end &= 0x3FFFFF; |
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1316 } |
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1317 } |
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1318 } |
1502
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1319 //TODO: support BRAM cart |
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1320 main_cpu_map[0].buffer = cd->rom_mut; |
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1321 main_cpu_map[2].buffer = cd->rom; |
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1322 main_cpu_map[1].buffer = cd->prog_ram; |
2054
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1323 main_cpu_map[3].buffer = cd->word_ram; |
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1324 main_cpu_map[4].buffer = cd->word_ram + 0x10000; |
1502
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1325 *num_chunks = sizeof(main_cpu_map) / sizeof(*main_cpu_map); |
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1326 return main_cpu_map; |
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1327 } |