Mercurial > repos > blastem
annotate cpu_dsl.py @ 2442:52cfc7b14dd2
Sugar for some basic conditionals in CPU DSL
author | Michael Pavone <pavone@retrodev.com> |
---|---|
date | Sun, 11 Feb 2024 20:41:28 -0800 |
parents | 4435abe5db5e |
children | 461fffc226e0 |
rev | line source |
---|---|
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1 #!/usr/bin/env python3 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2 |
2440
338c78da3fff
Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents:
1991
diff
changeset
|
3 assignmentOps = { |
338c78da3fff
Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents:
1991
diff
changeset
|
4 '=': 'mov', |
338c78da3fff
Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents:
1991
diff
changeset
|
5 '+=': 'add', |
338c78da3fff
Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents:
1991
diff
changeset
|
6 '-=': 'sub', |
338c78da3fff
Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents:
1991
diff
changeset
|
7 '<<=': 'lsl', |
338c78da3fff
Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents:
1991
diff
changeset
|
8 '>>=': 'lsr', |
338c78da3fff
Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents:
1991
diff
changeset
|
9 '&=': 'and', |
338c78da3fff
Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents:
1991
diff
changeset
|
10 '|=': 'or', |
338c78da3fff
Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents:
1991
diff
changeset
|
11 '^=': 'xor' |
338c78da3fff
Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents:
1991
diff
changeset
|
12 } |
2441
4435abe5db5e
Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
2440
diff
changeset
|
13 binaryOps = { |
4435abe5db5e
Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
2440
diff
changeset
|
14 '+': 'add', |
4435abe5db5e
Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
2440
diff
changeset
|
15 '-': 'sub', |
4435abe5db5e
Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
2440
diff
changeset
|
16 '<<': 'lsl', |
4435abe5db5e
Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
2440
diff
changeset
|
17 '>>': 'lsr', |
4435abe5db5e
Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
2440
diff
changeset
|
18 '&': 'and', |
4435abe5db5e
Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
2440
diff
changeset
|
19 '|': 'or', |
4435abe5db5e
Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
2440
diff
changeset
|
20 '^': 'xor' |
4435abe5db5e
Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
2440
diff
changeset
|
21 } |
2442
52cfc7b14dd2
Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
2441
diff
changeset
|
22 compareOps = {'>=U', '=', '!='} |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
23 class Block: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
24 def addOp(self, op): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
25 pass |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
26 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
27 def processLine(self, parts): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
28 if parts[0] == 'switch': |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
29 o = Switch(self, parts[1]) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
30 self.addOp(o) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
31 return o |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
32 elif parts[0] == 'if': |
2442
52cfc7b14dd2
Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
2441
diff
changeset
|
33 if len(parts) == 4 and parts[2] in compareOps: |
52cfc7b14dd2
Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
2441
diff
changeset
|
34 self.addOp(NormalOp(['cmp', parts[3], parts[1]])) |
52cfc7b14dd2
Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
2441
diff
changeset
|
35 cond = parts[2] |
52cfc7b14dd2
Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
2441
diff
changeset
|
36 else: |
52cfc7b14dd2
Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
2441
diff
changeset
|
37 cond = parts[1] |
52cfc7b14dd2
Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
2441
diff
changeset
|
38 o = If(self, cond) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
39 self.addOp(o) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
40 return o |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
41 elif parts[0] == 'end': |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
42 raise Exception('end is only allowed inside a switch or if block') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
43 else: |
2440
338c78da3fff
Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents:
1991
diff
changeset
|
44 if len(parts) > 1 and parts[1] in assignmentOps: |
338c78da3fff
Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents:
1991
diff
changeset
|
45 dst = parts[0] |
338c78da3fff
Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents:
1991
diff
changeset
|
46 op = parts[1] |
338c78da3fff
Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents:
1991
diff
changeset
|
47 parts = [assignmentOps[op]] + parts[2:] |
2441
4435abe5db5e
Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
2440
diff
changeset
|
48 if op == '=': |
4435abe5db5e
Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
2440
diff
changeset
|
49 if len(parts) > 2 and parts[2] in binaryOps: |
4435abe5db5e
Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
2440
diff
changeset
|
50 op = parts[2] |
4435abe5db5e
Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
2440
diff
changeset
|
51 parts[0] = binaryOps[op] |
4435abe5db5e
Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
2440
diff
changeset
|
52 del parts[2] |
4435abe5db5e
Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
2440
diff
changeset
|
53 else: |
2440
338c78da3fff
Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents:
1991
diff
changeset
|
54 if op == '<<=' or op == '>>=': |
338c78da3fff
Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents:
1991
diff
changeset
|
55 parts.insert(1, dst) |
338c78da3fff
Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents:
1991
diff
changeset
|
56 else: |
338c78da3fff
Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents:
1991
diff
changeset
|
57 parts.append(dst) |
338c78da3fff
Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents:
1991
diff
changeset
|
58 parts.append(dst) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
59 self.addOp(NormalOp(parts)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
60 return self |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
61 |
1704
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
62 def processOps(self, prog, fieldVals, output, otype, oplist): |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
63 for i in range(0, len(oplist)): |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
64 if i + 1 < len(oplist) and oplist[i+1].op == 'update_flags': |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
65 flagUpdates, _ = prog.flags.parseFlagUpdate(oplist[i+1].params[0]) |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
66 else: |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
67 flagUpdates = None |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
68 oplist[i].generate(prog, self, fieldVals, output, otype, flagUpdates) |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
69 |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
70 def resolveLocal(self, name): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
71 return None |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
72 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
73 class ChildBlock(Block): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
74 def processLine(self, parts): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
75 if parts[0] == 'end': |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
76 return self.parent |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
77 return super().processLine(parts) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
78 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
79 #Represents an instruction of the emulated CPU |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
80 class Instruction(Block): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
81 def __init__(self, value, fields, name): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
82 self.value = value |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
83 self.fields = fields |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
84 self.name = name |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
85 self.implementation = [] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
86 self.locals = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
87 self.regValues = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
88 self.varyingBits = 0 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
89 self.invalidFieldValues = {} |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
90 self.invalidCombos = [] |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
91 self.newLocals = [] |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
92 for field in fields: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
93 self.varyingBits += fields[field][1] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
94 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
95 def addOp(self, op): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
96 if op.op == 'local': |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
97 name = op.params[0] |
1715
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1713
diff
changeset
|
98 size = int(op.params[1]) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
99 self.locals[name] = size |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
100 elif op.op == 'invalid': |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
101 if len(op.params) < 3: |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
102 name = op.params[0] |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
103 value = int(op.params[1]) |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
104 self.invalidFieldValues.setdefault(name, set()).add(value) |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
105 else: |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
106 vmap = {} |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
107 for i in range(0, len(op.params), 2): |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
108 name = op.params[i] |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
109 value = int(op.params[i+1]) |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
110 vmap[name] = value |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
111 self.invalidCombos.append(vmap) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
112 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
113 self.implementation.append(op) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
114 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
115 def resolveLocal(self, name): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
116 if name in self.locals: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
117 return name |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
118 return None |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
119 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
120 def addLocal(self, name, size): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
121 self.locals[name] = size |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
122 self.newLocals.append(name) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
123 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
124 def localSize(self, name): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
125 return self.locals.get(name) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
126 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
127 def __lt__(self, other): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
128 if isinstance(other, Instruction): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
129 if self.varyingBits != other.varyingBits: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
130 return self.varyingBits < other.varyingBits |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
131 return self.value < other.value |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
132 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
133 return NotImplemented |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
134 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
135 def allValues(self): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
136 values = [] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
137 for i in range(0, 1 << self.varyingBits): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
138 iword = self.value |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
139 doIt = True |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
140 combos = [] |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
141 for combo in self.invalidCombos: |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
142 combos.append(dict(combo)) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
143 for field in self.fields: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
144 shift,bits = self.fields[field] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
145 val = i & ((1 << bits) - 1) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
146 if field in self.invalidFieldValues and val in self.invalidFieldValues[field]: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
147 doIt = False |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
148 break |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
149 nextcombos = [] |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
150 for combo in combos: |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
151 if field in combo: |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
152 if combo[field] == val: |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
153 del combo[field] |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
154 if not combo: |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
155 doIt = False |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
156 break |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
157 else: |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
158 continue |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
159 nextcombos.append(combo) |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
160 combos = nextcombos |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
161 if not doIt: |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
162 break |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
163 i >>= bits |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
164 iword |= val << shift |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
165 if doIt: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
166 values.append(iword) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
167 return values |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
168 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
169 def getFieldVals(self, value): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
170 fieldVals = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
171 fieldBits = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
172 for field in self.fields: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
173 shift,bits = self.fields[field] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
174 val = (value >> shift) & ((1 << bits) - 1) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
175 fieldVals[field] = val |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
176 fieldBits[field] = bits |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
177 return (fieldVals, fieldBits) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
178 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
179 def generateName(self, value): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
180 fieldVals,fieldBits = self.getFieldVals(value) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
181 names = list(fieldVals.keys()) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
182 names.sort() |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
183 funName = self.name |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
184 for name in names: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
185 funName += '_{0}_{1:0>{2}}'.format(name, bin(fieldVals[name])[2:], fieldBits[name]) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
186 return funName |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
187 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
188 def generateBody(self, value, prog, otype): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
189 output = [] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
190 prog.meta = {} |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
191 prog.pushScope(self) |
1614
c9639139aedf
Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents:
1613
diff
changeset
|
192 self.regValues = {} |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
193 for var in self.locals: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
194 output.append('\n\tuint{sz}_t {name};'.format(sz=self.locals[var], name=var)) |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
195 self.newLocals = [] |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
196 fieldVals,_ = self.getFieldVals(value) |
1704
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
197 self.processOps(prog, fieldVals, output, otype, self.implementation) |
1749
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
198 |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
199 if prog.dispatch == 'call': |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
200 begin = '\nvoid ' + self.generateName(value) + '(' + prog.context_type + ' *context, uint32_t target_cycle)\n{' |
1749
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
201 elif prog.dispatch == 'goto': |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
202 begin = '\n' + self.generateName(value) + ': {' |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
203 else: |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
204 raise Exception('Unsupported dispatch type ' + prog.dispatch) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
205 if prog.needFlagCoalesce: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
206 begin += prog.flags.coalesceFlags(prog, otype) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
207 if prog.needFlagDisperse: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
208 output.append(prog.flags.disperseFlags(prog, otype)) |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
209 for var in self.newLocals: |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
210 begin += '\n\tuint{sz}_t {name};'.format(sz=self.locals[var], name=var) |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
211 for size in prog.temp: |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
212 begin += '\n\tuint{sz}_t gen_tmp{sz}__;'.format(sz=size) |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
213 prog.popScope() |
1749
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
214 if prog.dispatch == 'goto': |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
215 output += prog.nextInstruction(otype) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
216 return begin + ''.join(output) + '\n}' |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
217 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
218 def __str__(self): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
219 pieces = [self.name + ' ' + hex(self.value) + ' ' + str(self.fields)] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
220 for name in self.locals: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
221 pieces.append('\n\tlocal {0} {1}'.format(name, self.locals[name])) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
222 for op in self.implementation: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
223 pieces.append(str(op)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
224 return ''.join(pieces) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
225 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
226 #Represents the definition of a helper function |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
227 class SubRoutine(Block): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
228 def __init__(self, name): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
229 self.name = name |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
230 self.implementation = [] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
231 self.args = [] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
232 self.arg_map = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
233 self.locals = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
234 self.regValues = {} |
1721
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
235 self.argValues = {} |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
236 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
237 def addOp(self, op): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
238 if op.op == 'arg': |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
239 name = op.params[0] |
1721
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
240 size = int(op.params[1]) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
241 self.arg_map[name] = len(self.args) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
242 self.args.append((name, size)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
243 elif op.op == 'local': |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
244 name = op.params[0] |
1734
88fbc4e711fd
Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1733
diff
changeset
|
245 size = int(op.params[1]) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
246 self.locals[name] = size |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
247 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
248 self.implementation.append(op) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
249 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
250 def resolveLocal(self, name): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
251 if name in self.locals: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
252 return self.name + '_' + name |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
253 return None |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
254 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
255 def addLocal(self, name, size): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
256 self.locals[name] = size |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
257 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
258 def localSize(self, name): |
1721
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
259 if name in self.locals: |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
260 return self.locals[name] |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
261 if name in self.arg_map: |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
262 argIndex = self.arg_map[name] |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
263 return self.args[argIndex][1] |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
264 return None |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
265 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
266 def inline(self, prog, params, output, otype, parent): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
267 if len(params) != len(self.args): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
268 raise Exception('{0} expects {1} arguments, but was called with {2}'.format(self.name, len(self.args), len(params))) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
269 argValues = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
270 if parent: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
271 self.regValues = parent.regValues |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
272 prog.pushScope(self) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
273 i = 0 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
274 for name,size in self.args: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
275 argValues[name] = params[i] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
276 i += 1 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
277 for name in self.locals: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
278 size = self.locals[name] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
279 output.append('\n\tuint{size}_t {sub}_{local};'.format(size=size, sub=self.name, local=name)) |
1721
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
280 self.argValues = argValues |
1704
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
281 self.processOps(prog, argValues, output, otype, self.implementation) |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
282 prog.popScope() |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
283 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
284 def __str__(self): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
285 pieces = [self.name] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
286 for name,size in self.args: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
287 pieces.append('\n\targ {0} {1}'.format(name, size)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
288 for name in self.locals: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
289 pieces.append('\n\tlocal {0} {1}'.format(name, self.locals[name])) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
290 for op in self.implementation: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
291 pieces.append(str(op)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
292 return ''.join(pieces) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
293 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
294 class Op: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
295 def __init__(self, evalFun = None): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
296 self.evalFun = evalFun |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
297 self.impls = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
298 self.outOp = () |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
299 def cBinaryOperator(self, op): |
1704
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
300 def _impl(prog, params, rawParams, flagUpdates): |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
301 if op == '-': |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
302 a = params[1] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
303 b = params[0] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
304 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
305 a = params[0] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
306 b = params[1] |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
307 needsSizeAdjust = False |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
308 if len(params) > 3: |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
309 size = params[3] |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
310 if size == 0: |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
311 size = 8 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
312 elif size == 1: |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
313 size = 16 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
314 else: |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
315 size = 32 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
316 prog.lastSize = size |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
317 destSize = prog.paramSize(rawParams[2]) |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
318 if destSize > size: |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
319 needsSizeAdjust = True |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
320 prog.sizeAdjust = size |
1704
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
321 needsCarry = needsOflow = needsHalf = False |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
322 if flagUpdates: |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
323 for flag in flagUpdates: |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
324 calc = prog.flags.flagCalc[flag] |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
325 if calc == 'carry': |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
326 needsCarry = True |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
327 elif calc == 'half-carry': |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
328 needsHalf = True |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
329 elif calc == 'overflow': |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
330 needsOflow = True |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
331 decl = '' |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
332 if needsCarry or needsOflow or needsHalf or (flagUpdates and needsSizeAdjust): |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
333 if len(params) <= 3: |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
334 size = prog.paramSize(rawParams[2]) |
1723
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
335 if needsCarry and op != 'lsr': |
1704
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
336 size *= 2 |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
337 decl,name = prog.getTemp(size) |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
338 dst = prog.carryFlowDst = name |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
339 prog.lastA = a |
1708
5bfed2eedc9d
Fixed flag calculation for sub instructions in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1707
diff
changeset
|
340 prog.lastB = b |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
341 if size == 64: |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
342 a = '((uint64_t){a})'.format(a=a) |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
343 b = '((uint64_t){b})'.format(b=b) |
1711
87d4f0b4bf1d
Actually correct overflow flag calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1710
diff
changeset
|
344 prog.lastBFlow = b if op == '-' else '(~{b})'.format(b=b) |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
345 elif needsSizeAdjust: |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
346 decl,name = prog.getTemp(size) |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
347 dst = params[2] |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
348 return '{decl}\n\t{tmp} = ({a} & {mask}) {op} ({b} & {mask});\n\t{dst} = ({dst} & ~{mask}) | {tmp};'.format( |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
349 decl = decl, tmp = name, a = a, b = b, op = op, dst = dst, mask = ((1 << size) - 1) |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
350 ) |
1704
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
351 else: |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
352 dst = params[2] |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
353 if needsSizeAdjust: |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
354 return decl + '\n\t{dst} = ({a} & {mask}) {op} ({b} & {mask});'.format( |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
355 dst = dst, a = a, b = b, op = op, mask = (1 << prog.sizeAdjust) - 1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
356 ) |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
357 else: |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
358 return decl + '\n\t{dst} = {a} {op} {b};'.format( |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
359 dst = dst, a = a, b = b, op = op |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
360 ) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
361 self.impls['c'] = _impl |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
362 self.outOp = (2,) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
363 return self |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
364 def cUnaryOperator(self, op): |
1725
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1723
diff
changeset
|
365 def _impl(prog, params, rawParams, flagUpdates): |
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1723
diff
changeset
|
366 dst = params[1] |
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1723
diff
changeset
|
367 decl = '' |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
368 needsSizeAdjust = False |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
369 if len(params) > 2: |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
370 size = params[2] |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
371 if size == 0: |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
372 size = 8 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
373 elif size == 1: |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
374 size = 16 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
375 else: |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
376 size = 32 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
377 prog.lastSize = size |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
378 destSize = prog.paramSize(rawParams[1]) |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
379 if destSize > size: |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
380 needsSizeAdjust = True |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
381 prog.sizeAdjust = size |
1725
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1723
diff
changeset
|
382 if op == '-': |
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1723
diff
changeset
|
383 if flagUpdates: |
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1723
diff
changeset
|
384 for flag in flagUpdates: |
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1723
diff
changeset
|
385 calc = prog.flags.flagCalc[flag] |
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1723
diff
changeset
|
386 if calc == 'carry': |
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1723
diff
changeset
|
387 needsCarry = True |
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1723
diff
changeset
|
388 elif calc == 'half-carry': |
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1723
diff
changeset
|
389 needsHalf = True |
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1723
diff
changeset
|
390 elif calc == 'overflow': |
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1723
diff
changeset
|
391 needsOflow = True |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
392 if needsCarry or needsOflow or needsHalf or (flagUpdates and needsSizeAdjust): |
1725
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1723
diff
changeset
|
393 size = prog.paramSize(rawParams[1]) |
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1723
diff
changeset
|
394 if needsCarry: |
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1723
diff
changeset
|
395 size *= 2 |
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1723
diff
changeset
|
396 decl,name = prog.getTemp(size) |
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1723
diff
changeset
|
397 dst = prog.carryFlowDst = name |
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1723
diff
changeset
|
398 prog.lastA = 0 |
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1723
diff
changeset
|
399 prog.lastB = params[0] |
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1723
diff
changeset
|
400 prog.lastBFlow = params[0] |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
401 if needsSizeAdjust: |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
402 return decl + '\n\t{dst} = ({dst} & ~{mask}) | (({op}{a}) & {mask});'.format( |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
403 dst = dst, a = params[0], op = op, mask = (1 << prog.sizeAdjust) - 1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
404 ) |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
405 else: |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
406 return decl + '\n\t{dst} = {op}{a};'.format( |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
407 dst = dst, a = params[0], op = op |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
408 ) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
409 self.impls['c'] = _impl |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
410 self.outOp = (1,) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
411 return self |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
412 def addImplementation(self, lang, outOp, impl): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
413 self.impls[lang] = impl |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
414 if not outOp is None: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
415 if type(outOp) is tuple: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
416 self.outOp = outOp |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
417 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
418 self.outOp = (outOp,) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
419 return self |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
420 def evaluate(self, params): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
421 return self.evalFun(*params) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
422 def canEval(self): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
423 return not self.evalFun is None |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
424 def numArgs(self): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
425 return self.evalFun.__code__.co_argcount |
1716
04cafe626118
Better error reporting when an instruction is given an insufficient number of parameters
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
426 def numParams(self): |
04cafe626118
Better error reporting when an instruction is given an insufficient number of parameters
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
427 if self.outOp: |
04cafe626118
Better error reporting when an instruction is given an insufficient number of parameters
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
428 params = max(self.outOp) + 1 |
04cafe626118
Better error reporting when an instruction is given an insufficient number of parameters
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
429 else: |
04cafe626118
Better error reporting when an instruction is given an insufficient number of parameters
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
430 params = 0 |
04cafe626118
Better error reporting when an instruction is given an insufficient number of parameters
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
431 if self.evalFun: |
04cafe626118
Better error reporting when an instruction is given an insufficient number of parameters
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
432 params = max(params, self.numArgs()) |
04cafe626118
Better error reporting when an instruction is given an insufficient number of parameters
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
433 return params |
1704
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
434 def generate(self, otype, prog, params, rawParams, flagUpdates): |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
435 if self.impls[otype].__code__.co_argcount == 2: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
436 return self.impls[otype](prog, params) |
1704
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
437 elif self.impls[otype].__code__.co_argcount == 3: |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
438 return self.impls[otype](prog, params, rawParams) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
439 else: |
1704
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
440 return self.impls[otype](prog, params, rawParams, flagUpdates) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
441 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
442 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
443 def _xchgCImpl(prog, params, rawParams): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
444 size = prog.paramSize(rawParams[0]) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
445 decl,name = prog.getTemp(size) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
446 return decl + '\n\t{tmp} = {a};\n\t{a} = {b};\n\t{b} = {tmp};'.format(a = params[0], b = params[1], tmp = name) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
447 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
448 def _dispatchCImpl(prog, params): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
449 if len(params) == 1: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
450 table = 'main' |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
451 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
452 table = params[1] |
1749
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
453 if prog.dispatch == 'call': |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
454 return '\n\timpl_{tbl}[{op}](context, target_cycle);'.format(tbl = table, op = params[0]) |
1749
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
455 elif prog.dispatch == 'goto': |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
456 return '\n\tgoto *impl_{tbl}[{op}];'.format(tbl = table, op = params[0]) |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
457 else: |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
458 raise Exception('Unsupported dispatch type ' + prog.dispatch) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
459 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
460 def _updateFlagsCImpl(prog, params, rawParams): |
1704
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
461 autoUpdate, explicit = prog.flags.parseFlagUpdate(params[0]) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
462 output = [] |
1713
0264d8b288e2
Implement parity flag calculation type
Michael Pavone <pavone@retrodev.com>
parents:
1711
diff
changeset
|
463 parity = None |
1747
89ddf41a50bb
Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1745
diff
changeset
|
464 directFlags = {} |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
465 for flag in autoUpdate: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
466 calc = prog.flags.flagCalc[flag] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
467 calc,_,resultBit = calc.partition('-') |
1704
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
468 if prog.carryFlowDst: |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
469 lastDst = prog.carryFlowDst |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
470 else: |
1734
88fbc4e711fd
Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1733
diff
changeset
|
471 lastDst = prog.resolveParam(prog.lastDst, prog.currentScope, {}) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
472 storage = prog.flags.getStorage(flag) |
1705
9ab64ef5cba0
Initial stab at overflow flag implementation in CPU DSL. Probably broken for subtraction
Michael Pavone <pavone@retrodev.com>
parents:
1704
diff
changeset
|
473 if calc == 'bit' or calc == 'sign' or calc == 'carry' or calc == 'half' or calc == 'overflow': |
1704
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
474 myRes = lastDst |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
475 if calc == 'sign': |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
476 resultBit = prog.getLastSize() - 1 |
1704
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
477 elif calc == 'carry': |
1723
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
478 if prog.lastOp.op in ('asr', 'lsr'): |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
479 resultBit = 0 |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
480 myRes = prog.lastA |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
481 else: |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
482 resultBit = prog.getLastSize() |
1723
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
483 if prog.lastOp.op == 'ror': |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
484 resultBit -= 1 |
1704
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
485 elif calc == 'half': |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
486 resultBit = prog.getLastSize() - 4 |
1708
5bfed2eedc9d
Fixed flag calculation for sub instructions in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1707
diff
changeset
|
487 myRes = '({a} ^ {b} ^ {res})'.format(a = prog.lastA, b = prog.lastB, res = lastDst) |
1705
9ab64ef5cba0
Initial stab at overflow flag implementation in CPU DSL. Probably broken for subtraction
Michael Pavone <pavone@retrodev.com>
parents:
1704
diff
changeset
|
488 elif calc == 'overflow': |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
489 resultBit = prog.getLastSize() - 1 |
1711
87d4f0b4bf1d
Actually correct overflow flag calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1710
diff
changeset
|
490 myRes = '((({a} ^ {b})) & ({a} ^ {res}))'.format(a = prog.lastA, b = prog.lastBFlow, res = lastDst) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
491 else: |
1715
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1713
diff
changeset
|
492 #Note: offsetting this by the operation size - 8 makes sense for the Z80 |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1713
diff
changeset
|
493 #but might not for other CPUs with this kind of fixed bit flag behavior |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
494 resultBit = int(resultBit) + prog.getLastSize() - 8 |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
495 if type(storage) is tuple: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
496 reg,storageBit = storage |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
497 if storageBit == resultBit: |
1747
89ddf41a50bb
Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1745
diff
changeset
|
498 directFlags.setdefault((reg, myRes), []).append(resultBit) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
499 else: |
1747
89ddf41a50bb
Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1745
diff
changeset
|
500 reg = prog.resolveParam(reg, None, {}) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
501 if resultBit > storageBit: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
502 op = '>>' |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
503 shift = resultBit - storageBit |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
504 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
505 op = '<<' |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
506 shift = storageBit - resultBit |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
507 output.append('\n\t{reg} = ({reg} & ~{mask}U) | ({res} {op} {shift}U & {mask}U);'.format( |
1704
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
508 reg = reg, mask = 1 << storageBit, res = myRes, op = op, shift = shift |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
509 )) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
510 else: |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
511 reg = prog.resolveParam(storage, None, {}) |
1715
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1713
diff
changeset
|
512 maxBit = prog.paramSize(storage) - 1 |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1713
diff
changeset
|
513 if resultBit > maxBit: |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1713
diff
changeset
|
514 output.append('\n\t{reg} = {res} >> {shift} & {mask}U;'.format(reg=reg, res=myRes, shift = resultBit - maxBit, mask = 1 << maxBit)) |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1713
diff
changeset
|
515 else: |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1713
diff
changeset
|
516 output.append('\n\t{reg} = {res} & {mask}U;'.format(reg=reg, res=myRes, mask = 1 << resultBit)) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
517 elif calc == 'zero': |
1721
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
518 if prog.carryFlowDst: |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
519 realSize = prog.getLastSize() |
1721
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
520 if realSize != prog.paramSize(prog.carryFlowDst): |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
521 lastDst = '({res} & {mask})'.format(res=lastDst, mask = (1 << realSize) - 1) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
522 if type(storage) is tuple: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
523 reg,storageBit = storage |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
524 reg = prog.resolveParam(reg, None, {}) |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
525 output.append('\n\t{reg} = {res} ? ({reg} & {mask}U) : ({reg} | {bit}U);'.format( |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
526 reg = reg, mask = ~(1 << storageBit), res = lastDst, bit = 1 << storageBit |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
527 )) |
1703
49a52c737bf0
Fix zero flag calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1702
diff
changeset
|
528 else: |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
529 reg = prog.resolveParam(storage, None, {}) |
1703
49a52c737bf0
Fix zero flag calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1702
diff
changeset
|
530 output.append('\n\t{reg} = {res} == 0;'.format( |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
531 reg = reg, res = lastDst |
1705
9ab64ef5cba0
Initial stab at overflow flag implementation in CPU DSL. Probably broken for subtraction
Michael Pavone <pavone@retrodev.com>
parents:
1704
diff
changeset
|
532 )) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
533 elif calc == 'parity': |
1713
0264d8b288e2
Implement parity flag calculation type
Michael Pavone <pavone@retrodev.com>
parents:
1711
diff
changeset
|
534 parity = storage |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
535 paritySize = prog.getLastSize() |
1713
0264d8b288e2
Implement parity flag calculation type
Michael Pavone <pavone@retrodev.com>
parents:
1711
diff
changeset
|
536 if prog.carryFlowDst: |
0264d8b288e2
Implement parity flag calculation type
Michael Pavone <pavone@retrodev.com>
parents:
1711
diff
changeset
|
537 parityDst = paritySrc = prog.carryFlowDst |
0264d8b288e2
Implement parity flag calculation type
Michael Pavone <pavone@retrodev.com>
parents:
1711
diff
changeset
|
538 else: |
0264d8b288e2
Implement parity flag calculation type
Michael Pavone <pavone@retrodev.com>
parents:
1711
diff
changeset
|
539 paritySrc = lastDst |
0264d8b288e2
Implement parity flag calculation type
Michael Pavone <pavone@retrodev.com>
parents:
1711
diff
changeset
|
540 decl,name = prog.getTemp(paritySize) |
0264d8b288e2
Implement parity flag calculation type
Michael Pavone <pavone@retrodev.com>
parents:
1711
diff
changeset
|
541 output.append(decl) |
0264d8b288e2
Implement parity flag calculation type
Michael Pavone <pavone@retrodev.com>
parents:
1711
diff
changeset
|
542 parityDst = name |
1704
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
543 else: |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
544 raise Exception('Unknown flag calc type: ' + calc) |
1747
89ddf41a50bb
Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1745
diff
changeset
|
545 for reg, myRes in directFlags: |
89ddf41a50bb
Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1745
diff
changeset
|
546 bits = directFlags[(reg, myRes)] |
89ddf41a50bb
Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1745
diff
changeset
|
547 resolved = prog.resolveParam(reg, None, {}) |
89ddf41a50bb
Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1745
diff
changeset
|
548 if len(bits) == len(prog.flags.storageToFlags[reg]): |
89ddf41a50bb
Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1745
diff
changeset
|
549 output.append('\n\t{reg} = {res};'.format(reg = resolved, res = myRes)) |
89ddf41a50bb
Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1745
diff
changeset
|
550 else: |
89ddf41a50bb
Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1745
diff
changeset
|
551 mask = 0 |
89ddf41a50bb
Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1745
diff
changeset
|
552 for bit in bits: |
89ddf41a50bb
Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1745
diff
changeset
|
553 mask |= 1 << bit |
89ddf41a50bb
Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1745
diff
changeset
|
554 output.append('\n\t{reg} = ({reg} & ~{mask}U) | ({res} & {mask}U);'.format( |
89ddf41a50bb
Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1745
diff
changeset
|
555 reg = resolved, mask = mask, res = myRes |
89ddf41a50bb
Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1745
diff
changeset
|
556 )) |
1704
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
557 if prog.carryFlowDst: |
1719
fb5ae8c20b85
Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1716
diff
changeset
|
558 if prog.lastOp.op != 'cmp': |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
559 if prog.sizeAdjust: |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
560 output.append('\n\t{dst} = ({dst} & ~{mask}) | ({tmpdst} & {mask});'.format( |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
561 dst = prog.resolveParam(prog.lastDst, prog.currentScope, {}), tmpdst = prog.carryFlowDst, mask = ((1 << prog.sizeAdjust) - 1) |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
562 )) |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
563 prog.sizeAdjust = None |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
564 else: |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
565 output.append('\n\t{dst} = {tmpdst};'.format(dst = prog.resolveParam(prog.lastDst, prog.currentScope, {}), tmpdst = prog.carryFlowDst)) |
1704
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
566 prog.carryFlowDst = None |
1713
0264d8b288e2
Implement parity flag calculation type
Michael Pavone <pavone@retrodev.com>
parents:
1711
diff
changeset
|
567 if parity: |
0264d8b288e2
Implement parity flag calculation type
Michael Pavone <pavone@retrodev.com>
parents:
1711
diff
changeset
|
568 if paritySize > 8: |
0264d8b288e2
Implement parity flag calculation type
Michael Pavone <pavone@retrodev.com>
parents:
1711
diff
changeset
|
569 if paritySize > 16: |
0264d8b288e2
Implement parity flag calculation type
Michael Pavone <pavone@retrodev.com>
parents:
1711
diff
changeset
|
570 output.append('\n\t{dst} = {src} ^ ({src} >> 16);'.format(dst=parityDst, src=paritySrc)) |
0264d8b288e2
Implement parity flag calculation type
Michael Pavone <pavone@retrodev.com>
parents:
1711
diff
changeset
|
571 paritySrc = parityDst |
0264d8b288e2
Implement parity flag calculation type
Michael Pavone <pavone@retrodev.com>
parents:
1711
diff
changeset
|
572 output.append('\n\t{dst} = {src} ^ ({src} >> 8);'.format(dst=parityDst, src=paritySrc)) |
0264d8b288e2
Implement parity flag calculation type
Michael Pavone <pavone@retrodev.com>
parents:
1711
diff
changeset
|
573 paritySrc = parityDst |
0264d8b288e2
Implement parity flag calculation type
Michael Pavone <pavone@retrodev.com>
parents:
1711
diff
changeset
|
574 output.append('\n\t{dst} = ({src} ^ ({src} >> 4)) & 0xF;'.format(dst=parityDst, src=paritySrc)) |
0264d8b288e2
Implement parity flag calculation type
Michael Pavone <pavone@retrodev.com>
parents:
1711
diff
changeset
|
575 if type(parity) is tuple: |
0264d8b288e2
Implement parity flag calculation type
Michael Pavone <pavone@retrodev.com>
parents:
1711
diff
changeset
|
576 reg,bit = parity |
0264d8b288e2
Implement parity flag calculation type
Michael Pavone <pavone@retrodev.com>
parents:
1711
diff
changeset
|
577 reg = prog.resolveParam(reg, None, {}) |
0264d8b288e2
Implement parity flag calculation type
Michael Pavone <pavone@retrodev.com>
parents:
1711
diff
changeset
|
578 output.append('\n\t{flag} = ({flag} & ~{mask}U) | ((0x6996 >> {parity}) << {bit} & {mask}U);'.format( |
0264d8b288e2
Implement parity flag calculation type
Michael Pavone <pavone@retrodev.com>
parents:
1711
diff
changeset
|
579 flag=reg, mask = 1 << bit, bit = bit, parity = parityDst |
0264d8b288e2
Implement parity flag calculation type
Michael Pavone <pavone@retrodev.com>
parents:
1711
diff
changeset
|
580 )) |
0264d8b288e2
Implement parity flag calculation type
Michael Pavone <pavone@retrodev.com>
parents:
1711
diff
changeset
|
581 else: |
0264d8b288e2
Implement parity flag calculation type
Michael Pavone <pavone@retrodev.com>
parents:
1711
diff
changeset
|
582 reg = prog.resolveParam(parity, None, {}) |
0264d8b288e2
Implement parity flag calculation type
Michael Pavone <pavone@retrodev.com>
parents:
1711
diff
changeset
|
583 output.append('\n\t{flag} = 0x9669 >> {parity} & 1;'.format(flag=reg, parity=parityDst)) |
0264d8b288e2
Implement parity flag calculation type
Michael Pavone <pavone@retrodev.com>
parents:
1711
diff
changeset
|
584 |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
585 #TODO: combine explicit flags targeting the same storage location |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
586 for flag in explicit: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
587 location = prog.flags.getStorage(flag) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
588 if type(location) is tuple: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
589 reg,bit = location |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
590 reg = prog.resolveReg(reg, None, {}) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
591 value = str(1 << bit) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
592 if explicit[flag]: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
593 operator = '|=' |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
594 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
595 operator = '&=' |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
596 value = '~' + value |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
597 output.append('\n\t{reg} {op} {val};'.format(reg=reg, op=operator, val=value)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
598 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
599 reg = prog.resolveReg(location, None, {}) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
600 output.append('\n\t{reg} = {val};'.format(reg=reg, val=explicit[flag])) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
601 return ''.join(output) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
602 |
1719
fb5ae8c20b85
Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1716
diff
changeset
|
603 def _cmpCImpl(prog, params, rawParams, flagUpdates): |
fb5ae8c20b85
Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1716
diff
changeset
|
604 size = prog.paramSize(rawParams[1]) |
fb5ae8c20b85
Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1716
diff
changeset
|
605 needsCarry = False |
fb5ae8c20b85
Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1716
diff
changeset
|
606 if flagUpdates: |
fb5ae8c20b85
Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1716
diff
changeset
|
607 for flag in flagUpdates: |
fb5ae8c20b85
Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1716
diff
changeset
|
608 calc = prog.flags.flagCalc[flag] |
fb5ae8c20b85
Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1716
diff
changeset
|
609 if calc == 'carry': |
fb5ae8c20b85
Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1716
diff
changeset
|
610 needsCarry = True |
fb5ae8c20b85
Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1716
diff
changeset
|
611 break |
fb5ae8c20b85
Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1716
diff
changeset
|
612 if needsCarry: |
fb5ae8c20b85
Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1716
diff
changeset
|
613 size *= 2 |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
614 tmpvar = 'cmp_tmp{sz}__'.format(sz=size) |
1745
a8f04b0ab744
Fixes to DAA, SCF and CCF to pass ZEXALL in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1744
diff
changeset
|
615 if flagUpdates: |
a8f04b0ab744
Fixes to DAA, SCF and CCF to pass ZEXALL in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1744
diff
changeset
|
616 prog.carryFlowDst = tmpvar |
a8f04b0ab744
Fixes to DAA, SCF and CCF to pass ZEXALL in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1744
diff
changeset
|
617 prog.lastA = params[1] |
a8f04b0ab744
Fixes to DAA, SCF and CCF to pass ZEXALL in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1744
diff
changeset
|
618 prog.lastB = params[0] |
a8f04b0ab744
Fixes to DAA, SCF and CCF to pass ZEXALL in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1744
diff
changeset
|
619 prog.lastBFlow = params[0] |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
620 scope = prog.getRootScope() |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
621 if not scope.resolveLocal(tmpvar): |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
622 scope.addLocal(tmpvar, size) |
1719
fb5ae8c20b85
Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1716
diff
changeset
|
623 prog.lastDst = rawParams[1] |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
624 if len(params) > 2: |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
625 size = params[2] |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
626 if size == 0: |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
627 size = 8 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
628 elif size == 1: |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
629 size = 16 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
630 else: |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
631 size = 32 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
632 prog.lastSize = size |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
633 else: |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
634 prog.lastSize = None |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
635 return '\n\t{var} = {b} - {a};'.format(var = tmpvar, a = params[0], b = params[1]) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
636 |
1723
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
637 def _asrCImpl(prog, params, rawParams, flagUpdates): |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
638 needsCarry = False |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
639 if flagUpdates: |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
640 for flag in flagUpdates: |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
641 calc = prog.flags.flagCalc[flag] |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
642 if calc == 'carry': |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
643 needsCarry = True |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
644 decl = '' |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
645 size = prog.paramSize(rawParams[2]) |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
646 if needsCarry: |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
647 decl,name = prog.getTemp(size * 2) |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
648 dst = prog.carryFlowDst = name |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
649 prog.lastA = params[0] |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
650 else: |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
651 dst = params[2] |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
652 mask = 1 << (size - 1) |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
653 return decl + '\n\t{dst} = ({a} >> {b}) | ({a} & {mask} ? 0xFFFFFFFFU << ({size} - {b}) : 0);'.format( |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
654 a = params[0], b = params[1], dst = dst, mask = mask, size=size) |
1697
44d8c6e61ad4
Added new sext instruction for sign extension to CPU sdl
Michael Pavone <pavone@retrodev.com>
parents:
1621
diff
changeset
|
655 |
44d8c6e61ad4
Added new sext instruction for sign extension to CPU sdl
Michael Pavone <pavone@retrodev.com>
parents:
1621
diff
changeset
|
656 def _sext(size, src): |
44d8c6e61ad4
Added new sext instruction for sign extension to CPU sdl
Michael Pavone <pavone@retrodev.com>
parents:
1621
diff
changeset
|
657 if size == 16: |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
658 return src | 0xFF00 if src & 0x80 else src & 0x7F |
1697
44d8c6e61ad4
Added new sext instruction for sign extension to CPU sdl
Michael Pavone <pavone@retrodev.com>
parents:
1621
diff
changeset
|
659 else: |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
660 return src | 0xFFFF0000 if src & 0x8000 else src & 0x7FFF |
1697
44d8c6e61ad4
Added new sext instruction for sign extension to CPU sdl
Michael Pavone <pavone@retrodev.com>
parents:
1621
diff
changeset
|
661 |
44d8c6e61ad4
Added new sext instruction for sign extension to CPU sdl
Michael Pavone <pavone@retrodev.com>
parents:
1621
diff
changeset
|
662 def _sextCImpl(prog, params, rawParms): |
44d8c6e61ad4
Added new sext instruction for sign extension to CPU sdl
Michael Pavone <pavone@retrodev.com>
parents:
1621
diff
changeset
|
663 if params[0] == 16: |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
664 fmt = '\n\t{dst} = {src} & 0x80 ? {src} | 0xFF00 : {src} & 0x7F;' |
1697
44d8c6e61ad4
Added new sext instruction for sign extension to CPU sdl
Michael Pavone <pavone@retrodev.com>
parents:
1621
diff
changeset
|
665 else: |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
666 fmt = '\n\t{dst} = {src} & 0x8000 ? {src} | 0xFFFF0000 : {src} & 0x7FFF;' |
1697
44d8c6e61ad4
Added new sext instruction for sign extension to CPU sdl
Michael Pavone <pavone@retrodev.com>
parents:
1621
diff
changeset
|
667 return fmt.format(src=params[1], dst=params[2]) |
1702
73ac2e59fa3f
Implemented sbc instruction in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1701
diff
changeset
|
668 |
73ac2e59fa3f
Implemented sbc instruction in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1701
diff
changeset
|
669 def _getCarryCheck(prog): |
1701
4fd34fde390c
Added adc instruction to CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1700
diff
changeset
|
670 carryFlag = None |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
671 for flag in prog.flags.flagOrder: |
1701
4fd34fde390c
Added adc instruction to CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1700
diff
changeset
|
672 if prog.flags.flagCalc[flag] == 'carry': |
4fd34fde390c
Added adc instruction to CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1700
diff
changeset
|
673 carryFlag = flag |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
674 break |
1701
4fd34fde390c
Added adc instruction to CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1700
diff
changeset
|
675 if carryFlag is None: |
4fd34fde390c
Added adc instruction to CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1700
diff
changeset
|
676 raise Exception('adc requires a defined carry flag') |
4fd34fde390c
Added adc instruction to CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1700
diff
changeset
|
677 carryStorage = prog.flags.getStorage(carryFlag) |
4fd34fde390c
Added adc instruction to CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1700
diff
changeset
|
678 if type(carryStorage) is tuple: |
4fd34fde390c
Added adc instruction to CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1700
diff
changeset
|
679 reg,bit = carryStorage |
4fd34fde390c
Added adc instruction to CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1700
diff
changeset
|
680 reg = prog.resolveReg(reg, None, (), False) |
1702
73ac2e59fa3f
Implemented sbc instruction in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1701
diff
changeset
|
681 return '({reg} & 1 << {bit})'.format(reg=reg, bit=bit) |
1701
4fd34fde390c
Added adc instruction to CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1700
diff
changeset
|
682 else: |
1702
73ac2e59fa3f
Implemented sbc instruction in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1701
diff
changeset
|
683 return prog.resolveReg(carryStorage, None, (), False) |
73ac2e59fa3f
Implemented sbc instruction in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1701
diff
changeset
|
684 |
1709
9c058ea77b7a
Implementation of carry/overflow flags for adc instructions in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1708
diff
changeset
|
685 def _adcCImpl(prog, params, rawParams, flagUpdates): |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
686 needsSizeAdjust = False |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
687 if len(params) > 3: |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
688 size = params[3] |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
689 if size == 0: |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
690 size = 8 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
691 elif size == 1: |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
692 size = 16 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
693 else: |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
694 size = 32 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
695 prog.lastSize = size |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
696 destSize = prog.paramSize(rawParams[2]) |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
697 if destSize > size: |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
698 needsSizeAdjust = True |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
699 prog.sizeAdjust = size |
1709
9c058ea77b7a
Implementation of carry/overflow flags for adc instructions in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1708
diff
changeset
|
700 needsCarry = needsOflow = needsHalf = False |
9c058ea77b7a
Implementation of carry/overflow flags for adc instructions in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1708
diff
changeset
|
701 if flagUpdates: |
9c058ea77b7a
Implementation of carry/overflow flags for adc instructions in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1708
diff
changeset
|
702 for flag in flagUpdates: |
9c058ea77b7a
Implementation of carry/overflow flags for adc instructions in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1708
diff
changeset
|
703 calc = prog.flags.flagCalc[flag] |
9c058ea77b7a
Implementation of carry/overflow flags for adc instructions in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1708
diff
changeset
|
704 if calc == 'carry': |
9c058ea77b7a
Implementation of carry/overflow flags for adc instructions in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1708
diff
changeset
|
705 needsCarry = True |
9c058ea77b7a
Implementation of carry/overflow flags for adc instructions in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1708
diff
changeset
|
706 elif calc == 'half-carry': |
9c058ea77b7a
Implementation of carry/overflow flags for adc instructions in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1708
diff
changeset
|
707 needsHalf = True |
9c058ea77b7a
Implementation of carry/overflow flags for adc instructions in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1708
diff
changeset
|
708 elif calc == 'overflow': |
9c058ea77b7a
Implementation of carry/overflow flags for adc instructions in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1708
diff
changeset
|
709 needsOflow = True |
9c058ea77b7a
Implementation of carry/overflow flags for adc instructions in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1708
diff
changeset
|
710 decl = '' |
9c058ea77b7a
Implementation of carry/overflow flags for adc instructions in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1708
diff
changeset
|
711 carryCheck = _getCarryCheck(prog) |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
712 vals = '1 : 0' |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
713 if needsCarry or needsOflow or needsHalf or (flagUpdates and needsSizeAdjust): |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
714 if len(params) <= 3: |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
715 size = prog.paramSize(rawParams[2]) |
1709
9c058ea77b7a
Implementation of carry/overflow flags for adc instructions in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1708
diff
changeset
|
716 if needsCarry: |
9c058ea77b7a
Implementation of carry/overflow flags for adc instructions in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1708
diff
changeset
|
717 size *= 2 |
9c058ea77b7a
Implementation of carry/overflow flags for adc instructions in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1708
diff
changeset
|
718 decl,name = prog.getTemp(size) |
9c058ea77b7a
Implementation of carry/overflow flags for adc instructions in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1708
diff
changeset
|
719 dst = prog.carryFlowDst = name |
9c058ea77b7a
Implementation of carry/overflow flags for adc instructions in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1708
diff
changeset
|
720 prog.lastA = params[0] |
1744
91aa789e57bd
Fixed half-carry flag calcuation for adc/sbc in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1742
diff
changeset
|
721 prog.lastB = params[1] |
1711
87d4f0b4bf1d
Actually correct overflow flag calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1710
diff
changeset
|
722 prog.lastBFlow = '(~{b})'.format(b=params[1]) |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
723 if size == 64: |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
724 params[0] = '((uint64_t){a})'.format(a=params[0]) |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
725 params[1] = '((uint64_t){b})'.format(b=params[1]) |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
726 vals = '((uint64_t)1) : ((uint64_t)0)' |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
727 elif needsSizeAdjust: |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
728 decl,name = prog.getTemp(size) |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
729 dst = params[2] |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
730 return '{decl}\n\t{tmp} = ({a} & {mask}) + ({b} & {mask}) + ({check} ? 1 : 0);\n\t{dst} = ({dst} & ~{mask}) | {tmp};'.format( |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
731 decl = decl, tmp = name, a = a, b = b, op = op, dst = dst, mask = ((1 << size) - 1), check = carryCheck |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
732 ) |
1709
9c058ea77b7a
Implementation of carry/overflow flags for adc instructions in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1708
diff
changeset
|
733 else: |
9c058ea77b7a
Implementation of carry/overflow flags for adc instructions in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1708
diff
changeset
|
734 dst = params[2] |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
735 return decl + '\n\t{dst} = {a} + {b} + ({check} ? {vals});'.format(dst = dst, |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
736 a = params[0], b = params[1], check = carryCheck, vals = vals |
1702
73ac2e59fa3f
Implemented sbc instruction in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1701
diff
changeset
|
737 ) |
73ac2e59fa3f
Implemented sbc instruction in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1701
diff
changeset
|
738 |
1710
2344b3650b38
Fix sbc and implement carry/overflow flags for it in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1709
diff
changeset
|
739 def _sbcCImpl(prog, params, rawParams, flagUpdates): |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
740 needsSizeAdjust = False |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
741 if len(params) > 3: |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
742 size = params[3] |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
743 if size == 0: |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
744 size = 8 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
745 elif size == 1: |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
746 size = 16 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
747 else: |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
748 size = 32 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
749 prog.lastSize = size |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
750 destSize = prog.paramSize(rawParams[2]) |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
751 if destSize > size: |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
752 needsSizeAdjust = True |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
753 prog.sizeAdjust = size |
1710
2344b3650b38
Fix sbc and implement carry/overflow flags for it in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1709
diff
changeset
|
754 needsCarry = needsOflow = needsHalf = False |
2344b3650b38
Fix sbc and implement carry/overflow flags for it in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1709
diff
changeset
|
755 if flagUpdates: |
2344b3650b38
Fix sbc and implement carry/overflow flags for it in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1709
diff
changeset
|
756 for flag in flagUpdates: |
2344b3650b38
Fix sbc and implement carry/overflow flags for it in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1709
diff
changeset
|
757 calc = prog.flags.flagCalc[flag] |
2344b3650b38
Fix sbc and implement carry/overflow flags for it in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1709
diff
changeset
|
758 if calc == 'carry': |
2344b3650b38
Fix sbc and implement carry/overflow flags for it in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1709
diff
changeset
|
759 needsCarry = True |
2344b3650b38
Fix sbc and implement carry/overflow flags for it in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1709
diff
changeset
|
760 elif calc == 'half-carry': |
2344b3650b38
Fix sbc and implement carry/overflow flags for it in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1709
diff
changeset
|
761 needsHalf = True |
2344b3650b38
Fix sbc and implement carry/overflow flags for it in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1709
diff
changeset
|
762 elif calc == 'overflow': |
2344b3650b38
Fix sbc and implement carry/overflow flags for it in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1709
diff
changeset
|
763 needsOflow = True |
2344b3650b38
Fix sbc and implement carry/overflow flags for it in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1709
diff
changeset
|
764 decl = '' |
2344b3650b38
Fix sbc and implement carry/overflow flags for it in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1709
diff
changeset
|
765 carryCheck = _getCarryCheck(prog) |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
766 vals = '1 : 0' |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
767 if needsCarry or needsOflow or needsHalf or (flagUpdates and needsSizeAdjust): |
1710
2344b3650b38
Fix sbc and implement carry/overflow flags for it in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1709
diff
changeset
|
768 size = prog.paramSize(rawParams[2]) |
2344b3650b38
Fix sbc and implement carry/overflow flags for it in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1709
diff
changeset
|
769 if needsCarry: |
2344b3650b38
Fix sbc and implement carry/overflow flags for it in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1709
diff
changeset
|
770 size *= 2 |
2344b3650b38
Fix sbc and implement carry/overflow flags for it in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1709
diff
changeset
|
771 decl,name = prog.getTemp(size) |
2344b3650b38
Fix sbc and implement carry/overflow flags for it in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1709
diff
changeset
|
772 dst = prog.carryFlowDst = name |
2344b3650b38
Fix sbc and implement carry/overflow flags for it in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1709
diff
changeset
|
773 prog.lastA = params[1] |
1744
91aa789e57bd
Fixed half-carry flag calcuation for adc/sbc in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1742
diff
changeset
|
774 prog.lastB = params[0] |
1711
87d4f0b4bf1d
Actually correct overflow flag calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1710
diff
changeset
|
775 prog.lastBFlow = params[0] |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
776 if size == 64: |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
777 params[1] = '((uint64_t){a})'.format(a=params[1]) |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
778 params[0] = '((uint64_t){b})'.format(b=params[0]) |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
779 vals = '((uint64_t)1) : ((uint64_t)0)' |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
780 elif needsSizeAdjust: |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
781 decl,name = prog.getTemp(size) |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
782 dst = params[2] |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
783 return '{decl}\n\t{tmp} = ({b} & {mask}) - ({a} & {mask}) - ({check} ? 1 : 0);\n\t{dst} = ({dst} & ~{mask}) | {tmp};'.format( |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
784 decl = decl, tmp = name, a = params[0], b = params[1], op = op, dst = dst, mask = ((1 << size) - 1), check = carryCheck |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
785 ) |
1710
2344b3650b38
Fix sbc and implement carry/overflow flags for it in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1709
diff
changeset
|
786 else: |
2344b3650b38
Fix sbc and implement carry/overflow flags for it in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1709
diff
changeset
|
787 dst = params[2] |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
788 return decl + '\n\t{dst} = {b} - {a} - ({check} ? {vals});'.format(dst = dst, |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
789 a = params[0], b = params[1], check=_getCarryCheck(prog), vals = vals |
1702
73ac2e59fa3f
Implemented sbc instruction in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1701
diff
changeset
|
790 ) |
1721
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
791 |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
792 def _rolCImpl(prog, params, rawParams, flagUpdates): |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
793 needsCarry = False |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
794 if flagUpdates: |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
795 for flag in flagUpdates: |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
796 calc = prog.flags.flagCalc[flag] |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
797 if calc == 'carry': |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
798 needsCarry = True |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
799 decl = '' |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
800 size = prog.paramSize(rawParams[2]) |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
801 if needsCarry: |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
802 decl,name = prog.getTemp(size * 2) |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
803 dst = prog.carryFlowDst = name |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
804 else: |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
805 dst = params[2] |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
806 return decl + '\n\t{dst} = {a} << {b} | {a} >> ({size} - {b});'.format(dst = dst, |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
807 a = params[0], b = params[1], size=size |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
808 ) |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
809 |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
810 def _rlcCImpl(prog, params, rawParams, flagUpdates): |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
811 needsCarry = False |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
812 if flagUpdates: |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
813 for flag in flagUpdates: |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
814 calc = prog.flags.flagCalc[flag] |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
815 if calc == 'carry': |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
816 needsCarry = True |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
817 decl = '' |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
818 carryCheck = _getCarryCheck(prog) |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
819 size = prog.paramSize(rawParams[2]) |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
820 if needsCarry: |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
821 decl,name = prog.getTemp(size * 2) |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
822 dst = prog.carryFlowDst = name |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
823 else: |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
824 dst = params[2] |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
825 return decl + '\n\t{dst} = {a} << {b} | {a} >> ({size} + 1 - {b}) | ({check} ? 1 : 0) << ({b} - 1);'.format(dst = dst, |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
826 a = params[0], b = params[1], size=size, check=carryCheck |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
827 ) |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
828 |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
829 def _rorCImpl(prog, params, rawParams, flagUpdates): |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
830 size = prog.paramSize(rawParams[2]) |
1722
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
831 return '\n\t{dst} = {a} >> {b} | {a} << ({size} - {b});'.format(dst = params[2], |
1721
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
832 a = params[0], b = params[1], size=size |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
833 ) |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
834 |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
835 def _rrcCImpl(prog, params, rawParams, flagUpdates): |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
836 needsCarry = False |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
837 if flagUpdates: |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
838 for flag in flagUpdates: |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
839 calc = prog.flags.flagCalc[flag] |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
840 if calc == 'carry': |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
841 needsCarry = True |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
842 decl = '' |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
843 carryCheck = _getCarryCheck(prog) |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
844 size = prog.paramSize(rawParams[2]) |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
845 if needsCarry: |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
846 decl,name = prog.getTemp(size * 2) |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
847 dst = prog.carryFlowDst = name |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
848 else: |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
849 dst = params[2] |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
850 return decl + '\n\t{dst} = {a} >> {b} | {a} << ({size} + 1 - {b}) | ({check} ? 1 : 0) << ({size}-{b});'.format(dst = dst, |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
851 a = params[0], b = params[1], size=size, check=carryCheck |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
852 ) |
1752
d6d4c006a7b3
Initial attempt at interrupts in new Z80 core and integrating it into main executable
Michael Pavone <pavone@retrodev.com>
parents:
1750
diff
changeset
|
853 |
d6d4c006a7b3
Initial attempt at interrupts in new Z80 core and integrating it into main executable
Michael Pavone <pavone@retrodev.com>
parents:
1750
diff
changeset
|
854 def _updateSyncCImpl(prog, params): |
1759
6e4faa10f9ee
Store sync_cycle in context rather than in a local in CPU DSL. Fix the timing of a number of instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1754
diff
changeset
|
855 return '\n\t{sync}(context, target_cycle);'.format(sync=prog.sync_cycle) |
1701
4fd34fde390c
Added adc instruction to CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1700
diff
changeset
|
856 |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
857 _opMap = { |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
858 'mov': Op(lambda val: val).cUnaryOperator(''), |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
859 'not': Op(lambda val: ~val).cUnaryOperator('~'), |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
860 'lnot': Op(lambda val: 0 if val else 1).cUnaryOperator('!'), |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
861 'neg': Op(lambda val: -val).cUnaryOperator('-'), |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
862 'add': Op(lambda a, b: a + b).cBinaryOperator('+'), |
1701
4fd34fde390c
Added adc instruction to CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1700
diff
changeset
|
863 'adc': Op().addImplementation('c', 2, _adcCImpl), |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
864 'sub': Op(lambda a, b: b - a).cBinaryOperator('-'), |
1702
73ac2e59fa3f
Implemented sbc instruction in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1701
diff
changeset
|
865 'sbc': Op().addImplementation('c', 2, _sbcCImpl), |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
866 'lsl': Op(lambda a, b: a << b).cBinaryOperator('<<'), |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
867 'lsr': Op(lambda a, b: a >> b).cBinaryOperator('>>'), |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
868 'asr': Op(lambda a, b: a >> b).addImplementation('c', 2, _asrCImpl), |
1721
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
869 'rol': Op().addImplementation('c', 2, _rolCImpl), |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
870 'rlc': Op().addImplementation('c', 2, _rlcCImpl), |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
871 'ror': Op().addImplementation('c', 2, _rorCImpl), |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
872 'rrc': Op().addImplementation('c', 2, _rrcCImpl), |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
873 'and': Op(lambda a, b: a & b).cBinaryOperator('&'), |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
874 'or': Op(lambda a, b: a | b).cBinaryOperator('|'), |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
875 'xor': Op(lambda a, b: a ^ b).cBinaryOperator('^'), |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
876 'abs': Op(lambda val: abs(val)).addImplementation( |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
877 'c', 1, lambda prog, params: '\n\t{dst} = abs({src});'.format(dst=params[1], src=params[0]) |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
878 ), |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
879 'cmp': Op().addImplementation('c', None, _cmpCImpl), |
1697
44d8c6e61ad4
Added new sext instruction for sign extension to CPU sdl
Michael Pavone <pavone@retrodev.com>
parents:
1621
diff
changeset
|
880 'sext': Op(_sext).addImplementation('c', 2, _sextCImpl), |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
881 'ocall': Op().addImplementation('c', None, lambda prog, params: '\n\t{pre}{fun}({args});'.format( |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
882 pre = prog.prefix, fun = params[0], args = ', '.join(['context'] + [str(p) for p in params[1:]]) |
1759
6e4faa10f9ee
Store sync_cycle in context rather than in a local in CPU DSL. Fix the timing of a number of instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1754
diff
changeset
|
883 )), |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
884 'pcall': Op().addImplementation('c', None, lambda prog, params: '\n\t(({typ}){fun})({args});'.format( |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
885 typ = params[1], fun = params[0], args = ', '.join([str(p) for p in params[2:]]) |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
886 )), |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
887 'cycles': Op().addImplementation('c', None, |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
888 lambda prog, params: '\n\tcontext->cycles += context->opts->gen.clock_divider * {0};'.format( |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
889 params[0] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
890 ) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
891 ), |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
892 'addsize': Op( |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
893 lambda a, b: b + (2 * a if a else 1) |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
894 ).addImplementation('c', 2, lambda prog, params: '\n\t{dst} = {val} + ({sz} ? {sz} * 2 : 1);'.format( |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
895 dst = params[2], sz = params[0], val = params[1] |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
896 )), |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
897 'decsize': Op( |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
898 lambda a, b: b - (2 * a if a else 1) |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
899 ).addImplementation('c', 2, lambda prog, params: '\n\t{dst} = {val} - ({sz} ? {sz} * 2 : 1);'.format( |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
900 dst = params[2], sz = params[0], val = params[1] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
901 )), |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
902 'xchg': Op().addImplementation('c', (0,1), _xchgCImpl), |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
903 'dispatch': Op().addImplementation('c', None, _dispatchCImpl), |
1752
d6d4c006a7b3
Initial attempt at interrupts in new Z80 core and integrating it into main executable
Michael Pavone <pavone@retrodev.com>
parents:
1750
diff
changeset
|
904 'update_flags': Op().addImplementation('c', None, _updateFlagsCImpl), |
d6d4c006a7b3
Initial attempt at interrupts in new Z80 core and integrating it into main executable
Michael Pavone <pavone@retrodev.com>
parents:
1750
diff
changeset
|
905 'update_sync': Op().addImplementation('c', None, _updateSyncCImpl) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
906 } |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
907 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
908 #represents a simple DSL instruction |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
909 class NormalOp: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
910 def __init__(self, parts): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
911 self.op = parts[0] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
912 self.params = parts[1:] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
913 |
1704
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
914 def generate(self, prog, parent, fieldVals, output, otype, flagUpdates): |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
915 procParams = [] |
1737
2207cd2bae14
Fixed some issues involving conditional execution and temporaries/constant folding
Michael Pavone <pavone@retrodev.com>
parents:
1735
diff
changeset
|
916 allParamsConst = flagUpdates is None and not prog.conditional |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
917 opDef = _opMap.get(self.op) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
918 for param in self.params: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
919 isDst = (not opDef is None) and len(procParams) in opDef.outOp |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
920 allowConst = (self.op in prog.subroutines or not isDst) and param in parent.regValues |
1765
7b6831305a6a
Fix calculation for whether coalesceFlags is needed for xchg instruction in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1759
diff
changeset
|
921 if isDst and self.op == 'xchg': |
7b6831305a6a
Fix calculation for whether coalesceFlags is needed for xchg instruction in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1759
diff
changeset
|
922 #xchg uses its regs as both source and destination |
7b6831305a6a
Fix calculation for whether coalesceFlags is needed for xchg instruction in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1759
diff
changeset
|
923 #we need to resolve as both so that disperse/coalesce flag stuff gets done |
7b6831305a6a
Fix calculation for whether coalesceFlags is needed for xchg instruction in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1759
diff
changeset
|
924 prog.resolveParam(param, parent, fieldVals, allowConst, False) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
925 param = prog.resolveParam(param, parent, fieldVals, allowConst, isDst) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
926 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
927 if (not type(param) is int) and len(procParams) != len(self.params) - 1: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
928 allParamsConst = False |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
929 procParams.append(param) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
930 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
931 if self.op == 'meta': |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
932 param,_,index = self.params[1].partition('.') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
933 if index: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
934 index = (parent.resolveLocal(index) or index) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
935 if index in fieldVals: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
936 index = str(fieldVals[index]) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
937 param = param + '.' + index |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
938 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
939 param = parent.resolveLocal(param) or param |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
940 if param in fieldVals: |
1991
7d4df6b74263
Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
1938
diff
changeset
|
941 param = fieldVals[param] |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
942 prog.meta[self.params[0]] = param |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
943 elif self.op == 'dis': |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
944 #TODO: Disassembler |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
945 pass |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
946 elif not opDef is None: |
1716
04cafe626118
Better error reporting when an instruction is given an insufficient number of parameters
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
947 if opDef.numParams() > len(procParams): |
04cafe626118
Better error reporting when an instruction is given an insufficient number of parameters
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
948 raise Exception('Insufficient params for ' + self.op + ' (' + ', '.join(self.params) + ')') |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
949 if opDef.canEval() and allParamsConst: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
950 #do constant folding |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
951 if opDef.numArgs() >= len(procParams): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
952 raise Exception('Insufficient args for ' + self.op + ' (' + ', '.join(self.params) + ')') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
953 dst = self.params[opDef.numArgs()] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
954 result = opDef.evaluate(procParams[:opDef.numArgs()]) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
955 while dst in prog.meta: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
956 dst = prog.meta[dst] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
957 maybeLocal = parent.resolveLocal(dst) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
958 if maybeLocal: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
959 dst = maybeLocal |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
960 parent.regValues[dst] = result |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
961 if prog.isReg(dst): |
1699
93103ad9d7f7
Fix constant propagation to a non-ephemeral destination in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1698
diff
changeset
|
962 shortProc = (procParams[0], procParams[-1]) |
93103ad9d7f7
Fix constant propagation to a non-ephemeral destination in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1698
diff
changeset
|
963 shortParams = (self.params[0], self.params[-1]) |
1704
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
964 output.append(_opMap['mov'].generate(otype, prog, shortProc, shortParams, None)) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
965 else: |
1704
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
966 output.append(opDef.generate(otype, prog, procParams, self.params, flagUpdates)) |
1728
b0e01e64d76d
Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1725
diff
changeset
|
967 for dstIdx in opDef.outOp: |
b0e01e64d76d
Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1725
diff
changeset
|
968 dst = self.params[dstIdx] |
b0e01e64d76d
Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1725
diff
changeset
|
969 while dst in prog.meta: |
b0e01e64d76d
Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1725
diff
changeset
|
970 dst = prog.meta[dst] |
b0e01e64d76d
Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1725
diff
changeset
|
971 if dst in parent.regValues: |
b0e01e64d76d
Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1725
diff
changeset
|
972 del parent.regValues[dst] |
b0e01e64d76d
Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1725
diff
changeset
|
973 |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
974 elif self.op in prog.subroutines: |
1721
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
975 procParams = [] |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
976 for param in self.params: |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
977 begin,sep,end = param.partition('.') |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
978 if sep: |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
979 if end in fieldVals: |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
980 param = begin + '.' + str(fieldVals[end]) |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
981 else: |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
982 if param in fieldVals: |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
983 param = fieldVals[param] |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
984 else: |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
985 maybeLocal = parent.resolveLocal(param) |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
986 if maybeLocal and maybeLocal in parent.regValues: |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
987 param = parent.regValues[maybeLocal] |
1721
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
988 procParams.append(param) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
989 prog.subroutines[self.op].inline(prog, procParams, output, otype, parent) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
990 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
991 output.append('\n\t' + self.op + '(' + ', '.join([str(p) for p in procParams]) + ');') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
992 prog.lastOp = self |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
993 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
994 def __str__(self): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
995 return '\n\t' + self.op + ' ' + ' '.join(self.params) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
996 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
997 #represents a DSL switch construct |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
998 class Switch(ChildBlock): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
999 def __init__(self, parent, param): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1000 self.op = 'switch' |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1001 self.parent = parent |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1002 self.param = param |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1003 self.cases = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1004 self.regValues = None |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1005 self.current_locals = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1006 self.case_locals = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1007 self.current_case = None |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1008 self.default = None |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1009 self.default_locals = None |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1010 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1011 def addOp(self, op): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1012 if op.op == 'case': |
1619
0e8438a4c76f
Clean up warnings from -1 case
Michael Pavone <pavone@retrodev.com>
parents:
1618
diff
changeset
|
1013 val = int(op.params[0], 16) if op.params[0].startswith('0x') else int(op.params[0]) |
0e8438a4c76f
Clean up warnings from -1 case
Michael Pavone <pavone@retrodev.com>
parents:
1618
diff
changeset
|
1014 self.cases[val] = self.current_case = [] |
0e8438a4c76f
Clean up warnings from -1 case
Michael Pavone <pavone@retrodev.com>
parents:
1618
diff
changeset
|
1015 self.case_locals[val] = self.current_locals = {} |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1016 elif op.op == 'default': |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1017 self.default = self.current_case = [] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1018 self.default_locals = self.current_locals = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1019 elif self.current_case == None: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1020 raise ion('Orphan instruction in switch') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1021 elif op.op == 'local': |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1022 name = op.params[0] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1023 size = op.params[1] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1024 self.current_locals[name] = size |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1025 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1026 self.current_case.append(op) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1027 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1028 def resolveLocal(self, name): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1029 if name in self.current_locals: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1030 return name |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1031 return self.parent.resolveLocal(name) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1032 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1033 def addLocal(self, name, size): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1034 self.current_locals[name] = size |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1035 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1036 def localSize(self, name): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1037 if name in self.current_locals: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1038 return self.current_locals[name] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1039 return self.parent.localSize(name) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1040 |
1704
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1041 def generate(self, prog, parent, fieldVals, output, otype, flagUpdates): |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1042 prog.pushScope(self) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1043 param = prog.resolveParam(self.param, parent, fieldVals) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1044 if type(param) is int: |
1614
c9639139aedf
Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents:
1613
diff
changeset
|
1045 self.regValues = self.parent.regValues |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1046 if param in self.cases: |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1047 self.current_locals = self.case_locals[param] |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1048 output.append('\n\t{') |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1049 for local in self.case_locals[param]: |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1050 output.append('\n\tuint{0}_t {1};'.format(self.case_locals[param][local], local)) |
1704
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1051 self.processOps(prog, fieldVals, output, otype, self.cases[param]) |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1052 output.append('\n\t}') |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1053 elif self.default: |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1054 self.current_locals = self.default_locals |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1055 output.append('\n\t{') |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1056 for local in self.default_locals: |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1057 output.append('\n\tuint{0}_t {1};'.format(self.default[local], local)) |
1704
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1058 self.processOps(prog, fieldVals, output, otype, self.default) |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1059 output.append('\n\t}') |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1060 else: |
1737
2207cd2bae14
Fixed some issues involving conditional execution and temporaries/constant folding
Michael Pavone <pavone@retrodev.com>
parents:
1735
diff
changeset
|
1061 oldCond = prog.conditional |
2207cd2bae14
Fixed some issues involving conditional execution and temporaries/constant folding
Michael Pavone <pavone@retrodev.com>
parents:
1735
diff
changeset
|
1062 prog.conditional = True |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1063 output.append('\n\tswitch(' + param + ')') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1064 output.append('\n\t{') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1065 for case in self.cases: |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
1066 #temp = prog.temp.copy() |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1067 self.current_locals = self.case_locals[case] |
1614
c9639139aedf
Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents:
1613
diff
changeset
|
1068 self.regValues = dict(self.parent.regValues) |
1619
0e8438a4c76f
Clean up warnings from -1 case
Michael Pavone <pavone@retrodev.com>
parents:
1618
diff
changeset
|
1069 output.append('\n\tcase {0}U: '.format(case) + '{') |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1070 for local in self.case_locals[case]: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1071 output.append('\n\tuint{0}_t {1};'.format(self.case_locals[case][local], local)) |
1704
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1072 self.processOps(prog, fieldVals, output, otype, self.cases[case]) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1073 output.append('\n\tbreak;') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1074 output.append('\n\t}') |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
1075 #prog.temp = temp |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1076 if self.default: |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
1077 #temp = prog.temp.copy() |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1078 self.current_locals = self.default_locals |
1614
c9639139aedf
Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents:
1613
diff
changeset
|
1079 self.regValues = dict(self.parent.regValues) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1080 output.append('\n\tdefault: {') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1081 for local in self.default_locals: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1082 output.append('\n\tuint{0}_t {1};'.format(self.default_locals[local], local)) |
1704
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1083 self.processOps(prog, fieldVals, output, otype, self.default) |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
1084 #prog.temp = temp |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1085 output.append('\n\t}') |
1737
2207cd2bae14
Fixed some issues involving conditional execution and temporaries/constant folding
Michael Pavone <pavone@retrodev.com>
parents:
1735
diff
changeset
|
1086 prog.conditional = oldCond |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1087 prog.popScope() |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1088 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1089 def __str__(self): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1090 keys = self.cases.keys() |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1091 keys.sort() |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1092 lines = ['\n\tswitch'] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1093 for case in keys: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1094 lines.append('\n\tcase {0}'.format(case)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1095 lines.append(''.join([str(op) for op in self.cases[case]])) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1096 lines.append('\n\tend') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1097 return ''.join(lines) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1098 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1099 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1100 def _geuCImpl(prog, parent, fieldVals, output): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1101 if prog.lastOp.op == 'cmp': |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1102 output.pop() |
1616
8c78543c4783
Fix implementation cmp+condition version of if in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1615
diff
changeset
|
1103 params = [prog.resolveParam(p, parent, fieldVals) for p in prog.lastOp.params] |
8c78543c4783
Fix implementation cmp+condition version of if in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1615
diff
changeset
|
1104 return '\n\tif ({a} >= {b}) '.format(a=params[1], b = params[0]) + '{' |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1105 else: |
1733
1f0a86f5e055
Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1728
diff
changeset
|
1106 raise Exception(">=U not implemented in the general case yet") |
1f0a86f5e055
Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1728
diff
changeset
|
1107 |
1f0a86f5e055
Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1728
diff
changeset
|
1108 def _eqCImpl(prog, parent, fieldVals, output): |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
1109 if prog.lastOp.op == 'cmp': |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
1110 output.pop() |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
1111 params = [prog.resolveParam(p, parent, fieldVals) for p in prog.lastOp.params] |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
1112 return '\n\tif ({a} == {b}) '.format(a=params[1], b = params[0]) + '{' |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
1113 else: |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
1114 return '\n\tif (!{a}) {{'.format(a=prog.resolveParam(prog.lastDst, None, {})) |
1733
1f0a86f5e055
Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1728
diff
changeset
|
1115 |
1f0a86f5e055
Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1728
diff
changeset
|
1116 def _neqCImpl(prog, parent, fieldVals, output): |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
1117 return '\n\tif ({a}) {{'.format(a=prog.resolveParam(prog.lastDst, None, {})) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1118 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1119 _ifCmpImpl = { |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1120 'c': { |
1733
1f0a86f5e055
Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1728
diff
changeset
|
1121 '>=U': _geuCImpl, |
1f0a86f5e055
Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1728
diff
changeset
|
1122 '=': _eqCImpl, |
1f0a86f5e055
Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1728
diff
changeset
|
1123 '!=': _neqCImpl |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1124 } |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1125 } |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1126 #represents a DSL conditional construct |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1127 class If(ChildBlock): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1128 def __init__(self, parent, cond): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1129 self.op = 'if' |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1130 self.parent = parent |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1131 self.cond = cond |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1132 self.body = [] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1133 self.elseBody = [] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1134 self.curBody = self.body |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1135 self.locals = {} |
1614
c9639139aedf
Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents:
1613
diff
changeset
|
1136 self.elseLocals = {} |
c9639139aedf
Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents:
1613
diff
changeset
|
1137 self.curLocals = self.locals |
c9639139aedf
Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents:
1613
diff
changeset
|
1138 self.regValues = None |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1139 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1140 def addOp(self, op): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1141 if op.op in ('case', 'arg'): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1142 raise Exception(self.op + ' is not allows inside an if block') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1143 if op.op == 'local': |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1144 name = op.params[0] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1145 size = op.params[1] |
1737
2207cd2bae14
Fixed some issues involving conditional execution and temporaries/constant folding
Michael Pavone <pavone@retrodev.com>
parents:
1735
diff
changeset
|
1146 self.curLocals[name] = size |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1147 elif op.op == 'else': |
1614
c9639139aedf
Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents:
1613
diff
changeset
|
1148 self.curLocals = self.elseLocals |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1149 self.curBody = self.elseBody |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1150 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1151 self.curBody.append(op) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1152 |
1614
c9639139aedf
Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents:
1613
diff
changeset
|
1153 def localSize(self, name): |
c9639139aedf
Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents:
1613
diff
changeset
|
1154 return self.curLocals.get(name) |
c9639139aedf
Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents:
1613
diff
changeset
|
1155 |
c9639139aedf
Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents:
1613
diff
changeset
|
1156 def resolveLocal(self, name): |
1737
2207cd2bae14
Fixed some issues involving conditional execution and temporaries/constant folding
Michael Pavone <pavone@retrodev.com>
parents:
1735
diff
changeset
|
1157 if name in self.curLocals: |
1614
c9639139aedf
Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents:
1613
diff
changeset
|
1158 return name |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1159 return self.parent.resolveLocal(name) |
1614
c9639139aedf
Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents:
1613
diff
changeset
|
1160 |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1161 def _genTrueBody(self, prog, fieldVals, output, otype): |
1614
c9639139aedf
Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents:
1613
diff
changeset
|
1162 self.curLocals = self.locals |
1737
2207cd2bae14
Fixed some issues involving conditional execution and temporaries/constant folding
Michael Pavone <pavone@retrodev.com>
parents:
1735
diff
changeset
|
1163 subOut = [] |
2207cd2bae14
Fixed some issues involving conditional execution and temporaries/constant folding
Michael Pavone <pavone@retrodev.com>
parents:
1735
diff
changeset
|
1164 self.processOps(prog, fieldVals, subOut, otype, self.body) |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1165 for local in self.locals: |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1166 output.append('\n\tuint{sz}_t {nm};'.format(sz=self.locals[local], nm=local)) |
1737
2207cd2bae14
Fixed some issues involving conditional execution and temporaries/constant folding
Michael Pavone <pavone@retrodev.com>
parents:
1735
diff
changeset
|
1167 output += subOut |
1614
c9639139aedf
Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents:
1613
diff
changeset
|
1168 |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1169 def _genFalseBody(self, prog, fieldVals, output, otype): |
1614
c9639139aedf
Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents:
1613
diff
changeset
|
1170 self.curLocals = self.elseLocals |
1737
2207cd2bae14
Fixed some issues involving conditional execution and temporaries/constant folding
Michael Pavone <pavone@retrodev.com>
parents:
1735
diff
changeset
|
1171 subOut = [] |
2207cd2bae14
Fixed some issues involving conditional execution and temporaries/constant folding
Michael Pavone <pavone@retrodev.com>
parents:
1735
diff
changeset
|
1172 self.processOps(prog, fieldVals, subOut, otype, self.elseBody) |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1173 for local in self.elseLocals: |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1174 output.append('\n\tuint{sz}_t {nm};'.format(sz=self.elseLocals[local], nm=local)) |
1737
2207cd2bae14
Fixed some issues involving conditional execution and temporaries/constant folding
Michael Pavone <pavone@retrodev.com>
parents:
1735
diff
changeset
|
1175 output += subOut |
1614
c9639139aedf
Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents:
1613
diff
changeset
|
1176 |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1177 def _genConstParam(self, param, prog, fieldVals, output, otype): |
1614
c9639139aedf
Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents:
1613
diff
changeset
|
1178 if param: |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1179 self._genTrueBody(prog, fieldVals, output, otype) |
1614
c9639139aedf
Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents:
1613
diff
changeset
|
1180 else: |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1181 self._genFalseBody(prog, fieldVals, output, otype) |
1614
c9639139aedf
Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents:
1613
diff
changeset
|
1182 |
1704
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1183 def generate(self, prog, parent, fieldVals, output, otype, flagUpdates): |
1614
c9639139aedf
Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents:
1613
diff
changeset
|
1184 self.regValues = parent.regValues |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
1185 if self.cond in prog.booleans: |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1186 self._genConstParam(prog.checkBool(self.cond), prog, fieldVals, output, otype) |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
1187 else: |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1188 if self.cond in _ifCmpImpl[otype]: |
1737
2207cd2bae14
Fixed some issues involving conditional execution and temporaries/constant folding
Michael Pavone <pavone@retrodev.com>
parents:
1735
diff
changeset
|
1189 oldCond = prog.conditional |
2207cd2bae14
Fixed some issues involving conditional execution and temporaries/constant folding
Michael Pavone <pavone@retrodev.com>
parents:
1735
diff
changeset
|
1190 prog.conditional = True |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
1191 #temp = prog.temp.copy() |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1192 output.append(_ifCmpImpl[otype][self.cond](prog, parent, fieldVals, output)) |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1193 self._genTrueBody(prog, fieldVals, output, otype) |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
1194 #prog.temp = temp |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1195 if self.elseBody: |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
1196 #temp = prog.temp.copy() |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1197 output.append('\n\t} else {') |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1198 self._genFalseBody(prog, fieldVals, output, otype) |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
1199 #prog.temp = temp |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1200 output.append('\n\t}') |
1737
2207cd2bae14
Fixed some issues involving conditional execution and temporaries/constant folding
Michael Pavone <pavone@retrodev.com>
parents:
1735
diff
changeset
|
1201 prog.conditional = oldCond |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1202 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1203 cond = prog.resolveParam(self.cond, parent, fieldVals) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1204 if type(cond) is int: |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1205 self._genConstParam(cond, prog, fieldVals, output, otype) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1206 else: |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
1207 #temp = prog.temp.copy() |
1614
c9639139aedf
Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents:
1613
diff
changeset
|
1208 output.append('\n\tif ({cond}) '.format(cond=cond) + '{') |
1737
2207cd2bae14
Fixed some issues involving conditional execution and temporaries/constant folding
Michael Pavone <pavone@retrodev.com>
parents:
1735
diff
changeset
|
1209 oldCond = prog.conditional |
2207cd2bae14
Fixed some issues involving conditional execution and temporaries/constant folding
Michael Pavone <pavone@retrodev.com>
parents:
1735
diff
changeset
|
1210 prog.conditional = True |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1211 self._genTrueBody(prog, fieldVals, output, otype) |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
1212 #prog.temp = temp |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1213 if self.elseBody: |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
1214 #temp = prog.temp.copy() |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1215 output.append('\n\t} else {') |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1216 self._genFalseBody(prog, fieldVals, output, otype) |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
1217 #prog.temp = temp |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1218 output.append('\n\t}') |
1737
2207cd2bae14
Fixed some issues involving conditional execution and temporaries/constant folding
Michael Pavone <pavone@retrodev.com>
parents:
1735
diff
changeset
|
1219 prog.conditional = oldCond |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1220 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1221 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1222 def __str__(self): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1223 lines = ['\n\tif'] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1224 for op in self.body: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1225 lines.append(str(op)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1226 lines.append('\n\tend') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1227 return ''.join(lines) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1228 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1229 class Registers: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1230 def __init__(self): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1231 self.regs = {} |
1621
ca158bc091f9
Implement program ROM reads
Michael Pavone <pavone@retrodev.com>
parents:
1620
diff
changeset
|
1232 self.pointers = {} |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1233 self.regArrays = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1234 self.regToArray = {} |
1752
d6d4c006a7b3
Initial attempt at interrupts in new Z80 core and integrating it into main executable
Michael Pavone <pavone@retrodev.com>
parents:
1750
diff
changeset
|
1235 self.addReg('cycles', 32) |
1759
6e4faa10f9ee
Store sync_cycle in context rather than in a local in CPU DSL. Fix the timing of a number of instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1754
diff
changeset
|
1236 self.addReg('sync_cycle', 32) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1237 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1238 def addReg(self, name, size): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1239 self.regs[name] = size |
1621
ca158bc091f9
Implement program ROM reads
Michael Pavone <pavone@retrodev.com>
parents:
1620
diff
changeset
|
1240 |
1750
01236179fc71
Optimization to memory access in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1749
diff
changeset
|
1241 def addPointer(self, name, size, count): |
01236179fc71
Optimization to memory access in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1749
diff
changeset
|
1242 self.pointers[name] = (size, count) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1243 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1244 def addRegArray(self, name, size, regs): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1245 self.regArrays[name] = (size, regs) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1246 idx = 0 |
1615
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
1247 if not type(regs) is int: |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
1248 for reg in regs: |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
1249 self.regs[reg] = size |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
1250 self.regToArray[reg] = (name, idx) |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
1251 idx += 1 |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1252 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1253 def isReg(self, name): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1254 return name in self.regs |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1255 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1256 def isRegArray(self, name): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1257 return name in self.regArrays |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1258 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1259 def isRegArrayMember(self, name): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1260 return name in self.regToArray |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1261 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1262 def arrayMemberParent(self, name): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1263 return self.regToArray[name][0] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1264 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1265 def arrayMemberIndex(self, name): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1266 return self.regToArray[name][1] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1267 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1268 def arrayMemberName(self, array, index): |
1615
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
1269 if type(index) is int and not type(self.regArrays[array][1]) is int: |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1270 return self.regArrays[array][1][index] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1271 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1272 return None |
1615
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
1273 |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
1274 def isNamedArray(self, array): |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
1275 return array in self.regArrays and type(self.regArrays[array][1]) is int |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1276 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1277 def processLine(self, parts): |
1615
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
1278 if len(parts) == 3: |
1750
01236179fc71
Optimization to memory access in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1749
diff
changeset
|
1279 if parts[1].startswith('ptr'): |
01236179fc71
Optimization to memory access in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1749
diff
changeset
|
1280 self.addPointer(parts[0], parts[1][3:], int(parts[2])) |
01236179fc71
Optimization to memory access in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1749
diff
changeset
|
1281 else: |
01236179fc71
Optimization to memory access in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1749
diff
changeset
|
1282 self.addRegArray(parts[0], int(parts[1]), int(parts[2])) |
1615
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
1283 elif len(parts) > 2: |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1284 self.addRegArray(parts[0], int(parts[1]), parts[2:]) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1285 else: |
1621
ca158bc091f9
Implement program ROM reads
Michael Pavone <pavone@retrodev.com>
parents:
1620
diff
changeset
|
1286 if parts[1].startswith('ptr'): |
1750
01236179fc71
Optimization to memory access in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1749
diff
changeset
|
1287 self.addPointer(parts[0], parts[1][3:], 1) |
1621
ca158bc091f9
Implement program ROM reads
Michael Pavone <pavone@retrodev.com>
parents:
1620
diff
changeset
|
1288 else: |
ca158bc091f9
Implement program ROM reads
Michael Pavone <pavone@retrodev.com>
parents:
1620
diff
changeset
|
1289 self.addReg(parts[0], int(parts[1])) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1290 return self |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1291 |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1292 def writeHeader(self, otype, hFile): |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1293 fieldList = [] |
1621
ca158bc091f9
Implement program ROM reads
Michael Pavone <pavone@retrodev.com>
parents:
1620
diff
changeset
|
1294 for pointer in self.pointers: |
1735
ca2336469397
Get new Z80 core running in CPM harness
Michael Pavone <pavone@retrodev.com>
parents:
1734
diff
changeset
|
1295 stars = '*' |
1750
01236179fc71
Optimization to memory access in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1749
diff
changeset
|
1296 ptype, count = self.pointers[pointer] |
1735
ca2336469397
Get new Z80 core running in CPM harness
Michael Pavone <pavone@retrodev.com>
parents:
1734
diff
changeset
|
1297 while ptype.startswith('ptr'): |
ca2336469397
Get new Z80 core running in CPM harness
Michael Pavone <pavone@retrodev.com>
parents:
1734
diff
changeset
|
1298 stars += '*' |
ca2336469397
Get new Z80 core running in CPM harness
Michael Pavone <pavone@retrodev.com>
parents:
1734
diff
changeset
|
1299 ptype = ptype[3:] |
ca2336469397
Get new Z80 core running in CPM harness
Michael Pavone <pavone@retrodev.com>
parents:
1734
diff
changeset
|
1300 if ptype.isdigit(): |
ca2336469397
Get new Z80 core running in CPM harness
Michael Pavone <pavone@retrodev.com>
parents:
1734
diff
changeset
|
1301 ptype = 'uint{sz}_t'.format(sz=ptype) |
1750
01236179fc71
Optimization to memory access in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1749
diff
changeset
|
1302 if count > 1: |
01236179fc71
Optimization to memory access in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1749
diff
changeset
|
1303 arr = '[{n}]'.format(n=count) |
01236179fc71
Optimization to memory access in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1749
diff
changeset
|
1304 else: |
01236179fc71
Optimization to memory access in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1749
diff
changeset
|
1305 arr = '' |
01236179fc71
Optimization to memory access in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1749
diff
changeset
|
1306 hFile.write('\n\t{ptype} {stars}{nm}{arr};'.format(nm=pointer, ptype=ptype, stars=stars, arr=arr)) |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1307 for reg in self.regs: |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1308 if not self.isRegArrayMember(reg): |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1309 fieldList.append((self.regs[reg], 1, reg)) |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1310 for arr in self.regArrays: |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1311 size,regs = self.regArrays[arr] |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1312 if not type(regs) is int: |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1313 regs = len(regs) |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1314 fieldList.append((size, regs, arr)) |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1315 fieldList.sort() |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1316 fieldList.reverse() |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1317 for size, count, name in fieldList: |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1318 if count > 1: |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1319 hFile.write('\n\tuint{sz}_t {nm}[{ct}];'.format(sz=size, nm=name, ct=count)) |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1320 else: |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1321 hFile.write('\n\tuint{sz}_t {nm};'.format(sz=size, nm=name)) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1322 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1323 class Flags: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1324 def __init__(self): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1325 self.flagBits = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1326 self.flagCalc = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1327 self.flagStorage = {} |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
1328 self.flagOrder = [] |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1329 self.flagReg = None |
1747
89ddf41a50bb
Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1745
diff
changeset
|
1330 self.storageToFlags = {} |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1331 self.maxBit = -1 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1332 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1333 def processLine(self, parts): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1334 if parts[0] == 'register': |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1335 self.flagReg = parts[1] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1336 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1337 flag,bit,calc,storage = parts |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1338 bit,_,top = bit.partition('-') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1339 bit = int(bit) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1340 if top: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1341 top = int(bit) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1342 if top > self.maxBit: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1343 self.maxBit = top |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1344 self.flagBits[flag] = (bit,top) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1345 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1346 if bit > self.maxBit: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1347 self.maxBit = bit |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1348 self.flagBits[flag] = bit |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1349 self.flagCalc[flag] = calc |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1350 self.flagStorage[flag] = storage |
1747
89ddf41a50bb
Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1745
diff
changeset
|
1351 storage,_,storebit = storage.partition('.') |
89ddf41a50bb
Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1745
diff
changeset
|
1352 self.storageToFlags.setdefault(storage, []).append((storebit, flag)) |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
1353 self.flagOrder.append(flag) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1354 return self |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1355 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1356 def getStorage(self, flag): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1357 if not flag in self.flagStorage: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1358 raise Exception('Undefined flag ' + flag) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1359 loc,_,bit = self.flagStorage[flag].partition('.') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1360 if bit: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1361 return (loc, int(bit)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1362 else: |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1363 return loc |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1364 |
1704
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1365 def parseFlagUpdate(self, flagString): |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1366 last = '' |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1367 autoUpdate = set() |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1368 explicit = {} |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1369 for c in flagString: |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1370 if c.isdigit(): |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1371 if last.isalpha(): |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1372 num = int(c) |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1373 if num > 1: |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1374 raise Exception(c + ' is not a valid digit for update_flags') |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1375 explicit[last] = num |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1376 last = c |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1377 else: |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1378 raise Exception('Digit must follow flag letter in update_flags') |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1379 else: |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1380 if last.isalpha(): |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1381 autoUpdate.add(last) |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1382 last = c |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1383 if last.isalpha(): |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1384 autoUpdate.add(last) |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1385 return (autoUpdate, explicit) |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1386 |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1387 def disperseFlags(self, prog, otype): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1388 bitToFlag = [None] * (self.maxBit+1) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1389 src = prog.resolveReg(self.flagReg, None, {}) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1390 output = [] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1391 for flag in self.flagBits: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1392 bit = self.flagBits[flag] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1393 if type(bit) is tuple: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1394 bot,top = bit |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1395 mask = ((1 << (top + 1 - bot)) - 1) << bot |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1396 output.append('\n\t{dst} = {src} & mask;'.format( |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1397 dst=prog.resolveReg(self.flagStorage[flag], None, {}), src=src, mask=mask |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1398 )) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1399 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1400 bitToFlag[self.flagBits[flag]] = flag |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1401 multi = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1402 for bit in range(len(bitToFlag)-1,-1,-1): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1403 flag = bitToFlag[bit] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1404 if not flag is None: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1405 field,_,dstbit = self.flagStorage[flag].partition('.') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1406 dst = prog.resolveReg(field, None, {}) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1407 if dstbit: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1408 dstbit = int(dstbit) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1409 multi.setdefault(dst, []).append((dstbit, bit)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1410 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1411 output.append('\n\t{dst} = {src} & {mask};'.format(dst=dst, src=src, mask=(1 << bit))) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1412 for dst in multi: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1413 didClear = False |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1414 direct = [] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1415 for dstbit, bit in multi[dst]: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1416 if dstbit == bit: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1417 direct.append(bit) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1418 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1419 if not didClear: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1420 output.append('\n\t{dst} = 0;'.format(dst=dst)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1421 didClear = True |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1422 if dstbit > bit: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1423 shift = '<<' |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1424 diff = dstbit - bit |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1425 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1426 shift = '>>' |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1427 diff = bit - dstbit |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1428 output.append('\n\t{dst} |= {src} {shift} {diff} & {mask};'.format( |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1429 src=src, dst=dst, shift=shift, diff=diff, mask=(1 << dstbit) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1430 )) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1431 if direct: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1432 if len(direct) == len(multi[dst]): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1433 output.append('\n\t{dst} = {src};'.format(dst=dst, src=src)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1434 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1435 mask = 0 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1436 for bit in direct: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1437 mask = mask | (1 << bit) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1438 output.append('\n\t{dst} = {src} & {mask};'.format(dst=dst, src=src, mask=mask)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1439 return ''.join(output) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1440 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1441 def coalesceFlags(self, prog, otype): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1442 dst = prog.resolveReg(self.flagReg, None, {}) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1443 output = ['\n\t{dst} = 0;'.format(dst=dst)] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1444 bitToFlag = [None] * (self.maxBit+1) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1445 for flag in self.flagBits: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1446 bit = self.flagBits[flag] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1447 if type(bit) is tuple: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1448 bot,_ = bit |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1449 src = prog.resolveReg(self.flagStorage[flag], None, {}) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1450 if bot: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1451 output.append('\n\t{dst} |= {src} << {shift};'.format( |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1452 dst=dst, src = src, shift = bot |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1453 )) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1454 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1455 output.append('\n\t{dst} |= {src};'.format( |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1456 dst=dst, src = src |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1457 )) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1458 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1459 bitToFlag[bit] = flag |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1460 multi = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1461 for bit in range(len(bitToFlag)-1,-1,-1): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1462 flag = bitToFlag[bit] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1463 if not flag is None: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1464 field,_,srcbit = self.flagStorage[flag].partition('.') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1465 src = prog.resolveReg(field, None, {}) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1466 if srcbit: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1467 srcbit = int(srcbit) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1468 multi.setdefault(src, []).append((srcbit,bit)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1469 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1470 output.append('\n\tif ({src}) {{\n\t\t{dst} |= 1 << {bit};\n\t}}'.format( |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1471 dst=dst, src=src, bit=bit |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1472 )) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1473 for src in multi: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1474 direct = 0 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1475 for srcbit, dstbit in multi[src]: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1476 if srcbit == dstbit: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1477 direct = direct | (1 << srcbit) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1478 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1479 output.append('\n\tif ({src} & (1 << {srcbit})) {{\n\t\t{dst} |= 1 << {dstbit};\n\t}}'.format( |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1480 src=src, dst=dst, srcbit=srcbit, dstbit=dstbit |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1481 )) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1482 if direct: |
1698
90272218469c
Fixed missing semicolon in coalesceFlags
Michael Pavone <pavone@retrodev.com>
parents:
1697
diff
changeset
|
1483 output.append('\n\t{dst} |= {src} & {mask};'.format( |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1484 dst=dst, src=src, mask=direct |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1485 )) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1486 return ''.join(output) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1487 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1488 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1489 class Program: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1490 def __init__(self, regs, instructions, subs, info, flags): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1491 self.regs = regs |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1492 self.instructions = instructions |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1493 self.subroutines = subs |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1494 self.meta = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1495 self.booleans = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1496 self.prefix = info.get('prefix', [''])[0] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1497 self.opsize = int(info.get('opcode_size', ['8'])[0]) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1498 self.extra_tables = info.get('extra_tables', []) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1499 self.context_type = self.prefix + 'context' |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1500 self.body = info.get('body', [None])[0] |
1752
d6d4c006a7b3
Initial attempt at interrupts in new Z80 core and integrating it into main executable
Michael Pavone <pavone@retrodev.com>
parents:
1750
diff
changeset
|
1501 self.interrupt = info.get('interrupt', [None])[0] |
d6d4c006a7b3
Initial attempt at interrupts in new Z80 core and integrating it into main executable
Michael Pavone <pavone@retrodev.com>
parents:
1750
diff
changeset
|
1502 self.sync_cycle = info.get('sync_cycle', [None])[0] |
1620
a172f97d873f
Add the ability for a CPU definition to reference arbitrary C includes and use it to add a placeholder definition of svp_read_16
Michael Pavone <pavone@retrodev.com>
parents:
1619
diff
changeset
|
1503 self.includes = info.get('include', []) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1504 self.flags = flags |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1505 self.lastDst = None |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1506 self.scopes = [] |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1507 self.currentScope = None |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1508 self.lastOp = None |
1704
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1509 self.carryFlowDst = None |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1510 self.lastA = None |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1511 self.lastB = None |
1708
5bfed2eedc9d
Fixed flag calculation for sub instructions in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1707
diff
changeset
|
1512 self.lastBFlow = None |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
1513 self.sizeAdjust = None |
1737
2207cd2bae14
Fixed some issues involving conditional execution and temporaries/constant folding
Michael Pavone <pavone@retrodev.com>
parents:
1735
diff
changeset
|
1514 self.conditional = False |
1748
48a43dff4dc0
Added init functions to z80_util.c so new Z80 core is closer to a drop in replacement for the old one
Michael Pavone <pavone@retrodev.com>
parents:
1747
diff
changeset
|
1515 self.declares = [] |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
1516 self.lastSize = None |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1517 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1518 def __str__(self): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1519 pieces = [] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1520 for reg in self.regs: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1521 pieces.append(str(self.regs[reg])) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1522 for name in self.subroutines: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1523 pieces.append('\n'+str(self.subroutines[name])) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1524 for instruction in self.instructions: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1525 pieces.append('\n'+str(instruction)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1526 return ''.join(pieces) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1527 |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1528 def writeHeader(self, otype, header): |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1529 hFile = open(header, 'w') |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1530 macro = header.upper().replace('.', '_') |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1531 hFile.write('#ifndef {0}_'.format(macro)) |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1532 hFile.write('\n#define {0}_'.format(macro)) |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1533 hFile.write('\n#include "backend.h"') |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1534 hFile.write('\n\ntypedef struct {') |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1535 hFile.write('\n\tcpu_options gen;') |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1536 hFile.write('\n}} {0}options;'.format(self.prefix)) |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1537 hFile.write('\n\ntypedef struct {') |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1538 hFile.write('\n\t{0}options *opts;'.format(self.prefix)) |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1539 self.regs.writeHeader(otype, hFile) |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1540 hFile.write('\n}} {0}context;'.format(self.prefix)) |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1541 hFile.write('\n') |
1703
49a52c737bf0
Fix zero flag calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1702
diff
changeset
|
1542 hFile.write('\nvoid {pre}execute({type} *context, uint32_t target_cycle);'.format(pre = self.prefix, type = self.context_type)) |
1748
48a43dff4dc0
Added init functions to z80_util.c so new Z80 core is closer to a drop in replacement for the old one
Michael Pavone <pavone@retrodev.com>
parents:
1747
diff
changeset
|
1543 for decl in self.declares: |
48a43dff4dc0
Added init functions to z80_util.c so new Z80 core is closer to a drop in replacement for the old one
Michael Pavone <pavone@retrodev.com>
parents:
1747
diff
changeset
|
1544 hFile.write('\n' + decl) |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1545 hFile.write('\n#endif //{0}_'.format(macro)) |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1546 hFile.write('\n') |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1547 hFile.close() |
1700
e4b4e21a37fa
Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
1699
diff
changeset
|
1548 |
1749
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1549 def _buildTable(self, otype, table, body, lateBody): |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1550 pieces = [] |
1700
e4b4e21a37fa
Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
1699
diff
changeset
|
1551 opmap = [None] * (1 << self.opsize) |
e4b4e21a37fa
Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
1699
diff
changeset
|
1552 bodymap = {} |
e4b4e21a37fa
Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
1699
diff
changeset
|
1553 if table in self.instructions: |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1554 instructions = self.instructions[table] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1555 instructions.sort() |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1556 for inst in instructions: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1557 for val in inst.allValues(): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1558 if opmap[val] is None: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1559 self.meta = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1560 self.temp = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1561 self.needFlagCoalesce = False |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1562 self.needFlagDisperse = False |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1563 self.lastOp = None |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1564 opmap[val] = inst.generateName(val) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1565 bodymap[val] = inst.generateBody(val, self, otype) |
1700
e4b4e21a37fa
Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
1699
diff
changeset
|
1566 |
1749
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1567 if self.dispatch == 'call': |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1568 pieces.append('\nstatic impl_fun impl_{name}[{sz}] = {{'.format(name = table, sz=len(opmap))) |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1569 for inst in range(0, len(opmap)): |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1570 op = opmap[inst] |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1571 if op is None: |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1572 pieces.append('\n\tunimplemented,') |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1573 else: |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1574 pieces.append('\n\t' + op + ',') |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1575 body.append(bodymap[inst]) |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1576 pieces.append('\n};') |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1577 elif self.dispatch == 'goto': |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1578 body.append('\n\tstatic void *impl_{name}[{sz}] = {{'.format(name = table, sz=len(opmap))) |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1579 for inst in range(0, len(opmap)): |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1580 op = opmap[inst] |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1581 if op is None: |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1582 body.append('\n\t\t&&unimplemented,') |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1583 else: |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1584 body.append('\n\t\t&&' + op + ',') |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1585 lateBody.append(bodymap[inst]) |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1586 body.append('\n\t};') |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1587 else: |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1588 raise Exception("unimplmeneted dispatch type " + self.dispatch) |
1700
e4b4e21a37fa
Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
1699
diff
changeset
|
1589 body.extend(pieces) |
1749
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1590 |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1591 def nextInstruction(self, otype): |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1592 output = [] |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1593 if self.dispatch == 'goto': |
1752
d6d4c006a7b3
Initial attempt at interrupts in new Z80 core and integrating it into main executable
Michael Pavone <pavone@retrodev.com>
parents:
1750
diff
changeset
|
1594 if self.interrupt in self.subroutines: |
1759
6e4faa10f9ee
Store sync_cycle in context rather than in a local in CPU DSL. Fix the timing of a number of instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1754
diff
changeset
|
1595 output.append('\n\tif (context->cycles >= context->sync_cycle) {') |
1749
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1596 output.append('\n\tif (context->cycles >= target_cycle) { return; }') |
1752
d6d4c006a7b3
Initial attempt at interrupts in new Z80 core and integrating it into main executable
Michael Pavone <pavone@retrodev.com>
parents:
1750
diff
changeset
|
1597 if self.interrupt in self.subroutines: |
d6d4c006a7b3
Initial attempt at interrupts in new Z80 core and integrating it into main executable
Michael Pavone <pavone@retrodev.com>
parents:
1750
diff
changeset
|
1598 self.meta = {} |
d6d4c006a7b3
Initial attempt at interrupts in new Z80 core and integrating it into main executable
Michael Pavone <pavone@retrodev.com>
parents:
1750
diff
changeset
|
1599 self.temp = {} |
d6d4c006a7b3
Initial attempt at interrupts in new Z80 core and integrating it into main executable
Michael Pavone <pavone@retrodev.com>
parents:
1750
diff
changeset
|
1600 self.subroutines[self.interrupt].inline(self, [], output, otype, None) |
d6d4c006a7b3
Initial attempt at interrupts in new Z80 core and integrating it into main executable
Michael Pavone <pavone@retrodev.com>
parents:
1750
diff
changeset
|
1601 output.append('\n\t}') |
d6d4c006a7b3
Initial attempt at interrupts in new Z80 core and integrating it into main executable
Michael Pavone <pavone@retrodev.com>
parents:
1750
diff
changeset
|
1602 |
1749
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1603 self.meta = {} |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1604 self.temp = {} |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1605 self.subroutines[self.body].inline(self, [], output, otype, None) |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1606 return output |
1700
e4b4e21a37fa
Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
1699
diff
changeset
|
1607 |
e4b4e21a37fa
Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
1699
diff
changeset
|
1608 def build(self, otype): |
e4b4e21a37fa
Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
1699
diff
changeset
|
1609 body = [] |
e4b4e21a37fa
Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
1699
diff
changeset
|
1610 pieces = [] |
e4b4e21a37fa
Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
1699
diff
changeset
|
1611 for include in self.includes: |
e4b4e21a37fa
Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
1699
diff
changeset
|
1612 body.append('#include "{0}"\n'.format(include)) |
1749
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1613 if self.dispatch == 'call': |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
1614 body.append('\nstatic void unimplemented({pre}context *context, uint32_t target_cycle)'.format(pre = self.prefix)) |
1749
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1615 body.append('\n{') |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1616 body.append('\n\tfatal_error("Unimplemented instruction\\n");') |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1617 body.append('\n}\n') |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
1618 body.append('\ntypedef void (*impl_fun)({pre}context *context, uint32_t target_cycle);'.format(pre=self.prefix)) |
1749
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1619 for table in self.extra_tables: |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1620 body.append('\nstatic impl_fun impl_{name}[{sz}];'.format(name = table, sz=(1 << self.opsize))) |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1621 body.append('\nstatic impl_fun impl_main[{sz}];'.format(sz=(1 << self.opsize))) |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1622 elif self.dispatch == 'goto': |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1623 body.append('\nvoid {pre}execute({type} *context, uint32_t target_cycle)'.format(pre = self.prefix, type = self.context_type)) |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1624 body.append('\n{') |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1625 |
1740
28ab56ff8cea
Implement DD/FD prefixes for instructions that don't reference HL
Michael Pavone <pavone@retrodev.com>
parents:
1737
diff
changeset
|
1626 for table in self.extra_tables: |
1749
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1627 self._buildTable(otype, table, body, pieces) |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1628 self._buildTable(otype, 'main', body, pieces) |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1629 if self.dispatch == 'call' and self.body in self.subroutines: |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1630 pieces.append('\nvoid {pre}execute({type} *context, uint32_t target_cycle)'.format(pre = self.prefix, type = self.context_type)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1631 pieces.append('\n{') |
1759
6e4faa10f9ee
Store sync_cycle in context rather than in a local in CPU DSL. Fix the timing of a number of instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1754
diff
changeset
|
1632 pieces.append('\n\t{sync}(context, target_cycle);'.format(sync=self.sync_cycle)) |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1633 pieces.append('\n\twhile (context->cycles < target_cycle)') |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1634 pieces.append('\n\t{') |
1883
9ab5184811ea
Implement interrupts in call dispatch mode in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1838
diff
changeset
|
1635 if self.interrupt in self.subroutines: |
9ab5184811ea
Implement interrupts in call dispatch mode in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1838
diff
changeset
|
1636 pieces.append('\n\t\tif (context->cycles >= context->sync_cycle) {') |
9ab5184811ea
Implement interrupts in call dispatch mode in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1838
diff
changeset
|
1637 self.meta = {} |
9ab5184811ea
Implement interrupts in call dispatch mode in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1838
diff
changeset
|
1638 self.temp = {} |
1938
1dae90605199
Fix autogenerated temp variables in interrupt subroutine in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1883
diff
changeset
|
1639 intpieces = [] |
1dae90605199
Fix autogenerated temp variables in interrupt subroutine in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1883
diff
changeset
|
1640 self.subroutines[self.interrupt].inline(self, [], intpieces, otype, None) |
1dae90605199
Fix autogenerated temp variables in interrupt subroutine in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1883
diff
changeset
|
1641 for size in self.temp: |
1dae90605199
Fix autogenerated temp variables in interrupt subroutine in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1883
diff
changeset
|
1642 pieces.append('\n\tuint{sz}_t gen_tmp{sz}__;'.format(sz=size)) |
1dae90605199
Fix autogenerated temp variables in interrupt subroutine in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1883
diff
changeset
|
1643 pieces += intpieces |
1883
9ab5184811ea
Implement interrupts in call dispatch mode in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1838
diff
changeset
|
1644 pieces.append('\n\t\t}') |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1645 self.meta = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1646 self.temp = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1647 self.subroutines[self.body].inline(self, [], pieces, otype, None) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1648 pieces.append('\n\t}') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1649 pieces.append('\n}') |
1749
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1650 elif self.dispatch == 'goto': |
1759
6e4faa10f9ee
Store sync_cycle in context rather than in a local in CPU DSL. Fix the timing of a number of instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1754
diff
changeset
|
1651 body.append('\n\t{sync}(context, target_cycle);'.format(sync=self.sync_cycle)) |
1749
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1652 body += self.nextInstruction(otype) |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1653 pieces.append('\nunimplemented:') |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1654 pieces.append('\n\tfatal_error("Unimplemented instruction\\n");') |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1655 pieces.append('\n}') |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1656 return ''.join(body) + ''.join(pieces) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1657 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1658 def checkBool(self, name): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1659 if not name in self.booleans: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1660 raise Exception(name + ' is not a defined boolean flag') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1661 return self.booleans[name] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1662 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1663 def getTemp(self, size): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1664 if size in self.temp: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1665 return ('', self.temp[size]) |
1742
6290c88949bd
Fixed CPI/CPD/CPIR/CPDR in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1740
diff
changeset
|
1666 self.temp[size] = 'gen_tmp{sz}__'.format(sz=size); |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
1667 return ('', self.temp[size]) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1668 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1669 def resolveParam(self, param, parent, fieldVals, allowConstant=True, isdst=False): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1670 keepGoing = True |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1671 while keepGoing: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1672 keepGoing = False |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1673 try: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1674 if type(param) is int: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1675 pass |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1676 elif param.startswith('0x'): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1677 param = int(param, 16) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1678 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1679 param = int(param) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1680 except ValueError: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1681 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1682 if parent: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1683 if param in parent.regValues and allowConstant: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1684 return parent.regValues[param] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1685 maybeLocal = parent.resolveLocal(param) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1686 if maybeLocal: |
1715
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1713
diff
changeset
|
1687 if isdst: |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1713
diff
changeset
|
1688 self.lastDst = param |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
1689 self.lastSize = None |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1690 return maybeLocal |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1691 if param in fieldVals: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1692 param = fieldVals[param] |
1721
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1693 fieldVals = {} |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1694 keepGoing = True |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1695 elif param in self.meta: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1696 param = self.meta[param] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1697 keepGoing = True |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1698 elif self.isReg(param): |
1715
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1713
diff
changeset
|
1699 return self.resolveReg(param, parent, fieldVals, isdst) |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
1700 elif param in self.regs.pointers: |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
1701 return 'context->' + param |
1715
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1713
diff
changeset
|
1702 if isdst: |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1713
diff
changeset
|
1703 self.lastDst = param |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
1704 self.lastSize = None |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1705 return param |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1706 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1707 def isReg(self, name): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1708 if not type(name) is str: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1709 return False |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1710 begin,sep,_ = name.partition('.') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1711 if sep: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1712 if begin in self.meta: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1713 begin = self.meta[begin] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1714 return self.regs.isRegArray(begin) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1715 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1716 return self.regs.isReg(name) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1717 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1718 def resolveReg(self, name, parent, fieldVals, isDst=False): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1719 begin,sep,end = name.partition('.') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1720 if sep: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1721 if begin in self.meta: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1722 begin = self.meta[begin] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1723 if not self.regs.isRegArrayMember(end): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1724 end = self.resolveParam(end, parent, fieldVals) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1725 if not type(end) is int and self.regs.isRegArrayMember(end): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1726 arrayName = self.regs.arrayMemberParent(end) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1727 end = self.regs.arrayMemberIndex(end) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1728 if arrayName != begin: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1729 end = 'context->{0}[{1}]'.format(arrayName, end) |
1615
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
1730 if self.regs.isNamedArray(begin): |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
1731 regName = self.regs.arrayMemberName(begin, end) |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
1732 else: |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
1733 regName = '{0}.{1}'.format(begin, end) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1734 ret = 'context->{0}[{1}]'.format(begin, end) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1735 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1736 regName = name |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1737 if self.regs.isRegArrayMember(name): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1738 arr,idx = self.regs.regToArray[name] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1739 ret = 'context->{0}[{1}]'.format(arr, idx) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1740 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1741 ret = 'context->' + name |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1742 if regName == self.flags.flagReg: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1743 if isDst: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1744 self.needFlagDisperse = True |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1745 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1746 self.needFlagCoalesce = True |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1747 if isDst: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1748 self.lastDst = regName |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1749 return ret |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1750 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1751 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1752 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1753 def paramSize(self, name): |
1715
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1713
diff
changeset
|
1754 if name in self.meta: |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1713
diff
changeset
|
1755 return self.paramSize(self.meta[name]) |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1713
diff
changeset
|
1756 for i in range(len(self.scopes) -1, -1, -1): |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1713
diff
changeset
|
1757 size = self.scopes[i].localSize(name) |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1713
diff
changeset
|
1758 if size: |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1713
diff
changeset
|
1759 return size |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1760 begin,sep,_ = name.partition('.') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1761 if sep and self.regs.isRegArray(begin): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1762 return self.regs.regArrays[begin][0] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1763 if self.regs.isReg(name): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1764 return self.regs.regs[name] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1765 return 32 |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1766 |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
1767 def getLastSize(self): |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
1768 if self.lastSize: |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
1769 return self.lastSize |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
1770 return self.paramSize(self.lastDst) |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1765
diff
changeset
|
1771 |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1772 def pushScope(self, scope): |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1773 self.scopes.append(scope) |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1774 self.currentScope = scope |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1775 |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1776 def popScope(self): |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1777 ret = self.scopes.pop() |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1778 self.currentScope = self.scopes[-1] if self.scopes else None |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1779 return ret |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1780 |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1781 def getRootScope(self): |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1782 return self.scopes[0] |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1783 |
1749
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1784 def parse(args): |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1785 f = args.source |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1786 instructions = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1787 subroutines = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1788 registers = None |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1789 flags = None |
1748
48a43dff4dc0
Added init functions to z80_util.c so new Z80 core is closer to a drop in replacement for the old one
Michael Pavone <pavone@retrodev.com>
parents:
1747
diff
changeset
|
1790 declares = [] |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1791 errors = [] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1792 info = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1793 line_num = 0 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1794 cur_object = None |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1795 for line in f: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1796 line_num += 1 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1797 line,_,comment = line.partition('#') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1798 if not line.strip(): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1799 continue |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1800 if line[0].isspace(): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1801 if not cur_object is None: |
1754
043cf458704c
Basic support for string operands in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1753
diff
changeset
|
1802 sep = True |
043cf458704c
Basic support for string operands in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1753
diff
changeset
|
1803 parts = [] |
043cf458704c
Basic support for string operands in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1753
diff
changeset
|
1804 while sep: |
043cf458704c
Basic support for string operands in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1753
diff
changeset
|
1805 before,sep,after = line.partition('"') |
043cf458704c
Basic support for string operands in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1753
diff
changeset
|
1806 before = before.strip() |
043cf458704c
Basic support for string operands in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1753
diff
changeset
|
1807 if before: |
2440
338c78da3fff
Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents:
1991
diff
changeset
|
1808 parts += [el.strip() for el in before.split(' ') if el.strip()] |
1754
043cf458704c
Basic support for string operands in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1753
diff
changeset
|
1809 if sep: |
043cf458704c
Basic support for string operands in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1753
diff
changeset
|
1810 #TODO: deal with escaped quotes |
043cf458704c
Basic support for string operands in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1753
diff
changeset
|
1811 inside,sep,after = after.partition('"') |
043cf458704c
Basic support for string operands in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1753
diff
changeset
|
1812 parts.append('"' + inside + '"') |
043cf458704c
Basic support for string operands in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1753
diff
changeset
|
1813 line = after |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1814 if type(cur_object) is dict: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1815 cur_object[parts[0]] = parts[1:] |
1748
48a43dff4dc0
Added init functions to z80_util.c so new Z80 core is closer to a drop in replacement for the old one
Michael Pavone <pavone@retrodev.com>
parents:
1747
diff
changeset
|
1816 elif type(cur_object) is list: |
1754
043cf458704c
Basic support for string operands in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1753
diff
changeset
|
1817 cur_object.append(' '.join(parts)) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1818 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1819 cur_object = cur_object.processLine(parts) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1820 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1821 # if type(cur_object) is Registers: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1822 # if len(parts) > 2: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1823 # cur_object.addRegArray(parts[0], int(parts[1]), parts[2:]) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1824 # else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1825 # cur_object.addReg(parts[0], int(parts[1])) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1826 # elif type(cur_object) is dict: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1827 # cur_object[parts[0]] = parts[1:] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1828 # elif parts[0] == 'switch': |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1829 # o = Switch(cur_object, parts[1]) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1830 # cur_object.addOp(o) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1831 # cur_object = o |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1832 # elif parts[0] == 'if': |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1833 # o = If(cur_object, parts[1]) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1834 # cur_object.addOp(o) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1835 # cur_object = o |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1836 # elif parts[0] == 'end': |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1837 # cur_object = cur_object.parent |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1838 # else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1839 # cur_object.addOp(NormalOp(parts)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1840 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1841 errors.append("Orphan instruction on line {0}".format(line_num)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1842 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1843 parts = line.split(' ') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1844 if len(parts) > 1: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1845 if len(parts) > 2: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1846 table,bitpattern,name = parts |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1847 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1848 bitpattern,name = parts |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1849 table = 'main' |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1850 value = 0 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1851 fields = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1852 curbit = len(bitpattern) - 1 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1853 for char in bitpattern: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1854 value <<= 1 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1855 if char in ('0', '1'): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1856 value |= int(char) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1857 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1858 if char in fields: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1859 fields[char] = (curbit, fields[char][1] + 1) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1860 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1861 fields[char] = (curbit, 1) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1862 curbit -= 1 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1863 cur_object = Instruction(value, fields, name.strip()) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1864 instructions.setdefault(table, []).append(cur_object) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1865 elif line.strip() == 'regs': |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1866 if registers is None: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1867 registers = Registers() |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1868 cur_object = registers |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1869 elif line.strip() == 'info': |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1870 cur_object = info |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1871 elif line.strip() == 'flags': |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1872 if flags is None: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1873 flags = Flags() |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1874 cur_object = flags |
1748
48a43dff4dc0
Added init functions to z80_util.c so new Z80 core is closer to a drop in replacement for the old one
Michael Pavone <pavone@retrodev.com>
parents:
1747
diff
changeset
|
1875 elif line.strip() == 'declare': |
48a43dff4dc0
Added init functions to z80_util.c so new Z80 core is closer to a drop in replacement for the old one
Michael Pavone <pavone@retrodev.com>
parents:
1747
diff
changeset
|
1876 cur_object = declares |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1877 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1878 cur_object = SubRoutine(line.strip()) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1879 subroutines[cur_object.name] = cur_object |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1880 if errors: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1881 print(errors) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1882 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1883 p = Program(registers, instructions, subroutines, info, flags) |
1749
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1884 p.dispatch = args.dispatch |
1748
48a43dff4dc0
Added init functions to z80_util.c so new Z80 core is closer to a drop in replacement for the old one
Michael Pavone <pavone@retrodev.com>
parents:
1747
diff
changeset
|
1885 p.declares = declares |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1886 p.booleans['dynarec'] = False |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1887 p.booleans['interp'] = True |
1749
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1888 if args.define: |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1889 for define in args.define: |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1890 name,sep,val = define.partition('=') |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1891 name = name.strip() |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1892 val = val.strip() |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1893 if sep: |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1894 p.booleans[name] = bool(val) |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1895 else: |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1896 p.booleans[name] = True |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1897 |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1898 if 'header' in info: |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1899 print('#include "{0}"'.format(info['header'][0])) |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1900 p.writeHeader('c', info['header'][0]) |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1901 print('#include "util.h"') |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1902 print('#include <stdlib.h>') |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1903 print(p.build('c')) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1904 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1905 def main(argv): |
1749
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1906 from argparse import ArgumentParser, FileType |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1907 argParser = ArgumentParser(description='CPU emulator DSL compiler') |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1908 argParser.add_argument('source', type=FileType('r')) |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1909 argParser.add_argument('-D', '--define', action='append') |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1910 argParser.add_argument('-d', '--dispatch', choices=('call', 'switch', 'goto'), default='call') |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1911 parse(argParser.parse_args(argv[1:])) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1912 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1913 if __name__ == '__main__': |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1914 from sys import argv |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1915 main(argv) |