Mercurial > repos > blastem
annotate cpu_dsl.py @ 1715:4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
author | Michael Pavone <pavone@retrodev.com> |
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date | Tue, 29 Jan 2019 23:56:48 -0800 |
parents | 0264d8b288e2 |
children | 04cafe626118 |
rev | line source |
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1 #!/usr/bin/env python3 |
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2 |
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3 |
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4 class Block: |
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5 def addOp(self, op): |
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6 pass |
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7 |
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8 def processLine(self, parts): |
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9 if parts[0] == 'switch': |
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10 o = Switch(self, parts[1]) |
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11 self.addOp(o) |
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12 return o |
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13 elif parts[0] == 'if': |
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14 o = If(self, parts[1]) |
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15 self.addOp(o) |
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16 return o |
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17 elif parts[0] == 'end': |
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18 raise Exception('end is only allowed inside a switch or if block') |
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19 else: |
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20 self.addOp(NormalOp(parts)) |
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21 return self |
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22 |
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23 def processOps(self, prog, fieldVals, output, otype, oplist): |
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24 for i in range(0, len(oplist)): |
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25 if i + 1 < len(oplist) and oplist[i+1].op == 'update_flags': |
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26 flagUpdates, _ = prog.flags.parseFlagUpdate(oplist[i+1].params[0]) |
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27 else: |
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28 flagUpdates = None |
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29 oplist[i].generate(prog, self, fieldVals, output, otype, flagUpdates) |
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30 |
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31 def resolveLocal(self, name): |
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32 return None |
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33 |
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34 class ChildBlock(Block): |
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35 def processLine(self, parts): |
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36 if parts[0] == 'end': |
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37 return self.parent |
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38 return super().processLine(parts) |
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39 |
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40 #Represents an instruction of the emulated CPU |
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41 class Instruction(Block): |
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42 def __init__(self, value, fields, name): |
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43 self.value = value |
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44 self.fields = fields |
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45 self.name = name |
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46 self.implementation = [] |
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47 self.locals = {} |
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48 self.regValues = {} |
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49 self.varyingBits = 0 |
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50 self.invalidFieldValues = {} |
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51 self.newLocals = [] |
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52 for field in fields: |
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53 self.varyingBits += fields[field][1] |
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54 |
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55 def addOp(self, op): |
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56 if op.op == 'local': |
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57 name = op.params[0] |
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58 size = int(op.params[1]) |
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59 self.locals[name] = size |
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60 elif op.op == 'invalid': |
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61 name = op.params[0] |
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62 value = int(op.params[1]) |
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63 self.invalidFieldValues.setdefault(name, set()).add(value) |
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64 else: |
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65 self.implementation.append(op) |
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66 |
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67 def resolveLocal(self, name): |
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68 if name in self.locals: |
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69 return name |
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70 return None |
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71 |
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72 def addLocal(self, name, size): |
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73 self.locals[name] = size |
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74 self.newLocals.append(name) |
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75 |
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76 def localSize(self, name): |
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77 return self.locals.get(name) |
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78 |
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79 def __lt__(self, other): |
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80 if isinstance(other, Instruction): |
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81 if self.varyingBits != other.varyingBits: |
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82 return self.varyingBits < other.varyingBits |
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83 return self.value < other.value |
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84 else: |
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85 return NotImplemented |
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86 |
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87 def allValues(self): |
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88 values = [] |
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89 for i in range(0, 1 << self.varyingBits): |
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90 iword = self.value |
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91 doIt = True |
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92 for field in self.fields: |
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93 shift,bits = self.fields[field] |
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94 val = i & ((1 << bits) - 1) |
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95 if field in self.invalidFieldValues and val in self.invalidFieldValues[field]: |
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96 doIt = False |
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97 break |
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98 i >>= bits |
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99 iword |= val << shift |
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100 if doIt: |
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101 values.append(iword) |
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102 return values |
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103 |
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104 def getFieldVals(self, value): |
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105 fieldVals = {} |
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106 fieldBits = {} |
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107 for field in self.fields: |
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108 shift,bits = self.fields[field] |
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109 val = (value >> shift) & ((1 << bits) - 1) |
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110 fieldVals[field] = val |
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111 fieldBits[field] = bits |
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112 return (fieldVals, fieldBits) |
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113 |
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114 def generateName(self, value): |
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115 fieldVals,fieldBits = self.getFieldVals(value) |
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116 names = list(fieldVals.keys()) |
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117 names.sort() |
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118 funName = self.name |
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119 for name in names: |
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120 funName += '_{0}_{1:0>{2}}'.format(name, bin(fieldVals[name])[2:], fieldBits[name]) |
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121 return funName |
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122 |
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123 def generateBody(self, value, prog, otype): |
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124 output = [] |
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125 prog.meta = {} |
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126 prog.pushScope(self) |
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127 self.regValues = {} |
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128 for var in self.locals: |
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129 output.append('\n\tuint{sz}_t {name};'.format(sz=self.locals[var], name=var)) |
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130 self.newLocals = [] |
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131 fieldVals,_ = self.getFieldVals(value) |
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132 self.processOps(prog, fieldVals, output, otype, self.implementation) |
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133 begin = '\nvoid ' + self.generateName(value) + '(' + prog.context_type + ' *context)\n{' |
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134 if prog.needFlagCoalesce: |
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135 begin += prog.flags.coalesceFlags(prog, otype) |
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136 if prog.needFlagDisperse: |
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137 output.append(prog.flags.disperseFlags(prog, otype)) |
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138 for var in self.newLocals: |
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139 begin += '\n\tuint{sz}_t {name};'.format(sz=self.locals[var], name=var) |
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140 prog.popScope() |
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141 return begin + ''.join(output) + '\n}' |
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142 |
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143 def __str__(self): |
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144 pieces = [self.name + ' ' + hex(self.value) + ' ' + str(self.fields)] |
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145 for name in self.locals: |
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146 pieces.append('\n\tlocal {0} {1}'.format(name, self.locals[name])) |
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147 for op in self.implementation: |
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148 pieces.append(str(op)) |
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149 return ''.join(pieces) |
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150 |
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151 #Represents the definition of a helper function |
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152 class SubRoutine(Block): |
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153 def __init__(self, name): |
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154 self.name = name |
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155 self.implementation = [] |
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156 self.args = [] |
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157 self.arg_map = {} |
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158 self.locals = {} |
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159 self.regValues = {} |
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160 |
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161 def addOp(self, op): |
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162 if op.op == 'arg': |
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163 name = op.params[0] |
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164 size = op.params[1] |
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165 self.arg_map[name] = len(self.args) |
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166 self.args.append((name, size)) |
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167 elif op.op == 'local': |
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168 name = op.params[0] |
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169 size = op.params[1] |
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170 self.locals[name] = size |
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171 else: |
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172 self.implementation.append(op) |
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173 |
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174 def resolveLocal(self, name): |
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175 if name in self.locals: |
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176 return self.name + '_' + name |
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177 return None |
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178 |
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179 def addLocal(self, name, size): |
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180 self.locals[name] = size |
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181 |
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182 def localSize(self, name): |
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183 return self.locals.get(name) |
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184 |
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185 def inline(self, prog, params, output, otype, parent): |
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186 if len(params) != len(self.args): |
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187 raise Exception('{0} expects {1} arguments, but was called with {2}'.format(self.name, len(self.args), len(params))) |
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188 argValues = {} |
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189 if parent: |
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190 self.regValues = parent.regValues |
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191 prog.pushScope(self) |
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192 i = 0 |
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193 for name,size in self.args: |
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194 argValues[name] = params[i] |
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195 i += 1 |
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196 for name in self.locals: |
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197 size = self.locals[name] |
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198 output.append('\n\tuint{size}_t {sub}_{local};'.format(size=size, sub=self.name, local=name)) |
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199 self.processOps(prog, argValues, output, otype, self.implementation) |
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200 prog.popScope() |
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201 |
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202 def __str__(self): |
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203 pieces = [self.name] |
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204 for name,size in self.args: |
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205 pieces.append('\n\targ {0} {1}'.format(name, size)) |
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206 for name in self.locals: |
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207 pieces.append('\n\tlocal {0} {1}'.format(name, self.locals[name])) |
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208 for op in self.implementation: |
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209 pieces.append(str(op)) |
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210 return ''.join(pieces) |
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211 |
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212 class Op: |
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213 def __init__(self, evalFun = None): |
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214 self.evalFun = evalFun |
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215 self.impls = {} |
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216 self.outOp = () |
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217 def cBinaryOperator(self, op): |
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218 def _impl(prog, params, rawParams, flagUpdates): |
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219 if op == '-': |
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220 a = params[1] |
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221 b = params[0] |
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222 else: |
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223 a = params[0] |
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224 b = params[1] |
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225 needsCarry = needsOflow = needsHalf = False |
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226 if flagUpdates: |
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227 for flag in flagUpdates: |
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228 calc = prog.flags.flagCalc[flag] |
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229 if calc == 'carry': |
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230 needsCarry = True |
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231 elif calc == 'half-carry': |
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232 needsHalf = True |
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233 elif calc == 'overflow': |
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234 needsOflow = True |
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235 decl = '' |
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236 if needsCarry or needsOflow or needsHalf: |
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237 size = prog.paramSize(rawParams[2]) |
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238 if needsCarry: |
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239 size *= 2 |
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240 decl,name = prog.getTemp(size) |
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241 dst = prog.carryFlowDst = name |
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242 prog.lastA = a |
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243 prog.lastB = b |
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244 prog.lastBFlow = b if op == '-' else '(~{b})'.format(b=b) |
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245 else: |
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246 dst = params[2] |
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247 return decl + '\n\t{dst} = {a} {op} {b};'.format( |
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248 dst = dst, a = a, b = b, op = op |
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249 ) |
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250 self.impls['c'] = _impl |
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251 self.outOp = (2,) |
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252 return self |
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253 def cUnaryOperator(self, op): |
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254 def _impl(prog, params): |
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255 return '\n\t{dst} = {op}{a};'.format( |
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256 dst = params[1], a = params[0], op = op |
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257 ) |
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258 self.impls['c'] = _impl |
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259 self.outOp = (1,) |
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260 return self |
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261 def addImplementation(self, lang, outOp, impl): |
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262 self.impls[lang] = impl |
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263 if not outOp is None: |
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264 if type(outOp) is tuple: |
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265 self.outOp = outOp |
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266 else: |
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267 self.outOp = (outOp,) |
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268 return self |
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269 def evaluate(self, params): |
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270 return self.evalFun(*params) |
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271 def canEval(self): |
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272 return not self.evalFun is None |
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273 def numArgs(self): |
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274 return self.evalFun.__code__.co_argcount |
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275 def generate(self, otype, prog, params, rawParams, flagUpdates): |
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276 if self.impls[otype].__code__.co_argcount == 2: |
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277 return self.impls[otype](prog, params) |
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278 elif self.impls[otype].__code__.co_argcount == 3: |
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279 return self.impls[otype](prog, params, rawParams) |
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280 else: |
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281 return self.impls[otype](prog, params, rawParams, flagUpdates) |
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282 |
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283 |
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284 def _xchgCImpl(prog, params, rawParams): |
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285 size = prog.paramSize(rawParams[0]) |
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286 decl,name = prog.getTemp(size) |
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287 return decl + '\n\t{tmp} = {a};\n\t{a} = {b};\n\t{b} = {tmp};'.format(a = params[0], b = params[1], tmp = name) |
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288 |
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289 def _dispatchCImpl(prog, params): |
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290 if len(params) == 1: |
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291 table = 'main' |
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292 else: |
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293 table = params[1] |
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294 return '\n\timpl_{tbl}[{op}](context);'.format(tbl = table, op = params[0]) |
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295 |
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296 def _updateFlagsCImpl(prog, params, rawParams): |
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297 autoUpdate, explicit = prog.flags.parseFlagUpdate(params[0]) |
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298 output = [] |
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299 parity = None |
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300 for flag in autoUpdate: |
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301 calc = prog.flags.flagCalc[flag] |
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302 calc,_,resultBit = calc.partition('-') |
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303 if prog.carryFlowDst: |
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304 lastDst = prog.carryFlowDst |
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305 else: |
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306 lastDst = prog.resolveParam(prog.lastDst, None, {}) |
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307 storage = prog.flags.getStorage(flag) |
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308 if calc == 'bit' or calc == 'sign' or calc == 'carry' or calc == 'half' or calc == 'overflow': |
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309 myRes = lastDst |
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310 if calc == 'sign': |
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311 resultBit = prog.paramSize(prog.lastDst) - 1 |
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312 elif calc == 'carry': |
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313 resultBit = prog.paramSize(prog.lastDst) |
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314 elif calc == 'half': |
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315 resultBit = prog.paramSize(prog.lastDst) - 4 |
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316 myRes = '({a} ^ {b} ^ {res})'.format(a = prog.lastA, b = prog.lastB, res = lastDst) |
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317 elif calc == 'overflow': |
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318 resultBit = prog.paramSize(prog.lastDst) - 1 |
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319 myRes = '((({a} ^ {b})) & ({a} ^ {res}))'.format(a = prog.lastA, b = prog.lastBFlow, res = lastDst) |
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320 else: |
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321 #Note: offsetting this by the operation size - 8 makes sense for the Z80 |
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322 #but might not for other CPUs with this kind of fixed bit flag behavior |
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323 resultBit = int(resultBit) + prog.paramSize(prog.lastDst) - 8 |
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324 if type(storage) is tuple: |
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325 reg,storageBit = storage |
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326 reg = prog.resolveParam(reg, None, {}) |
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327 if storageBit == resultBit: |
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328 #TODO: optimize this case |
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329 output.append('\n\t{reg} = ({reg} & ~{mask}U) | ({res} & {mask}U);'.format( |
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330 reg = reg, mask = 1 << resultBit, res = myRes |
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331 )) |
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332 else: |
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333 if resultBit > storageBit: |
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334 op = '>>' |
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335 shift = resultBit - storageBit |
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336 else: |
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337 op = '<<' |
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338 shift = storageBit - resultBit |
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339 output.append('\n\t{reg} = ({reg} & ~{mask}U) | ({res} {op} {shift}U & {mask}U);'.format( |
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340 reg = reg, mask = 1 << storageBit, res = myRes, op = op, shift = shift |
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341 )) |
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342 else: |
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343 reg = prog.resolveParam(storage, None, {}) |
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344 maxBit = prog.paramSize(storage) - 1 |
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345 if resultBit > maxBit: |
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346 output.append('\n\t{reg} = {res} >> {shift} & {mask}U;'.format(reg=reg, res=myRes, shift = resultBit - maxBit, mask = 1 << maxBit)) |
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347 else: |
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348 output.append('\n\t{reg} = {res} & {mask}U;'.format(reg=reg, res=myRes, mask = 1 << resultBit)) |
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349 elif calc == 'zero': |
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350 if type(storage) is tuple: |
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351 reg,storageBit = storage |
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352 reg = prog.resolveParam(reg, None, {}) |
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353 output.append('\n\t{reg} = {res} ? ({reg} & {mask}U) : ({reg} | {bit}U);'.format( |
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354 reg = reg, mask = ~(1 << storageBit), res = lastDst, bit = 1 << storageBit |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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355 )) |
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356 else: |
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357 reg = prog.resolveParam(storage, None, {}) |
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358 output.append('\n\t{reg} = {res} == 0;'.format( |
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359 reg = reg, res = lastDst |
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360 )) |
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361 elif calc == 'parity': |
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362 parity = storage |
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363 paritySize = prog.paramSize(prog.lastDst) |
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364 if prog.carryFlowDst: |
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365 parityDst = paritySrc = prog.carryFlowDst |
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366 else: |
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367 paritySrc = lastDst |
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368 decl,name = prog.getTemp(paritySize) |
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369 output.append(decl) |
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370 parityDst = name |
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371 else: |
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372 raise Exception('Unknown flag calc type: ' + calc) |
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373 if prog.carryFlowDst: |
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374 output.append('\n\t{dst} = {tmpdst};'.format(dst = prog.resolveParam(prog.lastDst, None, {}), tmpdst = prog.carryFlowDst)) |
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375 prog.carryFlowDst = None |
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376 if parity: |
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377 if paritySize > 8: |
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378 if paritySize > 16: |
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379 output.append('\n\t{dst} = {src} ^ ({src} >> 16);'.format(dst=parityDst, src=paritySrc)) |
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380 paritySrc = parityDst |
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381 output.append('\n\t{dst} = {src} ^ ({src} >> 8);'.format(dst=parityDst, src=paritySrc)) |
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382 paritySrc = parityDst |
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383 output.append('\n\t{dst} = ({src} ^ ({src} >> 4)) & 0xF;'.format(dst=parityDst, src=paritySrc)) |
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384 if type(parity) is tuple: |
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385 reg,bit = parity |
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386 reg = prog.resolveParam(reg, None, {}) |
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387 output.append('\n\t{flag} = ({flag} & ~{mask}U) | ((0x6996 >> {parity}) << {bit} & {mask}U);'.format( |
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388 flag=reg, mask = 1 << bit, bit = bit, parity = parityDst |
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389 )) |
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390 else: |
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391 reg = prog.resolveParam(parity, None, {}) |
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392 output.append('\n\t{flag} = 0x9669 >> {parity} & 1;'.format(flag=reg, parity=parityDst)) |
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393 |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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394 #TODO: combine explicit flags targeting the same storage location |
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395 for flag in explicit: |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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396 location = prog.flags.getStorage(flag) |
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397 if type(location) is tuple: |
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|
398 reg,bit = location |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
399 reg = prog.resolveReg(reg, None, {}) |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
400 value = str(1 << bit) |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
401 if explicit[flag]: |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
402 operator = '|=' |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
403 else: |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
404 operator = '&=' |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
405 value = '~' + value |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
406 output.append('\n\t{reg} {op} {val};'.format(reg=reg, op=operator, val=value)) |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
407 else: |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
408 reg = prog.resolveReg(location, None, {}) |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
409 output.append('\n\t{reg} = {val};'.format(reg=reg, val=explicit[flag])) |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
410 return ''.join(output) |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
411 |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
412 def _cmpCImpl(prog, params): |
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|
413 size = prog.paramSize(params[1]) |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
414 tmpvar = 'cmp_tmp{sz}__'.format(sz=size) |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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changeset
|
415 typename = '' |
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changeset
|
416 scope = prog.getRootScope() |
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|
417 if not scope.resolveLocal(tmpvar): |
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|
418 scope.addLocal(tmpvar, size) |
1613
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
419 prog.lastDst = tmpvar |
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|
420 return '\n\t{var} = {b} - {a};'.format(var = tmpvar, a = params[0], b = params[1]) |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
421 |
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changeset
|
422 def _asrCImpl(prog, params, rawParams): |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
423 shiftSize = prog.paramSize(rawParams[0]) |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
424 mask = 1 << (shiftSize - 1) |
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|
425 return '\n\t{dst} = ({a} >> {b}) | ({a} & {mask});'.format(a = params[0], b = params[1], dst = params[2], mask = mask) |
1697
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Added new sext instruction for sign extension to CPU sdl
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|
426 |
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|
427 def _sext(size, src): |
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|
428 if size == 16: |
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|
429 return src | 0xFF00 if src & 0x80 else src |
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Added new sext instruction for sign extension to CPU sdl
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|
430 else: |
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Added new sext instruction for sign extension to CPU sdl
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|
431 return src | 0xFFFF0000 if src & 0x8000 else src |
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Added new sext instruction for sign extension to CPU sdl
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|
432 |
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|
433 def _sextCImpl(prog, params, rawParms): |
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|
434 if params[0] == 16: |
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|
435 fmt = '\n\t{dst} = {src} & 0x80 ? {src} | 0xFF00 : {src};' |
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|
436 else: |
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|
437 fmt = '\n\t{dst} = {src} & 0x8000 ? {src} | 0xFFFF0000 : {src};' |
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|
438 return fmt.format(src=params[1], dst=params[2]) |
1702
73ac2e59fa3f
Implemented sbc instruction in CPU DSL
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1701
diff
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|
439 |
73ac2e59fa3f
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440 def _getCarryCheck(prog): |
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441 carryFlag = None |
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442 for flag in prog.flags.flagCalc: |
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443 if prog.flags.flagCalc[flag] == 'carry': |
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444 carryFlag = flag |
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445 if carryFlag is None: |
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446 raise Exception('adc requires a defined carry flag') |
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447 carryStorage = prog.flags.getStorage(carryFlag) |
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448 if type(carryStorage) is tuple: |
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449 reg,bit = carryStorage |
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450 reg = prog.resolveReg(reg, None, (), False) |
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451 return '({reg} & 1 << {bit})'.format(reg=reg, bit=bit) |
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452 else: |
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453 return prog.resolveReg(carryStorage, None, (), False) |
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454 |
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455 def _adcCImpl(prog, params, rawParams, flagUpdates): |
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456 needsCarry = needsOflow = needsHalf = False |
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457 if flagUpdates: |
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458 for flag in flagUpdates: |
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459 calc = prog.flags.flagCalc[flag] |
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460 if calc == 'carry': |
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461 needsCarry = True |
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462 elif calc == 'half-carry': |
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463 needsHalf = True |
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464 elif calc == 'overflow': |
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465 needsOflow = True |
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466 decl = '' |
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467 carryCheck = _getCarryCheck(prog) |
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468 if needsCarry or needsOflow or needsHalf: |
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469 size = prog.paramSize(rawParams[2]) |
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470 if needsCarry: |
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471 size *= 2 |
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472 decl,name = prog.getTemp(size) |
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473 dst = prog.carryFlowDst = name |
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474 prog.lastA = params[0] |
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475 prog.lastB = '({b} + ({check} ? 1 : 0))'.format(b = params[1], check = carryCheck) |
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476 prog.lastBFlow = '(~{b})'.format(b=params[1]) |
1709
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477 else: |
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478 dst = params[2] |
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479 return decl + '\n\t{dst} = {a} + {b} + ({check} ? 1 : 0);'.format(dst = dst, |
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480 a = params[0], b = params[1], check = carryCheck |
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481 ) |
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|
482 |
1710
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483 def _sbcCImpl(prog, params, rawParams, flagUpdates): |
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|
484 needsCarry = needsOflow = needsHalf = False |
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485 if flagUpdates: |
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486 for flag in flagUpdates: |
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|
487 calc = prog.flags.flagCalc[flag] |
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488 if calc == 'carry': |
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489 needsCarry = True |
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490 elif calc == 'half-carry': |
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491 needsHalf = True |
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492 elif calc == 'overflow': |
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493 needsOflow = True |
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|
494 decl = '' |
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|
495 carryCheck = _getCarryCheck(prog) |
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|
496 if needsCarry or needsOflow or needsHalf: |
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497 size = prog.paramSize(rawParams[2]) |
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|
498 if needsCarry: |
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|
499 size *= 2 |
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|
500 decl,name = prog.getTemp(size) |
2344b3650b38
Fix sbc and implement carry/overflow flags for it in CPU DSL
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diff
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|
501 dst = prog.carryFlowDst = name |
2344b3650b38
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|
502 prog.lastA = params[1] |
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Fix sbc and implement carry/overflow flags for it in CPU DSL
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1709
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|
503 prog.lastB = '({b} ^ ({check} ? 1 : 0))'.format(b = params[0], check = carryCheck) |
1711
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Actually correct overflow flag calculation in CPU DSL
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parents:
1710
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changeset
|
504 prog.lastBFlow = params[0] |
1710
2344b3650b38
Fix sbc and implement carry/overflow flags for it in CPU DSL
Michael Pavone <pavone@retrodev.com>
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1709
diff
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|
505 else: |
2344b3650b38
Fix sbc and implement carry/overflow flags for it in CPU DSL
Michael Pavone <pavone@retrodev.com>
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1709
diff
changeset
|
506 dst = params[2] |
2344b3650b38
Fix sbc and implement carry/overflow flags for it in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1709
diff
changeset
|
507 return decl + '\n\t{dst} = {b} - {a} - ({check} ? 1 : 0);'.format(dst = dst, |
1702
73ac2e59fa3f
Implemented sbc instruction in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1701
diff
changeset
|
508 a = params[0], b = params[1], check=_getCarryCheck(prog) |
73ac2e59fa3f
Implemented sbc instruction in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1701
diff
changeset
|
509 ) |
1701
4fd34fde390c
Added adc instruction to CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1700
diff
changeset
|
510 |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
diff
changeset
|
511 _opMap = { |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
512 'mov': Op(lambda val: val).cUnaryOperator(''), |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
diff
changeset
|
513 'not': Op(lambda val: ~val).cUnaryOperator('~'), |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
514 'lnot': Op(lambda val: 0 if val else 1).cUnaryOperator('!'), |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
515 'neg': Op(lambda val: -val).cUnaryOperator('-'), |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
516 'add': Op(lambda a, b: a + b).cBinaryOperator('+'), |
1701
4fd34fde390c
Added adc instruction to CPU DSL
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parents:
1700
diff
changeset
|
517 'adc': Op().addImplementation('c', 2, _adcCImpl), |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
518 'sub': Op(lambda a, b: b - a).cBinaryOperator('-'), |
1702
73ac2e59fa3f
Implemented sbc instruction in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1701
diff
changeset
|
519 'sbc': Op().addImplementation('c', 2, _sbcCImpl), |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
520 'lsl': Op(lambda a, b: a << b).cBinaryOperator('<<'), |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
diff
changeset
|
521 'lsr': Op(lambda a, b: a >> b).cBinaryOperator('>>'), |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
522 'asr': Op(lambda a, b: a >> b).addImplementation('c', 2, _asrCImpl), |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
523 'and': Op(lambda a, b: a & b).cBinaryOperator('&'), |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
524 'or': Op(lambda a, b: a | b).cBinaryOperator('|'), |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
525 'xor': Op(lambda a, b: a ^ b).cBinaryOperator('^'), |
1618
5dbc453cd345
Getting SVP core closer to compiling
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parents:
1616
diff
changeset
|
526 'abs': Op(lambda val: abs(val)).addImplementation( |
5dbc453cd345
Getting SVP core closer to compiling
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parents:
1616
diff
changeset
|
527 'c', 1, lambda prog, params: '\n\t{dst} = abs({src});'.format(dst=params[1], src=params[0]) |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
528 ), |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
529 'cmp': Op().addImplementation('c', None, _cmpCImpl), |
1697
44d8c6e61ad4
Added new sext instruction for sign extension to CPU sdl
Michael Pavone <pavone@retrodev.com>
parents:
1621
diff
changeset
|
530 'sext': Op(_sext).addImplementation('c', 2, _sextCImpl), |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
531 'ocall': Op().addImplementation('c', None, lambda prog, params: '\n\t{pre}{fun}({args});'.format( |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
532 pre = prog.prefix, fun = params[0], args = ', '.join(['context'] + [str(p) for p in params[1:]]) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
533 )), |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
534 'cycles': Op().addImplementation('c', None, |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
535 lambda prog, params: '\n\tcontext->cycles += context->opts->gen.clock_divider * {0};'.format( |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
536 params[0] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
537 ) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
538 ), |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
539 'addsize': Op( |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
540 lambda a, b: b + (2 * a if a else 1) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
541 ).addImplementation('c', 2, lambda prog, params: '\n\t{dst} = {val} + {sz} ? {sz} * 2 : 1;'.format( |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
542 dst = params[2], sz = params[0], val = params[1] |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
543 )), |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
544 'decsize': Op( |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
545 lambda a, b: b - (2 * a if a else 1) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
546 ).addImplementation('c', 2, lambda prog, params: '\n\t{dst} = {val} - {sz} ? {sz} * 2 : 1;'.format( |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
547 dst = params[2], sz = params[0], val = params[1] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
548 )), |
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549 'xchg': Op().addImplementation('c', (0,1), _xchgCImpl), |
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550 'dispatch': Op().addImplementation('c', None, _dispatchCImpl), |
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551 'update_flags': Op().addImplementation('c', None, _updateFlagsCImpl) |
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552 } |
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553 |
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554 #represents a simple DSL instruction |
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555 class NormalOp: |
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556 def __init__(self, parts): |
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557 self.op = parts[0] |
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558 self.params = parts[1:] |
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559 |
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560 def generate(self, prog, parent, fieldVals, output, otype, flagUpdates): |
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561 procParams = [] |
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562 allParamsConst = flagUpdates is None |
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563 opDef = _opMap.get(self.op) |
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564 for param in self.params: |
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565 allowConst = (self.op in prog.subroutines or len(procParams) != len(self.params) - 1) and param in parent.regValues |
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566 isDst = (not opDef is None) and len(procParams) in opDef.outOp |
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567 param = prog.resolveParam(param, parent, fieldVals, allowConst, isDst) |
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568 |
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569 if (not type(param) is int) and len(procParams) != len(self.params) - 1: |
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570 allParamsConst = False |
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571 procParams.append(param) |
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572 |
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573 if self.op == 'meta': |
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574 param,_,index = self.params[1].partition('.') |
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575 if index: |
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576 index = (parent.resolveLocal(index) or index) |
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577 if index in fieldVals: |
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578 index = str(fieldVals[index]) |
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579 param = param + '.' + index |
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580 else: |
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581 param = parent.resolveLocal(param) or param |
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582 if param in fieldVals: |
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583 param = fieldVals[index] |
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584 prog.meta[self.params[0]] = param |
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585 elif self.op == 'dis': |
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586 #TODO: Disassembler |
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587 pass |
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588 elif not opDef is None: |
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589 if opDef.canEval() and allParamsConst: |
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590 #do constant folding |
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591 if opDef.numArgs() >= len(procParams): |
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592 raise Exception('Insufficient args for ' + self.op + ' (' + ', '.join(self.params) + ')') |
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593 dst = self.params[opDef.numArgs()] |
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594 result = opDef.evaluate(procParams[:opDef.numArgs()]) |
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595 while dst in prog.meta: |
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596 dst = prog.meta[dst] |
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597 maybeLocal = parent.resolveLocal(dst) |
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598 if maybeLocal: |
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599 dst = maybeLocal |
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600 parent.regValues[dst] = result |
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601 if prog.isReg(dst): |
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602 shortProc = (procParams[0], procParams[-1]) |
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603 shortParams = (self.params[0], self.params[-1]) |
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604 output.append(_opMap['mov'].generate(otype, prog, shortProc, shortParams, None)) |
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605 else: |
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606 output.append(opDef.generate(otype, prog, procParams, self.params, flagUpdates)) |
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607 elif self.op in prog.subroutines: |
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608 prog.subroutines[self.op].inline(prog, procParams, output, otype, parent) |
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609 else: |
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610 output.append('\n\t' + self.op + '(' + ', '.join([str(p) for p in procParams]) + ');') |
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611 prog.lastOp = self |
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612 |
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613 def __str__(self): |
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614 return '\n\t' + self.op + ' ' + ' '.join(self.params) |
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615 |
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616 #represents a DSL switch construct |
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617 class Switch(ChildBlock): |
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618 def __init__(self, parent, param): |
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619 self.op = 'switch' |
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620 self.parent = parent |
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621 self.param = param |
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622 self.cases = {} |
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623 self.regValues = None |
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624 self.current_locals = {} |
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625 self.case_locals = {} |
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626 self.current_case = None |
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627 self.default = None |
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628 self.default_locals = None |
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629 |
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630 def addOp(self, op): |
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631 if op.op == 'case': |
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632 val = int(op.params[0], 16) if op.params[0].startswith('0x') else int(op.params[0]) |
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633 self.cases[val] = self.current_case = [] |
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634 self.case_locals[val] = self.current_locals = {} |
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635 elif op.op == 'default': |
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636 self.default = self.current_case = [] |
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637 self.default_locals = self.current_locals = {} |
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638 elif self.current_case == None: |
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639 raise ion('Orphan instruction in switch') |
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640 elif op.op == 'local': |
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641 name = op.params[0] |
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642 size = op.params[1] |
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643 self.current_locals[name] = size |
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644 else: |
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645 self.current_case.append(op) |
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646 |
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647 def resolveLocal(self, name): |
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648 if name in self.current_locals: |
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649 return name |
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650 return self.parent.resolveLocal(name) |
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651 |
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652 def addLocal(self, name, size): |
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653 self.current_locals[name] = size |
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654 |
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655 def localSize(self, name): |
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656 if name in self.current_locals: |
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657 return self.current_locals[name] |
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658 return self.parent.localSize(name) |
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659 |
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660 def generate(self, prog, parent, fieldVals, output, otype, flagUpdates): |
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661 prog.pushScope(self) |
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662 param = prog.resolveParam(self.param, parent, fieldVals) |
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663 if type(param) is int: |
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664 self.regValues = self.parent.regValues |
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665 if param in self.cases: |
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666 self.current_locals = self.case_locals[param] |
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667 output.append('\n\t{') |
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668 for local in self.case_locals[param]: |
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669 output.append('\n\tuint{0}_t {1};'.format(self.case_locals[param][local], local)) |
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670 self.processOps(prog, fieldVals, output, otype, self.cases[param]) |
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671 output.append('\n\t}') |
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672 elif self.default: |
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673 self.current_locals = self.default_locals |
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674 output.append('\n\t{') |
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675 for local in self.default_locals: |
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676 output.append('\n\tuint{0}_t {1};'.format(self.default[local], local)) |
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677 self.processOps(prog, fieldVals, output, otype, self.default) |
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678 output.append('\n\t}') |
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679 else: |
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680 output.append('\n\tswitch(' + param + ')') |
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681 output.append('\n\t{') |
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682 for case in self.cases: |
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683 self.current_locals = self.case_locals[case] |
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684 self.regValues = dict(self.parent.regValues) |
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685 output.append('\n\tcase {0}U: '.format(case) + '{') |
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686 for local in self.case_locals[case]: |
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687 output.append('\n\tuint{0}_t {1};'.format(self.case_locals[case][local], local)) |
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688 self.processOps(prog, fieldVals, output, otype, self.cases[case]) |
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689 output.append('\n\tbreak;') |
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690 output.append('\n\t}') |
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|
691 if self.default: |
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692 self.current_locals = self.default_locals |
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693 self.regValues = dict(self.parent.regValues) |
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|
694 output.append('\n\tdefault: {') |
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|
695 for local in self.default_locals: |
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|
696 output.append('\n\tuint{0}_t {1};'.format(self.default_locals[local], local)) |
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697 self.processOps(prog, fieldVals, output, otype, self.default) |
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698 output.append('\n\t}') |
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699 prog.popScope() |
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|
700 |
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|
701 def __str__(self): |
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|
702 keys = self.cases.keys() |
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|
703 keys.sort() |
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|
704 lines = ['\n\tswitch'] |
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|
705 for case in keys: |
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|
706 lines.append('\n\tcase {0}'.format(case)) |
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|
707 lines.append(''.join([str(op) for op in self.cases[case]])) |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
708 lines.append('\n\tend') |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
709 return ''.join(lines) |
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|
710 |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
711 |
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|
712 def _geuCImpl(prog, parent, fieldVals, output): |
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|
713 if prog.lastOp.op == 'cmp': |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
714 output.pop() |
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|
715 params = [prog.resolveParam(p, parent, fieldVals) for p in prog.lastOp.params] |
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|
716 return '\n\tif ({a} >= {b}) '.format(a=params[1], b = params[0]) + '{' |
1613
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|
717 else: |
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|
718 raise ion(">=U not implemented in the general case yet") |
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|
719 |
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|
720 _ifCmpImpl = { |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
721 'c': { |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
722 '>=U': _geuCImpl |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
723 } |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
724 } |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
725 #represents a DSL conditional construct |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
726 class If(ChildBlock): |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
727 def __init__(self, parent, cond): |
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|
728 self.op = 'if' |
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|
729 self.parent = parent |
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|
730 self.cond = cond |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
731 self.body = [] |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
732 self.elseBody = [] |
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|
733 self.curBody = self.body |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
734 self.locals = {} |
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|
735 self.elseLocals = {} |
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|
736 self.curLocals = self.locals |
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|
737 self.regValues = None |
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|
738 |
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|
739 def addOp(self, op): |
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|
740 if op.op in ('case', 'arg'): |
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|
741 raise Exception(self.op + ' is not allows inside an if block') |
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|
742 if op.op == 'local': |
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|
743 name = op.params[0] |
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|
744 size = op.params[1] |
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|
745 self.locals[name] = size |
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|
746 elif op.op == 'else': |
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|
747 self.curLocals = self.elseLocals |
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|
748 self.curBody = self.elseBody |
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|
749 else: |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
750 self.curBody.append(op) |
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|
751 |
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|
752 def localSize(self, name): |
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753 return self.curLocals.get(name) |
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|
754 |
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|
755 def resolveLocal(self, name): |
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|
756 if name in self.locals: |
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|
757 return name |
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758 return self.parent.resolveLocal(name) |
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|
759 |
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|
760 def _genTrueBody(self, prog, fieldVals, output, otype): |
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|
761 self.curLocals = self.locals |
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|
762 for local in self.locals: |
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|
763 output.append('\n\tuint{sz}_t {nm};'.format(sz=self.locals[local], nm=local)) |
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Michael Pavone <pavone@retrodev.com>
parents:
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|
764 self.processOps(prog, fieldVals, output, otype, self.body) |
1614
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Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
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parents:
1613
diff
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|
765 |
1618
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Getting SVP core closer to compiling
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parents:
1616
diff
changeset
|
766 def _genFalseBody(self, prog, fieldVals, output, otype): |
1614
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Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
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parents:
1613
diff
changeset
|
767 self.curLocals = self.elseLocals |
1618
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Getting SVP core closer to compiling
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parents:
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diff
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|
768 for local in self.elseLocals: |
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Getting SVP core closer to compiling
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parents:
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diff
changeset
|
769 output.append('\n\tuint{sz}_t {nm};'.format(sz=self.elseLocals[local], nm=local)) |
1704
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
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parents:
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diff
changeset
|
770 self.processOps(prog, fieldVals, output, otype, self.elsebody) |
1614
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Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents:
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diff
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|
771 |
1618
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Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
772 def _genConstParam(self, param, prog, fieldVals, output, otype): |
1614
c9639139aedf
Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents:
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|
773 if param: |
1618
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Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
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diff
changeset
|
774 self._genTrueBody(prog, fieldVals, output, otype) |
1614
c9639139aedf
Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents:
1613
diff
changeset
|
775 else: |
1618
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Getting SVP core closer to compiling
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parents:
1616
diff
changeset
|
776 self._genFalseBody(prog, fieldVals, output, otype) |
1614
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Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents:
1613
diff
changeset
|
777 |
1704
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First stab at carry and half-carry calculation in CPU DSL
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parents:
1703
diff
changeset
|
778 def generate(self, prog, parent, fieldVals, output, otype, flagUpdates): |
1614
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Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents:
1613
diff
changeset
|
779 self.regValues = parent.regValues |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
780 try: |
1618
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Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
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diff
changeset
|
781 self._genConstParam(prog.checkBool(self.cond), prog, fieldVals, output, otype) |
1613
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
782 except Exception: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
783 if self.cond in _ifCmpImpl[otype]: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
784 output.append(_ifCmpImpl[otype][self.cond](prog, parent, fieldVals, output)) |
1618
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Getting SVP core closer to compiling
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parents:
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changeset
|
785 self._genTrueBody(prog, fieldVals, output, otype) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
786 if self.elseBody: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
787 output.append('\n\t} else {') |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
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diff
changeset
|
788 self._genFalseBody(prog, fieldVals, output, otype) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
789 output.append('\n\t}') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
790 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
791 cond = prog.resolveParam(self.cond, parent, fieldVals) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
792 if type(cond) is int: |
1618
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Getting SVP core closer to compiling
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diff
changeset
|
793 self._genConstParam(cond, prog, fieldVals, output, otype) |
1613
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
794 else: |
1614
c9639139aedf
Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents:
1613
diff
changeset
|
795 output.append('\n\tif ({cond}) '.format(cond=cond) + '{') |
1618
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Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
796 self._genTrueBody(prog, fieldVals, output, otype) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
797 if self.elseBody: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
798 output.append('\n\t} else {') |
1618
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Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
799 self._genFalseBody(prog, fieldVals, output, otype) |
1613
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
800 output.append('\n\t}') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
801 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
802 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
803 def __str__(self): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
804 lines = ['\n\tif'] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
805 for op in self.body: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
806 lines.append(str(op)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
807 lines.append('\n\tend') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
808 return ''.join(lines) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
809 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
810 class Registers: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
811 def __init__(self): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
812 self.regs = {} |
1621
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Implement program ROM reads
Michael Pavone <pavone@retrodev.com>
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1620
diff
changeset
|
813 self.pointers = {} |
1613
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
814 self.regArrays = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
815 self.regToArray = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
816 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
817 def addReg(self, name, size): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
818 self.regs[name] = size |
1621
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1620
diff
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|
819 |
ca158bc091f9
Implement program ROM reads
Michael Pavone <pavone@retrodev.com>
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1620
diff
changeset
|
820 def addPointer(self, name, size): |
ca158bc091f9
Implement program ROM reads
Michael Pavone <pavone@retrodev.com>
parents:
1620
diff
changeset
|
821 self.pointers[name] = size |
1613
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
822 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
823 def addRegArray(self, name, size, regs): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
824 self.regArrays[name] = (size, regs) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
825 idx = 0 |
1615
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Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
826 if not type(regs) is int: |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
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changeset
|
827 for reg in regs: |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
828 self.regs[reg] = size |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
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changeset
|
829 self.regToArray[reg] = (name, idx) |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
830 idx += 1 |
1613
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
831 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
832 def isReg(self, name): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
833 return name in self.regs |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
834 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
835 def isRegArray(self, name): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
836 return name in self.regArrays |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
837 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
838 def isRegArrayMember(self, name): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
839 return name in self.regToArray |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
840 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
841 def arrayMemberParent(self, name): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
842 return self.regToArray[name][0] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
843 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
844 def arrayMemberIndex(self, name): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
845 return self.regToArray[name][1] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
846 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
847 def arrayMemberName(self, array, index): |
1615
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Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
848 if type(index) is int and not type(self.regArrays[array][1]) is int: |
1613
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
849 return self.regArrays[array][1][index] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
850 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
851 return None |
1615
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Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
852 |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
853 def isNamedArray(self, array): |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
854 return array in self.regArrays and type(self.regArrays[array][1]) is int |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
855 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
856 def processLine(self, parts): |
1615
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
857 if len(parts) == 3: |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
858 self.addRegArray(parts[0], int(parts[1]), int(parts[2])) |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
859 elif len(parts) > 2: |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
860 self.addRegArray(parts[0], int(parts[1]), parts[2:]) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
861 else: |
1621
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Michael Pavone <pavone@retrodev.com>
parents:
1620
diff
changeset
|
862 if parts[1].startswith('ptr'): |
ca158bc091f9
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Michael Pavone <pavone@retrodev.com>
parents:
1620
diff
changeset
|
863 self.addPointer(parts[0], int(parts[1][3:])) |
ca158bc091f9
Implement program ROM reads
Michael Pavone <pavone@retrodev.com>
parents:
1620
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|
864 else: |
ca158bc091f9
Implement program ROM reads
Michael Pavone <pavone@retrodev.com>
parents:
1620
diff
changeset
|
865 self.addReg(parts[0], int(parts[1])) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
866 return self |
1618
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Getting SVP core closer to compiling
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parents:
1616
diff
changeset
|
867 |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
868 def writeHeader(self, otype, hFile): |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
869 fieldList = [] |
1621
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Implement program ROM reads
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parents:
1620
diff
changeset
|
870 for pointer in self.pointers: |
ca158bc091f9
Implement program ROM reads
Michael Pavone <pavone@retrodev.com>
parents:
1620
diff
changeset
|
871 hFile.write('\n\tuint{sz}_t *{nm};'.format(nm=pointer, sz=self.pointers[pointer])) |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
872 for reg in self.regs: |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
873 if not self.isRegArrayMember(reg): |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
874 fieldList.append((self.regs[reg], 1, reg)) |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
875 for arr in self.regArrays: |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
876 size,regs = self.regArrays[arr] |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
877 if not type(regs) is int: |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
878 regs = len(regs) |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
879 fieldList.append((size, regs, arr)) |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
880 fieldList.sort() |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
881 fieldList.reverse() |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
882 for size, count, name in fieldList: |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
883 if count > 1: |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
884 hFile.write('\n\tuint{sz}_t {nm}[{ct}];'.format(sz=size, nm=name, ct=count)) |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
885 else: |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
886 hFile.write('\n\tuint{sz}_t {nm};'.format(sz=size, nm=name)) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
887 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
888 class Flags: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
889 def __init__(self): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
890 self.flagBits = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
891 self.flagCalc = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
892 self.flagStorage = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
893 self.flagReg = None |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
894 self.maxBit = -1 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
895 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
896 def processLine(self, parts): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
897 if parts[0] == 'register': |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
898 self.flagReg = parts[1] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
899 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
900 flag,bit,calc,storage = parts |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
901 bit,_,top = bit.partition('-') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
902 bit = int(bit) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
903 if top: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
904 top = int(bit) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
905 if top > self.maxBit: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
906 self.maxBit = top |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
907 self.flagBits[flag] = (bit,top) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
908 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
909 if bit > self.maxBit: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
910 self.maxBit = bit |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
911 self.flagBits[flag] = bit |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
912 self.flagCalc[flag] = calc |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
913 self.flagStorage[flag] = storage |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
914 return self |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
915 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
916 def getStorage(self, flag): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
917 if not flag in self.flagStorage: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
918 raise Exception('Undefined flag ' + flag) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
919 loc,_,bit = self.flagStorage[flag].partition('.') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
920 if bit: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
921 return (loc, int(bit)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
922 else: |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
923 return loc |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
924 |
1704
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
925 def parseFlagUpdate(self, flagString): |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
926 last = '' |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
927 autoUpdate = set() |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
928 explicit = {} |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
929 for c in flagString: |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
930 if c.isdigit(): |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
931 if last.isalpha(): |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
932 num = int(c) |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
933 if num > 1: |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
934 raise Exception(c + ' is not a valid digit for update_flags') |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
935 explicit[last] = num |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
936 last = c |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
937 else: |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
938 raise Exception('Digit must follow flag letter in update_flags') |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
939 else: |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
940 if last.isalpha(): |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
941 autoUpdate.add(last) |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
942 last = c |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
943 if last.isalpha(): |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
944 autoUpdate.add(last) |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
945 return (autoUpdate, explicit) |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
946 |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
947 def disperseFlags(self, prog, otype): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
948 bitToFlag = [None] * (self.maxBit+1) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
949 src = prog.resolveReg(self.flagReg, None, {}) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
950 output = [] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
951 for flag in self.flagBits: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
952 bit = self.flagBits[flag] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
953 if type(bit) is tuple: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
954 bot,top = bit |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
955 mask = ((1 << (top + 1 - bot)) - 1) << bot |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
956 output.append('\n\t{dst} = {src} & mask;'.format( |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
957 dst=prog.resolveReg(self.flagStorage[flag], None, {}), src=src, mask=mask |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
958 )) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
959 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
960 bitToFlag[self.flagBits[flag]] = flag |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
961 multi = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
962 for bit in range(len(bitToFlag)-1,-1,-1): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
963 flag = bitToFlag[bit] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
964 if not flag is None: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
965 field,_,dstbit = self.flagStorage[flag].partition('.') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
966 dst = prog.resolveReg(field, None, {}) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
967 if dstbit: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
968 dstbit = int(dstbit) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
969 multi.setdefault(dst, []).append((dstbit, bit)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
970 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
971 output.append('\n\t{dst} = {src} & {mask};'.format(dst=dst, src=src, mask=(1 << bit))) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
972 for dst in multi: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
973 didClear = False |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
974 direct = [] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
975 for dstbit, bit in multi[dst]: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
976 if dstbit == bit: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
977 direct.append(bit) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
978 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
979 if not didClear: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
980 output.append('\n\t{dst} = 0;'.format(dst=dst)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
981 didClear = True |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
982 if dstbit > bit: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
983 shift = '<<' |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
984 diff = dstbit - bit |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
985 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
986 shift = '>>' |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
987 diff = bit - dstbit |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
988 output.append('\n\t{dst} |= {src} {shift} {diff} & {mask};'.format( |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
989 src=src, dst=dst, shift=shift, diff=diff, mask=(1 << dstbit) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
990 )) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
991 if direct: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
992 if len(direct) == len(multi[dst]): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
993 output.append('\n\t{dst} = {src};'.format(dst=dst, src=src)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
994 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
995 mask = 0 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
996 for bit in direct: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
997 mask = mask | (1 << bit) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
998 output.append('\n\t{dst} = {src} & {mask};'.format(dst=dst, src=src, mask=mask)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
999 return ''.join(output) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1000 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1001 def coalesceFlags(self, prog, otype): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1002 dst = prog.resolveReg(self.flagReg, None, {}) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1003 output = ['\n\t{dst} = 0;'.format(dst=dst)] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1004 bitToFlag = [None] * (self.maxBit+1) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1005 for flag in self.flagBits: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1006 bit = self.flagBits[flag] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1007 if type(bit) is tuple: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1008 bot,_ = bit |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1009 src = prog.resolveReg(self.flagStorage[flag], None, {}) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1010 if bot: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1011 output.append('\n\t{dst} |= {src} << {shift};'.format( |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1012 dst=dst, src = src, shift = bot |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1013 )) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1014 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1015 output.append('\n\t{dst} |= {src};'.format( |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1016 dst=dst, src = src |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1017 )) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1018 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1019 bitToFlag[bit] = flag |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1020 multi = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1021 for bit in range(len(bitToFlag)-1,-1,-1): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1022 flag = bitToFlag[bit] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1023 if not flag is None: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1024 field,_,srcbit = self.flagStorage[flag].partition('.') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1025 src = prog.resolveReg(field, None, {}) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1026 if srcbit: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1027 srcbit = int(srcbit) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1028 multi.setdefault(src, []).append((srcbit,bit)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1029 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1030 output.append('\n\tif ({src}) {{\n\t\t{dst} |= 1 << {bit};\n\t}}'.format( |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1031 dst=dst, src=src, bit=bit |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1032 )) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1033 for src in multi: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1034 direct = 0 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1035 for srcbit, dstbit in multi[src]: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1036 if srcbit == dstbit: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1037 direct = direct | (1 << srcbit) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1038 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1039 output.append('\n\tif ({src} & (1 << {srcbit})) {{\n\t\t{dst} |= 1 << {dstbit};\n\t}}'.format( |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1040 src=src, dst=dst, srcbit=srcbit, dstbit=dstbit |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1041 )) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1042 if direct: |
1698
90272218469c
Fixed missing semicolon in coalesceFlags
Michael Pavone <pavone@retrodev.com>
parents:
1697
diff
changeset
|
1043 output.append('\n\t{dst} |= {src} & {mask};'.format( |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1044 dst=dst, src=src, mask=direct |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1045 )) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1046 return ''.join(output) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1047 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1048 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1049 class Program: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1050 def __init__(self, regs, instructions, subs, info, flags): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1051 self.regs = regs |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1052 self.instructions = instructions |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1053 self.subroutines = subs |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1054 self.meta = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1055 self.booleans = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1056 self.prefix = info.get('prefix', [''])[0] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1057 self.opsize = int(info.get('opcode_size', ['8'])[0]) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1058 self.extra_tables = info.get('extra_tables', []) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1059 self.context_type = self.prefix + 'context' |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1060 self.body = info.get('body', [None])[0] |
1620
a172f97d873f
Add the ability for a CPU definition to reference arbitrary C includes and use it to add a placeholder definition of svp_read_16
Michael Pavone <pavone@retrodev.com>
parents:
1619
diff
changeset
|
1061 self.includes = info.get('include', []) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1062 self.flags = flags |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1063 self.lastDst = None |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1064 self.scopes = [] |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1065 self.currentScope = None |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1066 self.lastOp = None |
1704
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1067 self.carryFlowDst = None |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1068 self.lastA = None |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1069 self.lastB = None |
1708
5bfed2eedc9d
Fixed flag calculation for sub instructions in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1707
diff
changeset
|
1070 self.lastBFlow = None |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1071 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1072 def __str__(self): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1073 pieces = [] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1074 for reg in self.regs: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1075 pieces.append(str(self.regs[reg])) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1076 for name in self.subroutines: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1077 pieces.append('\n'+str(self.subroutines[name])) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1078 for instruction in self.instructions: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1079 pieces.append('\n'+str(instruction)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1080 return ''.join(pieces) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1081 |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1082 def writeHeader(self, otype, header): |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1083 hFile = open(header, 'w') |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1084 macro = header.upper().replace('.', '_') |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1085 hFile.write('#ifndef {0}_'.format(macro)) |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1086 hFile.write('\n#define {0}_'.format(macro)) |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1087 hFile.write('\n#include "backend.h"') |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1088 hFile.write('\n\ntypedef struct {') |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1089 hFile.write('\n\tcpu_options gen;') |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1090 hFile.write('\n}} {0}options;'.format(self.prefix)) |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1091 hFile.write('\n\ntypedef struct {') |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1092 hFile.write('\n\t{0}options *opts;'.format(self.prefix)) |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1093 hFile.write('\n\tuint32_t cycles;') |
5dbc453cd345
Getting SVP core closer to compiling
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1616
diff
changeset
|
1094 self.regs.writeHeader(otype, hFile) |
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Getting SVP core closer to compiling
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parents:
1616
diff
changeset
|
1095 hFile.write('\n}} {0}context;'.format(self.prefix)) |
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Getting SVP core closer to compiling
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parents:
1616
diff
changeset
|
1096 hFile.write('\n') |
1703
49a52c737bf0
Fix zero flag calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1702
diff
changeset
|
1097 hFile.write('\nvoid {pre}execute({type} *context, uint32_t target_cycle);'.format(pre = self.prefix, type = self.context_type)) |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1098 hFile.write('\n#endif //{0}_'.format(macro)) |
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Getting SVP core closer to compiling
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diff
changeset
|
1099 hFile.write('\n') |
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Getting SVP core closer to compiling
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diff
changeset
|
1100 hFile.close() |
1700
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Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
1699
diff
changeset
|
1101 |
e4b4e21a37fa
Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
1699
diff
changeset
|
1102 def _buildTable(self, otype, table, body): |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1103 pieces = [] |
1700
e4b4e21a37fa
Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
1699
diff
changeset
|
1104 opmap = [None] * (1 << self.opsize) |
e4b4e21a37fa
Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
1699
diff
changeset
|
1105 bodymap = {} |
e4b4e21a37fa
Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
1699
diff
changeset
|
1106 if table in self.instructions: |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1107 instructions = self.instructions[table] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1108 instructions.sort() |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1109 for inst in instructions: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1110 for val in inst.allValues(): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1111 if opmap[val] is None: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1112 self.meta = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1113 self.temp = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1114 self.needFlagCoalesce = False |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1115 self.needFlagDisperse = False |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1116 self.lastOp = None |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1117 opmap[val] = inst.generateName(val) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1118 bodymap[val] = inst.generateBody(val, self, otype) |
1700
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Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
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diff
changeset
|
1119 |
e4b4e21a37fa
Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
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diff
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|
1120 pieces.append('\ntypedef void (*impl_fun)({pre}context *context);'.format(pre=self.prefix)) |
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Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
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diff
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|
1121 pieces.append('\nstatic impl_fun impl_{name}[{sz}] = {{'.format(name = table, sz=len(opmap))) |
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Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
1699
diff
changeset
|
1122 for inst in range(0, len(opmap)): |
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Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
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diff
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|
1123 op = opmap[inst] |
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Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
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diff
changeset
|
1124 if op is None: |
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Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
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diff
changeset
|
1125 pieces.append('\n\tunimplemented,') |
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Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
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parents:
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diff
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|
1126 else: |
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Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
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diff
changeset
|
1127 pieces.append('\n\t' + op + ',') |
e4b4e21a37fa
Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
1699
diff
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|
1128 body.append(bodymap[inst]) |
e4b4e21a37fa
Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
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diff
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|
1129 pieces.append('\n};') |
e4b4e21a37fa
Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
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diff
changeset
|
1130 body.extend(pieces) |
e4b4e21a37fa
Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
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diff
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|
1131 |
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Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
1699
diff
changeset
|
1132 def build(self, otype): |
e4b4e21a37fa
Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
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diff
changeset
|
1133 body = [] |
e4b4e21a37fa
Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
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diff
changeset
|
1134 pieces = [] |
e4b4e21a37fa
Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
1699
diff
changeset
|
1135 for include in self.includes: |
e4b4e21a37fa
Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
1699
diff
changeset
|
1136 body.append('#include "{0}"\n'.format(include)) |
e4b4e21a37fa
Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
1699
diff
changeset
|
1137 body.append('\nstatic void unimplemented({pre}context *context)'.format(pre = self.prefix)) |
e4b4e21a37fa
Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
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diff
changeset
|
1138 body.append('\n{') |
e4b4e21a37fa
Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
1699
diff
changeset
|
1139 body.append('\n\tfatal_error("Unimplemented instruction");') |
e4b4e21a37fa
Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
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diff
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|
1140 body.append('\n}\n') |
e4b4e21a37fa
Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
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diff
changeset
|
1141 for table in self.extra_tables: |
e4b4e21a37fa
Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
1699
diff
changeset
|
1142 self._buildTable(otype, table, body) |
e4b4e21a37fa
Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
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diff
changeset
|
1143 self._buildTable(otype, 'main', body) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1144 if self.body in self.subroutines: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1145 pieces.append('\nvoid {pre}execute({type} *context, uint32_t target_cycle)'.format(pre = self.prefix, type = self.context_type)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1146 pieces.append('\n{') |
1618
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Getting SVP core closer to compiling
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1616
diff
changeset
|
1147 pieces.append('\n\twhile (context->cycles < target_cycle)') |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1148 pieces.append('\n\t{') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1149 self.meta = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1150 self.temp = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1151 self.subroutines[self.body].inline(self, [], pieces, otype, None) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1152 pieces.append('\n\t}') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1153 pieces.append('\n}') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1154 return ''.join(body) + ''.join(pieces) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1155 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1156 def checkBool(self, name): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1157 if not name in self.booleans: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1158 raise Exception(name + ' is not a defined boolean flag') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1159 return self.booleans[name] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1160 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1161 def getTemp(self, size): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1162 if size in self.temp: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1163 return ('', self.temp[size]) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1164 self.temp[size] = 'tmp{sz}'.format(sz=size); |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
1165 return ('\n\tuint{sz}_t tmp{sz};'.format(sz=size), self.temp[size]) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
1166 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1167 def resolveParam(self, param, parent, fieldVals, allowConstant=True, isdst=False): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1168 keepGoing = True |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1169 while keepGoing: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1170 keepGoing = False |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1171 try: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1172 if type(param) is int: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1173 pass |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1174 elif param.startswith('0x'): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1175 param = int(param, 16) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1176 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1177 param = int(param) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
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changeset
|
1178 except ValueError: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1179 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
diff
changeset
|
1180 if parent: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1181 if param in parent.regValues and allowConstant: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1182 return parent.regValues[param] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1183 maybeLocal = parent.resolveLocal(param) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1184 if maybeLocal: |
1715
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1713
diff
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|
1185 if isdst: |
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Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
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1713
diff
changeset
|
1186 self.lastDst = param |
1613
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
diff
changeset
|
1187 return maybeLocal |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1188 if param in fieldVals: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1189 param = fieldVals[param] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
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changeset
|
1190 elif param in self.meta: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1191 param = self.meta[param] |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1192 keepGoing = True |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1193 elif self.isReg(param): |
1715
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1713
diff
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|
1194 return self.resolveReg(param, parent, fieldVals, isdst) |
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diff
changeset
|
1195 if isdst: |
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changeset
|
1196 self.lastDst = param |
1613
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
diff
changeset
|
1197 return param |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
diff
changeset
|
1198 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1199 def isReg(self, name): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1200 if not type(name) is str: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1201 return False |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1202 begin,sep,_ = name.partition('.') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1203 if sep: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1204 if begin in self.meta: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1205 begin = self.meta[begin] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1206 return self.regs.isRegArray(begin) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1207 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1208 return self.regs.isReg(name) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1209 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1210 def resolveReg(self, name, parent, fieldVals, isDst=False): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1211 begin,sep,end = name.partition('.') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1212 if sep: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1213 if begin in self.meta: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1214 begin = self.meta[begin] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1215 if not self.regs.isRegArrayMember(end): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1216 end = self.resolveParam(end, parent, fieldVals) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1217 if not type(end) is int and self.regs.isRegArrayMember(end): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1218 arrayName = self.regs.arrayMemberParent(end) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1219 end = self.regs.arrayMemberIndex(end) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1220 if arrayName != begin: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1221 end = 'context->{0}[{1}]'.format(arrayName, end) |
1615
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
1222 if self.regs.isNamedArray(begin): |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
1223 regName = self.regs.arrayMemberName(begin, end) |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
1224 else: |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
1225 regName = '{0}.{1}'.format(begin, end) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1226 ret = 'context->{0}[{1}]'.format(begin, end) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1227 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1228 regName = name |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1229 if self.regs.isRegArrayMember(name): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1230 arr,idx = self.regs.regToArray[name] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1231 ret = 'context->{0}[{1}]'.format(arr, idx) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1232 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1233 ret = 'context->' + name |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1234 if regName == self.flags.flagReg: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1235 if isDst: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1236 self.needFlagDisperse = True |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1237 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1238 self.needFlagCoalesce = True |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1239 if isDst: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1240 self.lastDst = regName |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1241 return ret |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1242 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1243 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1244 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1245 def paramSize(self, name): |
1715
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1713
diff
changeset
|
1246 if name in self.meta: |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1713
diff
changeset
|
1247 return self.paramSize(self.meta[name]) |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1713
diff
changeset
|
1248 for i in range(len(self.scopes) -1, -1, -1): |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1713
diff
changeset
|
1249 size = self.scopes[i].localSize(name) |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1713
diff
changeset
|
1250 if size: |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1713
diff
changeset
|
1251 return size |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1252 begin,sep,_ = name.partition('.') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1253 if sep and self.regs.isRegArray(begin): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1254 return self.regs.regArrays[begin][0] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1255 if self.regs.isReg(name): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1256 return self.regs.regs[name] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1257 return 32 |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1258 |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1259 def pushScope(self, scope): |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1260 self.scopes.append(scope) |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1261 self.currentScope = scope |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1262 |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1263 def popScope(self): |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1264 ret = self.scopes.pop() |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1265 self.currentScope = self.scopes[-1] if self.scopes else None |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1266 return ret |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1267 |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1268 def getRootScope(self): |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1269 return self.scopes[0] |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1270 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1271 def parse(f): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1272 instructions = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1273 subroutines = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1274 registers = None |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1275 flags = None |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1276 errors = [] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1277 info = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1278 line_num = 0 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1279 cur_object = None |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1280 for line in f: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1281 line_num += 1 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1282 line,_,comment = line.partition('#') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1283 if not line.strip(): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1284 continue |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1285 if line[0].isspace(): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1286 if not cur_object is None: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1287 parts = [el.strip() for el in line.split(' ')] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1288 if type(cur_object) is dict: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1289 cur_object[parts[0]] = parts[1:] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1290 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1291 cur_object = cur_object.processLine(parts) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1292 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1293 # if type(cur_object) is Registers: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1294 # if len(parts) > 2: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1295 # cur_object.addRegArray(parts[0], int(parts[1]), parts[2:]) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1296 # else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1297 # cur_object.addReg(parts[0], int(parts[1])) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1298 # elif type(cur_object) is dict: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1299 # cur_object[parts[0]] = parts[1:] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1300 # elif parts[0] == 'switch': |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1301 # o = Switch(cur_object, parts[1]) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1302 # cur_object.addOp(o) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1303 # cur_object = o |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1304 # elif parts[0] == 'if': |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1305 # o = If(cur_object, parts[1]) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1306 # cur_object.addOp(o) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1307 # cur_object = o |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1308 # elif parts[0] == 'end': |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1309 # cur_object = cur_object.parent |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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1310 # else: |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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1311 # cur_object.addOp(NormalOp(parts)) |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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1312 else: |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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1313 errors.append("Orphan instruction on line {0}".format(line_num)) |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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1314 else: |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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1315 parts = line.split(' ') |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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1316 if len(parts) > 1: |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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1317 if len(parts) > 2: |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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1318 table,bitpattern,name = parts |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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1319 else: |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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1320 bitpattern,name = parts |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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1321 table = 'main' |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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1322 value = 0 |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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1323 fields = {} |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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1324 curbit = len(bitpattern) - 1 |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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1325 for char in bitpattern: |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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1326 value <<= 1 |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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1327 if char in ('0', '1'): |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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1328 value |= int(char) |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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1329 else: |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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1330 if char in fields: |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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1331 fields[char] = (curbit, fields[char][1] + 1) |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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1332 else: |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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1333 fields[char] = (curbit, 1) |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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1334 curbit -= 1 |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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1335 cur_object = Instruction(value, fields, name.strip()) |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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1336 instructions.setdefault(table, []).append(cur_object) |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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1337 elif line.strip() == 'regs': |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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1338 if registers is None: |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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1339 registers = Registers() |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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1340 cur_object = registers |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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1341 elif line.strip() == 'info': |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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1342 cur_object = info |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
1343 elif line.strip() == 'flags': |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
1344 if flags is None: |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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1345 flags = Flags() |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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1346 cur_object = flags |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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1347 else: |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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1348 cur_object = SubRoutine(line.strip()) |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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1349 subroutines[cur_object.name] = cur_object |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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1350 if errors: |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
1351 print(errors) |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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1352 else: |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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1353 p = Program(registers, instructions, subroutines, info, flags) |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
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1354 p.booleans['dynarec'] = False |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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1355 p.booleans['interp'] = True |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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1356 |
1618
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1357 if 'header' in info: |
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1358 print('#include "{0}"'.format(info['header'][0])) |
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1359 p.writeHeader('c', info['header'][0]) |
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1360 print('#include "util.h"') |
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1361 print('#include <stdlib.h>') |
1613
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1362 print(p.build('c')) |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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1363 |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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1364 def main(argv): |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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1365 f = open(argv[1]) |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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1366 parse(f) |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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1367 |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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1368 if __name__ == '__main__': |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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1369 from sys import argv |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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1370 main(argv) |