Mercurial > repos > blastem
annotate z80_to_x86.c @ 1369:3e7a921718de
Fix handling of test register selected sprite layer in border area. Gets rid of the border garbage in the "disco floor/ceiling" scene of OD2
author | Michael Pavone <pavone@retrodev.com> |
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date | Tue, 23 May 2017 19:09:57 -0700 |
parents | cad1642baf66 |
children | 70d88d9bfe13 |
rev | line source |
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1 /* |
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2 Copyright 2013 Michael Pavone |
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The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
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3 This file is part of BlastEm. |
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4 BlastEm is free software distributed under the terms of the GNU General Public License version 3 or greater. See COPYING for full license text. |
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5 */ |
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6 #include "z80inst.h" |
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7 #include "z80_to_x86.h" |
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8 #include "gen_x86.h" |
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9 #include "mem.h" |
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10 #include "util.h" |
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11 #include <stdio.h> |
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12 #include <stdlib.h> |
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13 #include <stddef.h> |
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14 #include <string.h> |
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15 |
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16 #define MODE_UNUSED (MODE_IMMED-1) |
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17 #define MAX_MCYCLE_LENGTH 6 |
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18 #define NATIVE_CHUNK_SIZE 1024 |
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19 #define NATIVE_MAP_CHUNKS (0x10000 / NATIVE_CHUNK_SIZE) |
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20 |
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21 //#define DO_DEBUG_PRINT |
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22 |
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23 #ifdef DO_DEBUG_PRINT |
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24 #define dprintf printf |
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25 #else |
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26 #define dprintf |
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27 #endif |
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28 |
652 | 29 uint32_t zbreakpoint_patch(z80_context * context, uint16_t address, code_ptr dst); |
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30 void z80_handle_deferred(z80_context * context); |
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31 |
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32 uint8_t z80_size(z80inst * inst) |
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33 { |
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34 uint8_t reg = (inst->reg & 0x1F); |
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35 if (reg != Z80_UNUSED && reg != Z80_USE_IMMED) { |
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36 return reg < Z80_BC ? SZ_B : SZ_W; |
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37 } |
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38 //TODO: Handle any necessary special cases |
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39 return SZ_B; |
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40 } |
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41 |
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42 uint8_t zf_off(uint8_t flag) |
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43 { |
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44 return offsetof(z80_context, flags) + flag; |
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45 } |
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46 |
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47 uint8_t zaf_off(uint8_t flag) |
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48 { |
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49 return offsetof(z80_context, alt_flags) + flag; |
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50 } |
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51 |
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52 uint8_t zr_off(uint8_t reg) |
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53 { |
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54 if (reg > Z80_A) { |
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55 reg = z80_low_reg(reg); |
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56 } |
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57 return offsetof(z80_context, regs) + reg; |
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58 } |
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59 |
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60 uint8_t zar_off(uint8_t reg) |
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61 { |
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62 if (reg > Z80_A) { |
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63 reg = z80_low_reg(reg); |
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64 } |
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65 return offsetof(z80_context, alt_regs) + reg; |
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66 } |
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67 |
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68 void zreg_to_native(z80_options *opts, uint8_t reg, uint8_t native_reg) |
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69 { |
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70 if (opts->regs[reg] >= 0) { |
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71 mov_rr(&opts->gen.code, opts->regs[reg], native_reg, reg > Z80_A ? SZ_W : SZ_B); |
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72 } else { |
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73 mov_rdispr(&opts->gen.code, opts->gen.context_reg, zr_off(reg), native_reg, reg > Z80_A ? SZ_W : SZ_B); |
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74 } |
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75 } |
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76 |
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77 void native_to_zreg(z80_options *opts, uint8_t native_reg, uint8_t reg) |
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78 { |
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79 if (opts->regs[reg] >= 0) { |
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80 mov_rr(&opts->gen.code, native_reg, opts->regs[reg], reg > Z80_A ? SZ_W : SZ_B); |
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81 } else { |
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82 mov_rrdisp(&opts->gen.code, native_reg, opts->gen.context_reg, zr_off(reg), reg > Z80_A ? SZ_W : SZ_B); |
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83 } |
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84 } |
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85 |
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86 void translate_z80_reg(z80inst * inst, host_ea * ea, z80_options * opts) |
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87 { |
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88 code_info *code = &opts->gen.code; |
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89 if (inst->reg == Z80_USE_IMMED) { |
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90 ea->mode = MODE_IMMED; |
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91 ea->disp = inst->immed; |
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92 } else if ((inst->reg & 0x1F) == Z80_UNUSED) { |
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93 ea->mode = MODE_UNUSED; |
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94 } else { |
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95 ea->mode = MODE_REG_DIRECT; |
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96 if (inst->reg == Z80_IYH && opts->regs[Z80_IYL] >= 0) { |
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97 if ((inst->addr_mode & 0x1F) == Z80_REG && inst->ea_reg == Z80_IYL) { |
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98 mov_rr(code, opts->regs[Z80_IY], opts->gen.scratch1, SZ_W); |
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99 ror_ir(code, 8, opts->gen.scratch1, SZ_W); |
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100 ea->base = opts->gen.scratch1; |
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101 } else { |
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102 ea->base = opts->regs[Z80_IYL]; |
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103 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W); |
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104 } |
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105 } else if(opts->regs[inst->reg] >= 0) { |
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106 ea->base = opts->regs[inst->reg]; |
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107 if (ea->base >= AH && ea->base <= BH) { |
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108 if ((inst->addr_mode & 0x1F) == Z80_REG) { |
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109 uint8_t other_reg = opts->regs[inst->ea_reg]; |
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110 if (other_reg >= R8 || (other_reg >= RSP && other_reg <= RDI)) { |
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111 //we can't mix an *H reg with a register that requires the REX prefix |
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112 ea->base = opts->regs[z80_low_reg(inst->reg)]; |
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113 ror_ir(code, 8, ea->base, SZ_W); |
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114 } |
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115 } else if((inst->addr_mode & 0x1F) != Z80_UNUSED && (inst->addr_mode & 0x1F) != Z80_IMMED) { |
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116 //temp regs require REX prefix too |
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117 ea->base = opts->regs[z80_low_reg(inst->reg)]; |
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118 ror_ir(code, 8, ea->base, SZ_W); |
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119 } |
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120 } |
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121 } else { |
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122 ea->mode = MODE_REG_DISPLACE8; |
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123 ea->base = opts->gen.context_reg; |
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124 ea->disp = zr_off(inst->reg); |
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125 } |
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126 } |
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127 } |
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128 |
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129 void z80_save_reg(z80inst * inst, z80_options * opts) |
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130 { |
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131 code_info *code = &opts->gen.code; |
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132 if (inst->reg == Z80_USE_IMMED || inst->reg == Z80_UNUSED) { |
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133 return; |
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134 } |
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135 if (inst->reg == Z80_IYH && opts->regs[Z80_IYL] >= 0) { |
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136 if ((inst->addr_mode & 0x1F) == Z80_REG && inst->ea_reg == Z80_IYL) { |
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137 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W); |
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138 mov_rr(code, opts->gen.scratch1, opts->regs[Z80_IYL], SZ_B); |
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139 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W); |
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140 } else { |
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141 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W); |
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142 } |
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143 } else if (opts->regs[inst->reg] >= AH && opts->regs[inst->reg] <= BH) { |
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144 if ((inst->addr_mode & 0x1F) == Z80_REG) { |
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145 uint8_t other_reg = opts->regs[inst->ea_reg]; |
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146 if (other_reg >= R8 || (other_reg >= RSP && other_reg <= RDI)) { |
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147 //we can't mix an *H reg with a register that requires the REX prefix |
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148 ror_ir(code, 8, opts->regs[z80_low_reg(inst->reg)], SZ_W); |
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149 } |
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150 } else if((inst->addr_mode & 0x1F) != Z80_UNUSED && (inst->addr_mode & 0x1F) != Z80_IMMED) { |
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151 //temp regs require REX prefix too |
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152 ror_ir(code, 8, opts->regs[z80_low_reg(inst->reg)], SZ_W); |
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153 } |
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154 } |
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155 } |
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156 |
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157 void translate_z80_ea(z80inst * inst, host_ea * ea, z80_options * opts, uint8_t read, uint8_t modify) |
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158 { |
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159 code_info *code = &opts->gen.code; |
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160 uint8_t size, areg; |
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161 int8_t reg; |
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162 ea->mode = MODE_REG_DIRECT; |
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163 areg = read ? opts->gen.scratch1 : opts->gen.scratch2; |
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164 switch(inst->addr_mode & 0x1F) |
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165 { |
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166 case Z80_REG: |
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167 if (inst->ea_reg == Z80_IYH && opts->regs[Z80_IYL] >= 0) { |
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168 if (inst->reg == Z80_IYL) { |
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169 mov_rr(code, opts->regs[Z80_IY], opts->gen.scratch1, SZ_W); |
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170 ror_ir(code, 8, opts->gen.scratch1, SZ_W); |
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171 ea->base = opts->gen.scratch1; |
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172 } else { |
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173 ea->base = opts->regs[Z80_IYL]; |
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174 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W); |
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175 } |
651
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176 } else if(opts->regs[inst->ea_reg] >= 0) { |
213
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177 ea->base = opts->regs[inst->ea_reg]; |
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178 if (ea->base >= AH && ea->base <= BH && inst->reg != Z80_UNUSED && inst->reg != Z80_USE_IMMED) { |
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179 uint8_t other_reg = opts->regs[inst->reg]; |
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180 #ifdef X86_64 |
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181 if (other_reg >= R8 || (other_reg >= RSP && other_reg <= RDI)) { |
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182 //we can't mix an *H reg with a register that requires the REX prefix |
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183 ea->base = opts->regs[z80_low_reg(inst->ea_reg)]; |
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184 ror_ir(code, 8, ea->base, SZ_W); |
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185 } |
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186 #endif |
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187 } |
651
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188 } else { |
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|
189 ea->mode = MODE_REG_DISPLACE8; |
659
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190 ea->base = opts->gen.context_reg; |
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191 ea->disp = zr_off(inst->ea_reg); |
213
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192 } |
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193 break; |
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194 case Z80_REG_INDIRECT: |
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195 zreg_to_native(opts, inst->ea_reg, areg); |
213
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196 size = z80_size(inst); |
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197 if (read) { |
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198 if (modify) { |
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199 //push_r(code, opts->gen.scratch1); |
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200 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, offsetof(z80_context, scratch1), SZ_W); |
213
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Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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|
201 } |
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Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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|
202 if (size == SZ_B) { |
590
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|
203 call(code, opts->read_8); |
213
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|
204 } else { |
591
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Get Z80 core back into compileable state
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diff
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|
205 call(code, opts->read_16); |
213
4d4559b04c59
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|
206 } |
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|
207 } |
590
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|
208 ea->base = opts->gen.scratch1; |
213
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Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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|
209 break; |
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|
210 case Z80_IMMED: |
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|
211 ea->mode = MODE_IMMED; |
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|
212 ea->disp = inst->immed; |
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|
213 break; |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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|
214 case Z80_IMMED_INDIRECT: |
591
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|
215 mov_ir(code, inst->immed, areg, SZ_W); |
213
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|
216 size = z80_size(inst); |
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|
217 if (read) { |
277
765e132edd71
Using push/pop inside translated code is not compatible with the current way the Z80 core returns to the caller
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218 /*if (modify) { |
591
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219 push_r(code, opts->gen.scratch1); |
277
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220 }*/ |
213
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|
221 if (size == SZ_B) { |
593
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222 call(code, opts->read_8); |
213
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223 } else { |
593
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224 call(code, opts->read_16); |
213
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|
225 } |
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|
226 } |
590
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227 ea->base = opts->gen.scratch1; |
213
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|
228 break; |
235
d9bf8e61c33c
Get Z80 core working for simple programs
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213
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229 case Z80_IX_DISPLACE: |
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213
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230 case Z80_IY_DISPLACE: |
731
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|
231 zreg_to_native(opts, (inst->addr_mode & 0x1F) == Z80_IX_DISPLACE ? Z80_IX : Z80_IY, areg); |
591
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232 add_ir(code, inst->ea_reg & 0x80 ? inst->ea_reg - 256 : inst->ea_reg, areg, SZ_W); |
213
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233 size = z80_size(inst); |
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234 if (read) { |
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|
235 if (modify) { |
591
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|
236 //push_r(code, opts->gen.scratch1); |
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237 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, offsetof(z80_context, scratch1), SZ_W); |
213
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|
238 } |
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|
239 if (size == SZ_B) { |
593
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|
240 call(code, opts->read_8); |
213
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|
241 } else { |
593
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|
242 call(code, opts->read_16); |
213
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243 } |
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|
244 } |
590
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|
245 ea->base = opts->gen.scratch1; |
213
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246 break; |
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|
247 case Z80_UNUSED: |
235
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213
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|
248 ea->mode = MODE_UNUSED; |
213
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|
249 break; |
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|
250 default: |
792
724bbec47f86
Use a new fatal_error function instead of calling fprintf and exit for fatal errors. This new function more gracefully handles the case in which BlastEm was not started from a terminal or disconnected from ther terminal (Windows).
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diff
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|
251 fatal_error("Unrecognized Z80 addressing mode %d\n", inst->addr_mode & 0x1F); |
213
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|
252 } |
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|
253 } |
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|
254 |
591
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|
255 void z80_save_ea(code_info *code, z80inst * inst, z80_options * opts) |
213
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|
256 { |
267
1788e3f29c28
Don't mix *H regs with the REX prefix
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266
diff
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|
257 if ((inst->addr_mode & 0x1F) == Z80_REG) { |
731
0835cd3dfc36
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730
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|
258 if (inst->ea_reg == Z80_IYH && opts->regs[Z80_IYL] >= 0) { |
312
cf7ecda060c7
Properly handle instructions that use boty IYH and IYL
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311
diff
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|
259 if (inst->reg == Z80_IYL) { |
591
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|
260 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W); |
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|
261 mov_rr(code, opts->gen.scratch1, opts->regs[Z80_IYL], SZ_B); |
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changeset
|
262 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W); |
312
cf7ecda060c7
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311
diff
changeset
|
263 } else { |
591
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changeset
|
264 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W); |
312
cf7ecda060c7
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311
diff
changeset
|
265 } |
267
1788e3f29c28
Don't mix *H regs with the REX prefix
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266
diff
changeset
|
266 } else if (inst->reg != Z80_UNUSED && inst->reg != Z80_USE_IMMED && opts->regs[inst->ea_reg] >= AH && opts->regs[inst->ea_reg] <= BH) { |
1788e3f29c28
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266
diff
changeset
|
267 uint8_t other_reg = opts->regs[inst->reg]; |
666
b68039895627
In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed
Michael Pavone <pavone@retrodev.com>
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665
diff
changeset
|
268 #ifdef X86_64 |
269
3c054d977175
Fix IX/IY displace modes. Fix check for registers requiring REX.
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268
diff
changeset
|
269 if (other_reg >= R8 || (other_reg >= RSP && other_reg <= RDI)) { |
267
1788e3f29c28
Don't mix *H regs with the REX prefix
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266
diff
changeset
|
270 //we can't mix an *H reg with a register that requires the REX prefix |
591
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changeset
|
271 ror_ir(code, 8, opts->regs[z80_low_reg(inst->ea_reg)], SZ_W); |
267
1788e3f29c28
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266
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|
272 } |
666
b68039895627
In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed
Michael Pavone <pavone@retrodev.com>
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diff
changeset
|
273 #endif |
267
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Don't mix *H regs with the REX prefix
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266
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|
274 } |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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|
275 } |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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|
276 } |
4d4559b04c59
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|
277 |
593
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|
278 void z80_save_result(z80_options *opts, z80inst * inst) |
213
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|
279 { |
253
3b34deba4ca0
Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
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252
diff
changeset
|
280 switch(inst->addr_mode & 0x1f) |
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|
281 { |
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|
282 case Z80_REG_INDIRECT: |
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|
283 case Z80_IMMED_INDIRECT: |
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|
284 case Z80_IX_DISPLACE: |
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|
285 case Z80_IY_DISPLACE: |
1045
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Implement half-carry for INC, DEC and NEG
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|
286 if (inst->op != Z80_LD) { |
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|
287 mov_rdispr(&opts->gen.code, opts->gen.context_reg, offsetof(z80_context, scratch1), opts->gen.scratch2, SZ_W); |
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|
288 } |
253
3b34deba4ca0
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|
289 if (z80_size(inst) == SZ_B) { |
593
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|
290 call(&opts->gen.code, opts->write_8); |
253
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|
291 } else { |
593
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changeset
|
292 call(&opts->gen.code, opts->write_16_lowfirst); |
253
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|
293 } |
213
4d4559b04c59
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|
294 } |
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Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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|
295 } |
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|
296 |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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changeset
|
297 enum { |
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|
298 DONT_READ=0, |
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|
299 READ |
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|
300 }; |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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|
301 |
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302 enum { |
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303 DONT_MODIFY=0, |
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304 MODIFY |
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305 }; |
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306 |
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307 void z80_print_regs_exit(z80_context * context) |
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308 { |
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309 printf("A: %X\nB: %X\nC: %X\nD: %X\nE: %X\nHL: %X\nIX: %X\nIY: %X\nSP: %X\n\nIM: %d, IFF1: %d, IFF2: %d\n", |
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310 context->regs[Z80_A], context->regs[Z80_B], context->regs[Z80_C], |
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311 context->regs[Z80_D], context->regs[Z80_E], |
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312 (context->regs[Z80_H] << 8) | context->regs[Z80_L], |
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313 (context->regs[Z80_IXH] << 8) | context->regs[Z80_IXL], |
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314 (context->regs[Z80_IYH] << 8) | context->regs[Z80_IYL], |
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315 context->sp, context->im, context->iff1, context->iff2); |
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316 puts("--Alternate Regs--"); |
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317 printf("A: %X\nB: %X\nC: %X\nD: %X\nE: %X\nHL: %X\nIX: %X\nIY: %X\n", |
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318 context->alt_regs[Z80_A], context->alt_regs[Z80_B], context->alt_regs[Z80_C], |
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319 context->alt_regs[Z80_D], context->alt_regs[Z80_E], |
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320 (context->alt_regs[Z80_H] << 8) | context->alt_regs[Z80_L], |
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321 (context->alt_regs[Z80_IXH] << 8) | context->alt_regs[Z80_IXL], |
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322 (context->alt_regs[Z80_IYH] << 8) | context->alt_regs[Z80_IYL]); |
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323 exit(0); |
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324 } |
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325 |
652 | 326 void translate_z80inst(z80inst * inst, z80_context * context, uint16_t address, uint8_t interp) |
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327 { |
591
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328 uint32_t num_cycles; |
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329 host_ea src_op, dst_op; |
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330 uint8_t size; |
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331 z80_options *opts = context->options; |
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332 uint8_t * start = opts->gen.code.cur; |
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333 code_info *code = &opts->gen.code; |
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334 if (!interp) { |
652 | 335 check_cycles_int(&opts->gen, address); |
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336 if (context->breakpoint_flags[address / 8] & (1 << (address % 8))) { |
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337 zbreakpoint_patch(context, address, start); |
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338 } |
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339 num_cycles = 4 * inst->opcode_bytes; |
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340 add_ir(code, inst->opcode_bytes > 1 ? 2 : 1, opts->regs[Z80_R], SZ_B); |
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341 #ifdef Z80_LOG_ADDRESS |
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342 log_address(&opts->gen, address, "Z80: %X @ %d\n"); |
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343 #endif |
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344 } |
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345 switch(inst->op) |
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346 { |
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347 case Z80_LD: |
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348 size = z80_size(inst); |
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349 switch (inst->addr_mode & 0x1F) |
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350 { |
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351 case Z80_REG: |
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352 case Z80_REG_INDIRECT: |
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353 if (size != SZ_B) { |
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354 num_cycles += 2; |
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355 } |
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356 if (inst->reg == Z80_I || inst->ea_reg == Z80_I || inst->reg == Z80_R || inst->ea_reg == Z80_R) { |
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357 num_cycles += 1; |
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358 } |
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359 break; |
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360 case Z80_IMMED: |
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361 num_cycles += size == SZ_B ? 3 : 6; |
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362 break; |
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363 case Z80_IMMED_INDIRECT: |
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364 num_cycles += 6; |
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365 break; |
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366 case Z80_IX_DISPLACE: |
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367 case Z80_IY_DISPLACE: |
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368 num_cycles += 8; //3 for displacement, 5 for address addition |
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369 break; |
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370 } |
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371 cycles(&opts->gen, num_cycles); |
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372 if (inst->addr_mode & Z80_DIR) { |
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373 translate_z80_ea(inst, &dst_op, opts, DONT_READ, MODIFY); |
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374 translate_z80_reg(inst, &src_op, opts); |
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375 } else { |
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376 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY); |
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377 translate_z80_reg(inst, &dst_op, opts); |
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378 } |
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379 if (inst->reg == Z80_R) { |
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380 mov_rr(code, opts->regs[Z80_A], opts->gen.scratch1, SZ_B); |
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381 mov_rr(code, opts->regs[Z80_A], opts->regs[Z80_R], SZ_B); |
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382 and_ir(code, 0x80, opts->gen.scratch1, SZ_B); |
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383 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zr_off(Z80_R), SZ_B); |
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384 } else if (inst->ea_reg == Z80_R && inst->addr_mode == Z80_REG) { |
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385 mov_rr(code, opts->regs[Z80_R], opts->regs[Z80_A], SZ_B); |
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386 and_ir(code, 0x7F, opts->regs[Z80_A], SZ_B); |
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387 or_rdispr(code, opts->gen.context_reg, zr_off(Z80_R), opts->regs[Z80_A], SZ_B); |
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388 } else if (src_op.mode == MODE_REG_DIRECT) { |
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389 if(dst_op.mode == MODE_REG_DISPLACE8) { |
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390 mov_rrdisp(code, src_op.base, dst_op.base, dst_op.disp, size); |
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391 } else { |
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392 mov_rr(code, src_op.base, dst_op.base, size); |
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393 } |
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394 } else if(src_op.mode == MODE_IMMED) { |
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395 if(dst_op.mode == MODE_REG_DISPLACE8) { |
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396 mov_irdisp(code, src_op.disp, dst_op.base, dst_op.disp, size); |
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397 } else { |
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398 mov_ir(code, src_op.disp, dst_op.base, size); |
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399 } |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff
changeset
|
400 } else { |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
401 if(dst_op.mode == MODE_REG_DISPLACE8) { |
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More bugfixes for the 32-bit build of the Z80 core
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729
diff
changeset
|
402 mov_rdispr(code, src_op.base, src_op.disp, opts->gen.scratch1, size); |
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diff
changeset
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403 mov_rrdisp(code, opts->gen.scratch1, dst_op.base, dst_op.disp, size); |
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diff
changeset
|
404 } else { |
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More bugfixes for the 32-bit build of the Z80 core
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729
diff
changeset
|
405 mov_rdispr(code, src_op.base, src_op.disp, dst_op.base, size); |
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|
406 } |
213
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Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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|
407 } |
842 | 408 if ((inst->ea_reg == Z80_I || inst->ea_reg == Z80_R) && inst->addr_mode == Z80_REG) { |
409 //ld a, i and ld a, r sets some flags | |
652 | 410 cmp_ir(code, 0, dst_op.base, SZ_B); |
411 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); | |
412 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); | |
821
21a69dfb6ee7
Implement half carry for a couple of the trivial cases
Michael Pavone <pavone@retrodev.com>
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819
diff
changeset
|
413 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);; |
652 | 414 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);; |
659
759c38bf97f8
Minor Z80 core cleanup
Michael Pavone <pavone@retrodev.com>
parents:
657
diff
changeset
|
415 mov_rdispr(code, opts->gen.context_reg, offsetof(z80_context, iff2), opts->gen.scratch1, SZ_B); |
652 | 416 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_PV), SZ_B); |
651
103d5cabbe14
Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents:
644
diff
changeset
|
417 } |
591
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418 z80_save_reg(inst, opts); |
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diff
changeset
|
419 z80_save_ea(code, inst, opts); |
235
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420 if (inst->addr_mode & Z80_DIR) { |
593
5ef3fe516da9
Z80 core is sort of working again
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592
diff
changeset
|
421 z80_save_result(opts, inst); |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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diff
changeset
|
422 } |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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diff
changeset
|
423 break; |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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diff
changeset
|
424 case Z80_PUSH: |
1044
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|
425 cycles(&opts->gen, num_cycles + 1); |
591
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426 sub_ir(code, 2, opts->regs[Z80_SP], SZ_W); |
235
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|
427 if (inst->reg == Z80_AF) { |
729
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
428 zreg_to_native(opts, Z80_A, opts->gen.scratch1); |
591
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diff
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|
429 shl_ir(code, 8, opts->gen.scratch1, SZ_W); |
1049
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|
430 mov_rdispr(code, opts->gen.context_reg, zf_off(ZF_XY), opts->gen.scratch1, SZ_B); |
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|
431 and_ir(code, 0x28, opts->gen.scratch1, SZ_B); |
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432 or_rdispr(code, opts->gen.context_reg, zf_off(ZF_C), opts->gen.scratch1, SZ_B); |
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|
433 ror_ir(code, 1, opts->gen.scratch1, SZ_B); |
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434 or_rdispr(code, opts->gen.context_reg, zf_off(ZF_N), opts->gen.scratch1, SZ_B); |
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435 ror_ir(code, 1, opts->gen.scratch1, SZ_B); |
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436 or_rdispr(code, opts->gen.context_reg, zf_off(ZF_PV), opts->gen.scratch1, SZ_B); |
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437 ror_ir(code, 2, opts->gen.scratch1, SZ_B); |
591
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438 or_rdispr(code, opts->gen.context_reg, zf_off(ZF_H), opts->gen.scratch1, SZ_B); |
1049
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439 ror_ir(code, 2, opts->gen.scratch1, SZ_B); |
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|
440 or_rdispr(code, opts->gen.context_reg, zf_off(ZF_Z), opts->gen.scratch1, SZ_B); |
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|
441 ror_ir(code, 1, opts->gen.scratch1, SZ_B); |
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changeset
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442 or_rdispr(code, opts->gen.context_reg, zf_off(ZF_S), opts->gen.scratch1, SZ_B); |
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443 ror_ir(code, 1, opts->gen.scratch1, SZ_B); |
235
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diff
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444 } else { |
731
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
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730
diff
changeset
|
445 zreg_to_native(opts, inst->reg, opts->gen.scratch1); |
235
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446 } |
591
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changeset
|
447 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch2, SZ_W); |
593
5ef3fe516da9
Z80 core is sort of working again
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parents:
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diff
changeset
|
448 call(code, opts->write_16_highfirst); |
235
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diff
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449 //no call to save_z80_reg needed since there's no chance we'll use the only |
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213
diff
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|
450 //the upper half of a register pair |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
451 break; |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
452 case Z80_POP: |
1044
1625555e346e
Properly handle redundant prefixes
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parents:
1043
diff
changeset
|
453 cycles(&opts->gen, num_cycles); |
591
966b46c68942
Get Z80 core back into compileable state
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590
diff
changeset
|
454 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W); |
593
5ef3fe516da9
Z80 core is sort of working again
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parents:
592
diff
changeset
|
455 call(code, opts->read_16); |
591
966b46c68942
Get Z80 core back into compileable state
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diff
changeset
|
456 add_ir(code, 2, opts->regs[Z80_SP], SZ_W); |
235
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Get Z80 core working for simple programs
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213
diff
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|
457 if (inst->reg == Z80_AF) { |
505
b7b7a1cab44a
The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
458 |
591
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Get Z80 core back into compileable state
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diff
changeset
|
459 bt_ir(code, 0, opts->gen.scratch1, SZ_W); |
966b46c68942
Get Z80 core back into compileable state
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parents:
590
diff
changeset
|
460 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
966b46c68942
Get Z80 core back into compileable state
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parents:
590
diff
changeset
|
461 bt_ir(code, 1, opts->gen.scratch1, SZ_W); |
966b46c68942
Get Z80 core back into compileable state
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diff
changeset
|
462 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_N)); |
966b46c68942
Get Z80 core back into compileable state
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parents:
590
diff
changeset
|
463 bt_ir(code, 2, opts->gen.scratch1, SZ_W); |
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Get Z80 core back into compileable state
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590
diff
changeset
|
464 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_PV)); |
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Get Z80 core back into compileable state
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590
diff
changeset
|
465 bt_ir(code, 4, opts->gen.scratch1, SZ_W); |
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Get Z80 core back into compileable state
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590
diff
changeset
|
466 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H)); |
966b46c68942
Get Z80 core back into compileable state
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parents:
590
diff
changeset
|
467 bt_ir(code, 6, opts->gen.scratch1, SZ_W); |
966b46c68942
Get Z80 core back into compileable state
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diff
changeset
|
468 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_Z)); |
966b46c68942
Get Z80 core back into compileable state
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parents:
590
diff
changeset
|
469 bt_ir(code, 7, opts->gen.scratch1, SZ_W); |
966b46c68942
Get Z80 core back into compileable state
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parents:
590
diff
changeset
|
470 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_S)); |
1049
ef7ee9919a73
Partial support for undocumented flag bits
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1048
diff
changeset
|
471 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
591
966b46c68942
Get Z80 core back into compileable state
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parents:
590
diff
changeset
|
472 shr_ir(code, 8, opts->gen.scratch1, SZ_W); |
729
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
473 native_to_zreg(opts, opts->gen.scratch1, Z80_A); |
235
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Get Z80 core working for simple programs
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213
diff
changeset
|
474 } else { |
731
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
475 native_to_zreg(opts, opts->gen.scratch1, inst->reg); |
235
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diff
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|
476 } |
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diff
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|
477 //no call to save_z80_reg needed since there's no chance we'll use the only |
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
478 //the upper half of a register pair |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff
changeset
|
479 break; |
241
2586d49ddd46
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|
480 case Z80_EX: |
591
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diff
changeset
|
481 cycles(&opts->gen, num_cycles); |
241
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|
482 if (inst->addr_mode == Z80_REG) { |
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239
diff
changeset
|
483 if(inst->reg == Z80_AF) { |
729
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
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parents:
716
diff
changeset
|
484 zreg_to_native(opts, Z80_A, opts->gen.scratch1); |
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Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
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parents:
716
diff
changeset
|
485 mov_rdispr(code, opts->gen.context_reg, zar_off(Z80_A), opts->gen.scratch2, SZ_B); |
591
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diff
changeset
|
486 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zar_off(Z80_A), SZ_B); |
729
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
487 native_to_zreg(opts, opts->gen.scratch2, Z80_A); |
505
b7b7a1cab44a
The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
488 |
241
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489 //Flags are currently word aligned, so we can move |
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490 //them efficiently a word at a time |
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491 for (int f = ZF_C; f < ZF_NUM; f+=2) { |
591
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changeset
|
492 mov_rdispr(code, opts->gen.context_reg, zf_off(f), opts->gen.scratch1, SZ_W); |
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493 mov_rdispr(code, opts->gen.context_reg, zaf_off(f), opts->gen.scratch2, SZ_W); |
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changeset
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494 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zaf_off(f), SZ_W); |
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changeset
|
495 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(f), SZ_W); |
241
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496 } |
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497 } else { |
729
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
498 if (opts->regs[Z80_DE] >= 0 && opts->regs[Z80_HL] >= 0) { |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
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parents:
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diff
changeset
|
499 xchg_rr(code, opts->regs[Z80_DE], opts->regs[Z80_HL], SZ_W); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
500 } else { |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
501 zreg_to_native(opts, Z80_DE, opts->gen.scratch1); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
502 zreg_to_native(opts, Z80_HL, opts->gen.scratch2); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
503 native_to_zreg(opts, opts->gen.scratch1, Z80_HL); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
504 native_to_zreg(opts, opts->gen.scratch2, Z80_DE); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
505 } |
241
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
506 } |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
507 } else { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
508 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
509 call(code, opts->read_8); |
729
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
510 if (opts->regs[inst->reg] >= 0) { |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
511 xchg_rr(code, opts->regs[inst->reg], opts->gen.scratch1, SZ_B); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
512 } else { |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
513 zreg_to_native(opts, inst->reg, opts->gen.scratch2); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
514 xchg_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
515 native_to_zreg(opts, opts->gen.scratch2, inst->reg); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
516 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
517 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch2, SZ_W); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
518 call(code, opts->write_8); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
519 cycles(&opts->gen, 1); |
241
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
520 uint8_t high_reg = z80_high_reg(inst->reg); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
521 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
522 add_ir(code, 1, opts->gen.scratch1, SZ_W); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
523 call(code, opts->read_8); |
729
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
524 if (opts->regs[inst->reg] >= 0) { |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
525 //even though some of the upper halves can be used directly |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
526 //the limitations on mixing *H regs with the REX prefix |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
527 //prevent us from taking advantage of it |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
528 uint8_t use_reg = opts->regs[inst->reg]; |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
529 ror_ir(code, 8, use_reg, SZ_W); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
530 xchg_rr(code, use_reg, opts->gen.scratch1, SZ_B); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
531 //restore reg to normal rotation |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
532 ror_ir(code, 8, use_reg, SZ_W); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
533 } else { |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
534 zreg_to_native(opts, high_reg, opts->gen.scratch2); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
535 xchg_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
536 native_to_zreg(opts, opts->gen.scratch2, high_reg); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
537 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
538 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch2, SZ_W); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
539 add_ir(code, 1, opts->gen.scratch2, SZ_W); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
540 call(code, opts->write_8); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
541 cycles(&opts->gen, 2); |
241
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
542 } |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
543 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
544 case Z80_EXX: |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
545 cycles(&opts->gen, num_cycles); |
729
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
546 zreg_to_native(opts, Z80_BC, opts->gen.scratch1); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
547 mov_rdispr(code, opts->gen.context_reg, zar_off(Z80_BC), opts->gen.scratch2, SZ_W); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
548 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zar_off(Z80_BC), SZ_W); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
549 native_to_zreg(opts, opts->gen.scratch2, Z80_BC); |
840
5822c6e5642f
Fix timing of IM instruction
Michael Pavone <pavone@retrodev.com>
parents:
828
diff
changeset
|
550 |
729
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
551 zreg_to_native(opts, Z80_HL, opts->gen.scratch1); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
552 mov_rdispr(code, opts->gen.context_reg, zar_off(Z80_HL), opts->gen.scratch2, SZ_W); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
553 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zar_off(Z80_HL), SZ_W); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
554 native_to_zreg(opts, opts->gen.scratch2, Z80_HL); |
840
5822c6e5642f
Fix timing of IM instruction
Michael Pavone <pavone@retrodev.com>
parents:
828
diff
changeset
|
555 |
729
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
556 zreg_to_native(opts, Z80_DE, opts->gen.scratch1); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
557 mov_rdispr(code, opts->gen.context_reg, zar_off(Z80_DE), opts->gen.scratch2, SZ_W); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
558 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zar_off(Z80_DE), SZ_W); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
559 native_to_zreg(opts, opts->gen.scratch2, Z80_DE); |
241
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
560 break; |
272 | 561 case Z80_LDI: { |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
562 cycles(&opts->gen, num_cycles); |
729
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
563 zreg_to_native(opts, Z80_HL, opts->gen.scratch1); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
564 call(code, opts->read_8); |
729
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
565 zreg_to_native(opts, Z80_DE, opts->gen.scratch2); |
1052
366c28ac6c55
Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents:
1051
diff
changeset
|
566 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
567 call(code, opts->write_8); |
1052
366c28ac6c55
Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents:
1051
diff
changeset
|
568 mov_rdispr(code, opts->gen.context_reg, zf_off(ZF_XY), opts->gen.scratch1, SZ_B); |
366c28ac6c55
Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents:
1051
diff
changeset
|
569 add_rr(code, opts->regs[Z80_A], opts->gen.scratch1, SZ_B); |
366c28ac6c55
Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents:
1051
diff
changeset
|
570 mov_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B); |
366c28ac6c55
Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents:
1051
diff
changeset
|
571 and_ir(code, 0x8, opts->gen.scratch1, SZ_B); |
366c28ac6c55
Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents:
1051
diff
changeset
|
572 shl_ir(code, 4, opts->gen.scratch2, SZ_B); |
366c28ac6c55
Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents:
1051
diff
changeset
|
573 or_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B); |
366c28ac6c55
Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents:
1051
diff
changeset
|
574 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
575 cycles(&opts->gen, 2); |
729
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
576 if (opts->regs[Z80_DE] >= 0) { |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
577 add_ir(code, 1, opts->regs[Z80_DE], SZ_W); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
578 } else { |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
579 add_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_DE), SZ_W); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
580 } |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
581 if (opts->regs[Z80_HL] >= 0) { |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
582 add_ir(code, 1, opts->regs[Z80_HL], SZ_W); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
583 } else { |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
584 add_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_W); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
585 } |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
586 if (opts->regs[Z80_BC] >= 0) { |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
587 sub_ir(code, 1, opts->regs[Z80_BC], SZ_W); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
588 } else { |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
589 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_BC), SZ_W); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
590 } |
821
21a69dfb6ee7
Implement half carry for a couple of the trivial cases
Michael Pavone <pavone@retrodev.com>
parents:
819
diff
changeset
|
591 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
592 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
593 setcc_rdisp(code, CC_NZ, opts->gen.context_reg, zf_off(ZF_PV)); |
272 | 594 break; |
595 } | |
261
f0c53a4bbfa3
Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write
Mike Pavone <pavone@retrodev.com>
parents:
259
diff
changeset
|
596 case Z80_LDIR: { |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
597 cycles(&opts->gen, num_cycles); |
729
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
598 zreg_to_native(opts, Z80_HL, opts->gen.scratch1); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
599 call(code, opts->read_8); |
729
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
600 zreg_to_native(opts, Z80_DE, opts->gen.scratch2); |
1052
366c28ac6c55
Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents:
1051
diff
changeset
|
601 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
602 call(code, opts->write_8); |
1052
366c28ac6c55
Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents:
1051
diff
changeset
|
603 mov_rdispr(code, opts->gen.context_reg, zf_off(ZF_XY), opts->gen.scratch1, SZ_B); |
366c28ac6c55
Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents:
1051
diff
changeset
|
604 add_rr(code, opts->regs[Z80_A], opts->gen.scratch1, SZ_B); |
366c28ac6c55
Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents:
1051
diff
changeset
|
605 mov_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B); |
366c28ac6c55
Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents:
1051
diff
changeset
|
606 and_ir(code, 0x8, opts->gen.scratch1, SZ_B); |
366c28ac6c55
Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents:
1051
diff
changeset
|
607 shl_ir(code, 4, opts->gen.scratch2, SZ_B); |
366c28ac6c55
Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents:
1051
diff
changeset
|
608 or_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B); |
366c28ac6c55
Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents:
1051
diff
changeset
|
609 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
729
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
610 if (opts->regs[Z80_DE] >= 0) { |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
611 add_ir(code, 1, opts->regs[Z80_DE], SZ_W); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
612 } else { |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
613 add_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_DE), SZ_W); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
614 } |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
615 if (opts->regs[Z80_HL] >= 0) { |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
616 add_ir(code, 1, opts->regs[Z80_HL], SZ_W); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
617 } else { |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
618 add_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_W); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
619 } |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
620 if (opts->regs[Z80_BC] >= 0) { |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
621 sub_ir(code, 1, opts->regs[Z80_BC], SZ_W); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
622 } else { |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
623 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_BC), SZ_W); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
624 } |
1043
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
625 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B); |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
626 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
627 uint8_t * cont = code->cur+1; |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
628 jcc(code, CC_Z, code->cur+2); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
629 cycles(&opts->gen, 7); |
1043
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
630 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_PV), SZ_B); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
631 jmp(code, start); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
632 *cont = code->cur - (cont + 1); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
633 cycles(&opts->gen, 2); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
634 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_PV), SZ_B); |
261
f0c53a4bbfa3
Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write
Mike Pavone <pavone@retrodev.com>
parents:
259
diff
changeset
|
635 break; |
f0c53a4bbfa3
Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write
Mike Pavone <pavone@retrodev.com>
parents:
259
diff
changeset
|
636 } |
273 | 637 case Z80_LDD: { |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
638 cycles(&opts->gen, num_cycles); |
729
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
639 zreg_to_native(opts, Z80_HL, opts->gen.scratch1); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
640 call(code, opts->read_8); |
729
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
641 zreg_to_native(opts, Z80_DE, opts->gen.scratch2); |
1052
366c28ac6c55
Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents:
1051
diff
changeset
|
642 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
643 call(code, opts->write_8); |
1052
366c28ac6c55
Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents:
1051
diff
changeset
|
644 mov_rdispr(code, opts->gen.context_reg, zf_off(ZF_XY), opts->gen.scratch1, SZ_B); |
366c28ac6c55
Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents:
1051
diff
changeset
|
645 add_rr(code, opts->regs[Z80_A], opts->gen.scratch1, SZ_B); |
366c28ac6c55
Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents:
1051
diff
changeset
|
646 mov_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B); |
366c28ac6c55
Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents:
1051
diff
changeset
|
647 and_ir(code, 0x8, opts->gen.scratch1, SZ_B); |
366c28ac6c55
Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents:
1051
diff
changeset
|
648 shl_ir(code, 4, opts->gen.scratch2, SZ_B); |
366c28ac6c55
Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents:
1051
diff
changeset
|
649 or_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B); |
366c28ac6c55
Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents:
1051
diff
changeset
|
650 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
651 cycles(&opts->gen, 2); |
729
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
652 if (opts->regs[Z80_DE] >= 0) { |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
653 sub_ir(code, 1, opts->regs[Z80_DE], SZ_W); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
654 } else { |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
655 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_DE), SZ_W); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
656 } |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
657 if (opts->regs[Z80_HL] >= 0) { |
828
22c3c52b9871
Fixed a copy pasta error in the implementation of LDD and LDDR. HL should be decremented and not incremented in those instructions.
Michael Pavone <pavone@retrodev.com>
parents:
821
diff
changeset
|
658 sub_ir(code, 1, opts->regs[Z80_HL], SZ_W); |
729
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
659 } else { |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
660 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_W); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
661 } |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
662 if (opts->regs[Z80_BC] >= 0) { |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
663 sub_ir(code, 1, opts->regs[Z80_BC], SZ_W); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
664 } else { |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
665 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_BC), SZ_W); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
666 } |
821
21a69dfb6ee7
Implement half carry for a couple of the trivial cases
Michael Pavone <pavone@retrodev.com>
parents:
819
diff
changeset
|
667 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
668 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
669 setcc_rdisp(code, CC_NZ, opts->gen.context_reg, zf_off(ZF_PV)); |
273 | 670 break; |
671 } | |
672 case Z80_LDDR: { | |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
673 cycles(&opts->gen, num_cycles); |
729
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
674 zreg_to_native(opts, Z80_HL, opts->gen.scratch1); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
675 call(code, opts->read_8); |
729
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
676 zreg_to_native(opts, Z80_DE, opts->gen.scratch2); |
1052
366c28ac6c55
Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents:
1051
diff
changeset
|
677 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
678 call(code, opts->write_8); |
1052
366c28ac6c55
Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents:
1051
diff
changeset
|
679 mov_rdispr(code, opts->gen.context_reg, zf_off(ZF_XY), opts->gen.scratch1, SZ_B); |
366c28ac6c55
Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents:
1051
diff
changeset
|
680 add_rr(code, opts->regs[Z80_A], opts->gen.scratch1, SZ_B); |
366c28ac6c55
Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents:
1051
diff
changeset
|
681 mov_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B); |
366c28ac6c55
Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents:
1051
diff
changeset
|
682 and_ir(code, 0x8, opts->gen.scratch1, SZ_B); |
366c28ac6c55
Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents:
1051
diff
changeset
|
683 shl_ir(code, 4, opts->gen.scratch2, SZ_B); |
366c28ac6c55
Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents:
1051
diff
changeset
|
684 or_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B); |
366c28ac6c55
Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents:
1051
diff
changeset
|
685 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
729
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
686 if (opts->regs[Z80_DE] >= 0) { |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
687 sub_ir(code, 1, opts->regs[Z80_DE], SZ_W); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
688 } else { |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
689 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_DE), SZ_W); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
690 } |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
691 if (opts->regs[Z80_HL] >= 0) { |
828
22c3c52b9871
Fixed a copy pasta error in the implementation of LDD and LDDR. HL should be decremented and not incremented in those instructions.
Michael Pavone <pavone@retrodev.com>
parents:
821
diff
changeset
|
692 sub_ir(code, 1, opts->regs[Z80_HL], SZ_W); |
729
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
693 } else { |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
694 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_W); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
695 } |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
696 if (opts->regs[Z80_BC] >= 0) { |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
697 sub_ir(code, 1, opts->regs[Z80_BC], SZ_W); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
698 } else { |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
699 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_BC), SZ_W); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
700 } |
1043
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
701 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B); |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
702 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
703 uint8_t * cont = code->cur+1; |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
704 jcc(code, CC_Z, code->cur+2); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
705 cycles(&opts->gen, 7); |
1043
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
706 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_PV), SZ_B); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
707 jmp(code, start); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
708 *cont = code->cur - (cont + 1); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
709 cycles(&opts->gen, 2); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
710 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_PV), SZ_B); |
273 | 711 break; |
712 } | |
1043
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
713 case Z80_CPI: |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
714 cycles(&opts->gen, num_cycles);//T-States 4,4 |
1043
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
715 zreg_to_native(opts, Z80_HL, opts->gen.scratch1); |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
716 call(code, opts->read_8);//T-States 3 |
1046
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
717 mov_rr(code, opts->regs[Z80_A], opts->gen.scratch2, SZ_B); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
718 sub_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B); |
1043
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
719 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
720 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
721 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
1046
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
722 xor_rr(code, opts->regs[Z80_A], opts->gen.scratch2, SZ_B); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
723 xor_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
724 bt_ir(code, 4, opts->gen.scratch2, SZ_B); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
725 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H)); |
1043
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
726 cycles(&opts->gen, 5);//T-States 5 |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
727 if (opts->regs[Z80_HL] >= 0) { |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
728 add_ir(code, 1, opts->regs[Z80_HL], SZ_W); |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
729 } else { |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
730 add_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_W); |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
731 } |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
732 if (opts->regs[Z80_BC] >= 0) { |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
733 sub_ir(code, 1, opts->regs[Z80_BC], SZ_W); |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
734 } else { |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
735 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_BC), SZ_W); |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
736 } |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
737 setcc_rdisp(code, CC_NZ, opts->gen.context_reg, zf_off(ZF_PV)); |
1051
11ff5726fd5e
Implement undocumented flag bits for block CP instructions
Michael Pavone <pavone@retrodev.com>
parents:
1050
diff
changeset
|
738 mov_rr(code, opts->regs[Z80_A], opts->gen.scratch2, SZ_B); |
11ff5726fd5e
Implement undocumented flag bits for block CP instructions
Michael Pavone <pavone@retrodev.com>
parents:
1050
diff
changeset
|
739 sub_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B); |
11ff5726fd5e
Implement undocumented flag bits for block CP instructions
Michael Pavone <pavone@retrodev.com>
parents:
1050
diff
changeset
|
740 sub_rdispr(code, opts->gen.context_reg, zf_off(ZF_H), opts->gen.scratch2, SZ_B); |
11ff5726fd5e
Implement undocumented flag bits for block CP instructions
Michael Pavone <pavone@retrodev.com>
parents:
1050
diff
changeset
|
741 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
11ff5726fd5e
Implement undocumented flag bits for block CP instructions
Michael Pavone <pavone@retrodev.com>
parents:
1050
diff
changeset
|
742 shl_ir(code, 4, opts->gen.scratch2, SZ_B); |
11ff5726fd5e
Implement undocumented flag bits for block CP instructions
Michael Pavone <pavone@retrodev.com>
parents:
1050
diff
changeset
|
743 and_irdisp(code, 0x8, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
11ff5726fd5e
Implement undocumented flag bits for block CP instructions
Michael Pavone <pavone@retrodev.com>
parents:
1050
diff
changeset
|
744 and_ir(code, 0x20, opts->gen.scratch2, SZ_B); |
11ff5726fd5e
Implement undocumented flag bits for block CP instructions
Michael Pavone <pavone@retrodev.com>
parents:
1050
diff
changeset
|
745 or_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
1043
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
746 break; |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
747 case Z80_CPIR: { |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
748 cycles(&opts->gen, num_cycles);//T-States 4,4 |
1043
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
749 zreg_to_native(opts, Z80_HL, opts->gen.scratch1); |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
750 call(code, opts->read_8);//T-States 3 |
1046
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
751 mov_rr(code, opts->regs[Z80_A], opts->gen.scratch2, SZ_B); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
752 sub_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B); |
1043
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
753 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
754 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
755 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
1046
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
756 xor_rr(code, opts->regs[Z80_A], opts->gen.scratch2, SZ_B); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
757 xor_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
758 bt_ir(code, 4, opts->gen.scratch2, SZ_B); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
759 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H)); |
1043
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
760 cycles(&opts->gen, 5);//T-States 5 |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
761 if (opts->regs[Z80_HL] >= 0) { |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
762 add_ir(code, 1, opts->regs[Z80_HL], SZ_W); |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
763 } else { |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
764 add_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_W); |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
765 } |
1051
11ff5726fd5e
Implement undocumented flag bits for block CP instructions
Michael Pavone <pavone@retrodev.com>
parents:
1050
diff
changeset
|
766 mov_rr(code, opts->regs[Z80_A], opts->gen.scratch2, SZ_B); |
11ff5726fd5e
Implement undocumented flag bits for block CP instructions
Michael Pavone <pavone@retrodev.com>
parents:
1050
diff
changeset
|
767 sub_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B); |
11ff5726fd5e
Implement undocumented flag bits for block CP instructions
Michael Pavone <pavone@retrodev.com>
parents:
1050
diff
changeset
|
768 sub_rdispr(code, opts->gen.context_reg, zf_off(ZF_H), opts->gen.scratch2, SZ_B); |
11ff5726fd5e
Implement undocumented flag bits for block CP instructions
Michael Pavone <pavone@retrodev.com>
parents:
1050
diff
changeset
|
769 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
11ff5726fd5e
Implement undocumented flag bits for block CP instructions
Michael Pavone <pavone@retrodev.com>
parents:
1050
diff
changeset
|
770 shl_ir(code, 4, opts->gen.scratch2, SZ_B); |
11ff5726fd5e
Implement undocumented flag bits for block CP instructions
Michael Pavone <pavone@retrodev.com>
parents:
1050
diff
changeset
|
771 and_irdisp(code, 0x8, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
11ff5726fd5e
Implement undocumented flag bits for block CP instructions
Michael Pavone <pavone@retrodev.com>
parents:
1050
diff
changeset
|
772 and_ir(code, 0x20, opts->gen.scratch2, SZ_B); |
11ff5726fd5e
Implement undocumented flag bits for block CP instructions
Michael Pavone <pavone@retrodev.com>
parents:
1050
diff
changeset
|
773 or_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
1043
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
774 if (opts->regs[Z80_BC] >= 0) { |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
775 sub_ir(code, 1, opts->regs[Z80_BC], SZ_W); |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
776 } else { |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
777 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_BC), SZ_W); |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
778 } |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
779 setcc_rdisp(code, CC_NZ, opts->gen.context_reg, zf_off(ZF_PV)); |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
780 uint8_t * cont = code->cur+1; |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
781 jcc(code, CC_Z, code->cur+2); |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
782 cmp_rr(code, opts->gen.scratch1, opts->regs[Z80_A], SZ_B); |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
783 uint8_t * cont2 = code->cur+1; |
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784 jcc(code, CC_Z, code->cur+2); |
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Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
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changeset
|
785 //repeat case |
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786 cycles(&opts->gen, 5);//T-States 5 |
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Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
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787 jmp(code, start); |
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Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
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|
788 *cont = code->cur - (cont + 1); |
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Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
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|
789 *cont2 = code->cur - (cont2 + 1); |
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Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
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790 break; |
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Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
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791 } |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
792 case Z80_CPD: |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
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diff
changeset
|
793 cycles(&opts->gen, num_cycles);//T-States 4,4 |
1043
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|
794 zreg_to_native(opts, Z80_HL, opts->gen.scratch1); |
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Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
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changeset
|
795 call(code, opts->read_8);//T-States 3 |
1046
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
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diff
changeset
|
796 mov_rr(code, opts->regs[Z80_A], opts->gen.scratch2, SZ_B); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
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|
797 sub_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B); |
1043
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798 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
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Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
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799 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
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|
800 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
1046
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
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changeset
|
801 xor_rr(code, opts->regs[Z80_A], opts->gen.scratch2, SZ_B); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
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changeset
|
802 xor_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
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803 bt_ir(code, 4, opts->gen.scratch2, SZ_B); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
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804 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H)); |
1043
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|
805 cycles(&opts->gen, 5);//T-States 5 |
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Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
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|
806 if (opts->regs[Z80_HL] >= 0) { |
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807 sub_ir(code, 1, opts->regs[Z80_HL], SZ_W); |
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808 } else { |
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809 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_W); |
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Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
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810 } |
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811 if (opts->regs[Z80_BC] >= 0) { |
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812 sub_ir(code, 1, opts->regs[Z80_BC], SZ_W); |
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813 } else { |
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814 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_BC), SZ_W); |
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815 } |
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Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
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816 setcc_rdisp(code, CC_NZ, opts->gen.context_reg, zf_off(ZF_PV)); |
1051
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817 mov_rr(code, opts->regs[Z80_A], opts->gen.scratch2, SZ_B); |
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Implement undocumented flag bits for block CP instructions
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818 sub_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B); |
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819 sub_rdispr(code, opts->gen.context_reg, zf_off(ZF_H), opts->gen.scratch2, SZ_B); |
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820 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
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821 shl_ir(code, 4, opts->gen.scratch2, SZ_B); |
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Implement undocumented flag bits for block CP instructions
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|
822 and_irdisp(code, 0x8, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
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|
823 and_ir(code, 0x20, opts->gen.scratch2, SZ_B); |
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Implement undocumented flag bits for block CP instructions
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|
824 or_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
1043
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|
825 break; |
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changeset
|
826 case Z80_CPDR: { |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
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diff
changeset
|
827 cycles(&opts->gen, num_cycles);//T-States 4,4 |
1043
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|
828 zreg_to_native(opts, Z80_HL, opts->gen.scratch1); |
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changeset
|
829 call(code, opts->read_8);//T-States 3 |
1046
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
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changeset
|
830 mov_rr(code, opts->regs[Z80_A], opts->gen.scratch2, SZ_B); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
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changeset
|
831 sub_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B); |
1043
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832 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
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833 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
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Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
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changeset
|
834 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
1046
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
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changeset
|
835 xor_rr(code, opts->regs[Z80_A], opts->gen.scratch2, SZ_B); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
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changeset
|
836 xor_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
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changeset
|
837 bt_ir(code, 4, opts->gen.scratch2, SZ_B); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
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changeset
|
838 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H)); |
1043
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|
839 cycles(&opts->gen, 5);//T-States 5 |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
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|
840 if (opts->regs[Z80_HL] >= 0) { |
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Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
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|
841 sub_ir(code, 1, opts->regs[Z80_HL], SZ_W); |
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|
842 } else { |
3980ef0f6307
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|
843 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_W); |
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|
844 } |
1051
11ff5726fd5e
Implement undocumented flag bits for block CP instructions
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changeset
|
845 mov_rr(code, opts->regs[Z80_A], opts->gen.scratch2, SZ_B); |
11ff5726fd5e
Implement undocumented flag bits for block CP instructions
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changeset
|
846 sub_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B); |
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|
847 sub_rdispr(code, opts->gen.context_reg, zf_off(ZF_H), opts->gen.scratch2, SZ_B); |
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changeset
|
848 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
11ff5726fd5e
Implement undocumented flag bits for block CP instructions
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changeset
|
849 shl_ir(code, 4, opts->gen.scratch2, SZ_B); |
11ff5726fd5e
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changeset
|
850 and_irdisp(code, 0x8, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
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changeset
|
851 and_ir(code, 0x20, opts->gen.scratch2, SZ_B); |
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|
852 or_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
1043
3980ef0f6307
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|
853 if (opts->regs[Z80_BC] >= 0) { |
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Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
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|
854 sub_ir(code, 1, opts->regs[Z80_BC], SZ_W); |
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|
855 } else { |
3980ef0f6307
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|
856 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_BC), SZ_W); |
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Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
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|
857 } |
3980ef0f6307
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|
858 setcc_rdisp(code, CC_NZ, opts->gen.context_reg, zf_off(ZF_PV)); |
3980ef0f6307
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|
859 uint8_t * cont = code->cur+1; |
3980ef0f6307
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|
860 jcc(code, CC_Z, code->cur+2); |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
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|
861 cmp_rr(code, opts->gen.scratch1, opts->regs[Z80_A], SZ_B); |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
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|
862 uint8_t * cont2 = code->cur+1; |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
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|
863 jcc(code, CC_Z, code->cur+2); |
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Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
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|
864 //repeat case |
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changeset
|
865 cycles(&opts->gen, 5);//T-States 5 |
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866 jmp(code, start); |
3980ef0f6307
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|
867 *cont = code->cur - (cont + 1); |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
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|
868 *cont2 = code->cur - (cont2 + 1); |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
869 break; |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
870 } |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
871 case Z80_ADD: |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
872 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
873 num_cycles += 8; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
874 } else if(inst->addr_mode == Z80_IMMED) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
875 num_cycles += 3; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
876 } else if(z80_size(inst) == SZ_W) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
877 num_cycles += 4; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
878 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
879 cycles(&opts->gen, num_cycles); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
880 translate_z80_reg(inst, &dst_op, opts); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
881 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY); |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
882 if (dst_op.mode == MODE_REG_DIRECT) { |
1046
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
883 mov_rr(code, dst_op.base, opts->gen.scratch2, z80_size(inst)); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
884 } else { |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
885 mov_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch2, z80_size(inst)); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
886 } |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
887 if (src_op.mode == MODE_REG_DIRECT) { |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
888 xor_rr(code, src_op.base, opts->gen.scratch2, z80_size(inst)); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
889 } else if (src_op.mode == MODE_IMMED) { |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
890 xor_ir(code, src_op.disp, opts->gen.scratch2, z80_size(inst)); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
891 } else { |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
892 xor_rdispr(code, src_op.base, src_op.disp, opts->gen.scratch2, z80_size(inst)); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
893 } |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
894 if (dst_op.mode == MODE_REG_DIRECT) { |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
895 if (src_op.mode == MODE_REG_DIRECT) { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
896 add_rr(code, src_op.base, dst_op.base, z80_size(inst)); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
897 } else if (src_op.mode == MODE_IMMED) { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
898 add_ir(code, src_op.disp, dst_op.base, z80_size(inst)); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
899 } else { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
900 add_rdispr(code, src_op.base, src_op.disp, dst_op.base, z80_size(inst)); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
901 } |
1049
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
902 if (z80_size(inst) == SZ_B) { |
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
903 mov_rrdisp(code, dst_op.base, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
904 } |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
905 } else { |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
906 if (src_op.mode == MODE_REG_DIRECT) { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
907 add_rrdisp(code, src_op.base, dst_op.base, dst_op.disp, z80_size(inst)); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
908 } else if (src_op.mode == MODE_IMMED) { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
909 add_irdisp(code, src_op.disp, dst_op.base, dst_op.disp, z80_size(inst)); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
910 } else { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
911 mov_rdispr(code, src_op.base, src_op.disp, opts->gen.scratch1, z80_size(inst)); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
912 add_rrdisp(code, opts->gen.scratch1, dst_op.base, dst_op.disp, z80_size(inst)); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
913 } |
1057
ff46d8fc2de8
Fix handling of undocumented flag bits for ADD in 32-bit builds
Michael Pavone <pavone@retrodev.com>
parents:
1056
diff
changeset
|
914 mov_rdispr(code, dst_op.base, dst_op.disp + (z80_size(inst) == SZ_B ? 0 : 1), opts->gen.scratch1, SZ_B); |
1049
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
915 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
916 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
917 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
918 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
919 if (z80_size(inst) == SZ_B) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
920 setcc_rdisp(code, CC_O, opts->gen.context_reg, zf_off(ZF_PV)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
921 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
922 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
923 } |
1046
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
924 if (dst_op.mode == MODE_REG_DIRECT) { |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
925 xor_rr(code, dst_op.base, opts->gen.scratch2, z80_size(inst)); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
926 } else { |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
927 xor_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch2, z80_size(inst)); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
928 } |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
929 bt_ir(code, z80_size(inst) == SZ_B ? 4 : 12, opts->gen.scratch2, z80_size(inst)); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
930 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H)); |
1049
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
931 if (z80_size(inst) == SZ_W & dst_op.mode == MODE_REG_DIRECT) { |
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
932 mov_rr(code, dst_op.base, opts->gen.scratch2, SZ_W); |
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
933 shr_ir(code, 8, opts->gen.scratch2, SZ_W); |
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
934 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
935 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
936 z80_save_reg(inst, opts); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
937 z80_save_ea(code, inst, opts); |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
938 break; |
248
9c7a3db7bcd0
Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents:
247
diff
changeset
|
939 case Z80_ADC: |
9c7a3db7bcd0
Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents:
247
diff
changeset
|
940 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
941 num_cycles += 8; |
248
9c7a3db7bcd0
Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents:
247
diff
changeset
|
942 } else if(inst->addr_mode == Z80_IMMED) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
943 num_cycles += 3; |
248
9c7a3db7bcd0
Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents:
247
diff
changeset
|
944 } else if(z80_size(inst) == SZ_W) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
945 num_cycles += 4; |
248
9c7a3db7bcd0
Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents:
247
diff
changeset
|
946 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
947 cycles(&opts->gen, num_cycles); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
948 translate_z80_reg(inst, &dst_op, opts); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
949 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY); |
1046
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
950 if (dst_op.mode == MODE_REG_DIRECT) { |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
951 mov_rr(code, dst_op.base, opts->gen.scratch2, z80_size(inst)); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
952 } else { |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
953 mov_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch2, z80_size(inst)); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
954 } |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
955 if (src_op.mode == MODE_REG_DIRECT) { |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
956 xor_rr(code, src_op.base, opts->gen.scratch2, z80_size(inst)); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
957 } else if (src_op.mode == MODE_IMMED) { |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
958 xor_ir(code, src_op.disp, opts->gen.scratch2, z80_size(inst)); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
959 } else { |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
960 xor_rdispr(code, src_op.base, src_op.disp, opts->gen.scratch2, z80_size(inst)); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
961 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
962 bt_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B); |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
963 if (dst_op.mode == MODE_REG_DIRECT) { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
964 if (src_op.mode == MODE_REG_DIRECT) { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
965 adc_rr(code, src_op.base, dst_op.base, z80_size(inst)); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
966 } else if (src_op.mode == MODE_IMMED) { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
967 adc_ir(code, src_op.disp, dst_op.base, z80_size(inst)); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
968 } else { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
969 adc_rdispr(code, src_op.base, src_op.disp, dst_op.base, z80_size(inst)); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
970 } |
1049
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
971 if (z80_size(inst) == SZ_B) { |
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
972 mov_rrdisp(code, dst_op.base, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
973 } |
248
9c7a3db7bcd0
Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents:
247
diff
changeset
|
974 } else { |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
975 if (src_op.mode == MODE_REG_DIRECT) { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
976 adc_rrdisp(code, src_op.base, dst_op.base, dst_op.disp, z80_size(inst)); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
977 } else if (src_op.mode == MODE_IMMED) { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
978 adc_irdisp(code, src_op.disp, dst_op.base, dst_op.disp, z80_size(inst)); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
979 } else { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
980 mov_rdispr(code, src_op.base, src_op.disp, opts->gen.scratch1, z80_size(inst)); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
981 adc_rrdisp(code, opts->gen.scratch1, dst_op.base, dst_op.disp, z80_size(inst)); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
982 } |
1049
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
983 mov_rdispr(code, dst_op.base, dst_op.disp + z80_size(inst) == SZ_B ? 0 : 8, opts->gen.scratch1, SZ_B); |
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
984 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
248
9c7a3db7bcd0
Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents:
247
diff
changeset
|
985 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
986 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
987 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
988 setcc_rdisp(code, CC_O, opts->gen.context_reg, zf_off(ZF_PV)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
989 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
990 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
1046
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
991 if (dst_op.mode == MODE_REG_DIRECT) { |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
992 xor_rr(code, dst_op.base, opts->gen.scratch2, z80_size(inst)); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
993 } else { |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
994 xor_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch2, z80_size(inst)); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
995 } |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
996 bt_ir(code, z80_size(inst) == SZ_B ? 4 : 12, opts->gen.scratch2, z80_size(inst)); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
997 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H)); |
1049
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
998 if (z80_size(inst) == SZ_W & dst_op.mode == MODE_REG_DIRECT) { |
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
999 mov_rr(code, dst_op.base, opts->gen.scratch2, SZ_W); |
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
1000 shr_ir(code, 8, opts->gen.scratch2, SZ_W); |
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
1001 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
1002 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1003 z80_save_reg(inst, opts); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1004 z80_save_ea(code, inst, opts); |
248
9c7a3db7bcd0
Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents:
247
diff
changeset
|
1005 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1006 case Z80_SUB: |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1007 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
1008 num_cycles += 8; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1009 } else if(inst->addr_mode == Z80_IMMED) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1010 num_cycles += 3; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1011 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1012 cycles(&opts->gen, num_cycles); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1013 translate_z80_reg(inst, &dst_op, opts); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1014 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY); |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1015 if (dst_op.mode == MODE_REG_DIRECT) { |
1046
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1016 mov_rr(code, dst_op.base, opts->gen.scratch2, z80_size(inst)); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1017 } else { |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1018 mov_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch2, z80_size(inst)); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1019 } |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1020 if (src_op.mode == MODE_REG_DIRECT) { |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1021 xor_rr(code, src_op.base, opts->gen.scratch2, z80_size(inst)); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1022 } else if (src_op.mode == MODE_IMMED) { |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1023 xor_ir(code, src_op.disp, opts->gen.scratch2, z80_size(inst)); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1024 } else { |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1025 xor_rdispr(code, src_op.base, src_op.disp, opts->gen.scratch2, z80_size(inst)); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1026 } |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1027 if (dst_op.mode == MODE_REG_DIRECT) { |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1028 if (src_op.mode == MODE_REG_DIRECT) { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1029 sub_rr(code, src_op.base, dst_op.base, z80_size(inst)); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1030 } else if (src_op.mode == MODE_IMMED) { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1031 sub_ir(code, src_op.disp, dst_op.base, z80_size(inst)); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1032 } else { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1033 sub_rdispr(code, src_op.base, src_op.disp, dst_op.base, z80_size(inst)); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1034 } |
1049
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
1035 if (z80_size(inst) == SZ_B) { |
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
1036 mov_rrdisp(code, dst_op.base, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
1037 } |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1038 } else { |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1039 if (src_op.mode == MODE_REG_DIRECT) { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1040 sub_rrdisp(code, src_op.base, dst_op.base, dst_op.disp, z80_size(inst)); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1041 } else if (src_op.mode == MODE_IMMED) { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1042 sub_irdisp(code, src_op.disp, dst_op.base, dst_op.disp, z80_size(inst)); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1043 } else { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1044 mov_rdispr(code, src_op.base, src_op.disp, opts->gen.scratch1, z80_size(inst)); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1045 sub_rrdisp(code, opts->gen.scratch1, dst_op.base, dst_op.disp, z80_size(inst)); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1046 } |
1049
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
1047 mov_rdispr(code, dst_op.base, dst_op.disp + z80_size(inst) == SZ_B ? 0 : 8, opts->gen.scratch1, SZ_B); |
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
1048 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1049 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1050 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1051 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1052 setcc_rdisp(code, CC_O, opts->gen.context_reg, zf_off(ZF_PV)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1053 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1054 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
1046
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1055 if (dst_op.mode == MODE_REG_DIRECT) { |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1056 xor_rr(code, dst_op.base, opts->gen.scratch2, z80_size(inst)); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1057 } else { |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1058 xor_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch2, z80_size(inst)); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1059 } |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1060 bt_ir(code, z80_size(inst) == SZ_B ? 4 : 12, opts->gen.scratch2, z80_size(inst)); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1061 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H)); |
1049
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
1062 if (z80_size(inst) == SZ_W & dst_op.mode == MODE_REG_DIRECT) { |
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
1063 mov_rr(code, dst_op.base, opts->gen.scratch2, SZ_W); |
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
1064 shr_ir(code, 8, opts->gen.scratch2, SZ_W); |
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
1065 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
1066 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1067 z80_save_reg(inst, opts); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1068 z80_save_ea(code, inst, opts); |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1069 break; |
248
9c7a3db7bcd0
Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents:
247
diff
changeset
|
1070 case Z80_SBC: |
9c7a3db7bcd0
Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents:
247
diff
changeset
|
1071 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
1072 num_cycles += 8; |
248
9c7a3db7bcd0
Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents:
247
diff
changeset
|
1073 } else if(inst->addr_mode == Z80_IMMED) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1074 num_cycles += 3; |
248
9c7a3db7bcd0
Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents:
247
diff
changeset
|
1075 } else if(z80_size(inst) == SZ_W) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1076 num_cycles += 4; |
248
9c7a3db7bcd0
Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents:
247
diff
changeset
|
1077 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1078 cycles(&opts->gen, num_cycles); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1079 translate_z80_reg(inst, &dst_op, opts); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1080 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY); |
1046
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1081 if (dst_op.mode == MODE_REG_DIRECT) { |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1082 mov_rr(code, dst_op.base, opts->gen.scratch2, z80_size(inst)); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1083 } else { |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1084 mov_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch2, z80_size(inst)); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1085 } |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1086 if (src_op.mode == MODE_REG_DIRECT) { |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1087 xor_rr(code, src_op.base, opts->gen.scratch2, z80_size(inst)); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1088 } else if (src_op.mode == MODE_IMMED) { |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1089 xor_ir(code, src_op.disp, opts->gen.scratch2, z80_size(inst)); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1090 } else { |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1091 xor_rdispr(code, src_op.base, src_op.disp, opts->gen.scratch2, z80_size(inst)); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1092 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1093 bt_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B); |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1094 if (dst_op.mode == MODE_REG_DIRECT) { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1095 if (src_op.mode == MODE_REG_DIRECT) { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1096 sbb_rr(code, src_op.base, dst_op.base, z80_size(inst)); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1097 } else if (src_op.mode == MODE_IMMED) { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1098 sbb_ir(code, src_op.disp, dst_op.base, z80_size(inst)); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1099 } else { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1100 sbb_rdispr(code, src_op.base, src_op.disp, dst_op.base, z80_size(inst)); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1101 } |
1049
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
1102 if (z80_size(inst) == SZ_B) { |
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
1103 mov_rrdisp(code, dst_op.base, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
1104 } |
248
9c7a3db7bcd0
Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents:
247
diff
changeset
|
1105 } else { |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1106 if (src_op.mode == MODE_REG_DIRECT) { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1107 sbb_rrdisp(code, src_op.base, dst_op.base, dst_op.disp, z80_size(inst)); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1108 } else if (src_op.mode == MODE_IMMED) { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1109 sbb_irdisp(code, src_op.disp, dst_op.base, dst_op.disp, z80_size(inst)); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1110 } else { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1111 mov_rdispr(code, src_op.base, src_op.disp, opts->gen.scratch1, z80_size(inst)); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1112 sbb_rrdisp(code, opts->gen.scratch1, dst_op.base, dst_op.disp, z80_size(inst)); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1113 } |
1049
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
1114 mov_rdispr(code, dst_op.base, dst_op.disp + z80_size(inst) == SZ_B ? 0 : 8, opts->gen.scratch1, SZ_B); |
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
1115 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
248
9c7a3db7bcd0
Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents:
247
diff
changeset
|
1116 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1117 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1118 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1119 setcc_rdisp(code, CC_O, opts->gen.context_reg, zf_off(ZF_PV)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1120 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1121 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
1046
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1122 if (dst_op.mode == MODE_REG_DIRECT) { |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1123 xor_rr(code, dst_op.base, opts->gen.scratch2, z80_size(inst)); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1124 } else { |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1125 xor_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch2, z80_size(inst)); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1126 } |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1127 bt_ir(code, z80_size(inst) == SZ_B ? 4 : 12, opts->gen.scratch2, z80_size(inst)); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1128 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H)); |
1049
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
1129 if (z80_size(inst) == SZ_W & dst_op.mode == MODE_REG_DIRECT) { |
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
1130 mov_rr(code, dst_op.base, opts->gen.scratch2, SZ_W); |
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
1131 shr_ir(code, 8, opts->gen.scratch2, SZ_W); |
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
1132 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
1133 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1134 z80_save_reg(inst, opts); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1135 z80_save_ea(code, inst, opts); |
248
9c7a3db7bcd0
Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents:
247
diff
changeset
|
1136 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1137 case Z80_AND: |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1138 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
1139 num_cycles += 8; |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1140 } else if(inst->addr_mode == Z80_IMMED) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1141 num_cycles += 3; |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1142 } else if(z80_size(inst) == SZ_W) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1143 num_cycles += 4; |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1144 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1145 cycles(&opts->gen, num_cycles); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1146 translate_z80_reg(inst, &dst_op, opts); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1147 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY); |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1148 if (src_op.mode == MODE_REG_DIRECT) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1149 and_rr(code, src_op.base, dst_op.base, z80_size(inst)); |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1150 } else if (src_op.mode == MODE_IMMED) { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1151 and_ir(code, src_op.disp, dst_op.base, z80_size(inst)); |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1152 } else { |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1153 and_rdispr(code, src_op.base, src_op.disp, dst_op.base, z80_size(inst)); |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1154 } |
1049
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
1155 mov_rrdisp(code, dst_op.base, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1156 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
1042
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1157 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B); |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1158 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_H), SZ_B); |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1159 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV)); |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1160 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1161 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1162 z80_save_reg(inst, opts); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1163 z80_save_ea(code, inst, opts); |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1164 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1165 case Z80_OR: |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1166 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
1167 num_cycles += 8; |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1168 } else if(inst->addr_mode == Z80_IMMED) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1169 num_cycles += 3; |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1170 } else if(z80_size(inst) == SZ_W) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1171 num_cycles += 4; |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1172 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1173 cycles(&opts->gen, num_cycles); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1174 translate_z80_reg(inst, &dst_op, opts); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1175 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY); |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1176 if (src_op.mode == MODE_REG_DIRECT) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1177 or_rr(code, src_op.base, dst_op.base, z80_size(inst)); |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1178 } else if (src_op.mode == MODE_IMMED) { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1179 or_ir(code, src_op.disp, dst_op.base, z80_size(inst)); |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1180 } else { |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1181 or_rdispr(code, src_op.base, src_op.disp, dst_op.base, z80_size(inst)); |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1182 } |
1049
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
1183 mov_rrdisp(code, dst_op.base, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1184 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
1042
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1185 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B); |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1186 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B); |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1187 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV)); |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1188 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1189 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1190 z80_save_reg(inst, opts); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1191 z80_save_ea(code, inst, opts); |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1192 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1193 case Z80_XOR: |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1194 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
1195 num_cycles += 8; |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1196 } else if(inst->addr_mode == Z80_IMMED) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1197 num_cycles += 3; |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1198 } else if(z80_size(inst) == SZ_W) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1199 num_cycles += 4; |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1200 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1201 cycles(&opts->gen, num_cycles); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1202 translate_z80_reg(inst, &dst_op, opts); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1203 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY); |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1204 if (src_op.mode == MODE_REG_DIRECT) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1205 xor_rr(code, src_op.base, dst_op.base, z80_size(inst)); |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1206 } else if (src_op.mode == MODE_IMMED) { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1207 xor_ir(code, src_op.disp, dst_op.base, z80_size(inst)); |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1208 } else { |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1209 xor_rdispr(code, src_op.base, src_op.disp, dst_op.base, z80_size(inst)); |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1210 } |
1049
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
1211 mov_rrdisp(code, dst_op.base, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1212 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
1042
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1213 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B); |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1214 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B); |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1215 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV)); |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1216 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1217 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1218 z80_save_reg(inst, opts); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1219 z80_save_ea(code, inst, opts); |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1220 break; |
242 | 1221 case Z80_CP: |
1222 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { | |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
1223 num_cycles += 8; |
242 | 1224 } else if(inst->addr_mode == Z80_IMMED) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1225 num_cycles += 3; |
242 | 1226 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1227 cycles(&opts->gen, num_cycles); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1228 translate_z80_reg(inst, &dst_op, opts); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1229 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY); |
1046
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1230 mov_rr(code, dst_op.base, opts->gen.scratch2, z80_size(inst)); |
242 | 1231 if (src_op.mode == MODE_REG_DIRECT) { |
1046
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1232 sub_rr(code, src_op.base, opts->gen.scratch2, z80_size(inst)); |
1049
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
1233 mov_rrdisp(code, src_op.base, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1234 } else if (src_op.mode == MODE_IMMED) { |
1046
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1235 sub_ir(code, src_op.disp, opts->gen.scratch2, z80_size(inst)); |
1049
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
1236 mov_irdisp(code, src_op.disp, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
242 | 1237 } else { |
1046
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1238 sub_rdispr(code, src_op.base, src_op.disp, opts->gen.scratch2, z80_size(inst)); |
1049
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
1239 mov_rdispr(code, src_op.base, src_op.disp, opts->gen.scratch1, SZ_B); |
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
1240 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
242 | 1241 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1242 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1243 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1244 setcc_rdisp(code, CC_O, opts->gen.context_reg, zf_off(ZF_PV)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1245 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1246 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
1046
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1247 xor_rr(code, dst_op.base, opts->gen.scratch2, z80_size(inst)); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1248 if (src_op.mode == MODE_REG_DIRECT) { |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1249 xor_rr(code, src_op.base, opts->gen.scratch2, z80_size(inst)); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1250 } else if (src_op.mode == MODE_IMMED) { |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1251 xor_ir(code, src_op.disp, opts->gen.scratch2, z80_size(inst)); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1252 } else { |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1253 xor_rdispr(code, src_op.base, src_op.disp, opts->gen.scratch2, z80_size(inst)); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1254 } |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1255 bt_ir(code, 4, opts->gen.scratch2, SZ_B); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1256 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H)); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1257 z80_save_reg(inst, opts); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1258 z80_save_ea(code, inst, opts); |
242 | 1259 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1260 case Z80_INC: |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1261 case Z80_DEC: |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
1262 if(z80_size(inst) == SZ_W) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1263 num_cycles += 2; |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1264 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1265 cycles(&opts->gen, num_cycles); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1266 translate_z80_reg(inst, &dst_op, opts); |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1267 if (dst_op.mode == MODE_UNUSED) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1268 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY); |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1269 } |
1045
e0489abfdab0
Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents:
1044
diff
changeset
|
1270 if (z80_size(inst) == SZ_B) { |
e0489abfdab0
Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents:
1044
diff
changeset
|
1271 if (dst_op.mode == MODE_REG_DIRECT) { |
e0489abfdab0
Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents:
1044
diff
changeset
|
1272 if (dst_op.base >= AH && dst_op.base <= BH) { |
e0489abfdab0
Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents:
1044
diff
changeset
|
1273 mov_rr(code, dst_op.base - AH, opts->gen.scratch2, SZ_W); |
e0489abfdab0
Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents:
1044
diff
changeset
|
1274 } else { |
e0489abfdab0
Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents:
1044
diff
changeset
|
1275 mov_rr(code, dst_op.base, opts->gen.scratch2, SZ_B); |
e0489abfdab0
Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents:
1044
diff
changeset
|
1276 } |
e0489abfdab0
Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents:
1044
diff
changeset
|
1277 } else { |
e0489abfdab0
Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents:
1044
diff
changeset
|
1278 mov_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch2, SZ_B); |
e0489abfdab0
Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents:
1044
diff
changeset
|
1279 } |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1280 } |
1045
e0489abfdab0
Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents:
1044
diff
changeset
|
1281 if (inst->op == Z80_INC) { |
e0489abfdab0
Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents:
1044
diff
changeset
|
1282 if (dst_op.mode == MODE_REG_DIRECT) { |
e0489abfdab0
Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents:
1044
diff
changeset
|
1283 add_ir(code, 1, dst_op.base, z80_size(inst)); |
e0489abfdab0
Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents:
1044
diff
changeset
|
1284 } else { |
e0489abfdab0
Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents:
1044
diff
changeset
|
1285 add_irdisp(code, 1, dst_op.base, dst_op.disp, z80_size(inst)); |
e0489abfdab0
Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents:
1044
diff
changeset
|
1286 } |
e0489abfdab0
Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents:
1044
diff
changeset
|
1287 } else { |
e0489abfdab0
Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents:
1044
diff
changeset
|
1288 if (dst_op.mode == MODE_REG_DIRECT) { |
e0489abfdab0
Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents:
1044
diff
changeset
|
1289 sub_ir(code, 1, dst_op.base, z80_size(inst)); |
e0489abfdab0
Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents:
1044
diff
changeset
|
1290 } else { |
e0489abfdab0
Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents:
1044
diff
changeset
|
1291 sub_irdisp(code, 1, dst_op.base, dst_op.disp, z80_size(inst)); |
e0489abfdab0
Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents:
1044
diff
changeset
|
1292 } |
e0489abfdab0
Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents:
1044
diff
changeset
|
1293 } |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1294 if (z80_size(inst) == SZ_B) { |
1045
e0489abfdab0
Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents:
1044
diff
changeset
|
1295 mov_irdisp(code, inst->op == Z80_DEC, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1296 setcc_rdisp(code, CC_O, opts->gen.context_reg, zf_off(ZF_PV)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1297 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1298 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
1045
e0489abfdab0
Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents:
1044
diff
changeset
|
1299 int bit = 4; |
e0489abfdab0
Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents:
1044
diff
changeset
|
1300 if (dst_op.mode == MODE_REG_DIRECT) { |
1049
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
1301 mov_rrdisp(code, dst_op.base, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
1045
e0489abfdab0
Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents:
1044
diff
changeset
|
1302 if (dst_op.base >= AH && dst_op.base <= BH) { |
e0489abfdab0
Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents:
1044
diff
changeset
|
1303 bit = 12; |
e0489abfdab0
Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents:
1044
diff
changeset
|
1304 xor_rr(code, dst_op.base - AH, opts->gen.scratch2, SZ_W); |
e0489abfdab0
Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents:
1044
diff
changeset
|
1305 } else { |
e0489abfdab0
Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents:
1044
diff
changeset
|
1306 xor_rr(code, dst_op.base, opts->gen.scratch2, SZ_B); |
e0489abfdab0
Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents:
1044
diff
changeset
|
1307 } |
e0489abfdab0
Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents:
1044
diff
changeset
|
1308 } else { |
1049
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
1309 mov_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch1, SZ_B); |
1045
e0489abfdab0
Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents:
1044
diff
changeset
|
1310 xor_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch2, SZ_B); |
1049
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
1311 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
1045
e0489abfdab0
Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents:
1044
diff
changeset
|
1312 } |
e0489abfdab0
Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents:
1044
diff
changeset
|
1313 bt_ir(code, bit, opts->gen.scratch2, SZ_W); |
e0489abfdab0
Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents:
1044
diff
changeset
|
1314 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H)); |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1315 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1316 z80_save_reg(inst, opts); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1317 z80_save_ea(code, inst, opts); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
1318 z80_save_result(opts, inst); |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1319 break; |
1046
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1320 case Z80_DAA: { |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
1321 cycles(&opts->gen, num_cycles); |
1042
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1322 xor_rr(code, opts->gen.scratch2, opts->gen.scratch2, SZ_B); |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1323 zreg_to_native(opts, Z80_A, opts->gen.scratch1); |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1324 and_ir(code, 0xF, opts->gen.scratch1, SZ_B); |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1325 cmp_ir(code, 0xA, opts->gen.scratch1, SZ_B); |
1046
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1326 mov_ir(code, 0xA0, opts->gen.scratch1, SZ_B); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1327 code_ptr corf_low_range = code->cur + 1; |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1328 jcc(code, CC_NC, code->cur+2); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1329 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1330 code_ptr corf_low = code->cur + 1; |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1331 jcc(code, CC_NZ, code->cur+2); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1332 code_ptr no_corf_low = code->cur + 1; |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1333 jmp(code, code->cur + 2); |
1042
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1334 |
1046
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1335 *corf_low_range = code->cur - (corf_low_range + 1); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1336 mov_ir(code, 0x90, opts->gen.scratch1, SZ_B); |
1042
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1337 *corf_low = code->cur - (corf_low + 1); |
1046
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1338 mov_ir(code, 0x06, opts->gen.scratch2, SZ_B); |
1042
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1339 |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1340 *no_corf_low = code->cur - (no_corf_low + 1); |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1341 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B); |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1342 code_ptr corf_high = code->cur+1; |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1343 jcc(code, CC_NZ, code->cur+2); |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1344 cmp_rr(code, opts->gen.scratch1, opts->regs[Z80_A], SZ_B); |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1345 code_ptr no_corf_high = code->cur+1; |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1346 jcc(code, CC_C, code->cur+2); |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1347 *corf_high = code->cur - (corf_high + 1); |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1348 or_ir(code, 0x60, opts->gen.scratch2, SZ_B); |
1046
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1349 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_C), SZ_B); |
1042
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1350 *no_corf_high = code->cur - (no_corf_high + 1); |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1351 |
1046
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1352 mov_rr(code, opts->regs[Z80_A], opts->gen.scratch1, SZ_B); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1353 xor_rr(code, opts->gen.scratch2, opts->gen.scratch1, SZ_B); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1354 |
1042
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1355 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1356 code_ptr not_sub = code->cur+1; |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1357 jcc(code, CC_Z, code->cur+2); |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1358 neg_r(code, opts->gen.scratch2, SZ_B); |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1359 *not_sub = code->cur - (not_sub + 1); |
1046
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1360 |
1042
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1361 add_rr(code, opts->gen.scratch2, opts->regs[Z80_A], SZ_B); |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1362 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1363 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1364 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV)); |
1046
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1365 xor_rr(code, opts->regs[Z80_A], opts->gen.scratch1, SZ_B); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1366 bt_ir(code, 4, opts->gen.scratch1, SZ_B); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1367 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H)); |
1050
d06c947a9a77
Implement undoumented flag bits for DAA, CPL, SCF and CCF
Michael Pavone <pavone@retrodev.com>
parents:
1049
diff
changeset
|
1368 mov_rrdisp(code, opts->regs[Z80_A], opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
1042
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1369 break; |
1046
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1370 } |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1371 case Z80_CPL: |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
1372 cycles(&opts->gen, num_cycles); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1373 not_r(code, opts->regs[Z80_A], SZ_B); |
1042
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1374 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_H), SZ_B); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1375 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
1050
d06c947a9a77
Implement undoumented flag bits for DAA, CPL, SCF and CCF
Michael Pavone <pavone@retrodev.com>
parents:
1049
diff
changeset
|
1376 mov_rrdisp(code, opts->regs[Z80_A], opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
274
be2b845d3e94
Implement CPL and NEG (untested)
Mike Pavone <pavone@retrodev.com>
parents:
273
diff
changeset
|
1377 break; |
be2b845d3e94
Implement CPL and NEG (untested)
Mike Pavone <pavone@retrodev.com>
parents:
273
diff
changeset
|
1378 case Z80_NEG: |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
1379 cycles(&opts->gen, num_cycles); |
1045
e0489abfdab0
Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents:
1044
diff
changeset
|
1380 mov_rr(code, opts->regs[Z80_A], opts->gen.scratch2, SZ_B); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1381 neg_r(code, opts->regs[Z80_A], SZ_B); |
1056
47c748455365
Fixed bug introduced in NEG with addition of undocumented flags
Michael Pavone <pavone@retrodev.com>
parents:
1055
diff
changeset
|
1382 mov_rrdisp(code, opts->regs[Z80_A], opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1383 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1384 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1385 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1386 setcc_rdisp(code, CC_O, opts->gen.context_reg, zf_off(ZF_PV)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1387 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
1045
e0489abfdab0
Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents:
1044
diff
changeset
|
1388 xor_rr(code, opts->regs[Z80_A], opts->gen.scratch2, SZ_B); |
e0489abfdab0
Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents:
1044
diff
changeset
|
1389 bt_ir(code, 4, opts->gen.scratch2, SZ_B); |
e0489abfdab0
Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents:
1044
diff
changeset
|
1390 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H)); |
274
be2b845d3e94
Implement CPL and NEG (untested)
Mike Pavone <pavone@retrodev.com>
parents:
273
diff
changeset
|
1391 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1392 case Z80_CCF: |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
1393 cycles(&opts->gen, num_cycles); |
1042
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1394 mov_rdispr(code, opts->gen.context_reg, zf_off(ZF_C), opts->gen.scratch1, SZ_B); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1395 xor_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_C), SZ_B); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1396 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
1042
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1397 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_H), SZ_B); |
1050
d06c947a9a77
Implement undoumented flag bits for DAA, CPL, SCF and CCF
Michael Pavone <pavone@retrodev.com>
parents:
1049
diff
changeset
|
1398 mov_rrdisp(code, opts->regs[Z80_A], opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
257 | 1399 break; |
1400 case Z80_SCF: | |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
1401 cycles(&opts->gen, num_cycles); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1402 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_C), SZ_B); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1403 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
1042
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1404 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B); |
1050
d06c947a9a77
Implement undoumented flag bits for DAA, CPL, SCF and CCF
Michael Pavone <pavone@retrodev.com>
parents:
1049
diff
changeset
|
1405 mov_rrdisp(code, opts->regs[Z80_A], opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
257 | 1406 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1407 case Z80_NOP: |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
1408 cycles(&opts->gen, num_cycles); |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1409 break; |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
1410 case Z80_HALT: { |
667
30ccf56842d6
All cycle counters are now based off the master clock. This seems to have messed up Z80 interrupt timing (music in Sonic 2 is too slow for instance), but things are generally working
Michael Pavone <pavone@retrodev.com>
parents:
666
diff
changeset
|
1411 code_ptr loop_top = code->cur; |
30ccf56842d6
All cycle counters are now based off the master clock. This seems to have messed up Z80 interrupt timing (music in Sonic 2 is too slow for instance), but things are generally working
Michael Pavone <pavone@retrodev.com>
parents:
666
diff
changeset
|
1412 //this isn't terribly efficient, but it's good enough for now |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
1413 cycles(&opts->gen, num_cycles); |
1147
06468b25a543
Fix implementation of Z80 HALT instruction
Michael Pavone <pavone@retrodev.com>
parents:
1142
diff
changeset
|
1414 check_cycles_int(&opts->gen, address+1); |
667
30ccf56842d6
All cycle counters are now based off the master clock. This seems to have messed up Z80 interrupt timing (music in Sonic 2 is too slow for instance), but things are generally working
Michael Pavone <pavone@retrodev.com>
parents:
666
diff
changeset
|
1415 jmp(code, loop_top); |
285
021aeb6df19b
Implement HALT (sort of tested)
Mike Pavone <pavone@retrodev.com>
parents:
284
diff
changeset
|
1416 break; |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
1417 } |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1418 case Z80_DI: |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
1419 cycles(&opts->gen, num_cycles); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1420 mov_irdisp(code, 0, opts->gen.context_reg, offsetof(z80_context, iff1), SZ_B); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1421 mov_irdisp(code, 0, opts->gen.context_reg, offsetof(z80_context, iff2), SZ_B); |
1110
d1eed3b1121c
Fix a couple of timing regressions in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1062
diff
changeset
|
1422 //turn cycles remaining into current cycle |
d1eed3b1121c
Fix a couple of timing regressions in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1062
diff
changeset
|
1423 neg_r(code, opts->gen.cycles, SZ_D); |
1047
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
1424 add_rdispr(code, opts->gen.context_reg, offsetof(z80_context, target_cycle), opts->gen.cycles, SZ_D); |
1110
d1eed3b1121c
Fix a couple of timing regressions in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1062
diff
changeset
|
1425 //set interrupt cycle to never and fetch the new target cycle from sync_cycle |
1047
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
1426 mov_rdispr(code, opts->gen.context_reg, offsetof(z80_context, sync_cycle), opts->gen.scratch1, SZ_D); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1427 mov_irdisp(code, 0xFFFFFFFF, opts->gen.context_reg, offsetof(z80_context, int_cycle), SZ_D); |
1047
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
1428 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, offsetof(z80_context, target_cycle), SZ_D); |
1110
d1eed3b1121c
Fix a couple of timing regressions in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1062
diff
changeset
|
1429 //turn current cycle back into cycles remaining |
d1eed3b1121c
Fix a couple of timing regressions in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1062
diff
changeset
|
1430 neg_r(code, opts->gen.cycles, SZ_D); |
d1eed3b1121c
Fix a couple of timing regressions in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1062
diff
changeset
|
1431 add_rr(code, opts->gen.scratch1, opts->gen.cycles, SZ_D); |
243
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
1432 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1433 case Z80_EI: |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
1434 cycles(&opts->gen, num_cycles); |
1047
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
1435 neg_r(code, opts->gen.cycles, SZ_D); |
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
1436 add_rdispr(code, opts->gen.context_reg, offsetof(z80_context, target_cycle), opts->gen.cycles, SZ_D); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1437 mov_rrdisp(code, opts->gen.cycles, opts->gen.context_reg, offsetof(z80_context, int_enable_cycle), SZ_D); |
1047
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
1438 neg_r(code, opts->gen.cycles, SZ_D); |
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
1439 add_rdispr(code, opts->gen.context_reg, offsetof(z80_context, target_cycle), opts->gen.cycles, SZ_D); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1440 mov_irdisp(code, 1, opts->gen.context_reg, offsetof(z80_context, iff1), SZ_B); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1441 mov_irdisp(code, 1, opts->gen.context_reg, offsetof(z80_context, iff2), SZ_B); |
335 | 1442 //interrupt enable has a one-instruction latency, minimum instruction duration is 4 cycles |
667
30ccf56842d6
All cycle counters are now based off the master clock. This seems to have messed up Z80 interrupt timing (music in Sonic 2 is too slow for instance), but things are generally working
Michael Pavone <pavone@retrodev.com>
parents:
666
diff
changeset
|
1443 add_irdisp(code, 4*opts->gen.clock_divider, opts->gen.context_reg, offsetof(z80_context, int_enable_cycle), SZ_D); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
1444 call(code, opts->do_sync); |
243
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
1445 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1446 case Z80_IM: |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
1447 cycles(&opts->gen, num_cycles); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1448 mov_irdisp(code, inst->immed, opts->gen.context_reg, offsetof(z80_context, im), SZ_B); |
243
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
1449 break; |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1450 case Z80_RLC: |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
1451 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
1452 num_cycles += 8; |
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
1453 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1454 cycles(&opts->gen, num_cycles); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1455 if (inst->addr_mode != Z80_UNUSED) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1456 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1457 translate_z80_reg(inst, &src_op, opts); //For IX/IY variants that also write to a register |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1458 cycles(&opts->gen, 1); |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1459 } else { |
302
3b831fe32c15
More fixes for confusion between Z80_UNUSED and MODE_UNUSED
Mike Pavone <pavone@retrodev.com>
parents:
301
diff
changeset
|
1460 src_op.mode = MODE_UNUSED; |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1461 translate_z80_reg(inst, &dst_op, opts); |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1462 } |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1463 if (dst_op.mode == MODE_REG_DIRECT) { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1464 rol_ir(code, 1, dst_op.base, SZ_B); |
1053
b86c3ce007d9
Implemented undocumented flag bits for rotate instructions
Michael Pavone <pavone@retrodev.com>
parents:
1052
diff
changeset
|
1465 mov_rrdisp(code, dst_op.base, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1466 } else { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1467 rol_irdisp(code, 1, dst_op.base, dst_op.disp, SZ_B); |
1053
b86c3ce007d9
Implemented undocumented flag bits for rotate instructions
Michael Pavone <pavone@retrodev.com>
parents:
1052
diff
changeset
|
1468 mov_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch1, SZ_B); |
b86c3ce007d9
Implemented undocumented flag bits for rotate instructions
Michael Pavone <pavone@retrodev.com>
parents:
1052
diff
changeset
|
1469 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1470 } |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1471 if (src_op.mode == MODE_REG_DIRECT) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1472 mov_rr(code, dst_op.base, src_op.base, SZ_B); |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1473 } else if(src_op.mode == MODE_REG_DISPLACE8) { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1474 mov_rrdisp(code, dst_op.base, src_op.base, src_op.disp, SZ_B); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1475 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1476 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1477 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
1042
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1478 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B); |
651
103d5cabbe14
Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents:
644
diff
changeset
|
1479 if (inst->immed) { |
103d5cabbe14
Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents:
644
diff
changeset
|
1480 //rlca does not set these flags |
731
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
1481 if (dst_op.mode == MODE_REG_DIRECT) { |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
1482 cmp_ir(code, 0, dst_op.base, SZ_B); |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
1483 } else { |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
1484 cmp_irdisp(code, 0, dst_op.base, dst_op.disp, SZ_B); |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
1485 } |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1486 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV)); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1487 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1488 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
651
103d5cabbe14
Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents:
644
diff
changeset
|
1489 } |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1490 if (inst->addr_mode != Z80_UNUSED) { |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
1491 z80_save_result(opts, inst); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1492 if (src_op.mode != MODE_UNUSED) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1493 z80_save_reg(inst, opts); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1494 } |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1495 } else { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1496 z80_save_reg(inst, opts); |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1497 } |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1498 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1499 case Z80_RL: |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
1500 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
1501 num_cycles += 8; |
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
1502 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1503 cycles(&opts->gen, num_cycles); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1504 if (inst->addr_mode != Z80_UNUSED) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1505 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1506 translate_z80_reg(inst, &src_op, opts); //For IX/IY variants that also write to a register |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1507 cycles(&opts->gen, 1); |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1508 } else { |
302
3b831fe32c15
More fixes for confusion between Z80_UNUSED and MODE_UNUSED
Mike Pavone <pavone@retrodev.com>
parents:
301
diff
changeset
|
1509 src_op.mode = MODE_UNUSED; |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1510 translate_z80_reg(inst, &dst_op, opts); |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1511 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1512 bt_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B); |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1513 if (dst_op.mode == MODE_REG_DIRECT) { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1514 rcl_ir(code, 1, dst_op.base, SZ_B); |
1053
b86c3ce007d9
Implemented undocumented flag bits for rotate instructions
Michael Pavone <pavone@retrodev.com>
parents:
1052
diff
changeset
|
1515 mov_rrdisp(code, dst_op.base, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1516 } else { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1517 rcl_irdisp(code, 1, dst_op.base, dst_op.disp, SZ_B); |
1053
b86c3ce007d9
Implemented undocumented flag bits for rotate instructions
Michael Pavone <pavone@retrodev.com>
parents:
1052
diff
changeset
|
1518 mov_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch1, SZ_B); |
b86c3ce007d9
Implemented undocumented flag bits for rotate instructions
Michael Pavone <pavone@retrodev.com>
parents:
1052
diff
changeset
|
1519 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1520 } |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1521 if (src_op.mode == MODE_REG_DIRECT) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1522 mov_rr(code, dst_op.base, src_op.base, SZ_B); |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1523 } else if(src_op.mode == MODE_REG_DISPLACE8) { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1524 mov_rrdisp(code, dst_op.base, src_op.base, src_op.disp, SZ_B); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1525 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1526 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1527 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
1042
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1528 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B); |
651
103d5cabbe14
Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents:
644
diff
changeset
|
1529 if (inst->immed) { |
103d5cabbe14
Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents:
644
diff
changeset
|
1530 //rla does not set these flags |
731
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
1531 if (dst_op.mode == MODE_REG_DIRECT) { |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
1532 cmp_ir(code, 0, dst_op.base, SZ_B); |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
1533 } else { |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
1534 cmp_irdisp(code, 0, dst_op.base, dst_op.disp, SZ_B); |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
1535 } |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1536 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV)); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1537 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1538 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
651
103d5cabbe14
Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents:
644
diff
changeset
|
1539 } |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1540 if (inst->addr_mode != Z80_UNUSED) { |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
1541 z80_save_result(opts, inst); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1542 if (src_op.mode != MODE_UNUSED) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1543 z80_save_reg(inst, opts); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1544 } |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1545 } else { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1546 z80_save_reg(inst, opts); |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1547 } |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1548 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1549 case Z80_RRC: |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
1550 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
1551 num_cycles += 8; |
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
1552 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1553 cycles(&opts->gen, num_cycles); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1554 if (inst->addr_mode != Z80_UNUSED) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1555 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1556 translate_z80_reg(inst, &src_op, opts); //For IX/IY variants that also write to a register |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1557 cycles(&opts->gen, 1); |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1558 } else { |
302
3b831fe32c15
More fixes for confusion between Z80_UNUSED and MODE_UNUSED
Mike Pavone <pavone@retrodev.com>
parents:
301
diff
changeset
|
1559 src_op.mode = MODE_UNUSED; |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1560 translate_z80_reg(inst, &dst_op, opts); |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1561 } |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1562 if (dst_op.mode == MODE_REG_DIRECT) { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1563 ror_ir(code, 1, dst_op.base, SZ_B); |
1053
b86c3ce007d9
Implemented undocumented flag bits for rotate instructions
Michael Pavone <pavone@retrodev.com>
parents:
1052
diff
changeset
|
1564 mov_rrdisp(code, dst_op.base, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1565 } else { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1566 ror_irdisp(code, 1, dst_op.base, dst_op.disp, SZ_B); |
1053
b86c3ce007d9
Implemented undocumented flag bits for rotate instructions
Michael Pavone <pavone@retrodev.com>
parents:
1052
diff
changeset
|
1567 mov_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch1, SZ_B); |
b86c3ce007d9
Implemented undocumented flag bits for rotate instructions
Michael Pavone <pavone@retrodev.com>
parents:
1052
diff
changeset
|
1568 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1569 } |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1570 if (src_op.mode == MODE_REG_DIRECT) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1571 mov_rr(code, dst_op.base, src_op.base, SZ_B); |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1572 } else if(src_op.mode == MODE_REG_DISPLACE8) { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1573 mov_rrdisp(code, dst_op.base, src_op.base, src_op.disp, SZ_B); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1574 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1575 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1576 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
1042
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1577 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B); |
651
103d5cabbe14
Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents:
644
diff
changeset
|
1578 if (inst->immed) { |
103d5cabbe14
Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents:
644
diff
changeset
|
1579 //rrca does not set these flags |
731
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
1580 if (dst_op.mode == MODE_REG_DIRECT) { |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
1581 cmp_ir(code, 0, dst_op.base, SZ_B); |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
1582 } else { |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
1583 cmp_irdisp(code, 0, dst_op.base, dst_op.disp, SZ_B); |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
1584 } |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1585 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV)); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1586 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1587 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
651
103d5cabbe14
Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents:
644
diff
changeset
|
1588 } |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1589 if (inst->addr_mode != Z80_UNUSED) { |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
1590 z80_save_result(opts, inst); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1591 if (src_op.mode != MODE_UNUSED) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1592 z80_save_reg(inst, opts); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1593 } |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1594 } else { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1595 z80_save_reg(inst, opts); |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1596 } |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1597 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1598 case Z80_RR: |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
1599 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
1600 num_cycles += 8; |
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
1601 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1602 cycles(&opts->gen, num_cycles); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1603 if (inst->addr_mode != Z80_UNUSED) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1604 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1605 translate_z80_reg(inst, &src_op, opts); //For IX/IY variants that also write to a register |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1606 cycles(&opts->gen, 1); |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1607 } else { |
302
3b831fe32c15
More fixes for confusion between Z80_UNUSED and MODE_UNUSED
Mike Pavone <pavone@retrodev.com>
parents:
301
diff
changeset
|
1608 src_op.mode = MODE_UNUSED; |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1609 translate_z80_reg(inst, &dst_op, opts); |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1610 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1611 bt_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B); |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1612 if (dst_op.mode == MODE_REG_DIRECT) { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1613 rcr_ir(code, 1, dst_op.base, SZ_B); |
1053
b86c3ce007d9
Implemented undocumented flag bits for rotate instructions
Michael Pavone <pavone@retrodev.com>
parents:
1052
diff
changeset
|
1614 mov_rrdisp(code, dst_op.base, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1615 } else { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1616 rcr_irdisp(code, 1, dst_op.base, dst_op.disp, SZ_B); |
1053
b86c3ce007d9
Implemented undocumented flag bits for rotate instructions
Michael Pavone <pavone@retrodev.com>
parents:
1052
diff
changeset
|
1617 mov_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch1, SZ_B); |
b86c3ce007d9
Implemented undocumented flag bits for rotate instructions
Michael Pavone <pavone@retrodev.com>
parents:
1052
diff
changeset
|
1618 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1619 } |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1620 if (src_op.mode == MODE_REG_DIRECT) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1621 mov_rr(code, dst_op.base, src_op.base, SZ_B); |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1622 } else if(src_op.mode == MODE_REG_DISPLACE8) { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1623 mov_rrdisp(code, dst_op.base, src_op.base, src_op.disp, SZ_B); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1624 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1625 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1626 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
1042
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1627 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B); |
651
103d5cabbe14
Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents:
644
diff
changeset
|
1628 if (inst->immed) { |
103d5cabbe14
Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents:
644
diff
changeset
|
1629 //rra does not set these flags |
731
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
1630 if (dst_op.mode == MODE_REG_DIRECT) { |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
1631 cmp_ir(code, 0, dst_op.base, SZ_B); |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
1632 } else { |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
1633 cmp_irdisp(code, 0, dst_op.base, dst_op.disp, SZ_B); |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
1634 } |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1635 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV)); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1636 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1637 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
651
103d5cabbe14
Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents:
644
diff
changeset
|
1638 } |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1639 if (inst->addr_mode != Z80_UNUSED) { |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
1640 z80_save_result(opts, inst); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1641 if (src_op.mode != MODE_UNUSED) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1642 z80_save_reg(inst, opts); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1643 } |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1644 } else { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1645 z80_save_reg(inst, opts); |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1646 } |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1647 break; |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1648 case Z80_SLA: |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1649 case Z80_SLL: |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
1650 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
1651 num_cycles += 8; |
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
1652 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1653 cycles(&opts->gen, num_cycles); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1654 if (inst->addr_mode != Z80_UNUSED) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1655 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1656 translate_z80_reg(inst, &src_op, opts); //For IX/IY variants that also write to a register |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1657 cycles(&opts->gen, 1); |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1658 } else { |
302
3b831fe32c15
More fixes for confusion between Z80_UNUSED and MODE_UNUSED
Mike Pavone <pavone@retrodev.com>
parents:
301
diff
changeset
|
1659 src_op.mode = MODE_UNUSED; |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1660 translate_z80_reg(inst, &dst_op, opts); |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1661 } |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1662 if (dst_op.mode == MODE_REG_DIRECT) { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1663 shl_ir(code, 1, dst_op.base, SZ_B); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1664 } else { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1665 shl_irdisp(code, 1, dst_op.base, dst_op.disp, SZ_B); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1666 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1667 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
310
bf440db64086
Implement carry flag for shift instructions. Implement weird behavior for bit 0 of SLL. Fix missing break statement in SRL.
Mike Pavone <pavone@retrodev.com>
parents:
309
diff
changeset
|
1668 if (inst->op == Z80_SLL) { |
731
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
1669 if (dst_op.mode == MODE_REG_DIRECT) { |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
1670 or_ir(code, 1, dst_op.base, SZ_B); |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
1671 } else { |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
1672 or_irdisp(code, 1, dst_op.base, dst_op.disp, SZ_B); |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
1673 } |
310
bf440db64086
Implement carry flag for shift instructions. Implement weird behavior for bit 0 of SLL. Fix missing break statement in SRL.
Mike Pavone <pavone@retrodev.com>
parents:
309
diff
changeset
|
1674 } |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1675 if (src_op.mode == MODE_REG_DIRECT) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1676 mov_rr(code, dst_op.base, src_op.base, SZ_B); |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1677 } else if(src_op.mode == MODE_REG_DISPLACE8) { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1678 mov_rrdisp(code, dst_op.base, src_op.base, src_op.disp, SZ_B); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1679 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1680 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
1042
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1681 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B); |
731
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
1682 if (dst_op.mode == MODE_REG_DIRECT) { |
1055
ac4615d16226
Implement undocumented flag bits for shift instructions
Michael Pavone <pavone@retrodev.com>
parents:
1054
diff
changeset
|
1683 mov_rrdisp(code, dst_op.base, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
731
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
1684 cmp_ir(code, 0, dst_op.base, SZ_B); |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
1685 } else { |
1055
ac4615d16226
Implement undocumented flag bits for shift instructions
Michael Pavone <pavone@retrodev.com>
parents:
1054
diff
changeset
|
1686 mov_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch1, SZ_B); |
ac4615d16226
Implement undocumented flag bits for shift instructions
Michael Pavone <pavone@retrodev.com>
parents:
1054
diff
changeset
|
1687 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
731
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
1688 cmp_irdisp(code, 0, dst_op.base, dst_op.disp, SZ_B); |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
1689 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1690 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1691 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1692 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1693 if (inst->addr_mode != Z80_UNUSED) { |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
1694 z80_save_result(opts, inst); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1695 if (src_op.mode != MODE_UNUSED) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1696 z80_save_reg(inst, opts); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1697 } |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1698 } else { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1699 z80_save_reg(inst, opts); |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1700 } |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1701 break; |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1702 case Z80_SRA: |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
1703 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
1704 num_cycles += 8; |
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
1705 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1706 cycles(&opts->gen, num_cycles); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1707 if (inst->addr_mode != Z80_UNUSED) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1708 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1709 translate_z80_reg(inst, &src_op, opts); //For IX/IY variants that also write to a register |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1710 cycles(&opts->gen, 1); |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1711 } else { |
302
3b831fe32c15
More fixes for confusion between Z80_UNUSED and MODE_UNUSED
Mike Pavone <pavone@retrodev.com>
parents:
301
diff
changeset
|
1712 src_op.mode = MODE_UNUSED; |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1713 translate_z80_reg(inst, &dst_op, opts); |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1714 } |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1715 if (dst_op.mode == MODE_REG_DIRECT) { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1716 sar_ir(code, 1, dst_op.base, SZ_B); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1717 } else { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1718 sar_irdisp(code, 1, dst_op.base, dst_op.disp, SZ_B); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1719 } |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1720 if (src_op.mode == MODE_REG_DIRECT) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1721 mov_rr(code, dst_op.base, src_op.base, SZ_B); |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1722 } else if(src_op.mode == MODE_REG_DISPLACE8) { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1723 mov_rrdisp(code, dst_op.base, src_op.base, src_op.disp, SZ_B); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1724 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1725 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1726 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
1042
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1727 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B); |
731
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
1728 if (dst_op.mode == MODE_REG_DIRECT) { |
1055
ac4615d16226
Implement undocumented flag bits for shift instructions
Michael Pavone <pavone@retrodev.com>
parents:
1054
diff
changeset
|
1729 mov_rrdisp(code, dst_op.base, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
731
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
1730 cmp_ir(code, 0, dst_op.base, SZ_B); |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
1731 } else { |
1055
ac4615d16226
Implement undocumented flag bits for shift instructions
Michael Pavone <pavone@retrodev.com>
parents:
1054
diff
changeset
|
1732 mov_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch1, SZ_B); |
ac4615d16226
Implement undocumented flag bits for shift instructions
Michael Pavone <pavone@retrodev.com>
parents:
1054
diff
changeset
|
1733 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
731
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
1734 cmp_irdisp(code, 0, dst_op.base, dst_op.disp, SZ_B); |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
1735 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1736 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1737 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1738 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1739 if (inst->addr_mode != Z80_UNUSED) { |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
1740 z80_save_result(opts, inst); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1741 if (src_op.mode != MODE_UNUSED) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1742 z80_save_reg(inst, opts); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1743 } |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1744 } else { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1745 z80_save_reg(inst, opts); |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1746 } |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1747 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1748 case Z80_SRL: |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
1749 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
1750 num_cycles += 8; |
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
1751 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1752 cycles(&opts->gen, num_cycles); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1753 if (inst->addr_mode != Z80_UNUSED) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1754 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1755 translate_z80_reg(inst, &src_op, opts); //For IX/IY variants that also write to a register |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1756 cycles(&opts->gen, 1); |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1757 } else { |
302
3b831fe32c15
More fixes for confusion between Z80_UNUSED and MODE_UNUSED
Mike Pavone <pavone@retrodev.com>
parents:
301
diff
changeset
|
1758 src_op.mode = MODE_UNUSED; |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1759 translate_z80_reg(inst, &dst_op, opts); |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1760 } |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1761 if (dst_op.mode == MODE_REG_DIRECT) { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1762 shr_ir(code, 1, dst_op.base, SZ_B); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1763 } else { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1764 shr_irdisp(code, 1, dst_op.base, dst_op.disp, SZ_B); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1765 } |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1766 if (src_op.mode == MODE_REG_DIRECT) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1767 mov_rr(code, dst_op.base, src_op.base, SZ_B); |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1768 } else if(src_op.mode == MODE_REG_DISPLACE8) { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1769 mov_rrdisp(code, dst_op.base, src_op.base, src_op.disp, SZ_B); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1770 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1771 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1772 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
1042
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1773 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B); |
731
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
1774 if (dst_op.mode == MODE_REG_DIRECT) { |
1055
ac4615d16226
Implement undocumented flag bits for shift instructions
Michael Pavone <pavone@retrodev.com>
parents:
1054
diff
changeset
|
1775 mov_rrdisp(code, dst_op.base, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
731
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
1776 cmp_ir(code, 0, dst_op.base, SZ_B); |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
1777 } else { |
1055
ac4615d16226
Implement undocumented flag bits for shift instructions
Michael Pavone <pavone@retrodev.com>
parents:
1054
diff
changeset
|
1778 mov_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch1, SZ_B); |
ac4615d16226
Implement undocumented flag bits for shift instructions
Michael Pavone <pavone@retrodev.com>
parents:
1054
diff
changeset
|
1779 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
731
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
1780 cmp_irdisp(code, 0, dst_op.base, dst_op.disp, SZ_B); |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
1781 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1782 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1783 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1784 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1785 if (inst->addr_mode != Z80_UNUSED) { |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
1786 z80_save_result(opts, inst); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1787 if (src_op.mode != MODE_UNUSED) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1788 z80_save_reg(inst, opts); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1789 } |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1790 } else { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1791 z80_save_reg(inst, opts); |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1792 } |
310
bf440db64086
Implement carry flag for shift instructions. Implement weird behavior for bit 0 of SLL. Fix missing break statement in SRL.
Mike Pavone <pavone@retrodev.com>
parents:
309
diff
changeset
|
1793 break; |
286 | 1794 case Z80_RLD: |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
1795 cycles(&opts->gen, num_cycles); |
734
e21c274a008e
Fix RLD and RRD for the case in which HL does not map to a native register
Michael Pavone <pavone@retrodev.com>
parents:
731
diff
changeset
|
1796 zreg_to_native(opts, Z80_HL, opts->gen.scratch1); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
1797 call(code, opts->read_8); |
286 | 1798 //Before: (HL) = 0x12, A = 0x34 |
1799 //After: (HL) = 0x24, A = 0x31 | |
734
e21c274a008e
Fix RLD and RRD for the case in which HL does not map to a native register
Michael Pavone <pavone@retrodev.com>
parents:
731
diff
changeset
|
1800 zreg_to_native(opts, Z80_A, opts->gen.scratch2); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1801 shl_ir(code, 4, opts->gen.scratch1, SZ_W); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1802 and_ir(code, 0xF, opts->gen.scratch2, SZ_W); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1803 and_ir(code, 0xFFF, opts->gen.scratch1, SZ_W); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1804 and_ir(code, 0xF0, opts->regs[Z80_A], SZ_B); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1805 or_rr(code, opts->gen.scratch2, opts->gen.scratch1, SZ_W); |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
1806 //opts->gen.scratch1 = 0x0124 |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1807 ror_ir(code, 8, opts->gen.scratch1, SZ_W); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1808 cycles(&opts->gen, 4); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1809 or_rr(code, opts->gen.scratch1, opts->regs[Z80_A], SZ_B); |
287
fb840e0a48cd
Implement RRD and implement flags on RLD
Mike Pavone <pavone@retrodev.com>
parents:
286
diff
changeset
|
1810 //set flags |
1042
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1811 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1812 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1813 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1814 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1815 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
1054
ca38a29d2d76
Implement undocumented flag bits for RLD and RRD
Michael Pavone <pavone@retrodev.com>
parents:
1053
diff
changeset
|
1816 mov_rrdisp(code, opts->regs[Z80_A], opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
505
b7b7a1cab44a
The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1817 |
734
e21c274a008e
Fix RLD and RRD for the case in which HL does not map to a native register
Michael Pavone <pavone@retrodev.com>
parents:
731
diff
changeset
|
1818 zreg_to_native(opts, Z80_HL, opts->gen.scratch2); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1819 ror_ir(code, 8, opts->gen.scratch1, SZ_W); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
1820 call(code, opts->write_8); |
286 | 1821 break; |
287
fb840e0a48cd
Implement RRD and implement flags on RLD
Mike Pavone <pavone@retrodev.com>
parents:
286
diff
changeset
|
1822 case Z80_RRD: |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
1823 cycles(&opts->gen, num_cycles); |
734
e21c274a008e
Fix RLD and RRD for the case in which HL does not map to a native register
Michael Pavone <pavone@retrodev.com>
parents:
731
diff
changeset
|
1824 zreg_to_native(opts, Z80_HL, opts->gen.scratch1); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
1825 call(code, opts->read_8); |
287
fb840e0a48cd
Implement RRD and implement flags on RLD
Mike Pavone <pavone@retrodev.com>
parents:
286
diff
changeset
|
1826 //Before: (HL) = 0x12, A = 0x34 |
fb840e0a48cd
Implement RRD and implement flags on RLD
Mike Pavone <pavone@retrodev.com>
parents:
286
diff
changeset
|
1827 //After: (HL) = 0x41, A = 0x32 |
734
e21c274a008e
Fix RLD and RRD for the case in which HL does not map to a native register
Michael Pavone <pavone@retrodev.com>
parents:
731
diff
changeset
|
1828 zreg_to_native(opts, Z80_A, opts->gen.scratch2); |
591
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diff
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|
1829 ror_ir(code, 4, opts->gen.scratch1, SZ_W); |
966b46c68942
Get Z80 core back into compileable state
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590
diff
changeset
|
1830 shl_ir(code, 4, opts->gen.scratch2, SZ_W); |
966b46c68942
Get Z80 core back into compileable state
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parents:
590
diff
changeset
|
1831 and_ir(code, 0xF00F, opts->gen.scratch1, SZ_W); |
966b46c68942
Get Z80 core back into compileable state
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590
diff
changeset
|
1832 and_ir(code, 0xF0, opts->regs[Z80_A], SZ_B); |
967
1eb616b8cbe9
Fix bug in Z80 rrd implementation. This fixes the annoying high pitched wine in Afterburner II.
Michael Pavone <pavone@retrodev.com>
parents:
966
diff
changeset
|
1833 and_ir(code, 0xF0, opts->gen.scratch2, SZ_W); |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
1834 //opts->gen.scratch1 = 0x2001 |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
1835 //opts->gen.scratch2 = 0x0040 |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1836 or_rr(code, opts->gen.scratch2, opts->gen.scratch1, SZ_W); |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
1837 //opts->gen.scratch1 = 0x2041 |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1838 ror_ir(code, 8, opts->gen.scratch1, SZ_W); |
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Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1839 cycles(&opts->gen, 4); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1840 shr_ir(code, 4, opts->gen.scratch1, SZ_B); |
966b46c68942
Get Z80 core back into compileable state
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diff
changeset
|
1841 or_rr(code, opts->gen.scratch1, opts->regs[Z80_A], SZ_B); |
287
fb840e0a48cd
Implement RRD and implement flags on RLD
Mike Pavone <pavone@retrodev.com>
parents:
286
diff
changeset
|
1842 //set flags |
1042
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1843 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B); |
591
966b46c68942
Get Z80 core back into compileable state
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diff
changeset
|
1844 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
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Get Z80 core back into compileable state
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diff
changeset
|
1845 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV)); |
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Get Z80 core back into compileable state
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diff
changeset
|
1846 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1847 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
1054
ca38a29d2d76
Implement undocumented flag bits for RLD and RRD
Michael Pavone <pavone@retrodev.com>
parents:
1053
diff
changeset
|
1848 mov_rrdisp(code, opts->regs[Z80_A], opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
505
b7b7a1cab44a
The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1849 |
734
e21c274a008e
Fix RLD and RRD for the case in which HL does not map to a native register
Michael Pavone <pavone@retrodev.com>
parents:
731
diff
changeset
|
1850 zreg_to_native(opts, Z80_HL, opts->gen.scratch2); |
591
966b46c68942
Get Z80 core back into compileable state
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590
diff
changeset
|
1851 ror_ir(code, 8, opts->gen.scratch1, SZ_W); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
1852 call(code, opts->write_8); |
287
fb840e0a48cd
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Mike Pavone <pavone@retrodev.com>
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286
diff
changeset
|
1853 break; |
308
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Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
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diff
changeset
|
1854 case Z80_BIT: { |
1044
1625555e346e
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Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
1855 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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diff
changeset
|
1856 num_cycles += 8; |
1625555e346e
Properly handle redundant prefixes
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diff
changeset
|
1857 } |
591
966b46c68942
Get Z80 core back into compileable state
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diff
changeset
|
1858 cycles(&opts->gen, num_cycles); |
308
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diff
changeset
|
1859 uint8_t bit; |
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diff
changeset
|
1860 if ((inst->addr_mode & 0x1F) == Z80_REG && opts->regs[inst->ea_reg] >= AH && opts->regs[inst->ea_reg] <= BH) { |
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307
diff
changeset
|
1861 src_op.base = opts->regs[z80_word_reg(inst->ea_reg)]; |
737
043393b79e28
Fixes for the 32-bit build accidentally introduced a bug into the 64-bit build, this commit fixes the regression
Michael Pavone <pavone@retrodev.com>
parents:
735
diff
changeset
|
1862 src_op.mode = MODE_REG_DIRECT; |
308
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diff
changeset
|
1863 size = SZ_W; |
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diff
changeset
|
1864 bit = inst->immed + 8; |
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|
1865 } else { |
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diff
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|
1866 size = SZ_B; |
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diff
changeset
|
1867 bit = inst->immed; |
591
966b46c68942
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590
diff
changeset
|
1868 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY); |
308
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diff
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|
1869 } |
239
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
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238
diff
changeset
|
1870 if (inst->addr_mode != Z80_REG) { |
a5bea9711a46
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diff
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|
1871 //Reads normally take 3 cycles, but the read at the end of a bit instruction takes 4 |
591
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590
diff
changeset
|
1872 cycles(&opts->gen, 1); |
239
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diff
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|
1873 } |
731
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
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parents:
730
diff
changeset
|
1874 if (src_op.mode == MODE_REG_DIRECT) { |
0835cd3dfc36
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Michael Pavone <pavone@retrodev.com>
parents:
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diff
changeset
|
1875 bt_ir(code, bit, src_op.base, size); |
0835cd3dfc36
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Michael Pavone <pavone@retrodev.com>
parents:
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diff
changeset
|
1876 } else { |
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Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
1877 bt_irdisp(code, bit, src_op.base, src_op.disp, size); |
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Michael Pavone <pavone@retrodev.com>
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diff
changeset
|
1878 } |
591
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diff
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|
1879 setcc_rdisp(code, CC_NC, opts->gen.context_reg, zf_off(ZF_Z)); |
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diff
changeset
|
1880 setcc_rdisp(code, CC_NC, opts->gen.context_reg, zf_off(ZF_PV)); |
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diff
changeset
|
1881 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
1042
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1882 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_H), SZ_B); |
307
b6393b89a7e4
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parents:
306
diff
changeset
|
1883 if (inst->immed == 7) { |
731
0835cd3dfc36
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parents:
730
diff
changeset
|
1884 if (src_op.mode == MODE_REG_DIRECT) { |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
1885 cmp_ir(code, 0, src_op.base, size); |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
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parents:
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diff
changeset
|
1886 } else { |
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Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
1887 cmp_irdisp(code, 0, src_op.base, src_op.disp, size); |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
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parents:
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diff
changeset
|
1888 } |
591
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parents:
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diff
changeset
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1889 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
307
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diff
changeset
|
1890 } else { |
591
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diff
changeset
|
1891 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_S), SZ_B); |
307
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changeset
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1892 } |
1049
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diff
changeset
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1893 |
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changeset
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1894 if ((inst->addr_mode & 0x1F) == Z80_REG) { |
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parents:
1048
diff
changeset
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1895 if (src_op.mode == MODE_REG_DIRECT) { |
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parents:
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diff
changeset
|
1896 if (size == SZ_W) { |
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parents:
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diff
changeset
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1897 mov_rr(code, src_op.base, opts->gen.scratch1, SZ_W); |
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parents:
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changeset
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1898 shr_ir(code, 8, opts->gen.scratch1, SZ_W); |
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parents:
1048
diff
changeset
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1899 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
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1900 } else { |
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diff
changeset
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1901 mov_rrdisp(code, src_op.base, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
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Partial support for undocumented flag bits
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changeset
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1902 } |
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Partial support for undocumented flag bits
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diff
changeset
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1903 } else { |
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diff
changeset
|
1904 mov_rdispr(code, src_op.base, src_op.disp, opts->gen.scratch1, SZ_B); |
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Partial support for undocumented flag bits
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diff
changeset
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1905 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
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Partial support for undocumented flag bits
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diff
changeset
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1906 } |
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changeset
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1907 } else if((inst->addr_mode & 0x1F) != Z80_REG_INDIRECT) { |
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parents:
1048
diff
changeset
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1908 zreg_to_native(opts, (inst->addr_mode & 0x1F) == Z80_IX_DISPLACE ? Z80_IX : Z80_IY, opts->gen.scratch2); |
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parents:
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diff
changeset
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1909 add_ir(code, inst->ea_reg & 0x80 ? inst->ea_reg - 256 : inst->ea_reg, opts->gen.scratch2, SZ_W); |
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diff
changeset
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1910 shr_ir(code, 8, opts->gen.scratch2, SZ_W); |
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changeset
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1911 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
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changeset
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1912 } |
239
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238
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1913 break; |
308
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1914 } |
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diff
changeset
|
1915 case Z80_SET: { |
1044
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parents:
1043
diff
changeset
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1916 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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changeset
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1917 num_cycles += 8; |
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1918 } |
591
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changeset
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1919 cycles(&opts->gen, num_cycles); |
308
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diff
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1920 uint8_t bit; |
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changeset
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1921 if ((inst->addr_mode & 0x1F) == Z80_REG && opts->regs[inst->ea_reg] >= AH && opts->regs[inst->ea_reg] <= BH) { |
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diff
changeset
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1922 src_op.base = opts->regs[z80_word_reg(inst->ea_reg)]; |
737
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Fixes for the 32-bit build accidentally introduced a bug into the 64-bit build, this commit fixes the regression
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parents:
735
diff
changeset
|
1923 src_op.mode = MODE_REG_DIRECT; |
308
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1924 size = SZ_W; |
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1925 bit = inst->immed + 8; |
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1926 } else { |
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1927 size = SZ_B; |
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|
1928 bit = inst->immed; |
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1929 translate_z80_ea(inst, &src_op, opts, READ, MODIFY); |
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1930 } |
299
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1931 if (inst->reg != Z80_USE_IMMED) { |
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1932 translate_z80_reg(inst, &dst_op, opts); |
299
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1933 } |
247
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Implement rotation and bit set/reset instructions (untested).
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1934 if (inst->addr_mode != Z80_REG) { |
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1935 //Reads normally take 3 cycles, but the read in the middle of a set instruction takes 4 |
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1936 cycles(&opts->gen, 1); |
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1937 } |
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1938 if (src_op.mode == MODE_REG_DIRECT) { |
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1939 bts_ir(code, bit, src_op.base, size); |
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1940 } else { |
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|
1941 bts_irdisp(code, bit, src_op.base, src_op.disp, size); |
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|
1942 } |
299
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1943 if (inst->reg != Z80_USE_IMMED) { |
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1944 if (size == SZ_W) { |
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1945 #ifdef X86_64 |
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1946 if (dst_op.base >= R8) { |
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1947 ror_ir(code, 8, src_op.base, SZ_W); |
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1948 mov_rr(code, opts->regs[z80_low_reg(inst->ea_reg)], dst_op.base, SZ_B); |
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1949 ror_ir(code, 8, src_op.base, SZ_W); |
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1950 } else { |
666
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1951 #endif |
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1952 if (dst_op.mode == MODE_REG_DIRECT) { |
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1953 zreg_to_native(opts, inst->ea_reg, dst_op.base); |
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1954 } else { |
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|
1955 zreg_to_native(opts, inst->ea_reg, opts->gen.scratch1); |
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changeset
|
1956 mov_rrdisp(code, opts->gen.scratch1, dst_op.base, dst_op.disp, SZ_B); |
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1957 } |
666
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|
1958 #ifdef X86_64 |
505
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The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
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1959 } |
666
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|
1960 #endif |
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1961 } else { |
731
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1962 if (dst_op.mode == MODE_REG_DIRECT) { |
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|
1963 if (src_op.mode == MODE_REG_DIRECT) { |
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|
1964 mov_rr(code, src_op.base, dst_op.base, SZ_B); |
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|
1965 } else { |
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parents:
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|
1966 mov_rdispr(code, src_op.base, src_op.disp, dst_op.base, SZ_B); |
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parents:
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|
1967 } |
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changeset
|
1968 } else if (src_op.mode == MODE_REG_DIRECT) { |
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diff
changeset
|
1969 mov_rrdisp(code, src_op.base, dst_op.base, dst_op.disp, SZ_B); |
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parents:
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diff
changeset
|
1970 } else { |
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parents:
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diff
changeset
|
1971 mov_rdispr(code, src_op.base, src_op.disp, opts->gen.scratch1, SZ_B); |
0835cd3dfc36
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parents:
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diff
changeset
|
1972 mov_rrdisp(code, opts->gen.scratch1, dst_op.base, dst_op.disp, SZ_B); |
0835cd3dfc36
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parents:
730
diff
changeset
|
1973 } |
308
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1974 } |
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|
1975 } |
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diff
changeset
|
1976 if ((inst->addr_mode & 0x1F) != Z80_REG) { |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
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diff
changeset
|
1977 z80_save_result(opts, inst); |
308
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diff
changeset
|
1978 if (inst->reg != Z80_USE_IMMED) { |
591
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diff
changeset
|
1979 z80_save_reg(inst, opts); |
308
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parents:
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diff
changeset
|
1980 } |
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parents:
307
diff
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|
1981 } |
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307
diff
changeset
|
1982 break; |
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diff
changeset
|
1983 } |
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parents:
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diff
changeset
|
1984 case Z80_RES: { |
1044
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Properly handle redundant prefixes
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parents:
1043
diff
changeset
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1985 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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parents:
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diff
changeset
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1986 num_cycles += 8; |
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Properly handle redundant prefixes
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parents:
1043
diff
changeset
|
1987 } |
591
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parents:
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diff
changeset
|
1988 cycles(&opts->gen, num_cycles); |
308
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Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
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parents:
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diff
changeset
|
1989 uint8_t bit; |
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Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
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parents:
307
diff
changeset
|
1990 if ((inst->addr_mode & 0x1F) == Z80_REG && opts->regs[inst->ea_reg] >= AH && opts->regs[inst->ea_reg] <= BH) { |
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Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
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parents:
307
diff
changeset
|
1991 src_op.base = opts->regs[z80_word_reg(inst->ea_reg)]; |
737
043393b79e28
Fixes for the 32-bit build accidentally introduced a bug into the 64-bit build, this commit fixes the regression
Michael Pavone <pavone@retrodev.com>
parents:
735
diff
changeset
|
1992 src_op.mode = MODE_REG_DIRECT; |
308
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307
diff
changeset
|
1993 size = SZ_W; |
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parents:
307
diff
changeset
|
1994 bit = inst->immed + 8; |
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Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
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parents:
307
diff
changeset
|
1995 } else { |
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Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
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parents:
307
diff
changeset
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1996 size = SZ_B; |
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Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
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parents:
307
diff
changeset
|
1997 bit = inst->immed; |
591
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Get Z80 core back into compileable state
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parents:
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diff
changeset
|
1998 translate_z80_ea(inst, &src_op, opts, READ, MODIFY); |
308
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Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
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parents:
307
diff
changeset
|
1999 } |
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Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
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parents:
307
diff
changeset
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2000 if (inst->reg != Z80_USE_IMMED) { |
591
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parents:
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diff
changeset
|
2001 translate_z80_reg(inst, &dst_op, opts); |
308
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Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
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parents:
307
diff
changeset
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2002 } |
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Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
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parents:
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diff
changeset
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2003 if (inst->addr_mode != Z80_REG) { |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
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parents:
307
diff
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2004 //Reads normally take 3 cycles, but the read in the middle of a set instruction takes 4 |
591
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Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
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2005 cycles(&opts->gen, 1); |
308
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parents:
307
diff
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|
2006 } |
731
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Z80 test cases that passed on 64-bit now pass on 32-bit
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parents:
730
diff
changeset
|
2007 if (src_op.mode == MODE_REG_DIRECT) { |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
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parents:
730
diff
changeset
|
2008 btr_ir(code, bit, src_op.base, size); |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
2009 } else { |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
2010 btr_irdisp(code, bit, src_op.base, src_op.disp, size); |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
2011 } |
308
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Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
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parents:
307
diff
changeset
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2012 if (inst->reg != Z80_USE_IMMED) { |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
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parents:
307
diff
changeset
|
2013 if (size == SZ_W) { |
666
b68039895627
In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed
Michael Pavone <pavone@retrodev.com>
parents:
665
diff
changeset
|
2014 #ifdef X86_64 |
308
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Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
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parents:
307
diff
changeset
|
2015 if (dst_op.base >= R8) { |
591
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Get Z80 core back into compileable state
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parents:
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diff
changeset
|
2016 ror_ir(code, 8, src_op.base, SZ_W); |
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parents:
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diff
changeset
|
2017 mov_rr(code, opts->regs[z80_low_reg(inst->ea_reg)], dst_op.base, SZ_B); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2018 ror_ir(code, 8, src_op.base, SZ_W); |
308
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Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
2019 } else { |
666
b68039895627
In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed
Michael Pavone <pavone@retrodev.com>
parents:
665
diff
changeset
|
2020 #endif |
731
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
2021 if (dst_op.mode == MODE_REG_DIRECT) { |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
2022 zreg_to_native(opts, inst->ea_reg, dst_op.base); |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
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parents:
730
diff
changeset
|
2023 } else { |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
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parents:
730
diff
changeset
|
2024 zreg_to_native(opts, inst->ea_reg, opts->gen.scratch1); |
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Z80 test cases that passed on 64-bit now pass on 32-bit
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parents:
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diff
changeset
|
2025 mov_rrdisp(code, opts->gen.scratch1, dst_op.base, dst_op.disp, SZ_B); |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
2026 } |
666
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In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed
Michael Pavone <pavone@retrodev.com>
parents:
665
diff
changeset
|
2027 #ifdef X86_64 |
505
b7b7a1cab44a
The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
2028 } |
666
b68039895627
In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed
Michael Pavone <pavone@retrodev.com>
parents:
665
diff
changeset
|
2029 #endif |
308
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
2030 } else { |
731
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
2031 if (dst_op.mode == MODE_REG_DIRECT) { |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
2032 if (src_op.mode == MODE_REG_DIRECT) { |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
2033 mov_rr(code, src_op.base, dst_op.base, SZ_B); |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
2034 } else { |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
2035 mov_rdispr(code, src_op.base, src_op.disp, dst_op.base, SZ_B); |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
2036 } |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
2037 } else if (src_op.mode == MODE_REG_DIRECT) { |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
2038 mov_rrdisp(code, src_op.base, dst_op.base, dst_op.disp, SZ_B); |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
2039 } else { |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
2040 mov_rdispr(code, src_op.base, src_op.disp, opts->gen.scratch1, SZ_B); |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
2041 mov_rrdisp(code, opts->gen.scratch1, dst_op.base, dst_op.disp, SZ_B); |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
2042 } |
308
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
2043 } |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
2044 } |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
2045 if (inst->addr_mode != Z80_REG) { |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2046 z80_save_result(opts, inst); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
2047 if (inst->reg != Z80_USE_IMMED) { |
591
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Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2048 z80_save_reg(inst, opts); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
2049 } |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
2050 } |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
2051 break; |
308
e0e81551fd7e
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
2052 } |
236
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
2053 case Z80_JP: { |
506
a3b48a57e847
Fix timing of certain ld and jp instructions in the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
505
diff
changeset
|
2054 if (inst->addr_mode != Z80_REG_INDIRECT) { |
591
966b46c68942
Get Z80 core back into compileable state
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parents:
590
diff
changeset
|
2055 num_cycles += 6; |
236
19fb3523a9e5
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parents:
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diff
changeset
|
2056 } |
591
966b46c68942
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Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2057 cycles(&opts->gen, num_cycles); |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
2058 if (inst->addr_mode != Z80_REG_INDIRECT) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2059 code_ptr call_dst = z80_get_native_address(context, inst->immed); |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
2060 if (!call_dst) { |
591
966b46c68942
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parents:
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diff
changeset
|
2061 opts->gen.deferred = defer_address(opts->gen.deferred, inst->immed, code->cur + 1); |
236
19fb3523a9e5
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parents:
235
diff
changeset
|
2062 //fake address to force large displacement |
601
f0061e3d2ad9
Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor
Michael Pavone <pavone@retrodev.com>
parents:
598
diff
changeset
|
2063 call_dst = code->cur + 256; |
236
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
parents:
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diff
changeset
|
2064 } |
591
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parents:
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diff
changeset
|
2065 jmp(code, call_dst); |
236
19fb3523a9e5
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parents:
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diff
changeset
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2066 } else { |
239
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
2067 if (inst->addr_mode == Z80_REG_INDIRECT) { |
729
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
2068 zreg_to_native(opts, inst->ea_reg, opts->gen.scratch1); |
236
19fb3523a9e5
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parents:
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diff
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2069 } else { |
591
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parents:
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diff
changeset
|
2070 mov_ir(code, inst->immed, opts->gen.scratch1, SZ_W); |
236
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parents:
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diff
changeset
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2071 } |
593
5ef3fe516da9
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parents:
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diff
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|
2072 call(code, opts->native_addr); |
591
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parents:
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diff
changeset
|
2073 jmp_r(code, opts->gen.scratch1); |
236
19fb3523a9e5
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parents:
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diff
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|
2074 } |
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parents:
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diff
changeset
|
2075 break; |
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parents:
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|
2076 } |
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parents:
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diff
changeset
|
2077 case Z80_JPCC: { |
1044
1625555e346e
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Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
2078 cycles(&opts->gen, num_cycles + 3);//T States: 4,3 |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
2079 uint8_t cond = CC_Z; |
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
2080 switch (inst->reg) |
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Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
2081 { |
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parents:
235
diff
changeset
|
2082 case Z80_CC_NZ: |
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
2083 cond = CC_NZ; |
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
2084 case Z80_CC_Z: |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2085 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_Z), SZ_B); |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
2086 break; |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
2087 case Z80_CC_NC: |
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
2088 cond = CC_NZ; |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
2089 case Z80_CC_C: |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2090 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B); |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
2091 break; |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
2092 case Z80_CC_PO: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
2093 cond = CC_NZ; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
2094 case Z80_CC_PE: |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2095 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_PV), SZ_B); |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
2096 break; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
2097 case Z80_CC_P: |
367
f20562f2a570
Fix P condition in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
366
diff
changeset
|
2098 cond = CC_NZ; |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
2099 case Z80_CC_M: |
591
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Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2100 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_S), SZ_B); |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
2101 break; |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
2102 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2103 uint8_t *no_jump_off = code->cur+1; |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2104 jcc(code, cond, code->cur+2); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2105 cycles(&opts->gen, 5);//T States: 5 |
236
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Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
2106 uint16_t dest_addr = inst->immed; |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
2107 code_ptr call_dst = z80_get_native_address(context, dest_addr); |
236
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Implement more Z80 instructions (untested)
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parents:
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diff
changeset
|
2108 if (!call_dst) { |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
2109 opts->gen.deferred = defer_address(opts->gen.deferred, dest_addr, code->cur + 1); |
236
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Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
2110 //fake address to force large displacement |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
2111 call_dst = code->cur + 256; |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
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diff
changeset
|
2112 } |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
2113 jmp(code, call_dst); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2114 *no_jump_off = code->cur - (no_jump_off+1); |
236
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Implement more Z80 instructions (untested)
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parents:
235
diff
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|
2115 break; |
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
2116 } |
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Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
2117 case Z80_JR: { |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
2118 cycles(&opts->gen, num_cycles + 8);//T States: 4,3,5 |
236
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Implement more Z80 instructions (untested)
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parents:
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diff
changeset
|
2119 uint16_t dest_addr = address + inst->immed + 2; |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
2120 code_ptr call_dst = z80_get_native_address(context, dest_addr); |
236
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Implement more Z80 instructions (untested)
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parents:
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diff
changeset
|
2121 if (!call_dst) { |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
2122 opts->gen.deferred = defer_address(opts->gen.deferred, dest_addr, code->cur + 1); |
236
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Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
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diff
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|
2123 //fake address to force large displacement |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
2124 call_dst = code->cur + 256; |
236
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Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
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diff
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2125 } |
653
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Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
2126 jmp(code, call_dst); |
236
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Implement more Z80 instructions (untested)
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parents:
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diff
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|
2127 break; |
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parents:
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diff
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|
2128 } |
235
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Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2129 case Z80_JRCC: { |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
2130 cycles(&opts->gen, num_cycles + 3);//T States: 4,3 |
235
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diff
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2131 uint8_t cond = CC_Z; |
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parents:
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diff
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2132 switch (inst->reg) |
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parents:
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diff
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|
2133 { |
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Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
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diff
changeset
|
2134 case Z80_CC_NZ: |
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parents:
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diff
changeset
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2135 cond = CC_NZ; |
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Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2136 case Z80_CC_Z: |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2137 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_Z), SZ_B); |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2138 break; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2139 case Z80_CC_NC: |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2140 cond = CC_NZ; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2141 case Z80_CC_C: |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2142 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B); |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2143 break; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2144 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2145 uint8_t *no_jump_off = code->cur+1; |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2146 jcc(code, cond, code->cur+2); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2147 cycles(&opts->gen, 5);//T States: 5 |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2148 uint16_t dest_addr = address + inst->immed + 2; |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
2149 code_ptr call_dst = z80_get_native_address(context, dest_addr); |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2150 if (!call_dst) { |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
2151 opts->gen.deferred = defer_address(opts->gen.deferred, dest_addr, code->cur + 1); |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2152 //fake address to force large displacement |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
2153 call_dst = code->cur + 256; |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2154 } |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
2155 jmp(code, call_dst); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2156 *no_jump_off = code->cur - (no_jump_off+1); |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2157 break; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2158 } |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
2159 case Z80_DJNZ: { |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
2160 cycles(&opts->gen, num_cycles + 4);//T States: 5,3 |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
2161 if (opts->regs[Z80_B] >= 0) { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
2162 sub_ir(code, 1, opts->regs[Z80_B], SZ_B); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
2163 } else { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
2164 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_B), SZ_B); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
2165 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2166 uint8_t *no_jump_off = code->cur+1; |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2167 jcc(code, CC_Z, code->cur+2); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2168 cycles(&opts->gen, 5);//T States: 5 |
239
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
2169 uint16_t dest_addr = address + inst->immed + 2; |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
2170 code_ptr call_dst = z80_get_native_address(context, dest_addr); |
239
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
2171 if (!call_dst) { |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
2172 opts->gen.deferred = defer_address(opts->gen.deferred, dest_addr, code->cur + 1); |
239
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
2173 //fake address to force large displacement |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
2174 call_dst = code->cur + 256; |
239
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
2175 } |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
2176 jmp(code, call_dst); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2177 *no_jump_off = code->cur - (no_jump_off+1); |
239
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
2178 break; |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
2179 } |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2180 case Z80_CALL: { |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
2181 cycles(&opts->gen, num_cycles + 7);//T States: 4,3,4 |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2182 sub_ir(code, 2, opts->regs[Z80_SP], SZ_W); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2183 mov_ir(code, address + 3, opts->gen.scratch1, SZ_W); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2184 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch2, SZ_W); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2185 call(code, opts->write_16_highfirst);//T States: 3, 3 |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
2186 code_ptr call_dst = z80_get_native_address(context, inst->immed); |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2187 if (!call_dst) { |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
2188 opts->gen.deferred = defer_address(opts->gen.deferred, inst->immed, code->cur + 1); |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2189 //fake address to force large displacement |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
2190 call_dst = code->cur + 256; |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2191 } |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
2192 jmp(code, call_dst); |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2193 break; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2194 } |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
2195 case Z80_CALLCC: { |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
2196 cycles(&opts->gen, num_cycles + 6);//T States: 4,3,3 (false case) |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
2197 uint8_t cond = CC_Z; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
2198 switch (inst->reg) |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
2199 { |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
2200 case Z80_CC_NZ: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
2201 cond = CC_NZ; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
2202 case Z80_CC_Z: |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2203 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_Z), SZ_B); |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
2204 break; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
2205 case Z80_CC_NC: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
2206 cond = CC_NZ; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
2207 case Z80_CC_C: |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2208 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B); |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
2209 break; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
2210 case Z80_CC_PO: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
2211 cond = CC_NZ; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
2212 case Z80_CC_PE: |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2213 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_PV), SZ_B); |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
2214 break; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
2215 case Z80_CC_P: |
367
f20562f2a570
Fix P condition in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
366
diff
changeset
|
2216 cond = CC_NZ; |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
2217 case Z80_CC_M: |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2218 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_S), SZ_B); |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
2219 break; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
2220 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2221 uint8_t *no_call_off = code->cur+1; |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2222 jcc(code, cond, code->cur+2); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2223 cycles(&opts->gen, 1);//Last of the above T states takes an extra cycle in the true case |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2224 sub_ir(code, 2, opts->regs[Z80_SP], SZ_W); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2225 mov_ir(code, address + 3, opts->gen.scratch1, SZ_W); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2226 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch2, SZ_W); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2227 call(code, opts->write_16_highfirst);//T States: 3, 3 |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
2228 code_ptr call_dst = z80_get_native_address(context, inst->immed); |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
2229 if (!call_dst) { |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
2230 opts->gen.deferred = defer_address(opts->gen.deferred, inst->immed, code->cur + 1); |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
2231 //fake address to force large displacement |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
2232 call_dst = code->cur + 256; |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
2233 } |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
2234 jmp(code, call_dst); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2235 *no_call_off = code->cur - (no_call_off+1); |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
2236 break; |
682 | 2237 } |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2238 case Z80_RET: |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
2239 cycles(&opts->gen, num_cycles);//T States: 4 |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2240 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2241 call(code, opts->read_16);//T STates: 3, 3 |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2242 add_ir(code, 2, opts->regs[Z80_SP], SZ_W); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2243 call(code, opts->native_addr); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2244 jmp_r(code, opts->gen.scratch1); |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2245 break; |
246
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
2246 case Z80_RETCC: { |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
2247 cycles(&opts->gen, num_cycles + 1);//T States: 5 |
246
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
2248 uint8_t cond = CC_Z; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
2249 switch (inst->reg) |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
2250 { |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
2251 case Z80_CC_NZ: |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
2252 cond = CC_NZ; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
2253 case Z80_CC_Z: |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2254 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_Z), SZ_B); |
246
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
2255 break; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
2256 case Z80_CC_NC: |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
2257 cond = CC_NZ; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
2258 case Z80_CC_C: |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2259 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B); |
246
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
2260 break; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
2261 case Z80_CC_PO: |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
2262 cond = CC_NZ; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
2263 case Z80_CC_PE: |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2264 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_PV), SZ_B); |
246
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
2265 break; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
2266 case Z80_CC_P: |
367
f20562f2a570
Fix P condition in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
366
diff
changeset
|
2267 cond = CC_NZ; |
246
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
2268 case Z80_CC_M: |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2269 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_S), SZ_B); |
246
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
2270 break; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
2271 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2272 uint8_t *no_call_off = code->cur+1; |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2273 jcc(code, cond, code->cur+2); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2274 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2275 call(code, opts->read_16);//T STates: 3, 3 |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2276 add_ir(code, 2, opts->regs[Z80_SP], SZ_W); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2277 call(code, opts->native_addr); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2278 jmp_r(code, opts->gen.scratch1); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2279 *no_call_off = code->cur - (no_call_off+1); |
246
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
2280 break; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
2281 } |
283
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
2282 case Z80_RETI: |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
2283 //For some systems, this may need a callback for signalling interrupt routine completion |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
2284 cycles(&opts->gen, num_cycles);//T States: 4, 4 |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2285 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2286 call(code, opts->read_16);//T STates: 3, 3 |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2287 add_ir(code, 2, opts->regs[Z80_SP], SZ_W); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2288 call(code, opts->native_addr); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2289 jmp_r(code, opts->gen.scratch1); |
283
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
2290 break; |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
2291 case Z80_RETN: |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
2292 cycles(&opts->gen, num_cycles);//T States: 4, 4 |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2293 mov_rdispr(code, opts->gen.context_reg, offsetof(z80_context, iff2), opts->gen.scratch2, SZ_B); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2294 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2295 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, offsetof(z80_context, iff1), SZ_B); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2296 call(code, opts->read_16);//T STates: 3, 3 |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2297 add_ir(code, 2, opts->regs[Z80_SP], SZ_W); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2298 call(code, opts->native_addr); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2299 jmp_r(code, opts->gen.scratch1); |
283
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
2300 break; |
241
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
2301 case Z80_RST: { |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
2302 //RST is basically CALL to an address in page 0 |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
2303 cycles(&opts->gen, num_cycles + 1);//T States: 5 |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2304 sub_ir(code, 2, opts->regs[Z80_SP], SZ_W); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2305 mov_ir(code, address + 1, opts->gen.scratch1, SZ_W); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2306 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch2, SZ_W); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2307 call(code, opts->write_16_highfirst);//T States: 3, 3 |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2308 code_ptr call_dst = z80_get_native_address(context, inst->immed); |
241
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
2309 if (!call_dst) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2310 opts->gen.deferred = defer_address(opts->gen.deferred, inst->immed, code->cur + 1); |
241
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
2311 //fake address to force large displacement |
601
f0061e3d2ad9
Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor
Michael Pavone <pavone@retrodev.com>
parents:
598
diff
changeset
|
2312 call_dst = code->cur + 256; |
241
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
2313 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2314 jmp(code, call_dst); |
241
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
2315 break; |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
2316 } |
284
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
2317 case Z80_IN: |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
2318 if (inst->addr_mode == Z80_IMMED_INDIRECT) { |
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
2319 num_cycles += 3; |
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
2320 } |
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
2321 cycles(&opts->gen, num_cycles);//T States: 4 3/4 |
284
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
2322 if (inst->addr_mode == Z80_IMMED_INDIRECT) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2323 mov_ir(code, inst->immed, opts->gen.scratch1, SZ_B); |
284
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
2324 } else { |
1260
cad1642baf66
Fix implementation of in c and out c on 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
1225
diff
changeset
|
2325 zreg_to_native(opts, Z80_C, opts->gen.scratch2); |
284
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
2326 } |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2327 call(code, opts->read_io); |
1042
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
2328 if (inst->addr_mode != Z80_IMMED_INDIRECT) { |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
2329 or_rr(code, opts->gen.scratch1, opts->gen.scratch1, SZ_B); |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
2330 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B); |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
2331 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
2332 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV)); |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
2333 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
2334 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
2335 } |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
2336 if (inst->reg != Z80_UNUSED) { |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
2337 translate_z80_reg(inst, &dst_op, opts); |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
2338 if (dst_op.mode == MODE_REG_DIRECT) { |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
2339 mov_rr(code, opts->gen.scratch1, dst_op.base, SZ_B); |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
2340 } else { |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
2341 mov_rrdisp(code, opts->gen.scratch1, dst_op.base, dst_op.disp, SZ_B); |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
2342 } |
735
539d12fa6a4d
Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function.
Michael Pavone <pavone@retrodev.com>
parents:
734
diff
changeset
|
2343 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2344 z80_save_reg(inst, opts); |
284
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
2345 break; |
1060 | 2346 case Z80_INI: |
2347 cycles(&opts->gen, num_cycles + 1);//T States: 4, 5 | |
2348 //read from IO (C) | |
2349 zreg_to_native(opts, Z80_BC, opts->gen.scratch1); | |
2350 call(code, opts->read_io);//T states 3 | |
2351 | |
2352 //undocumented N flag behavior | |
2353 //flag set on bit 7 of value written | |
2354 bt_ir(code, 7, opts->gen.scratch1, SZ_B); | |
2355 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_N)); | |
2356 //save value to be written for flag calculation, as the write func does not | |
2357 //guarantee that it's preserved across the call | |
2358 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, offsetof(z80_context, scratch1), SZ_B); | |
2359 | |
2360 //write to (HL) | |
2361 zreg_to_native(opts, Z80_HL, opts->gen.scratch2); | |
2362 call(code, opts->write_8);//T states 4 | |
2363 cycles(&opts->gen, 1); | |
2364 | |
2365 //increment HL | |
2366 if (opts->regs[Z80_HL] >= 0) { | |
2367 add_ir(code, 1, opts->regs[Z80_HL], SZ_W); | |
2368 } else { | |
2369 add_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_B); | |
2370 } | |
2371 mov_rdispr(code, opts->gen.context_reg, offsetof(z80_context, scratch1), opts->gen.scratch1, SZ_B); | |
2372 if (opts->regs[Z80_C] >= 0) { | |
2373 add_rr(code, opts->regs[Z80_C], opts->gen.scratch1, SZ_B); | |
2374 } else { | |
2375 add_rdispr(code, opts->gen.context_reg, zr_off(Z80_C), opts->gen.scratch1, SZ_B); | |
2376 } | |
2377 add_ir(code, 1, opts->gen.scratch1, SZ_B); | |
2378 //undocumented C and H flag behavior | |
2379 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); | |
2380 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H)); | |
2381 //decrement B | |
2382 if (opts->regs[Z80_B] >= 0) { | |
2383 sub_ir(code, 1, opts->regs[Z80_B], SZ_B); | |
2384 mov_rrdisp(code, opts->regs[Z80_B], opts->gen.context_reg, zf_off(ZF_XY), SZ_B); | |
2385 } else { | |
2386 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_B), SZ_B); | |
2387 } | |
2388 //undocumented Z and S flag behavior, set based on decrement of B | |
2389 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); | |
2390 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); | |
2391 //crazy undocumented P/V flag behavior | |
2392 and_ir(code, 7, opts->gen.scratch1, SZ_B); | |
2393 if (opts->regs[Z80_B] >= 0) { | |
2394 //deal with silly x86-64 restrictions on *H registers | |
2395 ror_ir(code, 8, opts->regs[Z80_BC], SZ_W); | |
2396 xor_rr(code, opts->regs[Z80_C], opts->gen.scratch1, SZ_B); | |
2397 ror_ir(code, 8, opts->regs[Z80_BC], SZ_W); | |
2398 } else { | |
2399 xor_rdispr(code, opts->gen.context_reg, zr_off(Z80_B), opts->gen.scratch1, SZ_B); | |
2400 } | |
2401 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV)); | |
2402 break; | |
1061 | 2403 case Z80_INIR: { |
2404 cycles(&opts->gen, num_cycles + 1);//T States: 4, 5 | |
2405 //read from IO (C) | |
2406 zreg_to_native(opts, Z80_BC, opts->gen.scratch1); | |
2407 call(code, opts->read_io);//T states 3 | |
2408 | |
2409 //undocumented N flag behavior | |
2410 //flag set on bit 7 of value written | |
2411 bt_ir(code, 7, opts->gen.scratch1, SZ_B); | |
2412 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_N)); | |
2413 //save value to be written for flag calculation, as the write func does not | |
2414 //guarantee that it's preserved across the call | |
2415 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, offsetof(z80_context, scratch1), SZ_B); | |
2416 | |
2417 //write to (HL) | |
2418 zreg_to_native(opts, Z80_HL, opts->gen.scratch2); | |
2419 call(code, opts->write_8);//T states 4 | |
2420 cycles(&opts->gen, 1); | |
2421 | |
2422 //increment HL | |
2423 if (opts->regs[Z80_HL] >= 0) { | |
2424 add_ir(code, 1, opts->regs[Z80_HL], SZ_W); | |
2425 } else { | |
2426 add_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_B); | |
2427 } | |
2428 mov_rdispr(code, opts->gen.context_reg, offsetof(z80_context, scratch1), opts->gen.scratch1, SZ_B); | |
2429 if (opts->regs[Z80_C] >= 0) { | |
2430 add_rr(code, opts->regs[Z80_C], opts->gen.scratch1, SZ_B); | |
2431 } else { | |
2432 add_rdispr(code, opts->gen.context_reg, zr_off(Z80_C), opts->gen.scratch1, SZ_B); | |
2433 } | |
2434 add_ir(code, 1, opts->gen.scratch1, SZ_B); | |
2435 //undocumented C and H flag behavior | |
2436 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); | |
2437 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H)); | |
2438 //decrement B | |
2439 if (opts->regs[Z80_B] >= 0) { | |
2440 sub_ir(code, 1, opts->regs[Z80_B], SZ_B); | |
2441 mov_rrdisp(code, opts->regs[Z80_B], opts->gen.context_reg, zf_off(ZF_XY), SZ_B); | |
2442 } else { | |
2443 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_B), SZ_B); | |
2444 } | |
2445 //undocumented Z and S flag behavior, set based on decrement of B | |
2446 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); | |
2447 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); | |
2448 //crazy undocumented P/V flag behavior | |
2449 and_ir(code, 7, opts->gen.scratch1, SZ_B); | |
2450 if (opts->regs[Z80_B] >= 0) { | |
2451 //deal with silly x86-64 restrictions on *H registers | |
2452 ror_ir(code, 8, opts->regs[Z80_BC], SZ_W); | |
2453 xor_rr(code, opts->regs[Z80_C], opts->gen.scratch1, SZ_B); | |
2454 ror_ir(code, 8, opts->regs[Z80_BC], SZ_W); | |
2455 } else { | |
2456 xor_rdispr(code, opts->gen.context_reg, zr_off(Z80_B), opts->gen.scratch1, SZ_B); | |
2457 } | |
2458 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV)); | |
2459 if (opts->regs[Z80_B] >= 0) { | |
2460 cmp_ir(code, 0, opts->regs[Z80_B], SZ_B); | |
2461 } else { | |
2462 cmp_irdisp(code, 0, opts->gen.context_reg, zr_off(Z80_B), SZ_B); | |
2463 } | |
2464 code_ptr done = code->cur+1; | |
2465 jcc(code, CC_Z, code->cur+2); | |
2466 cycles(&opts->gen, 5); | |
2467 jmp(code, start); | |
2468 *done = code->cur - (done + 1); | |
2469 break; | |
2470 } | |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2471 case Z80_IND: |
1062
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2472 cycles(&opts->gen, num_cycles + 1);//T States: 4, 5 |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2473 //read from IO (C) |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2474 zreg_to_native(opts, Z80_BC, opts->gen.scratch1); |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2475 call(code, opts->read_io);//T states 3 |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2476 |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2477 //undocumented N flag behavior |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2478 //flag set on bit 7 of value written |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2479 bt_ir(code, 7, opts->gen.scratch1, SZ_B); |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2480 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_N)); |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2481 //save value to be written for flag calculation, as the write func does not |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2482 //guarantee that it's preserved across the call |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2483 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, offsetof(z80_context, scratch1), SZ_B); |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2484 |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2485 //write to (HL) |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2486 zreg_to_native(opts, Z80_HL, opts->gen.scratch2); |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2487 call(code, opts->write_8);//T states 4 |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2488 cycles(&opts->gen, 1); |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2489 |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2490 //decrement HL |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2491 if (opts->regs[Z80_HL] >= 0) { |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2492 sub_ir(code, 1, opts->regs[Z80_HL], SZ_W); |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2493 } else { |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2494 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_B); |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2495 } |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2496 mov_rdispr(code, opts->gen.context_reg, offsetof(z80_context, scratch1), opts->gen.scratch1, SZ_B); |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2497 if (opts->regs[Z80_C] >= 0) { |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2498 add_rr(code, opts->regs[Z80_C], opts->gen.scratch1, SZ_B); |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2499 } else { |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2500 add_rdispr(code, opts->gen.context_reg, zr_off(Z80_C), opts->gen.scratch1, SZ_B); |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2501 } |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2502 add_ir(code, 1, opts->gen.scratch1, SZ_B); |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2503 //undocumented C and H flag behavior |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2504 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2505 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H)); |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2506 //decrement B |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2507 if (opts->regs[Z80_B] >= 0) { |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2508 sub_ir(code, 1, opts->regs[Z80_B], SZ_B); |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2509 mov_rrdisp(code, opts->regs[Z80_B], opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2510 } else { |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2511 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_B), SZ_B); |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2512 } |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2513 //undocumented Z and S flag behavior, set based on decrement of B |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2514 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2515 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2516 //crazy undocumented P/V flag behavior |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2517 and_ir(code, 7, opts->gen.scratch1, SZ_B); |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2518 if (opts->regs[Z80_B] >= 0) { |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2519 //deal with silly x86-64 restrictions on *H registers |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2520 ror_ir(code, 8, opts->regs[Z80_BC], SZ_W); |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2521 xor_rr(code, opts->regs[Z80_C], opts->gen.scratch1, SZ_B); |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2522 ror_ir(code, 8, opts->regs[Z80_BC], SZ_W); |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2523 } else { |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2524 xor_rdispr(code, opts->gen.context_reg, zr_off(Z80_B), opts->gen.scratch1, SZ_B); |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2525 } |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2526 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV)); |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2527 break; |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2528 case Z80_INDR: { |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2529 cycles(&opts->gen, num_cycles + 1);//T States: 4, 5 |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2530 //read from IO (C) |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2531 zreg_to_native(opts, Z80_BC, opts->gen.scratch1); |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2532 call(code, opts->read_io);//T states 3 |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2533 |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2534 //undocumented N flag behavior |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2535 //flag set on bit 7 of value written |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2536 bt_ir(code, 7, opts->gen.scratch1, SZ_B); |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2537 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_N)); |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2538 //save value to be written for flag calculation, as the write func does not |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2539 //guarantee that it's preserved across the call |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2540 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, offsetof(z80_context, scratch1), SZ_B); |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2541 |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2542 //write to (HL) |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2543 zreg_to_native(opts, Z80_HL, opts->gen.scratch2); |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2544 call(code, opts->write_8);//T states 4 |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2545 cycles(&opts->gen, 1); |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2546 |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2547 //decrement HL |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2548 if (opts->regs[Z80_HL] >= 0) { |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2549 sub_ir(code, 1, opts->regs[Z80_HL], SZ_W); |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2550 } else { |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2551 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_B); |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2552 } |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2553 mov_rdispr(code, opts->gen.context_reg, offsetof(z80_context, scratch1), opts->gen.scratch1, SZ_B); |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2554 if (opts->regs[Z80_C] >= 0) { |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2555 add_rr(code, opts->regs[Z80_C], opts->gen.scratch1, SZ_B); |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2556 } else { |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2557 add_rdispr(code, opts->gen.context_reg, zr_off(Z80_C), opts->gen.scratch1, SZ_B); |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2558 } |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2559 add_ir(code, 1, opts->gen.scratch1, SZ_B); |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2560 //undocumented C and H flag behavior |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2561 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2562 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H)); |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2563 //decrement B |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2564 if (opts->regs[Z80_B] >= 0) { |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2565 sub_ir(code, 1, opts->regs[Z80_B], SZ_B); |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2566 mov_rrdisp(code, opts->regs[Z80_B], opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2567 } else { |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2568 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_B), SZ_B); |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2569 } |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2570 //undocumented Z and S flag behavior, set based on decrement of B |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2571 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2572 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2573 //crazy undocumented P/V flag behavior |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2574 and_ir(code, 7, opts->gen.scratch1, SZ_B); |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2575 if (opts->regs[Z80_B] >= 0) { |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2576 //deal with silly x86-64 restrictions on *H registers |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2577 ror_ir(code, 8, opts->regs[Z80_BC], SZ_W); |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2578 xor_rr(code, opts->regs[Z80_C], opts->gen.scratch1, SZ_B); |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2579 ror_ir(code, 8, opts->regs[Z80_BC], SZ_W); |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2580 } else { |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2581 xor_rdispr(code, opts->gen.context_reg, zr_off(Z80_B), opts->gen.scratch1, SZ_B); |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2582 } |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2583 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV)); |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2584 if (opts->regs[Z80_B] >= 0) { |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2585 cmp_ir(code, 0, opts->regs[Z80_B], SZ_B); |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2586 } else { |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2587 cmp_irdisp(code, 0, opts->gen.context_reg, zr_off(Z80_B), SZ_B); |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2588 } |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2589 code_ptr done = code->cur+1; |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2590 jcc(code, CC_Z, code->cur+2); |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2591 cycles(&opts->gen, 5); |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2592 jmp(code, start); |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2593 *done = code->cur - (done + 1); |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2594 break; |
779acbfb74d0
Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents:
1061
diff
changeset
|
2595 } |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2596 case Z80_OUT: |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
2597 if (inst->reg == Z80_A) { |
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
2598 num_cycles += 3; |
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
2599 } |
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
2600 cycles(&opts->gen, num_cycles);//T States: 4 3/4 |
284
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
2601 if ((inst->addr_mode & 0x1F) == Z80_IMMED_INDIRECT) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2602 mov_ir(code, inst->immed, opts->gen.scratch2, SZ_B); |
284
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
2603 } else { |
735
539d12fa6a4d
Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function.
Michael Pavone <pavone@retrodev.com>
parents:
734
diff
changeset
|
2604 zreg_to_native(opts, Z80_C, opts->gen.scratch2); |
284
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
2605 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2606 translate_z80_reg(inst, &src_op, opts); |
735
539d12fa6a4d
Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function.
Michael Pavone <pavone@retrodev.com>
parents:
734
diff
changeset
|
2607 if (src_op.mode == MODE_REG_DIRECT) { |
539d12fa6a4d
Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function.
Michael Pavone <pavone@retrodev.com>
parents:
734
diff
changeset
|
2608 mov_rr(code, src_op.base, opts->gen.scratch1, SZ_B); |
539d12fa6a4d
Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function.
Michael Pavone <pavone@retrodev.com>
parents:
734
diff
changeset
|
2609 } else if (src_op.mode == MODE_IMMED) { |
539d12fa6a4d
Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function.
Michael Pavone <pavone@retrodev.com>
parents:
734
diff
changeset
|
2610 mov_ir(code, src_op.disp, opts->gen.scratch1, SZ_B); |
539d12fa6a4d
Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function.
Michael Pavone <pavone@retrodev.com>
parents:
734
diff
changeset
|
2611 } else { |
539d12fa6a4d
Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function.
Michael Pavone <pavone@retrodev.com>
parents:
734
diff
changeset
|
2612 mov_rdispr(code, src_op.base, src_op.disp, opts->gen.scratch1, SZ_B); |
539d12fa6a4d
Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function.
Michael Pavone <pavone@retrodev.com>
parents:
734
diff
changeset
|
2613 } |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2614 call(code, opts->write_io); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2615 z80_save_reg(inst, opts); |
284
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
2616 break; |
1040
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2617 case Z80_OUTI: |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
2618 cycles(&opts->gen, num_cycles + 1);//T States: 4, 5 |
1040
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2619 //read from (HL) |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2620 zreg_to_native(opts, Z80_HL, opts->gen.scratch1); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2621 call(code, opts->read_8);//T states 3 |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2622 //undocumented N flag behavior |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2623 //flag set on bit 7 of value written |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2624 bt_ir(code, 7, opts->gen.scratch1, SZ_B); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2625 setcc_rdisp(code, CC_NC, opts->gen.context_reg, zf_off(ZF_N)); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2626 //write to IO (C) |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2627 zreg_to_native(opts, Z80_C, opts->gen.scratch2); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2628 call(code, opts->write_io);//T states 4 |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2629 //increment HL |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2630 if (opts->regs[Z80_HL] >= 0) { |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2631 add_ir(code, 1, opts->regs[Z80_HL], SZ_W); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2632 add_rr(code, opts->regs[Z80_L], opts->gen.scratch1, SZ_B); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2633 } else { |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2634 add_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_B); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2635 add_rdispr(code, opts->gen.context_reg, zr_off(Z80_L), opts->gen.scratch1, SZ_B); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2636 } |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2637 //undocumented C and H flag behavior |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2638 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2639 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H)); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2640 //decrement B |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2641 if (opts->regs[Z80_B] >= 0) { |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2642 sub_ir(code, 1, opts->regs[Z80_B], SZ_B); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2643 } else { |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2644 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_B), SZ_B); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2645 } |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2646 //undocumented Z and S flag behavior, set based on decrement of B |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2647 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2648 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2649 //crazy undocumented P/V flag behavior |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2650 and_ir(code, 7, opts->gen.scratch1, SZ_B); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2651 if (opts->regs[Z80_B] >= 0) { |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2652 //deal with silly x86-64 restrictions on *H registers |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2653 ror_ir(code, 8, opts->regs[Z80_BC], SZ_W); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2654 xor_rr(code, opts->regs[Z80_C], opts->gen.scratch1, SZ_B); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2655 ror_ir(code, 8, opts->regs[Z80_BC], SZ_W); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2656 } else { |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2657 xor_rdispr(code, opts->gen.context_reg, zr_off(Z80_B), opts->gen.scratch1, SZ_B); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2658 } |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2659 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV)); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2660 break; |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2661 case Z80_OTIR: { |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2662 code_ptr start = code->cur; |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
2663 cycles(&opts->gen, num_cycles + 1);//T States: 4, 5 |
1040
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2664 //read from (HL) |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2665 zreg_to_native(opts, Z80_HL, opts->gen.scratch1); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2666 call(code, opts->read_8);//T states 3 |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2667 //undocumented N flag behavior |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2668 //flag set on bit 7 of value written |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2669 bt_ir(code, 7, opts->gen.scratch1, SZ_B); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2670 setcc_rdisp(code, CC_NC, opts->gen.context_reg, zf_off(ZF_N)); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2671 //write to IO (C) |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2672 zreg_to_native(opts, Z80_C, opts->gen.scratch2); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2673 call(code, opts->write_io);//T states 4 |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2674 //increment HL |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2675 if (opts->regs[Z80_HL] >= 0) { |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2676 add_ir(code, 1, opts->regs[Z80_HL], SZ_W); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2677 add_rr(code, opts->regs[Z80_L], opts->gen.scratch1, SZ_B); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2678 } else { |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2679 add_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_B); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2680 add_rdispr(code, opts->gen.context_reg, zr_off(Z80_L), opts->gen.scratch1, SZ_B); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2681 } |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2682 //undocumented C and H flag behavior |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2683 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2684 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H)); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2685 //decrement B |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2686 if (opts->regs[Z80_B] >= 0) { |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2687 sub_ir(code, 1, opts->regs[Z80_B], SZ_B); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2688 } else { |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2689 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_B), SZ_B); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2690 } |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2691 //undocumented Z and S flag behavior, set based on decrement of B |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2692 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2693 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2694 //crazy undocumented P/V flag behavior |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2695 and_ir(code, 7, opts->gen.scratch1, SZ_B); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2696 if (opts->regs[Z80_B] >= 0) { |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2697 //deal with silly x86-64 restrictions on *H registers |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2698 ror_ir(code, 8, opts->regs[Z80_BC], SZ_W); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2699 xor_rr(code, opts->regs[Z80_C], opts->gen.scratch1, SZ_B); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2700 ror_ir(code, 8, opts->regs[Z80_BC], SZ_W); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2701 } else { |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2702 xor_rdispr(code, opts->gen.context_reg, zr_off(Z80_B), opts->gen.scratch1, SZ_B); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2703 } |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2704 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV)); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2705 if (opts->regs[Z80_B] >= 0) { |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2706 cmp_ir(code, 0, opts->regs[Z80_B], SZ_B); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2707 } else { |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2708 cmp_irdisp(code, 0, opts->gen.context_reg, zr_off(Z80_B), SZ_B); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2709 } |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2710 code_ptr done = code->cur+1; |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2711 jcc(code, CC_Z, code->cur+2); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2712 cycles(&opts->gen, 5); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2713 jmp(code, start); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2714 *done = code->cur - (done + 1); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2715 break; |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2716 } |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2717 case Z80_OUTD: |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
2718 cycles(&opts->gen, num_cycles + 1);//T States: 4, 5 |
1040
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2719 //read from (HL) |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2720 zreg_to_native(opts, Z80_HL, opts->gen.scratch1); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2721 call(code, opts->read_8);//T states 3 |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2722 //undocumented N flag behavior |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2723 //flag set on bit 7 of value written |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2724 bt_ir(code, 7, opts->gen.scratch1, SZ_B); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2725 setcc_rdisp(code, CC_NC, opts->gen.context_reg, zf_off(ZF_N)); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2726 //write to IO (C) |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2727 zreg_to_native(opts, Z80_C, opts->gen.scratch2); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2728 call(code, opts->write_io);//T states 4 |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2729 //decrement HL |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2730 if (opts->regs[Z80_HL] >= 0) { |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2731 sub_ir(code, 1, opts->regs[Z80_HL], SZ_W); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2732 add_rr(code, opts->regs[Z80_L], opts->gen.scratch1, SZ_B); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2733 } else { |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2734 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_B); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2735 add_rdispr(code, opts->gen.context_reg, zr_off(Z80_L), opts->gen.scratch1, SZ_B); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2736 } |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2737 //undocumented C and H flag behavior |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2738 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2739 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H)); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2740 //decrement B |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2741 if (opts->regs[Z80_B] >= 0) { |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2742 sub_ir(code, 1, opts->regs[Z80_B], SZ_B); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2743 } else { |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2744 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_B), SZ_B); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2745 } |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2746 //undocumented Z and S flag behavior, set based on decrement of B |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2747 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2748 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2749 //crazy undocumented P/V flag behavior |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2750 and_ir(code, 7, opts->gen.scratch1, SZ_B); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2751 if (opts->regs[Z80_B] >= 0) { |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2752 //deal with silly x86-64 restrictions on *H registers |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2753 ror_ir(code, 8, opts->regs[Z80_BC], SZ_W); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2754 xor_rr(code, opts->regs[Z80_C], opts->gen.scratch1, SZ_B); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2755 ror_ir(code, 8, opts->regs[Z80_BC], SZ_W); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2756 } else { |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2757 xor_rdispr(code, opts->gen.context_reg, zr_off(Z80_B), opts->gen.scratch1, SZ_B); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2758 } |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2759 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV)); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2760 break; |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2761 case Z80_OTDR: { |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2762 code_ptr start = code->cur; |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
2763 cycles(&opts->gen, num_cycles + 1);//T States: 4, 5 |
1040
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2764 //read from (HL) |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2765 zreg_to_native(opts, Z80_HL, opts->gen.scratch1); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2766 call(code, opts->read_8);//T states 3 |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2767 //undocumented N flag behavior |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2768 //flag set on bit 7 of value written |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2769 bt_ir(code, 7, opts->gen.scratch1, SZ_B); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2770 setcc_rdisp(code, CC_NC, opts->gen.context_reg, zf_off(ZF_N)); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2771 //write to IO (C) |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2772 zreg_to_native(opts, Z80_C, opts->gen.scratch2); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2773 call(code, opts->write_io);//T states 4 |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2774 //increment HL |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2775 if (opts->regs[Z80_HL] >= 0) { |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2776 sub_ir(code, 1, opts->regs[Z80_HL], SZ_W); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2777 add_rr(code, opts->regs[Z80_L], opts->gen.scratch1, SZ_B); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2778 } else { |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2779 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_B); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2780 add_rdispr(code, opts->gen.context_reg, zr_off(Z80_L), opts->gen.scratch1, SZ_B); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2781 } |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2782 //undocumented C and H flag behavior |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2783 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2784 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H)); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2785 //decrement B |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2786 if (opts->regs[Z80_B] >= 0) { |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2787 sub_ir(code, 1, opts->regs[Z80_B], SZ_B); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2788 } else { |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2789 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_B), SZ_B); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2790 } |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2791 //undocumented Z and S flag behavior, set based on decrement of B |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2792 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2793 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2794 //crazy undocumented P/V flag behavior |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2795 and_ir(code, 7, opts->gen.scratch1, SZ_B); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2796 if (opts->regs[Z80_B] >= 0) { |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2797 //deal with silly x86-64 restrictions on *H registers |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2798 ror_ir(code, 8, opts->regs[Z80_BC], SZ_W); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2799 xor_rr(code, opts->regs[Z80_C], opts->gen.scratch1, SZ_B); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2800 ror_ir(code, 8, opts->regs[Z80_BC], SZ_W); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2801 } else { |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2802 xor_rdispr(code, opts->gen.context_reg, zr_off(Z80_B), opts->gen.scratch1, SZ_B); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2803 } |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2804 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV)); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2805 if (opts->regs[Z80_B] >= 0) { |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2806 cmp_ir(code, 0, opts->regs[Z80_B], SZ_B); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2807 } else { |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2808 cmp_irdisp(code, 0, opts->gen.context_reg, zr_off(Z80_B), SZ_B); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2809 } |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2810 code_ptr done = code->cur+1; |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2811 jcc(code, CC_Z, code->cur+2); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2812 cycles(&opts->gen, 5); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2813 jmp(code, start); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2814 *done = code->cur - (done + 1); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2815 break; |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2816 } |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2817 default: { |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2818 char disbuf[80]; |
314
54c0e5f22198
Show absolute addresses for JR, JRCC and DJNZ in Z80 disassembler
Mike Pavone <pavone@retrodev.com>
parents:
313
diff
changeset
|
2819 z80_disasm(inst, disbuf, address); |
259
d9417261366f
Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called.
Mike Pavone <pavone@retrodev.com>
parents:
257
diff
changeset
|
2820 FILE * f = fopen("zram.bin", "wb"); |
d9417261366f
Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called.
Mike Pavone <pavone@retrodev.com>
parents:
257
diff
changeset
|
2821 fwrite(context->mem_pointers[0], 1, 8 * 1024, f); |
d9417261366f
Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called.
Mike Pavone <pavone@retrodev.com>
parents:
257
diff
changeset
|
2822 fclose(f); |
792
724bbec47f86
Use a new fatal_error function instead of calling fprintf and exit for fatal errors. This new function more gracefully handles the case in which BlastEm was not started from a terminal or disconnected from ther terminal (Windows).
Michael Pavone <pavone@retrodev.com>
parents:
755
diff
changeset
|
2823 fatal_error("unimplemented Z80 instruction: %s at %X\nZ80 RAM has been saved to zram.bin for debugging", disbuf, address); |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2824 } |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2825 } |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2826 } |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2827 |
627
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
2828 uint8_t * z80_interp_handler(uint8_t opcode, z80_context * context) |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
2829 { |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
2830 if (!context->interp_code[opcode]) { |
755
7306b3967c51
Cleanup some warnings under clang through a combination of code fixes and supressing specific warnings
Michael Pavone <pavone@retrodev.com>
parents:
737
diff
changeset
|
2831 if (opcode == 0xCB || (opcode >= 0xDD && (opcode & 0xF) == 0xD)) { |
792
724bbec47f86
Use a new fatal_error function instead of calling fprintf and exit for fatal errors. This new function more gracefully handles the case in which BlastEm was not started from a terminal or disconnected from ther terminal (Windows).
Michael Pavone <pavone@retrodev.com>
parents:
755
diff
changeset
|
2832 fatal_error("Encountered prefix byte %X at address %X. Z80 interpeter doesn't support those yet.", opcode, context->pc); |
627
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
2833 } |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
2834 uint8_t codebuf[8]; |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
2835 memset(codebuf, 0, sizeof(codebuf)); |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
2836 codebuf[0] = opcode; |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
2837 z80inst inst; |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
2838 uint8_t * after = z80_decode(codebuf, &inst); |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
2839 if (after - codebuf > 1) { |
792
724bbec47f86
Use a new fatal_error function instead of calling fprintf and exit for fatal errors. This new function more gracefully handles the case in which BlastEm was not started from a terminal or disconnected from ther terminal (Windows).
Michael Pavone <pavone@retrodev.com>
parents:
755
diff
changeset
|
2840 fatal_error("Encountered multi-byte Z80 instruction at %X. Z80 interpeter doesn't support those yet.", context->pc); |
627
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
2841 } |
652 | 2842 |
2843 z80_options * opts = context->options; | |
2844 code_info *code = &opts->gen.code; | |
2845 check_alloc_code(code, ZMAX_NATIVE_SIZE); | |
2846 context->interp_code[opcode] = code->cur; | |
2847 translate_z80inst(&inst, context, 0, 1); | |
2848 mov_rdispr(code, opts->gen.context_reg, offsetof(z80_context, pc), opts->gen.scratch1, SZ_W); | |
2849 add_ir(code, after - codebuf, opts->gen.scratch1, SZ_W); | |
2850 call(code, opts->native_addr); | |
2851 jmp_r(code, opts->gen.scratch1); | |
715
1c2020d3e275
Call z80_handle_deferred after generating an insruction handler so that instructions like rst work correctly
Michael Pavone <pavone@retrodev.com>
parents:
712
diff
changeset
|
2852 z80_handle_deferred(context); |
627
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
2853 } |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
2854 return context->interp_code[opcode]; |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
2855 } |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
2856 |
652 | 2857 code_info z80_make_interp_stub(z80_context * context, uint16_t address) |
627
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
2858 { |
652 | 2859 z80_options *opts = context->options; |
2860 code_info * code = &opts->gen.code; | |
2861 check_alloc_code(code, 32); | |
2862 code_info stub = {code->cur, NULL}; | |
627
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
2863 //TODO: make this play well with the breakpoint code |
652 | 2864 mov_ir(code, address, opts->gen.scratch1, SZ_W); |
2865 call(code, opts->read_8); | |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
2866 //opcode fetch M-cycles have one extra T-state |
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
2867 cycles(&opts->gen, 1); |
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
2868 //TODO: increment R |
652 | 2869 check_cycles_int(&opts->gen, address); |
2870 call(code, opts->gen.save_context); | |
2871 mov_irdisp(code, address, opts->gen.context_reg, offsetof(z80_context, pc), SZ_W); | |
2872 push_r(code, opts->gen.context_reg); | |
712
382a2b5b70c0
Fix crash bug in Z80 interpreter
Michael Pavone <pavone@retrodev.com>
parents:
702
diff
changeset
|
2873 call_args(code, (code_ptr)z80_interp_handler, 2, opts->gen.scratch1, opts->gen.context_reg); |
664
bca748422bf0
Use SZ_PTR instead of SZ_Q in Z80 core for 32-bit compat
Michael Pavone <pavone@retrodev.com>
parents:
663
diff
changeset
|
2874 mov_rr(code, RAX, opts->gen.scratch1, SZ_PTR); |
652 | 2875 pop_r(code, opts->gen.context_reg); |
2876 call(code, opts->gen.load_context); | |
2877 jmp_r(code, opts->gen.scratch1); | |
2878 stub.last = code->cur; | |
2879 return stub; | |
627
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
2880 } |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
2881 |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
2882 |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2883 uint8_t * z80_get_native_address(z80_context * context, uint32_t address) |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2884 { |
1130
8f14767661fa
Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2885 z80_options *opts = context->options; |
8f14767661fa
Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2886 native_map_slot * native_code_map = opts->gen.native_code_map; |
8f14767661fa
Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2887 |
8f14767661fa
Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2888 memmap_chunk const *mem_chunk = find_map_chunk(address, &opts->gen, 0, NULL); |
8f14767661fa
Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2889 if (mem_chunk) { |
8f14767661fa
Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2890 //calculate the lowest alias for this address |
8f14767661fa
Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2891 address = mem_chunk->start + ((address - mem_chunk->start) & mem_chunk->mask); |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2892 } |
1130
8f14767661fa
Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2893 uint32_t chunk = address / NATIVE_CHUNK_SIZE; |
8f14767661fa
Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2894 if (!native_code_map[chunk].base) { |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2895 return NULL; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2896 } |
1130
8f14767661fa
Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2897 uint32_t offset = address % NATIVE_CHUNK_SIZE; |
8f14767661fa
Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2898 if (native_code_map[chunk].offsets[offset] == INVALID_OFFSET || native_code_map[chunk].offsets[offset] == EXTENSION_WORD) { |
8f14767661fa
Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2899 return NULL; |
8f14767661fa
Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2900 } |
8f14767661fa
Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2901 return native_code_map[chunk].base + native_code_map[chunk].offsets[offset]; |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2902 } |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2903 |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2904 uint8_t z80_get_native_inst_size(z80_options * opts, uint32_t address) |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2905 { |
1130
8f14767661fa
Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2906 uint32_t meta_off; |
1142
5c8b1c33ca10
Invalidate translated code on a cartridge bank change in SMS mode. Fix handling of bank 0
Michael Pavone <pavone@retrodev.com>
parents:
1131
diff
changeset
|
2907 memmap_chunk const *chunk = find_map_chunk(address, &opts->gen, MMAP_CODE, &meta_off); |
1130
8f14767661fa
Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2908 if (chunk) { |
8f14767661fa
Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2909 meta_off += (address - chunk->start) & chunk->mask; |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
2910 } |
1130
8f14767661fa
Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2911 uint32_t slot = meta_off/1024; |
8f14767661fa
Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2912 return opts->gen.ram_inst_sizes[slot][meta_off%1024]; |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
2913 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
2914 |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
2915 void z80_map_native_address(z80_context * context, uint32_t address, uint8_t * native_address, uint8_t size, uint8_t native_size) |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
2916 { |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2917 z80_options * opts = context->options; |
1130
8f14767661fa
Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2918 uint32_t meta_off; |
1142
5c8b1c33ca10
Invalidate translated code on a cartridge bank change in SMS mode. Fix handling of bank 0
Michael Pavone <pavone@retrodev.com>
parents:
1131
diff
changeset
|
2919 memmap_chunk const *mem_chunk = find_map_chunk(address, &opts->gen, MMAP_CODE, &meta_off); |
1130
8f14767661fa
Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2920 if (mem_chunk) { |
1142
5c8b1c33ca10
Invalidate translated code on a cartridge bank change in SMS mode. Fix handling of bank 0
Michael Pavone <pavone@retrodev.com>
parents:
1131
diff
changeset
|
2921 if (mem_chunk->flags & MMAP_CODE) { |
1130
8f14767661fa
Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2922 uint32_t masked = (address & mem_chunk->mask); |
8f14767661fa
Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2923 uint32_t final_off = masked + meta_off; |
8f14767661fa
Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2924 uint32_t ram_flags_off = final_off >> (opts->gen.ram_flags_shift + 3); |
8f14767661fa
Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2925 context->ram_code_flags[ram_flags_off] |= 1 << ((final_off >> opts->gen.ram_flags_shift) & 7); |
8f14767661fa
Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2926 |
8f14767661fa
Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2927 uint32_t slot = final_off / 1024; |
8f14767661fa
Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2928 if (!opts->gen.ram_inst_sizes[slot]) { |
8f14767661fa
Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2929 opts->gen.ram_inst_sizes[slot] = malloc(sizeof(uint8_t) * 1024); |
8f14767661fa
Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2930 } |
8f14767661fa
Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2931 opts->gen.ram_inst_sizes[slot][final_off % 1024] = native_size; |
8f14767661fa
Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2932 |
8f14767661fa
Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2933 //TODO: Deal with case in which end of instruction is in a different memory chunk |
8f14767661fa
Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2934 masked = (address + size - 1) & mem_chunk->mask; |
8f14767661fa
Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2935 final_off = masked + meta_off; |
8f14767661fa
Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2936 ram_flags_off = final_off >> (opts->gen.ram_flags_shift + 3); |
8f14767661fa
Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2937 context->ram_code_flags[ram_flags_off] |= 1 << ((final_off >> opts->gen.ram_flags_shift) & 7); |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2938 } |
1130
8f14767661fa
Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2939 //calculate the lowest alias for this address |
8f14767661fa
Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2940 address = mem_chunk->start + ((address - mem_chunk->start) & mem_chunk->mask); |
1222
60d73f42a606
Hacky fix so sound works in Project MD again
Michael Pavone <pavone@retrodev.com>
parents:
1182
diff
changeset
|
2941 } else { |
60d73f42a606
Hacky fix so sound works in Project MD again
Michael Pavone <pavone@retrodev.com>
parents:
1182
diff
changeset
|
2942 address &= opts->gen.address_mask; |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2943 } |
1130
8f14767661fa
Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2944 |
8f14767661fa
Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2945 native_map_slot *map = opts->gen.native_code_map + address / NATIVE_CHUNK_SIZE; |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2946 if (!map->base) { |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2947 map->base = native_address; |
1130
8f14767661fa
Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2948 map->offsets = malloc(sizeof(int32_t) * NATIVE_CHUNK_SIZE); |
8f14767661fa
Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2949 memset(map->offsets, 0xFF, sizeof(int32_t) * NATIVE_CHUNK_SIZE); |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2950 } |
1130
8f14767661fa
Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2951 map->offsets[address % NATIVE_CHUNK_SIZE] = native_address - map->base; |
1182
2a799f24563f
Fix regression in tracking of 3+ byte instructions in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1147
diff
changeset
|
2952 for(--size, address++; size; --size, address++) { |
1130
8f14767661fa
Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2953 address &= opts->gen.address_mask; |
8f14767661fa
Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2954 map = opts->gen.native_code_map + address / NATIVE_CHUNK_SIZE; |
8f14767661fa
Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2955 if (!map->base) { |
8f14767661fa
Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2956 map->base = native_address; |
8f14767661fa
Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2957 map->offsets = malloc(sizeof(int32_t) * NATIVE_CHUNK_SIZE); |
8f14767661fa
Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2958 memset(map->offsets, 0xFF, sizeof(int32_t) * NATIVE_CHUNK_SIZE); |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
2959 } |
1130
8f14767661fa
Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2960 |
1224
15c5be05e6a9
Ported correct but inefficient overlapping instruction handling from 68K core to Z80 core. Fixed remaining stack alignment issue for Z80 breakpoints on 64-bit. Probably still needs fixing for 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
1222
diff
changeset
|
2961 if (map->offsets[address % NATIVE_CHUNK_SIZE] == INVALID_OFFSET) { |
15c5be05e6a9
Ported correct but inefficient overlapping instruction handling from 68K core to Z80 core. Fixed remaining stack alignment issue for Z80 breakpoints on 64-bit. Probably still needs fixing for 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
1222
diff
changeset
|
2962 //TODO: better handling of potentially overlapping instructions |
15c5be05e6a9
Ported correct but inefficient overlapping instruction handling from 68K core to Z80 core. Fixed remaining stack alignment issue for Z80 breakpoints on 64-bit. Probably still needs fixing for 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
1222
diff
changeset
|
2963 map->offsets[address % NATIVE_CHUNK_SIZE] = EXTENSION_WORD; |
15c5be05e6a9
Ported correct but inefficient overlapping instruction handling from 68K core to Z80 core. Fixed remaining stack alignment issue for Z80 breakpoints on 64-bit. Probably still needs fixing for 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
1222
diff
changeset
|
2964 } |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
2965 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
2966 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
2967 |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
2968 #define INVALID_INSTRUCTION_START 0xFEEDFEED |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
2969 |
1130
8f14767661fa
Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2970 uint32_t z80_get_instruction_start(z80_context *context, uint32_t address) |
8f14767661fa
Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2971 { |
8f14767661fa
Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2972 z80_options *opts = context->options; |
8f14767661fa
Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2973 native_map_slot * native_code_map = opts->gen.native_code_map; |
8f14767661fa
Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2974 memmap_chunk const *mem_chunk = find_map_chunk(address, &opts->gen, 0, NULL); |
8f14767661fa
Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2975 if (mem_chunk) { |
8f14767661fa
Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2976 //calculate the lowest alias for this address |
8f14767661fa
Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2977 address = mem_chunk->start + ((address - mem_chunk->start) & mem_chunk->mask); |
8f14767661fa
Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2978 } |
8f14767661fa
Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2979 |
8f14767661fa
Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2980 uint32_t chunk = address / NATIVE_CHUNK_SIZE; |
8f14767661fa
Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2981 if (!native_code_map[chunk].base) { |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
2982 return INVALID_INSTRUCTION_START; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
2983 } |
1130
8f14767661fa
Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2984 uint32_t offset = address % NATIVE_CHUNK_SIZE; |
8f14767661fa
Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2985 if (native_code_map[chunk].offsets[offset] == INVALID_OFFSET) { |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
2986 return INVALID_INSTRUCTION_START; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
2987 } |
1130
8f14767661fa
Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2988 while (native_code_map[chunk].offsets[offset] == EXTENSION_WORD) |
8f14767661fa
Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2989 { |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
2990 --address; |
1130
8f14767661fa
Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2991 chunk = address / NATIVE_CHUNK_SIZE; |
8f14767661fa
Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2992 offset = address % NATIVE_CHUNK_SIZE; |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
2993 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
2994 return address; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
2995 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
2996 |
1224
15c5be05e6a9
Ported correct but inefficient overlapping instruction handling from 68K core to Z80 core. Fixed remaining stack alignment issue for Z80 breakpoints on 64-bit. Probably still needs fixing for 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
1222
diff
changeset
|
2997 //Technically unbounded due to redundant prefixes, but this is the max useful size |
15c5be05e6a9
Ported correct but inefficient overlapping instruction handling from 68K core to Z80 core. Fixed remaining stack alignment issue for Z80 breakpoints on 64-bit. Probably still needs fixing for 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
1222
diff
changeset
|
2998 #define Z80_MAX_INST_SIZE 4 |
15c5be05e6a9
Ported correct but inefficient overlapping instruction handling from 68K core to Z80 core. Fixed remaining stack alignment issue for Z80 breakpoints on 64-bit. Probably still needs fixing for 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
1222
diff
changeset
|
2999 |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
3000 z80_context * z80_handle_code_write(uint32_t address, z80_context * context) |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
3001 { |
1130
8f14767661fa
Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
3002 uint32_t inst_start = z80_get_instruction_start(context, address); |
1224
15c5be05e6a9
Ported correct but inefficient overlapping instruction handling from 68K core to Z80 core. Fixed remaining stack alignment issue for Z80 breakpoints on 64-bit. Probably still needs fixing for 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
1222
diff
changeset
|
3003 while (inst_start != INVALID_INSTRUCTION_START && (address - inst_start) < Z80_MAX_INST_SIZE) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
3004 code_ptr dst = z80_get_native_address(context, inst_start); |
899
07bfbbbb4b2e
Fix for Z80 retranslation post alignment rework
Michael Pavone <pavone@retrodev.com>
parents:
898
diff
changeset
|
3005 code_info code = {dst, dst+32, 0}; |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
3006 z80_options * opts = context->options; |
668
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3007 dprintf("patching code at %p for Z80 instruction at %X due to write to %X\n", code.cur, inst_start, address); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
3008 mov_ir(&code, inst_start, opts->gen.scratch1, SZ_D); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
3009 call(&code, opts->retrans_stub); |
1224
15c5be05e6a9
Ported correct but inefficient overlapping instruction handling from 68K core to Z80 core. Fixed remaining stack alignment issue for Z80 breakpoints on 64-bit. Probably still needs fixing for 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
1222
diff
changeset
|
3010 inst_start = z80_get_instruction_start(context, inst_start - 1); |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
3011 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
3012 return context; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
3013 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
3014 |
1142
5c8b1c33ca10
Invalidate translated code on a cartridge bank change in SMS mode. Fix handling of bank 0
Michael Pavone <pavone@retrodev.com>
parents:
1131
diff
changeset
|
3015 void z80_invalidate_code_range(z80_context *context, uint32_t start, uint32_t end) |
5c8b1c33ca10
Invalidate translated code on a cartridge bank change in SMS mode. Fix handling of bank 0
Michael Pavone <pavone@retrodev.com>
parents:
1131
diff
changeset
|
3016 { |
5c8b1c33ca10
Invalidate translated code on a cartridge bank change in SMS mode. Fix handling of bank 0
Michael Pavone <pavone@retrodev.com>
parents:
1131
diff
changeset
|
3017 z80_options *opts = context->options; |
5c8b1c33ca10
Invalidate translated code on a cartridge bank change in SMS mode. Fix handling of bank 0
Michael Pavone <pavone@retrodev.com>
parents:
1131
diff
changeset
|
3018 native_map_slot * native_code_map = opts->gen.native_code_map; |
5c8b1c33ca10
Invalidate translated code on a cartridge bank change in SMS mode. Fix handling of bank 0
Michael Pavone <pavone@retrodev.com>
parents:
1131
diff
changeset
|
3019 memmap_chunk const *mem_chunk = find_map_chunk(start, &opts->gen, 0, NULL); |
5c8b1c33ca10
Invalidate translated code on a cartridge bank change in SMS mode. Fix handling of bank 0
Michael Pavone <pavone@retrodev.com>
parents:
1131
diff
changeset
|
3020 if (mem_chunk) { |
5c8b1c33ca10
Invalidate translated code on a cartridge bank change in SMS mode. Fix handling of bank 0
Michael Pavone <pavone@retrodev.com>
parents:
1131
diff
changeset
|
3021 //calculate the lowest alias for this address |
5c8b1c33ca10
Invalidate translated code on a cartridge bank change in SMS mode. Fix handling of bank 0
Michael Pavone <pavone@retrodev.com>
parents:
1131
diff
changeset
|
3022 start = mem_chunk->start + ((start - mem_chunk->start) & mem_chunk->mask); |
5c8b1c33ca10
Invalidate translated code on a cartridge bank change in SMS mode. Fix handling of bank 0
Michael Pavone <pavone@retrodev.com>
parents:
1131
diff
changeset
|
3023 } |
5c8b1c33ca10
Invalidate translated code on a cartridge bank change in SMS mode. Fix handling of bank 0
Michael Pavone <pavone@retrodev.com>
parents:
1131
diff
changeset
|
3024 mem_chunk = find_map_chunk(end, &opts->gen, 0, NULL); |
5c8b1c33ca10
Invalidate translated code on a cartridge bank change in SMS mode. Fix handling of bank 0
Michael Pavone <pavone@retrodev.com>
parents:
1131
diff
changeset
|
3025 if (mem_chunk) { |
5c8b1c33ca10
Invalidate translated code on a cartridge bank change in SMS mode. Fix handling of bank 0
Michael Pavone <pavone@retrodev.com>
parents:
1131
diff
changeset
|
3026 //calculate the lowest alias for this address |
5c8b1c33ca10
Invalidate translated code on a cartridge bank change in SMS mode. Fix handling of bank 0
Michael Pavone <pavone@retrodev.com>
parents:
1131
diff
changeset
|
3027 end = mem_chunk->start + ((end - mem_chunk->start) & mem_chunk->mask); |
5c8b1c33ca10
Invalidate translated code on a cartridge bank change in SMS mode. Fix handling of bank 0
Michael Pavone <pavone@retrodev.com>
parents:
1131
diff
changeset
|
3028 } |
5c8b1c33ca10
Invalidate translated code on a cartridge bank change in SMS mode. Fix handling of bank 0
Michael Pavone <pavone@retrodev.com>
parents:
1131
diff
changeset
|
3029 uint32_t start_chunk = start / NATIVE_CHUNK_SIZE, end_chunk = end / NATIVE_CHUNK_SIZE; |
5c8b1c33ca10
Invalidate translated code on a cartridge bank change in SMS mode. Fix handling of bank 0
Michael Pavone <pavone@retrodev.com>
parents:
1131
diff
changeset
|
3030 for (uint32_t chunk = start_chunk; chunk <= end_chunk; chunk++) |
5c8b1c33ca10
Invalidate translated code on a cartridge bank change in SMS mode. Fix handling of bank 0
Michael Pavone <pavone@retrodev.com>
parents:
1131
diff
changeset
|
3031 { |
5c8b1c33ca10
Invalidate translated code on a cartridge bank change in SMS mode. Fix handling of bank 0
Michael Pavone <pavone@retrodev.com>
parents:
1131
diff
changeset
|
3032 if (native_code_map[chunk].base) { |
5c8b1c33ca10
Invalidate translated code on a cartridge bank change in SMS mode. Fix handling of bank 0
Michael Pavone <pavone@retrodev.com>
parents:
1131
diff
changeset
|
3033 uint32_t start_offset = chunk == start_chunk ? start % NATIVE_CHUNK_SIZE : 0; |
5c8b1c33ca10
Invalidate translated code on a cartridge bank change in SMS mode. Fix handling of bank 0
Michael Pavone <pavone@retrodev.com>
parents:
1131
diff
changeset
|
3034 uint32_t end_offset = chunk == end_chunk ? end % NATIVE_CHUNK_SIZE : NATIVE_CHUNK_SIZE; |
5c8b1c33ca10
Invalidate translated code on a cartridge bank change in SMS mode. Fix handling of bank 0
Michael Pavone <pavone@retrodev.com>
parents:
1131
diff
changeset
|
3035 for (uint32_t offset = start_offset; offset < end_offset; offset++) |
5c8b1c33ca10
Invalidate translated code on a cartridge bank change in SMS mode. Fix handling of bank 0
Michael Pavone <pavone@retrodev.com>
parents:
1131
diff
changeset
|
3036 { |
5c8b1c33ca10
Invalidate translated code on a cartridge bank change in SMS mode. Fix handling of bank 0
Michael Pavone <pavone@retrodev.com>
parents:
1131
diff
changeset
|
3037 if (native_code_map[chunk].offsets[offset] != INVALID_OFFSET && native_code_map[chunk].offsets[offset] != EXTENSION_WORD) { |
5c8b1c33ca10
Invalidate translated code on a cartridge bank change in SMS mode. Fix handling of bank 0
Michael Pavone <pavone@retrodev.com>
parents:
1131
diff
changeset
|
3038 code_info code; |
5c8b1c33ca10
Invalidate translated code on a cartridge bank change in SMS mode. Fix handling of bank 0
Michael Pavone <pavone@retrodev.com>
parents:
1131
diff
changeset
|
3039 code.cur = native_code_map[chunk].base + native_code_map[chunk].offsets[offset]; |
5c8b1c33ca10
Invalidate translated code on a cartridge bank change in SMS mode. Fix handling of bank 0
Michael Pavone <pavone@retrodev.com>
parents:
1131
diff
changeset
|
3040 code.last = code.cur + 32; |
5c8b1c33ca10
Invalidate translated code on a cartridge bank change in SMS mode. Fix handling of bank 0
Michael Pavone <pavone@retrodev.com>
parents:
1131
diff
changeset
|
3041 code.stack_off = 0; |
5c8b1c33ca10
Invalidate translated code on a cartridge bank change in SMS mode. Fix handling of bank 0
Michael Pavone <pavone@retrodev.com>
parents:
1131
diff
changeset
|
3042 mov_ir(&code, chunk * NATIVE_CHUNK_SIZE + offset, opts->gen.scratch1, SZ_D); |
5c8b1c33ca10
Invalidate translated code on a cartridge bank change in SMS mode. Fix handling of bank 0
Michael Pavone <pavone@retrodev.com>
parents:
1131
diff
changeset
|
3043 call(&code, opts->retrans_stub); |
5c8b1c33ca10
Invalidate translated code on a cartridge bank change in SMS mode. Fix handling of bank 0
Michael Pavone <pavone@retrodev.com>
parents:
1131
diff
changeset
|
3044 } |
5c8b1c33ca10
Invalidate translated code on a cartridge bank change in SMS mode. Fix handling of bank 0
Michael Pavone <pavone@retrodev.com>
parents:
1131
diff
changeset
|
3045 } |
5c8b1c33ca10
Invalidate translated code on a cartridge bank change in SMS mode. Fix handling of bank 0
Michael Pavone <pavone@retrodev.com>
parents:
1131
diff
changeset
|
3046 } |
5c8b1c33ca10
Invalidate translated code on a cartridge bank change in SMS mode. Fix handling of bank 0
Michael Pavone <pavone@retrodev.com>
parents:
1131
diff
changeset
|
3047 } |
5c8b1c33ca10
Invalidate translated code on a cartridge bank change in SMS mode. Fix handling of bank 0
Michael Pavone <pavone@retrodev.com>
parents:
1131
diff
changeset
|
3048 } |
5c8b1c33ca10
Invalidate translated code on a cartridge bank change in SMS mode. Fix handling of bank 0
Michael Pavone <pavone@retrodev.com>
parents:
1131
diff
changeset
|
3049 |
264
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
3050 uint8_t * z80_get_native_address_trans(z80_context * context, uint32_t address) |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
3051 { |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
3052 uint8_t * addr = z80_get_native_address(context, address); |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
3053 if (!addr) { |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
3054 translate_z80_stream(context, address); |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
3055 addr = z80_get_native_address(context, address); |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
3056 if (!addr) { |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
3057 printf("Failed to translate %X to native code\n", address); |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
3058 } |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
3059 } |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
3060 return addr; |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
3061 } |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
3062 |
266
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
3063 void z80_handle_deferred(z80_context * context) |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
3064 { |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3065 z80_options * opts = context->options; |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
3066 process_deferred(&opts->gen.deferred, context, (native_addr_func)z80_get_native_address); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
3067 if (opts->gen.deferred) { |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
3068 translate_z80_stream(context, opts->gen.deferred->address); |
266
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
3069 } |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
3070 } |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
3071 |
559
6b248602ab84
blastem builds and almost works on OS X now
Mike Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3072 extern void * z80_retranslate_inst(uint32_t address, z80_context * context, uint8_t * orig_start) asm("z80_retranslate_inst"); |
390
561fe3ea3fc8
Use a call instruction to figure out the original native address when retranslating so that it does not get lost when the byte transforms from a instruction word to extension word
Mike Pavone <pavone@retrodev.com>
parents:
389
diff
changeset
|
3073 void * z80_retranslate_inst(uint32_t address, z80_context * context, uint8_t * orig_start) |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
3074 { |
266
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
3075 char disbuf[80]; |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3076 z80_options * opts = context->options; |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
3077 uint8_t orig_size = z80_get_native_inst_size(opts, address); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
3078 code_info *code = &opts->gen.code; |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
3079 uint8_t *after, *inst = get_native_pointer(address, (void **)context->mem_pointers, &opts->gen); |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
3080 z80inst instbuf; |
268
6c2d7e003a55
Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents:
267
diff
changeset
|
3081 dprintf("Retranslating code at Z80 address %X, native address %p\n", address, orig_start); |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
3082 after = z80_decode(inst, &instbuf); |
268
6c2d7e003a55
Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents:
267
diff
changeset
|
3083 #ifdef DO_DEBUG_PRINT |
314
54c0e5f22198
Show absolute addresses for JR, JRCC and DJNZ in Z80 disassembler
Mike Pavone <pavone@retrodev.com>
parents:
313
diff
changeset
|
3084 z80_disasm(&instbuf, disbuf, address); |
266
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
3085 if (instbuf.op == Z80_NOP) { |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
3086 printf("%X\t%s(%d)\n", address, disbuf, instbuf.immed); |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
3087 } else { |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
3088 printf("%X\t%s\n", address, disbuf); |
267
1788e3f29c28
Don't mix *H regs with the REX prefix
Mike Pavone <pavone@retrodev.com>
parents:
266
diff
changeset
|
3089 } |
268
6c2d7e003a55
Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents:
267
diff
changeset
|
3090 #endif |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
3091 if (orig_size != ZMAX_NATIVE_SIZE) { |
597
8d6ae5b3b87b
Update code->cur before calling z80_get_address_trans in z80_retranslate_inst to avoid any newly translated instructions from being placed in the "buffer zone". Save the current value of the code_info struct for placing the final jmp instruction in the correct place
Michael Pavone <pavone@retrodev.com>
parents:
594
diff
changeset
|
3092 check_alloc_code(code, ZMAX_NATIVE_SIZE); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
3093 code_ptr start = code->cur; |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
3094 deferred_addr * orig_deferred = opts->gen.deferred; |
652 | 3095 translate_z80inst(&instbuf, context, address, 0); |
644
2d7e84ae818c
Temporarily comment out code to translate Z80 instructions in place as in rare cases it can stomp the next instruction if a branch goes from a short from to a long one
Michael Pavone <pavone@retrodev.com>
parents:
628
diff
changeset
|
3096 /* |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
3097 if ((native_end - dst) <= orig_size) { |
264
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
3098 uint8_t * native_next = z80_get_native_address(context, address + after-inst); |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
3099 if (native_next && ((native_next == orig_start + orig_size) || (orig_size - (native_end - dst)) > 5)) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
3100 remove_deferred_until(&opts->gen.deferred, orig_deferred); |
627
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
3101 native_end = translate_z80inst(&instbuf, orig_start, context, address, 0); |
266
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
3102 if (native_next == orig_start + orig_size && (native_next-native_end) < 2) { |
264
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
3103 while (native_end < orig_start + orig_size) { |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
3104 *(native_end++) = 0x90; //NOP |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
3105 } |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
3106 } else { |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
3107 jmp(native_end, native_next); |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
3108 } |
266
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
3109 z80_handle_deferred(context); |
264
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
3110 return orig_start; |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
3111 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
3112 }*/ |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
3113 z80_map_native_address(context, address, start, after-inst, ZMAX_NATIVE_SIZE); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
3114 code_info tmp_code = {orig_start, orig_start + 16}; |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
3115 jmp(&tmp_code, start); |
597
8d6ae5b3b87b
Update code->cur before calling z80_get_address_trans in z80_retranslate_inst to avoid any newly translated instructions from being placed in the "buffer zone". Save the current value of the code_info struct for placing the final jmp instruction in the correct place
Michael Pavone <pavone@retrodev.com>
parents:
594
diff
changeset
|
3116 tmp_code = *code; |
8d6ae5b3b87b
Update code->cur before calling z80_get_address_trans in z80_retranslate_inst to avoid any newly translated instructions from being placed in the "buffer zone". Save the current value of the code_info struct for placing the final jmp instruction in the correct place
Michael Pavone <pavone@retrodev.com>
parents:
594
diff
changeset
|
3117 code->cur = start + ZMAX_NATIVE_SIZE; |
283
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
3118 if (!z80_is_terminal(&instbuf)) { |
597
8d6ae5b3b87b
Update code->cur before calling z80_get_address_trans in z80_retranslate_inst to avoid any newly translated instructions from being placed in the "buffer zone". Save the current value of the code_info struct for placing the final jmp instruction in the correct place
Michael Pavone <pavone@retrodev.com>
parents:
594
diff
changeset
|
3119 jmp(&tmp_code, z80_get_native_address_trans(context, address + after-inst)); |
264
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
3120 } |
266
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
3121 z80_handle_deferred(context); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
3122 return start; |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
3123 } else { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
3124 code_info tmp_code = *code; |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
3125 code->cur = orig_start; |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
3126 code->last = orig_start + ZMAX_NATIVE_SIZE; |
652 | 3127 translate_z80inst(&instbuf, context, address, 0); |
601
f0061e3d2ad9
Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor
Michael Pavone <pavone@retrodev.com>
parents:
598
diff
changeset
|
3128 code_info tmp2 = *code; |
f0061e3d2ad9
Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor
Michael Pavone <pavone@retrodev.com>
parents:
598
diff
changeset
|
3129 *code = tmp_code; |
283
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
3130 if (!z80_is_terminal(&instbuf)) { |
652 | 3131 |
601
f0061e3d2ad9
Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor
Michael Pavone <pavone@retrodev.com>
parents:
598
diff
changeset
|
3132 jmp(&tmp2, z80_get_native_address_trans(context, address + after-inst)); |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
3133 } |
266
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
3134 z80_handle_deferred(context); |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
3135 return orig_start; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
3136 } |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
3137 } |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
3138 |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
3139 void translate_z80_stream(z80_context * context, uint32_t address) |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
3140 { |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
3141 char disbuf[80]; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
3142 if (z80_get_native_address(context, address)) { |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
3143 return; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
3144 } |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3145 z80_options * opts = context->options; |
505
b7b7a1cab44a
The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
3146 uint32_t start_address = address; |
627
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
3147 |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
3148 do |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
3149 { |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
3150 z80inst inst; |
268
6c2d7e003a55
Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents:
267
diff
changeset
|
3151 dprintf("translating Z80 code at address %X\n", address); |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
3152 do { |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
3153 uint8_t * existing = z80_get_native_address(context, address); |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
3154 if (existing) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
3155 jmp(&opts->gen.code, existing); |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
3156 break; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
3157 } |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
3158 uint8_t * encoded, *next; |
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
3159 encoded = get_native_pointer(address, (void **)context->mem_pointers, &opts->gen); |
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
3160 if (!encoded) { |
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
3161 code_info stub = z80_make_interp_stub(context, address); |
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
3162 z80_map_native_address(context, address, stub.cur, 1, stub.last - stub.cur); |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
3163 break; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
3164 } |
601
f0061e3d2ad9
Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor
Michael Pavone <pavone@retrodev.com>
parents:
598
diff
changeset
|
3165 //make sure prologue is in a contiguous chunk of code |
f0061e3d2ad9
Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor
Michael Pavone <pavone@retrodev.com>
parents:
598
diff
changeset
|
3166 check_code_prologue(&opts->gen.code); |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
3167 next = z80_decode(encoded, &inst); |
268
6c2d7e003a55
Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents:
267
diff
changeset
|
3168 #ifdef DO_DEBUG_PRINT |
314
54c0e5f22198
Show absolute addresses for JR, JRCC and DJNZ in Z80 disassembler
Mike Pavone <pavone@retrodev.com>
parents:
313
diff
changeset
|
3169 z80_disasm(&inst, disbuf, address); |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
3170 if (inst.op == Z80_NOP) { |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
3171 printf("%X\t%s(%d)\n", address, disbuf, inst.immed); |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
3172 } else { |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
3173 printf("%X\t%s\n", address, disbuf); |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
3174 } |
268
6c2d7e003a55
Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents:
267
diff
changeset
|
3175 #endif |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
3176 code_ptr start = opts->gen.code.cur; |
652 | 3177 translate_z80inst(&inst, context, address, 0); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
3178 z80_map_native_address(context, address, start, next-encoded, opts->gen.code.cur - start); |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
3179 address += next-encoded; |
255
572b935dd030
Properly handle wrapping around to 0 in translate_z80_stream
Mike Pavone <pavone@retrodev.com>
parents:
254
diff
changeset
|
3180 address &= 0xFFFF; |
283
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
3181 } while (!z80_is_terminal(&inst)); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
3182 process_deferred(&opts->gen.deferred, context, (native_addr_func)z80_get_native_address); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
3183 if (opts->gen.deferred) { |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
3184 address = opts->gen.deferred->address; |
268
6c2d7e003a55
Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents:
267
diff
changeset
|
3185 dprintf("defferred address: %X\n", address); |
792
724bbec47f86
Use a new fatal_error function instead of calling fprintf and exit for fatal errors. This new function more gracefully handles the case in which BlastEm was not started from a terminal or disconnected from ther terminal (Windows).
Michael Pavone <pavone@retrodev.com>
parents:
755
diff
changeset
|
3186 } |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
3187 } while (opts->gen.deferred); |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3188 } |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3189 |
1116
fe8c79f82c22
More cleanup in preparation for SMS/Mark III support
Michael Pavone <pavone@retrodev.com>
parents:
1110
diff
changeset
|
3190 void init_z80_opts(z80_options * options, memmap_chunk const * chunks, uint32_t num_chunks, memmap_chunk const * io_chunks, uint32_t num_io_chunks, uint32_t clock_divider, uint32_t io_address_mask) |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3191 { |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3192 memset(options, 0, sizeof(*options)); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3193 |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
3194 options->gen.memmap = chunks; |
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
3195 options->gen.memmap_chunks = num_chunks; |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3196 options->gen.address_size = SZ_W; |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3197 options->gen.address_mask = 0xFFFF; |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3198 options->gen.max_address = 0x10000; |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3199 options->gen.bus_cycles = 3; |
667
30ccf56842d6
All cycle counters are now based off the master clock. This seems to have messed up Z80 interrupt timing (music in Sonic 2 is too slow for instance), but things are generally working
Michael Pavone <pavone@retrodev.com>
parents:
666
diff
changeset
|
3200 options->gen.clock_divider = clock_divider; |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3201 options->gen.mem_ptr_off = offsetof(z80_context, mem_pointers); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3202 options->gen.ram_flags_off = offsetof(z80_context, ram_code_flags); |
620
9d6fed6501ba
Fix handling of code writes for Z80 core. This seems to get things close to being back to where they were before the big refactor that broke the Z80 core. Some problems remain. Notably the sound driver in Sonic 2 is still quite broken.
Michael Pavone <pavone@retrodev.com>
parents:
601
diff
changeset
|
3203 options->gen.ram_flags_shift = 7; |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3204 |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
3205 options->flags = 0; |
666
b68039895627
In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed
Michael Pavone <pavone@retrodev.com>
parents:
665
diff
changeset
|
3206 #ifdef X86_64 |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
3207 options->regs[Z80_B] = BH; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
3208 options->regs[Z80_C] = RBX; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
3209 options->regs[Z80_D] = CH; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
3210 options->regs[Z80_E] = RCX; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
3211 options->regs[Z80_H] = AH; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
3212 options->regs[Z80_L] = RAX; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
3213 options->regs[Z80_IXH] = DH; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
3214 options->regs[Z80_IXL] = RDX; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
3215 options->regs[Z80_IYH] = -1; |
239
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
3216 options->regs[Z80_IYL] = R8; |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
3217 options->regs[Z80_I] = -1; |
1047
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
3218 options->regs[Z80_R] = RDI; |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
3219 options->regs[Z80_A] = R10; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
3220 options->regs[Z80_BC] = RBX; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
3221 options->regs[Z80_DE] = RCX; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
3222 options->regs[Z80_HL] = RAX; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
3223 options->regs[Z80_SP] = R9; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
3224 options->regs[Z80_AF] = -1; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
3225 options->regs[Z80_IX] = RDX; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
3226 options->regs[Z80_IY] = R8; |
667
30ccf56842d6
All cycle counters are now based off the master clock. This seems to have messed up Z80 interrupt timing (music in Sonic 2 is too slow for instance), but things are generally working
Michael Pavone <pavone@retrodev.com>
parents:
666
diff
changeset
|
3227 |
666
b68039895627
In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed
Michael Pavone <pavone@retrodev.com>
parents:
665
diff
changeset
|
3228 options->gen.scratch1 = R13; |
b68039895627
In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed
Michael Pavone <pavone@retrodev.com>
parents:
665
diff
changeset
|
3229 options->gen.scratch2 = R14; |
b68039895627
In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed
Michael Pavone <pavone@retrodev.com>
parents:
665
diff
changeset
|
3230 #else |
b68039895627
In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed
Michael Pavone <pavone@retrodev.com>
parents:
665
diff
changeset
|
3231 memset(options->regs, -1, sizeof(options->regs)); |
b68039895627
In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed
Michael Pavone <pavone@retrodev.com>
parents:
665
diff
changeset
|
3232 options->regs[Z80_A] = RAX; |
1047
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
3233 options->regs[Z80_R] = AH; |
1048
05ecef6c73b6
More efficient register usage in 32-bit mode
Michael Pavone <pavone@retrodev.com>
parents:
1047
diff
changeset
|
3234 options->regs[Z80_H] = BH; |
05ecef6c73b6
More efficient register usage in 32-bit mode
Michael Pavone <pavone@retrodev.com>
parents:
1047
diff
changeset
|
3235 options->regs[Z80_L] = RBX; |
05ecef6c73b6
More efficient register usage in 32-bit mode
Michael Pavone <pavone@retrodev.com>
parents:
1047
diff
changeset
|
3236 options->regs[Z80_HL] = RBX; |
05ecef6c73b6
More efficient register usage in 32-bit mode
Michael Pavone <pavone@retrodev.com>
parents:
1047
diff
changeset
|
3237 |
05ecef6c73b6
More efficient register usage in 32-bit mode
Michael Pavone <pavone@retrodev.com>
parents:
1047
diff
changeset
|
3238 options->regs[Z80_SP] = RDI; |
667
30ccf56842d6
All cycle counters are now based off the master clock. This seems to have messed up Z80 interrupt timing (music in Sonic 2 is too slow for instance), but things are generally working
Michael Pavone <pavone@retrodev.com>
parents:
666
diff
changeset
|
3239 |
666
b68039895627
In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed
Michael Pavone <pavone@retrodev.com>
parents:
665
diff
changeset
|
3240 options->gen.scratch1 = RCX; |
b68039895627
In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed
Michael Pavone <pavone@retrodev.com>
parents:
665
diff
changeset
|
3241 options->gen.scratch2 = RDX; |
b68039895627
In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed
Michael Pavone <pavone@retrodev.com>
parents:
665
diff
changeset
|
3242 #endif |
667
30ccf56842d6
All cycle counters are now based off the master clock. This seems to have messed up Z80 interrupt timing (music in Sonic 2 is too slow for instance), but things are generally working
Michael Pavone <pavone@retrodev.com>
parents:
666
diff
changeset
|
3243 |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3244 options->gen.context_reg = RSI; |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3245 options->gen.cycles = RBP; |
1047
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
3246 options->gen.limit = -1; |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3247 |
1130
8f14767661fa
Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
3248 options->gen.native_code_map = malloc(sizeof(native_map_slot) * NATIVE_MAP_CHUNKS); |
8f14767661fa
Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
3249 memset(options->gen.native_code_map, 0, sizeof(native_map_slot) * NATIVE_MAP_CHUNKS); |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3250 options->gen.deferred = NULL; |
1130
8f14767661fa
Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
3251 uint32_t inst_size_size = sizeof(uint8_t *) * ram_size(&options->gen) / 1024; |
8f14767661fa
Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
3252 options->gen.ram_inst_sizes = malloc(inst_size_size); |
8f14767661fa
Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
3253 memset(options->gen.ram_inst_sizes, 0, inst_size_size); |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3254 |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3255 code_info *code = &options->gen.code; |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3256 init_code_info(code); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3257 |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3258 options->save_context_scratch = code->cur; |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3259 mov_rrdisp(code, options->gen.scratch1, options->gen.context_reg, offsetof(z80_context, scratch1), SZ_W); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3260 mov_rrdisp(code, options->gen.scratch2, options->gen.context_reg, offsetof(z80_context, scratch2), SZ_W); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3261 |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3262 options->gen.save_context = code->cur; |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3263 for (int i = 0; i <= Z80_A; i++) |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3264 { |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3265 int reg; |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3266 uint8_t size; |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3267 if (i < Z80_I) { |
594
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3268 reg = i /2 + Z80_BC + (i > Z80_H ? 2 : 0); |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3269 size = SZ_W; |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3270 } else { |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3271 reg = i; |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3272 size = SZ_B; |
1047
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
3273 } |
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
3274 if (reg == Z80_R) { |
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
3275 and_ir(code, 0x7F, options->regs[Z80_R], SZ_B); |
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
3276 or_rrdisp(code, options->regs[Z80_R], options->gen.context_reg, zr_off(Z80_R), SZ_B); |
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
3277 } else if (options->regs[reg] >= 0) { |
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
3278 mov_rrdisp(code, options->regs[reg], options->gen.context_reg, zr_off(reg), size); |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3279 } |
594
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3280 if (size == SZ_W) { |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3281 i++; |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3282 } |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3283 } |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3284 if (options->regs[Z80_SP] >= 0) { |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3285 mov_rrdisp(code, options->regs[Z80_SP], options->gen.context_reg, offsetof(z80_context, sp), SZ_W); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3286 } |
1047
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
3287 neg_r(code, options->gen.cycles, SZ_D); |
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
3288 add_rdispr(code, options->gen.context_reg, offsetof(z80_context, target_cycle), options->gen.cycles, SZ_D); |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3289 mov_rrdisp(code, options->gen.cycles, options->gen.context_reg, offsetof(z80_context, current_cycle), SZ_D); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
3290 retn(code); |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3291 |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3292 options->load_context_scratch = code->cur; |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3293 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, scratch1), options->gen.scratch1, SZ_W); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3294 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, scratch2), options->gen.scratch2, SZ_W); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3295 options->gen.load_context = code->cur; |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3296 for (int i = 0; i <= Z80_A; i++) |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3297 { |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3298 int reg; |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3299 uint8_t size; |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3300 if (i < Z80_I) { |
594
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3301 reg = i /2 + Z80_BC + (i > Z80_H ? 2 : 0); |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3302 size = SZ_W; |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3303 } else { |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3304 reg = i; |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3305 size = SZ_B; |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3306 } |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3307 if (options->regs[reg] >= 0) { |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3308 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, regs) + i, options->regs[reg], size); |
1225
197cb199a35b
Fix loading of the R register from the in memory context
Michael Pavone <pavone@retrodev.com>
parents:
1224
diff
changeset
|
3309 if (reg == Z80_R) { |
197cb199a35b
Fix loading of the R register from the in memory context
Michael Pavone <pavone@retrodev.com>
parents:
1224
diff
changeset
|
3310 and_irdisp(code, 0x80, options->gen.context_reg, zr_off(reg), SZ_B); |
197cb199a35b
Fix loading of the R register from the in memory context
Michael Pavone <pavone@retrodev.com>
parents:
1224
diff
changeset
|
3311 } |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3312 } |
594
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3313 if (size == SZ_W) { |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3314 i++; |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3315 } |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3316 } |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3317 if (options->regs[Z80_SP] >= 0) { |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3318 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, sp), options->regs[Z80_SP], SZ_W); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3319 } |
1047
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
3320 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, target_cycle), options->gen.cycles, SZ_D); |
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
3321 sub_rdispr(code, options->gen.context_reg, offsetof(z80_context, current_cycle), options->gen.cycles, SZ_D); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
3322 retn(code); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
3323 |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
3324 options->native_addr = code->cur; |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
3325 call(code, options->gen.save_context); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
3326 push_r(code, options->gen.context_reg); |
657
92ce5ea5ffc9
Use call_args and call_args_abi in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
653
diff
changeset
|
3327 movzx_rr(code, options->gen.scratch1, options->gen.scratch1, SZ_W, SZ_D); |
92ce5ea5ffc9
Use call_args and call_args_abi in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
653
diff
changeset
|
3328 call_args(code, (code_ptr)z80_get_native_address_trans, 2, options->gen.context_reg, options->gen.scratch1); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
3329 mov_rr(code, RAX, options->gen.scratch1, SZ_PTR); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
3330 pop_r(code, options->gen.context_reg); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
3331 call(code, options->gen.load_context); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
3332 retn(code); |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3333 |
895
13388ab6d78a
Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
3334 uint32_t tmp_stack_off; |
13388ab6d78a
Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
3335 |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3336 options->gen.handle_cycle_limit = code->cur; |
900
30efd12b1be1
Replace some hard-coded instruction length assumptions with a calculation so they will work properly on both 32-bit and 64-bit hosts
Michael Pavone <pavone@retrodev.com>
parents:
899
diff
changeset
|
3337 //calculate call/stack adjust size |
30efd12b1be1
Replace some hard-coded instruction length assumptions with a calculation so they will work properly on both 32-bit and 64-bit hosts
Michael Pavone <pavone@retrodev.com>
parents:
899
diff
changeset
|
3338 sub_ir(code, 16-sizeof(void *), RSP, SZ_PTR); |
30efd12b1be1
Replace some hard-coded instruction length assumptions with a calculation so they will work properly on both 32-bit and 64-bit hosts
Michael Pavone <pavone@retrodev.com>
parents:
899
diff
changeset
|
3339 call_noalign(code, options->gen.handle_cycle_limit); |
30efd12b1be1
Replace some hard-coded instruction length assumptions with a calculation so they will work properly on both 32-bit and 64-bit hosts
Michael Pavone <pavone@retrodev.com>
parents:
899
diff
changeset
|
3340 uint32_t call_adjust_size = code->cur - options->gen.handle_cycle_limit; |
30efd12b1be1
Replace some hard-coded instruction length assumptions with a calculation so they will work properly on both 32-bit and 64-bit hosts
Michael Pavone <pavone@retrodev.com>
parents:
899
diff
changeset
|
3341 code->cur = options->gen.handle_cycle_limit; |
30efd12b1be1
Replace some hard-coded instruction length assumptions with a calculation so they will work properly on both 32-bit and 64-bit hosts
Michael Pavone <pavone@retrodev.com>
parents:
899
diff
changeset
|
3342 |
1047
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
3343 neg_r(code, options->gen.cycles, SZ_D); |
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
3344 add_rdispr(code, options->gen.context_reg, offsetof(z80_context, target_cycle), options->gen.cycles, SZ_D); |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3345 cmp_rdispr(code, options->gen.context_reg, offsetof(z80_context, sync_cycle), options->gen.cycles, SZ_D); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3346 code_ptr no_sync = code->cur+1; |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3347 jcc(code, CC_B, no_sync); |
1047
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
3348 neg_r(code, options->gen.cycles, SZ_D); |
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
3349 add_rdispr(code, options->gen.context_reg, offsetof(z80_context, target_cycle), options->gen.cycles, SZ_D); |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3350 mov_irdisp(code, 0, options->gen.context_reg, offsetof(z80_context, pc), SZ_W); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3351 call(code, options->save_context_scratch); |
895
13388ab6d78a
Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
3352 tmp_stack_off = code->stack_off; |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3353 pop_r(code, RAX); //return address in read/write func |
895
13388ab6d78a
Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
3354 add_ir(code, 16-sizeof(void *), RSP, SZ_PTR); |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3355 pop_r(code, RBX); //return address in translated code |
895
13388ab6d78a
Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
3356 add_ir(code, 16-sizeof(void *), RSP, SZ_PTR); |
900
30efd12b1be1
Replace some hard-coded instruction length assumptions with a calculation so they will work properly on both 32-bit and 64-bit hosts
Michael Pavone <pavone@retrodev.com>
parents:
899
diff
changeset
|
3357 sub_ir(code, call_adjust_size, RAX, SZ_PTR); //adjust return address to point to the call + stack adjust that got us here |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3358 mov_rrdisp(code, RBX, options->gen.context_reg, offsetof(z80_context, extra_pc), SZ_PTR); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3359 mov_rrind(code, RAX, options->gen.context_reg, SZ_PTR); |
665
d0943769353b
Added functions to gen_x86 for saving and restoring callee save registers to better abstract over ABI differences between x86 and x86-64
Michael Pavone <pavone@retrodev.com>
parents:
664
diff
changeset
|
3360 restore_callee_save_regs(code); |
1047
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
3361 //return to caller of z80_run |
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
3362 retn(code); |
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
3363 |
598
faad1927d836
Fix an off-by-one error in a branch destination in the generation of handle_cycle_limit for the Z80
Michael Pavone <pavone@retrodev.com>
parents:
597
diff
changeset
|
3364 *no_sync = code->cur - (no_sync + 1); |
1047
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
3365 neg_r(code, options->gen.cycles, SZ_D); |
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
3366 add_rdispr(code, options->gen.context_reg, offsetof(z80_context, target_cycle), options->gen.cycles, SZ_D); |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3367 retn(code); |
895
13388ab6d78a
Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
3368 code->stack_off = tmp_stack_off; |
652 | 3369 |
594
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3370 options->gen.handle_code_write = (code_ptr)z80_handle_code_write; |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3371 |
594
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3372 options->read_8 = gen_mem_fun(&options->gen, chunks, num_chunks, READ_8, &options->read_8_noinc); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
3373 options->write_8 = gen_mem_fun(&options->gen, chunks, num_chunks, WRITE_8, &options->write_8_noinc); |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3374 |
895
13388ab6d78a
Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
3375 code_ptr skip_int = code->cur; |
900
30efd12b1be1
Replace some hard-coded instruction length assumptions with a calculation so they will work properly on both 32-bit and 64-bit hosts
Michael Pavone <pavone@retrodev.com>
parents:
899
diff
changeset
|
3376 //calculate adjust size |
30efd12b1be1
Replace some hard-coded instruction length assumptions with a calculation so they will work properly on both 32-bit and 64-bit hosts
Michael Pavone <pavone@retrodev.com>
parents:
899
diff
changeset
|
3377 add_ir(code, 16-sizeof(void *), RSP, SZ_PTR); |
30efd12b1be1
Replace some hard-coded instruction length assumptions with a calculation so they will work properly on both 32-bit and 64-bit hosts
Michael Pavone <pavone@retrodev.com>
parents:
899
diff
changeset
|
3378 uint32_t adjust_size = code->cur - skip_int; |
30efd12b1be1
Replace some hard-coded instruction length assumptions with a calculation so they will work properly on both 32-bit and 64-bit hosts
Michael Pavone <pavone@retrodev.com>
parents:
899
diff
changeset
|
3379 code->cur = skip_int; |
30efd12b1be1
Replace some hard-coded instruction length assumptions with a calculation so they will work properly on both 32-bit and 64-bit hosts
Michael Pavone <pavone@retrodev.com>
parents:
899
diff
changeset
|
3380 |
895
13388ab6d78a
Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
3381 cmp_rdispr(code, options->gen.context_reg, offsetof(z80_context, sync_cycle), options->gen.cycles, SZ_D); |
13388ab6d78a
Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
3382 code_ptr skip_sync = code->cur + 1; |
13388ab6d78a
Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
3383 jcc(code, CC_B, skip_sync); |
1047
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
3384 neg_r(code, options->gen.cycles, SZ_D); |
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
3385 add_rdispr(code, options->gen.context_reg, offsetof(z80_context, target_cycle), options->gen.cycles, SZ_D); |
895
13388ab6d78a
Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
3386 //save PC |
13388ab6d78a
Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
3387 mov_rrdisp(code, options->gen.scratch1, options->gen.context_reg, offsetof(z80_context, pc), SZ_D); |
13388ab6d78a
Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
3388 options->do_sync = code->cur; |
13388ab6d78a
Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
3389 call(code, options->gen.save_context); |
13388ab6d78a
Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
3390 tmp_stack_off = code->stack_off; |
13388ab6d78a
Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
3391 //pop return address off the stack and save for resume later |
898
2f1157f00dc6
Z80 core is now slightly less broken
Michael Pavone <pavone@retrodev.com>
parents:
895
diff
changeset
|
3392 //pop_rind(code, options->gen.context_reg); |
2f1157f00dc6
Z80 core is now slightly less broken
Michael Pavone <pavone@retrodev.com>
parents:
895
diff
changeset
|
3393 pop_r(code, RAX); |
900
30efd12b1be1
Replace some hard-coded instruction length assumptions with a calculation so they will work properly on both 32-bit and 64-bit hosts
Michael Pavone <pavone@retrodev.com>
parents:
899
diff
changeset
|
3394 add_ir(code, adjust_size, RAX, SZ_PTR); |
895
13388ab6d78a
Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
3395 add_ir(code, 16-sizeof(void *), RSP, SZ_PTR); |
898
2f1157f00dc6
Z80 core is now slightly less broken
Michael Pavone <pavone@retrodev.com>
parents:
895
diff
changeset
|
3396 mov_rrind(code, RAX, options->gen.context_reg, SZ_PTR); |
2f1157f00dc6
Z80 core is now slightly less broken
Michael Pavone <pavone@retrodev.com>
parents:
895
diff
changeset
|
3397 |
895
13388ab6d78a
Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
3398 //restore callee saved registers |
13388ab6d78a
Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
3399 restore_callee_save_regs(code); |
13388ab6d78a
Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
3400 //return to caller of z80_run |
1047
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
3401 retn(code); |
895
13388ab6d78a
Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
3402 *skip_sync = code->cur - (skip_sync+1); |
1047
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
3403 neg_r(code, options->gen.cycles, SZ_D); |
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
3404 add_rdispr(code, options->gen.context_reg, offsetof(z80_context, target_cycle), options->gen.cycles, SZ_D); |
895
13388ab6d78a
Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
3405 retn(code); |
13388ab6d78a
Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
3406 code->stack_off = tmp_stack_off; |
13388ab6d78a
Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
3407 |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3408 options->gen.handle_cycle_limit_int = code->cur; |
1047
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
3409 neg_r(code, options->gen.cycles, SZ_D); |
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
3410 add_rdispr(code, options->gen.context_reg, offsetof(z80_context, target_cycle), options->gen.cycles, SZ_D); |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3411 cmp_rdispr(code, options->gen.context_reg, offsetof(z80_context, int_cycle), options->gen.cycles, SZ_D); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3412 jcc(code, CC_B, skip_int); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3413 //set limit to the cycle limit |
1047
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
3414 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, sync_cycle), options->gen.scratch2, SZ_D); |
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
3415 mov_rrdisp(code, options->gen.scratch2, options->gen.context_reg, offsetof(z80_context, target_cycle), SZ_D); |
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
3416 neg_r(code, options->gen.cycles, SZ_D); |
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
3417 add_rr(code, options->gen.scratch2, options->gen.cycles, SZ_D); |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3418 //disable interrupts |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
3419 mov_irdisp(code, 0, options->gen.context_reg, offsetof(z80_context, iff1), SZ_B); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
3420 mov_irdisp(code, 0, options->gen.context_reg, offsetof(z80_context, iff2), SZ_B); |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3421 cycles(&options->gen, 7); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3422 //save return address (in scratch1) to Z80 stack |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3423 sub_ir(code, 2, options->regs[Z80_SP], SZ_W); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3424 mov_rr(code, options->regs[Z80_SP], options->gen.scratch2, SZ_W); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3425 //we need to do check_cycles and cycles outside of the write_8 call |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3426 //so that the stack has the correct depth if we need to return to C |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3427 //for a synchronization |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3428 check_cycles(&options->gen); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3429 cycles(&options->gen, 3); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3430 //save word to write before call to write_8_noinc |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3431 push_r(code, options->gen.scratch1); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3432 call(code, options->write_8_noinc); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3433 //restore word to write |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3434 pop_r(code, options->gen.scratch1); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3435 //write high byte to SP+1 |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3436 mov_rr(code, options->regs[Z80_SP], options->gen.scratch2, SZ_W); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3437 add_ir(code, 1, options->gen.scratch2, SZ_W); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3438 shr_ir(code, 8, options->gen.scratch1, SZ_W); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3439 check_cycles(&options->gen); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3440 cycles(&options->gen, 3); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3441 call(code, options->write_8_noinc); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3442 //dispose of return address as we'll be jumping somewhere else |
895
13388ab6d78a
Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
3443 add_ir(code, 16, RSP, SZ_PTR); |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3444 //TODO: Support interrupt mode 0 and 2 |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3445 mov_ir(code, 0x38, options->gen.scratch1, SZ_W); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
3446 call(code, options->native_addr); |
663
7a5461001242
Sync Z80 when taking an interrupt so that int_cycle gets updated
Michael Pavone <pavone@retrodev.com>
parents:
662
diff
changeset
|
3447 mov_rrind(code, options->gen.scratch1, options->gen.context_reg, SZ_PTR); |
895
13388ab6d78a
Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
3448 tmp_stack_off = code->stack_off; |
665
d0943769353b
Added functions to gen_x86 for saving and restoring callee save registers to better abstract over ABI differences between x86 and x86-64
Michael Pavone <pavone@retrodev.com>
parents:
664
diff
changeset
|
3449 restore_callee_save_regs(code); |
663
7a5461001242
Sync Z80 when taking an interrupt so that int_cycle gets updated
Michael Pavone <pavone@retrodev.com>
parents:
662
diff
changeset
|
3450 //return to caller of z80_run to sync |
7a5461001242
Sync Z80 when taking an interrupt so that int_cycle gets updated
Michael Pavone <pavone@retrodev.com>
parents:
662
diff
changeset
|
3451 retn(code); |
895
13388ab6d78a
Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
3452 code->stack_off = tmp_stack_off; |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
3453 |
819
ab017fb09e77
Added support for an IO memory map in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
792
diff
changeset
|
3454 //HACK |
ab017fb09e77
Added support for an IO memory map in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
792
diff
changeset
|
3455 options->gen.address_size = SZ_D; |
1116
fe8c79f82c22
More cleanup in preparation for SMS/Mark III support
Michael Pavone <pavone@retrodev.com>
parents:
1110
diff
changeset
|
3456 options->gen.address_mask = io_address_mask; |
819
ab017fb09e77
Added support for an IO memory map in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
792
diff
changeset
|
3457 options->read_io = gen_mem_fun(&options->gen, io_chunks, num_io_chunks, READ_8, NULL); |
ab017fb09e77
Added support for an IO memory map in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
792
diff
changeset
|
3458 options->write_io = gen_mem_fun(&options->gen, io_chunks, num_io_chunks, WRITE_8, NULL); |
ab017fb09e77
Added support for an IO memory map in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
792
diff
changeset
|
3459 options->gen.address_size = SZ_W; |
ab017fb09e77
Added support for an IO memory map in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
792
diff
changeset
|
3460 options->gen.address_mask = 0xFFFF; |
652 | 3461 |
594
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3462 options->read_16 = code->cur; |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3463 cycles(&options->gen, 3); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3464 check_cycles(&options->gen); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3465 //TODO: figure out how to handle the extra wait state for word reads to bank area |
657
92ce5ea5ffc9
Use call_args and call_args_abi in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
653
diff
changeset
|
3466 //may also need special handling to avoid too much stack depth when access is blocked |
594
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3467 push_r(code, options->gen.scratch1); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3468 call(code, options->read_8_noinc); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3469 mov_rr(code, options->gen.scratch1, options->gen.scratch2, SZ_B); |
735
539d12fa6a4d
Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function.
Michael Pavone <pavone@retrodev.com>
parents:
734
diff
changeset
|
3470 #ifndef X86_64 |
539d12fa6a4d
Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function.
Michael Pavone <pavone@retrodev.com>
parents:
734
diff
changeset
|
3471 //scratch 2 is a caller save register in 32-bit builds and may be clobbered by something called from the read8 fun |
539d12fa6a4d
Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function.
Michael Pavone <pavone@retrodev.com>
parents:
734
diff
changeset
|
3472 mov_rrdisp(code, options->gen.scratch1, options->gen.context_reg, offsetof(z80_context, scratch2), SZ_B); |
539d12fa6a4d
Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function.
Michael Pavone <pavone@retrodev.com>
parents:
734
diff
changeset
|
3473 #endif |
594
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3474 pop_r(code, options->gen.scratch1); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3475 add_ir(code, 1, options->gen.scratch1, SZ_W); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3476 cycles(&options->gen, 3); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3477 check_cycles(&options->gen); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3478 call(code, options->read_8_noinc); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3479 shl_ir(code, 8, options->gen.scratch1, SZ_W); |
735
539d12fa6a4d
Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function.
Michael Pavone <pavone@retrodev.com>
parents:
734
diff
changeset
|
3480 #ifdef X86_64 |
594
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3481 mov_rr(code, options->gen.scratch2, options->gen.scratch1, SZ_B); |
735
539d12fa6a4d
Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function.
Michael Pavone <pavone@retrodev.com>
parents:
734
diff
changeset
|
3482 #else |
539d12fa6a4d
Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function.
Michael Pavone <pavone@retrodev.com>
parents:
734
diff
changeset
|
3483 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, scratch2), options->gen.scratch1, SZ_B); |
539d12fa6a4d
Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function.
Michael Pavone <pavone@retrodev.com>
parents:
734
diff
changeset
|
3484 #endif |
594
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3485 retn(code); |
652 | 3486 |
594
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3487 options->write_16_highfirst = code->cur; |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3488 cycles(&options->gen, 3); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3489 check_cycles(&options->gen); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3490 push_r(code, options->gen.scratch2); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3491 push_r(code, options->gen.scratch1); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3492 add_ir(code, 1, options->gen.scratch2, SZ_W); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3493 shr_ir(code, 8, options->gen.scratch1, SZ_W); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3494 call(code, options->write_8_noinc); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3495 pop_r(code, options->gen.scratch1); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3496 pop_r(code, options->gen.scratch2); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3497 cycles(&options->gen, 3); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3498 check_cycles(&options->gen); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3499 //TODO: Check if we can get away with TCO here |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3500 call(code, options->write_8_noinc); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3501 retn(code); |
652 | 3502 |
594
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3503 options->write_16_lowfirst = code->cur; |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3504 cycles(&options->gen, 3); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3505 check_cycles(&options->gen); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3506 push_r(code, options->gen.scratch2); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3507 push_r(code, options->gen.scratch1); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3508 call(code, options->write_8_noinc); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3509 pop_r(code, options->gen.scratch1); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3510 pop_r(code, options->gen.scratch2); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3511 add_ir(code, 1, options->gen.scratch2, SZ_W); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3512 shr_ir(code, 8, options->gen.scratch1, SZ_W); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3513 cycles(&options->gen, 3); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3514 check_cycles(&options->gen); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3515 //TODO: Check if we can get away with TCO here |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3516 call(code, options->write_8_noinc); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3517 retn(code); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
3518 |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
3519 options->retrans_stub = code->cur; |
895
13388ab6d78a
Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
3520 tmp_stack_off = code->stack_off; |
899
07bfbbbb4b2e
Fix for Z80 retranslation post alignment rework
Michael Pavone <pavone@retrodev.com>
parents:
898
diff
changeset
|
3521 //calculate size of patch |
07bfbbbb4b2e
Fix for Z80 retranslation post alignment rework
Michael Pavone <pavone@retrodev.com>
parents:
898
diff
changeset
|
3522 mov_ir(code, 0x7FFF, options->gen.scratch1, SZ_D); |
07bfbbbb4b2e
Fix for Z80 retranslation post alignment rework
Michael Pavone <pavone@retrodev.com>
parents:
898
diff
changeset
|
3523 code->stack_off += sizeof(void *); |
07bfbbbb4b2e
Fix for Z80 retranslation post alignment rework
Michael Pavone <pavone@retrodev.com>
parents:
898
diff
changeset
|
3524 if (code->stack_off & 0xF) { |
07bfbbbb4b2e
Fix for Z80 retranslation post alignment rework
Michael Pavone <pavone@retrodev.com>
parents:
898
diff
changeset
|
3525 sub_ir(code, 16 - (code->stack_off & 0xF), RSP, SZ_PTR); |
07bfbbbb4b2e
Fix for Z80 retranslation post alignment rework
Michael Pavone <pavone@retrodev.com>
parents:
898
diff
changeset
|
3526 } |
07bfbbbb4b2e
Fix for Z80 retranslation post alignment rework
Michael Pavone <pavone@retrodev.com>
parents:
898
diff
changeset
|
3527 call_noalign(code, options->retrans_stub); |
07bfbbbb4b2e
Fix for Z80 retranslation post alignment rework
Michael Pavone <pavone@retrodev.com>
parents:
898
diff
changeset
|
3528 uint32_t patch_size = code->cur - options->retrans_stub; |
07bfbbbb4b2e
Fix for Z80 retranslation post alignment rework
Michael Pavone <pavone@retrodev.com>
parents:
898
diff
changeset
|
3529 code->cur = options->retrans_stub; |
07bfbbbb4b2e
Fix for Z80 retranslation post alignment rework
Michael Pavone <pavone@retrodev.com>
parents:
898
diff
changeset
|
3530 code->stack_off = tmp_stack_off; |
07bfbbbb4b2e
Fix for Z80 retranslation post alignment rework
Michael Pavone <pavone@retrodev.com>
parents:
898
diff
changeset
|
3531 |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
3532 //pop return address |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
3533 pop_r(code, options->gen.scratch2); |
895
13388ab6d78a
Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
3534 add_ir(code, 16-sizeof(void*), RSP, SZ_PTR); |
13388ab6d78a
Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
3535 code->stack_off = tmp_stack_off; |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
3536 call(code, options->gen.save_context); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
3537 //adjust pointer before move and call instructions that got us here |
899
07bfbbbb4b2e
Fix for Z80 retranslation post alignment rework
Michael Pavone <pavone@retrodev.com>
parents:
898
diff
changeset
|
3538 sub_ir(code, patch_size, options->gen.scratch2, SZ_PTR); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
3539 push_r(code, options->gen.context_reg); |
657
92ce5ea5ffc9
Use call_args and call_args_abi in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
653
diff
changeset
|
3540 call_args(code, (code_ptr)z80_retranslate_inst, 3, options->gen.scratch1, options->gen.context_reg, options->gen.scratch2); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
3541 pop_r(code, options->gen.context_reg); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
3542 mov_rr(code, RAX, options->gen.scratch1, SZ_PTR); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
3543 call(code, options->gen.load_context); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
3544 jmp_r(code, options->gen.scratch1); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
3545 |
1130
8f14767661fa
Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
3546 options->run = (z80_ctx_fun)code->cur; |
895
13388ab6d78a
Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
3547 tmp_stack_off = code->stack_off; |
665
d0943769353b
Added functions to gen_x86 for saving and restoring callee save registers to better abstract over ABI differences between x86 and x86-64
Michael Pavone <pavone@retrodev.com>
parents:
664
diff
changeset
|
3548 save_callee_save_regs(code); |
729
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
3549 #ifdef X86_64 |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
3550 mov_rr(code, RDI, options->gen.context_reg, SZ_PTR); |
729
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
3551 #else |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
3552 mov_rdispr(code, RSP, 5 * sizeof(int32_t), options->gen.context_reg, SZ_PTR); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
3553 #endif |
594
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3554 call(code, options->load_context_scratch); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
3555 cmp_irdisp(code, 0, options->gen.context_reg, offsetof(z80_context, extra_pc), SZ_PTR); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
3556 code_ptr no_extra = code->cur+1; |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
3557 jcc(code, CC_Z, no_extra); |
898
2f1157f00dc6
Z80 core is now slightly less broken
Michael Pavone <pavone@retrodev.com>
parents:
895
diff
changeset
|
3558 sub_ir(code, 16-sizeof(void *), RSP, SZ_PTR); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
3559 push_rdisp(code, options->gen.context_reg, offsetof(z80_context, extra_pc)); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
3560 mov_irdisp(code, 0, options->gen.context_reg, offsetof(z80_context, extra_pc), SZ_PTR); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
3561 *no_extra = code->cur - (no_extra + 1); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
3562 jmp_rind(code, options->gen.context_reg); |
895
13388ab6d78a
Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
3563 code->stack_off = tmp_stack_off; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3564 } |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
3565 |
1130
8f14767661fa
Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
3566 z80_context *init_z80_context(z80_options * options) |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
3567 { |
1130
8f14767661fa
Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
3568 size_t ctx_size = sizeof(z80_context) + ram_size(&options->gen) / (1 << options->gen.ram_flags_shift) / 8; |
8f14767661fa
Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
3569 z80_context *context = calloc(1, ctx_size); |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
3570 context->options = options; |
668
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3571 context->int_cycle = CYCLE_NEVER; |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3572 context->int_pulse_start = CYCLE_NEVER; |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3573 context->int_pulse_end = CYCLE_NEVER; |
1130
8f14767661fa
Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
3574 |
8f14767661fa
Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
3575 return context; |
668
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3576 } |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3577 |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3578 void z80_run(z80_context * context, uint32_t target_cycle) |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3579 { |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3580 if (context->reset || context->busack) { |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3581 context->current_cycle = target_cycle; |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3582 } else { |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3583 if (context->current_cycle < target_cycle) { |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3584 //busreq is sampled at the end of an m-cycle |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3585 //we can approximate that by running for a single m-cycle after a bus request |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3586 context->sync_cycle = context->busreq ? context->current_cycle + 3*context->options->gen.clock_divider : target_cycle; |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3587 if (!context->native_pc) { |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3588 context->native_pc = z80_get_native_address_trans(context, context->pc); |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3589 } |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3590 while (context->current_cycle < context->sync_cycle) |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3591 { |
1117
928a65750345
Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents:
1116
diff
changeset
|
3592 if (context->next_int_pulse && (context->int_pulse_end < context->current_cycle || context->int_pulse_end == CYCLE_NEVER)) { |
928a65750345
Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents:
1116
diff
changeset
|
3593 context->next_int_pulse(context); |
668
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3594 } |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3595 if (context->iff1) { |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3596 context->int_cycle = context->int_pulse_start < context->int_enable_cycle ? context->int_enable_cycle : context->int_pulse_start; |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3597 } else { |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3598 context->int_cycle = CYCLE_NEVER; |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3599 } |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3600 context->target_cycle = context->sync_cycle < context->int_cycle ? context->sync_cycle : context->int_cycle; |
670
f4f3e74b0ce6
Restore Z80 interrupt pulse duration and make a small improvement to debug print output
Michael Pavone <pavone@retrodev.com>
parents:
668
diff
changeset
|
3601 dprintf("Running Z80 from cycle %d to cycle %d. Int cycle: %d (%d - %d)\n", context->current_cycle, context->sync_cycle, context->int_cycle, context->int_pulse_start, context->int_pulse_end); |
668
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3602 context->options->run(context); |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3603 dprintf("Z80 ran to cycle %d\n", context->current_cycle); |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3604 } |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3605 if (context->busreq) { |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3606 context->busack = 1; |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3607 context->current_cycle = target_cycle; |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3608 } |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3609 } |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3610 } |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3611 } |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3612 |
884
252dfd29831d
Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents:
854
diff
changeset
|
3613 void z80_options_free(z80_options *opts) |
252dfd29831d
Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents:
854
diff
changeset
|
3614 { |
252dfd29831d
Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents:
854
diff
changeset
|
3615 free(opts->gen.native_code_map); |
252dfd29831d
Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents:
854
diff
changeset
|
3616 free(opts->gen.ram_inst_sizes); |
252dfd29831d
Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents:
854
diff
changeset
|
3617 free(opts); |
252dfd29831d
Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents:
854
diff
changeset
|
3618 } |
252dfd29831d
Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents:
854
diff
changeset
|
3619 |
668
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3620 void z80_assert_reset(z80_context * context, uint32_t cycle) |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3621 { |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3622 z80_run(context, cycle); |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3623 context->reset = 1; |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
3624 } |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
3625 |
668
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3626 void z80_clear_reset(z80_context * context, uint32_t cycle) |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3627 { |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3628 z80_run(context, cycle); |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3629 if (context->reset) { |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3630 //TODO: Handle case where reset is not asserted long enough |
701
200ee73c7210
Remove/comment verbose logging added for tracking down sync bug
Michael Pavone <pavone@retrodev.com>
parents:
697
diff
changeset
|
3631 context->im = 0; |
200ee73c7210
Remove/comment verbose logging added for tracking down sync bug
Michael Pavone <pavone@retrodev.com>
parents:
697
diff
changeset
|
3632 context->iff1 = context->iff2 = 0; |
668
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3633 context->native_pc = NULL; |
701
200ee73c7210
Remove/comment verbose logging added for tracking down sync bug
Michael Pavone <pavone@retrodev.com>
parents:
697
diff
changeset
|
3634 context->extra_pc = NULL; |
668
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3635 context->pc = 0; |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3636 context->reset = 0; |
676
41a399c11ef1
When going directly from reset to busreq, do not allow the Z80 to run
Michael Pavone <pavone@retrodev.com>
parents:
670
diff
changeset
|
3637 if (context->busreq) { |
41a399c11ef1
When going directly from reset to busreq, do not allow the Z80 to run
Michael Pavone <pavone@retrodev.com>
parents:
670
diff
changeset
|
3638 //TODO: Figure out appropriate delay |
41a399c11ef1
When going directly from reset to busreq, do not allow the Z80 to run
Michael Pavone <pavone@retrodev.com>
parents:
670
diff
changeset
|
3639 context->busack = 1; |
41a399c11ef1
When going directly from reset to busreq, do not allow the Z80 to run
Michael Pavone <pavone@retrodev.com>
parents:
670
diff
changeset
|
3640 } |
668
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3641 } |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3642 } |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3643 |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3644 void z80_assert_busreq(z80_context * context, uint32_t cycle) |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3645 { |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3646 z80_run(context, cycle); |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3647 context->busreq = 1; |
854
adeb6465ad53
Improve timing of Z80 busack. Fixes a crash in Barkley: Shut Up and Jam. Also vastly improves the audio output of Stuck Somewhere in Time
Michael Pavone <pavone@retrodev.com>
parents:
844
diff
changeset
|
3648 //this is an imperfect aproximation since most M-cycles take less tstates than the max |
adeb6465ad53
Improve timing of Z80 busack. Fixes a crash in Barkley: Shut Up and Jam. Also vastly improves the audio output of Stuck Somewhere in Time
Michael Pavone <pavone@retrodev.com>
parents:
844
diff
changeset
|
3649 //and a short 3-tstate m-cycle can take an unbounded number due to wait states |
adeb6465ad53
Improve timing of Z80 busack. Fixes a crash in Barkley: Shut Up and Jam. Also vastly improves the audio output of Stuck Somewhere in Time
Michael Pavone <pavone@retrodev.com>
parents:
844
diff
changeset
|
3650 if (context->current_cycle - cycle > MAX_MCYCLE_LENGTH * context->options->gen.clock_divider) { |
adeb6465ad53
Improve timing of Z80 busack. Fixes a crash in Barkley: Shut Up and Jam. Also vastly improves the audio output of Stuck Somewhere in Time
Michael Pavone <pavone@retrodev.com>
parents:
844
diff
changeset
|
3651 context->busack = 1; |
adeb6465ad53
Improve timing of Z80 busack. Fixes a crash in Barkley: Shut Up and Jam. Also vastly improves the audio output of Stuck Somewhere in Time
Michael Pavone <pavone@retrodev.com>
parents:
844
diff
changeset
|
3652 } |
701
200ee73c7210
Remove/comment verbose logging added for tracking down sync bug
Michael Pavone <pavone@retrodev.com>
parents:
697
diff
changeset
|
3653 } |
668
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3654 |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3655 void z80_clear_busreq(z80_context * context, uint32_t cycle) |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3656 { |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3657 z80_run(context, cycle); |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3658 context->busreq = 0; |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3659 context->busack = 0; |
844
74e161fe7d39
Small tweaks to timing of 68K/Z80 interactions based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
842
diff
changeset
|
3660 //there appears to be at least a 1 Z80 cycle delay between busreq |
74e161fe7d39
Small tweaks to timing of 68K/Z80 interactions based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
842
diff
changeset
|
3661 //being released and resumption of execution |
74e161fe7d39
Small tweaks to timing of 68K/Z80 interactions based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
842
diff
changeset
|
3662 context->current_cycle += context->options->gen.clock_divider; |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
3663 } |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
3664 |
668
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3665 uint8_t z80_get_busack(z80_context * context, uint32_t cycle) |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
3666 { |
668
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3667 z80_run(context, cycle); |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3668 return context->busack; |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3669 } |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3670 |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3671 void z80_adjust_cycles(z80_context * context, uint32_t deduction) |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3672 { |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3673 if (context->current_cycle < deduction) { |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3674 fprintf(stderr, "WARNING: Deduction of %u cycles when Z80 cycle counter is only %u\n", deduction, context->current_cycle); |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3675 context->current_cycle = 0; |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3676 } else { |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3677 context->current_cycle -= deduction; |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3678 } |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3679 if (context->int_enable_cycle != CYCLE_NEVER) { |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3680 if (context->int_enable_cycle < deduction) { |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3681 context->int_enable_cycle = 0; |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3682 } else { |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3683 context->int_enable_cycle -= deduction; |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3684 } |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3685 } |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3686 if (context->int_pulse_start != CYCLE_NEVER) { |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3687 if (context->int_pulse_end < deduction) { |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3688 context->int_pulse_start = context->int_pulse_end = CYCLE_NEVER; |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3689 } else { |
1117
928a65750345
Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents:
1116
diff
changeset
|
3690 if (context->int_pulse_end != CYCLE_NEVER) { |
928a65750345
Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents:
1116
diff
changeset
|
3691 context->int_pulse_end -= deduction; |
928a65750345
Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents:
1116
diff
changeset
|
3692 } |
668
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3693 if (context->int_pulse_start < deduction) { |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3694 context->int_pulse_start = 0; |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3695 } else { |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3696 context->int_pulse_start -= deduction; |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3697 } |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3698 } |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3699 } |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
3700 } |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
3701 |
652 | 3702 uint32_t zbreakpoint_patch(z80_context * context, uint16_t address, code_ptr dst) |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
3703 { |
1131
136b1676109b
Partial fix for Z80 debugger brokeness introduced with stack alignment changes
Michael Pavone <pavone@retrodev.com>
parents:
1130
diff
changeset
|
3704 code_info code = { |
136b1676109b
Partial fix for Z80 debugger brokeness introduced with stack alignment changes
Michael Pavone <pavone@retrodev.com>
parents:
1130
diff
changeset
|
3705 dst, |
136b1676109b
Partial fix for Z80 debugger brokeness introduced with stack alignment changes
Michael Pavone <pavone@retrodev.com>
parents:
1130
diff
changeset
|
3706 dst+32, |
136b1676109b
Partial fix for Z80 debugger brokeness introduced with stack alignment changes
Michael Pavone <pavone@retrodev.com>
parents:
1130
diff
changeset
|
3707 #ifdef X86_64 |
136b1676109b
Partial fix for Z80 debugger brokeness introduced with stack alignment changes
Michael Pavone <pavone@retrodev.com>
parents:
1130
diff
changeset
|
3708 8 |
136b1676109b
Partial fix for Z80 debugger brokeness introduced with stack alignment changes
Michael Pavone <pavone@retrodev.com>
parents:
1130
diff
changeset
|
3709 #else |
136b1676109b
Partial fix for Z80 debugger brokeness introduced with stack alignment changes
Michael Pavone <pavone@retrodev.com>
parents:
1130
diff
changeset
|
3710 0 |
136b1676109b
Partial fix for Z80 debugger brokeness introduced with stack alignment changes
Michael Pavone <pavone@retrodev.com>
parents:
1130
diff
changeset
|
3711 #endif |
136b1676109b
Partial fix for Z80 debugger brokeness introduced with stack alignment changes
Michael Pavone <pavone@retrodev.com>
parents:
1130
diff
changeset
|
3712 }; |
659
759c38bf97f8
Minor Z80 core cleanup
Michael Pavone <pavone@retrodev.com>
parents:
657
diff
changeset
|
3713 mov_ir(&code, address, context->options->gen.scratch1, SZ_W); |
652 | 3714 call(&code, context->bp_stub); |
3715 return code.cur-dst; | |
626
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
3716 } |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
3717 |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
3718 void zcreate_stub(z80_context * context) |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
3719 { |
1224
15c5be05e6a9
Ported correct but inefficient overlapping instruction handling from 68K core to Z80 core. Fixed remaining stack alignment issue for Z80 breakpoints on 64-bit. Probably still needs fixing for 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
1222
diff
changeset
|
3720 //FIXME: Stack offset stuff is probably broken on 32-bit |
652 | 3721 z80_options * opts = context->options; |
3722 code_info *code = &opts->gen.code; | |
894
a7774fc2de4b
Partially working change to do proper stack alignment rather than doing a lame alignment check when calling a C compile dfunction. 68K core seems okay, but Z80 is busted.
Michael Pavone <pavone@retrodev.com>
parents:
884
diff
changeset
|
3723 uint32_t start_stack_off = code->stack_off; |
652 | 3724 check_code_prologue(code); |
3725 context->bp_stub = code->cur; | |
626
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
3726 |
1131
136b1676109b
Partial fix for Z80 debugger brokeness introduced with stack alignment changes
Michael Pavone <pavone@retrodev.com>
parents:
1130
diff
changeset
|
3727 //Calculate length of prologue |
652 | 3728 check_cycles_int(&opts->gen, 0); |
3729 int check_int_size = code->cur-context->bp_stub; | |
3730 code->cur = context->bp_stub; | |
626
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
3731 |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
3732 //Calculate length of patch |
652 | 3733 int patch_size = zbreakpoint_patch(context, 0, code->cur); |
626
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
3734 |
1131
136b1676109b
Partial fix for Z80 debugger brokeness introduced with stack alignment changes
Michael Pavone <pavone@retrodev.com>
parents:
1130
diff
changeset
|
3735 #ifdef X86_64 |
136b1676109b
Partial fix for Z80 debugger brokeness introduced with stack alignment changes
Michael Pavone <pavone@retrodev.com>
parents:
1130
diff
changeset
|
3736 code->stack_off = 8; |
136b1676109b
Partial fix for Z80 debugger brokeness introduced with stack alignment changes
Michael Pavone <pavone@retrodev.com>
parents:
1130
diff
changeset
|
3737 #endif |
136b1676109b
Partial fix for Z80 debugger brokeness introduced with stack alignment changes
Michael Pavone <pavone@retrodev.com>
parents:
1130
diff
changeset
|
3738 //Save context and call breakpoint handler |
652 | 3739 call(code, opts->gen.save_context); |
3740 push_r(code, opts->gen.scratch1); | |
657
92ce5ea5ffc9
Use call_args and call_args_abi in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
653
diff
changeset
|
3741 call_args_abi(code, context->bp_handler, 2, opts->gen.context_reg, opts->gen.scratch1); |
664
bca748422bf0
Use SZ_PTR instead of SZ_Q in Z80 core for 32-bit compat
Michael Pavone <pavone@retrodev.com>
parents:
663
diff
changeset
|
3742 mov_rr(code, RAX, opts->gen.context_reg, SZ_PTR); |
682 | 3743 //Restore context |
652 | 3744 call(code, opts->gen.load_context); |
3745 pop_r(code, opts->gen.scratch1); | |
682 | 3746 //do prologue stuff |
1131
136b1676109b
Partial fix for Z80 debugger brokeness introduced with stack alignment changes
Michael Pavone <pavone@retrodev.com>
parents:
1130
diff
changeset
|
3747 cmp_ir(code, 1, opts->gen.cycles, SZ_D); |
652 | 3748 uint8_t * jmp_off = code->cur+1; |
1047
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
3749 jcc(code, CC_NS, code->cur + 7); |
652 | 3750 pop_r(code, opts->gen.scratch1); |
664
bca748422bf0
Use SZ_PTR instead of SZ_Q in Z80 core for 32-bit compat
Michael Pavone <pavone@retrodev.com>
parents:
663
diff
changeset
|
3751 add_ir(code, check_int_size - patch_size, opts->gen.scratch1, SZ_PTR); |
1224
15c5be05e6a9
Ported correct but inefficient overlapping instruction handling from 68K core to Z80 core. Fixed remaining stack alignment issue for Z80 breakpoints on 64-bit. Probably still needs fixing for 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
1222
diff
changeset
|
3752 #ifdef X86_64 |
15c5be05e6a9
Ported correct but inefficient overlapping instruction handling from 68K core to Z80 core. Fixed remaining stack alignment issue for Z80 breakpoints on 64-bit. Probably still needs fixing for 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
1222
diff
changeset
|
3753 sub_ir(code, 8, RSP, SZ_PTR); |
15c5be05e6a9
Ported correct but inefficient overlapping instruction handling from 68K core to Z80 core. Fixed remaining stack alignment issue for Z80 breakpoints on 64-bit. Probably still needs fixing for 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
1222
diff
changeset
|
3754 #endif |
652 | 3755 push_r(code, opts->gen.scratch1); |
3756 jmp(code, opts->gen.handle_cycle_limit_int); | |
3757 *jmp_off = code->cur - (jmp_off+1); | |
682 | 3758 //jump back to body of translated instruction |
652 | 3759 pop_r(code, opts->gen.scratch1); |
664
bca748422bf0
Use SZ_PTR instead of SZ_Q in Z80 core for 32-bit compat
Michael Pavone <pavone@retrodev.com>
parents:
663
diff
changeset
|
3760 add_ir(code, check_int_size - patch_size, opts->gen.scratch1, SZ_PTR); |
652 | 3761 jmp_r(code, opts->gen.scratch1); |
894
a7774fc2de4b
Partially working change to do proper stack alignment rather than doing a lame alignment check when calling a C compile dfunction. 68K core seems okay, but Z80 is busted.
Michael Pavone <pavone@retrodev.com>
parents:
884
diff
changeset
|
3762 code->stack_off = start_stack_off; |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
3763 } |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
3764 |
366
836585d389b8
Partial implementation of Z80 debugger
Mike Pavone <pavone@retrodev.com>
parents:
363
diff
changeset
|
3765 void zinsert_breakpoint(z80_context * context, uint16_t address, uint8_t * bp_handler) |
836585d389b8
Partial implementation of Z80 debugger
Mike Pavone <pavone@retrodev.com>
parents:
363
diff
changeset
|
3766 { |
626
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
3767 context->bp_handler = bp_handler; |
819
ab017fb09e77
Added support for an IO memory map in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
792
diff
changeset
|
3768 uint8_t bit = 1 << (address % 8); |
ab017fb09e77
Added support for an IO memory map in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
792
diff
changeset
|
3769 if (!(bit & context->breakpoint_flags[address / 8])) { |
ab017fb09e77
Added support for an IO memory map in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
792
diff
changeset
|
3770 context->breakpoint_flags[address / 8] |= bit; |
626
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
3771 if (!context->bp_stub) { |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
3772 zcreate_stub(context); |
366
836585d389b8
Partial implementation of Z80 debugger
Mike Pavone <pavone@retrodev.com>
parents:
363
diff
changeset
|
3773 } |
626
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
3774 uint8_t * native = z80_get_native_address(context, address); |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
3775 if (native) { |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
3776 zbreakpoint_patch(context, address, native); |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
3777 } |
366
836585d389b8
Partial implementation of Z80 debugger
Mike Pavone <pavone@retrodev.com>
parents:
363
diff
changeset
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3778 } |
836585d389b8
Partial implementation of Z80 debugger
Mike Pavone <pavone@retrodev.com>
parents:
363
diff
changeset
|
3779 } |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
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3780 |
366
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Partial implementation of Z80 debugger
Mike Pavone <pavone@retrodev.com>
parents:
363
diff
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3781 void zremove_breakpoint(z80_context * context, uint16_t address) |
836585d389b8
Partial implementation of Z80 debugger
Mike Pavone <pavone@retrodev.com>
parents:
363
diff
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3782 { |
819
ab017fb09e77
Added support for an IO memory map in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
792
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3783 context->breakpoint_flags[address / 8] &= ~(1 << (address % 8)); |
366
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Partial implementation of Z80 debugger
Mike Pavone <pavone@retrodev.com>
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3784 uint8_t * native = z80_get_native_address(context, address); |
626
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
3785 if (native) { |
652 | 3786 z80_options * opts = context->options; |
3787 code_info tmp_code = opts->gen.code; | |
3788 opts->gen.code.cur = native; | |
1131
136b1676109b
Partial fix for Z80 debugger brokeness introduced with stack alignment changes
Michael Pavone <pavone@retrodev.com>
parents:
1130
diff
changeset
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3789 opts->gen.code.last = native + 128; |
652 | 3790 check_cycles_int(&opts->gen, address); |
3791 opts->gen.code = tmp_code; | |
792
724bbec47f86
Use a new fatal_error function instead of calling fprintf and exit for fatal errors. This new function more gracefully handles the case in which BlastEm was not started from a terminal or disconnected from ther terminal (Windows).
Michael Pavone <pavone@retrodev.com>
parents:
755
diff
changeset
|
3792 } |
366
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Partial implementation of Z80 debugger
Mike Pavone <pavone@retrodev.com>
parents:
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diff
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|
3793 } |
836585d389b8
Partial implementation of Z80 debugger
Mike Pavone <pavone@retrodev.com>
parents:
363
diff
changeset
|
3794 |