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annotate backend_x86.c @ 2166:3a6680e9204a
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author | Michael Pavone <pavone@retrodev.com> |
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date | Sat, 23 Jul 2022 10:54:07 -0700 |
parents | b6338e18787e |
children | f82c090c1e89 |
rev | line source |
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567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
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1 #include "backend.h" |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
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2 #include "gen_x86.h" |
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3 #include <string.h> |
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4 |
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Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
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5 void cycles(cpu_options *opts, uint32_t num) |
8e395210f50f
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6 { |
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7 if (opts->limit < 0) { |
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8 sub_ir(&opts->code, num*opts->clock_divider, opts->cycles, SZ_D); |
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9 } else { |
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10 add_ir(&opts->code, num*opts->clock_divider, opts->cycles, SZ_D); |
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11 } |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
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12 } |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
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13 |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
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14 void check_cycles_int(cpu_options *opts, uint32_t address) |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
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15 { |
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16 code_info *code = &opts->code; |
1109
4bc27caa6e20
Fix a subtle bug in interrupt handling introduced with the move to a single cycle register in the Z80 core. Fixes regression in Puyo Puyo 2
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17 uint8_t cc; |
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18 if (opts->limit < 0) { |
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19 cmp_ir(code, 1, opts->cycles, SZ_D); |
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20 cc = CC_NS; |
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21 } else { |
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22 cmp_rr(code, opts->cycles, opts->limit, SZ_D); |
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23 cc = CC_A; |
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24 } |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
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25 code_ptr jmp_off = code->cur+1; |
1109
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Fix a subtle bug in interrupt handling introduced with the move to a single cycle register in the Z80 core. Fixes regression in Puyo Puyo 2
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26 jcc(code, cc, jmp_off+1); |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
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27 mov_ir(code, address, opts->scratch1, SZ_D); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
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28 call(code, opts->handle_cycle_limit_int); |
8e395210f50f
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29 *jmp_off = code->cur - (jmp_off+1); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
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30 } |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
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31 |
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32 void retranslate_calc(cpu_options *opts) |
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33 { |
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34 code_info *code = &opts->code; |
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35 code_info tmp = *code; |
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36 uint8_t cc; |
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37 if (opts->limit < 0) { |
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38 cmp_ir(code, 1, opts->cycles, SZ_D); |
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39 cc = CC_NS; |
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40 } else { |
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41 cmp_rr(code, opts->cycles, opts->limit, SZ_D); |
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42 cc = CC_A; |
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43 } |
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44 jcc(code, cc, code->cur+2); |
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45 opts->move_pc_off = code->cur - tmp.cur; |
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46 mov_ir(code, 0x1234, opts->scratch1, SZ_D); |
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47 opts->move_pc_size = code->cur - tmp.cur - opts->move_pc_off; |
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48 *code = tmp; |
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49 } |
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50 |
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51 void patch_for_retranslate(cpu_options *opts, code_ptr native_address, code_ptr handler) |
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52 { |
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53 if (!is_mov_ir(native_address)) { |
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54 //instruction is not already patched for either retranslation or a breakpoint |
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55 //copy original mov_ir instruction containing PC to beginning of native code area |
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56 memmove(native_address, native_address + opts->move_pc_off, opts->move_pc_size); |
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57 } |
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58 //jump to the retranslation handler |
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59 code_info tmp = { |
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60 .cur = native_address + opts->move_pc_size, |
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61 .last = native_address + 256, |
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62 .stack_off = 0 |
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63 }; |
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64 jmp(&tmp, handler); |
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65 } |
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66 |
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67 void defer_translation(cpu_options *opts, uint32_t address, code_ptr handler) |
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68 { |
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69 mov_ir(&opts->code, address, opts->scratch1, SZ_D); |
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70 jmp(&opts->code, handler); |
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71 } |
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72 |
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73 void check_cycles(cpu_options * opts) |
8e395210f50f
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74 { |
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Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
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75 code_info *code = &opts->code; |
1109
4bc27caa6e20
Fix a subtle bug in interrupt handling introduced with the move to a single cycle register in the Z80 core. Fixes regression in Puyo Puyo 2
Michael Pavone <pavone@retrodev.com>
parents:
1107
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76 uint8_t cc; |
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parents:
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77 if (opts->limit < 0) { |
1109
4bc27caa6e20
Fix a subtle bug in interrupt handling introduced with the move to a single cycle register in the Z80 core. Fixes regression in Puyo Puyo 2
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78 cmp_ir(code, 1, opts->cycles, SZ_D); |
4bc27caa6e20
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79 cc = CC_NS; |
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80 } else { |
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81 cmp_rr(code, opts->cycles, opts->limit, SZ_D); |
1109
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Fix a subtle bug in interrupt handling introduced with the move to a single cycle register in the Z80 core. Fixes regression in Puyo Puyo 2
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82 cc = CC_A; |
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83 } |
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84 check_alloc_code(code, MAX_INST_LEN*2); |
8e395210f50f
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85 code_ptr jmp_off = code->cur+1; |
1109
4bc27caa6e20
Fix a subtle bug in interrupt handling introduced with the move to a single cycle register in the Z80 core. Fixes regression in Puyo Puyo 2
Michael Pavone <pavone@retrodev.com>
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1107
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86 jcc(code, cc, jmp_off+1); |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
87 call(code, opts->handle_cycle_limit); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
88 *jmp_off = code->cur - (jmp_off+1); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
89 } |
589
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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parents:
567
diff
changeset
|
90 |
697
7f96bd1cb1be
Sync fixes and logging to fix more sync issues
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parents:
692
diff
changeset
|
91 void log_address(cpu_options *opts, uint32_t address, char * format) |
7f96bd1cb1be
Sync fixes and logging to fix more sync issues
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parents:
692
diff
changeset
|
92 { |
7f96bd1cb1be
Sync fixes and logging to fix more sync issues
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parents:
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diff
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|
93 code_info *code = &opts->code; |
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Sync fixes and logging to fix more sync issues
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parents:
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diff
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|
94 call(code, opts->save_context); |
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Sync fixes and logging to fix more sync issues
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diff
changeset
|
95 push_r(code, opts->context_reg); |
7f96bd1cb1be
Sync fixes and logging to fix more sync issues
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parents:
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diff
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|
96 mov_rr(code, opts->cycles, RDX, SZ_D); |
7f96bd1cb1be
Sync fixes and logging to fix more sync issues
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parents:
692
diff
changeset
|
97 mov_ir(code, (int64_t)format, RDI, SZ_PTR); |
7f96bd1cb1be
Sync fixes and logging to fix more sync issues
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parents:
692
diff
changeset
|
98 mov_ir(code, address, RSI, SZ_D); |
7f96bd1cb1be
Sync fixes and logging to fix more sync issues
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parents:
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diff
changeset
|
99 call_args_abi(code, (code_ptr)printf, 3, RDI, RSI, RDX); |
7f96bd1cb1be
Sync fixes and logging to fix more sync issues
Michael Pavone <pavone@retrodev.com>
parents:
692
diff
changeset
|
100 pop_r(code, opts->context_reg); |
7f96bd1cb1be
Sync fixes and logging to fix more sync issues
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parents:
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diff
changeset
|
101 call(code, opts->load_context); |
7f96bd1cb1be
Sync fixes and logging to fix more sync issues
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parents:
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diff
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|
102 } |
7f96bd1cb1be
Sync fixes and logging to fix more sync issues
Michael Pavone <pavone@retrodev.com>
parents:
692
diff
changeset
|
103 |
601
f0061e3d2ad9
Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor
Michael Pavone <pavone@retrodev.com>
parents:
595
diff
changeset
|
104 void check_code_prologue(code_info *code) |
f0061e3d2ad9
Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor
Michael Pavone <pavone@retrodev.com>
parents:
595
diff
changeset
|
105 { |
f0061e3d2ad9
Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor
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parents:
595
diff
changeset
|
106 check_alloc_code(code, MAX_INST_LEN*4); |
f0061e3d2ad9
Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor
Michael Pavone <pavone@retrodev.com>
parents:
595
diff
changeset
|
107 } |
f0061e3d2ad9
Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor
Michael Pavone <pavone@retrodev.com>
parents:
595
diff
changeset
|
108 |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
109 code_ptr gen_mem_fun(cpu_options * opts, memmap_chunk const * memmap, uint32_t num_chunks, ftype fun_type, code_ptr *after_inc) |
589
2dde38c1744f
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110 { |
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111 code_info *code = &opts->code; |
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|
112 code_ptr start = code->cur; |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
Michael Pavone <pavone@retrodev.com>
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diff
changeset
|
113 check_cycles(opts); |
987
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
114 uint8_t is_write = fun_type == WRITE_16 || fun_type == WRITE_8; |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
115 uint8_t adr_reg = is_write ? opts->scratch2 : opts->scratch1; |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
116 uint8_t size = (fun_type == READ_16 || fun_type == WRITE_16) ? SZ_W : SZ_B; |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
117 if (size != SZ_B && opts->align_error_mask) { |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
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diff
changeset
|
118 test_ir(code, opts->align_error_mask, adr_reg, SZ_D); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
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diff
changeset
|
119 jcc(code, CC_NZ, is_write ? opts->handle_align_error_write : opts->handle_align_error_read); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
120 } |
589
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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parents:
567
diff
changeset
|
121 cycles(opts, opts->bus_cycles); |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
589
diff
changeset
|
122 if (after_inc) { |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
589
diff
changeset
|
123 *after_inc = code->cur; |
ea80559c67cb
WIP effort to update z80 core for code gen changes
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parents:
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diff
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|
124 } |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
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diff
changeset
|
125 |
750
59b499f6b24f
Fix handling of address mask in gen_mem_fun
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parents:
697
diff
changeset
|
126 if (opts->address_size == SZ_D && opts->address_mask != 0xFFFFFFFF) { |
59b499f6b24f
Fix handling of address mask in gen_mem_fun
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parents:
697
diff
changeset
|
127 and_ir(code, opts->address_mask, adr_reg, SZ_D); |
1116
fe8c79f82c22
More cleanup in preparation for SMS/Mark III support
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parents:
1109
diff
changeset
|
128 } else if (opts->address_size == SZ_W && opts->address_mask != 0xFFFF) { |
fe8c79f82c22
More cleanup in preparation for SMS/Mark III support
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parents:
1109
diff
changeset
|
129 and_ir(code, opts->address_mask, adr_reg, SZ_W); |
589
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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diff
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|
130 } |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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diff
changeset
|
131 code_ptr lb_jcc = NULL, ub_jcc = NULL; |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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parents:
567
diff
changeset
|
132 uint16_t access_flag = is_write ? MMAP_WRITE : MMAP_READ; |
690
fc04781f4d28
Removed hardcoded assumptions in M68K core about which parts of the memory map are RAM
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
133 uint32_t ram_flags_off = opts->ram_flags_off; |
1086
f0a1e0a2263c
Made some optimizations to gen_mem_fun to keep the size of chunk handler sections within range of a single byte displacement
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parents:
1084
diff
changeset
|
134 uint32_t min_address = 0; |
f0a1e0a2263c
Made some optimizations to gen_mem_fun to keep the size of chunk handler sections within range of a single byte displacement
Michael Pavone <pavone@retrodev.com>
parents:
1084
diff
changeset
|
135 uint32_t max_address = opts->max_address; |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
2036
diff
changeset
|
136 uint8_t need_wide_jcc = 0; |
589
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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parents:
567
diff
changeset
|
137 for (uint32_t chunk = 0; chunk < num_chunks; chunk++) |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
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diff
changeset
|
138 { |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
2036
diff
changeset
|
139 code_info chunk_start = *code; |
1086
f0a1e0a2263c
Made some optimizations to gen_mem_fun to keep the size of chunk handler sections within range of a single byte displacement
Michael Pavone <pavone@retrodev.com>
parents:
1084
diff
changeset
|
140 if (memmap[chunk].start > min_address) { |
589
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
567
diff
changeset
|
141 cmp_ir(code, memmap[chunk].start, adr_reg, opts->address_size); |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
567
diff
changeset
|
142 lb_jcc = code->cur + 1; |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
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parents:
2036
diff
changeset
|
143 if (need_wide_jcc) { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
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parents:
2036
diff
changeset
|
144 jcc(code, CC_C, code->cur + 130); |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
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parents:
2036
diff
changeset
|
145 lb_jcc++; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
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parents:
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diff
changeset
|
146 } else { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
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parents:
2036
diff
changeset
|
147 jcc(code, CC_C, code->cur + 2); |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
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parents:
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diff
changeset
|
148 } |
1086
f0a1e0a2263c
Made some optimizations to gen_mem_fun to keep the size of chunk handler sections within range of a single byte displacement
Michael Pavone <pavone@retrodev.com>
parents:
1084
diff
changeset
|
149 } else { |
f0a1e0a2263c
Made some optimizations to gen_mem_fun to keep the size of chunk handler sections within range of a single byte displacement
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parents:
1084
diff
changeset
|
150 min_address = memmap[chunk].end; |
589
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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parents:
567
diff
changeset
|
151 } |
1086
f0a1e0a2263c
Made some optimizations to gen_mem_fun to keep the size of chunk handler sections within range of a single byte displacement
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parents:
1084
diff
changeset
|
152 if (memmap[chunk].end < max_address) { |
589
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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parents:
567
diff
changeset
|
153 cmp_ir(code, memmap[chunk].end, adr_reg, opts->address_size); |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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parents:
567
diff
changeset
|
154 ub_jcc = code->cur + 1; |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
2036
diff
changeset
|
155 if (need_wide_jcc) { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
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parents:
2036
diff
changeset
|
156 jcc(code, CC_NC, code->cur + 130); |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
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parents:
2036
diff
changeset
|
157 ub_jcc++; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
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parents:
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diff
changeset
|
158 } else { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
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parents:
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diff
changeset
|
159 jcc(code, CC_NC, code->cur + 2); |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
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parents:
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diff
changeset
|
160 } |
1086
f0a1e0a2263c
Made some optimizations to gen_mem_fun to keep the size of chunk handler sections within range of a single byte displacement
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parents:
1084
diff
changeset
|
161 } else { |
f0a1e0a2263c
Made some optimizations to gen_mem_fun to keep the size of chunk handler sections within range of a single byte displacement
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parents:
1084
diff
changeset
|
162 max_address = memmap[chunk].start; |
589
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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parents:
567
diff
changeset
|
163 } |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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parents:
567
diff
changeset
|
164 |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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parents:
567
diff
changeset
|
165 if (memmap[chunk].mask != opts->address_mask) { |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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parents:
567
diff
changeset
|
166 and_ir(code, memmap[chunk].mask, adr_reg, opts->address_size); |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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parents:
567
diff
changeset
|
167 } |
2134
9caebcfeac72
Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
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parents:
2133
diff
changeset
|
168 code_ptr after_normal = NULL; |
2138
b6338e18787e
Fix some dynarec code invalidation issues
Michael Pavone <pavone@retrodev.com>
parents:
2134
diff
changeset
|
169 uint8_t need_addr_pop = 0; |
2134
9caebcfeac72
Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
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parents:
2133
diff
changeset
|
170 if (size == SZ_B && memmap[chunk].shift != 0) { |
2138
b6338e18787e
Fix some dynarec code invalidation issues
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parents:
2134
diff
changeset
|
171 if (is_write && (memmap[chunk].flags & MMAP_CODE)) { |
b6338e18787e
Fix some dynarec code invalidation issues
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parents:
2134
diff
changeset
|
172 push_r(code, adr_reg); |
b6338e18787e
Fix some dynarec code invalidation issues
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parents:
2134
diff
changeset
|
173 need_addr_pop = 1; |
b6338e18787e
Fix some dynarec code invalidation issues
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parents:
2134
diff
changeset
|
174 } |
2134
9caebcfeac72
Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
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parents:
2133
diff
changeset
|
175 btr_ir(code, 0, adr_reg, opts->address_size); |
9caebcfeac72
Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
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parents:
2133
diff
changeset
|
176 code_ptr normal = code->cur+1; |
9caebcfeac72
Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
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parents:
2133
diff
changeset
|
177 jcc(code, CC_NC, normal); |
9caebcfeac72
Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
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2133
diff
changeset
|
178 if (memmap[chunk].shift > 0) { |
9caebcfeac72
Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
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parents:
2133
diff
changeset
|
179 shl_ir(code, memmap[chunk].shift, adr_reg, opts->address_size); |
9caebcfeac72
Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
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diff
changeset
|
180 } else { |
9caebcfeac72
Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
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parents:
2133
diff
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181 shr_ir(code, -memmap[chunk].shift, adr_reg, opts->address_size); |
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182 } |
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183 or_ir(code, 1, adr_reg, opts->address_size); |
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184 after_normal = code->cur + 1; |
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185 jmp(code, after_normal); |
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186 *normal = code->cur - (normal + 1); |
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187 } |
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188 if (memmap[chunk].shift > 0) { |
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189 if (!need_addr_pop && is_write && (memmap[chunk].flags & MMAP_CODE)) { |
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190 push_r(code, adr_reg); |
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191 need_addr_pop = 1; |
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192 } |
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193 shl_ir(code, memmap[chunk].shift, adr_reg, opts->address_size); |
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194 } else if (memmap[chunk].shift < 0) { |
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195 if (!need_addr_pop && is_write && (memmap[chunk].flags & MMAP_CODE)) { |
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196 push_r(code, adr_reg); |
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197 need_addr_pop = 1; |
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198 } |
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199 shr_ir(code, -memmap[chunk].shift, adr_reg, opts->address_size); |
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200 } |
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201 if (after_normal) { |
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202 *after_normal = code->cur - (after_normal + 1); |
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203 } |
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204 void * cfun; |
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205 switch (fun_type) |
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206 { |
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207 case READ_16: |
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208 cfun = memmap[chunk].read_16; |
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209 break; |
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210 case READ_8: |
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211 cfun = memmap[chunk].read_8; |
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212 break; |
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213 case WRITE_16: |
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214 cfun = memmap[chunk].write_16; |
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215 break; |
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216 case WRITE_8: |
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217 cfun = memmap[chunk].write_8; |
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218 break; |
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219 default: |
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220 cfun = NULL; |
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221 } |
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222 if(memmap[chunk].flags & access_flag) { |
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223 if (memmap[chunk].flags & MMAP_PTR_IDX) { |
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224 if (memmap[chunk].flags & MMAP_FUNC_NULL) { |
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225 cmp_irdisp(code, 0, opts->context_reg, opts->mem_ptr_off + sizeof(void*) * memmap[chunk].ptr_index, SZ_PTR); |
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226 code_ptr not_null = code->cur + 1; |
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227 jcc(code, CC_NZ, code->cur + 2); |
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228 call(code, opts->save_context); |
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229 if (is_write) { |
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230 call_args_abi(code, cfun, 3, opts->scratch2, opts->context_reg, opts->scratch1); |
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231 mov_rr(code, RAX, opts->context_reg, SZ_PTR); |
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232 } else { |
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233 push_r(code, opts->context_reg); |
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234 call_args_abi(code, cfun, 2, opts->scratch1, opts->context_reg); |
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235 pop_r(code, opts->context_reg); |
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236 mov_rr(code, RAX, opts->scratch1, size); |
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237 } |
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238 jmp(code, opts->load_context); |
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239 |
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240 *not_null = code->cur - (not_null + 1); |
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241 } |
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242 if ((opts->byte_swap || memmap[chunk].flags & MMAP_BYTESWAP) && size == SZ_B) { |
589
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243 xor_ir(code, 1, adr_reg, opts->address_size); |
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244 } |
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245 if (opts->address_size != SZ_D) { |
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246 movzx_rr(code, adr_reg, adr_reg, opts->address_size, SZ_D); |
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247 } |
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248 if (!need_addr_pop && is_write && (memmap[chunk].flags & MMAP_CODE)) { |
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249 push_r(code, adr_reg); |
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250 need_addr_pop = 1; |
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251 } |
589
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252 add_rdispr(code, opts->context_reg, opts->mem_ptr_off + sizeof(void*) * memmap[chunk].ptr_index, adr_reg, SZ_PTR); |
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253 if (is_write) { |
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254 mov_rrind(code, opts->scratch1, opts->scratch2, size); |
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255 } else { |
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256 mov_rindr(code, opts->scratch1, opts->scratch1, size); |
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257 } |
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258 } else { |
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259 uint8_t tmp_size = size; |
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260 if (size == SZ_B) { |
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261 if ((memmap[chunk].flags & MMAP_ONLY_ODD) || (memmap[chunk].flags & MMAP_ONLY_EVEN)) { |
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262 bt_ir(code, 0, adr_reg, opts->address_size); |
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263 code_ptr good_addr = code->cur + 1; |
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264 jcc(code, (memmap[chunk].flags & MMAP_ONLY_ODD) ? CC_C : CC_NC, code->cur + 2); |
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265 if (!is_write) { |
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266 mov_ir(code, 0xFF, opts->scratch1, SZ_B); |
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267 } |
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268 retn(code); |
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269 *good_addr = code->cur - (good_addr + 1); |
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270 shr_ir(code, 1, adr_reg, opts->address_size); |
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271 } else if (opts->byte_swap || memmap[chunk].flags & MMAP_BYTESWAP) { |
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272 xor_ir(code, 1, adr_reg, opts->address_size); |
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273 } |
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|
274 } else if ((memmap[chunk].flags & MMAP_ONLY_ODD) || (memmap[chunk].flags & MMAP_ONLY_EVEN)) { |
2dde38c1744f
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275 tmp_size = SZ_B; |
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276 shr_ir(code, 1, adr_reg, opts->address_size); |
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277 if ((memmap[chunk].flags & MMAP_ONLY_EVEN) && is_write) { |
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278 shr_ir(code, 8, opts->scratch1, SZ_W); |
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279 } |
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280 } |
595
68f86ca4bb32
Add a couple of missing checks for the byte_swap and address_size parameters in gen_mem_fun
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593
diff
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|
281 if (opts->address_size != SZ_D) { |
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|
282 movzx_rr(code, adr_reg, adr_reg, opts->address_size, SZ_D); |
68f86ca4bb32
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593
diff
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|
283 } |
589
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284 if ((intptr_t)memmap[chunk].buffer <= 0x7FFFFFFF && (intptr_t)memmap[chunk].buffer >= -2147483648) { |
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285 if (is_write) { |
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286 mov_rrdisp(code, opts->scratch1, opts->scratch2, (intptr_t)memmap[chunk].buffer, tmp_size); |
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287 } else { |
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288 mov_rdispr(code, opts->scratch1, (intptr_t)memmap[chunk].buffer, opts->scratch1, tmp_size); |
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289 } |
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290 } else { |
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291 if (is_write) { |
760
656b1fded67f
Fix self modifying code checks on platforms like OS X on which guest RAM ends up at an address unreachable with a 32-bit displacement
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292 push_r(code, opts->scratch2); |
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293 mov_ir(code, (intptr_t)memmap[chunk].buffer, opts->scratch2, SZ_PTR); |
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294 add_rdispr(code, RSP, 0, opts->scratch2, SZ_PTR); |
589
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295 mov_rrind(code, opts->scratch1, opts->scratch2, tmp_size); |
760
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296 if (is_write && (memmap[chunk].flags & MMAP_CODE)) { |
2138
b6338e18787e
Fix some dynarec code invalidation issues
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297 need_addr_pop = 1; |
760
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298 } else { |
1511
2a5649a767e7
Fix accidental add to RSP with SZ_D and SZ_PTR. Using SZ_D breakse when the stack is located outside of the 32-bit addressable range
Michael Pavone <pavone@retrodev.com>
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1465
diff
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|
299 add_ir(code, sizeof(void*), RSP, SZ_PTR); |
894
a7774fc2de4b
Partially working change to do proper stack alignment rather than doing a lame alignment check when calling a C compile dfunction. 68K core seems okay, but Z80 is busted.
Michael Pavone <pavone@retrodev.com>
parents:
892
diff
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|
300 code->stack_off -= sizeof(void *); |
760
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Fix self modifying code checks on platforms like OS X on which guest RAM ends up at an address unreachable with a 32-bit displacement
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301 } |
589
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302 } else { |
756
e1dc98f7ed9f
Preserve scratch2 when using it as a temporary in memory read functions. This fixes a bunch of issues with the Z80 core and possibly some issues with the 68K core as well
Michael Pavone <pavone@retrodev.com>
parents:
750
diff
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|
303 push_r(code, opts->scratch2); |
589
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304 mov_ir(code, (intptr_t)memmap[chunk].buffer, opts->scratch2, SZ_PTR); |
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305 mov_rindexr(code, opts->scratch2, opts->scratch1, 1, opts->scratch1, tmp_size); |
756
e1dc98f7ed9f
Preserve scratch2 when using it as a temporary in memory read functions. This fixes a bunch of issues with the Z80 core and possibly some issues with the 68K core as well
Michael Pavone <pavone@retrodev.com>
parents:
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diff
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|
306 pop_r(code, opts->scratch2); |
589
2dde38c1744f
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|
307 } |
2dde38c1744f
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diff
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|
308 } |
2dde38c1744f
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diff
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|
309 if (size != tmp_size && !is_write) { |
2dde38c1744f
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diff
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|
310 if (memmap[chunk].flags & MMAP_ONLY_EVEN) { |
2dde38c1744f
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diff
changeset
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311 shl_ir(code, 8, opts->scratch1, SZ_W); |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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diff
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312 mov_ir(code, 0xFF, opts->scratch1, SZ_B); |
2dde38c1744f
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313 } else { |
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diff
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|
314 or_ir(code, 0xFF00, opts->scratch1, SZ_W); |
2dde38c1744f
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315 } |
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316 } |
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317 } |
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318 if (is_write && (memmap[chunk].flags & MMAP_CODE)) { |
2138
b6338e18787e
Fix some dynarec code invalidation issues
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|
319 if (need_addr_pop) { |
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320 pop_r(code, adr_reg); |
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321 } |
589
2dde38c1744f
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diff
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322 mov_rr(code, opts->scratch2, opts->scratch1, opts->address_size); |
620
9d6fed6501ba
Fix handling of code writes for Z80 core. This seems to get things close to being back to where they were before the big refactor that broke the Z80 core. Some problems remain. Notably the sound driver in Sonic 2 is still quite broken.
Michael Pavone <pavone@retrodev.com>
parents:
604
diff
changeset
|
323 shr_ir(code, opts->ram_flags_shift, opts->scratch1, opts->address_size); |
690
fc04781f4d28
Removed hardcoded assumptions in M68K core about which parts of the memory map are RAM
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
324 bt_rrdisp(code, opts->scratch1, opts->context_reg, ram_flags_off, opts->address_size); |
589
2dde38c1744f
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changeset
|
325 code_ptr not_code = code->cur + 1; |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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|
326 jcc(code, CC_NC, code->cur + 2); |
1084
193db42e702b
Remove hacky assumption about Genesis memory map in M68K core
Michael Pavone <pavone@retrodev.com>
parents:
1081
diff
changeset
|
327 if (memmap[chunk].mask != opts->address_mask) { |
1107
fc125af5e4f1
Fix to the fix of handling of self modifying code. Was ORing the base address with the wrong register before calling the modified code handler
Michael Pavone <pavone@retrodev.com>
parents:
1086
diff
changeset
|
328 or_ir(code, memmap[chunk].start, opts->scratch2, opts->address_size); |
1084
193db42e702b
Remove hacky assumption about Genesis memory map in M68K core
Michael Pavone <pavone@retrodev.com>
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1081
diff
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|
329 } |
589
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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diff
changeset
|
330 call(code, opts->save_context); |
658
6aa29ac33f1a
Use call_args and call_args_abi inside gen_mem_fun
Michael Pavone <pavone@retrodev.com>
parents:
620
diff
changeset
|
331 call_args(code, opts->handle_code_write, 2, opts->scratch2, opts->context_reg); |
589
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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diff
changeset
|
332 mov_rr(code, RAX, opts->context_reg, SZ_PTR); |
1086
f0a1e0a2263c
Made some optimizations to gen_mem_fun to keep the size of chunk handler sections within range of a single byte displacement
Michael Pavone <pavone@retrodev.com>
parents:
1084
diff
changeset
|
333 jmp(code, opts->load_context); |
589
2dde38c1744f
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diff
changeset
|
334 *not_code = code->cur - (not_code+1); |
2dde38c1744f
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diff
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|
335 } |
2dde38c1744f
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diff
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|
336 retn(code); |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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diff
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|
337 } else if (cfun) { |
2dde38c1744f
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diff
changeset
|
338 call(code, opts->save_context); |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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parents:
567
diff
changeset
|
339 if (is_write) { |
658
6aa29ac33f1a
Use call_args and call_args_abi inside gen_mem_fun
Michael Pavone <pavone@retrodev.com>
parents:
620
diff
changeset
|
340 call_args_abi(code, cfun, 3, opts->scratch2, opts->context_reg, opts->scratch1); |
6aa29ac33f1a
Use call_args and call_args_abi inside gen_mem_fun
Michael Pavone <pavone@retrodev.com>
parents:
620
diff
changeset
|
341 mov_rr(code, RAX, opts->context_reg, SZ_PTR); |
589
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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diff
changeset
|
342 } else { |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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parents:
567
diff
changeset
|
343 push_r(code, opts->context_reg); |
658
6aa29ac33f1a
Use call_args and call_args_abi inside gen_mem_fun
Michael Pavone <pavone@retrodev.com>
parents:
620
diff
changeset
|
344 call_args_abi(code, cfun, 2, opts->scratch1, opts->context_reg); |
589
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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567
diff
changeset
|
345 pop_r(code, opts->context_reg); |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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567
diff
changeset
|
346 mov_rr(code, RAX, opts->scratch1, size); |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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diff
changeset
|
347 } |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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parents:
567
diff
changeset
|
348 jmp(code, opts->load_context); |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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diff
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|
349 } else { |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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567
diff
changeset
|
350 //Not sure the best course of action here |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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diff
changeset
|
351 if (!is_write) { |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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567
diff
changeset
|
352 mov_ir(code, size == SZ_B ? 0xFF : 0xFFFF, opts->scratch1, size); |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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diff
changeset
|
353 } |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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567
diff
changeset
|
354 retn(code); |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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567
diff
changeset
|
355 } |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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567
diff
changeset
|
356 if (lb_jcc) { |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
2036
diff
changeset
|
357 if (need_wide_jcc) { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
2036
diff
changeset
|
358 *((int32_t*)lb_jcc) = code->cur - (lb_jcc+4); |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
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2036
diff
changeset
|
359 } else if (code->cur - (lb_jcc+1) > 0x7f) { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
2036
diff
changeset
|
360 need_wide_jcc = 1; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
2036
diff
changeset
|
361 chunk--; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
2036
diff
changeset
|
362 *code = chunk_start; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
2036
diff
changeset
|
363 continue; |
8ee7ecbf3f21
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364 } else { |
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365 *lb_jcc = code->cur - (lb_jcc+1); |
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366 } |
589
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367 lb_jcc = NULL; |
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368 } |
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369 if (ub_jcc) { |
2054
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370 if (need_wide_jcc) { |
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371 *((int32_t*)ub_jcc) = code->cur - (ub_jcc+4); |
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372 } else if (code->cur - (ub_jcc+1) > 0x7f) { |
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373 need_wide_jcc = 1; |
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374 chunk--; |
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375 *code = chunk_start; |
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376 continue; |
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377 } else { |
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378 *ub_jcc = code->cur - (ub_jcc+1); |
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379 } |
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380 |
589
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381 ub_jcc = NULL; |
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382 } |
2070
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383 if (memmap[chunk].flags & MMAP_CODE) { |
2113
0013362c320c
Fix handling of ram code flag offset calculation for ranges that are not an even multiple of the code flag page size
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384 uint32_t size = chunk_size(opts, memmap + chunk); |
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385 uint32_t size_round_mask = (1 << (opts->ram_flags_shift + 3)) - 1; |
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386 if (size & size_round_mask) { |
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387 size &= ~size_round_mask; |
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388 size += size_round_mask + 1; |
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389 } |
2113
0013362c320c
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390 ram_flags_off += size >> (opts->ram_flags_shift + 3); |
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391 } |
2054
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392 if (need_wide_jcc) { |
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393 need_wide_jcc = 0; |
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394 } |
589
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395 } |
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396 if (!is_write) { |
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397 mov_ir(code, size == SZ_B ? 0xFF : 0xFFFF, opts->scratch1, size); |
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398 } |
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399 retn(code); |
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400 return start; |
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401 } |