annotate z80_to_x86.c @ 266:376df762ddf5

Fix some more retranslation bugs in the Z80 core
author Mike Pavone <pavone@retrodev.com>
date Wed, 01 May 2013 23:12:29 -0700
parents 8fd6652e56f8
children 1788e3f29c28
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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1 #include "z80inst.h"
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2 #include "z80_to_x86.h"
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3 #include "gen_x86.h"
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4 #include "mem.h"
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5 #include <stdio.h>
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6 #include <stdlib.h>
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7 #include <stddef.h>
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8 #include <string.h>
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9
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10 #define MODE_UNUSED (MODE_IMMED-1)
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11
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12 #define ZCYCLES RBP
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13 #define ZLIMIT RDI
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14 #define SCRATCH1 R13
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15 #define SCRATCH2 R14
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16 #define CONTEXT RSI
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17
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18 void z80_read_byte();
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19 void z80_read_word();
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20 void z80_write_byte();
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21 void z80_write_word_highfirst();
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22 void z80_write_word_lowfirst();
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23 void z80_save_context();
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24 void z80_native_addr();
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25 void z80_do_sync();
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26 void z80_handle_cycle_limit_int();
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27 void z80_retrans_stub();
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28
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29 uint8_t z80_size(z80inst * inst)
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30 {
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31 uint8_t reg = (inst->reg & 0x1F);
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32 if (reg != Z80_UNUSED && reg != Z80_USE_IMMED) {
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33 return reg < Z80_BC ? SZ_B : SZ_W;
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34 }
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35 //TODO: Handle any necessary special cases
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36 return SZ_B;
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37 }
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38
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39 uint8_t z80_high_reg(uint8_t reg)
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40 {
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41 switch(reg)
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42 {
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43 case Z80_C:
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44 case Z80_BC:
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45 return Z80_B;
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46 case Z80_E:
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47 case Z80_DE:
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48 return Z80_D;
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49 case Z80_L:
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50 case Z80_HL:
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51 return Z80_H;
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52 case Z80_IXL:
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53 case Z80_IX:
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54 return Z80_IXH;
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55 case Z80_IYL:
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56 case Z80_IY:
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57 return Z80_IYH;
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58 default:
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59 return Z80_UNUSED;
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60 }
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61 }
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62
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63 uint8_t * zcycles(uint8_t * dst, uint32_t num_cycles)
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64 {
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65 return add_ir(dst, num_cycles, ZCYCLES, SZ_D);
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66 }
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67
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68 uint8_t * z80_check_cycles_int(uint8_t * dst, uint16_t address)
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69 {
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70 dst = cmp_rr(dst, ZCYCLES, ZLIMIT, SZ_D);
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71 uint8_t * jmp_off = dst+1;
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72 dst = jcc(dst, CC_NC, dst + 7);
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73 dst = mov_ir(dst, address, SCRATCH1, SZ_W);
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74 dst = call(dst, (uint8_t *)z80_handle_cycle_limit_int);
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75 *jmp_off = dst - (jmp_off+1);
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76 return dst;
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77 }
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78
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79 uint8_t * translate_z80_reg(z80inst * inst, x86_ea * ea, uint8_t * dst, x86_z80_options * opts)
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80 {
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81 if (inst->reg == Z80_USE_IMMED) {
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82 ea->mode = MODE_IMMED;
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83 ea->disp = inst->immed;
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84 } else if ((inst->reg & 0x1F) == Z80_UNUSED) {
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85 ea->mode = MODE_UNUSED;
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86 } else {
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87 ea->mode = MODE_REG_DIRECT;
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88 if (inst->reg == Z80_IYH) {
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89 ea->base = opts->regs[Z80_IYL];
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90 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W);
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91 } else if(opts->regs[inst->reg] >= 0) {
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92 ea->base = opts->regs[inst->reg];
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93 } else {
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94 ea->mode = MODE_REG_DISPLACE8;
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95 ea->base = CONTEXT;
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96 ea->disp = offsetof(z80_context, regs) + inst->reg;
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97 }
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98 }
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99 return dst;
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100 }
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101
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102 uint8_t * z80_save_reg(uint8_t * dst, z80inst * inst, x86_z80_options * opts)
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103 {
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104 if (inst->reg == Z80_IYH) {
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105 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W);
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106 }
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107 return dst;
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108 }
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109
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110 uint8_t * translate_z80_ea(z80inst * inst, x86_ea * ea, uint8_t * dst, x86_z80_options * opts, uint8_t read, uint8_t modify)
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111 {
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112 uint8_t size, reg, areg;
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113 ea->mode = MODE_REG_DIRECT;
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114 areg = read ? SCRATCH1 : SCRATCH2;
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115 switch(inst->addr_mode & 0x1F)
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116 {
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117 case Z80_REG:
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118 if (inst->ea_reg == Z80_IYH) {
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
119 ea->base = opts->regs[Z80_IYL];
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff changeset
120 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff changeset
121 } else {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff changeset
122 ea->base = opts->regs[inst->ea_reg];
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff changeset
123 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff changeset
124 break;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
125 case Z80_REG_INDIRECT:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff changeset
126 dst = mov_rr(dst, opts->regs[inst->ea_reg], areg, SZ_W);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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diff changeset
127 size = z80_size(inst);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff changeset
128 if (read) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff changeset
129 if (modify) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff changeset
130 dst = push_r(dst, SCRATCH1);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff changeset
131 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff changeset
132 if (size == SZ_B) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff changeset
133 dst = call(dst, (uint8_t *)z80_read_byte);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff changeset
134 } else {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff changeset
135 dst = call(dst, (uint8_t *)z80_read_word);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff changeset
136 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff changeset
137 if (modify) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff changeset
138 dst = pop_r(dst, SCRATCH2);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff changeset
139 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff changeset
140 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff changeset
141 ea->base = SCRATCH1;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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diff changeset
142 break;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff changeset
143 case Z80_IMMED:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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diff changeset
144 ea->mode = MODE_IMMED;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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diff changeset
145 ea->disp = inst->immed;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff changeset
146 break;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff changeset
147 case Z80_IMMED_INDIRECT:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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diff changeset
148 dst = mov_ir(dst, inst->immed, areg, SZ_W);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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diff changeset
149 size = z80_size(inst);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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diff changeset
150 if (read) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff changeset
151 if (modify) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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diff changeset
152 dst = push_r(dst, SCRATCH1);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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diff changeset
153 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff changeset
154 if (size == SZ_B) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff changeset
155 dst = call(dst, (uint8_t *)z80_read_byte);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff changeset
156 } else {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff changeset
157 dst = call(dst, (uint8_t *)z80_read_word);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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diff changeset
158 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff changeset
159 if (modify) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff changeset
160 dst = pop_r(dst, SCRATCH2);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff changeset
161 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff changeset
162 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff changeset
163 ea->base = SCRATCH1;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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diff changeset
164 break;
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
165 case Z80_IX_DISPLACE:
d9bf8e61c33c Get Z80 core working for simple programs
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parents: 213
diff changeset
166 case Z80_IY_DISPLACE:
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parents: 213
diff changeset
167 reg = opts->regs[inst->addr_mode == Z80_IX_DISPLACE ? Z80_IX : Z80_IY];
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff changeset
168 dst = mov_rr(dst, reg, areg, SZ_W);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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diff changeset
169 dst = add_ir(dst, inst->immed, areg, SZ_W);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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diff changeset
170 size = z80_size(inst);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff changeset
171 if (read) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff changeset
172 if (modify) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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diff changeset
173 dst = push_r(dst, SCRATCH1);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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diff changeset
174 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff changeset
175 if (size == SZ_B) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff changeset
176 dst = call(dst, (uint8_t *)z80_read_byte);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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diff changeset
177 } else {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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diff changeset
178 dst = call(dst, (uint8_t *)z80_read_word);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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diff changeset
179 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff changeset
180 if (modify) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff changeset
181 dst = pop_r(dst, SCRATCH2);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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diff changeset
182 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff changeset
183 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff changeset
184 break;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
185 case Z80_UNUSED:
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
186 ea->mode = MODE_UNUSED;
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff changeset
187 break;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff changeset
188 default:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
189 fprintf(stderr, "Unrecognized Z80 addressing mode %d\n", inst->addr_mode);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff changeset
190 exit(1);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff changeset
191 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff changeset
192 return dst;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff changeset
193 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
194
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
195 uint8_t * z80_save_ea(uint8_t * dst, z80inst * inst, x86_z80_options * opts)
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
196 {
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
197 if (inst->addr_mode == Z80_REG && inst->ea_reg == Z80_IYH) {
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff changeset
198 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff changeset
199 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff changeset
200 return dst;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
201 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
202
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
203 uint8_t * z80_save_result(uint8_t * dst, z80inst * inst)
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
204 {
253
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents: 252
diff changeset
205 switch(inst->addr_mode & 0x1f)
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents: 252
diff changeset
206 {
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents: 252
diff changeset
207 case Z80_REG_INDIRECT:
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
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parents: 252
diff changeset
208 case Z80_IMMED_INDIRECT:
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents: 252
diff changeset
209 case Z80_IX_DISPLACE:
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents: 252
diff changeset
210 case Z80_IY_DISPLACE:
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents: 252
diff changeset
211 if (z80_size(inst) == SZ_B) {
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
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parents: 252
diff changeset
212 dst = call(dst, (uint8_t *)z80_write_byte);
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents: 252
diff changeset
213 } else {
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents: 252
diff changeset
214 dst = call(dst, (uint8_t *)z80_write_word_lowfirst);
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents: 252
diff changeset
215 }
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
216 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
217 return dst;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
218 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
219
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
220 enum {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
221 DONT_READ=0,
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
222 READ
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
223 };
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
224
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
225 enum {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
226 DONT_MODIFY=0,
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
227 MODIFY
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
228 };
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
229
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
230 uint8_t zf_off(uint8_t flag)
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
231 {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
232 return offsetof(z80_context, flags) + flag;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
233 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
234
241
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
235 uint8_t zaf_off(uint8_t flag)
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
236 {
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
237 return offsetof(z80_context, alt_flags) + flag;
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
238 }
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
239
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
240 uint8_t zar_off(uint8_t reg)
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
241 {
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
242 return offsetof(z80_context, alt_regs) + reg;
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
243 }
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
244
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
245 void z80_print_regs_exit(z80_context * context)
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
246 {
243
2f069a0b487e Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 242
diff changeset
247 printf("A: %X\nB: %X\nC: %X\nD: %X\nE: %X\nHL: %X\nIX: %X\nIY: %X\nSP: %X\n\nIM: %d, IFF1: %d, IFF2: %d\n",
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
248 context->regs[Z80_A], context->regs[Z80_B], context->regs[Z80_C],
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
249 context->regs[Z80_D], context->regs[Z80_E],
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
250 (context->regs[Z80_H] << 8) | context->regs[Z80_L],
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
251 (context->regs[Z80_IXH] << 8) | context->regs[Z80_IXL],
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
252 (context->regs[Z80_IYH] << 8) | context->regs[Z80_IYL],
243
2f069a0b487e Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 242
diff changeset
253 context->sp, context->im, context->iff1, context->iff2);
241
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
254 puts("--Alternate Regs--");
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
255 printf("A: %X\nB: %X\nC: %X\nD: %X\nE: %X\nHL: %X\nIX: %X\nIY: %X\n",
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
256 context->alt_regs[Z80_A], context->alt_regs[Z80_B], context->alt_regs[Z80_C],
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
257 context->alt_regs[Z80_D], context->alt_regs[Z80_E],
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
258 (context->alt_regs[Z80_H] << 8) | context->alt_regs[Z80_L],
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
259 (context->alt_regs[Z80_IXH] << 8) | context->alt_regs[Z80_IXL],
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
260 (context->alt_regs[Z80_IYH] << 8) | context->alt_regs[Z80_IYL]);
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
261 exit(0);
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
262 }
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
263
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
264 uint8_t * translate_z80inst(z80inst * inst, uint8_t * dst, z80_context * context, uint16_t address)
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
265 {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
266 uint32_t cycles;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
267 x86_ea src_op, dst_op;
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
268 uint8_t size;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
269 x86_z80_options *opts = context->options;
261
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write
Mike Pavone <pavone@retrodev.com>
parents: 259
diff changeset
270 uint8_t * start = dst;
250
5f1b68cecfc7 Implemented basic interrupt support in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents: 248
diff changeset
271 dst = z80_check_cycles_int(dst, address);
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
272 switch(inst->op)
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
273 {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
274 case Z80_LD:
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
275 size = z80_size(inst);
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
276 switch (inst->addr_mode & 0x1F)
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
277 {
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
278 case Z80_REG:
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
279 case Z80_REG_INDIRECT:
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
280 cycles = size == SZ_B ? 4 : 6;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
281 if (inst->ea_reg == Z80_IX || inst->ea_reg == Z80_IY) {
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
282 cycles += 4;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
283 }
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
284 break;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
285 case Z80_IMMED:
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
286 cycles = size == SZ_B ? 7 : 10;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
287 break;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
288 case Z80_IMMED_INDIRECT:
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
289 cycles = 10;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
290 break;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
291 case Z80_IX_DISPLACE:
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
292 case Z80_IY_DISPLACE:
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
293 cycles = 12;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
294 break;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
295 }
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
296 if ((inst->reg >= Z80_IXL && inst->reg <= Z80_IYH) || inst->reg == Z80_IX || inst->reg == Z80_IY) {
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
297 cycles += 4;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
298 }
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
299 dst = zcycles(dst, cycles);
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
300 if (inst->addr_mode & Z80_DIR) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
301 dst = translate_z80_reg(inst, &src_op, dst, opts);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
302 dst = translate_z80_ea(inst, &dst_op, dst, opts, DONT_READ, MODIFY);
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
303 } else {
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
304 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY);
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
305 dst = translate_z80_reg(inst, &dst_op, dst, opts);
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
306 }
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
307 if (src_op.mode == MODE_REG_DIRECT) {
262
d97c9eca49f4 Implement ld to and from the I and R registers
Mike Pavone <pavone@retrodev.com>
parents: 261
diff changeset
308 if(dst_op.mode == MODE_REG_DISPLACE8) {
d97c9eca49f4 Implement ld to and from the I and R registers
Mike Pavone <pavone@retrodev.com>
parents: 261
diff changeset
309 dst = mov_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, size);
d97c9eca49f4 Implement ld to and from the I and R registers
Mike Pavone <pavone@retrodev.com>
parents: 261
diff changeset
310 } else {
d97c9eca49f4 Implement ld to and from the I and R registers
Mike Pavone <pavone@retrodev.com>
parents: 261
diff changeset
311 dst = mov_rr(dst, src_op.base, dst_op.base, size);
d97c9eca49f4 Implement ld to and from the I and R registers
Mike Pavone <pavone@retrodev.com>
parents: 261
diff changeset
312 }
d97c9eca49f4 Implement ld to and from the I and R registers
Mike Pavone <pavone@retrodev.com>
parents: 261
diff changeset
313 } else if(src_op.mode == MODE_IMMED) {
d97c9eca49f4 Implement ld to and from the I and R registers
Mike Pavone <pavone@retrodev.com>
parents: 261
diff changeset
314 dst = mov_ir(dst, src_op.disp, dst_op.base, size);
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
315 } else {
262
d97c9eca49f4 Implement ld to and from the I and R registers
Mike Pavone <pavone@retrodev.com>
parents: 261
diff changeset
316 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, size);
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
317 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
318 dst = z80_save_reg(dst, inst, opts);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
319 dst = z80_save_ea(dst, inst, opts);
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
320 if (inst->addr_mode & Z80_DIR) {
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
321 dst = z80_save_result(dst, inst);
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
322 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
323 break;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
324 case Z80_PUSH:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
325 dst = zcycles(dst, (inst->reg == Z80_IX || inst->reg == Z80_IY) ? 9 : 5);
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
326 dst = sub_ir(dst, 2, opts->regs[Z80_SP], SZ_W);
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
327 if (inst->reg == Z80_AF) {
253
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents: 252
diff changeset
328 dst = mov_rdisp8r(dst, CONTEXT, zf_off(ZF_S), SCRATCH1, SZ_B);
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents: 252
diff changeset
329 dst = shl_ir(dst, 1, SCRATCH1, SZ_B);
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents: 252
diff changeset
330 dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_Z), SCRATCH1, SZ_B);
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents: 252
diff changeset
331 dst = shl_ir(dst, 2, SCRATCH1, SZ_B);
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents: 252
diff changeset
332 dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_H), SCRATCH1, SZ_B);
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents: 252
diff changeset
333 dst = shl_ir(dst, 2, SCRATCH1, SZ_B);
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents: 252
diff changeset
334 dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_PV), SCRATCH1, SZ_B);
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents: 252
diff changeset
335 dst = shl_ir(dst, 1, SCRATCH1, SZ_B);
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents: 252
diff changeset
336 dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_N), SCRATCH1, SZ_B);
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents: 252
diff changeset
337 dst = shl_ir(dst, 1, SCRATCH1, SZ_B);
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents: 252
diff changeset
338 dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_C), SCRATCH1, SZ_B);
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents: 252
diff changeset
339 dst = shl_ir(dst, 8, SCRATCH1, SZ_W);
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents: 252
diff changeset
340 dst = mov_rr(dst, opts->regs[Z80_A], SCRATCH1, SZ_B);
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
341 } else {
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
342 dst = translate_z80_reg(inst, &src_op, dst, opts);
253
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents: 252
diff changeset
343 dst = mov_rr(dst, src_op.base, SCRATCH1, SZ_W);
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
344 }
253
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents: 252
diff changeset
345 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W);
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
346 dst = call(dst, (uint8_t *)z80_write_word_highfirst);
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
347 //no call to save_z80_reg needed since there's no chance we'll use the only
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
348 //the upper half of a register pair
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
349 break;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
350 case Z80_POP:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
351 dst = zcycles(dst, (inst->reg == Z80_IX || inst->reg == Z80_IY) ? 8 : 4);
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
352 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W);
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
353 dst = call(dst, (uint8_t *)z80_read_word);
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
354 dst = add_ir(dst, 2, opts->regs[Z80_SP], SZ_W);
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
355 if (inst->reg == Z80_AF) {
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
356 dst = mov_rr(dst, SCRATCH1, opts->regs[Z80_A], SZ_B);
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
357 dst = bt_ir(dst, 8, SCRATCH1, SZ_W);
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
358 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C));
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
359 dst = bt_ir(dst, 9, SCRATCH1, SZ_W);
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
360 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_N));
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
361 dst = bt_ir(dst, 10, SCRATCH1, SZ_W);
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
362 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_PV));
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
363 dst = bt_ir(dst, 12, SCRATCH1, SZ_W);
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
364 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_H));
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
365 dst = bt_ir(dst, 14, SCRATCH1, SZ_W);
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
366 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_Z));
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
367 dst = bt_ir(dst, 15, SCRATCH1, SZ_W);
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
368 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_S));
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
369 } else {
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
370 dst = translate_z80_reg(inst, &src_op, dst, opts);
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
371 dst = mov_rr(dst, SCRATCH1, src_op.base, SZ_W);
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
372 }
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
373 //no call to save_z80_reg needed since there's no chance we'll use the only
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
374 //the upper half of a register pair
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
375 break;
241
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
376 case Z80_EX:
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
377 if (inst->addr_mode == Z80_REG || inst->reg == Z80_HL) {
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
378 cycles = 4;
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
379 } else {
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
380 cycles = 8;
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
381 }
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
382 dst = zcycles(dst, cycles);
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
383 if (inst->addr_mode == Z80_REG) {
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
384 if(inst->reg == Z80_AF) {
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
385 dst = mov_rr(dst, opts->regs[Z80_A], SCRATCH1, SZ_B);
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
386 dst = mov_rdisp8r(dst, CONTEXT, zar_off(Z80_A), opts->regs[Z80_A], SZ_B);
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
387 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, zar_off(Z80_A), SZ_B);
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
388
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
389 //Flags are currently word aligned, so we can move
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
390 //them efficiently a word at a time
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
391 for (int f = ZF_C; f < ZF_NUM; f+=2) {
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
392 dst = mov_rdisp8r(dst, CONTEXT, zf_off(f), SCRATCH1, SZ_W);
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
393 dst = mov_rdisp8r(dst, CONTEXT, zaf_off(f), SCRATCH2, SZ_W);
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
394 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, zaf_off(f), SZ_W);
253
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents: 252
diff changeset
395 dst = mov_rrdisp8(dst, SCRATCH2, CONTEXT, zf_off(f), SZ_W);
241
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
396 }
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
397 } else {
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
398 dst = xchg_rr(dst, opts->regs[Z80_DE], opts->regs[Z80_HL], SZ_W);
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
399 }
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
400 } else {
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
401 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W);
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
402 dst = call(dst, (uint8_t *)z80_read_byte);
253
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents: 252
diff changeset
403 dst = xchg_rr(dst, opts->regs[inst->reg], SCRATCH1, SZ_B);
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents: 252
diff changeset
404 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W);
241
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
405 dst = call(dst, (uint8_t *)z80_write_byte);
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
406 dst = zcycles(dst, 1);
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
407 uint8_t high_reg = z80_high_reg(inst->reg);
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
408 uint8_t use_reg;
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
409 //even though some of the upper halves can be used directly
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
410 //the limitations on mixing *H regs with the REX prefix
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
411 //prevent us from taking advantage of it
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
412 use_reg = opts->regs[inst->reg];
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
413 dst = ror_ir(dst, 8, use_reg, SZ_W);
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
414 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W);
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
415 dst = add_ir(dst, 1, SCRATCH1, SZ_W);
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
416 dst = call(dst, (uint8_t *)z80_read_byte);
253
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents: 252
diff changeset
417 dst = xchg_rr(dst, use_reg, SCRATCH1, SZ_B);
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents: 252
diff changeset
418 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W);
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents: 252
diff changeset
419 dst = add_ir(dst, 1, SCRATCH2, SZ_W);
241
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
420 dst = call(dst, (uint8_t *)z80_write_byte);
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
421 //restore reg to normal rotation
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
422 dst = ror_ir(dst, 8, use_reg, SZ_W);
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
423 dst = zcycles(dst, 2);
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
424 }
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
425 break;
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
426 case Z80_EXX:
241
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
427 dst = zcycles(dst, 4);
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
428 dst = mov_rr(dst, opts->regs[Z80_BC], SCRATCH1, SZ_W);
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
429 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH2, SZ_W);
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
430 dst = mov_rdisp8r(dst, CONTEXT, zar_off(Z80_C), opts->regs[Z80_BC], SZ_W);
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
431 dst = mov_rdisp8r(dst, CONTEXT, zar_off(Z80_L), opts->regs[Z80_HL], SZ_W);
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
432 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, zar_off(Z80_C), SZ_W);
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
433 dst = mov_rrdisp8(dst, SCRATCH2, CONTEXT, zar_off(Z80_L), SZ_W);
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
434 dst = mov_rr(dst, opts->regs[Z80_DE], SCRATCH1, SZ_W);
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
435 dst = mov_rdisp8r(dst, CONTEXT, zar_off(Z80_E), opts->regs[Z80_DE], SZ_W);
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
436 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, zar_off(Z80_E), SZ_W);
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
437 break;
261
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write
Mike Pavone <pavone@retrodev.com>
parents: 259
diff changeset
438 //case Z80_LDI:
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write
Mike Pavone <pavone@retrodev.com>
parents: 259
diff changeset
439 case Z80_LDIR: {
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write
Mike Pavone <pavone@retrodev.com>
parents: 259
diff changeset
440 dst = zcycles(dst, 8);
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write
Mike Pavone <pavone@retrodev.com>
parents: 259
diff changeset
441 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH1, SZ_W);
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write
Mike Pavone <pavone@retrodev.com>
parents: 259
diff changeset
442 dst = call(dst, (uint8_t *)z80_read_byte);
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write
Mike Pavone <pavone@retrodev.com>
parents: 259
diff changeset
443 dst = mov_rr(dst, opts->regs[Z80_DE], SCRATCH2, SZ_W);
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write
Mike Pavone <pavone@retrodev.com>
parents: 259
diff changeset
444 dst = call(dst, (uint8_t *)z80_read_byte);
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write
Mike Pavone <pavone@retrodev.com>
parents: 259
diff changeset
445 dst = add_ir(dst, 1, opts->regs[Z80_DE], SZ_W);
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write
Mike Pavone <pavone@retrodev.com>
parents: 259
diff changeset
446 dst = add_ir(dst, 1, opts->regs[Z80_HL], SZ_W);
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write
Mike Pavone <pavone@retrodev.com>
parents: 259
diff changeset
447
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write
Mike Pavone <pavone@retrodev.com>
parents: 259
diff changeset
448 dst = sub_ir(dst, 1, opts->regs[Z80_BC], SZ_W);
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write
Mike Pavone <pavone@retrodev.com>
parents: 259
diff changeset
449 uint8_t * cont = dst+1;
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write
Mike Pavone <pavone@retrodev.com>
parents: 259
diff changeset
450 dst = jcc(dst, CC_Z, dst+2);
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write
Mike Pavone <pavone@retrodev.com>
parents: 259
diff changeset
451 dst = zcycles(dst, 7);
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write
Mike Pavone <pavone@retrodev.com>
parents: 259
diff changeset
452 //TODO: Figure out what the flag state should be here
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write
Mike Pavone <pavone@retrodev.com>
parents: 259
diff changeset
453 //TODO: Figure out whether an interrupt can interrupt this
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write
Mike Pavone <pavone@retrodev.com>
parents: 259
diff changeset
454 dst = jmp(dst, start);
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write
Mike Pavone <pavone@retrodev.com>
parents: 259
diff changeset
455 *cont = dst - (cont + 1);
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write
Mike Pavone <pavone@retrodev.com>
parents: 259
diff changeset
456 dst = zcycles(dst, 2);
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write
Mike Pavone <pavone@retrodev.com>
parents: 259
diff changeset
457 //TODO: Implement half-carry
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write
Mike Pavone <pavone@retrodev.com>
parents: 259
diff changeset
458 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B);
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write
Mike Pavone <pavone@retrodev.com>
parents: 259
diff changeset
459 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_PV), SZ_B);
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write
Mike Pavone <pavone@retrodev.com>
parents: 259
diff changeset
460 break;
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write
Mike Pavone <pavone@retrodev.com>
parents: 259
diff changeset
461 }
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write
Mike Pavone <pavone@retrodev.com>
parents: 259
diff changeset
462 /*case Z80_LDD:
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
463 case Z80_LDDR:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
464 case Z80_CPI:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
465 case Z80_CPIR:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
466 case Z80_CPD:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
467 case Z80_CPDR:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
468 break;*/
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
469 case Z80_ADD:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
470 cycles = 4;
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
471 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) {
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
472 cycles += 12;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
473 } else if(inst->addr_mode == Z80_IMMED) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
474 cycles += 3;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
475 } else if(z80_size(inst) == SZ_W) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
476 cycles += 4;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
477 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
478 dst = zcycles(dst, cycles);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
479 dst = translate_z80_reg(inst, &dst_op, dst, opts);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
480 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
481 if (src_op.mode == MODE_REG_DIRECT) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
482 dst = add_rr(dst, src_op.base, dst_op.base, z80_size(inst));
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
483 } else {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
484 dst = add_ir(dst, src_op.disp, dst_op.base, z80_size(inst));
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
485 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
486 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C));
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
487 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B);
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
488 //TODO: Implement half-carry flag
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
489 if (z80_size(inst) == SZ_B) {
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
490 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV));
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
491 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z));
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
492 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S));
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
493 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
494 dst = z80_save_reg(dst, inst, opts);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
495 dst = z80_save_ea(dst, inst, opts);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
496 break;
248
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
497 case Z80_ADC:
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
498 cycles = 4;
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
499 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) {
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
500 cycles += 12;
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
501 } else if(inst->addr_mode == Z80_IMMED) {
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
502 cycles += 3;
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
503 } else if(z80_size(inst) == SZ_W) {
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
504 cycles += 4;
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
505 }
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
506 dst = zcycles(dst, cycles);
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
507 dst = translate_z80_reg(inst, &dst_op, dst, opts);
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
508 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY);
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
509 if (src_op.mode == MODE_REG_DIRECT) {
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
510 dst = adc_rr(dst, src_op.base, dst_op.base, z80_size(inst));
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
511 } else {
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
512 dst = adc_ir(dst, src_op.disp, dst_op.base, z80_size(inst));
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
513 }
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
514 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C));
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
515 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B);
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
516 //TODO: Implement half-carry flag
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
517 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV));
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
518 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z));
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
519 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S));
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
520 dst = z80_save_reg(dst, inst, opts);
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
521 dst = z80_save_ea(dst, inst, opts);
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
522 break;
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
523 case Z80_SUB:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
524 cycles = 4;
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
525 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) {
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
526 cycles += 12;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
527 } else if(inst->addr_mode == Z80_IMMED) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
528 cycles += 3;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
529 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
530 dst = zcycles(dst, cycles);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
531 dst = translate_z80_reg(inst, &dst_op, dst, opts);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
532 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
533 if (src_op.mode == MODE_REG_DIRECT) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
534 dst = sub_rr(dst, src_op.base, dst_op.base, z80_size(inst));
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
535 } else {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
536 dst = sub_ir(dst, src_op.disp, dst_op.base, z80_size(inst));
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
537 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
538 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C));
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
539 dst = mov_irdisp8(dst, 1, CONTEXT, zf_off(ZF_N), SZ_B);
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
540 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV));
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
541 //TODO: Implement half-carry flag
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
542 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z));
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
543 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S));
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
544 dst = z80_save_reg(dst, inst, opts);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
545 dst = z80_save_ea(dst, inst, opts);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
546 break;
248
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
547 case Z80_SBC:
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
548 cycles = 4;
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
549 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) {
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
550 cycles += 12;
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
551 } else if(inst->addr_mode == Z80_IMMED) {
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
552 cycles += 3;
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
553 } else if(z80_size(inst) == SZ_W) {
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
554 cycles += 4;
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
555 }
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
556 dst = zcycles(dst, cycles);
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
557 dst = translate_z80_reg(inst, &dst_op, dst, opts);
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
558 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY);
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
559 if (src_op.mode == MODE_REG_DIRECT) {
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
560 dst = sbb_rr(dst, src_op.base, dst_op.base, z80_size(inst));
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
561 } else {
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
562 dst = sbb_ir(dst, src_op.disp, dst_op.base, z80_size(inst));
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
563 }
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
564 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C));
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
565 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B);
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
566 //TODO: Implement half-carry flag
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
567 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV));
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
568 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z));
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
569 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S));
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
570 dst = z80_save_reg(dst, inst, opts);
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
571 dst = z80_save_ea(dst, inst, opts);
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
572 break;
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
573 case Z80_AND:
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
574 cycles = 4;
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
575 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) {
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
576 cycles += 12;
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
577 } else if(inst->addr_mode == Z80_IMMED) {
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
578 cycles += 3;
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
579 } else if(z80_size(inst) == SZ_W) {
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
580 cycles += 4;
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
581 }
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
582 dst = zcycles(dst, cycles);
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
583 dst = translate_z80_reg(inst, &dst_op, dst, opts);
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
584 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY);
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
585 if (src_op.mode == MODE_REG_DIRECT) {
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
586 dst = and_rr(dst, src_op.base, dst_op.base, z80_size(inst));
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
587 } else {
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
588 dst = and_ir(dst, src_op.disp, dst_op.base, z80_size(inst));
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
589 }
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
590 //TODO: Cleanup flags
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
591 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C));
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
592 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B);
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
593 //TODO: Implement half-carry flag
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
594 if (z80_size(inst) == SZ_B) {
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
595 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV));
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
596 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z));
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
597 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S));
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
598 }
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
599 dst = z80_save_reg(dst, inst, opts);
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
600 dst = z80_save_ea(dst, inst, opts);
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
601 break;
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
602 case Z80_OR:
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
603 cycles = 4;
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
604 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) {
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
605 cycles += 12;
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
606 } else if(inst->addr_mode == Z80_IMMED) {
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
607 cycles += 3;
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
608 } else if(z80_size(inst) == SZ_W) {
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
609 cycles += 4;
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
610 }
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
611 dst = zcycles(dst, cycles);
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
612 dst = translate_z80_reg(inst, &dst_op, dst, opts);
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
613 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY);
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
614 if (src_op.mode == MODE_REG_DIRECT) {
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
615 dst = or_rr(dst, src_op.base, dst_op.base, z80_size(inst));
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
616 } else {
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
617 dst = or_ir(dst, src_op.disp, dst_op.base, z80_size(inst));
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
618 }
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
619 //TODO: Cleanup flags
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
620 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C));
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
621 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B);
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
622 //TODO: Implement half-carry flag
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
623 if (z80_size(inst) == SZ_B) {
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
624 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV));
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
625 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z));
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
626 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S));
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
627 }
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
628 dst = z80_save_reg(dst, inst, opts);
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
629 dst = z80_save_ea(dst, inst, opts);
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
630 break;
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
631 case Z80_XOR:
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
632 cycles = 4;
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
633 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) {
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
634 cycles += 12;
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
635 } else if(inst->addr_mode == Z80_IMMED) {
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
636 cycles += 3;
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
637 } else if(z80_size(inst) == SZ_W) {
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
638 cycles += 4;
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
639 }
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
640 dst = zcycles(dst, cycles);
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
641 dst = translate_z80_reg(inst, &dst_op, dst, opts);
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
642 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY);
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
643 if (src_op.mode == MODE_REG_DIRECT) {
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
644 dst = add_rr(dst, src_op.base, dst_op.base, z80_size(inst));
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
645 } else {
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
646 dst = add_ir(dst, src_op.disp, dst_op.base, z80_size(inst));
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
647 }
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
648 //TODO: Cleanup flags
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
649 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C));
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
650 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B);
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
651 //TODO: Implement half-carry flag
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
652 if (z80_size(inst) == SZ_B) {
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
653 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV));
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
654 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z));
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
655 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S));
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
656 }
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
657 dst = z80_save_reg(dst, inst, opts);
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
658 dst = z80_save_ea(dst, inst, opts);
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
659 break;
242
d3b84b2a4397 Implemente CP (untested)
Mike Pavone <pavone@retrodev.com>
parents: 241
diff changeset
660 case Z80_CP:
d3b84b2a4397 Implemente CP (untested)
Mike Pavone <pavone@retrodev.com>
parents: 241
diff changeset
661 cycles = 4;
d3b84b2a4397 Implemente CP (untested)
Mike Pavone <pavone@retrodev.com>
parents: 241
diff changeset
662 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) {
d3b84b2a4397 Implemente CP (untested)
Mike Pavone <pavone@retrodev.com>
parents: 241
diff changeset
663 cycles += 12;
d3b84b2a4397 Implemente CP (untested)
Mike Pavone <pavone@retrodev.com>
parents: 241
diff changeset
664 } else if(inst->addr_mode == Z80_IMMED) {
d3b84b2a4397 Implemente CP (untested)
Mike Pavone <pavone@retrodev.com>
parents: 241
diff changeset
665 cycles += 3;
d3b84b2a4397 Implemente CP (untested)
Mike Pavone <pavone@retrodev.com>
parents: 241
diff changeset
666 }
d3b84b2a4397 Implemente CP (untested)
Mike Pavone <pavone@retrodev.com>
parents: 241
diff changeset
667 dst = zcycles(dst, cycles);
d3b84b2a4397 Implemente CP (untested)
Mike Pavone <pavone@retrodev.com>
parents: 241
diff changeset
668 dst = translate_z80_reg(inst, &dst_op, dst, opts);
d3b84b2a4397 Implemente CP (untested)
Mike Pavone <pavone@retrodev.com>
parents: 241
diff changeset
669 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY);
d3b84b2a4397 Implemente CP (untested)
Mike Pavone <pavone@retrodev.com>
parents: 241
diff changeset
670 if (src_op.mode == MODE_REG_DIRECT) {
d3b84b2a4397 Implemente CP (untested)
Mike Pavone <pavone@retrodev.com>
parents: 241
diff changeset
671 dst = cmp_rr(dst, src_op.base, dst_op.base, z80_size(inst));
d3b84b2a4397 Implemente CP (untested)
Mike Pavone <pavone@retrodev.com>
parents: 241
diff changeset
672 } else {
d3b84b2a4397 Implemente CP (untested)
Mike Pavone <pavone@retrodev.com>
parents: 241
diff changeset
673 dst = cmp_ir(dst, src_op.disp, dst_op.base, z80_size(inst));
d3b84b2a4397 Implemente CP (untested)
Mike Pavone <pavone@retrodev.com>
parents: 241
diff changeset
674 }
d3b84b2a4397 Implemente CP (untested)
Mike Pavone <pavone@retrodev.com>
parents: 241
diff changeset
675 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C));
d3b84b2a4397 Implemente CP (untested)
Mike Pavone <pavone@retrodev.com>
parents: 241
diff changeset
676 dst = mov_irdisp8(dst, 1, CONTEXT, zf_off(ZF_N), SZ_B);
d3b84b2a4397 Implemente CP (untested)
Mike Pavone <pavone@retrodev.com>
parents: 241
diff changeset
677 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV));
d3b84b2a4397 Implemente CP (untested)
Mike Pavone <pavone@retrodev.com>
parents: 241
diff changeset
678 //TODO: Implement half-carry flag
d3b84b2a4397 Implemente CP (untested)
Mike Pavone <pavone@retrodev.com>
parents: 241
diff changeset
679 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z));
d3b84b2a4397 Implemente CP (untested)
Mike Pavone <pavone@retrodev.com>
parents: 241
diff changeset
680 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S));
d3b84b2a4397 Implemente CP (untested)
Mike Pavone <pavone@retrodev.com>
parents: 241
diff changeset
681 dst = z80_save_reg(dst, inst, opts);
d3b84b2a4397 Implemente CP (untested)
Mike Pavone <pavone@retrodev.com>
parents: 241
diff changeset
682 dst = z80_save_ea(dst, inst, opts);
d3b84b2a4397 Implemente CP (untested)
Mike Pavone <pavone@retrodev.com>
parents: 241
diff changeset
683 break;
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
684 case Z80_INC:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
685 cycles = 4;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
686 if (inst->reg == Z80_IX || inst->reg == Z80_IY) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
687 cycles += 6;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
688 } else if(z80_size(inst) == SZ_W) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
689 cycles += 2;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
690 } else if(inst->reg == Z80_IXH || inst->reg == Z80_IXL || inst->reg == Z80_IYH || inst->reg == Z80_IYL || inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
691 cycles += 4;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
692 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
693 dst = translate_z80_reg(inst, &dst_op, dst, opts);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
694 if (dst_op.mode == MODE_UNUSED) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
695 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
696 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
697 dst = add_ir(dst, 1, dst_op.base, z80_size(inst));
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
698 if (z80_size(inst) == SZ_B) {
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
699 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B);
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
700 //TODO: Implement half-carry flag
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
701 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV));
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
702 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z));
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
703 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S));
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
704 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
705 dst = z80_save_reg(dst, inst, opts);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
706 dst = z80_save_ea(dst, inst, opts);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
707 break;
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
708 case Z80_DEC:
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
709 cycles = 4;
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
710 if (inst->reg == Z80_IX || inst->reg == Z80_IY) {
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
711 cycles += 6;
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
712 } else if(z80_size(inst) == SZ_W) {
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
713 cycles += 2;
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
714 } else if(inst->reg == Z80_IXH || inst->reg == Z80_IXL || inst->reg == Z80_IYH || inst->reg == Z80_IYL || inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) {
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
715 cycles += 4;
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
716 }
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
717 dst = translate_z80_reg(inst, &dst_op, dst, opts);
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
718 if (dst_op.mode == MODE_UNUSED) {
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
719 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY);
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
720 }
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
721 dst = sub_ir(dst, 1, dst_op.base, z80_size(inst));
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
722 if (z80_size(inst) == SZ_B) {
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
723 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B);
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
724 //TODO: Implement half-carry flag
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
725 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV));
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
726 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z));
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
727 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S));
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
728 }
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
729 dst = z80_save_reg(dst, inst, opts);
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
730 dst = z80_save_ea(dst, inst, opts);
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
731 break;
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
732 /*case Z80_DAA:
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
733 case Z80_CPL:
257
4c7933444df4 Implement CCF and SCF
Mike Pavone <pavone@retrodev.com>
parents: 255
diff changeset
734 case Z80_NEG:*/
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
735 case Z80_CCF:
257
4c7933444df4 Implement CCF and SCF
Mike Pavone <pavone@retrodev.com>
parents: 255
diff changeset
736 dst = zcycles(dst, 4);
4c7933444df4 Implement CCF and SCF
Mike Pavone <pavone@retrodev.com>
parents: 255
diff changeset
737 dst = xor_irdisp8(dst, 1, CONTEXT, zf_off(ZF_C), SZ_B);
4c7933444df4 Implement CCF and SCF
Mike Pavone <pavone@retrodev.com>
parents: 255
diff changeset
738 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B);
4c7933444df4 Implement CCF and SCF
Mike Pavone <pavone@retrodev.com>
parents: 255
diff changeset
739 //TODO: Implement half-carry flag
4c7933444df4 Implement CCF and SCF
Mike Pavone <pavone@retrodev.com>
parents: 255
diff changeset
740 break;
4c7933444df4 Implement CCF and SCF
Mike Pavone <pavone@retrodev.com>
parents: 255
diff changeset
741 case Z80_SCF:
4c7933444df4 Implement CCF and SCF
Mike Pavone <pavone@retrodev.com>
parents: 255
diff changeset
742 dst = zcycles(dst, 4);
4c7933444df4 Implement CCF and SCF
Mike Pavone <pavone@retrodev.com>
parents: 255
diff changeset
743 dst = mov_irdisp8(dst, 1, CONTEXT, zf_off(ZF_C), SZ_B);
4c7933444df4 Implement CCF and SCF
Mike Pavone <pavone@retrodev.com>
parents: 255
diff changeset
744 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B);
4c7933444df4 Implement CCF and SCF
Mike Pavone <pavone@retrodev.com>
parents: 255
diff changeset
745 //TODO: Implement half-carry flag
4c7933444df4 Implement CCF and SCF
Mike Pavone <pavone@retrodev.com>
parents: 255
diff changeset
746 break;
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
747 case Z80_NOP:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
748 if (inst->immed == 42) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
749 dst = call(dst, (uint8_t *)z80_save_context);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
750 dst = mov_rr(dst, CONTEXT, RDI, SZ_Q);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
751 dst = jmp(dst, (uint8_t *)z80_print_regs_exit);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
752 } else {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
753 dst = zcycles(dst, 4 * inst->immed);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
754 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
755 break;
243
2f069a0b487e Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 242
diff changeset
756 //case Z80_HALT:
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
757 case Z80_DI:
243
2f069a0b487e Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 242
diff changeset
758 dst = zcycles(dst, 4);
2f069a0b487e Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 242
diff changeset
759 dst = mov_irdisp8(dst, 0, CONTEXT, offsetof(z80_context, iff1), SZ_B);
2f069a0b487e Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 242
diff changeset
760 dst = mov_irdisp8(dst, 0, CONTEXT, offsetof(z80_context, iff2), SZ_B);
250
5f1b68cecfc7 Implemented basic interrupt support in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents: 248
diff changeset
761 dst = mov_rdisp8r(dst, CONTEXT, offsetof(z80_context, sync_cycle), ZLIMIT, SZ_D);
243
2f069a0b487e Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 242
diff changeset
762 break;
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
763 case Z80_EI:
243
2f069a0b487e Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 242
diff changeset
764 //TODO: Implement interrupt enable latency of 1 instruction afer EI
2f069a0b487e Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 242
diff changeset
765 dst = zcycles(dst, 4);
2f069a0b487e Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 242
diff changeset
766 dst = mov_irdisp8(dst, 1, CONTEXT, offsetof(z80_context, iff1), SZ_B);
2f069a0b487e Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 242
diff changeset
767 dst = mov_irdisp8(dst, 1, CONTEXT, offsetof(z80_context, iff2), SZ_B);
250
5f1b68cecfc7 Implemented basic interrupt support in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents: 248
diff changeset
768 dst = call(dst, (uint8_t *)z80_do_sync);
243
2f069a0b487e Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 242
diff changeset
769 break;
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
770 case Z80_IM:
243
2f069a0b487e Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 242
diff changeset
771 dst = zcycles(dst, 4);
2f069a0b487e Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 242
diff changeset
772 dst = mov_irdisp8(dst, inst->immed, CONTEXT, offsetof(z80_context, im), SZ_B);
2f069a0b487e Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 242
diff changeset
773 break;
247
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
774 case Z80_RLC:
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
775 cycles = inst->immed == 1 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8);
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
776 dst = zcycles(dst, cycles);
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
777 if (inst->reg == Z80_UNUSED) {
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
778 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY);
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
779 dst = zcycles(dst, 1);
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
780 } else {
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
781 dst = translate_z80_reg(inst, &dst_op, dst, opts);
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
782 }
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
783 dst = rol_ir(dst, 1, dst_op.base, SZ_B);
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
784 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C));
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
785 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B);
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
786 //TODO: Implement half-carry flag
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
787 dst = cmp_ir(dst, 0, dst_op.base, SZ_B);
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
788 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV));
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
789 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z));
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
790 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S));
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
791 if (inst->reg == Z80_UNUSED) {
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
792 dst = z80_save_result(dst, inst);
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
793 } else {
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
794 dst = z80_save_reg(dst, inst, opts);
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
795 }
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
796 break;
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
797 case Z80_RL:
247
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
798 cycles = inst->immed == 1 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8);
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
799 dst = zcycles(dst, cycles);
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
800 if (inst->reg == Z80_UNUSED) {
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
801 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY);
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
802 dst = zcycles(dst, 1);
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
803 } else {
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
804 dst = translate_z80_reg(inst, &dst_op, dst, opts);
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
805 }
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
806 dst = bt_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B);
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
807 dst = rcl_ir(dst, 1, dst_op.base, SZ_B);
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
808 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C));
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
809 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B);
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
810 //TODO: Implement half-carry flag
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
811 dst = cmp_ir(dst, 0, dst_op.base, SZ_B);
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
812 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV));
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
813 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z));
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
814 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S));
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
815 if (inst->reg == Z80_UNUSED) {
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
816 dst = z80_save_result(dst, inst);
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
817 } else {
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
818 dst = z80_save_reg(dst, inst, opts);
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
819 }
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
820 break;
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
821 case Z80_RRC:
247
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
822 cycles = inst->immed == 1 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8);
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
823 dst = zcycles(dst, cycles);
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
824 if (inst->reg == Z80_UNUSED) {
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
825 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY);
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
826 dst = zcycles(dst, 1);
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
827 } else {
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
828 dst = translate_z80_reg(inst, &dst_op, dst, opts);
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
829 }
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
830 dst = ror_ir(dst, 1, dst_op.base, SZ_B);
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
831 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C));
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
832 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B);
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
833 //TODO: Implement half-carry flag
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
834 dst = cmp_ir(dst, 0, dst_op.base, SZ_B);
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
835 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV));
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
836 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z));
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
837 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S));
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
838 if (inst->reg == Z80_UNUSED) {
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
839 dst = z80_save_result(dst, inst);
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
840 } else {
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
841 dst = z80_save_reg(dst, inst, opts);
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
842 }
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
843 break;
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
844 case Z80_RR:
247
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
845 cycles = inst->immed == 1 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8);
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
846 dst = zcycles(dst, cycles);
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
847 if (inst->reg == Z80_UNUSED) {
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
848 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY);
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
849 dst = zcycles(dst, 1);
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
850 } else {
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
851 dst = translate_z80_reg(inst, &dst_op, dst, opts);
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
852 }
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
853 dst = bt_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B);
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
854 dst = rcr_ir(dst, 1, dst_op.base, SZ_B);
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
855 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C));
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
856 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B);
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
857 //TODO: Implement half-carry flag
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
858 dst = cmp_ir(dst, 0, dst_op.base, SZ_B);
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
859 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV));
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
860 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z));
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
861 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S));
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
862 if (inst->reg == Z80_UNUSED) {
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
863 dst = z80_save_result(dst, inst);
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
864 } else {
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
865 dst = z80_save_reg(dst, inst, opts);
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
866 }
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
867 break;
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
868 /*case Z80_SLA:
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
869 case Z80_SRA:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
870 case Z80_SLL:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
871 case Z80_SRL:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
872 case Z80_RLD:
239
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents: 238
diff changeset
873 case Z80_RRD:*/
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
874 case Z80_BIT:
239
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents: 238
diff changeset
875 cycles = (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) ? 8 : 16;
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents: 238
diff changeset
876 dst = zcycles(dst, cycles);
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents: 238
diff changeset
877 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY);
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents: 238
diff changeset
878 if (inst->addr_mode != Z80_REG) {
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents: 238
diff changeset
879 //Reads normally take 3 cycles, but the read at the end of a bit instruction takes 4
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents: 238
diff changeset
880 dst = zcycles(dst, 1);
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents: 238
diff changeset
881 }
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents: 238
diff changeset
882 dst = bt_ir(dst, inst->immed, src_op.base, SZ_B);
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents: 238
diff changeset
883 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_Z));
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents: 238
diff changeset
884 break;
247
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
885 case Z80_SET:
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
886 cycles = (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) ? 8 : 16;
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
887 dst = zcycles(dst, cycles);
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
888 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY);
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
889 if (inst->addr_mode != Z80_REG) {
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
890 //Reads normally take 3 cycles, but the read in the middle of a set instruction takes 4
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
891 dst = zcycles(dst, 1);
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
892 }
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
893 dst = bts_ir(dst, inst->immed, src_op.base, SZ_B);
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
894 if (inst->addr_mode != Z80_REG) {
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
895 dst = z80_save_result(dst, inst);
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
896 }
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
897 break;
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
898 case Z80_RES:
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
899 cycles = (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) ? 8 : 16;
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
900 dst = zcycles(dst, cycles);
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
901 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY);
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
902 if (inst->addr_mode != Z80_REG) {
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
903 //Reads normally take 3 cycles, but the read in the middle of a set instruction takes 4
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
904 dst = zcycles(dst, 1);
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
905 }
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
906 dst = btr_ir(dst, inst->immed, src_op.base, SZ_B);
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
907 if (inst->addr_mode != Z80_REG) {
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
908 dst = z80_save_result(dst, inst);
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
909 }
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
910 break;
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
911 case Z80_JP: {
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
912 cycles = 4;
239
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents: 238
diff changeset
913 if (inst->addr_mode != Z80_REG) {
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
914 cycles += 6;
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
915 } else if(inst->ea_reg == Z80_IX || inst->ea_reg == Z80_IY) {
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
916 cycles += 4;
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
917 }
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
918 dst = zcycles(dst, cycles);
239
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents: 238
diff changeset
919 if (inst->addr_mode != Z80_REG_INDIRECT && inst->immed < 0x4000) {
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
920 uint8_t * call_dst = z80_get_native_address(context, inst->immed);
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
921 if (!call_dst) {
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
922 opts->deferred = defer_address(opts->deferred, inst->immed, dst + 1);
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
923 //fake address to force large displacement
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
924 call_dst = dst + 256;
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
925 }
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
926 dst = jmp(dst, call_dst);
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
927 } else {
239
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents: 238
diff changeset
928 if (inst->addr_mode == Z80_REG_INDIRECT) {
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
929 dst = mov_rr(dst, opts->regs[inst->ea_reg], SCRATCH1, SZ_W);
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
930 } else {
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
931 dst = mov_ir(dst, inst->immed, SCRATCH1, SZ_W);
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
932 }
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
933 dst = call(dst, (uint8_t *)z80_native_addr);
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
934 dst = jmp_r(dst, SCRATCH1);
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
935 }
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
936 break;
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
937 }
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
938 case Z80_JPCC: {
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
939 dst = zcycles(dst, 7);//T States: 4,3
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
940 uint8_t cond = CC_Z;
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
941 switch (inst->reg)
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
942 {
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
943 case Z80_CC_NZ:
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
944 cond = CC_NZ;
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
945 case Z80_CC_Z:
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
946 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_Z), SZ_B);
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
947 break;
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
948 case Z80_CC_NC:
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
949 cond = CC_NZ;
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
950 case Z80_CC_C:
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
951 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B);
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
952 break;
238
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
953 case Z80_CC_PO:
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
954 cond = CC_NZ;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
955 case Z80_CC_PE:
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
956 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_PV), SZ_B);
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
957 break;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
958 case Z80_CC_P:
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
959 case Z80_CC_M:
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
960 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_S), SZ_B);
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
961 break;
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
962 }
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
963 uint8_t *no_jump_off = dst+1;
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
964 dst = jcc(dst, cond, dst+2);
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
965 dst = zcycles(dst, 5);//T States: 5
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
966 uint16_t dest_addr = inst->immed;
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
967 if (dest_addr < 0x4000) {
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
968 uint8_t * call_dst = z80_get_native_address(context, dest_addr);
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
969 if (!call_dst) {
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
970 opts->deferred = defer_address(opts->deferred, dest_addr, dst + 1);
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
971 //fake address to force large displacement
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
972 call_dst = dst + 256;
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
973 }
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
974 dst = jmp(dst, call_dst);
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
975 } else {
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
976 dst = mov_ir(dst, dest_addr, SCRATCH1, SZ_W);
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
977 dst = call(dst, (uint8_t *)z80_native_addr);
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
978 dst = jmp_r(dst, SCRATCH1);
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
979 }
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
980 *no_jump_off = dst - (no_jump_off+1);
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
981 break;
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
982 }
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
983 case Z80_JR: {
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
984 dst = zcycles(dst, 12);//T States: 4,3,5
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
985 uint16_t dest_addr = address + inst->immed + 2;
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
986 if (dest_addr < 0x4000) {
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
987 uint8_t * call_dst = z80_get_native_address(context, dest_addr);
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
988 if (!call_dst) {
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
989 opts->deferred = defer_address(opts->deferred, dest_addr, dst + 1);
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
990 //fake address to force large displacement
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
991 call_dst = dst + 256;
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
992 }
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
993 dst = jmp(dst, call_dst);
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
994 } else {
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
995 dst = mov_ir(dst, dest_addr, SCRATCH1, SZ_W);
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
996 dst = call(dst, (uint8_t *)z80_native_addr);
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
997 dst = jmp_r(dst, SCRATCH1);
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
998 }
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
999 break;
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
1000 }
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1001 case Z80_JRCC: {
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1002 dst = zcycles(dst, 7);//T States: 4,3
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1003 uint8_t cond = CC_Z;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1004 switch (inst->reg)
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1005 {
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1006 case Z80_CC_NZ:
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1007 cond = CC_NZ;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1008 case Z80_CC_Z:
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1009 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_Z), SZ_B);
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1010 break;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1011 case Z80_CC_NC:
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1012 cond = CC_NZ;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1013 case Z80_CC_C:
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1014 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B);
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1015 break;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1016 }
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1017 uint8_t *no_jump_off = dst+1;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1018 dst = jcc(dst, cond, dst+2);
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1019 dst = zcycles(dst, 5);//T States: 5
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1020 uint16_t dest_addr = address + inst->immed + 2;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1021 if (dest_addr < 0x4000) {
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1022 uint8_t * call_dst = z80_get_native_address(context, dest_addr);
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1023 if (!call_dst) {
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1024 opts->deferred = defer_address(opts->deferred, dest_addr, dst + 1);
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1025 //fake address to force large displacement
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1026 call_dst = dst + 256;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1027 }
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1028 dst = jmp(dst, call_dst);
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1029 } else {
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1030 dst = mov_ir(dst, dest_addr, SCRATCH1, SZ_W);
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1031 dst = call(dst, (uint8_t *)z80_native_addr);
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1032 dst = jmp_r(dst, SCRATCH1);
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1033 }
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1034 *no_jump_off = dst - (no_jump_off+1);
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1035 break;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1036 }
239
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents: 238
diff changeset
1037 case Z80_DJNZ:
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents: 238
diff changeset
1038 dst = zcycles(dst, 8);//T States: 5,3
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents: 238
diff changeset
1039 dst = sub_ir(dst, 1, opts->regs[Z80_B], SZ_B);
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents: 238
diff changeset
1040 uint8_t *no_jump_off = dst+1;
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents: 238
diff changeset
1041 dst = jcc(dst, CC_Z, dst+2);
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents: 238
diff changeset
1042 dst = zcycles(dst, 5);//T States: 5
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents: 238
diff changeset
1043 uint16_t dest_addr = address + inst->immed + 2;
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents: 238
diff changeset
1044 if (dest_addr < 0x4000) {
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents: 238
diff changeset
1045 uint8_t * call_dst = z80_get_native_address(context, dest_addr);
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents: 238
diff changeset
1046 if (!call_dst) {
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents: 238
diff changeset
1047 opts->deferred = defer_address(opts->deferred, dest_addr, dst + 1);
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents: 238
diff changeset
1048 //fake address to force large displacement
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents: 238
diff changeset
1049 call_dst = dst + 256;
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents: 238
diff changeset
1050 }
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents: 238
diff changeset
1051 dst = jmp(dst, call_dst);
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents: 238
diff changeset
1052 } else {
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents: 238
diff changeset
1053 dst = mov_ir(dst, dest_addr, SCRATCH1, SZ_W);
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents: 238
diff changeset
1054 dst = call(dst, (uint8_t *)z80_native_addr);
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents: 238
diff changeset
1055 dst = jmp_r(dst, SCRATCH1);
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents: 238
diff changeset
1056 }
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents: 238
diff changeset
1057 *no_jump_off = dst - (no_jump_off+1);
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents: 238
diff changeset
1058 break;
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1059 case Z80_CALL: {
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1060 dst = zcycles(dst, 11);//T States: 4,3,4
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1061 dst = sub_ir(dst, 2, opts->regs[Z80_SP], SZ_W);
253
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents: 252
diff changeset
1062 dst = mov_ir(dst, address + 3, SCRATCH1, SZ_W);
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents: 252
diff changeset
1063 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W);
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1064 dst = call(dst, (uint8_t *)z80_write_word_highfirst);//T States: 3, 3
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1065 if (inst->immed < 0x4000) {
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1066 uint8_t * call_dst = z80_get_native_address(context, inst->immed);
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1067 if (!call_dst) {
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1068 opts->deferred = defer_address(opts->deferred, inst->immed, dst + 1);
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1069 //fake address to force large displacement
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1070 call_dst = dst + 256;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1071 }
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1072 dst = jmp(dst, call_dst);
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1073 } else {
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1074 dst = mov_ir(dst, inst->immed, SCRATCH1, SZ_W);
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1075 dst = call(dst, (uint8_t *)z80_native_addr);
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1076 dst = jmp_r(dst, SCRATCH1);
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1077 }
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1078 break;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1079 }
238
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
1080 case Z80_CALLCC:
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
1081 dst = zcycles(dst, 10);//T States: 4,3,3 (false case)
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
1082 uint8_t cond = CC_Z;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
1083 switch (inst->reg)
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
1084 {
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
1085 case Z80_CC_NZ:
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
1086 cond = CC_NZ;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
1087 case Z80_CC_Z:
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
1088 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_Z), SZ_B);
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
1089 break;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
1090 case Z80_CC_NC:
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
1091 cond = CC_NZ;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
1092 case Z80_CC_C:
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
1093 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B);
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
1094 break;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
1095 case Z80_CC_PO:
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
1096 cond = CC_NZ;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
1097 case Z80_CC_PE:
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
1098 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_PV), SZ_B);
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
1099 break;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
1100 case Z80_CC_P:
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
1101 case Z80_CC_M:
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
1102 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_S), SZ_B);
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
1103 break;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
1104 }
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
1105 uint8_t *no_call_off = dst+1;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
1106 dst = jcc(dst, cond, dst+2);
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
1107 dst = zcycles(dst, 1);//Last of the above T states takes an extra cycle in the true case
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
1108 dst = sub_ir(dst, 2, opts->regs[Z80_SP], SZ_W);
253
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents: 252
diff changeset
1109 dst = mov_ir(dst, address + 3, SCRATCH1, SZ_W);
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents: 252
diff changeset
1110 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W);
238
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
1111 dst = call(dst, (uint8_t *)z80_write_word_highfirst);//T States: 3, 3
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
1112 if (inst->immed < 0x4000) {
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
1113 uint8_t * call_dst = z80_get_native_address(context, inst->immed);
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
1114 if (!call_dst) {
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
1115 opts->deferred = defer_address(opts->deferred, inst->immed, dst + 1);
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
1116 //fake address to force large displacement
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
1117 call_dst = dst + 256;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
1118 }
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
1119 dst = jmp(dst, call_dst);
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
1120 } else {
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
1121 dst = mov_ir(dst, inst->immed, SCRATCH1, SZ_W);
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
1122 dst = call(dst, (uint8_t *)z80_native_addr);
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
1123 dst = jmp_r(dst, SCRATCH1);
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
1124 }
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
1125 *no_call_off = dst - (no_call_off+1);
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
1126 break;
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1127 case Z80_RET:
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1128 dst = zcycles(dst, 4);//T States: 4
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1129 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W);
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1130 dst = call(dst, (uint8_t *)z80_read_word);//T STates: 3, 3
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1131 dst = add_ir(dst, 2, opts->regs[Z80_SP], SZ_W);
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1132 dst = call(dst, (uint8_t *)z80_native_addr);
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1133 dst = jmp_r(dst, SCRATCH1);
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1134 break;
246
ed548c77b598 Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents: 243
diff changeset
1135 case Z80_RETCC: {
ed548c77b598 Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents: 243
diff changeset
1136 dst = zcycles(dst, 5);//T States: 5
ed548c77b598 Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents: 243
diff changeset
1137 uint8_t cond = CC_Z;
ed548c77b598 Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents: 243
diff changeset
1138 switch (inst->reg)
ed548c77b598 Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents: 243
diff changeset
1139 {
ed548c77b598 Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents: 243
diff changeset
1140 case Z80_CC_NZ:
ed548c77b598 Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents: 243
diff changeset
1141 cond = CC_NZ;
ed548c77b598 Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents: 243
diff changeset
1142 case Z80_CC_Z:
ed548c77b598 Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents: 243
diff changeset
1143 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_Z), SZ_B);
ed548c77b598 Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents: 243
diff changeset
1144 break;
ed548c77b598 Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents: 243
diff changeset
1145 case Z80_CC_NC:
ed548c77b598 Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents: 243
diff changeset
1146 cond = CC_NZ;
ed548c77b598 Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents: 243
diff changeset
1147 case Z80_CC_C:
ed548c77b598 Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents: 243
diff changeset
1148 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B);
ed548c77b598 Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents: 243
diff changeset
1149 break;
ed548c77b598 Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents: 243
diff changeset
1150 case Z80_CC_PO:
ed548c77b598 Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents: 243
diff changeset
1151 cond = CC_NZ;
ed548c77b598 Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents: 243
diff changeset
1152 case Z80_CC_PE:
ed548c77b598 Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents: 243
diff changeset
1153 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_PV), SZ_B);
ed548c77b598 Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents: 243
diff changeset
1154 break;
ed548c77b598 Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents: 243
diff changeset
1155 case Z80_CC_P:
ed548c77b598 Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents: 243
diff changeset
1156 case Z80_CC_M:
ed548c77b598 Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents: 243
diff changeset
1157 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_S), SZ_B);
ed548c77b598 Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents: 243
diff changeset
1158 break;
ed548c77b598 Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents: 243
diff changeset
1159 }
ed548c77b598 Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents: 243
diff changeset
1160 uint8_t *no_call_off = dst+1;
ed548c77b598 Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents: 243
diff changeset
1161 dst = jcc(dst, cond, dst+2);
ed548c77b598 Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents: 243
diff changeset
1162 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W);
ed548c77b598 Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents: 243
diff changeset
1163 dst = call(dst, (uint8_t *)z80_read_word);//T STates: 3, 3
ed548c77b598 Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents: 243
diff changeset
1164 dst = add_ir(dst, 2, opts->regs[Z80_SP], SZ_W);
ed548c77b598 Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents: 243
diff changeset
1165 dst = call(dst, (uint8_t *)z80_native_addr);
ed548c77b598 Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents: 243
diff changeset
1166 dst = jmp_r(dst, SCRATCH1);
ed548c77b598 Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents: 243
diff changeset
1167 *no_call_off = dst - (no_call_off+1);
ed548c77b598 Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents: 243
diff changeset
1168 break;
ed548c77b598 Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents: 243
diff changeset
1169 }
ed548c77b598 Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents: 243
diff changeset
1170 /*case Z80_RETI:
241
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
1171 case Z80_RETN:*/
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
1172 case Z80_RST: {
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
1173 //RST is basically CALL to an address in page 0
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
1174 dst = zcycles(dst, 5);//T States: 5
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
1175 dst = sub_ir(dst, 2, opts->regs[Z80_SP], SZ_W);
253
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents: 252
diff changeset
1176 dst = mov_ir(dst, address + 3, SCRATCH1, SZ_W);
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents: 252
diff changeset
1177 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W);
241
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
1178 dst = call(dst, (uint8_t *)z80_write_word_highfirst);//T States: 3, 3
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
1179 uint8_t * call_dst = z80_get_native_address(context, inst->immed);
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
1180 if (!call_dst) {
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
1181 opts->deferred = defer_address(opts->deferred, inst->immed, dst + 1);
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
1182 //fake address to force large displacement
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
1183 call_dst = dst + 256;
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
1184 }
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
1185 dst = jmp(dst, call_dst);
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
1186 break;
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
1187 }
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
1188 /*case Z80_IN:
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1189 case Z80_INI:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1190 case Z80_INIR:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1191 case Z80_IND:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1192 case Z80_INDR:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1193 case Z80_OUT:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1194 case Z80_OUTI:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1195 case Z80_OTIR:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1196 case Z80_OUTD:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1197 case Z80_OTDR:*/
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1198 default: {
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1199 char disbuf[80];
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1200 z80_disasm(inst, disbuf);
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1201 fprintf(stderr, "unimplemented instruction: %s\n", disbuf);
259
d9417261366f Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called.
Mike Pavone <pavone@retrodev.com>
parents: 257
diff changeset
1202 FILE * f = fopen("zram.bin", "wb");
d9417261366f Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called.
Mike Pavone <pavone@retrodev.com>
parents: 257
diff changeset
1203 fwrite(context->mem_pointers[0], 1, 8 * 1024, f);
d9417261366f Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called.
Mike Pavone <pavone@retrodev.com>
parents: 257
diff changeset
1204 fclose(f);
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1205 exit(1);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1206 }
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1207 }
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1208 return dst;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1209 }
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1210
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1211 uint8_t * z80_get_native_address(z80_context * context, uint32_t address)
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1212 {
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1213 native_map_slot *map;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1214 if (address < 0x4000) {
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1215 address &= 0x1FFF;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1216 map = context->static_code_map;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1217 } else if (address >= 0x8000) {
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1218 address &= 0x7FFF;
252
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1219 map = context->banked_code_map + (context->bank_reg << 15);
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1220 } else {
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1221 return NULL;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1222 }
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1223 if (!map->base || !map->offsets || map->offsets[address] == INVALID_OFFSET) {
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1224 return NULL;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1225 }
264
8fd6652e56f8 Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents: 262
diff changeset
1226 //printf("z80_get_native_address: %X %p\n", address, map->base + map->offsets[address]);
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1227 return map->base + map->offsets[address];
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1228 }
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1229
252
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1230 uint8_t z80_get_native_inst_size(x86_z80_options * opts, uint32_t address)
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1231 {
252
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1232 if (address >= 0x4000) {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1233 return 0;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1234 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1235 return opts->ram_inst_sizes[address & 0x1FFF];
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1236 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1237
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1238 void z80_map_native_address(z80_context * context, uint32_t address, uint8_t * native_address, uint8_t size, uint8_t native_size)
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1239 {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1240 uint32_t orig_address = address;
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1241 native_map_slot *map;
252
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1242 x86_z80_options * opts = context->options;
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1243 if (address < 0x4000) {
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1244 address &= 0x1FFF;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1245 map = context->static_code_map;
252
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1246 opts->ram_inst_sizes[address] = native_size;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1247 context->ram_code_flags[(address & 0x1C00) >> 10] |= 1 << ((address & 0x380) >> 7);
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1248 context->ram_code_flags[((address + size) & 0x1C00) >> 10] |= 1 << (((address + size) & 0x380) >> 7);
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1249 } else if (address >= 0x8000) {
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1250 address &= 0x7FFF;
252
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1251 map = context->banked_code_map + (context->bank_reg << 15);
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1252 if (!map->offsets) {
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1253 map->offsets = malloc(sizeof(int32_t) * 0x8000);
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1254 memset(map->offsets, 0xFF, sizeof(int32_t) * 0x8000);
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1255 }
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1256 } else {
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1257 return;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1258 }
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1259 if (!map->base) {
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1260 map->base = native_address;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1261 }
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1262 map->offsets[address] = native_address - map->base;
253
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents: 252
diff changeset
1263 for(--size, orig_address++; size; --size, orig_address++) {
252
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1264 address = orig_address;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1265 if (address < 0x4000) {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1266 address &= 0x1FFF;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1267 map = context->static_code_map;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1268 } else if (address >= 0x8000) {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1269 address &= 0x7FFF;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1270 map = context->banked_code_map + (context->bank_reg << 15);
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1271 } else {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1272 return;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1273 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1274 if (!map->offsets) {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1275 map->offsets = malloc(sizeof(int32_t) * 0x8000);
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1276 memset(map->offsets, 0xFF, sizeof(int32_t) * 0x8000);
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1277 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1278 map->offsets[address] = EXTENSION_WORD;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1279 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1280 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1281
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1282 #define INVALID_INSTRUCTION_START 0xFEEDFEED
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1283
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1284 uint32_t z80_get_instruction_start(native_map_slot * static_code_map, uint32_t address)
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1285 {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1286 if (!static_code_map->base || address >= 0x4000) {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1287 return INVALID_INSTRUCTION_START;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1288 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1289 address &= 0x1FFF;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1290 if (static_code_map->offsets[address] == INVALID_OFFSET) {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1291 return INVALID_INSTRUCTION_START;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1292 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1293 while (static_code_map->offsets[address] == EXTENSION_WORD) {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1294 --address;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1295 address &= 0x1FFF;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1296 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1297 return address;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1298 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1299
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1300 z80_context * z80_handle_code_write(uint32_t address, z80_context * context)
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1301 {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1302 uint32_t inst_start = z80_get_instruction_start(context->static_code_map, address);
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1303 if (inst_start != INVALID_INSTRUCTION_START) {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1304 uint8_t * dst = z80_get_native_address(context, inst_start);
264
8fd6652e56f8 Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents: 262
diff changeset
1305 //printf("patching code at %p for Z80 instruction at %X due to write to %X\n", dst, inst_start, address);
252
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1306 dst = mov_ir(dst, inst_start, SCRATCH1, SZ_D);
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1307 dst = jmp(dst, (uint8_t *)z80_retrans_stub);
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1308 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1309 return context;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1310 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1311
264
8fd6652e56f8 Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents: 262
diff changeset
1312 uint8_t * z80_get_native_address_trans(z80_context * context, uint32_t address)
8fd6652e56f8 Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents: 262
diff changeset
1313 {
8fd6652e56f8 Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents: 262
diff changeset
1314 uint8_t * addr = z80_get_native_address(context, address);
8fd6652e56f8 Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents: 262
diff changeset
1315 if (!addr) {
8fd6652e56f8 Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents: 262
diff changeset
1316 translate_z80_stream(context, address);
8fd6652e56f8 Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents: 262
diff changeset
1317 addr = z80_get_native_address(context, address);
8fd6652e56f8 Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents: 262
diff changeset
1318 if (!addr) {
8fd6652e56f8 Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents: 262
diff changeset
1319 printf("Failed to translate %X to native code\n", address);
8fd6652e56f8 Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents: 262
diff changeset
1320 }
8fd6652e56f8 Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents: 262
diff changeset
1321 }
8fd6652e56f8 Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents: 262
diff changeset
1322 return addr;
8fd6652e56f8 Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents: 262
diff changeset
1323 }
8fd6652e56f8 Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents: 262
diff changeset
1324
266
376df762ddf5 Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 264
diff changeset
1325 void z80_handle_deferred(z80_context * context)
376df762ddf5 Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 264
diff changeset
1326 {
376df762ddf5 Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 264
diff changeset
1327 x86_z80_options * opts = context->options;
376df762ddf5 Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 264
diff changeset
1328 process_deferred(&opts->deferred, context, (native_addr_func)z80_get_native_address);
376df762ddf5 Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 264
diff changeset
1329 if (opts->deferred) {
376df762ddf5 Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 264
diff changeset
1330 translate_z80_stream(context, opts->deferred->address);
376df762ddf5 Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 264
diff changeset
1331 }
376df762ddf5 Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 264
diff changeset
1332 }
376df762ddf5 Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 264
diff changeset
1333
252
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1334 void * z80_retranslate_inst(uint32_t address, z80_context * context)
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1335 {
266
376df762ddf5 Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 264
diff changeset
1336 char disbuf[80];
252
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1337 x86_z80_options * opts = context->options;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1338 uint8_t orig_size = z80_get_native_inst_size(opts, address);
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1339 uint8_t * orig_start = z80_get_native_address(context, address);
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1340 uint32_t orig = address;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1341 address &= 0x1FFF;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1342 uint8_t * dst = opts->cur_code;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1343 uint8_t * dst_end = opts->code_end;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1344 uint8_t *after, *inst = context->mem_pointers[0] + address;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1345 z80inst instbuf;
266
376df762ddf5 Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 264
diff changeset
1346 //printf("Retranslating code at Z80 address %X, native address %p\n", address, orig_start);
252
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1347 after = z80_decode(inst, &instbuf);
266
376df762ddf5 Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 264
diff changeset
1348 /*z80_disasm(&instbuf, disbuf);
376df762ddf5 Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 264
diff changeset
1349 if (instbuf.op == Z80_NOP) {
376df762ddf5 Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 264
diff changeset
1350 printf("%X\t%s(%d)\n", address, disbuf, instbuf.immed);
376df762ddf5 Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 264
diff changeset
1351 } else {
376df762ddf5 Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 264
diff changeset
1352 printf("%X\t%s\n", address, disbuf);
376df762ddf5 Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 264
diff changeset
1353 }*/
252
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1354 if (orig_size != ZMAX_NATIVE_SIZE) {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1355 if (dst_end - dst < ZMAX_NATIVE_SIZE) {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1356 size_t size = 1024*1024;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1357 dst = alloc_code(&size);
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1358 opts->code_end = dst_end = dst + size;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1359 opts->cur_code = dst;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1360 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1361 uint8_t * native_end = translate_z80inst(&instbuf, dst, context, address);
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1362 if ((native_end - dst) <= orig_size) {
264
8fd6652e56f8 Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents: 262
diff changeset
1363 uint8_t * native_next = z80_get_native_address(context, address + after-inst);
8fd6652e56f8 Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents: 262
diff changeset
1364 if (native_next && ((native_next == orig_start + orig_size) || (orig_size - (native_end - dst)) > 5)) {
8fd6652e56f8 Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents: 262
diff changeset
1365 native_end = translate_z80inst(&instbuf, orig_start, context, address);
266
376df762ddf5 Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 264
diff changeset
1366 if (native_next == orig_start + orig_size && (native_next-native_end) < 2) {
264
8fd6652e56f8 Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents: 262
diff changeset
1367 while (native_end < orig_start + orig_size) {
8fd6652e56f8 Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents: 262
diff changeset
1368 *(native_end++) = 0x90; //NOP
8fd6652e56f8 Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents: 262
diff changeset
1369 }
8fd6652e56f8 Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents: 262
diff changeset
1370 } else {
8fd6652e56f8 Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents: 262
diff changeset
1371 jmp(native_end, native_next);
8fd6652e56f8 Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents: 262
diff changeset
1372 }
266
376df762ddf5 Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 264
diff changeset
1373 z80_handle_deferred(context);
264
8fd6652e56f8 Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents: 262
diff changeset
1374 return orig_start;
252
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1375 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1376 }
264
8fd6652e56f8 Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents: 262
diff changeset
1377 z80_map_native_address(context, address, dst, after-inst, ZMAX_NATIVE_SIZE);
266
376df762ddf5 Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 264
diff changeset
1378 opts->cur_code = dst+ZMAX_NATIVE_SIZE;
376df762ddf5 Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 264
diff changeset
1379 jmp(orig_start, dst);
264
8fd6652e56f8 Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents: 262
diff changeset
1380 if(!(instbuf.op == Z80_RET || instbuf.op == Z80_RETI || instbuf.op == Z80_RETN || instbuf.op == Z80_JP || (instbuf.op == Z80_NOP && instbuf.immed == 42))) {
8fd6652e56f8 Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents: 262
diff changeset
1381 jmp(native_end, z80_get_native_address_trans(context, address + after-inst));
8fd6652e56f8 Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents: 262
diff changeset
1382 }
266
376df762ddf5 Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 264
diff changeset
1383 z80_handle_deferred(context);
264
8fd6652e56f8 Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents: 262
diff changeset
1384 return dst;
252
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1385 } else {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1386 dst = translate_z80inst(&instbuf, orig_start, context, address);
254
64feb6b67244 Fix bug in end condition inside translate_z80_stream.
Mike Pavone <pavone@retrodev.com>
parents: 253
diff changeset
1387 if(!(instbuf.op == Z80_RET || instbuf.op == Z80_RETI || instbuf.op == Z80_RETN || instbuf.op == Z80_JP || (instbuf.op == Z80_NOP && instbuf.immed == 42))) {
264
8fd6652e56f8 Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents: 262
diff changeset
1388 dst = jmp(dst, z80_get_native_address_trans(context, address + after-inst));
252
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1389 }
266
376df762ddf5 Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 264
diff changeset
1390 z80_handle_deferred(context);
252
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1391 return orig_start;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1392 }
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1393 }
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1394
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1395 void translate_z80_stream(z80_context * context, uint32_t address)
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1396 {
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1397 char disbuf[80];
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1398 if (z80_get_native_address(context, address)) {
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1399 return;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1400 }
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1401 x86_z80_options * opts = context->options;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1402 uint8_t * encoded = NULL, *next;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1403 if (address < 0x4000) {
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1404 encoded = context->mem_pointers[0] + (address & 0x1FFF);
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1405 } else if(address >= 0x8000 && context->mem_pointers[1]) {
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1406 encoded = context->mem_pointers[1] + (address & 0x7FFF);
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1407 }
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1408 while (encoded != NULL)
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1409 {
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1410 z80inst inst;
264
8fd6652e56f8 Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents: 262
diff changeset
1411 //printf("translating Z80 code at address %X\n", address);
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1412 do {
252
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1413 if (opts->code_end-opts->cur_code < ZMAX_NATIVE_SIZE) {
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1414 if (opts->code_end-opts->cur_code < 5) {
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1415 puts("out of code memory, not enough space for jmp to next chunk");
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1416 exit(1);
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1417 }
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1418 size_t size = 1024*1024;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1419 opts->cur_code = alloc_code(&size);
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1420 opts->code_end = opts->cur_code + size;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1421 jmp(opts->cur_code, opts->cur_code);
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1422 }
255
572b935dd030 Properly handle wrapping around to 0 in translate_z80_stream
Mike Pavone <pavone@retrodev.com>
parents: 254
diff changeset
1423 if (address > 0x4000 && address < 0x8000) {
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1424 opts->cur_code = xor_rr(opts->cur_code, RDI, RDI, SZ_D);
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1425 opts->cur_code = call(opts->cur_code, (uint8_t *)exit);
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1426 break;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1427 }
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1428 uint8_t * existing = z80_get_native_address(context, address);
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1429 if (existing) {
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1430 opts->cur_code = jmp(opts->cur_code, existing);
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1431 break;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1432 }
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1433 next = z80_decode(encoded, &inst);
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1434 z80_disasm(&inst, disbuf);
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1435 if (inst.op == Z80_NOP) {
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1436 printf("%X\t%s(%d)\n", address, disbuf, inst.immed);
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1437 } else {
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1438 printf("%X\t%s\n", address, disbuf);
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1439 }
248
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
1440 uint8_t *after = translate_z80inst(&inst, opts->cur_code, context, address);
252
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1441 z80_map_native_address(context, address, opts->cur_code, next-encoded, after - opts->cur_code);
248
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
1442 opts->cur_code = after;
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1443 address += next-encoded;
255
572b935dd030 Properly handle wrapping around to 0 in translate_z80_stream
Mike Pavone <pavone@retrodev.com>
parents: 254
diff changeset
1444 if (address > 0xFFFF) {
572b935dd030 Properly handle wrapping around to 0 in translate_z80_stream
Mike Pavone <pavone@retrodev.com>
parents: 254
diff changeset
1445 address &= 0xFFFF;
572b935dd030 Properly handle wrapping around to 0 in translate_z80_stream
Mike Pavone <pavone@retrodev.com>
parents: 254
diff changeset
1446
572b935dd030 Properly handle wrapping around to 0 in translate_z80_stream
Mike Pavone <pavone@retrodev.com>
parents: 254
diff changeset
1447 } else {
572b935dd030 Properly handle wrapping around to 0 in translate_z80_stream
Mike Pavone <pavone@retrodev.com>
parents: 254
diff changeset
1448 encoded = next;
572b935dd030 Properly handle wrapping around to 0 in translate_z80_stream
Mike Pavone <pavone@retrodev.com>
parents: 254
diff changeset
1449 }
254
64feb6b67244 Fix bug in end condition inside translate_z80_stream.
Mike Pavone <pavone@retrodev.com>
parents: 253
diff changeset
1450 } while (!(inst.op == Z80_RET || inst.op == Z80_RETI || inst.op == Z80_RETN || inst.op == Z80_JP || (inst.op == Z80_NOP && inst.immed == 42)));
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1451 process_deferred(&opts->deferred, context, (native_addr_func)z80_get_native_address);
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1452 if (opts->deferred) {
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1453 address = opts->deferred->address;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1454 printf("defferred address: %X\n", address);
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1455 if (address < 0x4000) {
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1456 encoded = context->mem_pointers[0] + (address & 0x1FFF);
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1457 } else if (address > 0x8000 && context->mem_pointers[1]) {
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1458 encoded = context->mem_pointers[1] + (address & 0x7FFF);
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1459 } else {
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1460 printf("attempt to translate non-memory address: %X\n", address);
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1461 exit(1);
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1462 }
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1463 } else {
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1464 encoded = NULL;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1465 }
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1466 }
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1467 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1468
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1469 void init_x86_z80_opts(x86_z80_options * options)
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1470 {
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1471 options->flags = 0;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1472 options->regs[Z80_B] = BH;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1473 options->regs[Z80_C] = RBX;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1474 options->regs[Z80_D] = CH;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1475 options->regs[Z80_E] = RCX;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1476 options->regs[Z80_H] = AH;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1477 options->regs[Z80_L] = RAX;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1478 options->regs[Z80_IXH] = DH;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1479 options->regs[Z80_IXL] = RDX;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1480 options->regs[Z80_IYH] = -1;
239
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents: 238
diff changeset
1481 options->regs[Z80_IYL] = R8;
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1482 options->regs[Z80_I] = -1;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1483 options->regs[Z80_R] = -1;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1484 options->regs[Z80_A] = R10;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1485 options->regs[Z80_BC] = RBX;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1486 options->regs[Z80_DE] = RCX;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1487 options->regs[Z80_HL] = RAX;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1488 options->regs[Z80_SP] = R9;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1489 options->regs[Z80_AF] = -1;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1490 options->regs[Z80_IX] = RDX;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1491 options->regs[Z80_IY] = R8;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1492 size_t size = 1024 * 1024;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1493 options->cur_code = alloc_code(&size);
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1494 options->code_end = options->cur_code + size;
252
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1495 options->ram_inst_sizes = malloc(sizeof(uint8_t) * 0x2000);
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
1496 memset(options->ram_inst_sizes, 0, sizeof(uint8_t) * 0x2000);
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1497 options->deferred = NULL;
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1498 }
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1499
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1500 void init_z80_context(z80_context * context, x86_z80_options * options)
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1501 {
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1502 memset(context, 0, sizeof(*context));
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1503 context->static_code_map = malloc(sizeof(context->static_code_map));
259
d9417261366f Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called.
Mike Pavone <pavone@retrodev.com>
parents: 257
diff changeset
1504 context->static_code_map->base = NULL;
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1505 context->static_code_map->offsets = malloc(sizeof(int32_t) * 0x2000);
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1506 memset(context->static_code_map->offsets, 0xFF, sizeof(int32_t) * 0x2000);
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1507 context->banked_code_map = malloc(sizeof(native_map_slot) * (1 << 9));
259
d9417261366f Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called.
Mike Pavone <pavone@retrodev.com>
parents: 257
diff changeset
1508 memset(context->banked_code_map, 0, sizeof(native_map_slot) * (1 << 9));
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1509 context->options = options;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1510 }
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1511
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1512 void z80_reset(z80_context * context)
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1513 {
259
d9417261366f Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called.
Mike Pavone <pavone@retrodev.com>
parents: 257
diff changeset
1514 context->im = 0;
d9417261366f Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called.
Mike Pavone <pavone@retrodev.com>
parents: 257
diff changeset
1515 context->iff1 = context->iff2 = 0;
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1516 context->native_pc = z80_get_native_address_trans(context, 0);
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1517 }
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1518
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1519