Mercurial > repos > blastem
annotate gen_arm.c @ 711:3342548de036
Adjust H32 vint slot in response to latest test ROM data
author | Michael Pavone <pavone@retrodev.com> |
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date | Sat, 16 May 2015 23:08:07 -0700 |
parents | bff307e03a94 |
children | 724bbec47f86 |
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1 /* |
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2 Copyright 2014 Michael Pavone |
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3 This file is part of BlastEm. |
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4 BlastEm is free software distributed under the terms of the GNU General Public License version 3 or greater. See COPYING for full license text. |
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5 */ |
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6 #include "gen_arm.h" |
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7 #include "mem.h" |
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8 #include <stdio.h> |
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9 #include <stdlib.h> |
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10 |
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11 #define OP_FIELD_SHIFT 21u |
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12 |
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13 //Data processing format instructions |
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14 #define OP_AND 0x0u |
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15 #define OP_EOR (0x1u << OP_FIELD_SHIFT) |
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16 #define OP_SUB (0x2u << OP_FIELD_SHIFT) |
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17 #define OP_RSB (0x3u << OP_FIELD_SHIFT) |
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18 #define OP_ADD (0x4u << OP_FIELD_SHIFT) |
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19 #define OP_ADC (0x5u << OP_FIELD_SHIFT) |
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20 #define OP_SBC (0x6u << OP_FIELD_SHIFT) |
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21 #define OP_RSC (0x7u << OP_FIELD_SHIFT) |
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22 #define OP_TST (0x8u << OP_FIELD_SHIFT) |
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23 #define OP_TEQ (0x9u << OP_FIELD_SHIFT) |
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24 #define OP_CMP (0xAu << OP_FIELD_SHIFT) |
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25 #define OP_CMN (0xBu << OP_FIELD_SHIFT) |
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26 #define OP_ORR (0xCu << OP_FIELD_SHIFT) |
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27 #define OP_MOV (0xDu << OP_FIELD_SHIFT) |
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28 #define OP_BIC (0xEu << OP_FIELD_SHIFT) |
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29 #define OP_MVN (0xFu << OP_FIELD_SHIFT) |
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30 |
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31 //branch instructions |
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32 #define OP_B 0xA000000u |
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33 #define OP_BL 0xB000000u |
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34 #define OP_BX 0x12FFF10u |
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35 |
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36 //load/store |
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37 #define OP_STR 0x4000000u |
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38 #define OP_LDR 0x4100000u |
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39 #define OP_STM 0x8000000u |
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40 #define OP_LDM 0x8100000u |
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41 #define POST_IND 0u |
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42 #define PRE_IND 0x1000000u |
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43 #define DIR_DOWN 0u |
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44 #define DIR_UP 0x0800000u |
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45 #define SZ_W 0u |
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46 #define SZ_B 0x0400000u |
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47 #define WRITE_B 0x0200000u |
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48 #define OFF_IMM 0u |
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49 #define OFF_REG 0x2000000u |
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50 |
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51 #define PUSH (OP_STR | PRE_IND | OFF_IMM | SZ_W | WRITE_B | DIR_DOWN | sizeof(uint32_t) | (sp << 16)) |
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52 #define POP (OP_LDR | POST_IND | OFF_IMM | SZ_W | DIR_UP | sizeof(uint32_t) | (sp << 16)) |
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53 #define PUSHM (OP_STM | PRE_IND | SZ_W | WRITE_B | DIR_DOWN | (sp << 16)) |
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54 #define POPM (OP_LDM | POST_IND | SZ_W | WRITE_B | DIR_UP | (sp << 16)) |
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55 |
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56 #define IMMED 0x2000000u |
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57 #define REG 0u |
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58 |
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59 |
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60 uint32_t make_immed(uint32_t val) |
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61 { |
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62 uint32_t rot_amount = 0; |
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63 for (; rot_amount < 0x20; rot_amount += 2) |
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64 { |
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65 uint32_t test_mask = ~(0xFF << rot_amount | 0xFF >> (32-rot_amount)); |
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66 if (!(test_mask & val)) { |
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67 return val << rot_amount | val >> (32-rot_amount) | rot_amount << 7; |
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68 } |
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69 } |
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70 return INVALID_IMMED; |
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71 } |
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72 |
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73 void check_alloc_code(code_info *code) |
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74 { |
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75 if (code->cur == code->last) { |
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76 size_t size = CODE_ALLOC_SIZE; |
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77 uint32_t *next_code = alloc_code(&size); |
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78 if (!next_code) { |
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79 fputs("Failed to allocate memory for generated code\n", stderr); |
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80 exit(1); |
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81 } |
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82 if (next_code = code->last + RESERVE_WORDS) { |
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83 //new chunk is contiguous with the current one |
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84 code->last = next_code + size/sizeof(code_word) - RESERVE_WORDS; |
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85 } else { |
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86 uint32_t * from = code->cur + 2; |
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87 if (next_code - from < 0x400000 || from - next_code <= 0x400000) { |
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88 *from = CC_AL | OP_B | ((next_code - from) & 0xFFFFFF); |
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89 } else { |
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90 //push r0 onto the stack |
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91 *(from++) = CC_AL | PUSH; |
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92 uint32_t immed = make_immed((uint32_t)next_code); |
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93 if (immed == INVALID_IMMED) { |
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94 //Load target into r0 from word after next instruction into register 0 |
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95 *(from++) = CC_AL | OP_LDR | OFF_IMM | DIR_DOWN | PRE_IND | SZ_W | (pc << 16) | 4; |
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96 from[1] = (uint32_t)next_code; |
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97 } else { |
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98 //Load target into r0 |
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99 *(from++) = CC_AL | OP_MOV | IMMED | NO_COND | immed; |
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100 } |
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101 //branch to address in r0 |
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102 *from = CC_AL | OP_BX; |
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103 code->last = next_code + size/sizeof(code_word) - RESERVE_WORDS; |
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104 //pop r0 |
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105 *(next_code++) = CC_AL | POP; |
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106 code->cur = next_code; |
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107 } |
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108 } |
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109 } |
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110 } |
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111 |
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112 uint32_t data_proc(code_info *code, uint32_t cond, uint32_t op, uint32_t set_cond, uint32_t dst, uint32_t src1, uint32_t src2) |
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113 { |
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114 check_alloc_code(code); |
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115 *(code->cur++) = cond | op | set_cond | (src1 << 16) | (dst << 12) | src2; |
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116 |
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117 return CODE_OK; |
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118 } |
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119 |
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120 uint32_t data_proci(code_info *code, uint32_t cond, uint32_t op, uint32_t set_cond, uint32_t dst, uint32_t src1, uint32_t immed) |
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121 { |
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122 immed = make_immed(immed); |
554
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123 if (immed == INVALID_IMMED) { |
553
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124 return immed; |
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125 } |
554
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126 return data_proc(code, cond, op | IMMED, set_cond, dst, src1, immed); |
553
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127 } |
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128 |
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129 //TODO: support shifted register for op2 |
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130 |
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131 uint32_t and(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t set_cond) |
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132 { |
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133 return data_proc(code, CC_AL, OP_AND, set_cond, dst, src1, src2); |
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134 } |
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135 |
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136 uint32_t andi(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t set_cond) |
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137 { |
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138 return data_proci(code, CC_AL, OP_AND, set_cond, dst, src1, immed); |
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139 } |
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140 |
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141 uint32_t and_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t cc, uint32_t set_cond) |
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142 { |
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143 return data_proc(code, cc, OP_AND, set_cond, dst, src1, src2); |
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144 } |
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145 |
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146 uint32_t andi_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t cc, uint32_t set_cond) |
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147 { |
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148 return data_proci(code, cc, OP_AND, set_cond, dst, src1, immed); |
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149 } |
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150 |
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151 uint32_t eor(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t set_cond) |
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152 { |
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153 return data_proc(code, CC_AL, OP_EOR, set_cond, dst, src1, src2); |
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154 } |
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155 |
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156 uint32_t eori(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t set_cond) |
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157 { |
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158 return data_proci(code, CC_AL, OP_EOR, set_cond, dst, src1, immed); |
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159 } |
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160 |
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161 uint32_t eor_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t cc, uint32_t set_cond) |
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162 { |
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163 return data_proc(code, cc, OP_EOR, set_cond, dst, src1, src2); |
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164 } |
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165 |
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166 uint32_t eori_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t cc, uint32_t set_cond) |
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167 { |
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168 return data_proci(code, cc, OP_EOR, set_cond, dst, src1, immed); |
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169 } |
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170 |
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171 uint32_t sub(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t set_cond) |
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172 { |
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173 return data_proc(code, CC_AL, OP_SUB, set_cond, dst, src1, src2); |
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174 } |
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175 |
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176 uint32_t subi(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t set_cond) |
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177 { |
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178 return data_proci(code, CC_AL, OP_SUB, set_cond, dst, src1, immed); |
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179 } |
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180 |
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181 uint32_t sub_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t cc, uint32_t set_cond) |
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182 { |
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183 return data_proc(code, cc, OP_SUB, set_cond, dst, src1, src2); |
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184 } |
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185 |
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186 uint32_t subi_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t cc, uint32_t set_cond) |
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187 { |
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188 return data_proci(code, cc, OP_SUB, set_cond, dst, src1, immed); |
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189 } |
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190 |
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191 uint32_t rsb(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t set_cond) |
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|
192 { |
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193 return data_proc(code, CC_AL, OP_RSB, set_cond, dst, src1, src2); |
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194 } |
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195 |
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196 uint32_t rsbi(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t set_cond) |
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197 { |
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198 return data_proci(code, CC_AL, OP_RSB, set_cond, dst, src1, immed); |
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|
199 } |
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200 |
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|
201 uint32_t rsb_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t cc, uint32_t set_cond) |
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|
202 { |
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203 return data_proc(code, cc, OP_RSB, set_cond, dst, src1, src2); |
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|
204 } |
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|
205 |
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|
206 uint32_t rsbi_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t cc, uint32_t set_cond) |
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|
207 { |
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|
208 return data_proci(code, cc, OP_RSB, set_cond, dst, src1, immed); |
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|
209 } |
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diff
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|
210 |
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|
211 uint32_t add(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t set_cond) |
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|
212 { |
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|
213 return data_proc(code, CC_AL, OP_ADD, set_cond, dst, src1, src2); |
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|
214 } |
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diff
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|
215 |
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|
216 uint32_t addi(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t set_cond) |
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|
217 { |
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|
218 return data_proci(code, CC_AL, OP_ADD, set_cond, dst, src1, immed); |
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|
219 } |
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|
220 |
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|
221 uint32_t add_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t cc, uint32_t set_cond) |
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|
222 { |
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223 return data_proc(code, cc, OP_ADD, set_cond, dst, src1, src2); |
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|
224 } |
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diff
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|
225 |
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|
226 uint32_t addi_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t cc, uint32_t set_cond) |
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|
227 { |
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|
228 return data_proci(code, cc, OP_ADD, set_cond, dst, src1, immed); |
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|
229 } |
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diff
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|
230 |
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|
231 uint32_t adc(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t set_cond) |
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|
232 { |
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|
233 return data_proc(code, CC_AL, OP_ADC, set_cond, dst, src1, src2); |
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|
234 } |
1af6c1052993
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|
235 |
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|
236 uint32_t adci(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t set_cond) |
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|
237 { |
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|
238 return data_proci(code, CC_AL, OP_ADC, set_cond, dst, src1, immed); |
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|
239 } |
1af6c1052993
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diff
changeset
|
240 |
1af6c1052993
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241 uint32_t adc_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t cc, uint32_t set_cond) |
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242 { |
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243 return data_proc(code, cc, OP_ADC, set_cond, dst, src1, src2); |
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244 } |
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245 |
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246 uint32_t adci_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t cc, uint32_t set_cond) |
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247 { |
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248 return data_proci(code, cc, OP_ADC, set_cond, dst, src1, immed); |
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249 } |
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250 |
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251 uint32_t sbc(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t set_cond) |
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252 { |
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253 return data_proc(code, CC_AL, OP_SBC, set_cond, dst, src1, src2); |
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254 } |
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255 |
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256 uint32_t sbci(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t set_cond) |
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257 { |
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258 return data_proci(code, CC_AL, OP_SBC, set_cond, dst, src1, immed); |
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259 } |
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260 |
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261 uint32_t sbc_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t cc, uint32_t set_cond) |
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262 { |
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263 return data_proc(code, cc, OP_SBC, set_cond, dst, src1, src2); |
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264 } |
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265 |
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266 uint32_t sbci_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t cc, uint32_t set_cond) |
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267 { |
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268 return data_proci(code, cc, OP_SBC, set_cond, dst, src1, immed); |
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269 } |
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270 |
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271 uint32_t rsc(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t set_cond) |
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272 { |
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273 return data_proc(code, CC_AL, OP_RSC, set_cond, dst, src1, src2); |
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274 } |
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275 |
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276 uint32_t rsci(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t set_cond) |
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277 { |
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278 return data_proci(code, CC_AL, OP_RSC, set_cond, dst, src1, immed); |
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279 } |
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280 |
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281 uint32_t rsc_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t cc, uint32_t set_cond) |
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282 { |
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283 return data_proc(code, cc, OP_RSC, set_cond, dst, src1, src2); |
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284 } |
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285 |
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286 uint32_t rsci_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t cc, uint32_t set_cond) |
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287 { |
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288 return data_proci(code, cc, OP_RSC, set_cond, dst, src1, immed); |
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289 } |
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290 |
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291 uint32_t tst(code_info *code, uint32_t src1, uint32_t src2) |
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292 { |
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293 return data_proc(code, CC_AL, OP_TST, SET_COND, r0, src1, src2); |
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294 } |
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295 |
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296 uint32_t tsti(code_info *code, uint32_t src1, uint32_t immed) |
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297 { |
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298 return data_proci(code, CC_AL, OP_TST, SET_COND, r0, src1, immed); |
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|
299 } |
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|
300 |
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301 uint32_t tst_cc(code_info *code, uint32_t src1, uint32_t src2, uint32_t cc) |
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|
302 { |
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|
303 return data_proc(code, cc, OP_TST, SET_COND, r0, src1, src2); |
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|
304 } |
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diff
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|
305 |
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|
306 uint32_t tsti_cc(code_info *code, uint32_t src1, uint32_t immed, uint32_t cc) |
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|
307 { |
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diff
changeset
|
308 return data_proci(code, cc, OP_TST, SET_COND, r0, src1, immed); |
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|
309 } |
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|
310 |
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diff
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|
311 uint32_t teq(code_info *code, uint32_t src1, uint32_t src2) |
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|
312 { |
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|
313 return data_proc(code, CC_AL, OP_TEQ, SET_COND, r0, src1, src2); |
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|
314 } |
1af6c1052993
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Mike Pavone <pavone@retrodev.com>
parents:
diff
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|
315 |
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|
316 uint32_t teqi(code_info *code, uint32_t src1, uint32_t immed) |
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|
317 { |
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|
318 return data_proci(code, CC_AL, OP_TEQ, SET_COND, r0, src1, immed); |
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|
319 } |
1af6c1052993
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Mike Pavone <pavone@retrodev.com>
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diff
changeset
|
320 |
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Mike Pavone <pavone@retrodev.com>
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diff
changeset
|
321 uint32_t teq_cc(code_info *code, uint32_t src1, uint32_t src2, uint32_t cc) |
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diff
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|
322 { |
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diff
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|
323 return data_proc(code, cc, OP_TEQ, SET_COND, r0, src1, src2); |
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diff
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|
324 } |
1af6c1052993
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Mike Pavone <pavone@retrodev.com>
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diff
changeset
|
325 |
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Mike Pavone <pavone@retrodev.com>
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diff
changeset
|
326 uint32_t teqi_cc(code_info *code, uint32_t src1, uint32_t immed, uint32_t cc) |
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diff
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|
327 { |
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diff
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|
328 return data_proci(code, cc, OP_TEQ, SET_COND, r0, src1, immed); |
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|
329 } |
1af6c1052993
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
330 |
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Mike Pavone <pavone@retrodev.com>
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diff
changeset
|
331 uint32_t cmp(code_info *code, uint32_t src1, uint32_t src2) |
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diff
changeset
|
332 { |
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Mike Pavone <pavone@retrodev.com>
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diff
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|
333 return data_proc(code, CC_AL, OP_CMP, SET_COND, r0, src1, src2); |
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parents:
diff
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|
334 } |
1af6c1052993
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
335 |
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diff
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|
336 uint32_t cmpi(code_info *code, uint32_t src1, uint32_t immed) |
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diff
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|
337 { |
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Mike Pavone <pavone@retrodev.com>
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diff
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|
338 return data_proci(code, CC_AL, OP_CMP, SET_COND, r0, src1, immed); |
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diff
changeset
|
339 } |
1af6c1052993
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
340 |
1af6c1052993
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Mike Pavone <pavone@retrodev.com>
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diff
changeset
|
341 uint32_t cmp_cc(code_info *code, uint32_t src1, uint32_t src2, uint32_t cc) |
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diff
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|
342 { |
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diff
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|
343 return data_proc(code, cc, OP_CMP, SET_COND, r0, src1, src2); |
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diff
changeset
|
344 } |
1af6c1052993
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
345 |
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Mike Pavone <pavone@retrodev.com>
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diff
changeset
|
346 uint32_t cmpi_cc(code_info *code, uint32_t src1, uint32_t immed, uint32_t cc) |
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parents:
diff
changeset
|
347 { |
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diff
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|
348 return data_proci(code, cc, OP_CMP, SET_COND, r0, src1, immed); |
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parents:
diff
changeset
|
349 } |
1af6c1052993
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
350 |
1af6c1052993
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Mike Pavone <pavone@retrodev.com>
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diff
changeset
|
351 uint32_t cmn(code_info *code, uint32_t src1, uint32_t src2) |
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parents:
diff
changeset
|
352 { |
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
353 return data_proc(code, CC_AL, OP_CMN, SET_COND, r0, src1, src2); |
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parents:
diff
changeset
|
354 } |
1af6c1052993
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
355 |
1af6c1052993
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
356 uint32_t cmni(code_info *code, uint32_t src1, uint32_t immed) |
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parents:
diff
changeset
|
357 { |
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
358 return data_proci(code, CC_AL, OP_CMN, SET_COND, r0, src1, immed); |
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parents:
diff
changeset
|
359 } |
1af6c1052993
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
360 |
1af6c1052993
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
361 uint32_t cmn_cc(code_info *code, uint32_t src1, uint32_t src2, uint32_t cc) |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
362 { |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
363 return data_proc(code, cc, OP_CMN, SET_COND, r0, src1, src2); |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
364 } |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
365 |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
366 uint32_t cmni_cc(code_info *code, uint32_t src1, uint32_t immed, uint32_t cc) |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
367 { |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
368 return data_proci(code, cc, OP_CMN, SET_COND, r0, src1, immed); |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
369 } |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
370 |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
371 uint32_t orr(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t set_cond) |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
372 { |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
373 return data_proc(code, CC_AL, OP_ORR, set_cond, dst, src1, src2); |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
374 } |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
375 |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
376 uint32_t orri(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t set_cond) |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
377 { |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
378 return data_proci(code, CC_AL, OP_ORR, set_cond, dst, src1, immed); |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
379 } |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
380 |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
381 uint32_t orr_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t cc, uint32_t set_cond) |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
382 { |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
383 return data_proc(code, cc, OP_ORR, set_cond, dst, src1, src2); |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
384 } |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
385 |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
386 uint32_t orri_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t cc, uint32_t set_cond) |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
387 { |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
388 return data_proci(code, cc, OP_ORR, set_cond, dst, src1, immed); |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
389 } |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
390 |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
391 uint32_t mov(code_info *code, uint32_t dst, uint32_t src2, uint32_t set_cond) |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
392 { |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
393 return data_proc(code, CC_AL, OP_MOV, set_cond, dst, 0, src2); |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
394 } |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
395 |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
396 uint32_t movi(code_info *code, uint32_t dst, uint32_t immed, uint32_t set_cond) |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
397 { |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
398 return data_proci(code, CC_AL, OP_MOV, set_cond, dst, 0, immed); |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
399 } |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
400 |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
401 uint32_t mov_cc(code_info *code, uint32_t dst, uint32_t src2, uint32_t cc, uint32_t set_cond) |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
402 { |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
403 return data_proc(code, cc, OP_MOV, set_cond, dst, 0, src2); |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
404 } |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
405 |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
406 uint32_t movi_cc(code_info *code, uint32_t dst, uint32_t immed, uint32_t cc, uint32_t set_cond) |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
407 { |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
408 return data_proci(code, cc, OP_MOV, set_cond, dst, 0, immed); |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
409 } |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
410 |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
411 uint32_t bic(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t set_cond) |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
412 { |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
413 return data_proc(code, CC_AL, OP_BIC, set_cond, dst, src1, src2); |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
414 } |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
415 |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
416 uint32_t bici(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t set_cond) |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
417 { |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
418 return data_proci(code, CC_AL, OP_BIC, set_cond, dst, src1, immed); |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
419 } |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
420 |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
421 uint32_t bic_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t cc, uint32_t set_cond) |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
422 { |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
423 return data_proc(code, cc, OP_BIC, set_cond, dst, src1, src2); |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
424 } |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
425 |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
426 uint32_t bici_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t cc, uint32_t set_cond) |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
427 { |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
428 return data_proci(code, cc, OP_BIC, set_cond, dst, src1, immed); |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
429 } |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
430 |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
431 uint32_t mvn(code_info *code, uint32_t dst, uint32_t src2, uint32_t set_cond) |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
432 { |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
433 return data_proc(code, CC_AL, OP_MVN, set_cond, dst, 0, src2); |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
434 } |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
435 |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
436 uint32_t mvni(code_info *code, uint32_t dst, uint32_t immed, uint32_t set_cond) |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
437 { |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
438 return data_proci(code, CC_AL, OP_MVN, set_cond, dst, 0, immed); |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
439 } |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
440 |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
441 uint32_t mvn_cc(code_info *code, uint32_t dst, uint32_t src2, uint32_t cc, uint32_t set_cond) |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
442 { |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
443 return data_proc(code, cc, OP_MVN, set_cond, dst, 0, src2); |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
444 } |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
445 |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
446 uint32_t mvni_cc(code_info *code, uint32_t dst, uint32_t immed, uint32_t cc, uint32_t set_cond) |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
447 { |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
448 return data_proci(code, cc, OP_MVN, set_cond, dst, 0, immed); |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
449 } |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
450 |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
451 uint32_t branchi(code_info *code, uint32_t cc, uint32_t op, uint32_t *dst) |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
452 { |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
453 uint32_t * from = code->cur + 2; |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
454 if (dst - from >= 0x400000 && from - dst > 0x400000) { |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
455 return INVALID_IMMED; |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
456 } |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
457 check_alloc_code(code); |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
458 *(code->cur++) = cc | op | ((dst - from) & 0xFFFFFF); |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
459 return CODE_OK; |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
460 } |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
461 |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
462 uint32_t b(code_info *code, uint32_t *dst) |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
463 { |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
464 return branchi(code, CC_AL, OP_B, dst); |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
465 } |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
466 |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
467 uint32_t b_cc(code_info *code, uint32_t *dst, uint32_t cc) |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
468 { |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
469 return branchi(code, cc, OP_B, dst); |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
470 } |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
471 |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
472 uint32_t bl(code_info *code, uint32_t *dst) |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
473 { |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
474 return branchi(code, CC_AL, OP_BL, dst); |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
475 } |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
476 |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
477 uint32_t bl_cc(code_info *code, uint32_t *dst, uint32_t cc) |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
478 { |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
479 return branchi(code, cc, OP_BL, dst); |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
480 } |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
481 |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
482 uint32_t bx(code_info *code, uint32_t dst) |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
483 { |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
484 check_alloc_code(code); |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
485 *(code->cur++) = CC_AL | OP_BX | dst; |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
486 return CODE_OK; |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
487 } |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
488 |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
489 uint32_t bx_cc(code_info *code, uint32_t dst, uint32_t cc) |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
490 { |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
491 check_alloc_code(code); |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
492 *(code->cur++) = cc | OP_BX | dst; |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
493 return CODE_OK; |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
494 } |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
495 |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
496 uint32_t push(code_info *code, uint32_t reg) |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
497 { |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
498 check_alloc_code(code); |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
499 *(code->cur++) = CC_AL | PUSH | reg << 12; |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
500 return CODE_OK; |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
501 } |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
502 |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
503 uint32_t push_cc(code_info *code, uint32_t reg, uint32_t cc) |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
504 { |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
505 check_alloc_code(code); |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
506 *(code->cur++) = cc | PUSH | reg << 12; |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
507 return CODE_OK; |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
508 } |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
509 |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
510 uint32_t pushm(code_info *code, uint32_t reglist) |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
511 { |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
512 check_alloc_code(code); |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
513 *(code->cur++) = CC_AL | PUSHM | reglist; |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
514 return CODE_OK; |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
515 } |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
516 |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
517 uint32_t pushm_cc(code_info *code, uint32_t reglist, uint32_t cc) |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
518 { |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
519 check_alloc_code(code); |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
520 *(code->cur++) = cc | PUSHM | reglist; |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
521 return CODE_OK; |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
522 } |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
523 |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
524 uint32_t pop(code_info *code, uint32_t reg) |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
525 { |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
526 check_alloc_code(code); |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
527 *(code->cur++) = CC_AL | POP | reg << 12; |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
528 return CODE_OK; |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
529 } |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
530 |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
531 uint32_t pop_cc(code_info *code, uint32_t reg, uint32_t cc) |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
532 { |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
533 check_alloc_code(code); |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
534 *(code->cur++) = cc | POP | reg << 12; |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
535 return CODE_OK; |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
536 } |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
537 |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
538 uint32_t popm(code_info *code, uint32_t reglist) |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
539 { |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
540 check_alloc_code(code); |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
541 *(code->cur++) = CC_AL | POPM | reglist; |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
542 return CODE_OK; |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
543 } |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
544 |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
545 uint32_t popm_cc(code_info *code, uint32_t reglist, uint32_t cc) |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
546 { |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
547 check_alloc_code(code); |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
548 *(code->cur++) = cc | POPM | reglist; |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
549 return CODE_OK; |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
550 } |
684
bff307e03a94
Added ldr and str instructions to gen_arm
Michael Pavone <pavone@retrodev.com>
parents:
563
diff
changeset
|
551 |
bff307e03a94
Added ldr and str instructions to gen_arm
Michael Pavone <pavone@retrodev.com>
parents:
563
diff
changeset
|
552 uint32_t load_store_immoff(code_info *code, uint32_t op, uint32_t dst, uint32_t base, int32_t offset, uint32_t cc) |
bff307e03a94
Added ldr and str instructions to gen_arm
Michael Pavone <pavone@retrodev.com>
parents:
563
diff
changeset
|
553 { |
bff307e03a94
Added ldr and str instructions to gen_arm
Michael Pavone <pavone@retrodev.com>
parents:
563
diff
changeset
|
554 if (offset >= 0x1000 || offset <= -0x1000) { |
bff307e03a94
Added ldr and str instructions to gen_arm
Michael Pavone <pavone@retrodev.com>
parents:
563
diff
changeset
|
555 return INVALID_IMMED; |
bff307e03a94
Added ldr and str instructions to gen_arm
Michael Pavone <pavone@retrodev.com>
parents:
563
diff
changeset
|
556 } |
bff307e03a94
Added ldr and str instructions to gen_arm
Michael Pavone <pavone@retrodev.com>
parents:
563
diff
changeset
|
557 check_alloc_code(code); |
bff307e03a94
Added ldr and str instructions to gen_arm
Michael Pavone <pavone@retrodev.com>
parents:
563
diff
changeset
|
558 uint32_t instruction = cc | op | POST_IND | OFF_IMM | SZ_W | base << 16 | dst << 12; |
bff307e03a94
Added ldr and str instructions to gen_arm
Michael Pavone <pavone@retrodev.com>
parents:
563
diff
changeset
|
559 if (offset >= 0) { |
bff307e03a94
Added ldr and str instructions to gen_arm
Michael Pavone <pavone@retrodev.com>
parents:
563
diff
changeset
|
560 instruction |= offset | DIR_UP; |
bff307e03a94
Added ldr and str instructions to gen_arm
Michael Pavone <pavone@retrodev.com>
parents:
563
diff
changeset
|
561 } else { |
bff307e03a94
Added ldr and str instructions to gen_arm
Michael Pavone <pavone@retrodev.com>
parents:
563
diff
changeset
|
562 instruction |= (-offset) | DIR_DOWN; |
bff307e03a94
Added ldr and str instructions to gen_arm
Michael Pavone <pavone@retrodev.com>
parents:
563
diff
changeset
|
563 } |
bff307e03a94
Added ldr and str instructions to gen_arm
Michael Pavone <pavone@retrodev.com>
parents:
563
diff
changeset
|
564 *(code->cur++) = instruction; |
bff307e03a94
Added ldr and str instructions to gen_arm
Michael Pavone <pavone@retrodev.com>
parents:
563
diff
changeset
|
565 return CODE_OK; |
bff307e03a94
Added ldr and str instructions to gen_arm
Michael Pavone <pavone@retrodev.com>
parents:
563
diff
changeset
|
566 } |
bff307e03a94
Added ldr and str instructions to gen_arm
Michael Pavone <pavone@retrodev.com>
parents:
563
diff
changeset
|
567 |
bff307e03a94
Added ldr and str instructions to gen_arm
Michael Pavone <pavone@retrodev.com>
parents:
563
diff
changeset
|
568 uint32_t ldr_cc(code_info *code, uint32_t dst, uint32_t base, int32_t offset, uint32_t cc) |
bff307e03a94
Added ldr and str instructions to gen_arm
Michael Pavone <pavone@retrodev.com>
parents:
563
diff
changeset
|
569 { |
bff307e03a94
Added ldr and str instructions to gen_arm
Michael Pavone <pavone@retrodev.com>
parents:
563
diff
changeset
|
570 return load_store_immoff(code, OP_LDR, dst, base, offset, cc); |
bff307e03a94
Added ldr and str instructions to gen_arm
Michael Pavone <pavone@retrodev.com>
parents:
563
diff
changeset
|
571 } |
bff307e03a94
Added ldr and str instructions to gen_arm
Michael Pavone <pavone@retrodev.com>
parents:
563
diff
changeset
|
572 |
bff307e03a94
Added ldr and str instructions to gen_arm
Michael Pavone <pavone@retrodev.com>
parents:
563
diff
changeset
|
573 uint32_t ldr(code_info *code, uint32_t dst, uint32_t base, int32_t offset) |
bff307e03a94
Added ldr and str instructions to gen_arm
Michael Pavone <pavone@retrodev.com>
parents:
563
diff
changeset
|
574 { |
bff307e03a94
Added ldr and str instructions to gen_arm
Michael Pavone <pavone@retrodev.com>
parents:
563
diff
changeset
|
575 return ldr_cc(code, dst, base, offset, CC_AL); |
bff307e03a94
Added ldr and str instructions to gen_arm
Michael Pavone <pavone@retrodev.com>
parents:
563
diff
changeset
|
576 } |
bff307e03a94
Added ldr and str instructions to gen_arm
Michael Pavone <pavone@retrodev.com>
parents:
563
diff
changeset
|
577 |
bff307e03a94
Added ldr and str instructions to gen_arm
Michael Pavone <pavone@retrodev.com>
parents:
563
diff
changeset
|
578 uint32_t str_cc(code_info *code, uint32_t src, uint32_t base, int32_t offset, uint32_t cc) |
bff307e03a94
Added ldr and str instructions to gen_arm
Michael Pavone <pavone@retrodev.com>
parents:
563
diff
changeset
|
579 { |
bff307e03a94
Added ldr and str instructions to gen_arm
Michael Pavone <pavone@retrodev.com>
parents:
563
diff
changeset
|
580 return load_store_immoff(code, OP_STR, src, base, offset, cc); |
bff307e03a94
Added ldr and str instructions to gen_arm
Michael Pavone <pavone@retrodev.com>
parents:
563
diff
changeset
|
581 } |
bff307e03a94
Added ldr and str instructions to gen_arm
Michael Pavone <pavone@retrodev.com>
parents:
563
diff
changeset
|
582 |
bff307e03a94
Added ldr and str instructions to gen_arm
Michael Pavone <pavone@retrodev.com>
parents:
563
diff
changeset
|
583 uint32_t str(code_info *code, uint32_t src, uint32_t base, int32_t offset) |
bff307e03a94
Added ldr and str instructions to gen_arm
Michael Pavone <pavone@retrodev.com>
parents:
563
diff
changeset
|
584 { |
bff307e03a94
Added ldr and str instructions to gen_arm
Michael Pavone <pavone@retrodev.com>
parents:
563
diff
changeset
|
585 return str_cc(code, src, base, offset, CC_AL); |
bff307e03a94
Added ldr and str instructions to gen_arm
Michael Pavone <pavone@retrodev.com>
parents:
563
diff
changeset
|
586 } |