Mercurial > repos > blastem
annotate vdp.c @ 900:30efd12b1be1
Replace some hard-coded instruction length assumptions with a calculation so they will work properly on both 32-bit and 64-bit hosts
author | Michael Pavone <pavone@retrodev.com> |
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date | Fri, 27 Nov 2015 10:47:35 -0800 |
parents | 252dfd29831d |
children | e64168bb2b25 |
rev | line source |
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1 /* |
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2 Copyright 2013 Michael Pavone |
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Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
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3 This file is part of BlastEm. |
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4 BlastEm is free software distributed under the terms of the GNU General Public License version 3 or greater. See COPYING for full license text. |
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5 */ |
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6 #include "vdp.h" |
75 | 7 #include "blastem.h" |
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8 #include <stdlib.h> |
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9 #include <string.h> |
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10 #include "render.h" |
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11 |
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Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
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12 #define NTSC_INACTIVE_START 224 |
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13 #define PAL_INACTIVE_START 240 |
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14 #define BUF_BIT_PRIORITY 0x40 |
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15 #define MAP_BIT_PRIORITY 0x8000 |
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16 #define MAP_BIT_H_FLIP 0x800 |
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17 #define MAP_BIT_V_FLIP 0x1000 |
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18 |
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19 #define SCROLL_BUFFER_SIZE 32 |
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20 #define SCROLL_BUFFER_MASK (SCROLL_BUFFER_SIZE-1) |
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21 #define SCROLL_BUFFER_DRAW (SCROLL_BUFFER_SIZE/2) |
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22 |
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23 #define MCLKS_SLOT_H40 16 |
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24 #define MCLKS_SLOT_H32 20 |
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25 #define VINT_SLOT_H40 4 //21 slots before HSYNC, 16 during, 10 after |
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Adjust H32 vint slot in response to latest test ROM data
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26 #define VINT_SLOT_H32 4 //old value was 23, but recent tests suggest the actual value is close to the H40 one |
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Sync fixes and logging to fix more sync issues
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27 #define HSYNC_SLOT_H40 234 |
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28 #define HSYNC_END_H40 (HSYNC_SLOT_H40+17) |
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29 #define HSYNC_END_H32 (33 * MCLKS_SLOT_H32) |
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30 #define HBLANK_START_H40 178 //should be 179 according to Nemesis, but 178 seems to fit slightly better with my test ROM results |
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31 #define HBLANK_END_H40 0 //should be 5.5 according to Nemesis, but 0 seems to fit better with my test ROM results |
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32 #define HBLANK_START_H32 233 //should be 147 according to Nemesis which is very different from my test ROM result |
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33 #define HBLANK_END_H32 0 //should be 5 according to Nemesis, but 0 seems to fit better with my test ROM results |
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34 #define LINE_CHANGE_H40 165 |
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35 #define LINE_CHANGE_H32 132 |
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Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
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36 #define VBLANK_START_H40 (LINE_CHANGE_H40+2) |
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37 #define VBLANK_START_H32 (LINE_CHANGE_H32+2) |
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38 #define FIFO_LATENCY 3 |
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39 |
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40 int32_t color_map[1 << 12]; |
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41 uint8_t levels[] = {0, 27, 49, 71, 87, 103, 119, 130, 146, 157, 174, 190, 206, 228, 255}; |
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42 |
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43 uint8_t debug_base[][3] = { |
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44 {127, 127, 127}, //BG |
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45 {0, 0, 127}, //A |
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46 {127, 0, 0}, //Window |
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47 {0, 127, 0}, //B |
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48 {127, 0, 127} //Sprites |
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49 }; |
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50 |
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51 uint8_t color_map_init_done; |
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52 |
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53 void init_vdp_context(vdp_context * context, uint8_t region_pal) |
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54 { |
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55 memset(context, 0, sizeof(*context)); |
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56 context->vdpmem = malloc(VRAM_SIZE); |
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57 memset(context->vdpmem, 0, VRAM_SIZE); |
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58 /* |
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59 */ |
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60 if (headless) { |
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61 context->oddbuf = context->framebuf = malloc(FRAMEBUF_ENTRIES * (32 / 8)); |
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62 memset(context->framebuf, 0, FRAMEBUF_ENTRIES * (32 / 8)); |
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63 context->evenbuf = malloc(FRAMEBUF_ENTRIES * (32 / 8)); |
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The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
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64 memset(context->evenbuf, 0, FRAMEBUF_ENTRIES * (32 / 8)); |
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65 } else { |
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The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
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66 render_alloc_surfaces(context); |
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67 } |
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68 context->framebuf = context->oddbuf; |
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69 context->linebuf = malloc(LINEBUF_SIZE + SCROLL_BUFFER_SIZE*2); |
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70 memset(context->linebuf, 0, LINEBUF_SIZE + SCROLL_BUFFER_SIZE*2); |
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71 context->tmp_buf_a = context->linebuf + LINEBUF_SIZE; |
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72 context->tmp_buf_b = context->tmp_buf_a + SCROLL_BUFFER_SIZE; |
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73 context->sprite_draws = MAX_DRAWS; |
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74 context->fifo_write = 0; |
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75 context->fifo_read = -1; |
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76 |
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77 if (!color_map_init_done) { |
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78 uint8_t b,g,r; |
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79 for (uint16_t color = 0; color < (1 << 12); color++) { |
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80 if (color & FBUF_SHADOW) { |
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81 b = levels[(color >> 9) & 0x7]; |
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82 g = levels[(color >> 5) & 0x7]; |
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83 r = levels[(color >> 1) & 0x7]; |
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84 } else if(color & FBUF_HILIGHT) { |
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85 b = levels[((color >> 9) & 0x7) + 7]; |
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86 g = levels[((color >> 5) & 0x7) + 7]; |
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87 r = levels[((color >> 1) & 0x7) + 7]; |
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88 } else { |
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89 b = levels[(color >> 8) & 0xE]; |
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90 g = levels[(color >> 4) & 0xE]; |
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91 r = levels[color & 0xE]; |
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92 } |
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93 color_map[color] = render_map_color(r, g, b); |
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94 } |
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95 color_map_init_done = 1; |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
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96 } |
437
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97 for (uint8_t color = 0; color < (1 << (3 + 1 + 1 + 1)); color++) |
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|
98 { |
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99 uint8_t src = color & DBG_SRC_MASK; |
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100 if (src > DBG_SRC_S) { |
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101 context->debugcolors[color] = 0; |
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102 } else { |
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103 uint8_t r,g,b; |
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104 b = debug_base[src][0]; |
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105 g = debug_base[src][1]; |
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106 r = debug_base[src][2]; |
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107 if (color & DBG_PRIORITY) |
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|
108 { |
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109 if (b) { |
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110 b += 48; |
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111 } |
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112 if (g) { |
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113 g += 48; |
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114 } |
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115 if (r) { |
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116 r += 48; |
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117 } |
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118 } |
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119 if (color & DBG_SHADOW) { |
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120 b /= 2; |
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121 g /= 2; |
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122 r /=2 ; |
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123 } |
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124 if (color & DBG_HILIGHT) { |
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125 if (b) { |
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126 b += 72; |
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127 } |
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128 if (g) { |
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129 g += 72; |
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130 } |
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131 if (r) { |
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132 r += 72; |
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133 } |
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134 } |
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135 context->debugcolors[color] = render_map_color(r, g, b); |
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136 } |
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137 } |
623
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138 if (region_pal) { |
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139 context->flags2 |= FLAG2_REGION_PAL; |
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140 } |
20
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141 } |
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142 |
884
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143 void vdp_free(vdp_context *context) |
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144 { |
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145 free(context->vdpmem); |
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146 free(context->linebuf); |
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147 if (headless) { |
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148 free(context->oddbuf); |
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149 free(context->evenbuf); |
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150 } else { |
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151 render_free_surfaces(context); |
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152 } |
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153 free(context); |
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|
154 } |
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|
155 |
460
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|
156 int is_refresh(vdp_context * context, uint32_t slot) |
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157 { |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
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parents:
621
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|
158 if (context->regs[REG_MODE_4] & BIT_H40) { |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
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parents:
621
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|
159 return slot == 250 || slot == 26 || slot == 59 || slot == 90 || slot == 122 || slot == 154; |
460
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160 } else { |
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|
161 //TODO: Figure out which slots are refresh when display is off in 32-cell mode |
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diff
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|
162 //These numbers are guesses based on H40 numbers |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
163 return slot == 243 || slot == 19 || slot == 51 || slot == 83 || slot == 115; |
460
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parents:
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diff
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|
164 //The numbers below are the refresh slots during active display |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
165 //return (slot == 29 || slot == 61 || slot == 93 || slot == 125); |
460
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454
diff
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|
166 } |
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454
diff
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|
167 } |
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454
diff
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|
168 |
21
72ce60cb1711
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parents:
20
diff
changeset
|
169 void render_sprite_cells(vdp_context * context) |
20
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parents:
diff
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|
170 { |
21
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parents:
20
diff
changeset
|
171 if (context->cur_slot >= context->sprite_draws) { |
72ce60cb1711
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parents:
20
diff
changeset
|
172 sprite_draw * d = context->sprite_draw_list + context->cur_slot; |
450
3758bcdae5de
Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty
Mike Pavone <pavone@retrodev.com>
parents:
438
diff
changeset
|
173 |
20
f664eeb55cb4
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parents:
diff
changeset
|
174 uint16_t dir; |
f664eeb55cb4
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parents:
diff
changeset
|
175 int16_t x; |
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parents:
diff
changeset
|
176 if (d->h_flip) { |
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diff
changeset
|
177 x = d->x_pos + 7; |
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parents:
diff
changeset
|
178 dir = -1; |
f664eeb55cb4
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diff
changeset
|
179 } else { |
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diff
changeset
|
180 x = d->x_pos; |
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parents:
diff
changeset
|
181 dir = 1; |
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parents:
diff
changeset
|
182 } |
27
aa1c47fab3f1
Fix sprite transparency for overlapping sprites
Mike Pavone <pavone@retrodev.com>
parents:
26
diff
changeset
|
183 //printf("Draw Slot %d of %d, Rendering sprite cell from %X to x: %d\n", context->cur_slot, context->sprite_draws, d->address, x); |
26
a7c2b92d8056
Fix management of context->sprite_draws so the sprite layer only draws when it should
Mike Pavone <pavone@retrodev.com>
parents:
25
diff
changeset
|
184 context->cur_slot--; |
143
e5487ef04619
Fix infinite loop bug in sprite rendering
Mike Pavone <pavone@retrodev.com>
parents:
142
diff
changeset
|
185 for (uint16_t address = d->address; address != ((d->address+4) & 0xFFFF); address++) { |
27
aa1c47fab3f1
Fix sprite transparency for overlapping sprites
Mike Pavone <pavone@retrodev.com>
parents:
26
diff
changeset
|
186 if (x >= 0 && x < 320 && !(context->linebuf[x] & 0xF)) { |
494
8ac0eb05642c
Initial implementation of sprite overflow and sprite collision status register flags
Mike Pavone <pavone@retrodev.com>
parents:
481
diff
changeset
|
187 if (context->linebuf[x] && (context->vdpmem[address] >> 4)) { |
8ac0eb05642c
Initial implementation of sprite overflow and sprite collision status register flags
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parents:
481
diff
changeset
|
188 context->flags2 |= FLAG2_SPRITE_COLLIDE; |
8ac0eb05642c
Initial implementation of sprite overflow and sprite collision status register flags
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parents:
481
diff
changeset
|
189 } |
20
f664eeb55cb4
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parents:
diff
changeset
|
190 context->linebuf[x] = (context->vdpmem[address] >> 4) | d->pal_priority; |
f664eeb55cb4
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parents:
diff
changeset
|
191 } |
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parents:
diff
changeset
|
192 x += dir; |
27
aa1c47fab3f1
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Mike Pavone <pavone@retrodev.com>
parents:
26
diff
changeset
|
193 if (x >= 0 && x < 320 && !(context->linebuf[x] & 0xF)) { |
494
8ac0eb05642c
Initial implementation of sprite overflow and sprite collision status register flags
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parents:
481
diff
changeset
|
194 if (context->linebuf[x] && (context->vdpmem[address] & 0xF)) { |
8ac0eb05642c
Initial implementation of sprite overflow and sprite collision status register flags
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parents:
481
diff
changeset
|
195 context->flags2 |= FLAG2_SPRITE_COLLIDE; |
8ac0eb05642c
Initial implementation of sprite overflow and sprite collision status register flags
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parents:
481
diff
changeset
|
196 } |
20
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diff
changeset
|
197 context->linebuf[x] = (context->vdpmem[address] & 0xF) | d->pal_priority; |
f664eeb55cb4
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parents:
diff
changeset
|
198 } |
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parents:
diff
changeset
|
199 x += dir; |
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parents:
diff
changeset
|
200 } |
f664eeb55cb4
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parents:
diff
changeset
|
201 } |
f664eeb55cb4
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parents:
diff
changeset
|
202 } |
f664eeb55cb4
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parents:
diff
changeset
|
203 |
322
8e2fa485c0f2
Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview.
Mike Pavone <pavone@retrodev.com>
parents:
318
diff
changeset
|
204 void vdp_print_sprite_table(vdp_context * context) |
8e2fa485c0f2
Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview.
Mike Pavone <pavone@retrodev.com>
parents:
318
diff
changeset
|
205 { |
8e2fa485c0f2
Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview.
Mike Pavone <pavone@retrodev.com>
parents:
318
diff
changeset
|
206 uint16_t sat_address = (context->regs[REG_SAT] & 0x7F) << 9; |
8e2fa485c0f2
Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview.
Mike Pavone <pavone@retrodev.com>
parents:
318
diff
changeset
|
207 uint16_t current_index = 0; |
8e2fa485c0f2
Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview.
Mike Pavone <pavone@retrodev.com>
parents:
318
diff
changeset
|
208 uint8_t count = 0; |
8e2fa485c0f2
Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview.
Mike Pavone <pavone@retrodev.com>
parents:
318
diff
changeset
|
209 do { |
8e2fa485c0f2
Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview.
Mike Pavone <pavone@retrodev.com>
parents:
318
diff
changeset
|
210 uint16_t address = current_index * 8 + sat_address; |
8e2fa485c0f2
Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview.
Mike Pavone <pavone@retrodev.com>
parents:
318
diff
changeset
|
211 uint8_t height = ((context->vdpmem[address+2] & 0x3) + 1) * 8; |
8e2fa485c0f2
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212 uint8_t width = (((context->vdpmem[address+2] >> 2) & 0x3) + 1) * 8; |
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213 int16_t y = ((context->vdpmem[address] & 0x3) << 8 | context->vdpmem[address+1]) & 0x1FF; |
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214 int16_t x = ((context->vdpmem[address+ 6] & 0x3) << 8 | context->vdpmem[address + 7]) & 0x1FF; |
322
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215 uint16_t link = context->vdpmem[address+3] & 0x7F; |
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216 uint8_t pal = context->vdpmem[address + 4] >> 5 & 0x3; |
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217 uint8_t pri = context->vdpmem[address + 4] >> 7; |
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218 uint16_t pattern = ((context->vdpmem[address + 4] << 8 | context->vdpmem[address + 5]) & 0x7FF) << 5; |
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219 printf("Sprite %d: X=%d(%d), Y=%d(%d), Width=%u, Height=%u, Link=%u, Pal=%u, Pri=%u, Pat=%X\n", current_index, x, x-128, y, y-128, width, height, link, pal, pri, pattern); |
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220 current_index = link; |
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221 count++; |
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222 } while (current_index != 0 && count < 80); |
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223 } |
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224 |
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225 #define VRAM_READ 0 //0000 |
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226 #define VRAM_WRITE 1 //0001 |
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227 //2 would trigger register write 0010 |
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228 #define CRAM_WRITE 3 //0011 |
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229 #define VSRAM_READ 4 //0100 |
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230 #define VSRAM_WRITE 5//0101 |
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231 //6 would trigger regsiter write 0110 |
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232 //7 is a mystery |
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233 #define CRAM_READ 8 //1000 |
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234 //9 is also a mystery //1001 |
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235 //A would trigger register write 1010 |
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236 //B is a mystery 1011 |
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237 #define VRAM_READ8 0xC //1100 |
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238 //D is a mystery 1101 |
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239 //E would trigger register write 1110 |
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240 //F is a mystery 1111 |
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241 #define DMA_START 0x20 |
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242 |
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243 const char * cd_name(uint8_t cd) |
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244 { |
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245 switch (cd & 0xF) |
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246 { |
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247 case VRAM_READ: |
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248 return "VRAM read"; |
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249 case VRAM_WRITE: |
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250 return "VRAM write"; |
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251 case CRAM_WRITE: |
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252 return "CRAM write"; |
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253 case VSRAM_READ: |
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254 return "VSRAM read"; |
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255 case VSRAM_WRITE: |
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256 return "VSRAM write"; |
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257 case VRAM_READ8: |
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258 return "VRAM read (undocumented 8-bit mode)"; |
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259 default: |
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260 return "invalid"; |
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261 } |
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262 } |
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263 |
327
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264 void vdp_print_reg_explain(vdp_context * context) |
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265 { |
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266 char * hscroll[] = {"full", "7-line", "cell", "line"}; |
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267 printf("**Mode Group**\n" |
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268 "00: %.2X | H-ints %s, Pal Select %d, HVC latch %s, Display gen %s\n" |
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269 "01: %.2X | Display %s, V-ints %s, Height: %d, Mode %d\n" |
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270 "0B: %.2X | E-ints %s, V-Scroll: %s, H-Scroll: %s\n" |
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271 "0C: %.2X | Width: %d, Shadow/Highlight: %s\n", |
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272 context->regs[REG_MODE_1], context->regs[REG_MODE_1] & BIT_HINT_EN ? "enabled" : "disabled", (context->regs[REG_MODE_1] & BIT_PAL_SEL) != 0, |
327
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273 context->regs[REG_MODE_1] & BIT_HVC_LATCH ? "enabled" : "disabled", context->regs[REG_MODE_1] & BIT_DISP_DIS ? "disabled" : "enabled", |
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274 context->regs[REG_MODE_2], context->regs[REG_MODE_2] & BIT_DISP_EN ? "enabled" : "disabled", context->regs[REG_MODE_2] & BIT_VINT_EN ? "enabled" : "disabled", |
327
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275 context->regs[REG_MODE_2] & BIT_PAL ? 30 : 28, context->regs[REG_MODE_2] & BIT_MODE_5 ? 5 : 4, |
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276 context->regs[REG_MODE_3], context->regs[REG_MODE_3] & BIT_EINT_EN ? "enabled" : "disabled", context->regs[REG_MODE_3] & BIT_VSCROLL ? "2 cell" : "full", |
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277 hscroll[context->regs[REG_MODE_3] & 0x3], |
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278 context->regs[REG_MODE_4], context->regs[REG_MODE_4] & BIT_H40 ? 40 : 32, context->regs[REG_MODE_4] & BIT_HILIGHT ? "enabled" : "disabled"); |
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279 printf("\n**Table Group**\n" |
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280 "02: %.2X | Scroll A Name Table: $%.4X\n" |
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281 "03: %.2X | Window Name Table: $%.4X\n" |
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282 "04: %.2X | Scroll B Name Table: $%.4X\n" |
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283 "05: %.2X | Sprite Attribute Table: $%.4X\n" |
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284 "0D: %.2X | HScroll Data Table: $%.4X\n", |
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285 context->regs[REG_SCROLL_A], (context->regs[REG_SCROLL_A] & 0x38) << 10, |
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286 context->regs[REG_WINDOW], (context->regs[REG_WINDOW] & (context->regs[REG_MODE_4] & BIT_H40 ? 0x3C : 0x3E)) << 10, |
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287 context->regs[REG_SCROLL_B], (context->regs[REG_SCROLL_B] & 0x7) << 13, |
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288 context->regs[REG_SAT], (context->regs[REG_SAT] & (context->regs[REG_MODE_4] & BIT_H40 ? 0x7E : 0x7F)) << 9, |
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289 context->regs[REG_HSCROLL], (context->regs[REG_HSCROLL] & 0x3F) << 10); |
327
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290 char * sizes[] = {"32", "64", "invalid", "128"}; |
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291 printf("\n**Misc Group**\n" |
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292 "07: %.2X | Backdrop Color: $%X\n" |
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293 "0A: %.2X | H-Int Counter: %u\n" |
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294 "0F: %.2X | Auto-increment: $%X\n" |
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295 "10: %.2X | Scroll A/B Size: %sx%s\n", |
505
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The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
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296 context->regs[REG_BG_COLOR], context->regs[REG_BG_COLOR], |
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297 context->regs[REG_HINT], context->regs[REG_HINT], |
327
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298 context->regs[REG_AUTOINC], context->regs[REG_AUTOINC], |
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299 context->regs[REG_SCROLL], sizes[context->regs[REG_SCROLL] & 0x3], sizes[context->regs[REG_SCROLL] >> 4 & 0x3]); |
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300 char * src_types[] = {"68K", "68K", "Copy", "Fill"}; |
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301 printf("\n**DMA Group**\n" |
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302 "13: %.2X |\n" |
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303 "14: %.2X | DMA Length: $%.4X words\n" |
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304 "15: %.2X |\n" |
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305 "16: %.2X |\n" |
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306 "17: %.2X | DMA Source Address: $%.6X, Type: %s\n", |
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307 context->regs[REG_DMALEN_L], |
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308 context->regs[REG_DMALEN_H], context->regs[REG_DMALEN_H] << 8 | context->regs[REG_DMALEN_L], |
5196333b37a6
Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
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309 context->regs[REG_DMASRC_L], |
5196333b37a6
Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
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310 context->regs[REG_DMASRC_M], |
5196333b37a6
Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents:
515
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311 context->regs[REG_DMASRC_H], |
629
9089951a1994
Small fix to display of DMA source address in vr debug command
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312 context->regs[REG_DMASRC_H] << 17 | context->regs[REG_DMASRC_M] << 9 | context->regs[REG_DMASRC_L] << 1, |
621
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parents:
515
diff
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313 src_types[context->regs[REG_DMASRC_H] >> 6 & 3]); |
438
b3cee2fe690b
Add address/cd registers to VDP debug message
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314 printf("\n**Internal Group**\n" |
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315 "Address: %X\n" |
705
ce4046476abc
Add description of cd register value to vr debugger command
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316 "CD: %X - %s\n" |
647
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Fix the HV counter and adjust the slots of certain VDP events
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317 "Pending: %s\n" |
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318 "VCounter: %d\n" |
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319 "HCounter: %d\n", |
705
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320 context->address, context->cd, cd_name(context->cd), (context->flags & FLAG_PENDING) ? "true" : "false", |
647
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321 context->vcounter, context->hslot*2); |
450
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322 |
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323 //TODO: Window Group, DMA Group |
327
1b00258b1f29
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324 } |
1b00258b1f29
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325 |
20
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326 void scan_sprite_table(uint32_t line, vdp_context * context) |
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327 { |
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328 if (context->sprite_index && context->slot_counter) { |
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329 line += 1; |
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330 line &= 0xFF; |
413
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331 uint16_t ymask, ymin; |
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332 uint8_t height_mult; |
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333 if (context->double_res) { |
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334 line *= 2; |
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335 if (context->framebuf != context->oddbuf) { |
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336 line++; |
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337 } |
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338 ymask = 0x3FF; |
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339 ymin = 256; |
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340 height_mult = 16; |
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341 } else { |
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342 ymask = 0x1FF; |
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343 ymin = 128; |
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344 height_mult = 8; |
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345 } |
20
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346 context->sprite_index &= 0x7F; |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
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347 if (context->regs[REG_MODE_4] & BIT_H40) { |
38
898e3d035f42
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348 if (context->sprite_index >= MAX_SPRITES_FRAME) { |
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349 context->sprite_index = 0; |
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350 return; |
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351 } |
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352 } else if(context->sprite_index >= MAX_SPRITES_FRAME_H32) { |
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353 context->sprite_index = 0; |
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354 return; |
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|
355 } |
20
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356 //TODO: Read from SAT cache rather than from VRAM |
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357 uint16_t sat_address = (context->regs[REG_SAT] & 0x7F) << 9; |
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358 uint16_t address = context->sprite_index * 8 + sat_address; |
413
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diff
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359 line += ymin; |
415
8c60c8c09a0f
Fix sprite y mask in interlace mode. Fix framebuffer selection when switching out of interlace mode.
Mike Pavone <pavone@retrodev.com>
parents:
414
diff
changeset
|
360 uint16_t y = ((context->vdpmem[address] & 0x3) << 8 | context->vdpmem[address+1]) & ymask; |
413
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361 uint8_t height = ((context->vdpmem[address+2] & 0x3) + 1) * height_mult; |
21
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diff
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|
362 //printf("Sprite %d | y: %d, height: %d\n", context->sprite_index, y, height); |
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parents:
20
diff
changeset
|
363 if (y <= line && line < (y + height)) { |
27
aa1c47fab3f1
Fix sprite transparency for overlapping sprites
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26
diff
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|
364 //printf("Sprite %d at y: %d with height %d is on line %d\n", context->sprite_index, y, height, line); |
20
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365 context->sprite_info_list[--(context->slot_counter)].size = context->vdpmem[address+2]; |
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|
366 context->sprite_info_list[context->slot_counter].index = context->sprite_index; |
413
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|
367 context->sprite_info_list[context->slot_counter].y = y-ymin; |
20
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|
368 } |
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|
369 context->sprite_index = context->vdpmem[address+3] & 0x7F; |
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|
370 if (context->sprite_index && context->slot_counter) |
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diff
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|
371 { |
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|
372 address = context->sprite_index * 8 + sat_address; |
415
8c60c8c09a0f
Fix sprite y mask in interlace mode. Fix framebuffer selection when switching out of interlace mode.
Mike Pavone <pavone@retrodev.com>
parents:
414
diff
changeset
|
373 y = ((context->vdpmem[address] & 0x3) << 8 | context->vdpmem[address+1]) & ymask; |
413
36fbbced25c2
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diff
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|
374 height = ((context->vdpmem[address+2] & 0x3) + 1) * height_mult; |
323
8c01b4154480
Properly mask sprite X and Y coordinates
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parents:
322
diff
changeset
|
375 //printf("Sprite %d | y: %d, height: %d\n", context->sprite_index, y, height); |
21
72ce60cb1711
Sprites somewhat less broken
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parents:
20
diff
changeset
|
376 if (y <= line && line < (y + height)) { |
27
aa1c47fab3f1
Fix sprite transparency for overlapping sprites
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parents:
26
diff
changeset
|
377 //printf("Sprite %d at y: %d with height %d is on line %d\n", context->sprite_index, y, height, line); |
20
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diff
changeset
|
378 context->sprite_info_list[--(context->slot_counter)].size = context->vdpmem[address+2]; |
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diff
changeset
|
379 context->sprite_info_list[context->slot_counter].index = context->sprite_index; |
413
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|
380 context->sprite_info_list[context->slot_counter].y = y-ymin; |
20
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|
381 } |
21
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20
diff
changeset
|
382 context->sprite_index = context->vdpmem[address+3] & 0x7F; |
20
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|
383 } |
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diff
changeset
|
384 } |
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diff
changeset
|
385 } |
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diff
changeset
|
386 |
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diff
changeset
|
387 void read_sprite_x(uint32_t line, vdp_context * context) |
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diff
changeset
|
388 { |
34
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
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32
diff
changeset
|
389 if (context->cur_slot >= context->slot_counter) { |
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32
diff
changeset
|
390 if (context->sprite_draws) { |
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32
diff
changeset
|
391 line += 1; |
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diff
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|
392 line &= 0xFF; |
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diff
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|
393 //in tiles |
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diff
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|
394 uint8_t width = ((context->sprite_info_list[context->cur_slot].size >> 2) & 0x3) + 1; |
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diff
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|
395 //in pixels |
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diff
changeset
|
396 uint8_t height = ((context->sprite_info_list[context->cur_slot].size & 0x3) + 1) * 8; |
413
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changeset
|
397 if (context->double_res) { |
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|
398 line *= 2; |
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|
399 if (context->framebuf != context->oddbuf) { |
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|
400 line++; |
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changeset
|
401 } |
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|
402 height *= 2; |
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|
403 } |
34
0e7df84158b1
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32
diff
changeset
|
404 uint16_t att_addr = ((context->regs[REG_SAT] & 0x7F) << 9) + context->sprite_info_list[context->cur_slot].index * 8 + 4; |
450
3758bcdae5de
Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty
Mike Pavone <pavone@retrodev.com>
parents:
438
diff
changeset
|
405 uint16_t tileinfo = (context->vdpmem[att_addr] << 8) | context->vdpmem[att_addr+1]; |
34
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
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32
diff
changeset
|
406 uint8_t pal_priority = (tileinfo >> 9) & 0x70; |
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Improve sprite masking to almost completely pass Nemesis' sprite masking test
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32
diff
changeset
|
407 uint8_t row; |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
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32
diff
changeset
|
408 if (tileinfo & MAP_BIT_V_FLIP) { |
0e7df84158b1
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32
diff
changeset
|
409 row = (context->sprite_info_list[context->cur_slot].y + height - 1) - line; |
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32
diff
changeset
|
410 } else { |
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32
diff
changeset
|
411 row = line-context->sprite_info_list[context->cur_slot].y; |
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32
diff
changeset
|
412 } |
413
36fbbced25c2
Initial work on interlace
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337
diff
changeset
|
413 uint16_t address; |
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diff
changeset
|
414 if (context->double_res) { |
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changeset
|
415 address = ((tileinfo & 0x3FF) << 6) + row * 4; |
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changeset
|
416 } else { |
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|
417 address = ((tileinfo & 0x7FF) << 5) + row * 4; |
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diff
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|
418 } |
323
8c01b4154480
Properly mask sprite X and Y coordinates
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322
diff
changeset
|
419 int16_t x = ((context->vdpmem[att_addr+ 2] & 0x3) << 8 | context->vdpmem[att_addr + 3]) & 0x1FF; |
36
04672c060062
Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents:
35
diff
changeset
|
420 if (x) { |
04672c060062
Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents:
35
diff
changeset
|
421 context->flags |= FLAG_CAN_MASK; |
04672c060062
Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents:
35
diff
changeset
|
422 } else if(context->flags & (FLAG_CAN_MASK | FLAG_DOT_OFLOW)) { |
04672c060062
Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents:
35
diff
changeset
|
423 context->flags |= FLAG_MASKED; |
04672c060062
Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents:
35
diff
changeset
|
424 } |
450
3758bcdae5de
Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty
Mike Pavone <pavone@retrodev.com>
parents:
438
diff
changeset
|
425 |
36
04672c060062
Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents:
35
diff
changeset
|
426 context->flags &= ~FLAG_DOT_OFLOW; |
04672c060062
Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents:
35
diff
changeset
|
427 int16_t i; |
04672c060062
Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents:
35
diff
changeset
|
428 if (context->flags & FLAG_MASKED) { |
04672c060062
Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents:
35
diff
changeset
|
429 for (i=0; i < width && context->sprite_draws; i++) { |
04672c060062
Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents:
35
diff
changeset
|
430 --context->sprite_draws; |
04672c060062
Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents:
35
diff
changeset
|
431 context->sprite_draw_list[context->sprite_draws].x_pos = -128; |
34
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
432 } |
36
04672c060062
Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents:
35
diff
changeset
|
433 } else { |
34
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
434 x -= 128; |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
435 int16_t base_x = x; |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
436 int16_t dir; |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
437 if (tileinfo & MAP_BIT_H_FLIP) { |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
438 x += (width-1) * 8; |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
439 dir = -8; |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
440 } else { |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
441 dir = 8; |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
442 } |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
443 //printf("Sprite %d | x: %d, y: %d, width: %d, height: %d, pal_priority: %X, row: %d, tile addr: %X\n", context->sprite_info_list[context->cur_slot].index, x, context->sprite_info_list[context->cur_slot].y, width, height, pal_priority, row, address); |
35
233c7737c152
Small fix to overflow flag
Mike Pavone <pavone@retrodev.com>
parents:
34
diff
changeset
|
444 for (i=0; i < width && context->sprite_draws; i++, x += dir) { |
34
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
445 --context->sprite_draws; |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
446 context->sprite_draw_list[context->sprite_draws].address = address + i * height * 4; |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
447 context->sprite_draw_list[context->sprite_draws].x_pos = x; |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
448 context->sprite_draw_list[context->sprite_draws].pal_priority = pal_priority; |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
449 context->sprite_draw_list[context->sprite_draws].h_flip = (tileinfo & MAP_BIT_H_FLIP) ? 1 : 0; |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
450 } |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
451 } |
36
04672c060062
Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents:
35
diff
changeset
|
452 if (i < width) { |
04672c060062
Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents:
35
diff
changeset
|
453 context->flags |= FLAG_DOT_OFLOW; |
04672c060062
Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents:
35
diff
changeset
|
454 } |
04672c060062
Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents:
35
diff
changeset
|
455 context->cur_slot--; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
456 } else { |
34
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
457 context->flags |= FLAG_DOT_OFLOW; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
458 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
459 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
460 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
461 |
427
2802318c14e1
Refactor duplicated CRAM writing code and fix a bug in the process
Mike Pavone <pavone@retrodev.com>
parents:
426
diff
changeset
|
462 void write_cram(vdp_context * context, uint16_t address, uint16_t value) |
2802318c14e1
Refactor duplicated CRAM writing code and fix a bug in the process
Mike Pavone <pavone@retrodev.com>
parents:
426
diff
changeset
|
463 { |
2802318c14e1
Refactor duplicated CRAM writing code and fix a bug in the process
Mike Pavone <pavone@retrodev.com>
parents:
426
diff
changeset
|
464 uint16_t addr = (address/2) & (CRAM_SIZE-1); |
2802318c14e1
Refactor duplicated CRAM writing code and fix a bug in the process
Mike Pavone <pavone@retrodev.com>
parents:
426
diff
changeset
|
465 context->cram[addr] = value; |
2802318c14e1
Refactor duplicated CRAM writing code and fix a bug in the process
Mike Pavone <pavone@retrodev.com>
parents:
426
diff
changeset
|
466 context->colors[addr] = color_map[value & 0xEEE]; |
2802318c14e1
Refactor duplicated CRAM writing code and fix a bug in the process
Mike Pavone <pavone@retrodev.com>
parents:
426
diff
changeset
|
467 context->colors[addr + CRAM_SIZE] = color_map[(value & 0xEEE) | FBUF_SHADOW]; |
2802318c14e1
Refactor duplicated CRAM writing code and fix a bug in the process
Mike Pavone <pavone@retrodev.com>
parents:
426
diff
changeset
|
468 context->colors[addr + CRAM_SIZE*2] = color_map[(value & 0xEEE) | FBUF_HILIGHT]; |
2802318c14e1
Refactor duplicated CRAM writing code and fix a bug in the process
Mike Pavone <pavone@retrodev.com>
parents:
426
diff
changeset
|
469 } |
2802318c14e1
Refactor duplicated CRAM writing code and fix a bug in the process
Mike Pavone <pavone@retrodev.com>
parents:
426
diff
changeset
|
470 |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
471 void external_slot(vdp_context * context) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
472 { |
471
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
473 fifo_entry * start = context->fifo + context->fifo_read; |
474
e128e55710bd
Remove read pending stuff, that had been added in an attempt to fix CRAM/VSRAM undefined bit results. Set number of bits actually saved in VSRAM to 11
Mike Pavone <pavone@retrodev.com>
parents:
473
diff
changeset
|
474 /*if (context->flags2 & FLAG2_READ_PENDING) { |
470
541c1ae8abf3
Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
475 context->flags2 &= ~FLAG2_READ_PENDING; |
541c1ae8abf3
Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
476 context->flags |= FLAG_UNUSED_SLOT; |
541c1ae8abf3
Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
477 return; |
474
e128e55710bd
Remove read pending stuff, that had been added in an attempt to fix CRAM/VSRAM undefined bit results. Set number of bits actually saved in VSRAM to 11
Mike Pavone <pavone@retrodev.com>
parents:
473
diff
changeset
|
478 }*/ |
471
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
479 if (context->fifo_read >= 0 && start->cycle <= context->cycles) { |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
480 switch (start->cd & 0xF) |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
481 { |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
482 case VRAM_WRITE: |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
483 if (start->partial) { |
471
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
484 //printf("VRAM Write: %X to %X at %d (line %d, slot %d)\n", start->value, start->address ^ 1, context->cycles, context->cycles/MCLKS_LINE, (context->cycles%MCLKS_LINE)/16); |
478
2e4a4188cfb0
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents:
477
diff
changeset
|
485 context->vdpmem[start->address ^ 1] = start->partial == 2 ? start->value >> 8 : start->value; |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
486 } else { |
471
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
487 //printf("VRAM Write High: %X to %X at %d (line %d, slot %d)\n", start->value >> 8, start->address, context->cycles, context->cycles/MCLKS_LINE, (context->cycles%MCLKS_LINE)/16); |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
488 context->vdpmem[start->address] = start->value >> 8; |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
489 start->partial = 1; |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
490 //skip auto-increment and removal of entry from fifo |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
491 return; |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
492 } |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
493 break; |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
494 case CRAM_WRITE: { |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
495 //printf("CRAM Write | %X to %X\n", start->value, (start->address/2) & (CRAM_SIZE-1)); |
479
863e868752cf
Implement funny behavior for DMA fill to CRAM and VSRAM. Return VSRAM address 0 for reads to VSRAM at >= 40
Mike Pavone <pavone@retrodev.com>
parents:
478
diff
changeset
|
496 write_cram(context, start->address, start->partial == 2 ? context->fifo[context->fifo_write].value : start->value); |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
497 break; |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
498 } |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
499 case VSRAM_WRITE: |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
500 if (((start->address/2) & 63) < VSRAM_SIZE) { |
718
eaba6789f316
Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents:
717
diff
changeset
|
501 //printf("VSRAM Write: %X to %X @ vcounter: %d, hslot: %d, cycle: %d\n", start->value, context->address, context->vcounter, context->hslot, context->cycles); |
479
863e868752cf
Implement funny behavior for DMA fill to CRAM and VSRAM. Return VSRAM address 0 for reads to VSRAM at >= 40
Mike Pavone <pavone@retrodev.com>
parents:
478
diff
changeset
|
502 context->vsram[(start->address/2) & 63] = start->partial == 2 ? context->fifo[context->fifo_write].value : start->value; |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
503 } |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
504 |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
505 break; |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
506 } |
471
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
507 context->fifo_read = (context->fifo_read+1) & (FIFO_SIZE-1); |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
508 if (context->fifo_read == context->fifo_write) { |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
509 context->fifo_read = -1; |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
510 } |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
511 context->flags &= ~FLAG_UNUSED_SLOT; |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
512 } else { |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
513 context->flags |= FLAG_UNUSED_SLOT; |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
514 } |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
515 } |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
516 |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
517 void run_dma_src(vdp_context * context, uint32_t slot) |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
518 { |
75 | 519 //TODO: Figure out what happens if CD bit 4 is not set in DMA copy mode |
520 //TODO: Figure out what happens when CD:0-3 is not set to a write mode in DMA operations | |
521 //TODO: Figure out what happens if DMA gets disabled part way through a DMA fill or DMA copy | |
471
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
522 if (context->fifo_write == context->fifo_read) { |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
523 return; |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
524 } |
478
2e4a4188cfb0
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents:
477
diff
changeset
|
525 fifo_entry * cur = NULL; |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
526 switch(context->regs[REG_DMASRC_H] & 0xC0) |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
527 { |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
528 //68K -> VDP |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
529 case 0: |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
530 case 0x40: |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
531 if (!slot || !is_refresh(context, slot-1)) { |
478
2e4a4188cfb0
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents:
477
diff
changeset
|
532 cur = context->fifo + context->fifo_write; |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
533 cur->cycle = context->cycles + ((context->regs[REG_MODE_4] & BIT_H40) ? 16 : 20)*FIFO_LATENCY; |
478
2e4a4188cfb0
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents:
477
diff
changeset
|
534 cur->address = context->address; |
2e4a4188cfb0
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents:
477
diff
changeset
|
535 cur->value = read_dma_value((context->regs[REG_DMASRC_H] << 16) | (context->regs[REG_DMASRC_M] << 8) | context->regs[REG_DMASRC_L]); |
2e4a4188cfb0
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents:
477
diff
changeset
|
536 cur->cd = context->cd; |
2e4a4188cfb0
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents:
477
diff
changeset
|
537 cur->partial = 0; |
2e4a4188cfb0
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents:
477
diff
changeset
|
538 if (context->fifo_read < 0) { |
2e4a4188cfb0
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents:
477
diff
changeset
|
539 context->fifo_read = context->fifo_write; |
2e4a4188cfb0
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents:
477
diff
changeset
|
540 } |
2e4a4188cfb0
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents:
477
diff
changeset
|
541 context->fifo_write = (context->fifo_write + 1) & (FIFO_SIZE-1); |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
542 } |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
543 break; |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
544 //Copy |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
545 case 0xC0: |
478
2e4a4188cfb0
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents:
477
diff
changeset
|
546 if (context->flags & FLAG_UNUSED_SLOT && context->fifo_read < 0) { |
2e4a4188cfb0
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents:
477
diff
changeset
|
547 //TODO: Fix this to not use the FIFO at all once read-caching is properly implemented |
2e4a4188cfb0
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents:
477
diff
changeset
|
548 context->fifo_read = (context->fifo_write-1) & (FIFO_SIZE-1); |
2e4a4188cfb0
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents:
477
diff
changeset
|
549 cur = context->fifo + context->fifo_read; |
2e4a4188cfb0
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents:
477
diff
changeset
|
550 cur->cycle = context->cycles; |
2e4a4188cfb0
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents:
477
diff
changeset
|
551 cur->address = context->address; |
2e4a4188cfb0
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents:
477
diff
changeset
|
552 cur->partial = 1; |
2e4a4188cfb0
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents:
477
diff
changeset
|
553 cur->value = context->vdpmem[(context->regs[REG_DMASRC_M] << 8) | context->regs[REG_DMASRC_L] ^ 1] | (cur->value & 0xFF00); |
2e4a4188cfb0
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents:
477
diff
changeset
|
554 cur->cd = VRAM_WRITE; |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
555 context->flags &= ~FLAG_UNUSED_SLOT; |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
556 } |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
557 break; |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
558 case 0x80: |
478
2e4a4188cfb0
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents:
477
diff
changeset
|
559 if (context->fifo_read < 0) { |
2e4a4188cfb0
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents:
477
diff
changeset
|
560 context->fifo_read = (context->fifo_write-1) & (FIFO_SIZE-1); |
2e4a4188cfb0
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents:
477
diff
changeset
|
561 cur = context->fifo + context->fifo_read; |
2e4a4188cfb0
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents:
477
diff
changeset
|
562 cur->cycle = context->cycles; |
2e4a4188cfb0
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents:
477
diff
changeset
|
563 cur->address = context->address; |
2e4a4188cfb0
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents:
477
diff
changeset
|
564 cur->partial = 2; |
2e4a4188cfb0
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents:
477
diff
changeset
|
565 } |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
566 break; |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
567 } |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
568 |
478
2e4a4188cfb0
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents:
477
diff
changeset
|
569 if (cur) { |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
570 context->regs[REG_DMASRC_L] += 1; |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
571 if (!context->regs[REG_DMASRC_L]) { |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
572 context->regs[REG_DMASRC_M] += 1; |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
573 } |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
574 context->address += context->regs[REG_AUTOINC]; |
478
2e4a4188cfb0
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents:
477
diff
changeset
|
575 uint16_t dma_len = ((context->regs[REG_DMALEN_H] << 8) | context->regs[REG_DMALEN_L]) - 1; |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
576 context->regs[REG_DMALEN_H] = dma_len >> 8; |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
577 context->regs[REG_DMALEN_L] = dma_len; |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
578 if (!dma_len) { |
717
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
579 //printf("DMA end at cycle %d, frame: %d, vcounter: %d, hslot: %d\n", context->cycles, context->frame, context->vcounter, context->hslot); |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
580 context->flags &= ~FLAG_DMA_RUN; |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
581 context->cd &= 0xF; |
75 | 582 } |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
583 } |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
584 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
585 |
40 | 586 #define WINDOW_RIGHT 0x80 |
587 #define WINDOW_DOWN 0x80 | |
588 | |
25
4d0c20ad815a
Fix vertical scroll value for plane B
Mike Pavone <pavone@retrodev.com>
parents:
24
diff
changeset
|
589 void read_map_scroll(uint16_t column, uint16_t vsram_off, uint32_t line, uint16_t address, uint16_t hscroll_val, vdp_context * context) |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
590 { |
417
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
415
diff
changeset
|
591 uint16_t window_line_shift, v_offset_mask, vscroll_shift; |
414
51ee0f117365
Fix vscroll calculation in double resultion interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
413
diff
changeset
|
592 if (context->double_res) { |
413
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
593 line *= 2; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
594 if (context->framebuf != context->oddbuf) { |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
595 line++; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
596 } |
417
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
415
diff
changeset
|
597 window_line_shift = 4; |
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
415
diff
changeset
|
598 v_offset_mask = 0xF; |
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
415
diff
changeset
|
599 vscroll_shift = 4; |
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
415
diff
changeset
|
600 } else { |
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
415
diff
changeset
|
601 window_line_shift = 3; |
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
415
diff
changeset
|
602 v_offset_mask = 0x7; |
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
415
diff
changeset
|
603 vscroll_shift = 3; |
414
51ee0f117365
Fix vscroll calculation in double resultion interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
413
diff
changeset
|
604 } |
40 | 605 if (!vsram_off) { |
606 uint16_t left_col, right_col; | |
607 if (context->regs[REG_WINDOW_H] & WINDOW_RIGHT) { | |
41
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
608 left_col = (context->regs[REG_WINDOW_H] & 0x1F) * 2; |
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
609 right_col = 42; |
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
610 } else { |
40 | 611 left_col = 0; |
612 right_col = (context->regs[REG_WINDOW_H] & 0x1F) * 2; | |
613 if (right_col) { | |
614 right_col += 2; | |
615 } | |
616 } | |
41
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
617 uint16_t top_line, bottom_line; |
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
618 if (context->regs[REG_WINDOW_V] & WINDOW_DOWN) { |
417
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
415
diff
changeset
|
619 top_line = (context->regs[REG_WINDOW_V] & 0x1F) << window_line_shift; |
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
415
diff
changeset
|
620 bottom_line = context->double_res ? 481 : 241; |
41
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
621 } else { |
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
622 top_line = 0; |
417
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
415
diff
changeset
|
623 bottom_line = (context->regs[REG_WINDOW_V] & 0x1F) << window_line_shift; |
41
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
624 } |
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
625 if ((column >= left_col && column < right_col) || (line >= top_line && line < bottom_line)) { |
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
626 uint16_t address = context->regs[REG_WINDOW] << 10; |
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
627 uint16_t line_offset, offset, mask; |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
628 if (context->regs[REG_MODE_4] & BIT_H40) { |
41
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
629 address &= 0xF000; |
417
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
415
diff
changeset
|
630 line_offset = (((line) >> vscroll_shift) * 64 * 2) & 0xFFF; |
41
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
631 mask = 0x7F; |
450
3758bcdae5de
Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty
Mike Pavone <pavone@retrodev.com>
parents:
438
diff
changeset
|
632 |
41
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
633 } else { |
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
634 address &= 0xF800; |
417
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
415
diff
changeset
|
635 line_offset = (((line) >> vscroll_shift) * 32 * 2) & 0xFFF; |
41
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
636 mask = 0x3F; |
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
637 } |
417
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
415
diff
changeset
|
638 if (context->double_res) { |
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
415
diff
changeset
|
639 mask <<= 1; |
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
415
diff
changeset
|
640 mask |= 1; |
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
415
diff
changeset
|
641 } |
42
6653e67a6811
Fix bug in tile address masking. Remove some debug code from window plane.
Mike Pavone <pavone@retrodev.com>
parents:
41
diff
changeset
|
642 offset = address + line_offset + (((column - 2) * 2) & mask); |
41
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
643 context->col_1 = (context->vdpmem[offset] << 8) | context->vdpmem[offset+1]; |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
644 //printf("Window | top: %d, bot: %d, left: %d, right: %d, base: %X, line: %X offset: %X, tile: %X, reg: %X\n", top_line, bottom_line, left_col, right_col, address, line_offset, offset, ((context->col_1 & 0x3FF) << 5), context->regs[REG_WINDOW]); |
42
6653e67a6811
Fix bug in tile address masking. Remove some debug code from window plane.
Mike Pavone <pavone@retrodev.com>
parents:
41
diff
changeset
|
645 offset = address + line_offset + (((column - 1) * 2) & mask); |
41
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
646 context->col_2 = (context->vdpmem[offset] << 8) | context->vdpmem[offset+1]; |
417
acdd6c5240fe
Fix window layer in double res interlace mode
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parents:
415
diff
changeset
|
647 context->v_offset = (line) & v_offset_mask; |
41
e591004487bc
More correct window support, maybe
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parents:
40
diff
changeset
|
648 context->flags |= FLAG_WINDOW; |
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
649 return; |
40 | 650 } |
651 context->flags &= ~FLAG_WINDOW; | |
652 } | |
20
f664eeb55cb4
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parents:
diff
changeset
|
653 uint16_t vscroll; |
f664eeb55cb4
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parents:
diff
changeset
|
654 switch(context->regs[REG_SCROLL] & 0x30) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
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parents:
diff
changeset
|
655 { |
f664eeb55cb4
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parents:
diff
changeset
|
656 case 0: |
f664eeb55cb4
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diff
changeset
|
657 vscroll = 0xFF; |
f664eeb55cb4
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parents:
diff
changeset
|
658 break; |
f664eeb55cb4
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parents:
diff
changeset
|
659 case 0x10: |
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diff
changeset
|
660 vscroll = 0x1FF; |
f664eeb55cb4
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parents:
diff
changeset
|
661 break; |
f664eeb55cb4
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parents:
diff
changeset
|
662 case 0x20: |
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diff
changeset
|
663 //TODO: Verify this behavior |
f664eeb55cb4
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diff
changeset
|
664 vscroll = 0; |
f664eeb55cb4
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diff
changeset
|
665 break; |
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parents:
diff
changeset
|
666 case 0x30: |
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diff
changeset
|
667 vscroll = 0x3FF; |
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parents:
diff
changeset
|
668 break; |
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parents:
diff
changeset
|
669 } |
414
51ee0f117365
Fix vscroll calculation in double resultion interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
413
diff
changeset
|
670 if (context->double_res) { |
413
36fbbced25c2
Initial work on interlace
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671 vscroll <<= 1; |
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672 vscroll |= 1; |
414
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Fix vscroll calculation in double resultion interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
413
diff
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|
673 } |
718
eaba6789f316
Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents:
717
diff
changeset
|
674 //TODO: Further research on vscroll latch behavior and the "first column bug" |
eaba6789f316
Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents:
717
diff
changeset
|
675 if (!column) { |
eaba6789f316
Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents:
717
diff
changeset
|
676 if (context->regs[REG_MODE_3] & BIT_VSCROLL) { |
eaba6789f316
Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents:
717
diff
changeset
|
677 if (context->regs[REG_MODE_4] & BIT_H40) { |
eaba6789f316
Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents:
717
diff
changeset
|
678 //Based on observed behavior documented by Eke-Eke, I'm guessing the VDP |
eaba6789f316
Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents:
717
diff
changeset
|
679 //ends up fetching the last value on the VSRAM bus in the H40 case |
eaba6789f316
Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents:
717
diff
changeset
|
680 //getting the last latched value should be close enough for now |
eaba6789f316
Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents:
717
diff
changeset
|
681 if (!vsram_off) { |
eaba6789f316
Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents:
717
diff
changeset
|
682 context->vscroll_latch[0] = context->vscroll_latch[1]; |
eaba6789f316
Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents:
717
diff
changeset
|
683 } |
eaba6789f316
Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents:
717
diff
changeset
|
684 } else { |
eaba6789f316
Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents:
717
diff
changeset
|
685 //supposedly it's always forced to 0 in the H32 case |
eaba6789f316
Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents:
717
diff
changeset
|
686 context->vscroll_latch[0] = context->vscroll_latch[1] = 0; |
eaba6789f316
Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents:
717
diff
changeset
|
687 } |
eaba6789f316
Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents:
717
diff
changeset
|
688 } else { |
eaba6789f316
Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents:
717
diff
changeset
|
689 context->vscroll_latch[vsram_off] = context->vsram[vsram_off]; |
eaba6789f316
Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents:
717
diff
changeset
|
690 } |
eaba6789f316
Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents:
717
diff
changeset
|
691 } else if (context->regs[REG_MODE_3] & BIT_VSCROLL) { |
710
4cd8823f79e3
First pass at emulating a vscroll latch. Titan's Overdrive demo seems to depend on the scroll value being latched early in the line before the HINT gets a chance to change it
Michael Pavone <pavone@retrodev.com>
parents:
708
diff
changeset
|
692 context->vscroll_latch[vsram_off] = context->vsram[column - 2 + vsram_off]; |
4cd8823f79e3
First pass at emulating a vscroll latch. Titan's Overdrive demo seems to depend on the scroll value being latched early in the line before the HINT gets a chance to change it
Michael Pavone <pavone@retrodev.com>
parents:
708
diff
changeset
|
693 } |
4cd8823f79e3
First pass at emulating a vscroll latch. Titan's Overdrive demo seems to depend on the scroll value being latched early in the line before the HINT gets a chance to change it
Michael Pavone <pavone@retrodev.com>
parents:
708
diff
changeset
|
694 vscroll &= context->vscroll_latch[vsram_off] + line; |
414
51ee0f117365
Fix vscroll calculation in double resultion interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
413
diff
changeset
|
695 context->v_offset = vscroll & v_offset_mask; |
26
a7c2b92d8056
Fix management of context->sprite_draws so the sprite layer only draws when it should
Mike Pavone <pavone@retrodev.com>
parents:
25
diff
changeset
|
696 //printf("%s | line %d, vsram: %d, vscroll: %d, v_offset: %d\n",(vsram_off ? "B" : "A"), line, context->vsram[context->regs[REG_MODE_3] & 0x4 ? column : 0], vscroll, context->v_offset); |
414
51ee0f117365
Fix vscroll calculation in double resultion interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
413
diff
changeset
|
697 vscroll >>= vscroll_shift; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
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parents:
diff
changeset
|
698 uint16_t hscroll_mask; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
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parents:
diff
changeset
|
699 uint16_t v_mul; |
f664eeb55cb4
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parents:
diff
changeset
|
700 switch(context->regs[REG_SCROLL] & 0x3) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
701 { |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
702 case 0: |
108
1a551a85cb06
Fix horizontal mask values for scroll plane map address calculation
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
703 hscroll_mask = 0x1F; |
20
f664eeb55cb4
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
704 v_mul = 64; |
f664eeb55cb4
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
705 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
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parents:
diff
changeset
|
706 case 0x1: |
39
3c69319269ef
Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should
Mike Pavone <pavone@retrodev.com>
parents:
38
diff
changeset
|
707 hscroll_mask = 0x3F; |
20
f664eeb55cb4
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parents:
diff
changeset
|
708 v_mul = 128; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
709 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
710 case 0x2: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
711 //TODO: Verify this behavior |
f664eeb55cb4
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
712 hscroll_mask = 0; |
f664eeb55cb4
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parents:
diff
changeset
|
713 v_mul = 0; |
f664eeb55cb4
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
714 break; |
f664eeb55cb4
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parents:
diff
changeset
|
715 case 0x3: |
108
1a551a85cb06
Fix horizontal mask values for scroll plane map address calculation
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
716 hscroll_mask = 0x7F; |
20
f664eeb55cb4
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parents:
diff
changeset
|
717 v_mul = 256; |
f664eeb55cb4
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
718 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
719 } |
28 | 720 uint16_t hscroll, offset; |
721 for (int i = 0; i < 2; i++) { | |
39
3c69319269ef
Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should
Mike Pavone <pavone@retrodev.com>
parents:
38
diff
changeset
|
722 hscroll = (column - 2 + i - ((hscroll_val/8) & 0xFFFE)) & hscroll_mask; |
3c69319269ef
Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should
Mike Pavone <pavone@retrodev.com>
parents:
38
diff
changeset
|
723 offset = address + ((vscroll * v_mul + hscroll*2) & 0x1FFF); |
3c69319269ef
Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should
Mike Pavone <pavone@retrodev.com>
parents:
38
diff
changeset
|
724 //printf("%s | line: %d, col: %d, x: %d, hs_mask %X, scr reg: %X, tbl addr: %X\n", (vsram_off ? "B" : "A"), line, (column-2+i), hscroll, hscroll_mask, context->regs[REG_SCROLL], offset); |
28 | 725 uint16_t col_val = (context->vdpmem[offset] << 8) | context->vdpmem[offset+1]; |
726 if (i) { | |
727 context->col_2 = col_val; | |
728 } else { | |
729 context->col_1 = col_val; | |
730 } | |
731 } | |
20
f664eeb55cb4
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parents:
diff
changeset
|
732 } |
f664eeb55cb4
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
733 |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
734 void read_map_scroll_a(uint16_t column, uint32_t line, vdp_context * context) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
735 { |
25
4d0c20ad815a
Fix vertical scroll value for plane B
Mike Pavone <pavone@retrodev.com>
parents:
24
diff
changeset
|
736 read_map_scroll(column, 0, line, (context->regs[REG_SCROLL_A] & 0x38) << 10, context->hscroll_a, context); |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
737 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
738 |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
739 void read_map_scroll_b(uint16_t column, uint32_t line, vdp_context * context) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
740 { |
25
4d0c20ad815a
Fix vertical scroll value for plane B
Mike Pavone <pavone@retrodev.com>
parents:
24
diff
changeset
|
741 read_map_scroll(column, 1, line, (context->regs[REG_SCROLL_B] & 0x7) << 13, context->hscroll_b, context); |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
742 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
743 |
436
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
744 void render_map(uint16_t col, uint8_t * tmp_buf, uint8_t offset, vdp_context * context) |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
745 { |
413
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
746 uint16_t address; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
747 uint8_t shift, add; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
748 if (context->double_res) { |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
749 address = ((col & 0x3FF) << 6); |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
750 shift = 1; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
751 add = context->framebuf != context->oddbuf ? 1 : 0; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
752 } else { |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
753 address = ((col & 0x7FF) << 5); |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
754 shift = 0; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
755 add = 0; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
756 } |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
757 if (col & MAP_BIT_V_FLIP) { |
414
51ee0f117365
Fix vscroll calculation in double resultion interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
413
diff
changeset
|
758 address += 28 - 4 * context->v_offset/*((context->v_offset << shift) + add)*/; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
759 } else { |
414
51ee0f117365
Fix vscroll calculation in double resultion interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
413
diff
changeset
|
760 address += 4 * context->v_offset/*((context->v_offset << shift) + add)*/; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
761 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
762 uint16_t pal_priority = (col >> 9) & 0x70; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
763 int32_t dir; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
764 if (col & MAP_BIT_H_FLIP) { |
436
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
765 offset += 7; |
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
766 offset &= SCROLL_BUFFER_MASK; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
767 dir = -1; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
768 } else { |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
769 dir = 1; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
770 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
771 for (uint32_t i=0; i < 4; i++, address++) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
772 { |
436
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
773 tmp_buf[offset] = pal_priority | (context->vdpmem[address] >> 4); |
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
774 offset += dir; |
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
775 offset &= SCROLL_BUFFER_MASK; |
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
776 tmp_buf[offset] = pal_priority | (context->vdpmem[address] & 0xF); |
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
777 offset += dir; |
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
778 offset &= SCROLL_BUFFER_MASK; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
779 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
780 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
781 |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
782 void render_map_1(vdp_context * context) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
783 { |
436
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
784 render_map(context->col_1, context->tmp_buf_a, context->buf_a_off, context); |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
785 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
786 |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
787 void render_map_2(vdp_context * context) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
788 { |
436
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
789 render_map(context->col_2, context->tmp_buf_a, context->buf_a_off+8, context); |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
790 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
791 |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
792 void render_map_3(vdp_context * context) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
793 { |
436
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
794 render_map(context->col_1, context->tmp_buf_b, context->buf_b_off, context); |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
795 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
796 |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
797 void render_map_output(uint32_t line, int32_t col, vdp_context * context) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
798 { |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
799 if (line >= 240) { |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
800 return; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
801 } |
436
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
802 render_map(context->col_2, context->tmp_buf_b, context->buf_b_off+8, context); |
719
019d27995e32
Upgrade to SDL 2.0 and drop support for the non-OpenGL render path
Michael Pavone <pavone@retrodev.com>
parents:
718
diff
changeset
|
803 uint32_t *dst; |
436
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
804 uint8_t *sprite_buf, *plane_a, *plane_b; |
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
805 int plane_a_off, plane_b_off; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
806 if (col) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
807 { |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
808 col-=2; |
719
019d27995e32
Upgrade to SDL 2.0 and drop support for the non-OpenGL render path
Michael Pavone <pavone@retrodev.com>
parents:
718
diff
changeset
|
809 dst = context->framebuf; |
019d27995e32
Upgrade to SDL 2.0 and drop support for the non-OpenGL render path
Michael Pavone <pavone@retrodev.com>
parents:
718
diff
changeset
|
810 dst += line * 320 + col * 8; |
722
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
811 if (context->debug < 2) { |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
812 sprite_buf = context->linebuf + col * 8; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
813 uint8_t a_src, src; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
814 if (context->flags & FLAG_WINDOW) { |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
815 plane_a_off = context->buf_a_off; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
816 a_src = DBG_SRC_W; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
817 } else { |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
818 plane_a_off = context->buf_a_off - (context->hscroll_a & 0xF); |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
819 a_src = DBG_SRC_A; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
820 } |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
821 plane_b_off = context->buf_b_off - (context->hscroll_b & 0xF); |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
822 //printf("A | tmp_buf offset: %d\n", 8 - (context->hscroll_a & 0x7)); |
450
3758bcdae5de
Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty
Mike Pavone <pavone@retrodev.com>
parents:
438
diff
changeset
|
823 |
722
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
824 if (context->regs[REG_MODE_4] & BIT_HILIGHT) { |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
825 for (int i = 0; i < 16; ++plane_a_off, ++plane_b_off, ++sprite_buf, ++i) { |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
826 plane_a = context->tmp_buf_a + (plane_a_off & SCROLL_BUFFER_MASK); |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
827 plane_b = context->tmp_buf_b + (plane_b_off & SCROLL_BUFFER_MASK); |
748
45b62d237b7b
Fixed shadow/highlight mode
Michael Pavone <pavone@retrodev.com>
parents:
724
diff
changeset
|
828 uint8_t pixel = context->regs[REG_BG_COLOR]; |
45b62d237b7b
Fixed shadow/highlight mode
Michael Pavone <pavone@retrodev.com>
parents:
724
diff
changeset
|
829 uint32_t *colors = context->colors; |
722
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
830 src = DBG_SRC_BG; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
831 if (*plane_b & 0xF) { |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
832 pixel = *plane_b; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
833 src = DBG_SRC_B; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
834 } |
748
45b62d237b7b
Fixed shadow/highlight mode
Michael Pavone <pavone@retrodev.com>
parents:
724
diff
changeset
|
835 uint8_t intensity = *plane_b & BUF_BIT_PRIORITY; |
722
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
836 if (*plane_a & 0xF && (*plane_a & BUF_BIT_PRIORITY) >= (pixel & BUF_BIT_PRIORITY)) { |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
837 pixel = *plane_a; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
838 src = DBG_SRC_A; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
839 } |
748
45b62d237b7b
Fixed shadow/highlight mode
Michael Pavone <pavone@retrodev.com>
parents:
724
diff
changeset
|
840 intensity |= *plane_a & BUF_BIT_PRIORITY; |
45b62d237b7b
Fixed shadow/highlight mode
Michael Pavone <pavone@retrodev.com>
parents:
724
diff
changeset
|
841 if (*sprite_buf & 0xF && (*sprite_buf & BUF_BIT_PRIORITY) >= (pixel & BUF_BIT_PRIORITY)) { |
45b62d237b7b
Fixed shadow/highlight mode
Michael Pavone <pavone@retrodev.com>
parents:
724
diff
changeset
|
842 if ((*sprite_buf & 0x3F) == 0x3E) { |
45b62d237b7b
Fixed shadow/highlight mode
Michael Pavone <pavone@retrodev.com>
parents:
724
diff
changeset
|
843 intensity += BUF_BIT_PRIORITY; |
45b62d237b7b
Fixed shadow/highlight mode
Michael Pavone <pavone@retrodev.com>
parents:
724
diff
changeset
|
844 } else if ((*sprite_buf & 0x3F) == 0x3F) { |
45b62d237b7b
Fixed shadow/highlight mode
Michael Pavone <pavone@retrodev.com>
parents:
724
diff
changeset
|
845 intensity = 0; |
45b62d237b7b
Fixed shadow/highlight mode
Michael Pavone <pavone@retrodev.com>
parents:
724
diff
changeset
|
846 } else { |
722
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
847 pixel = *sprite_buf; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
848 src = DBG_SRC_S; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
849 if ((pixel & 0xF) == 0xE) { |
748
45b62d237b7b
Fixed shadow/highlight mode
Michael Pavone <pavone@retrodev.com>
parents:
724
diff
changeset
|
850 intensity = BUF_BIT_PRIORITY; |
45b62d237b7b
Fixed shadow/highlight mode
Michael Pavone <pavone@retrodev.com>
parents:
724
diff
changeset
|
851 } else { |
45b62d237b7b
Fixed shadow/highlight mode
Michael Pavone <pavone@retrodev.com>
parents:
724
diff
changeset
|
852 intensity |= pixel & BUF_BIT_PRIORITY; |
722
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
853 } |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
854 } |
748
45b62d237b7b
Fixed shadow/highlight mode
Michael Pavone <pavone@retrodev.com>
parents:
724
diff
changeset
|
855 } |
45b62d237b7b
Fixed shadow/highlight mode
Michael Pavone <pavone@retrodev.com>
parents:
724
diff
changeset
|
856 if (!intensity) { |
505
b7b7a1cab44a
The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents:
503
diff
changeset
|
857 src |= DBG_SHADOW; |
748
45b62d237b7b
Fixed shadow/highlight mode
Michael Pavone <pavone@retrodev.com>
parents:
724
diff
changeset
|
858 colors += CRAM_SIZE; |
45b62d237b7b
Fixed shadow/highlight mode
Michael Pavone <pavone@retrodev.com>
parents:
724
diff
changeset
|
859 } else if (intensity == BUF_BIT_PRIORITY*2) { |
45b62d237b7b
Fixed shadow/highlight mode
Michael Pavone <pavone@retrodev.com>
parents:
724
diff
changeset
|
860 src |= DBG_HILIGHT; |
45b62d237b7b
Fixed shadow/highlight mode
Michael Pavone <pavone@retrodev.com>
parents:
724
diff
changeset
|
861 colors += CRAM_SIZE*2; |
722
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
862 } |
884
252dfd29831d
Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents:
822
diff
changeset
|
863 |
722
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
864 uint32_t outpixel; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
865 if (context->debug) { |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
866 outpixel = context->debugcolors[src]; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
867 } else { |
748
45b62d237b7b
Fixed shadow/highlight mode
Michael Pavone <pavone@retrodev.com>
parents:
724
diff
changeset
|
868 outpixel = colors[pixel & 0x3F]; |
722
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
869 } |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
870 *(dst++) = outpixel; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
871 } |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
872 } else { |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
873 for (int i = 0; i < 16; ++plane_a_off, ++plane_b_off, ++sprite_buf, ++i) { |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
874 plane_a = context->tmp_buf_a + (plane_a_off & SCROLL_BUFFER_MASK); |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
875 plane_b = context->tmp_buf_b + (plane_b_off & SCROLL_BUFFER_MASK); |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
876 uint8_t pixel = context->regs[REG_BG_COLOR]; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
877 src = DBG_SRC_BG; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
878 if (*plane_b & 0xF) { |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
879 pixel = *plane_b; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
880 src = DBG_SRC_B; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
881 } |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
882 if (*plane_a & 0xF && (*plane_a & BUF_BIT_PRIORITY) >= (pixel & BUF_BIT_PRIORITY)) { |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
883 pixel = *plane_a; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
884 src = DBG_SRC_A; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
885 } |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
886 if (*sprite_buf & 0xF && (*sprite_buf & BUF_BIT_PRIORITY) >= (pixel & BUF_BIT_PRIORITY)) { |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
887 pixel = *sprite_buf; |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
888 src = DBG_SRC_S; |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
889 } |
722
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
890 uint32_t outpixel; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
891 if (context->debug) { |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
892 outpixel = context->debugcolors[src]; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
893 } else { |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
894 outpixel = context->colors[pixel & 0x3F]; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
895 } |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
896 *(dst++) = outpixel; |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
897 } |
722
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
898 } |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
899 } else if (context->debug == 2) { |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
900 if (col < 32) { |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
901 *(dst++) = context->colors[col * 2]; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
902 *(dst++) = context->colors[col * 2]; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
903 *(dst++) = context->colors[col * 2]; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
904 *(dst++) = context->colors[col * 2]; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
905 *(dst++) = context->colors[col * 2 + 1]; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
906 *(dst++) = context->colors[col * 2 + 1]; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
907 *(dst++) = context->colors[col * 2 + 1]; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
908 *(dst++) = context->colors[col * 2 + 1]; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
909 *(dst++) = context->colors[col * 2 + 2]; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
910 *(dst++) = context->colors[col * 2 + 2]; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
911 *(dst++) = context->colors[col * 2 + 2]; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
912 *(dst++) = context->colors[col * 2 + 2]; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
913 *(dst++) = context->colors[col * 2 + 3]; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
914 *(dst++) = context->colors[col * 2 + 3]; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
915 *(dst++) = context->colors[col * 2 + 3]; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
916 *(dst++) = context->colors[col * 2 + 3]; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
917 } else if (col == 32 || line >= 192) { |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
918 for (int32_t i = 0; i < 16; i ++) { |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
919 *(dst++) = 0; |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
920 } |
722
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
921 } else { |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
922 for (int32_t i = 0; i < 16; i ++) { |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
923 *(dst++) = context->colors[line / 3 + (col - 34) * 0x20]; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
924 } |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
925 } |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
926 } else { |
771
0565b2c1a034
Add ability to change start address for VRAM viewer. Fix handling of DMA enable flag when it comes to DMA fills. This fixes a bug in James Pond 3
Michael Pavone <pavone@retrodev.com>
parents:
757
diff
changeset
|
927 uint32_t base = (context->debug - 3) * 0x200; |
0565b2c1a034
Add ability to change start address for VRAM viewer. Fix handling of DMA enable flag when it comes to DMA fills. This fixes a bug in James Pond 3
Michael Pavone <pavone@retrodev.com>
parents:
757
diff
changeset
|
928 uint32_t cell = base + (line / 8) * (context->regs[REG_MODE_4] & BIT_H40 ? 40 : 32) + col; |
0565b2c1a034
Add ability to change start address for VRAM viewer. Fix handling of DMA enable flag when it comes to DMA fills. This fixes a bug in James Pond 3
Michael Pavone <pavone@retrodev.com>
parents:
757
diff
changeset
|
929 uint32_t address = (cell * 32 + (line % 8) * 4) & 0xFFFF; |
722
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
930 for (int32_t i = 0; i < 4; i ++) { |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
931 *(dst++) = context->colors[(context->debug_pal << 4) | (context->vdpmem[address] >> 4)]; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
932 *(dst++) = context->colors[(context->debug_pal << 4) | (context->vdpmem[address] & 0xF)]; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
933 address++; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
934 } |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
935 cell++; |
771
0565b2c1a034
Add ability to change start address for VRAM viewer. Fix handling of DMA enable flag when it comes to DMA fills. This fixes a bug in James Pond 3
Michael Pavone <pavone@retrodev.com>
parents:
757
diff
changeset
|
936 address = (cell * 32 + (line % 8) * 4) & 0xFFFF; |
722
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
937 for (int32_t i = 0; i < 4; i ++) { |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
938 *(dst++) = context->colors[(context->debug_pal << 4) | (context->vdpmem[address] >> 4)]; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
939 *(dst++) = context->colors[(context->debug_pal << 4) | (context->vdpmem[address] & 0xF)]; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
940 address++; |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
941 } |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
942 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
943 } |
436
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
944 context->buf_a_off = (context->buf_a_off + SCROLL_BUFFER_DRAW) & SCROLL_BUFFER_MASK; |
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
945 context->buf_b_off = (context->buf_b_off + SCROLL_BUFFER_DRAW) & SCROLL_BUFFER_MASK; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
946 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
947 |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
948 uint32_t const h40_hsync_cycles[] = {19, 20, 20, 20, 18, 20, 20, 20, 18, 20, 20, 20, 18, 20, 20, 20, 19}; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
949 |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
950 void vdp_advance_line(vdp_context *context) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
951 { |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
952 context->vcounter++; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
953 context->vcounter &= 0x1FF; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
954 if (context->flags2 & FLAG2_REGION_PAL) { |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
955 if (context->latched_mode & BIT_PAL) { |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
956 if (context->vcounter == 0x10B) { |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
957 context->vcounter = 0x1D2; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
958 } |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
959 } else if (context->vcounter == 0x103){ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
960 context->vcounter = 0x1CA; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
961 } |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
962 } else if (!(context->latched_mode & BIT_PAL) && context->vcounter == 0xEB) { |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
963 context->vcounter = 0x1E5; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
964 } |
884
252dfd29831d
Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents:
822
diff
changeset
|
965 |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
966 if (context->vcounter > (context->latched_mode & BIT_PAL ? PAL_INACTIVE_START : NTSC_INACTIVE_START)) { |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
967 context->hint_counter = context->regs[REG_HINT]; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
968 } else if (context->hint_counter) { |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
969 context->hint_counter--; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
970 } else { |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
971 context->flags2 |= FLAG2_HINT_PENDING; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
972 context->pending_hint_start = context->cycles; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
973 context->hint_counter = context->regs[REG_HINT]; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
974 } |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
975 } |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
976 |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
977 #define CHECK_ONLY if (context->cycles >= target_cycles) { return; } |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
978 #define CHECK_LIMIT if (context->flags & FLAG_DMA_RUN) { run_dma_src(context, context->hslot); } context->hslot++; context->cycles += slot_cycles; CHECK_ONLY |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
979 |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
980 #define COLUMN_RENDER_BLOCK(column, startcyc) \ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
981 case startcyc:\ |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
982 read_map_scroll_a(column, context->vcounter, context);\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
983 CHECK_LIMIT\ |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
984 case (startcyc+1):\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
985 external_slot(context);\ |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
986 CHECK_LIMIT\ |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
987 case (startcyc+2):\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
988 render_map_1(context);\ |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
989 CHECK_LIMIT\ |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
990 case (startcyc+3):\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
991 render_map_2(context);\ |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
992 CHECK_LIMIT\ |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
993 case (startcyc+4):\ |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
994 read_map_scroll_b(column, context->vcounter, context);\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
995 CHECK_LIMIT\ |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
996 case (startcyc+5):\ |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
997 read_sprite_x(context->vcounter, context);\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
998 CHECK_LIMIT\ |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
999 case (startcyc+6):\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1000 render_map_3(context);\ |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1001 CHECK_LIMIT\ |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1002 case (startcyc+7):\ |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1003 render_map_output(context->vcounter, column, context);\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1004 CHECK_LIMIT |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1005 |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1006 #define COLUMN_RENDER_BLOCK_REFRESH(column, startcyc) \ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1007 case startcyc:\ |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1008 read_map_scroll_a(column, context->vcounter, context);\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1009 CHECK_LIMIT\ |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1010 case (startcyc+1):\ |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1011 /* refresh, no don't run dma src */\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1012 context->hslot++;\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1013 context->cycles += slot_cycles;\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1014 CHECK_ONLY\ |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1015 case (startcyc+2):\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1016 render_map_1(context);\ |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1017 CHECK_LIMIT\ |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1018 case (startcyc+3):\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1019 render_map_2(context);\ |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1020 CHECK_LIMIT\ |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1021 case (startcyc+4):\ |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1022 read_map_scroll_b(column, context->vcounter, context);\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1023 CHECK_LIMIT\ |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1024 case (startcyc+5):\ |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1025 read_sprite_x(context->vcounter, context);\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1026 CHECK_LIMIT\ |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1027 case (startcyc+6):\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1028 render_map_3(context);\ |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1029 CHECK_LIMIT\ |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1030 case (startcyc+7):\ |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1031 render_map_output(context->vcounter, column, context);\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1032 if (column == 40 || (column == 32 && startcyc == 124)) {\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1033 vdp_advance_line(context);\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1034 }\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1035 CHECK_LIMIT |
884
252dfd29831d
Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents:
822
diff
changeset
|
1036 |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1037 #define SPRITE_RENDER_H40(slot) \ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1038 case slot:\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1039 render_sprite_cells( context);\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1040 scan_sprite_table(context->vcounter, context);\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1041 if (context->flags & FLAG_DMA_RUN) { run_dma_src(context, context->hslot); } \ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1042 if (slot == 182) {\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1043 context->hslot = 229;\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1044 context->cycles += slot_cycles;\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1045 } else {\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1046 context->hslot++;\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1047 if (slot >= HSYNC_SLOT_H40 && slot < HSYNC_END_H40) {\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1048 context->cycles += h40_hsync_cycles[slot - HSYNC_SLOT_H40];\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1049 } else {\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1050 context->cycles += slot_cycles;\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1051 }\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1052 }\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1053 CHECK_ONLY |
884
252dfd29831d
Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents:
822
diff
changeset
|
1054 |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1055 #define SPRITE_RENDER_H32(slot) \ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1056 case slot:\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1057 render_sprite_cells( context);\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1058 scan_sprite_table(context->vcounter, context);\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1059 if (context->flags & FLAG_DMA_RUN) { run_dma_src(context, context->hslot); } \ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1060 if (slot == 147) {\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1061 context->hslot = 233;\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1062 } else {\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1063 context->hslot++;\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1064 }\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1065 context->cycles += slot_cycles;\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1066 CHECK_ONLY |
884
252dfd29831d
Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents:
822
diff
changeset
|
1067 |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1068 |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1069 void vdp_h40(vdp_context * context, uint32_t target_cycles) |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1070 { |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1071 uint16_t address; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1072 uint32_t mask; |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1073 uint32_t const slot_cycles = MCLKS_SLOT_H40; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1074 switch(context->hslot) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1075 { |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1076 for (;;) |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1077 { |
647
5d58dcd94733
Fix the HV counter and adjust the slots of certain VDP events
Michael Pavone <pavone@retrodev.com>
parents:
629
diff
changeset
|
1078 case 165: |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1079 external_slot(context); |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1080 CHECK_LIMIT |
647
5d58dcd94733
Fix the HV counter and adjust the slots of certain VDP events
Michael Pavone <pavone@retrodev.com>
parents:
629
diff
changeset
|
1081 case 166: |
5d58dcd94733
Fix the HV counter and adjust the slots of certain VDP events
Michael Pavone <pavone@retrodev.com>
parents:
629
diff
changeset
|
1082 external_slot(context); |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1083 CHECK_LIMIT |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1084 //sprite render to line buffer starts |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1085 case 167: |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1086 context->cur_slot = MAX_DRAWS-1; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1087 memset(context->linebuf, 0, LINEBUF_SIZE); |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1088 if (context->vcounter == 0x1FF) { |
329
fd5f6577db9b
Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents:
328
diff
changeset
|
1089 external_slot(context); |
fd5f6577db9b
Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents:
328
diff
changeset
|
1090 } else { |
fd5f6577db9b
Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents:
328
diff
changeset
|
1091 render_sprite_cells(context); |
fd5f6577db9b
Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents:
328
diff
changeset
|
1092 } |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1093 CHECK_LIMIT |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1094 case 168: |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1095 if (context->vcounter == 0x1FF) { |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1096 external_slot(context); |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1097 } else { |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1098 render_sprite_cells(context); |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1099 } |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1100 CHECK_LIMIT |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1101 case 169: |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1102 if (context->vcounter == 0x1FF) { |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1103 external_slot(context); |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1104 } else { |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1105 render_sprite_cells(context); |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1106 } |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1107 CHECK_LIMIT |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1108 case 170: |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1109 if (context->vcounter == 0x1FF) { |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1110 external_slot(context); |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1111 } else { |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1112 render_sprite_cells(context); |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1113 if (context->vcounter == (context->latched_mode & BIT_PAL ? PAL_INACTIVE_START : NTSC_INACTIVE_START)) { |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1114 context->hslot++; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1115 context->cycles += slot_cycles; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1116 return; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1117 } |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1118 } |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1119 CHECK_LIMIT |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1120 //sprite attribute table scan starts |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1121 case 171: |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1122 context->sprite_index = 0x80; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1123 context->slot_counter = MAX_SPRITES_LINE; |
21
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
1124 render_sprite_cells( context); |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1125 scan_sprite_table(context->vcounter, context); |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1126 CHECK_LIMIT |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1127 SPRITE_RENDER_H40(172) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1128 SPRITE_RENDER_H40(173) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1129 SPRITE_RENDER_H40(174) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1130 SPRITE_RENDER_H40(175) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1131 SPRITE_RENDER_H40(176) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1132 SPRITE_RENDER_H40(177) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1133 SPRITE_RENDER_H40(178) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1134 SPRITE_RENDER_H40(179) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1135 SPRITE_RENDER_H40(180) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1136 SPRITE_RENDER_H40(181) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1137 SPRITE_RENDER_H40(182) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1138 SPRITE_RENDER_H40(229) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1139 SPRITE_RENDER_H40(230) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1140 SPRITE_RENDER_H40(231) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1141 SPRITE_RENDER_H40(232) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1142 SPRITE_RENDER_H40(233) |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1143 //!HSYNC asserted |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1144 SPRITE_RENDER_H40(234) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1145 SPRITE_RENDER_H40(235) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1146 SPRITE_RENDER_H40(236) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1147 SPRITE_RENDER_H40(237) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1148 SPRITE_RENDER_H40(238) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1149 SPRITE_RENDER_H40(239) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1150 SPRITE_RENDER_H40(240) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1151 SPRITE_RENDER_H40(241) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1152 SPRITE_RENDER_H40(242) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1153 SPRITE_RENDER_H40(243) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1154 SPRITE_RENDER_H40(244) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1155 SPRITE_RENDER_H40(245) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1156 SPRITE_RENDER_H40(246) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1157 SPRITE_RENDER_H40(247) |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1158 case 248: |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1159 address = (context->regs[REG_HSCROLL] & 0x3F) << 10; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1160 mask = 0; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1161 if (context->regs[REG_MODE_3] & 0x2) { |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1162 mask |= 0xF8; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1163 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1164 if (context->regs[REG_MODE_3] & 0x1) { |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1165 mask |= 0x7; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1166 } |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1167 address += (context->vcounter & mask) * 4; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1168 context->hscroll_a = context->vdpmem[address] << 8 | context->vdpmem[address+1]; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1169 context->hscroll_b = context->vdpmem[address+2] << 8 | context->vdpmem[address+3]; |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1170 //printf("%d: HScroll A: %d, HScroll B: %d\n", context->vcounter, context->hscroll_a, context->hscroll_b); |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1171 if (context->flags & FLAG_DMA_RUN) { run_dma_src(context, context->hslot); } |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1172 context->hslot++; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1173 context->cycles += h40_hsync_cycles[14]; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1174 CHECK_ONLY |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1175 //!HSYNC high |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1176 SPRITE_RENDER_H40(249) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1177 SPRITE_RENDER_H40(250) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1178 SPRITE_RENDER_H40(251) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1179 SPRITE_RENDER_H40(252) |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1180 case 253: |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1181 read_map_scroll_a(0, context->vcounter, context); |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1182 CHECK_LIMIT |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1183 SPRITE_RENDER_H40(254) |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1184 case 255: |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1185 render_map_1(context); |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1186 scan_sprite_table(context->vcounter, context);//Just a guess |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1187 if (context->flags & FLAG_DMA_RUN) { run_dma_src(context, context->hslot); } |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1188 context->hslot = 0; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1189 context->cycles += slot_cycles; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1190 CHECK_ONLY |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1191 case 0: |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1192 render_map_2(context); |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1193 scan_sprite_table(context->vcounter, context);//Just a guess |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1194 CHECK_LIMIT |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1195 case 1: |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1196 read_map_scroll_b(0, context->vcounter, context); |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1197 CHECK_LIMIT |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1198 SPRITE_RENDER_H40(2) |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1199 case 3: |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1200 render_map_3(context); |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1201 scan_sprite_table(context->vcounter, context);//Just a guess |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1202 CHECK_LIMIT |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1203 case 4: |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1204 if (context->vcounter == (context->latched_mode & BIT_PAL ? PAL_INACTIVE_START : NTSC_INACTIVE_START)) { |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1205 context->flags2 |= FLAG2_VINT_PENDING; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1206 context->pending_vint_start = context->cycles; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1207 } |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1208 render_map_output(context->vcounter, 0, context); |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1209 scan_sprite_table(context->vcounter, context);//Just a guess |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1210 //reverse context slot counter so it counts the number of sprite slots |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1211 //filled rather than the number of available slots |
21
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
1212 //context->slot_counter = MAX_SPRITES_LINE - context->slot_counter; |
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
1213 context->cur_slot = MAX_SPRITES_LINE-1; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1214 context->sprite_draws = MAX_DRAWS; |
36
04672c060062
Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents:
35
diff
changeset
|
1215 context->flags &= (~FLAG_CAN_MASK & ~FLAG_MASKED); |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1216 CHECK_LIMIT |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1217 COLUMN_RENDER_BLOCK(2, 5) |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1218 COLUMN_RENDER_BLOCK(4, 13) |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1219 COLUMN_RENDER_BLOCK(6, 21) |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1220 COLUMN_RENDER_BLOCK_REFRESH(8, 29) |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1221 COLUMN_RENDER_BLOCK(10, 37) |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1222 COLUMN_RENDER_BLOCK(12, 45) |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1223 COLUMN_RENDER_BLOCK(14, 53) |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1224 COLUMN_RENDER_BLOCK_REFRESH(16, 61) |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1225 COLUMN_RENDER_BLOCK(18, 69) |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1226 COLUMN_RENDER_BLOCK(20, 77) |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1227 COLUMN_RENDER_BLOCK(22, 85) |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1228 COLUMN_RENDER_BLOCK_REFRESH(24, 93) |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1229 COLUMN_RENDER_BLOCK(26, 101) |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1230 COLUMN_RENDER_BLOCK(28, 109) |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1231 COLUMN_RENDER_BLOCK(30, 117) |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1232 COLUMN_RENDER_BLOCK_REFRESH(32, 125) |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1233 COLUMN_RENDER_BLOCK(34, 133) |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1234 COLUMN_RENDER_BLOCK(36, 141) |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1235 COLUMN_RENDER_BLOCK(38, 149) |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1236 COLUMN_RENDER_BLOCK_REFRESH(40, 157) |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1237 } |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1238 default: |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1239 context->hslot++; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1240 context->cycles += slot_cycles; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1241 return; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1242 } |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1243 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1244 |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1245 void vdp_h32(vdp_context * context, uint32_t target_cycles) |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1246 { |
37 | 1247 uint16_t address; |
1248 uint32_t mask; | |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1249 uint32_t const slot_cycles = MCLKS_SLOT_H32; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1250 switch(context->hslot) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1251 { |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1252 for (;;) |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1253 { |
647
5d58dcd94733
Fix the HV counter and adjust the slots of certain VDP events
Michael Pavone <pavone@retrodev.com>
parents:
629
diff
changeset
|
1254 case 132: |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1255 external_slot(context); |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1256 CHECK_LIMIT |
647
5d58dcd94733
Fix the HV counter and adjust the slots of certain VDP events
Michael Pavone <pavone@retrodev.com>
parents:
629
diff
changeset
|
1257 case 133: |
5d58dcd94733
Fix the HV counter and adjust the slots of certain VDP events
Michael Pavone <pavone@retrodev.com>
parents:
629
diff
changeset
|
1258 external_slot(context); |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1259 CHECK_LIMIT |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1260 //sprite render to line buffer starts |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1261 case 134: |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1262 context->cur_slot = MAX_DRAWS_H32-1; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1263 memset(context->linebuf, 0, LINEBUF_SIZE); |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1264 if (context->vcounter == 0x1FF) { |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1265 external_slot(context); |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1266 } else { |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1267 render_sprite_cells(context); |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1268 } |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1269 CHECK_LIMIT |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1270 case 135: |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1271 if (context->vcounter == 0x1FF) { |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1272 external_slot(context); |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1273 } else { |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1274 render_sprite_cells(context); |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1275 } |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1276 CHECK_LIMIT |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1277 case 136: |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1278 if (context->vcounter == 0x1FF) { |
329
fd5f6577db9b
Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents:
328
diff
changeset
|
1279 external_slot(context); |
fd5f6577db9b
Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents:
328
diff
changeset
|
1280 } else { |
fd5f6577db9b
Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents:
328
diff
changeset
|
1281 render_sprite_cells(context); |
fd5f6577db9b
Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents:
328
diff
changeset
|
1282 } |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1283 CHECK_LIMIT |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1284 case 137: |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1285 if (context->vcounter == 0x1FF) { |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1286 external_slot(context); |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1287 } else { |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1288 render_sprite_cells(context); |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1289 if (context->vcounter == (context->latched_mode & BIT_PAL ? PAL_INACTIVE_START : NTSC_INACTIVE_START)) { |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1290 context->hslot++; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1291 context->cycles += slot_cycles; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1292 return; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1293 } |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1294 } |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1295 CHECK_LIMIT |
37 | 1296 //sprite attribute table scan starts |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1297 case 138: |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1298 context->sprite_index = 0x80; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1299 context->slot_counter = MAX_SPRITES_LINE_H32; |
37 | 1300 render_sprite_cells( context); |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1301 scan_sprite_table(context->vcounter, context); |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1302 CHECK_LIMIT |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1303 SPRITE_RENDER_H32(139) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1304 SPRITE_RENDER_H32(140) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1305 SPRITE_RENDER_H32(141) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1306 SPRITE_RENDER_H32(142) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1307 SPRITE_RENDER_H32(143) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1308 SPRITE_RENDER_H32(144) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1309 SPRITE_RENDER_H32(145) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1310 SPRITE_RENDER_H32(146) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1311 SPRITE_RENDER_H32(147) |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1312 case 233: |
37 | 1313 external_slot(context); |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1314 CHECK_LIMIT |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1315 SPRITE_RENDER_H32(234) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1316 SPRITE_RENDER_H32(235) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1317 SPRITE_RENDER_H32(236) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1318 SPRITE_RENDER_H32(237) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1319 SPRITE_RENDER_H32(238) |
37 | 1320 //HSYNC start |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1321 SPRITE_RENDER_H32(239) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1322 SPRITE_RENDER_H32(240) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1323 SPRITE_RENDER_H32(241) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1324 SPRITE_RENDER_H32(242) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1325 SPRITE_RENDER_H32(243) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1326 SPRITE_RENDER_H32(244) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1327 SPRITE_RENDER_H32(245) |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1328 case 246: |
37 | 1329 external_slot(context); |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1330 CHECK_LIMIT |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1331 case 247: |
37 | 1332 address = (context->regs[REG_HSCROLL] & 0x3F) << 10; |
1333 mask = 0; | |
1334 if (context->regs[REG_MODE_3] & 0x2) { | |
1335 mask |= 0xF8; | |
1336 } | |
1337 if (context->regs[REG_MODE_3] & 0x1) { | |
1338 mask |= 0x7; | |
1339 } | |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1340 address += (context->vcounter & mask) * 4; |
37 | 1341 context->hscroll_a = context->vdpmem[address] << 8 | context->vdpmem[address+1]; |
1342 context->hscroll_b = context->vdpmem[address+2] << 8 | context->vdpmem[address+3]; | |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1343 //printf("%d: HScroll A: %d, HScroll B: %d\n", context->vcounter, context->hscroll_a, context->hscroll_b); |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1344 CHECK_LIMIT |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1345 SPRITE_RENDER_H32(248) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1346 SPRITE_RENDER_H32(249) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1347 SPRITE_RENDER_H32(250) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1348 SPRITE_RENDER_H32(251) |
37 | 1349 //!HSYNC high |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1350 case 252: |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1351 read_map_scroll_a(0, context->vcounter, context); |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1352 CHECK_LIMIT |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1353 SPRITE_RENDER_H32(253) |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1354 case 254: |
37 | 1355 render_map_1(context); |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1356 scan_sprite_table(context->vcounter, context);//Just a guess |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1357 CHECK_LIMIT |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1358 case 255: |
37 | 1359 render_map_2(context); |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1360 scan_sprite_table(context->vcounter, context);//Just a guess |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1361 if (context->flags & FLAG_DMA_RUN) { run_dma_src(context, context->hslot); } |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1362 context->cycles += slot_cycles; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1363 context->hslot = 0; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1364 CHECK_ONLY |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1365 case 0: |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1366 read_map_scroll_b(0, context->vcounter, context); |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1367 CHECK_LIMIT |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1368 case 1: |
37 | 1369 render_sprite_cells(context); |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1370 scan_sprite_table(context->vcounter, context); |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1371 CHECK_LIMIT |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1372 case 2: |
37 | 1373 render_map_3(context); |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1374 scan_sprite_table(context->vcounter, context);//Just a guess |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1375 CHECK_LIMIT |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1376 case 3: |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1377 render_map_output(context->vcounter, 0, context); |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1378 scan_sprite_table(context->vcounter, context);//Just a guess |
37 | 1379 //reverse context slot counter so it counts the number of sprite slots |
1380 //filled rather than the number of available slots | |
1381 //context->slot_counter = MAX_SPRITES_LINE - context->slot_counter; | |
1382 context->cur_slot = MAX_SPRITES_LINE_H32-1; | |
1383 context->sprite_draws = MAX_DRAWS_H32; | |
1384 context->flags &= (~FLAG_CAN_MASK & ~FLAG_MASKED); | |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1385 CHECK_LIMIT |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1386 COLUMN_RENDER_BLOCK(2, 4) |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1387 COLUMN_RENDER_BLOCK(4, 12) |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1388 COLUMN_RENDER_BLOCK(6, 20) |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1389 COLUMN_RENDER_BLOCK_REFRESH(8, 28) |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1390 COLUMN_RENDER_BLOCK(10, 36) |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1391 COLUMN_RENDER_BLOCK(12, 44) |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1392 COLUMN_RENDER_BLOCK(14, 52) |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1393 COLUMN_RENDER_BLOCK_REFRESH(16, 60) |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1394 COLUMN_RENDER_BLOCK(18, 68) |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1395 COLUMN_RENDER_BLOCK(20, 76) |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1396 COLUMN_RENDER_BLOCK(22, 84) |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1397 COLUMN_RENDER_BLOCK_REFRESH(24, 92) |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1398 COLUMN_RENDER_BLOCK(26, 100) |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1399 COLUMN_RENDER_BLOCK(28, 108) |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1400 COLUMN_RENDER_BLOCK(30, 116) |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1401 COLUMN_RENDER_BLOCK_REFRESH(32, 124) |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1402 } |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1403 default: |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1404 context->hslot++; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1405 context->cycles += MCLKS_SLOT_H32; |
503
eee6be465c47
Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
499
diff
changeset
|
1406 } |
eee6be465c47
Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
499
diff
changeset
|
1407 } |
eee6be465c47
Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
499
diff
changeset
|
1408 |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1409 void latch_mode(vdp_context * context) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1410 { |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1411 context->latched_mode = context->regs[REG_MODE_2] & BIT_PAL; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1412 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1413 |
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1414 void check_render_bg(vdp_context * context, int32_t line, uint32_t slot) |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1415 { |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1416 int starti = -1; |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1417 if (context->regs[REG_MODE_4] & BIT_H40) { |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1418 if (slot >= 12 && slot < 172) { |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1419 uint32_t x = (slot-12)*2; |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1420 starti = line * 320 + x; |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1421 } |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1422 } else { |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1423 if (slot >= 11 && slot < 139) { |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1424 uint32_t x = (slot-11)*2; |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1425 starti = line * 320 + x; |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1426 } |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1427 } |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1428 if (starti >= 0) { |
719
019d27995e32
Upgrade to SDL 2.0 and drop support for the non-OpenGL render path
Michael Pavone <pavone@retrodev.com>
parents:
718
diff
changeset
|
1429 uint32_t color = context->colors[context->regs[REG_BG_COLOR]]; |
019d27995e32
Upgrade to SDL 2.0 and drop support for the non-OpenGL render path
Michael Pavone <pavone@retrodev.com>
parents:
718
diff
changeset
|
1430 uint32_t * start = context->framebuf; |
019d27995e32
Upgrade to SDL 2.0 and drop support for the non-OpenGL render path
Michael Pavone <pavone@retrodev.com>
parents:
718
diff
changeset
|
1431 start += starti; |
019d27995e32
Upgrade to SDL 2.0 and drop support for the non-OpenGL render path
Michael Pavone <pavone@retrodev.com>
parents:
718
diff
changeset
|
1432 for (int i = 0; i < 2; i++) { |
019d27995e32
Upgrade to SDL 2.0 and drop support for the non-OpenGL render path
Michael Pavone <pavone@retrodev.com>
parents:
718
diff
changeset
|
1433 *(start++) = color; |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1434 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1435 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1436 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1437 |
717
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1438 |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1439 void vdp_run_context(vdp_context * context, uint32_t target_cycles) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1440 { |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1441 while(context->cycles < target_cycles) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1442 { |
697
7f96bd1cb1be
Sync fixes and logging to fix more sync issues
Michael Pavone <pavone@retrodev.com>
parents:
680
diff
changeset
|
1443 uint32_t inactive_start = context->latched_mode & BIT_PAL ? PAL_INACTIVE_START : NTSC_INACTIVE_START; |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1444 //line 0x1FF is basically active even though it's not displayed |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1445 uint8_t active_slot = context->vcounter < inactive_start || context->vcounter == 0x1FF; |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1446 uint8_t is_h40 = context->regs[REG_MODE_4] & BIT_H40; |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1447 if (context->vcounter == inactive_start) { |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1448 if (is_h40) { |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1449 //the first inactive line behaves as an active one for the first 4 slots |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1450 if (context->hslot > LINE_CHANGE_H40 && context->hslot < 171) { |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1451 active_slot = 1; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1452 } |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1453 } else { |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1454 //the first inactive line behaves as an active one for the first few slots |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1455 if (context->hslot > LINE_CHANGE_H32 && context->hslot < 138) { |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1456 active_slot = 1; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1457 } |
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1458 } |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1459 } |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1460 if (context->regs[REG_MODE_2] & DISPLAY_ENABLE && active_slot) { |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1461 if (is_h40) { |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1462 vdp_h40(context, target_cycles); |
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1463 } else { |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1464 vdp_h32(context, target_cycles); |
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1465 } |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1466 } else { |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1467 if (is_h40) { |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1468 if (context->hslot == 167) { |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1469 context->cur_slot = MAX_DRAWS-1; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1470 memset(context->linebuf, 0, LINEBUF_SIZE); |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1471 } else if (context->hslot == 171) { |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1472 context->sprite_index = 0x80; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1473 context->slot_counter = MAX_SPRITES_LINE; |
503
eee6be465c47
Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
499
diff
changeset
|
1474 } |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1475 } else { |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1476 if (context->hslot == 134) { |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1477 context->cur_slot = MAX_DRAWS_H32-1; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1478 memset(context->linebuf, 0, LINEBUF_SIZE); |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1479 } else if (context->hslot == 138) { |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1480 context->sprite_index = 0x80; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1481 context->slot_counter = MAX_SPRITES_LINE_H32; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1482 } |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1483 } |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1484 if(context->vcounter == inactive_start) { |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1485 uint32_t intslot = context->regs[REG_MODE_4] & BIT_H40 ? VINT_SLOT_H40 : VINT_SLOT_H32; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1486 if (context->hslot == intslot) { |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1487 context->flags2 |= FLAG2_VINT_PENDING; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1488 context->pending_vint_start = context->cycles; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1489 } |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1490 } |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1491 uint32_t inccycles; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1492 if (is_h40) { |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1493 if (context->hslot < HSYNC_SLOT_H40 || context->hslot >= HSYNC_END_H40) { |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1494 inccycles = MCLKS_SLOT_H40; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1495 } else { |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1496 inccycles = h40_hsync_cycles[context->hslot-HSYNC_SLOT_H40]; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1497 } |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1498 } else { |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1499 inccycles = MCLKS_SLOT_H32; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1500 } |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1501 if (!is_refresh(context, context->hslot)) { |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1502 external_slot(context); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1503 } |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1504 if (context->vcounter < inactive_start) { |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1505 check_render_bg(context, context->vcounter, context->hslot); |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1506 } |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1507 if (context->flags & FLAG_DMA_RUN && !is_refresh(context, context->hslot)) { |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1508 run_dma_src(context, context->hslot); |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1509 } |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1510 context->cycles += inccycles; |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1511 context->hslot++; |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1512 context->hslot &= 0xFF; |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1513 if (is_h40) { |
647
5d58dcd94733
Fix the HV counter and adjust the slots of certain VDP events
Michael Pavone <pavone@retrodev.com>
parents:
629
diff
changeset
|
1514 if (context->hslot == LINE_CHANGE_H40) { |
717
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1515 vdp_advance_line(context); |
699
d8a1fdec68fc
Fix frame counter increment and VINT cycle time calculation
Michael Pavone <pavone@retrodev.com>
parents:
697
diff
changeset
|
1516 if (context->vcounter == (inactive_start + 8)) { |
d8a1fdec68fc
Fix frame counter increment and VINT cycle time calculation
Michael Pavone <pavone@retrodev.com>
parents:
697
diff
changeset
|
1517 context->frame++; |
d8a1fdec68fc
Fix frame counter increment and VINT cycle time calculation
Michael Pavone <pavone@retrodev.com>
parents:
697
diff
changeset
|
1518 } |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1519 } else if (context->hslot == 183) { |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1520 context->hslot = 229; |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1521 } |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1522 } else { |
647
5d58dcd94733
Fix the HV counter and adjust the slots of certain VDP events
Michael Pavone <pavone@retrodev.com>
parents:
629
diff
changeset
|
1523 if (context->hslot == LINE_CHANGE_H32) { |
717
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1524 vdp_advance_line(context); |
699
d8a1fdec68fc
Fix frame counter increment and VINT cycle time calculation
Michael Pavone <pavone@retrodev.com>
parents:
697
diff
changeset
|
1525 if (context->vcounter == (inactive_start + 8)) { |
d8a1fdec68fc
Fix frame counter increment and VINT cycle time calculation
Michael Pavone <pavone@retrodev.com>
parents:
697
diff
changeset
|
1526 context->frame++; |
d8a1fdec68fc
Fix frame counter increment and VINT cycle time calculation
Michael Pavone <pavone@retrodev.com>
parents:
697
diff
changeset
|
1527 } |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1528 } else if (context->hslot == 148) { |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1529 context->hslot = 233; |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1530 } |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1531 } |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1532 } |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1533 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1534 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1535 |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1536 uint32_t vdp_run_to_vblank(vdp_context * context) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1537 { |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1538 uint32_t target_cycles = ((context->latched_mode & BIT_PAL) ? PAL_INACTIVE_START : NTSC_INACTIVE_START) * MCLKS_LINE; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1539 vdp_run_context(context, target_cycles); |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1540 return context->cycles; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1541 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1542 |
75 | 1543 void vdp_run_dma_done(vdp_context * context, uint32_t target_cycles) |
1544 { | |
1545 for(;;) { | |
1546 uint32_t dmalen = (context->regs[REG_DMALEN_H] << 8) | context->regs[REG_DMALEN_L]; | |
1547 if (!dmalen) { | |
1548 dmalen = 0x10000; | |
1549 } | |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1550 uint32_t min_dma_complete = dmalen * (context->regs[REG_MODE_4] & BIT_H40 ? 16 : 20); |
75 | 1551 if ((context->regs[REG_DMASRC_H] & 0xC0) == 0xC0 || (context->cd & 0xF) == VRAM_WRITE) { |
1552 //DMA copies take twice as long to complete since they require a read and a write | |
1553 //DMA Fills and transfers to VRAM also take twice as long as it requires 2 writes for a single word | |
1554 min_dma_complete *= 2; | |
1555 } | |
1556 min_dma_complete += context->cycles; | |
1557 if (target_cycles < min_dma_complete) { | |
1558 vdp_run_context(context, target_cycles); | |
1559 return; | |
1560 } else { | |
1561 vdp_run_context(context, min_dma_complete); | |
1562 if (!(context->flags & FLAG_DMA_RUN)) { | |
1563 return; | |
1564 } | |
1565 } | |
1566 } | |
1567 } | |
1568 | |
1569 int vdp_control_port_write(vdp_context * context, uint16_t value) | |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1570 { |
471
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1571 //printf("control port write: %X at %d\n", value, context->cycles); |
149
139e5dcd6aa3
Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents:
143
diff
changeset
|
1572 if (context->flags & FLAG_DMA_RUN) { |
139e5dcd6aa3
Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents:
143
diff
changeset
|
1573 return -1; |
139e5dcd6aa3
Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents:
143
diff
changeset
|
1574 } |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1575 if (context->flags & FLAG_PENDING) { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1576 context->address = (context->address & 0x3FFF) | (value << 14); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1577 context->cd = (context->cd & 0x3) | ((value >> 2) & 0x3C); |
75 | 1578 context->flags &= ~FLAG_PENDING; |
453
b491df8bdbc0
Adjust VBLANK flag and refresh timing to be in line with logic analyzer and visual observations of direct color DMA demos. Remove debug print statements.
Mike Pavone <pavone@retrodev.com>
parents:
452
diff
changeset
|
1579 //printf("New Address: %X, New CD: %X\n", context->address, context->cd); |
327
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
1580 if (context->cd & 0x20 && (context->regs[REG_MODE_2] & BIT_DMA_ENABLE)) { |
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
1581 // |
75 | 1582 if((context->regs[REG_DMASRC_H] & 0xC0) != 0x80) { |
1583 //DMA copy or 68K -> VDP, transfer starts immediately | |
1584 context->flags |= FLAG_DMA_RUN; | |
131
8fc8e46be691
Fix bug that was causing DMA fills to lock up under certain circumstances
Mike Pavone <pavone@retrodev.com>
parents:
109
diff
changeset
|
1585 context->dma_cd = context->cd; |
717
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1586 //printf("DMA start (length: %X) at cycle %d, frame: %d, vcounter: %d, hslot: %d\n", (context->regs[REG_DMALEN_H] << 8) | context->regs[REG_DMALEN_L], context->cycles, context->frame, context->vcounter, context->hslot); |
75 | 1587 if (!(context->regs[REG_DMASRC_H] & 0x80)) { |
327
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
1588 //printf("DMA Address: %X, New CD: %X, Source: %X, Length: %X\n", context->address, context->cd, (context->regs[REG_DMASRC_H] << 17) | (context->regs[REG_DMASRC_M] << 9) | (context->regs[REG_DMASRC_L] << 1), context->regs[REG_DMALEN_H] << 8 | context->regs[REG_DMALEN_L]); |
75 | 1589 return 1; |
327
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
1590 } else { |
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
1591 //printf("DMA Copy Address: %X, New CD: %X, Source: %X\n", context->address, context->cd, (context->regs[REG_DMASRC_M] << 8) | context->regs[REG_DMASRC_L]); |
75 | 1592 } |
327
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
1593 } else { |
453
b491df8bdbc0
Adjust VBLANK flag and refresh timing to be in line with logic analyzer and visual observations of direct color DMA demos. Remove debug print statements.
Mike Pavone <pavone@retrodev.com>
parents:
452
diff
changeset
|
1594 //printf("DMA Fill Address: %X, New CD: %X\n", context->address, context->cd); |
75 | 1595 } |
63
a6dd5b7a971b
Add FPS counter to console output
Mike Pavone <pavone@retrodev.com>
parents:
58
diff
changeset
|
1596 } |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1597 } else { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1598 if ((value & 0xC000) == 0x8000) { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1599 //Register write |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1600 uint8_t reg = (value >> 8) & 0x1F; |
475
50e0cb475294
Don't allow register writes to regs above when in Mode 4
Mike Pavone <pavone@retrodev.com>
parents:
474
diff
changeset
|
1601 if (reg < (context->regs[REG_MODE_2] & BIT_MODE_5 ? VDP_REGS : 0xA)) { |
453
b491df8bdbc0
Adjust VBLANK flag and refresh timing to be in line with logic analyzer and visual observations of direct color DMA demos. Remove debug print statements.
Mike Pavone <pavone@retrodev.com>
parents:
452
diff
changeset
|
1602 //printf("register %d set to %X\n", reg, value & 0xFF); |
480
0737953132ad
Implement HV counter latch
Mike Pavone <pavone@retrodev.com>
parents:
479
diff
changeset
|
1603 if (reg == REG_MODE_1 && (value & BIT_HVC_LATCH) && !(context->regs[reg] & BIT_HVC_LATCH)) { |
0737953132ad
Implement HV counter latch
Mike Pavone <pavone@retrodev.com>
parents:
479
diff
changeset
|
1604 context->hv_latch = vdp_hv_counter_read(context); |
0737953132ad
Implement HV counter latch
Mike Pavone <pavone@retrodev.com>
parents:
479
diff
changeset
|
1605 } |
505
b7b7a1cab44a
The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents:
503
diff
changeset
|
1606 if (reg == REG_BG_COLOR) { |
b7b7a1cab44a
The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents:
503
diff
changeset
|
1607 value &= 0x3F; |
b7b7a1cab44a
The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents:
503
diff
changeset
|
1608 } |
718
eaba6789f316
Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents:
717
diff
changeset
|
1609 /*if (reg == REG_MODE_4 && ((value ^ context->regs[reg]) & BIT_H40)) { |
717
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1610 printf("Mode changed from H%d to H%d @ %d, frame: %d\n", context->regs[reg] & BIT_H40 ? 40 : 32, value & BIT_H40 ? 40 : 32, context->cycles, context->frame); |
718
eaba6789f316
Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents:
717
diff
changeset
|
1611 }*/ |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1612 context->regs[reg] = value; |
413
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1613 if (reg == REG_MODE_4) { |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1614 context->double_res = (value & (BIT_INTERLACE | BIT_DOUBLE_RES)) == (BIT_INTERLACE | BIT_DOUBLE_RES); |
415
8c60c8c09a0f
Fix sprite y mask in interlace mode. Fix framebuffer selection when switching out of interlace mode.
Mike Pavone <pavone@retrodev.com>
parents:
414
diff
changeset
|
1615 if (!context->double_res) { |
8c60c8c09a0f
Fix sprite y mask in interlace mode. Fix framebuffer selection when switching out of interlace mode.
Mike Pavone <pavone@retrodev.com>
parents:
414
diff
changeset
|
1616 context->framebuf = context->oddbuf; |
8c60c8c09a0f
Fix sprite y mask in interlace mode. Fix framebuffer selection when switching out of interlace mode.
Mike Pavone <pavone@retrodev.com>
parents:
414
diff
changeset
|
1617 } |
680
4996369f1463
Some small synchronization improvements that do not seem to fix anything
Michael Pavone <pavone@retrodev.com>
parents:
678
diff
changeset
|
1618 } |
476
5d7bc113653b
Clear the low 2 bits of CD when a register is written to
Mike Pavone <pavone@retrodev.com>
parents:
475
diff
changeset
|
1619 context->cd &= 0x3C; |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1620 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1621 } else { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1622 context->flags |= FLAG_PENDING; |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1623 context->address = (context->address &0xC000) | (value & 0x3FFF); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1624 context->cd = (context->cd &0x3C) | (value >> 14); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1625 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1626 } |
75 | 1627 return 0; |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1628 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1629 |
149
139e5dcd6aa3
Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents:
143
diff
changeset
|
1630 int vdp_data_port_write(vdp_context * context, uint16_t value) |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1631 { |
471
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1632 //printf("data port write: %X at %d\n", value, context->cycles); |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
1633 if (context->flags & FLAG_DMA_RUN && (context->regs[REG_DMASRC_H] & 0xC0) != 0x80) { |
149
139e5dcd6aa3
Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents:
143
diff
changeset
|
1634 return -1; |
139e5dcd6aa3
Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents:
143
diff
changeset
|
1635 } |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1636 context->flags &= ~FLAG_PENDING; |
109
004dd46e0a97
COmment out fifo full debug printf
Mike Pavone <pavone@retrodev.com>
parents:
108
diff
changeset
|
1637 /*if (context->fifo_cur == context->fifo_end) { |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1638 printf("FIFO full, waiting for space before next write at cycle %X\n", context->cycles); |
109
004dd46e0a97
COmment out fifo full debug printf
Mike Pavone <pavone@retrodev.com>
parents:
108
diff
changeset
|
1639 }*/ |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
1640 if (context->cd & 0x20 && (context->regs[REG_DMASRC_H] & 0xC0) == 0x80) { |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
1641 context->flags &= ~FLAG_DMA_RUN; |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
1642 } |
471
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1643 while (context->fifo_write == context->fifo_read) { |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1644 vdp_run_context(context, context->cycles + ((context->regs[REG_MODE_4] & BIT_H40) ? 16 : 20)); |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1645 } |
471
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1646 fifo_entry * cur = context->fifo + context->fifo_write; |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1647 cur->cycle = context->cycles + ((context->regs[REG_MODE_4] & BIT_H40) ? 16 : 20)*FIFO_LATENCY; |
471
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1648 cur->address = context->address; |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1649 cur->value = value; |
771
0565b2c1a034
Add ability to change start address for VRAM viewer. Fix handling of DMA enable flag when it comes to DMA fills. This fixes a bug in James Pond 3
Michael Pavone <pavone@retrodev.com>
parents:
757
diff
changeset
|
1650 if (context->cd & 0x20 && (context->regs[REG_DMASRC_H] & 0xC0) == 0x80 && (context->regs[REG_MODE_2] & BIT_DMA_ENABLE)) { |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
1651 context->flags |= FLAG_DMA_RUN; |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
1652 } |
471
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1653 cur->cd = context->cd; |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1654 cur->partial = 0; |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1655 if (context->fifo_read < 0) { |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1656 context->fifo_read = context->fifo_write; |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1657 } |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1658 context->fifo_write = (context->fifo_write + 1) & (FIFO_SIZE-1); |
138 | 1659 context->address += context->regs[REG_AUTOINC]; |
149
139e5dcd6aa3
Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents:
143
diff
changeset
|
1660 return 0; |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1661 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1662 |
470
541c1ae8abf3
Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1663 void vdp_test_port_write(vdp_context * context, uint16_t value) |
541c1ae8abf3
Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1664 { |
541c1ae8abf3
Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1665 //TODO: implement test register |
541c1ae8abf3
Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1666 } |
541c1ae8abf3
Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1667 |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1668 uint16_t vdp_control_port_read(vdp_context * context) |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1669 { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1670 context->flags &= ~FLAG_PENDING; |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1671 uint16_t value = 0x3400; |
471
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1672 if (context->fifo_read < 0) { |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1673 value |= 0x200; |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1674 } |
471
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1675 if (context->fifo_read == context->fifo_write) { |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1676 value |= 0x100; |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1677 } |
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1678 if (context->flags2 & FLAG2_VINT_PENDING) { |
413
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1679 value |= 0x80; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1680 } |
494
8ac0eb05642c
Initial implementation of sprite overflow and sprite collision status register flags
Mike Pavone <pavone@retrodev.com>
parents:
481
diff
changeset
|
1681 if (context->flags & FLAG_DOT_OFLOW) { |
8ac0eb05642c
Initial implementation of sprite overflow and sprite collision status register flags
Mike Pavone <pavone@retrodev.com>
parents:
481
diff
changeset
|
1682 value |= 0x40; |
8ac0eb05642c
Initial implementation of sprite overflow and sprite collision status register flags
Mike Pavone <pavone@retrodev.com>
parents:
481
diff
changeset
|
1683 } |
8ac0eb05642c
Initial implementation of sprite overflow and sprite collision status register flags
Mike Pavone <pavone@retrodev.com>
parents:
481
diff
changeset
|
1684 if (context->flags2 & FLAG2_SPRITE_COLLIDE) { |
8ac0eb05642c
Initial implementation of sprite overflow and sprite collision status register flags
Mike Pavone <pavone@retrodev.com>
parents:
481
diff
changeset
|
1685 value |= 0x20; |
8ac0eb05642c
Initial implementation of sprite overflow and sprite collision status register flags
Mike Pavone <pavone@retrodev.com>
parents:
481
diff
changeset
|
1686 //TODO: Test when this is actually cleared |
8ac0eb05642c
Initial implementation of sprite overflow and sprite collision status register flags
Mike Pavone <pavone@retrodev.com>
parents:
481
diff
changeset
|
1687 context->flags2 &= ~FLAG2_SPRITE_COLLIDE; |
8ac0eb05642c
Initial implementation of sprite overflow and sprite collision status register flags
Mike Pavone <pavone@retrodev.com>
parents:
481
diff
changeset
|
1688 } |
413
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1689 if ((context->regs[REG_MODE_4] & BIT_INTERLACE) && context->framebuf == context->oddbuf) { |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1690 value |= 0x10; |
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1691 } |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1692 uint32_t line= context->vcounter; |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1693 uint32_t slot = context->hslot; |
717
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1694 uint32_t inactive_start = (context->latched_mode & BIT_PAL ? PAL_INACTIVE_START : NTSC_INACTIVE_START); |
647
5d58dcd94733
Fix the HV counter and adjust the slots of certain VDP events
Michael Pavone <pavone@retrodev.com>
parents:
629
diff
changeset
|
1695 if ( |
5d58dcd94733
Fix the HV counter and adjust the slots of certain VDP events
Michael Pavone <pavone@retrodev.com>
parents:
629
diff
changeset
|
1696 ( |
717
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1697 line > inactive_start |
647
5d58dcd94733
Fix the HV counter and adjust the slots of certain VDP events
Michael Pavone <pavone@retrodev.com>
parents:
629
diff
changeset
|
1698 && line < 0x1FF |
5d58dcd94733
Fix the HV counter and adjust the slots of certain VDP events
Michael Pavone <pavone@retrodev.com>
parents:
629
diff
changeset
|
1699 ) |
884
252dfd29831d
Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents:
822
diff
changeset
|
1700 || (line == inactive_start |
717
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1701 && ( |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1702 slot >= (context->regs[REG_MODE_4] & BIT_H40 ? VBLANK_START_H40 : VBLANK_START_H32) |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1703 || slot < (context->regs[REG_MODE_4] & BIT_H40 ? LINE_CHANGE_H40 : LINE_CHANGE_H32) |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1704 ) |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1705 ) |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1706 || (line == 0x1FF |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1707 && slot < (context->regs[REG_MODE_4] & BIT_H40 ? VBLANK_START_H40 : VBLANK_START_H32)) |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1708 && slot >= (context->regs[REG_MODE_4] & BIT_H40 ? LINE_CHANGE_H40 : LINE_CHANGE_H32) |
647
5d58dcd94733
Fix the HV counter and adjust the slots of certain VDP events
Michael Pavone <pavone@retrodev.com>
parents:
629
diff
changeset
|
1709 || !(context->regs[REG_MODE_2] & BIT_DISP_EN) |
5d58dcd94733
Fix the HV counter and adjust the slots of certain VDP events
Michael Pavone <pavone@retrodev.com>
parents:
629
diff
changeset
|
1710 ) { |
318
789f2f5f2277
Implement hblank flag in status register
Mike Pavone <pavone@retrodev.com>
parents:
317
diff
changeset
|
1711 value |= 0x8; |
789f2f5f2277
Implement hblank flag in status register
Mike Pavone <pavone@retrodev.com>
parents:
317
diff
changeset
|
1712 } |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1713 if (context->regs[REG_MODE_4] & BIT_H40) { |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1714 if (slot < HBLANK_END_H40 || slot > HBLANK_START_H40) { |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1715 value |= 0x4; |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1716 } |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1717 } else { |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1718 if (slot < HBLANK_END_H32 || slot > HBLANK_START_H32) { |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1719 value |= 0x4; |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1720 } |
318
789f2f5f2277
Implement hblank flag in status register
Mike Pavone <pavone@retrodev.com>
parents:
317
diff
changeset
|
1721 } |
149
139e5dcd6aa3
Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents:
143
diff
changeset
|
1722 if (context->flags & FLAG_DMA_RUN) { |
141
576f55711d8d
Fix DMA in progress flag in VDP status register
Mike Pavone <pavone@retrodev.com>
parents:
138
diff
changeset
|
1723 value |= 0x2; |
75 | 1724 } |
714
e29bc2918f69
Fix VDP status register PAL bit based on observations of the Titan Overdrive demo
Michael Pavone <pavone@retrodev.com>
parents:
711
diff
changeset
|
1725 if (context->flags2 & FLAG2_REGION_PAL) { |
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1726 value |= 0x1; |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1727 } |
459
c49ecf575784
Revert change to VBLANK flag timing based on new direct color DMA test
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
1728 //printf("status read at cycle %d returned %X\n", context->cycles, value); |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1729 return value; |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1730 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1731 |
470
541c1ae8abf3
Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1732 #define CRAM_BITS 0xEEE |
474
e128e55710bd
Remove read pending stuff, that had been added in an attempt to fix CRAM/VSRAM undefined bit results. Set number of bits actually saved in VSRAM to 11
Mike Pavone <pavone@retrodev.com>
parents:
473
diff
changeset
|
1733 #define VSRAM_BITS 0x7FF |
471
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1734 #define VSRAM_DIRTY_BITS 0xF800 |
470
541c1ae8abf3
Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1735 |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1736 uint16_t vdp_data_port_read(vdp_context * context) |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1737 { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1738 context->flags &= ~FLAG_PENDING; |
138 | 1739 if (context->cd & 1) { |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1740 return 0; |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1741 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1742 //Not sure if the FIFO should be drained before processing a read or not, but it would make sense |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1743 context->flags &= ~FLAG_UNUSED_SLOT; |
474
e128e55710bd
Remove read pending stuff, that had been added in an attempt to fix CRAM/VSRAM undefined bit results. Set number of bits actually saved in VSRAM to 11
Mike Pavone <pavone@retrodev.com>
parents:
473
diff
changeset
|
1744 //context->flags2 |= FLAG2_READ_PENDING; |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1745 while (!(context->flags & FLAG_UNUSED_SLOT)) { |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1746 vdp_run_context(context, context->cycles + ((context->regs[REG_MODE_4] & BIT_H40) ? 16 : 20)); |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1747 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1748 uint16_t value = 0; |
138 | 1749 switch (context->cd & 0xF) |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1750 { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1751 case VRAM_READ: |
472 | 1752 value = context->vdpmem[context->address & 0xFFFE] << 8; |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1753 context->flags &= ~FLAG_UNUSED_SLOT; |
470
541c1ae8abf3
Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1754 context->flags2 |= FLAG2_READ_PENDING; |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1755 while (!(context->flags & FLAG_UNUSED_SLOT)) { |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1756 vdp_run_context(context, context->cycles + ((context->regs[REG_MODE_4] & BIT_H40) ? 16 : 20)); |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1757 } |
472 | 1758 value |= context->vdpmem[context->address | 1]; |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1759 break; |
473
1358045c0bdd
Implement undocumented 8-bit VRAM read
Mike Pavone <pavone@retrodev.com>
parents:
472
diff
changeset
|
1760 case VRAM_READ8: |
1358045c0bdd
Implement undocumented 8-bit VRAM read
Mike Pavone <pavone@retrodev.com>
parents:
472
diff
changeset
|
1761 value = context->vdpmem[context->address ^ 1]; |
1358045c0bdd
Implement undocumented 8-bit VRAM read
Mike Pavone <pavone@retrodev.com>
parents:
472
diff
changeset
|
1762 value |= context->fifo[context->fifo_write].value & 0xFF00; |
1358045c0bdd
Implement undocumented 8-bit VRAM read
Mike Pavone <pavone@retrodev.com>
parents:
472
diff
changeset
|
1763 break; |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1764 case CRAM_READ: |
470
541c1ae8abf3
Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1765 value = context->cram[(context->address/2) & (CRAM_SIZE-1)] & CRAM_BITS; |
471
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1766 value |= context->fifo[context->fifo_write].value & ~CRAM_BITS; |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1767 break; |
479
863e868752cf
Implement funny behavior for DMA fill to CRAM and VSRAM. Return VSRAM address 0 for reads to VSRAM at >= 40
Mike Pavone <pavone@retrodev.com>
parents:
478
diff
changeset
|
1768 case VSRAM_READ: { |
863e868752cf
Implement funny behavior for DMA fill to CRAM and VSRAM. Return VSRAM address 0 for reads to VSRAM at >= 40
Mike Pavone <pavone@retrodev.com>
parents:
478
diff
changeset
|
1769 uint16_t address = (context->address /2) & 63; |
863e868752cf
Implement funny behavior for DMA fill to CRAM and VSRAM. Return VSRAM address 0 for reads to VSRAM at >= 40
Mike Pavone <pavone@retrodev.com>
parents:
478
diff
changeset
|
1770 if (address >= VSRAM_SIZE) { |
863e868752cf
Implement funny behavior for DMA fill to CRAM and VSRAM. Return VSRAM address 0 for reads to VSRAM at >= 40
Mike Pavone <pavone@retrodev.com>
parents:
478
diff
changeset
|
1771 address = 0; |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1772 } |
479
863e868752cf
Implement funny behavior for DMA fill to CRAM and VSRAM. Return VSRAM address 0 for reads to VSRAM at >= 40
Mike Pavone <pavone@retrodev.com>
parents:
478
diff
changeset
|
1773 value = context->vsram[address] & VSRAM_BITS; |
863e868752cf
Implement funny behavior for DMA fill to CRAM and VSRAM. Return VSRAM address 0 for reads to VSRAM at >= 40
Mike Pavone <pavone@retrodev.com>
parents:
478
diff
changeset
|
1774 value |= context->fifo[context->fifo_write].value & VSRAM_DIRTY_BITS; |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1775 break; |
479
863e868752cf
Implement funny behavior for DMA fill to CRAM and VSRAM. Return VSRAM address 0 for reads to VSRAM at >= 40
Mike Pavone <pavone@retrodev.com>
parents:
478
diff
changeset
|
1776 } |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1777 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1778 context->address += context->regs[REG_AUTOINC]; |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1779 return value; |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1780 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1781 |
137 | 1782 uint16_t vdp_hv_counter_read(vdp_context * context) |
1783 { | |
480
0737953132ad
Implement HV counter latch
Mike Pavone <pavone@retrodev.com>
parents:
479
diff
changeset
|
1784 if (context->regs[REG_MODE_1] & BIT_HVC_LATCH) { |
0737953132ad
Implement HV counter latch
Mike Pavone <pavone@retrodev.com>
parents:
479
diff
changeset
|
1785 return context->hv_latch; |
0737953132ad
Implement HV counter latch
Mike Pavone <pavone@retrodev.com>
parents:
479
diff
changeset
|
1786 } |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1787 uint32_t line= context->vcounter & 0xFF; |
647
5d58dcd94733
Fix the HV counter and adjust the slots of certain VDP events
Michael Pavone <pavone@retrodev.com>
parents:
629
diff
changeset
|
1788 uint32_t linecyc = context->hslot; |
137 | 1789 linecyc &= 0xFF; |
413
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1790 if (context->double_res) { |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1791 line <<= 1; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1792 if (line & 0x100) { |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1793 line |= 1; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1794 } |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1795 } |
137 | 1796 return (line << 8) | linecyc; |
1797 } | |
1798 | |
470
541c1ae8abf3
Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1799 uint16_t vdp_test_port_read(vdp_context * context) |
541c1ae8abf3
Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1800 { |
541c1ae8abf3
Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1801 //TODO: Find out what actually gets returned here |
541c1ae8abf3
Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1802 return 0xFFFF; |
541c1ae8abf3
Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1803 } |
541c1ae8abf3
Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1804 |
65
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1805 void vdp_adjust_cycles(vdp_context * context, uint32_t deduction) |
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1806 { |
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1807 context->cycles -= deduction; |
717
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1808 if (context->pending_vint_start >= deduction) { |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1809 context->pending_vint_start -= deduction; |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1810 } else { |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1811 context->pending_vint_start = 0; |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1812 } |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1813 if (context->pending_hint_start >= deduction) { |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1814 context->pending_hint_start -= deduction; |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1815 } else { |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1816 context->pending_hint_start = 0; |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1817 } |
471
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1818 if (context->fifo_read >= 0) { |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1819 int32_t idx = context->fifo_read; |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1820 do { |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1821 if (context->fifo[idx].cycle >= deduction) { |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1822 context->fifo[idx].cycle -= deduction; |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1823 } else { |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1824 context->fifo[idx].cycle = 0; |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1825 } |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1826 idx = (idx+1) & (FIFO_SIZE-1); |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1827 } while(idx != context->fifo_write); |
65
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1828 } |
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1829 } |
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1830 |
717
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1831 uint32_t vdp_cycles_hslot_wrap_h40(vdp_context * context) |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1832 { |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1833 if (context->hslot < 183) { |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1834 return MCLKS_LINE - context->hslot * MCLKS_SLOT_H40; |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1835 } else if (context->hslot < HSYNC_END_H40) { |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1836 uint32_t before_hsync = context->hslot < HSYNC_SLOT_H40 ? (HSYNC_SLOT_H40 - context->hslot) * MCLKS_SLOT_H40 : 0; |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1837 uint32_t hsync = 0; |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1838 for (int i = context->hslot <= HSYNC_SLOT_H40 ? 0 : context->hslot - HSYNC_SLOT_H40; i < sizeof(h40_hsync_cycles)/sizeof(uint32_t); i++) |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1839 { |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1840 hsync += h40_hsync_cycles[i]; |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1841 } |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1842 uint32_t after_hsync = (256- HSYNC_END_H40) * MCLKS_SLOT_H40; |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1843 return before_hsync + hsync + after_hsync; |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1844 } else { |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1845 return (256-context->hslot) * MCLKS_SLOT_H40; |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1846 } |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1847 } |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1848 |
623
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1849 uint32_t vdp_cycles_next_line(vdp_context * context) |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1850 { |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1851 if (context->regs[REG_MODE_4] & BIT_H40) { |
647
5d58dcd94733
Fix the HV counter and adjust the slots of certain VDP events
Michael Pavone <pavone@retrodev.com>
parents:
629
diff
changeset
|
1852 if (context->hslot < LINE_CHANGE_H40) { |
697
7f96bd1cb1be
Sync fixes and logging to fix more sync issues
Michael Pavone <pavone@retrodev.com>
parents:
680
diff
changeset
|
1853 return (LINE_CHANGE_H40 - context->hslot) * MCLKS_SLOT_H40; |
623
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1854 } else { |
717
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1855 return vdp_cycles_hslot_wrap_h40(context) + LINE_CHANGE_H40 * MCLKS_SLOT_H40; |
623
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1856 } |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1857 } else { |
647
5d58dcd94733
Fix the HV counter and adjust the slots of certain VDP events
Michael Pavone <pavone@retrodev.com>
parents:
629
diff
changeset
|
1858 if (context->hslot < LINE_CHANGE_H32) { |
5d58dcd94733
Fix the HV counter and adjust the slots of certain VDP events
Michael Pavone <pavone@retrodev.com>
parents:
629
diff
changeset
|
1859 return (LINE_CHANGE_H32 - context->hslot) * MCLKS_SLOT_H32; |
623
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1860 } else if (context->hslot < 148) { |
647
5d58dcd94733
Fix the HV counter and adjust the slots of certain VDP events
Michael Pavone <pavone@retrodev.com>
parents:
629
diff
changeset
|
1861 return MCLKS_LINE - (context->hslot - LINE_CHANGE_H32) * MCLKS_SLOT_H32; |
623
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1862 } else { |
647
5d58dcd94733
Fix the HV counter and adjust the slots of certain VDP events
Michael Pavone <pavone@retrodev.com>
parents:
629
diff
changeset
|
1863 return (256-context->hslot + LINE_CHANGE_H32) * MCLKS_SLOT_H32; |
623
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1864 } |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1865 } |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1866 } |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1867 |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1868 uint32_t vdp_cycles_to_line(vdp_context * context, uint32_t target) |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1869 { |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1870 uint32_t jump_start, jump_dst; |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1871 if (context->flags2 & FLAG2_REGION_PAL) { |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1872 if (context->latched_mode & BIT_PAL) { |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1873 jump_start = 0x10B; |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1874 jump_dst = 0x1D2; |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1875 } else { |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1876 jump_start = 0x103; |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1877 jump_dst = 0x1CA; |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1878 } |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1879 } else { |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1880 if (context->latched_mode & BIT_PAL) { |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1881 jump_start = 0; |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1882 jump_dst = 0; |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1883 } else { |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1884 jump_start = 0xEB; |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1885 jump_dst = 0x1E5; |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1886 } |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1887 } |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1888 uint32_t lines; |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1889 if (context->vcounter < target) { |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1890 if (target < jump_start) { |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1891 lines = target - context->vcounter; |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1892 } else { |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1893 lines = jump_start - context->vcounter + target - jump_dst; |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1894 } |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1895 } else { |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1896 if (context->vcounter < jump_start) { |
718
eaba6789f316
Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents:
717
diff
changeset
|
1897 lines = jump_start - context->vcounter + 512 - jump_dst; |
623
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1898 } else { |
718
eaba6789f316
Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents:
717
diff
changeset
|
1899 lines = 512 - context->vcounter; |
623
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1900 } |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1901 if (target < jump_start) { |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1902 lines += target; |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1903 } else { |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1904 lines += jump_start + target - jump_dst; |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1905 } |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1906 } |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1907 return MCLKS_LINE * (lines - 1) + vdp_cycles_next_line(context); |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1908 } |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1909 |
680
4996369f1463
Some small synchronization improvements that do not seem to fix anything
Michael Pavone <pavone@retrodev.com>
parents:
678
diff
changeset
|
1910 uint32_t vdp_frame_end_line(vdp_context * context) |
623
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1911 { |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1912 uint32_t frame_end; |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1913 if (context->flags2 & FLAG2_REGION_PAL) { |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1914 if (context->latched_mode & BIT_PAL) { |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1915 frame_end = PAL_INACTIVE_START + 8; |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1916 } else { |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1917 frame_end = NTSC_INACTIVE_START + 8; |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1918 } |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1919 } else { |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1920 if (context->latched_mode & BIT_PAL) { |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1921 frame_end = 512; |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1922 } else { |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1923 frame_end = NTSC_INACTIVE_START + 8; |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1924 } |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1925 } |
680
4996369f1463
Some small synchronization improvements that do not seem to fix anything
Michael Pavone <pavone@retrodev.com>
parents:
678
diff
changeset
|
1926 return frame_end; |
4996369f1463
Some small synchronization improvements that do not seem to fix anything
Michael Pavone <pavone@retrodev.com>
parents:
678
diff
changeset
|
1927 } |
4996369f1463
Some small synchronization improvements that do not seem to fix anything
Michael Pavone <pavone@retrodev.com>
parents:
678
diff
changeset
|
1928 |
4996369f1463
Some small synchronization improvements that do not seem to fix anything
Michael Pavone <pavone@retrodev.com>
parents:
678
diff
changeset
|
1929 uint32_t vdp_cycles_to_frame_end(vdp_context * context) |
4996369f1463
Some small synchronization improvements that do not seem to fix anything
Michael Pavone <pavone@retrodev.com>
parents:
678
diff
changeset
|
1930 { |
4996369f1463
Some small synchronization improvements that do not seem to fix anything
Michael Pavone <pavone@retrodev.com>
parents:
678
diff
changeset
|
1931 return context->cycles + vdp_cycles_to_line(context, vdp_frame_end_line(context)); |
4996369f1463
Some small synchronization improvements that do not seem to fix anything
Michael Pavone <pavone@retrodev.com>
parents:
678
diff
changeset
|
1932 } |
4996369f1463
Some small synchronization improvements that do not seem to fix anything
Michael Pavone <pavone@retrodev.com>
parents:
678
diff
changeset
|
1933 |
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1934 uint32_t vdp_next_hint(vdp_context * context) |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1935 { |
327
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
1936 if (!(context->regs[REG_MODE_1] & BIT_HINT_EN)) { |
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1937 return 0xFFFFFFFF; |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1938 } |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1939 if (context->flags2 & FLAG2_HINT_PENDING) { |
717
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1940 return context->pending_hint_start; |
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1941 } |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1942 uint32_t inactive_start = context->latched_mode & BIT_PAL ? PAL_INACTIVE_START : NTSC_INACTIVE_START; |
623
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1943 uint32_t hint_line; |
708
61faa298af07
Small horizontal interrupt fixes
Michael Pavone <pavone@retrodev.com>
parents:
705
diff
changeset
|
1944 if (context->vcounter + context->hint_counter >= inactive_start) { |
724
2174f92c5f9b
Fix bug in vdp_next_hint that was causing HINTs to fire repeatedly when they should not have fired at all based on an HINT interval that was larger than the number of active lines in the display
Michael Pavone <pavone@retrodev.com>
parents:
722
diff
changeset
|
1945 if (context->regs[REG_HINT] > inactive_start) { |
2174f92c5f9b
Fix bug in vdp_next_hint that was causing HINTs to fire repeatedly when they should not have fired at all based on an HINT interval that was larger than the number of active lines in the display
Michael Pavone <pavone@retrodev.com>
parents:
722
diff
changeset
|
1946 return 0xFFFFFFFF; |
2174f92c5f9b
Fix bug in vdp_next_hint that was causing HINTs to fire repeatedly when they should not have fired at all based on an HINT interval that was larger than the number of active lines in the display
Michael Pavone <pavone@retrodev.com>
parents:
722
diff
changeset
|
1947 } |
623
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1948 hint_line = context->regs[REG_HINT]; |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1949 } else { |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1950 hint_line = context->vcounter + context->hint_counter + 1; |
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1951 } |
623
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1952 |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1953 return context->cycles + vdp_cycles_to_line(context, hint_line); |
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1954 } |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1955 |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1956 uint32_t vdp_next_vint(vdp_context * context) |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1957 { |
327
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
1958 if (!(context->regs[REG_MODE_2] & BIT_VINT_EN)) { |
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1959 return 0xFFFFFFFF; |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1960 } |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1961 if (context->flags2 & FLAG2_VINT_PENDING) { |
717
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1962 return context->pending_vint_start; |
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1963 } |
623
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1964 |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1965 |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1966 return vdp_next_vint_z80(context); |
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1967 } |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1968 |
333 | 1969 uint32_t vdp_next_vint_z80(vdp_context * context) |
1970 { | |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1971 uint32_t inactive_start = context->latched_mode & BIT_PAL ? PAL_INACTIVE_START : NTSC_INACTIVE_START; |
623
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1972 if (context->vcounter == inactive_start) { |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1973 if (context->regs[REG_MODE_4] & BIT_H40) { |
699
d8a1fdec68fc
Fix frame counter increment and VINT cycle time calculation
Michael Pavone <pavone@retrodev.com>
parents:
697
diff
changeset
|
1974 if (context->hslot >= LINE_CHANGE_H40) { |
717
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1975 return context->cycles + vdp_cycles_hslot_wrap_h40(context) + VINT_SLOT_H40 * MCLKS_SLOT_H40; |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1976 } else if (context->hslot <= VINT_SLOT_H40) { |
623
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1977 return context->cycles + (VINT_SLOT_H40 - context->hslot) * MCLKS_SLOT_H40; |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1978 } |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1979 } else { |
699
d8a1fdec68fc
Fix frame counter increment and VINT cycle time calculation
Michael Pavone <pavone@retrodev.com>
parents:
697
diff
changeset
|
1980 if (context->hslot >= LINE_CHANGE_H32) { |
623
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1981 if (context->hslot < 148) { |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1982 return context->cycles + (VINT_SLOT_H32 + 148 - context->hslot + 256 - 233) * MCLKS_SLOT_H32; |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1983 } else { |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1984 return context->cycles + (VINT_SLOT_H32 + 256 - context->hslot) * MCLKS_SLOT_H32; |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1985 } |
717
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1986 } else if (context->hslot <= VINT_SLOT_H32) { |
623
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1987 return context->cycles + (VINT_SLOT_H32 - context->hslot) * MCLKS_SLOT_H32; |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1988 } |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1989 } |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1990 } |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1991 int32_t cycles_to_vint = vdp_cycles_to_line(context, inactive_start); |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1992 if (context->regs[REG_MODE_4] & BIT_H40) { |
717
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
1993 cycles_to_vint += MCLKS_LINE - (LINE_CHANGE_H40 - VINT_SLOT_H40) * MCLKS_SLOT_H40; |
333 | 1994 } else { |
699
d8a1fdec68fc
Fix frame counter increment and VINT cycle time calculation
Michael Pavone <pavone@retrodev.com>
parents:
697
diff
changeset
|
1995 cycles_to_vint += (VINT_SLOT_H32 + 148 - LINE_CHANGE_H32 + 256 - 233) * MCLKS_SLOT_H32; |
333 | 1996 } |
623
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
1997 return context->cycles + cycles_to_vint; |
333 | 1998 } |
1999 | |
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
2000 void vdp_int_ack(vdp_context * context, uint16_t int_num) |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
2001 { |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
2002 if (int_num == 6) { |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
2003 context->flags2 &= ~FLAG2_VINT_PENDING; |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
2004 } else if(int_num ==4) { |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
2005 context->flags2 &= ~FLAG2_HINT_PENDING; |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
2006 } |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
2007 } |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
2008 |