Mercurial > repos > blastem
annotate cpu_dsl.py @ 1613:2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
author | Michael Pavone <pavone@retrodev.com> |
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date | Tue, 18 Sep 2018 09:06:42 -0700 |
parents | |
children | c9639139aedf |
rev | line source |
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1613
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1 #!/usr/bin/env python3 |
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2 |
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3 |
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4 class Block: |
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5 def addOp(self, op): |
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6 pass |
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7 |
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8 def processLine(self, parts): |
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9 if parts[0] == 'switch': |
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10 o = Switch(self, parts[1]) |
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11 self.addOp(o) |
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12 return o |
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13 elif parts[0] == 'if': |
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14 o = If(self, parts[1]) |
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15 self.addOp(o) |
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16 return o |
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17 elif parts[0] == 'end': |
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18 raise Exception('end is only allowed inside a switch or if block') |
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19 else: |
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20 self.addOp(NormalOp(parts)) |
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21 return self |
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22 |
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23 def resolveLocal(self, name): |
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24 return None |
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25 |
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26 class ChildBlock(Block): |
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27 def processLine(self, parts): |
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28 if parts[0] == 'end': |
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29 return self.parent |
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30 return super().processLine(parts) |
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31 |
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32 #Represents an instruction of the emulated CPU |
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33 class Instruction(Block): |
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34 def __init__(self, value, fields, name): |
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35 self.value = value |
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36 self.fields = fields |
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37 self.name = name |
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38 self.implementation = [] |
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39 self.locals = {} |
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40 self.regValues = {} |
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41 self.varyingBits = 0 |
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42 self.invalidFieldValues = {} |
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43 for field in fields: |
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44 self.varyingBits += fields[field][1] |
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45 |
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46 def addOp(self, op): |
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47 if op.op == 'local': |
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48 name = op.params[0] |
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49 size = op.params[1] |
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50 self.locals[name] = size |
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51 elif op.op == 'invalid': |
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52 name = op.params[0] |
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53 value = int(op.params[1]) |
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54 self.invalidFieldValues.setdefault(name, set()).add(value) |
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55 else: |
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56 self.implementation.append(op) |
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57 |
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58 def resolveLocal(self, name): |
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59 if name in self.locals: |
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60 return name |
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61 return None |
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62 |
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63 def addLocal(self, name, size): |
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64 self.locals[name] = size |
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65 |
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66 def localSize(self, name): |
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67 return self.locals.get(name) |
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68 |
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69 def __lt__(self, other): |
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70 if isinstance(other, Instruction): |
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71 if self.varyingBits != other.varyingBits: |
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72 return self.varyingBits < other.varyingBits |
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73 return self.value < other.value |
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74 else: |
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75 return NotImplemented |
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76 |
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77 def allValues(self): |
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78 values = [] |
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79 for i in range(0, 1 << self.varyingBits): |
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80 iword = self.value |
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81 doIt = True |
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82 for field in self.fields: |
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83 shift,bits = self.fields[field] |
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84 val = i & ((1 << bits) - 1) |
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85 if field in self.invalidFieldValues and val in self.invalidFieldValues[field]: |
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86 doIt = False |
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87 break |
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88 i >>= bits |
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89 iword |= val << shift |
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90 if doIt: |
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91 values.append(iword) |
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92 return values |
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93 |
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94 def getFieldVals(self, value): |
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95 fieldVals = {} |
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96 fieldBits = {} |
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97 for field in self.fields: |
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98 shift,bits = self.fields[field] |
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99 val = (value >> shift) & ((1 << bits) - 1) |
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100 fieldVals[field] = val |
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101 fieldBits[field] = bits |
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102 return (fieldVals, fieldBits) |
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103 |
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104 def generateName(self, value): |
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105 fieldVals,fieldBits = self.getFieldVals(value) |
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106 names = list(fieldVals.keys()) |
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107 names.sort() |
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108 funName = self.name |
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109 for name in names: |
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110 funName += '_{0}_{1:0>{2}}'.format(name, bin(fieldVals[name])[2:], fieldBits[name]) |
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111 return funName |
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112 |
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113 def generateBody(self, value, prog, otype): |
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114 output = [] |
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115 prog.meta = {} |
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116 prog.currentScope = self |
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117 for var in self.locals: |
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118 output.append('\n\tuint{sz}_t {name};'.format(sz=self.locals[var], name=var)) |
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119 fieldVals,_ = self.getFieldVals(value) |
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120 for op in self.implementation: |
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121 op.generate(prog, self, fieldVals, output, otype) |
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122 begin = '\nvoid ' + self.generateName(value) + '(' + prog.context_type + ' *context)\n{' |
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123 if prog.needFlagCoalesce: |
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124 begin += prog.flags.coalesceFlags(prog, otype) |
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125 if prog.needFlagDisperse: |
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126 output.append(prog.flags.disperseFlags(prog, otype)) |
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127 return begin + ''.join(output) + '\n}' |
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128 |
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129 def __str__(self): |
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130 pieces = [self.name + ' ' + hex(self.value) + ' ' + str(self.fields)] |
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131 for name in self.locals: |
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132 pieces.append('\n\tlocal {0} {1}'.format(name, self.locals[name])) |
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133 for op in self.implementation: |
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134 pieces.append(str(op)) |
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135 return ''.join(pieces) |
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136 |
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137 #Represents the definition of a helper function |
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138 class SubRoutine(Block): |
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139 def __init__(self, name): |
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140 self.name = name |
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141 self.implementation = [] |
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142 self.args = [] |
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143 self.arg_map = {} |
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144 self.locals = {} |
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145 self.regValues = {} |
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146 |
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147 def addOp(self, op): |
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148 if op.op == 'arg': |
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149 name = op.params[0] |
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150 size = op.params[1] |
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151 self.arg_map[name] = len(self.args) |
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152 self.args.append((name, size)) |
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153 elif op.op == 'local': |
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154 name = op.params[0] |
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155 size = op.params[1] |
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156 self.locals[name] = size |
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157 else: |
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158 self.implementation.append(op) |
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159 |
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160 def resolveLocal(self, name): |
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161 if name in self.locals: |
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162 return self.name + '_' + name |
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163 return None |
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164 |
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165 def addLocal(self, name, size): |
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166 self.locals[name] = size |
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167 |
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168 def localSize(self, name): |
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169 return self.locals.get(name) |
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170 |
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171 def inline(self, prog, params, output, otype, parent): |
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172 if len(params) != len(self.args): |
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173 raise Exception('{0} expects {1} arguments, but was called with {2}'.format(self.name, len(self.args), len(params))) |
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174 argValues = {} |
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175 if parent: |
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176 self.regValues = parent.regValues |
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177 oldScope = prog.currentScope |
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178 prog.currentScope = self |
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179 i = 0 |
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180 for name,size in self.args: |
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181 argValues[name] = params[i] |
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182 i += 1 |
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183 for name in self.locals: |
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184 size = self.locals[name] |
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185 output.append('\n\tuint{size}_t {sub}_{local};'.format(size=size, sub=self.name, local=name)) |
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186 for op in self.implementation: |
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187 op.generate(prog, self, argValues, output, otype) |
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188 prog.currentScope = oldScope |
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189 |
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190 def __str__(self): |
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191 pieces = [self.name] |
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192 for name,size in self.args: |
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193 pieces.append('\n\targ {0} {1}'.format(name, size)) |
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194 for name in self.locals: |
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195 pieces.append('\n\tlocal {0} {1}'.format(name, self.locals[name])) |
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196 for op in self.implementation: |
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197 pieces.append(str(op)) |
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198 return ''.join(pieces) |
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199 |
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200 class Op: |
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201 def __init__(self, evalFun = None): |
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202 self.evalFun = evalFun |
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203 self.impls = {} |
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204 self.outOp = () |
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205 def cBinaryOperator(self, op): |
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206 def _impl(prog, params): |
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207 if op == '-': |
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208 a = params[1] |
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209 b = params[0] |
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210 else: |
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211 a = params[0] |
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212 b = params[1] |
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213 return '\n\t{dst} = {a} {op} {b};'.format( |
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214 dst = params[2], a = a, b = b, op = op |
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215 ) |
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216 self.impls['c'] = _impl |
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217 self.outOp = (2,) |
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218 return self |
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219 def cUnaryOperator(self, op): |
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220 def _impl(prog, params): |
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221 return '\n\t{dst} = {op}{a};'.format( |
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222 dst = params[1], a = params[0], op = op |
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223 ) |
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224 self.impls['c'] = _impl |
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225 self.outOp = (1,) |
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226 return self |
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227 def addImplementation(self, lang, outOp, impl): |
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228 self.impls[lang] = impl |
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229 if not outOp is None: |
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230 if type(outOp) is tuple: |
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231 self.outOp = outOp |
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232 else: |
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233 self.outOp = (outOp,) |
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234 return self |
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235 def evaluate(self, params): |
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236 return self.evalFun(*params) |
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237 def canEval(self): |
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238 return not self.evalFun is None |
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239 def numArgs(self): |
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240 return self.evalFun.__code__.co_argcount |
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241 def generate(self, otype, prog, params, rawParams): |
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242 if self.impls[otype].__code__.co_argcount == 2: |
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243 return self.impls[otype](prog, params) |
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244 else: |
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245 return self.impls[otype](prog, params, rawParams) |
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246 |
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247 |
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248 def _xchgCImpl(prog, params, rawParams): |
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249 size = prog.paramSize(rawParams[0]) |
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250 decl,name = prog.getTemp(size) |
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251 return decl + '\n\t{tmp} = {a};\n\t{a} = {b};\n\t{b} = {tmp};'.format(a = params[0], b = params[1], tmp = name) |
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252 |
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253 def _dispatchCImpl(prog, params): |
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254 if len(params) == 1: |
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255 table = 'main' |
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256 else: |
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257 table = params[1] |
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258 return '\n\timpl_{tbl}[{op}](context);'.format(tbl = table, op = params[0]) |
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259 |
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260 def _updateFlagsCImpl(prog, params, rawParams): |
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261 i = 0 |
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262 last = '' |
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263 autoUpdate = set() |
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264 explicit = {} |
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265 for c in params[0]: |
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266 if c.isdigit(): |
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267 if last.isalpha(): |
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268 num = int(c) |
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269 if num > 1: |
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270 raise Exception(c + ' is not a valid digit for update_flags') |
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271 explicit[last] = num |
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272 last = c |
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273 else: |
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274 raise Exception('Digit must follow flag letter in update_flags') |
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275 else: |
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276 if last.isalpha(): |
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277 autoUpdate.add(last) |
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278 last = c |
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279 if last.isalpha(): |
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280 autoUpdate.add(last) |
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281 output = [] |
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282 #TODO: handle autoUpdate flags |
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283 for flag in autoUpdate: |
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284 calc = prog.flags.flagCalc[flag] |
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285 calc,_,resultBit = calc.partition('-') |
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286 lastDst = prog.resolveReg(prog.lastDst, None, {}) |
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287 storage = prog.flags.getStorage(flag) |
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288 if calc == 'bit' or calc == 'sign': |
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289 if calc == 'sign': |
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290 resultBit = prog.paramSize(prog.lastDst) - 1 |
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291 else: |
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292 resultBit = int(resultBit) |
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293 if type(storage) is tuple: |
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294 reg,storageBit = storage |
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295 reg = prog.resolveReg(reg, None, {}) |
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296 if storageBit == resultBit: |
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297 #TODO: optimize this case |
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298 output.append('\n\t{reg} = ({reg} & ~{mask}) | ({res} & {mask});'.format( |
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299 reg = reg, mask = 1 << resultBit, res = lastDst |
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300 )) |
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301 else: |
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302 if resultBit > storageBit: |
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303 op = '>>' |
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304 shift = resultBit - storageBit |
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305 else: |
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306 op = '<<' |
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307 shift = storageBit - resultBit |
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308 output.append('\n\t{reg} = ({reg} & ~{mask}) | ({res} {op} {shift} & {mask});'.format( |
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309 reg = reg, mask = 1 << storageBit, res = lastDst, op = op, shift = shift |
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310 )) |
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311 else: |
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312 reg = prog.resolveReg(storage, None, {}) |
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313 output.append('\n\t{reg} = {res} & {mask};'.format(reg=reg, res=lastDst, mask = 1 << resultBit)) |
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314 elif calc == 'zero': |
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315 if type(storage) is tuple: |
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316 reg,storageBit = storage |
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317 reg = prog.resolveReg(reg, None, {}) |
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318 output.append('\n\t{reg} = {res} ? ({reg} & {mask}) : ({reg} | {bit});'.format( |
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319 reg = reg, mask = ~(1 << storageBit), res = lastDst, bit = 1 << storageBit |
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320 )) |
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321 elif prog.paramSize(prog.lastDst) > prog.paramSize(storage): |
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322 reg = prog.resolveReg(storage, None, {}) |
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323 output.append('\n\t{reg} = {res} != 0;'.format( |
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324 reg = reg, res = lastDst |
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325 )) |
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326 else: |
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327 reg = prog.resolveReg(storage, None, {}) |
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328 output.append('\n\t{reg} = {res};'.format(reg = reg, res = lastDst)) |
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329 elif calc == 'half-carry': |
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330 pass |
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331 elif calc == 'carry': |
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332 pass |
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333 elif calc == 'overflow': |
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334 pass |
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335 elif calc == 'parity': |
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336 pass |
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337 #TODO: combine explicit flags targeting the same storage location |
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338 for flag in explicit: |
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339 location = prog.flags.getStorage(flag) |
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340 if type(location) is tuple: |
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341 reg,bit = location |
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342 reg = prog.resolveReg(reg, None, {}) |
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343 value = str(1 << bit) |
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344 if explicit[flag]: |
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345 operator = '|=' |
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346 else: |
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347 operator = '&=' |
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348 value = '~' + value |
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349 output.append('\n\t{reg} {op} {val};'.format(reg=reg, op=operator, val=value)) |
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350 else: |
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351 reg = prog.resolveReg(location, None, {}) |
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352 output.append('\n\t{reg} = {val};'.format(reg=reg, val=explicit[flag])) |
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353 return ''.join(output) |
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354 |
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355 def _cmpCImpl(prog, params): |
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356 size = prog.paramSize(params[1]) |
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357 tmpvar = 'cmp_tmp{sz}__'.format(sz=size) |
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358 typename = '' |
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359 if not prog.currentScope.resolveLocal(tmpvar): |
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360 prog.currentScope.addLocal(tmpvar, size) |
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361 typename = 'uint{sz}_t '.format(sz=size) |
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362 prog.lastDst = tmpvar |
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363 return '\n\t{tp}{var} = {b} - {a};'.format(tp = typename, var = tmpvar, a = params[0], b = params[1]) |
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364 |
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365 def _asrCImpl(prog, params, rawParams): |
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366 shiftSize = prog.paramSize(rawParams[0]) |
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367 mask = 1 << (shiftSize - 1) |
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368 return '\n\t{dst} = ({a} >> {b}) | ({a} & {mask}'.format(a = params[0], b = params[1], dst = params[2], mask = mask) |
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369 |
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370 _opMap = { |
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371 'mov': Op(lambda val: val).cUnaryOperator(''), |
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372 'not': Op(lambda val: ~val).cUnaryOperator('~'), |
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373 'lnot': Op(lambda val: 0 if val else 1).cUnaryOperator('!'), |
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374 'neg': Op(lambda val: -val).cUnaryOperator('-'), |
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375 'add': Op(lambda a, b: a + b).cBinaryOperator('+'), |
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376 'sub': Op(lambda a, b: b - a).cBinaryOperator('-'), |
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377 'lsl': Op(lambda a, b: a << b).cBinaryOperator('<<'), |
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378 'lsr': Op(lambda a, b: a >> b).cBinaryOperator('>>'), |
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379 'asr': Op(lambda a, b: a >> b).addImplementation('c', 2, _asrCImpl), |
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380 'and': Op(lambda a, b: a & b).cBinaryOperator('&'), |
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381 'or': Op(lambda a, b: a | b).cBinaryOperator('|'), |
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382 'xor': Op(lambda a, b: a ^ b).cBinaryOperator('^'), |
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383 'cmp': Op().addImplementation('c', None, _cmpCImpl), |
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384 'ocall': Op().addImplementation('c', None, lambda prog, params: '\n\t{pre}{fun}({args});'.format( |
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385 pre = prog.prefix, fun = params[0], args = ', '.join(['context'] + [str(p) for p in params[1:]]) |
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386 )), |
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387 'cycles': Op().addImplementation('c', None, |
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388 lambda prog, params: '\n\tcontext->current_cycle += context->opts->gen.clock_divider * {0};'.format( |
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389 params[0] |
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390 ) |
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391 ), |
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392 'addsize': Op( |
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393 lambda a, b: b + (2 * a if a else 1) |
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394 ).addImplementation('c', 2, lambda prog, params: '\n\t{dst} = {val} + {sz} ? {sz} * 2 : 1;'.format( |
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395 dst = params[1], sz = params[0], val = params[1] |
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396 )), |
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397 'decsize': Op( |
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398 lambda a, b: b - (2 * a if a else 1) |
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399 ).addImplementation('c', 2, lambda prog, params: '\n\t{dst} = {val} - {sz} ? {sz} * 2 : 1;'.format( |
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400 dst = params[2], sz = params[0], val = params[1] |
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401 )), |
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402 'xchg': Op().addImplementation('c', (0,1), _xchgCImpl), |
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403 'dispatch': Op().addImplementation('c', None, _dispatchCImpl), |
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404 'update_flags': Op().addImplementation('c', None, _updateFlagsCImpl) |
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405 } |
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406 |
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407 #represents a simple DSL instruction |
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408 class NormalOp: |
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409 def __init__(self, parts): |
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410 self.op = parts[0] |
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411 self.params = parts[1:] |
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412 |
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413 def generate(self, prog, parent, fieldVals, output, otype): |
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414 procParams = [] |
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415 allParamsConst = True |
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416 opDef = _opMap.get(self.op) |
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417 for param in self.params: |
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418 allowConst = (self.op in prog.subroutines or len(procParams) != len(self.params) - 1) and param in parent.regValues |
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419 isDst = (not opDef is None) and len(procParams) in opDef.outOp |
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420 param = prog.resolveParam(param, parent, fieldVals, allowConst, isDst) |
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421 |
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422 if (not type(param) is int) and len(procParams) != len(self.params) - 1: |
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423 allParamsConst = False |
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424 procParams.append(param) |
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425 |
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426 if self.op == 'meta': |
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427 param,_,index = self.params[1].partition('.') |
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428 if index: |
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429 index = (parent.resolveLocal(index) or index) |
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430 if index in fieldVals: |
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431 index = str(fieldVals[index]) |
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432 param = param + '.' + index |
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433 else: |
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434 param = parent.resolveLocal(param) or param |
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435 if param in fieldVals: |
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436 param = fieldVals[index] |
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437 prog.meta[self.params[0]] = param |
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438 elif self.op == 'dis': |
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439 #TODO: Disassembler |
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440 pass |
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441 elif not opDef is None: |
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442 if opDef.canEval() and allParamsConst: |
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443 #do constant folding |
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444 if opDef.numArgs() >= len(procParams): |
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445 raise Exception('Insufficient args for ' + self.op + ' (' + ', '.join(self.params) + ')') |
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446 dst = self.params[opDef.numArgs()] |
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447 result = opDef.evaluate(procParams[:opDef.numArgs()]) |
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448 while dst in prog.meta: |
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449 dst = prog.meta[dst] |
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450 maybeLocal = parent.resolveLocal(dst) |
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451 if maybeLocal: |
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452 dst = maybeLocal |
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453 parent.regValues[dst] = result |
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454 if prog.isReg(dst): |
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455 output.append(_opMap['mov'].generate(otype, prog, procParams, self.params)) |
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456 else: |
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457 output.append(opDef.generate(otype, prog, procParams, self.params)) |
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458 elif self.op in prog.subroutines: |
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459 prog.subroutines[self.op].inline(prog, procParams, output, otype, parent) |
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460 else: |
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461 output.append('\n\t' + self.op + '(' + ', '.join([str(p) for p in procParams]) + ');') |
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462 prog.lastOp = self |
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463 |
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464 def __str__(self): |
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465 return '\n\t' + self.op + ' ' + ' '.join(self.params) |
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466 |
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467 #represents a DSL switch construct |
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468 class Switch(ChildBlock): |
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469 def __init__(self, parent, param): |
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470 self.op = 'switch' |
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471 self.parent = parent |
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472 self.param = param |
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473 self.cases = {} |
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474 self.regValues = None |
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475 self.current_locals = {} |
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476 self.case_locals = {} |
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477 self.current_case = None |
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478 self.default = None |
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479 self.default_locals = None |
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480 |
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481 def addOp(self, op): |
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482 if op.op == 'case': |
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483 self.cases[int(op.params[0])] = self.current_case = [] |
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484 self.case_locals[int(op.params[0])] = self.current_locals = {} |
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485 elif op.op == 'default': |
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486 self.default = self.current_case = [] |
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487 self.default_locals = self.current_locals = {} |
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488 elif self.current_case == None: |
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489 raise ion('Orphan instruction in switch') |
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490 elif op.op == 'local': |
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491 name = op.params[0] |
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492 size = op.params[1] |
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493 self.current_locals[name] = size |
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494 else: |
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495 self.current_case.append(op) |
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496 |
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497 def resolveLocal(self, name): |
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498 if name in self.current_locals: |
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499 return name |
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500 return self.parent.resolveLocal(name) |
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501 |
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502 def addLocal(self, name, size): |
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503 self.current_locals[name] = size |
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504 |
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505 def localSize(self, name): |
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506 if name in self.current_locals: |
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507 return self.current_locals[name] |
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508 return self.parent.localSize(name) |
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509 |
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510 def generate(self, prog, parent, fieldVals, output, otype): |
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511 oldScope = prog.currentScope |
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512 prog.currentScope = self |
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513 self.regValues = self.parent.regValues |
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514 param = prog.resolveParam(self.param, parent, fieldVals) |
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515 if type(param) is int: |
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516 if param in self.cases: |
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517 if self.case_locals[param]: |
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518 output.append('\n\t{') |
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519 for local in self.case_locals[param]: |
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520 output.append('\n\tuint{0}_t {1};'.format(self.case_locals[param][local], local)) |
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521 for op in self.cases[param]: |
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522 op.generate(prog, self, fieldVals, output, otype) |
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523 if self.case_locals[param]: |
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524 output.append('\n\t}') |
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525 elif self.default: |
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526 if self.default_locals: |
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527 output.append('\n\t{') |
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528 for local in self.default: |
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529 output.append('\n\tuint{0}_t {1};'.format(self.default[local], local)) |
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530 for op in self.default: |
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531 op.generate(prog, self, fieldVals, output, otype) |
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532 else: |
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533 output.append('\n\tswitch(' + param + ')') |
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534 output.append('\n\t{') |
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535 for case in self.cases: |
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536 output.append('\n\tcase {0}: '.format(case) + '{') |
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537 for local in self.case_locals[case]: |
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538 output.append('\n\tuint{0}_t {1};'.format(self.case_locals[case][local], local)) |
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539 for op in self.cases[case]: |
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540 op.generate(prog, self, fieldVals, output, otype) |
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541 output.append('\n\tbreak;') |
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542 output.append('\n\t}') |
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543 if self.default: |
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544 output.append('\n\tdefault: {') |
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545 for local in self.default_locals: |
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546 output.append('\n\tuint{0}_t {1};'.format(self.default_locals[local], local)) |
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547 for op in self.default: |
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548 op.generate(prog, self, fieldVals, output, otype) |
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549 output.append('\n\t}') |
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550 prog.currentScope = oldScope |
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551 |
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552 def __str__(self): |
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553 keys = self.cases.keys() |
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554 keys.sort() |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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555 lines = ['\n\tswitch'] |
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|
556 for case in keys: |
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557 lines.append('\n\tcase {0}'.format(case)) |
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558 lines.append(''.join([str(op) for op in self.cases[case]])) |
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559 lines.append('\n\tend') |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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560 return ''.join(lines) |
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561 |
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562 |
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563 def _geuCImpl(prog, parent, fieldVals, output): |
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564 if prog.lastOp.op == 'cmp': |
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565 output.pop() |
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566 params = prog.lastOp.params |
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567 for i in range(0, len(params)): |
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568 params[i] = prog.resolveParam(params[i], parent, fieldVals) |
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569 return '\n\tif ({a} >= {b}) '.format(a=params[0], b = params[1]) + '{' |
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570 else: |
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571 raise ion(">=U not implemented in the general case yet") |
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572 |
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573 _ifCmpImpl = { |
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574 'c': { |
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575 '>=U': _geuCImpl |
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576 } |
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577 } |
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578 #represents a DSL conditional construct |
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579 class If(ChildBlock): |
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580 def __init__(self, parent, cond): |
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581 self.op = 'if' |
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582 self.parent = parent |
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583 self.cond = cond |
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584 self.body = [] |
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585 self.elseBody = [] |
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586 self.curBody = self.body |
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587 self.locals = {} |
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588 self.regValues = parent.regValues |
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589 |
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590 def addOp(self, op): |
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591 if op.op in ('case', 'arg'): |
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592 raise Exception(self.op + ' is not allows inside an if block') |
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593 if op.op == 'local': |
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594 name = op.params[0] |
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595 size = op.params[1] |
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596 self.locals[name] = size |
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597 elif op.op == 'else': |
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598 self.curBody = self.elseBody |
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599 else: |
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600 self.curBody.append(op) |
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601 |
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602 def generate(self, prog, parent, fieldVals, output, otype): |
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603 try: |
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604 if prog.checkBool(self.cond): |
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605 for op in self.body: |
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606 op.generate(prog, self, fieldVals, output, otype) |
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607 else: |
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608 for op in self.elseBody: |
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609 op.generate(prog, self, fieldVals, output, otype) |
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610 except Exception: |
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611 if self.cond in _ifCmpImpl[otype]: |
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612 output.append(_ifCmpImpl[otype][self.cond](prog, parent, fieldVals, output)) |
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613 for op in self.body: |
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614 op.generate(prog, self, fieldVals, output, otype) |
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615 if self.elseBody: |
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616 output.append('\n\t} else {') |
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617 for op in self.elseBody: |
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618 op.generate(prog, self, fieldVals, output, otype) |
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619 output.append('\n\t}') |
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620 else: |
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621 cond = prog.resolveParam(self.cond, parent, fieldVals) |
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622 if type(cond) is int: |
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623 if cond: |
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624 for op in self.body: |
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625 op.generate(prog, self, fieldVals, output, otype) |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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626 else: |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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627 for op in self.elseBody: |
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628 op.generate(prog, self, fieldVals, output, otype) |
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629 else: |
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630 output.append('\n\tif ({cond}) {'.format(cond=cond)) |
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631 for op in self.body: |
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632 op.generate(prog, self, fieldVals, output, otype) |
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633 if self.elseBody: |
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634 output.append('\n\t} else {') |
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635 for op in self.elseBody: |
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636 op.generate(prog, self, fieldVals, output, otype) |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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637 output.append('\n\t}') |
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638 |
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639 |
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640 def __str__(self): |
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641 lines = ['\n\tif'] |
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642 for op in self.body: |
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643 lines.append(str(op)) |
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644 lines.append('\n\tend') |
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645 return ''.join(lines) |
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646 |
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647 class Registers: |
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648 def __init__(self): |
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649 self.regs = {} |
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650 self.regArrays = {} |
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651 self.regToArray = {} |
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652 |
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653 def addReg(self, name, size): |
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654 self.regs[name] = size |
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655 |
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656 def addRegArray(self, name, size, regs): |
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|
657 self.regArrays[name] = (size, regs) |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
658 idx = 0 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
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|
659 for reg in regs: |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
diff
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|
660 self.regs[reg] = size |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
diff
changeset
|
661 self.regToArray[reg] = (name, idx) |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
diff
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|
662 idx += 1 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
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|
663 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
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|
664 def isReg(self, name): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
665 return name in self.regs |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
666 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
667 def isRegArray(self, name): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
diff
changeset
|
668 return name in self.regArrays |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
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|
669 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
670 def isRegArrayMember(self, name): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
671 return name in self.regToArray |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
672 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
673 def arrayMemberParent(self, name): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
674 return self.regToArray[name][0] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
675 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
676 def arrayMemberIndex(self, name): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
677 return self.regToArray[name][1] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
678 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
679 def arrayMemberName(self, array, index): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
680 if type(index) is int: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
681 return self.regArrays[array][1][index] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
682 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
683 return None |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
684 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
685 def processLine(self, parts): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
686 if len(parts) > 2: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
687 self.addRegArray(parts[0], int(parts[1]), parts[2:]) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
688 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
689 self.addReg(parts[0], int(parts[1])) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
690 return self |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
691 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
692 class Flags: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
693 def __init__(self): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
694 self.flagBits = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
695 self.flagCalc = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
696 self.flagStorage = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
697 self.flagReg = None |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
698 self.maxBit = -1 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
699 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
700 def processLine(self, parts): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
701 if parts[0] == 'register': |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
702 self.flagReg = parts[1] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
703 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
704 flag,bit,calc,storage = parts |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
705 bit,_,top = bit.partition('-') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
706 bit = int(bit) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
707 if top: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
708 top = int(bit) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
709 if top > self.maxBit: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
710 self.maxBit = top |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
711 self.flagBits[flag] = (bit,top) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
712 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
713 if bit > self.maxBit: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
714 self.maxBit = bit |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
715 self.flagBits[flag] = bit |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
716 self.flagCalc[flag] = calc |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
717 self.flagStorage[flag] = storage |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
718 return self |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
719 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
720 def getStorage(self, flag): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
721 if not flag in self.flagStorage: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
722 raise Exception('Undefined flag ' + flag) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
723 loc,_,bit = self.flagStorage[flag].partition('.') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
724 if bit: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
725 return (loc, int(bit)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
726 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
727 return loc |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
728 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
729 def disperseFlags(self, prog, otype): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
730 bitToFlag = [None] * (self.maxBit+1) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
731 src = prog.resolveReg(self.flagReg, None, {}) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
732 output = [] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
733 for flag in self.flagBits: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
734 bit = self.flagBits[flag] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
735 if type(bit) is tuple: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
736 bot,top = bit |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
737 mask = ((1 << (top + 1 - bot)) - 1) << bot |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
738 output.append('\n\t{dst} = {src} & mask;'.format( |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
739 dst=prog.resolveReg(self.flagStorage[flag], None, {}), src=src, mask=mask |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
740 )) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
741 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
742 bitToFlag[self.flagBits[flag]] = flag |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
743 multi = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
744 for bit in range(len(bitToFlag)-1,-1,-1): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
745 flag = bitToFlag[bit] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
746 if not flag is None: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
747 field,_,dstbit = self.flagStorage[flag].partition('.') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
748 dst = prog.resolveReg(field, None, {}) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
749 if dstbit: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
750 dstbit = int(dstbit) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
751 multi.setdefault(dst, []).append((dstbit, bit)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
752 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
753 output.append('\n\t{dst} = {src} & {mask};'.format(dst=dst, src=src, mask=(1 << bit))) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
754 for dst in multi: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
755 didClear = False |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
756 direct = [] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
757 for dstbit, bit in multi[dst]: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
758 if dstbit == bit: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
759 direct.append(bit) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
760 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
761 if not didClear: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
762 output.append('\n\t{dst} = 0;'.format(dst=dst)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
763 didClear = True |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
764 if dstbit > bit: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
765 shift = '<<' |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
766 diff = dstbit - bit |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
767 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
768 shift = '>>' |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
769 diff = bit - dstbit |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
770 output.append('\n\t{dst} |= {src} {shift} {diff} & {mask};'.format( |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
771 src=src, dst=dst, shift=shift, diff=diff, mask=(1 << dstbit) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
772 )) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
773 if direct: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
774 if len(direct) == len(multi[dst]): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
775 output.append('\n\t{dst} = {src};'.format(dst=dst, src=src)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
776 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
777 mask = 0 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
778 for bit in direct: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
779 mask = mask | (1 << bit) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
780 output.append('\n\t{dst} = {src} & {mask};'.format(dst=dst, src=src, mask=mask)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
781 return ''.join(output) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
782 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
783 def coalesceFlags(self, prog, otype): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
784 dst = prog.resolveReg(self.flagReg, None, {}) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
785 output = ['\n\t{dst} = 0;'.format(dst=dst)] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
786 bitToFlag = [None] * (self.maxBit+1) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
787 for flag in self.flagBits: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
788 bit = self.flagBits[flag] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
789 if type(bit) is tuple: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
790 bot,_ = bit |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
791 src = prog.resolveReg(self.flagStorage[flag], None, {}) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
792 if bot: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
793 output.append('\n\t{dst} |= {src} << {shift};'.format( |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
794 dst=dst, src = src, shift = bot |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
795 )) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
796 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
797 output.append('\n\t{dst} |= {src};'.format( |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
798 dst=dst, src = src |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
799 )) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
800 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
801 bitToFlag[bit] = flag |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
802 multi = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
803 for bit in range(len(bitToFlag)-1,-1,-1): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
804 flag = bitToFlag[bit] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
805 if not flag is None: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
806 field,_,srcbit = self.flagStorage[flag].partition('.') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
807 src = prog.resolveReg(field, None, {}) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
808 if srcbit: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
809 srcbit = int(srcbit) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
810 multi.setdefault(src, []).append((srcbit,bit)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
811 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
812 output.append('\n\tif ({src}) {{\n\t\t{dst} |= 1 << {bit};\n\t}}'.format( |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
813 dst=dst, src=src, bit=bit |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
814 )) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
815 for src in multi: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
816 direct = 0 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
817 for srcbit, dstbit in multi[src]: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
818 if srcbit == dstbit: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
819 direct = direct | (1 << srcbit) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
820 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
821 output.append('\n\tif ({src} & (1 << {srcbit})) {{\n\t\t{dst} |= 1 << {dstbit};\n\t}}'.format( |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
822 src=src, dst=dst, srcbit=srcbit, dstbit=dstbit |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
823 )) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
824 if direct: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
825 output.append('\n\t{dst} |= {src} & {mask}'.format( |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
826 dst=dst, src=src, mask=direct |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
827 )) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
828 return ''.join(output) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
829 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
830 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
831 class Program: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
832 def __init__(self, regs, instructions, subs, info, flags): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
833 self.regs = regs |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
834 self.instructions = instructions |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
835 self.subroutines = subs |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
836 self.meta = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
837 self.booleans = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
838 self.prefix = info.get('prefix', [''])[0] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
839 self.opsize = int(info.get('opcode_size', ['8'])[0]) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
840 self.extra_tables = info.get('extra_tables', []) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
841 self.context_type = self.prefix + 'context' |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
842 self.body = info.get('body', [None])[0] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
843 self.flags = flags |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
844 self.lastDst = None |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
845 self.currentScope = None |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
846 self.lastOp = None |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
847 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
848 def __str__(self): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
849 pieces = [] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
850 for reg in self.regs: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
851 pieces.append(str(self.regs[reg])) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
852 for name in self.subroutines: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
853 pieces.append('\n'+str(self.subroutines[name])) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
854 for instruction in self.instructions: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
855 pieces.append('\n'+str(instruction)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
856 return ''.join(pieces) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
857 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
858 def build(self, otype): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
859 body = [] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
860 pieces = [] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
861 for table in self.instructions: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
862 opmap = [None] * (1 << self.opsize) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
863 bodymap = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
864 instructions = self.instructions[table] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
865 instructions.sort() |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
866 for inst in instructions: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
867 for val in inst.allValues(): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
868 if opmap[val] is None: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
869 self.meta = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
870 self.temp = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
871 self.needFlagCoalesce = False |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
872 self.needFlagDisperse = False |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
873 self.lastOp = None |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
874 opmap[val] = inst.generateName(val) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
875 bodymap[val] = inst.generateBody(val, self, otype) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
876 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
877 pieces.append('\nstatic void *impl_{name}[{sz}] = {{'.format(name = table, sz=len(opmap))) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
878 for inst in range(0, len(opmap)): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
879 op = opmap[inst] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
880 if op is None: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
881 pieces.append('\n\tunimplemented,') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
882 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
883 pieces.append('\n\t' + op + ',') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
884 body.append(bodymap[inst]) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
885 pieces.append('\n};') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
886 if self.body in self.subroutines: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
887 pieces.append('\nvoid {pre}execute({type} *context, uint32_t target_cycle)'.format(pre = self.prefix, type = self.context_type)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
888 pieces.append('\n{') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
889 pieces.append('\n\twhile (context->current_cycle < target_cycle)') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
890 pieces.append('\n\t{') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
891 self.meta = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
892 self.temp = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
893 self.subroutines[self.body].inline(self, [], pieces, otype, None) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
894 pieces.append('\n\t}') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
895 pieces.append('\n}') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
896 return ''.join(body) + ''.join(pieces) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
897 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
898 def checkBool(self, name): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
899 if not name in self.booleans: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
900 raise Exception(name + ' is not a defined boolean flag') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
901 return self.booleans[name] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
902 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
903 def getTemp(self, size): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
904 if size in self.temp: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
905 return ('', self.temp[size]) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
906 self.temp[size] = 'tmp{sz}'.format(sz=size); |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
907 return ('\n\tuint{sz}_t tmp{sz};'.format(sz=size), self.temp[size]) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
908 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
909 def resolveParam(self, param, parent, fieldVals, allowConstant=True, isdst=False): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
910 keepGoing = True |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
911 while keepGoing: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
912 keepGoing = False |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
913 try: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
914 if type(param) is int: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
915 pass |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
916 elif param.startswith('0x'): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
917 param = int(param, 16) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
918 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
919 param = int(param) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
920 except ValueError: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
921 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
922 if parent: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
923 if param in parent.regValues and allowConstant: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
924 return parent.regValues[param] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
925 maybeLocal = parent.resolveLocal(param) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
926 if maybeLocal: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
927 return maybeLocal |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
928 if param in fieldVals: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
929 param = fieldVals[param] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
930 elif param in self.meta: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
931 param = self.meta[param] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
932 keepGoing = True |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
933 elif self.isReg(param): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
934 param = self.resolveReg(param, parent, fieldVals, isdst) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
935 return param |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
936 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
937 def isReg(self, name): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
938 if not type(name) is str: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
939 return False |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
940 begin,sep,_ = name.partition('.') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
941 if sep: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
942 if begin in self.meta: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
943 begin = self.meta[begin] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
944 return self.regs.isRegArray(begin) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
945 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
946 return self.regs.isReg(name) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
947 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
948 def resolveReg(self, name, parent, fieldVals, isDst=False): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
949 begin,sep,end = name.partition('.') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
950 if sep: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
951 if begin in self.meta: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
952 begin = self.meta[begin] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
953 if not self.regs.isRegArrayMember(end): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
954 end = self.resolveParam(end, parent, fieldVals) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
955 if not type(end) is int and self.regs.isRegArrayMember(end): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
956 arrayName = self.regs.arrayMemberParent(end) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
957 end = self.regs.arrayMemberIndex(end) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
958 if arrayName != begin: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
959 end = 'context->{0}[{1}]'.format(arrayName, end) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
960 regName = self.regs.arrayMemberName(begin, end) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
961 ret = 'context->{0}[{1}]'.format(begin, end) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
962 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
963 regName = name |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
964 if self.regs.isRegArrayMember(name): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
965 arr,idx = self.regs.regToArray[name] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
966 ret = 'context->{0}[{1}]'.format(arr, idx) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
967 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
968 ret = 'context->' + name |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
969 if regName == self.flags.flagReg: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
970 if isDst: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
971 self.needFlagDisperse = True |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
972 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
973 self.needFlagCoalesce = True |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
974 if isDst: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
975 self.lastDst = regName |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
976 return ret |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
977 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
978 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
979 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
980 def paramSize(self, name): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
981 size = self.currentScope.localSize(name) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
982 if size: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
983 return size |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
984 begin,sep,_ = name.partition('.') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
985 if sep and self.regs.isRegArray(begin): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
986 return self.regs.regArrays[begin][0] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
987 if self.regs.isReg(name): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
988 return self.regs.regs[name] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
989 return 32 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
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|
990 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
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|
991 def parse(f): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
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|
992 instructions = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
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|
993 subroutines = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
994 registers = None |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
995 flags = None |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
996 errors = [] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
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|
997 info = {} |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
998 line_num = 0 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
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|
999 cur_object = None |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
diff
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|
1000 for line in f: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
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|
1001 line_num += 1 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
1002 line,_,comment = line.partition('#') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
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|
1003 if not line.strip(): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
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|
1004 continue |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
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|
1005 if line[0].isspace(): |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
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|
1006 if not cur_object is None: |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
1007 parts = [el.strip() for el in line.split(' ')] |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
1008 if type(cur_object) is dict: |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
1009 cur_object[parts[0]] = parts[1:] |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
1010 else: |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
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|
1011 cur_object = cur_object.processLine(parts) |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
1012 |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
1013 # if type(cur_object) is Registers: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
1014 # if len(parts) > 2: |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
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|
1015 # cur_object.addRegArray(parts[0], int(parts[1]), parts[2:]) |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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1016 # else: |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
1017 # cur_object.addReg(parts[0], int(parts[1])) |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
1018 # elif type(cur_object) is dict: |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
1019 # cur_object[parts[0]] = parts[1:] |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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1020 # elif parts[0] == 'switch': |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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1021 # o = Switch(cur_object, parts[1]) |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
1022 # cur_object.addOp(o) |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
1023 # cur_object = o |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
1024 # elif parts[0] == 'if': |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
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|
1025 # o = If(cur_object, parts[1]) |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
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|
1026 # cur_object.addOp(o) |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
1027 # cur_object = o |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
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|
1028 # elif parts[0] == 'end': |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
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|
1029 # cur_object = cur_object.parent |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
1030 # else: |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
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|
1031 # cur_object.addOp(NormalOp(parts)) |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
1032 else: |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
1033 errors.append("Orphan instruction on line {0}".format(line_num)) |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
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|
1034 else: |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
1035 parts = line.split(' ') |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
1036 if len(parts) > 1: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
1037 if len(parts) > 2: |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
diff
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|
1038 table,bitpattern,name = parts |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
diff
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|
1039 else: |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
1040 bitpattern,name = parts |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
1041 table = 'main' |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
diff
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|
1042 value = 0 |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
1043 fields = {} |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
1044 curbit = len(bitpattern) - 1 |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
1045 for char in bitpattern: |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
1046 value <<= 1 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
1047 if char in ('0', '1'): |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
1048 value |= int(char) |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
diff
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|
1049 else: |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
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|
1050 if char in fields: |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
1051 fields[char] = (curbit, fields[char][1] + 1) |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
1052 else: |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
1053 fields[char] = (curbit, 1) |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
1054 curbit -= 1 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
1055 cur_object = Instruction(value, fields, name.strip()) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
1056 instructions.setdefault(table, []).append(cur_object) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
1057 elif line.strip() == 'regs': |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
1058 if registers is None: |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
1059 registers = Registers() |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
diff
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|
1060 cur_object = registers |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
diff
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|
1061 elif line.strip() == 'info': |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
1062 cur_object = info |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
1063 elif line.strip() == 'flags': |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
1064 if flags is None: |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
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|
1065 flags = Flags() |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
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|
1066 cur_object = flags |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
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|
1067 else: |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
1068 cur_object = SubRoutine(line.strip()) |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
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|
1069 subroutines[cur_object.name] = cur_object |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
1070 if errors: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
1071 print(errors) |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
1072 else: |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
1073 p = Program(registers, instructions, subroutines, info, flags) |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
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|
1074 p.booleans['dynarec'] = False |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
1075 p.booleans['interp'] = True |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
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|
1076 |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
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|
1077 print('#include "m68k_prefix.c"') |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
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|
1078 print(p.build('c')) |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
1079 |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
1080 def main(argv): |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
diff
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|
1081 f = open(argv[1]) |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
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|
1082 parse(f) |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
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|
1083 |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
diff
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|
1084 if __name__ == '__main__': |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
diff
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|
1085 from sys import argv |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
1086 main(argv) |