Mercurial > repos > blastem
annotate runtime.S @ 345:29d2ca563499
Don't sync the 68K clock to the VDP clock unless the 68K had to wait for the VDP. This unfortunately breaks the direct color DMA demos, but should be more correct overall.
author | Mike Pavone <pavone@retrodev.com> |
---|---|
date | Sun, 19 May 2013 13:47:47 -0700 |
parents | b46771135442 |
children | b24556b45d1e |
rev | line source |
---|---|
17
de0085d4ea40
Add asssembly runtime code stub
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1 |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
2 .global handle_cycle_limit |
150
3e68e517cc01
Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed.
Mike Pavone <pavone@retrodev.com>
parents:
149
diff
changeset
|
3 .global do_sync |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
4 handle_cycle_limit: |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
5 cmp 84(%rsi), %eax |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
6 jb skip_sync |
150
3e68e517cc01
Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed.
Mike Pavone <pavone@retrodev.com>
parents:
149
diff
changeset
|
7 do_sync: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
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8 push %rcx |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
|
9 push %rdi |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
10 call m68k_save_context |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
11 mov %rsi, %rdi |
198
209a37eed3e7
Add support for breaking into the debugger while game is running
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
12 xor %esi, %esi |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
13 call sync_components |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
14 mov %rax, %rsi |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
15 call m68k_load_context |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
|
16 pop %rdi |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
|
17 pop %rcx |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
18 skip_sync: |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
19 ret |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
20 |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
21 .global handle_cycle_limit_int |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
22 handle_cycle_limit_int: |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
23 cmp 88(%rsi), %eax |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
24 jb skip_int |
251
4a7ac10ac2d9
Fix target cycle count after 68K interrupt
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
25 mov 84(%rsi), %ebp |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
26 /* swap USP and SSP if not already in supervisor mode */ |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
27 bt $5, 5(%rsi) |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
28 jc already_supervisor |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
29 mov 72(%rsi), %edi |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
30 mov %r15d, 72(%rsi) |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
31 mov %edi, %r15d |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
32 already_supervisor: |
175
7504200cac86
Fix order of SR and PC saved in an exception stack frame
Mike Pavone <pavone@retrodev.com>
parents:
160
diff
changeset
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33 /* save PC */ |
7504200cac86
Fix order of SR and PC saved in an exception stack frame
Mike Pavone <pavone@retrodev.com>
parents:
160
diff
changeset
|
34 sub $4, %r15d |
7504200cac86
Fix order of SR and PC saved in an exception stack frame
Mike Pavone <pavone@retrodev.com>
parents:
160
diff
changeset
|
35 mov %r15d, %edi |
7504200cac86
Fix order of SR and PC saved in an exception stack frame
Mike Pavone <pavone@retrodev.com>
parents:
160
diff
changeset
|
36 call m68k_write_long_lowfirst |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
37 /* save status register on stack */ |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
38 sub $2, %r15d |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
39 mov %r15d, %edi |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
40 call get_sr |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
41 call m68k_write_word |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
42 /* update status register */ |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
43 andb $0xF8, 5(%rsi) |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
44 mov 92(%rsi), %cl |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
45 or $0x20, %cl |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
46 or %cl, 5(%rsi) |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
47 /* calculate interrupt vector address */ |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
48 mov 92(%rsi), %ecx |
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
251
diff
changeset
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49 mov %cx, 6(%rsi) /* interrupt acknowlege */ |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
50 shl $2, %ecx |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
51 add $0x60, %ecx |
321
146c87616b05
Don't update interrupt mask on non-interrupt exceptions
Mike Pavone <pavone@retrodev.com>
parents:
320
diff
changeset
|
52 /* push %rcx |
146c87616b05
Don't update interrupt mask on non-interrupt exceptions
Mike Pavone <pavone@retrodev.com>
parents:
320
diff
changeset
|
53 call debug_print_sr_int |
146c87616b05
Don't update interrupt mask on non-interrupt exceptions
Mike Pavone <pavone@retrodev.com>
parents:
320
diff
changeset
|
54 pop %rcx */ |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
55 call m68k_read_long_scratch1 |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
56 call m68k_native_addr_and_sync |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
57 add $24, %eax |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
58 /* discard function return address */ |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
59 pop %rdi |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
60 jmp *%rcx |
150
3e68e517cc01
Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed.
Mike Pavone <pavone@retrodev.com>
parents:
149
diff
changeset
|
61 ret |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
62 skip_int: |
150
3e68e517cc01
Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed.
Mike Pavone <pavone@retrodev.com>
parents:
149
diff
changeset
|
63 cmp 84(%rsi), %eax |
198
209a37eed3e7
Add support for breaking into the debugger while game is running
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
64 jb skip_sync_int |
209a37eed3e7
Add support for breaking into the debugger while game is running
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
65 call m68k_save_context |
209a37eed3e7
Add support for breaking into the debugger while game is running
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
66 mov %rsi, %rdi |
209a37eed3e7
Add support for breaking into the debugger while game is running
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
67 mov %ecx, %esi |
209a37eed3e7
Add support for breaking into the debugger while game is running
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
68 call sync_components |
209a37eed3e7
Add support for breaking into the debugger while game is running
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
69 mov %rax, %rsi |
209a37eed3e7
Add support for breaking into the debugger while game is running
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
70 call m68k_load_context |
209a37eed3e7
Add support for breaking into the debugger while game is running
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
71 skip_sync_int: |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
72 ret |
87
60b5c9e2f4e0
vertical interrupts now work
Mike Pavone <pavone@retrodev.com>
parents:
86
diff
changeset
|
73 |
321
146c87616b05
Don't update interrupt mask on non-interrupt exceptions
Mike Pavone <pavone@retrodev.com>
parents:
320
diff
changeset
|
74 sr_msg_int: |
146c87616b05
Don't update interrupt mask on non-interrupt exceptions
Mike Pavone <pavone@retrodev.com>
parents:
320
diff
changeset
|
75 .asciz "SR set to $%X due to interrupt\n" |
146c87616b05
Don't update interrupt mask on non-interrupt exceptions
Mike Pavone <pavone@retrodev.com>
parents:
320
diff
changeset
|
76 debug_print_sr_int: |
146c87616b05
Don't update interrupt mask on non-interrupt exceptions
Mike Pavone <pavone@retrodev.com>
parents:
320
diff
changeset
|
77 call m68k_save_context |
146c87616b05
Don't update interrupt mask on non-interrupt exceptions
Mike Pavone <pavone@retrodev.com>
parents:
320
diff
changeset
|
78 push %rsi |
146c87616b05
Don't update interrupt mask on non-interrupt exceptions
Mike Pavone <pavone@retrodev.com>
parents:
320
diff
changeset
|
79 lea sr_msg_int(%rip), %rdi |
146c87616b05
Don't update interrupt mask on non-interrupt exceptions
Mike Pavone <pavone@retrodev.com>
parents:
320
diff
changeset
|
80 movzxb 5(%rsi), %rsi |
146c87616b05
Don't update interrupt mask on non-interrupt exceptions
Mike Pavone <pavone@retrodev.com>
parents:
320
diff
changeset
|
81 xor %rax, %rax |
146c87616b05
Don't update interrupt mask on non-interrupt exceptions
Mike Pavone <pavone@retrodev.com>
parents:
320
diff
changeset
|
82 call printf |
146c87616b05
Don't update interrupt mask on non-interrupt exceptions
Mike Pavone <pavone@retrodev.com>
parents:
320
diff
changeset
|
83 pop %rsi |
146c87616b05
Don't update interrupt mask on non-interrupt exceptions
Mike Pavone <pavone@retrodev.com>
parents:
320
diff
changeset
|
84 call m68k_load_context |
146c87616b05
Don't update interrupt mask on non-interrupt exceptions
Mike Pavone <pavone@retrodev.com>
parents:
320
diff
changeset
|
85 ret |
146c87616b05
Don't update interrupt mask on non-interrupt exceptions
Mike Pavone <pavone@retrodev.com>
parents:
320
diff
changeset
|
86 |
146c87616b05
Don't update interrupt mask on non-interrupt exceptions
Mike Pavone <pavone@retrodev.com>
parents:
320
diff
changeset
|
87 sr_msg: |
146c87616b05
Don't update interrupt mask on non-interrupt exceptions
Mike Pavone <pavone@retrodev.com>
parents:
320
diff
changeset
|
88 .asciz "SR set to $%X\n" |
146c87616b05
Don't update interrupt mask on non-interrupt exceptions
Mike Pavone <pavone@retrodev.com>
parents:
320
diff
changeset
|
89 .global debug_print_sr |
146c87616b05
Don't update interrupt mask on non-interrupt exceptions
Mike Pavone <pavone@retrodev.com>
parents:
320
diff
changeset
|
90 debug_print_sr: |
146c87616b05
Don't update interrupt mask on non-interrupt exceptions
Mike Pavone <pavone@retrodev.com>
parents:
320
diff
changeset
|
91 call m68k_save_context |
146c87616b05
Don't update interrupt mask on non-interrupt exceptions
Mike Pavone <pavone@retrodev.com>
parents:
320
diff
changeset
|
92 push %rsi |
146c87616b05
Don't update interrupt mask on non-interrupt exceptions
Mike Pavone <pavone@retrodev.com>
parents:
320
diff
changeset
|
93 lea sr_msg(%rip), %rdi |
146c87616b05
Don't update interrupt mask on non-interrupt exceptions
Mike Pavone <pavone@retrodev.com>
parents:
320
diff
changeset
|
94 movzxb 5(%rsi), %rsi |
146c87616b05
Don't update interrupt mask on non-interrupt exceptions
Mike Pavone <pavone@retrodev.com>
parents:
320
diff
changeset
|
95 xor %rax, %rax |
146c87616b05
Don't update interrupt mask on non-interrupt exceptions
Mike Pavone <pavone@retrodev.com>
parents:
320
diff
changeset
|
96 call printf |
146c87616b05
Don't update interrupt mask on non-interrupt exceptions
Mike Pavone <pavone@retrodev.com>
parents:
320
diff
changeset
|
97 pop %rsi |
146c87616b05
Don't update interrupt mask on non-interrupt exceptions
Mike Pavone <pavone@retrodev.com>
parents:
320
diff
changeset
|
98 call m68k_load_context |
146c87616b05
Don't update interrupt mask on non-interrupt exceptions
Mike Pavone <pavone@retrodev.com>
parents:
320
diff
changeset
|
99 ret |
146c87616b05
Don't update interrupt mask on non-interrupt exceptions
Mike Pavone <pavone@retrodev.com>
parents:
320
diff
changeset
|
100 |
152
79958b95526f
Implement TRAP (untested)
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
101 .global m68k_trap |
79958b95526f
Implement TRAP (untested)
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
102 m68k_trap: |
79958b95526f
Implement TRAP (untested)
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
103 push %rdi |
79958b95526f
Implement TRAP (untested)
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
104 push %rcx |
79958b95526f
Implement TRAP (untested)
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
105 /* swap USP and SSP if not already in supervisor mode */ |
79958b95526f
Implement TRAP (untested)
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
106 bt $5, 5(%rsi) |
79958b95526f
Implement TRAP (untested)
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
107 jc already_supervisor_trap |
79958b95526f
Implement TRAP (untested)
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
108 mov 72(%rsi), %edi |
79958b95526f
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diff
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|
109 mov %r15d, 72(%rsi) |
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changeset
|
110 mov %edi, %r15d |
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diff
changeset
|
111 already_supervisor_trap: |
175
7504200cac86
Fix order of SR and PC saved in an exception stack frame
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160
diff
changeset
|
112 /* save PC */ |
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Fix order of SR and PC saved in an exception stack frame
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diff
changeset
|
113 sub $4, %r15d |
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Fix order of SR and PC saved in an exception stack frame
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diff
changeset
|
114 mov %r15d, %edi |
7504200cac86
Fix order of SR and PC saved in an exception stack frame
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160
diff
changeset
|
115 pop %rcx |
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Fix order of SR and PC saved in an exception stack frame
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160
diff
changeset
|
116 call m68k_write_long_lowfirst |
152
79958b95526f
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150
diff
changeset
|
117 /* save status register on stack */ |
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diff
changeset
|
118 sub $2, %r15d |
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Implement TRAP (untested)
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150
diff
changeset
|
119 mov %r15d, %edi |
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diff
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|
120 call get_sr |
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|
121 call m68k_write_word |
321
146c87616b05
Don't update interrupt mask on non-interrupt exceptions
Mike Pavone <pavone@retrodev.com>
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320
diff
changeset
|
122 /* set supervisor bit */ |
146c87616b05
Don't update interrupt mask on non-interrupt exceptions
Mike Pavone <pavone@retrodev.com>
parents:
320
diff
changeset
|
123 or $0x20, 5(%rsi) |
152
79958b95526f
Implement TRAP (untested)
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150
diff
changeset
|
124 /* calculate interrupt vector address */ |
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diff
changeset
|
125 pop %rcx |
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150
diff
changeset
|
126 shl $2, %ecx |
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|
127 call m68k_read_long_scratch1 |
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|
128 call m68k_native_addr_and_sync |
226
28a6697e847b
Implement CHK instruction (not fully tested).
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parents:
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diff
changeset
|
129 add $18, %eax |
152
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|
130 jmp *%rcx |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
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diff
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|
131 |
e2918b5208eb
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|
132 invalid_msg: |
e2918b5208eb
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175
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|
133 .asciz "Invalid instruction at %X\n" |
e2918b5208eb
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175
diff
changeset
|
134 |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
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diff
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|
135 .global m68k_invalid |
e2918b5208eb
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diff
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|
136 m68k_invalid: |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
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175
diff
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|
137 lea invalid_msg(%rip), %rdi |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
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175
diff
changeset
|
138 mov %ecx, %esi |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
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parents:
175
diff
changeset
|
139 xor %rax, %rax |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
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175
diff
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|
140 call printf |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
175
diff
changeset
|
141 mov $1, %rdi |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
175
diff
changeset
|
142 call exit |
194
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
143 |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
144 .global bcd_add |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
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193
diff
changeset
|
145 bcd_add: |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
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193
diff
changeset
|
146 xchg %rax, %rdi |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
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193
diff
changeset
|
147 |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
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parents:
193
diff
changeset
|
148 mov %cl, %ch |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
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parents:
193
diff
changeset
|
149 mov %al, %ah |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
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parents:
193
diff
changeset
|
150 and $0xF, %ch |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
151 and $0xF, %ah |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
152 and $0xF0, %cl |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
153 and $0xF0, %al |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
154 add %ah, %ch |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
155 cmp $10, %ch |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
156 jb no_adjust |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
157 add $6, %ch |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
158 no_adjust: |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
159 add %ch, %al |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
160 add %al, %cl |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
161 mov $0, %ch |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
162 jc def_adjust |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
163 cmp $0xA0, %cl |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
164 jb no_adjust_h |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
165 def_adjust: |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
166 add $0x60, %cl |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
167 mov $1, %ch |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
168 no_adjust_h: |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
169 |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
170 mov %rdi, %rax |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
171 ret |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
172 |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
173 .global bcd_sub |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
174 bcd_sub: |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
175 xchg %rax, %rdi |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
176 |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
177 mov %cl, %ch |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
178 mov %al, %ah |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
179 and $0xF, %ch |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
180 and $0xF, %ah |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
181 and $0xF0, %cl |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
182 and $0xF0, %al |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
183 sub %ah, %ch |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
184 cmp $10, %ch |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
185 jb no_adjusts |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
186 sub $6, %ch |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
187 no_adjusts: |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
188 add %ch, %cl |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
189 sub %al, %cl |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
190 mov $0, %ch |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
191 jc def_adjusts |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
192 cmp $0xA0, %cl |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
193 jb no_adjust_hs |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
194 def_adjusts: |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
195 sub $0x60, %cl |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
196 mov $1, %ch |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
197 no_adjust_hs: |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
198 |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
199 mov %rdi, %rax |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
200 ret |
150
3e68e517cc01
Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed.
Mike Pavone <pavone@retrodev.com>
parents:
149
diff
changeset
|
201 |
87
60b5c9e2f4e0
vertical interrupts now work
Mike Pavone <pavone@retrodev.com>
parents:
86
diff
changeset
|
202 int_dbg_msg: |
60b5c9e2f4e0
vertical interrupts now work
Mike Pavone <pavone@retrodev.com>
parents:
86
diff
changeset
|
203 .asciz "Executing Interrupt!" |
60b5c9e2f4e0
vertical interrupts now work
Mike Pavone <pavone@retrodev.com>
parents:
86
diff
changeset
|
204 print_int_dbg: |
60b5c9e2f4e0
vertical interrupts now work
Mike Pavone <pavone@retrodev.com>
parents:
86
diff
changeset
|
205 call m68k_save_context |
60b5c9e2f4e0
vertical interrupts now work
Mike Pavone <pavone@retrodev.com>
parents:
86
diff
changeset
|
206 push %rsi |
60b5c9e2f4e0
vertical interrupts now work
Mike Pavone <pavone@retrodev.com>
parents:
86
diff
changeset
|
207 lea int_dbg_msg(%rip), %rdi |
60b5c9e2f4e0
vertical interrupts now work
Mike Pavone <pavone@retrodev.com>
parents:
86
diff
changeset
|
208 call puts |
60b5c9e2f4e0
vertical interrupts now work
Mike Pavone <pavone@retrodev.com>
parents:
86
diff
changeset
|
209 pop %rsi |
60b5c9e2f4e0
vertical interrupts now work
Mike Pavone <pavone@retrodev.com>
parents:
86
diff
changeset
|
210 call m68k_load_context |
60b5c9e2f4e0
vertical interrupts now work
Mike Pavone <pavone@retrodev.com>
parents:
86
diff
changeset
|
211 ret |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
212 |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
213 .global get_sr |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
214 get_sr: |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
215 mov 5(%rsi), %cl |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
216 shl $8, %cx |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
217 mov (%rsi), %cl |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
218 shl $1, %cl |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
219 or %bl, %cl |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
220 shl $1, %cl |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
221 or %dl, %cl |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
222 shl $1, %cl |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
223 or %bh, %cl |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
224 shl $1, %cl |
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225 or %dh, %cl |
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226 ret |
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|
227 |
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|
228 .global set_sr |
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229 set_sr: |
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|
230 mov %cl, %dh |
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|
231 and $1, %dh |
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|
232 shr $1, %cl |
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233 mov %cl, %bh |
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234 and $1, %bh |
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Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
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|
235 shr $1, %cl |
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Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
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236 mov %cl, %dl |
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|
237 and $1, %dl |
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238 shr $1, %cl |
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|
239 mov %cl, %bl |
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240 and $1, %bl |
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Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
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|
241 shr $1, %cl |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
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|
242 and $1, %cl |
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Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
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|
243 mov %cl, (%rsi) |
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Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
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244 shr $8, %cx |
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|
245 mov %cl, 5(%rsi) |
321
146c87616b05
Don't update interrupt mask on non-interrupt exceptions
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246 /* call debug_print_sr */ |
82
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247 ret |
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248 |
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249 .global set_ccr |
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250 set_ccr: |
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251 mov %cl, %dh |
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Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
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252 and $1, %dh |
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Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
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253 shr $1, %cl |
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Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
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254 mov %cl, %bh |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
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255 and $1, %bh |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
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|
256 shr $1, %cl |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
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257 mov %cl, %dl |
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Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
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258 and $1, %dl |
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Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
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259 shr $1, %cl |
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Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
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260 mov %cl, %bl |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
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261 and $1, %bl |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
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262 shr $1, %cl |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
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263 and $1, %cl |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
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|
264 mov %cl, (%rsi) |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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265 ret |
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266 |
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267 do_vdp_port_write: |
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268 call m68k_save_context |
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269 mov %rcx, %rdx |
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270 call vdp_port_write |
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271 mov %rax, %rsi |
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272 call m68k_load_context |
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273 ret |
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274 |
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275 do_vdp_port_read: |
57
bc3bc7a60c4e
Code in runtime for checking for VDP reads was using the wrong register. This is now fixed.
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276 mov %ecx, %edi |
54
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277 call m68k_save_context |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
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diff
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|
278 push %rsi |
54
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279 call vdp_port_read |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
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|
280 pop %rsi |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
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|
281 mov %ax, %cx |
54
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|
282 call m68k_load_context |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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|
283 ret |
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M68K to x86 translation works for a limited subset of instructions and addressing modes
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|
284 |
66 | 285 do_io_write: |
286 call m68k_save_context | |
153
42c031184e8a
Implement access to Z80 RAM
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diff
changeset
|
287 and $0x1FFFF, %edi |
83
2c7267617d71
Implement Z80 reset and bus request registers.
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diff
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|
288 mov %ecx, %edx |
66 | 289 call io_write |
290 mov %rax, %rsi | |
291 call m68k_load_context | |
292 ret | |
293 do_io_read: | |
294 mov %ecx, %edi | |
153
42c031184e8a
Implement access to Z80 RAM
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|
295 and $0x1FFFF, %edi |
66 | 296 call m68k_save_context |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
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diff
changeset
|
297 push %rsi |
66 | 298 call io_read |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
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diff
changeset
|
299 pop %rsi |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
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diff
changeset
|
300 mov %al, %cl |
66 | 301 call m68k_load_context |
302 ret | |
83
2c7267617d71
Implement Z80 reset and bus request registers.
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diff
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|
303 |
2c7267617d71
Implement Z80 reset and bus request registers.
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|
304 do_io_write_w: |
2c7267617d71
Implement Z80 reset and bus request registers.
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changeset
|
305 call m68k_save_context |
153
42c031184e8a
Implement access to Z80 RAM
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diff
changeset
|
306 and $0x1FFFF, %edi |
83
2c7267617d71
Implement Z80 reset and bus request registers.
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parents:
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diff
changeset
|
307 mov %ecx, %edx |
2c7267617d71
Implement Z80 reset and bus request registers.
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diff
changeset
|
308 call io_write_w |
2c7267617d71
Implement Z80 reset and bus request registers.
Mike Pavone <pavone@retrodev.com>
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diff
changeset
|
309 mov %rax, %rsi |
2c7267617d71
Implement Z80 reset and bus request registers.
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changeset
|
310 call m68k_load_context |
2c7267617d71
Implement Z80 reset and bus request registers.
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diff
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|
311 ret |
2c7267617d71
Implement Z80 reset and bus request registers.
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changeset
|
312 do_io_read_w: |
2c7267617d71
Implement Z80 reset and bus request registers.
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diff
changeset
|
313 mov %ecx, %edi |
153
42c031184e8a
Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
314 and $0x1FFFF, %edi |
83
2c7267617d71
Implement Z80 reset and bus request registers.
Mike Pavone <pavone@retrodev.com>
parents:
82
diff
changeset
|
315 call m68k_save_context |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
|
316 push %rsi |
83
2c7267617d71
Implement Z80 reset and bus request registers.
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parents:
82
diff
changeset
|
317 call io_read_w |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
|
318 pop %rsi |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
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diff
changeset
|
319 mov %ax, %cx |
83
2c7267617d71
Implement Z80 reset and bus request registers.
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parents:
82
diff
changeset
|
320 call m68k_load_context |
2c7267617d71
Implement Z80 reset and bus request registers.
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diff
changeset
|
321 ret |
66 | 322 |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
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diff
changeset
|
323 bad_access_msg: |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
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diff
changeset
|
324 .asciz "Program tried to access illegal 68K address %X\n" |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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parents:
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diff
changeset
|
325 |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
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17
diff
changeset
|
326 .global m68k_write_word |
57
bc3bc7a60c4e
Code in runtime for checking for VDP reads was using the wrong register. This is now fixed.
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
327 .global try_fifo_write |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
328 m68k_write_word: |
64
2b1a65f4b85d
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
329 call inccycles |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
330 and $0xFFFFFF, %rdi |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
331 cmp $0x400000, %edi |
104
a0fdaa134964
Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
332 jbe cart_w |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
333 cmp $0xE00000, %edi |
104
a0fdaa134964
Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
334 jae workram_w |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
335 cmp $0xC00000, %edi |
104
a0fdaa134964
Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
336 jae vdp_psg_w |
153
42c031184e8a
Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
337 cmp $0xA00000, %edi |
104
a0fdaa134964
Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
338 jb not_io_w |
85
1db2a0b655d1
Fix Z80 BUSREQ/RESET implementation.
Mike Pavone <pavone@retrodev.com>
parents:
84
diff
changeset
|
339 cmp $0xA12000, %edi |
104
a0fdaa134964
Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
340 jae not_io_w |
85
1db2a0b655d1
Fix Z80 BUSREQ/RESET implementation.
Mike Pavone <pavone@retrodev.com>
parents:
84
diff
changeset
|
341 jmp do_io_write_w |
1db2a0b655d1
Fix Z80 BUSREQ/RESET implementation.
Mike Pavone <pavone@retrodev.com>
parents:
84
diff
changeset
|
342 not_io_w: |
64
2b1a65f4b85d
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
343 ret |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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|
344 workram_w: |
193
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|
345 and $0xFFFF, %edi |
18
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346 mov %cx, (%r9, %rdi) |
193
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|
347 mov %edi, %ecx |
320
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diff
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|
348 shr $11, %ecx |
193
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349 bt %ecx, 160(%rsi) |
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|
350 jnc not_code |
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|
351 call m68k_save_context |
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352 call m68k_handle_code_write |
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353 mov %rax, %rsi |
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354 call m68k_load_context |
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changeset
|
355 not_code: |
64
2b1a65f4b85d
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
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diff
changeset
|
356 ret |
18
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357 cart_w: |
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|
358 mov %cx, (%r8, %rdi) |
64
2b1a65f4b85d
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
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diff
changeset
|
359 ret |
54
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changeset
|
360 vdp_psg_w: |
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diff
changeset
|
361 test $0x2700E0, %edi |
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changeset
|
362 jnz crash |
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changeset
|
363 and $0x1F, %edi |
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changeset
|
364 cmp $4, %edi |
104
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95
diff
changeset
|
365 jb try_fifo_write |
54
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changeset
|
366 jmp do_vdp_port_write |
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367 try_fifo_write: |
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|
368 push %rdx |
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369 push %rbx |
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diff
changeset
|
370 /* fetch VDP context pointer from 68K context */ |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
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72
diff
changeset
|
371 mov 128(%rsi), %rdx |
149
139e5dcd6aa3
Make writes to control and data port block when DMA is in progress
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changeset
|
372 /* check DMA flag */ |
139e5dcd6aa3
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|
373 bt $6, 19(%rdx) |
139e5dcd6aa3
Make writes to control and data port block when DMA is in progress
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changeset
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374 jc fifo_fallback |
54
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diff
changeset
|
375 /* get fifo_cur and compare it to fifo_end */ |
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changeset
|
376 mov (%rdx), %rbx |
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changeset
|
377 cmp %rbx, 8(%rdx) |
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changeset
|
378 /* bail out if fifo is full */ |
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changeset
|
379 je fifo_fallback |
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diff
changeset
|
380 /* populate FIFO entry */ |
138 | 381 mov %cx, 6(%rbx) /* value */ |
382 mov 16(%rdx), %cx | |
383 mov %cx, 4(%rbx) /* address */ | |
384 mov 18(%rdx), %cl | |
385 mov %cl, 8(%rbx) /* cd */ | |
386 movb $0, 9(%rbx) /* partial */ | |
54
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changeset
|
387 mov %eax, %ecx |
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diff
changeset
|
388 shl $3, %ecx /* multiply by 68K cycle by 7 to get MCLK cycle */ |
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changeset
|
389 sub %eax, %ecx |
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changeset
|
390 mov %ecx, (%rbx) /* cycle */ |
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changeset
|
391 /* update fifo_cur and store back in 68K context */ |
138 | 392 add $12, %rbx |
54
3b79cbcf6846
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diff
changeset
|
393 mov %rbx, (%rdx) |
138 | 394 /* update address register */ |
395 movzbw 35(%rdx), %bx | |
396 add %bx, 16(%rdx) | |
54
3b79cbcf6846
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changeset
|
397 /* clear pending flag */ |
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changeset
|
398 andb $0xEF, 19(%rdx) |
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diff
changeset
|
399 pop %rbx |
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changeset
|
400 pop %rdx |
64
2b1a65f4b85d
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
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diff
changeset
|
401 ret |
54
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changeset
|
402 fifo_fallback: |
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changeset
|
403 pop %rbx |
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changeset
|
404 pop %rdx |
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changeset
|
405 jmp do_vdp_port_write |
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diff
changeset
|
406 crash: |
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changeset
|
407 mov %edi, %esi |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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diff
changeset
|
408 lea bad_access_msg(%rip), %rdi |
160
69ac23d42897
Fix crash in printf from "crash" function due to lack of clearing rax
Mike Pavone <pavone@retrodev.com>
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153
diff
changeset
|
409 xor %rax, %rax |
54
3b79cbcf6846
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diff
changeset
|
410 call printf |
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diff
changeset
|
411 mov $1, %rdi |
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diff
changeset
|
412 call exit |
18
3e7bfde7606e
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changeset
|
413 |
3e7bfde7606e
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changeset
|
414 .global m68k_write_byte |
3e7bfde7606e
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diff
changeset
|
415 m68k_write_byte: |
64
2b1a65f4b85d
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
416 call inccycles |
18
3e7bfde7606e
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changeset
|
417 and $0xFFFFFF, %rdi |
3e7bfde7606e
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diff
changeset
|
418 cmp $0x400000, %edi |
104
a0fdaa134964
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95
diff
changeset
|
419 jbe cart_wb |
18
3e7bfde7606e
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diff
changeset
|
420 cmp $0xE00000, %edi |
104
a0fdaa134964
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Mike Pavone <pavone@retrodev.com>
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95
diff
changeset
|
421 jae workram_wb |
66 | 422 cmp $0xC00000, %edi |
104
a0fdaa134964
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95
diff
changeset
|
423 jae vdp_psg_wb |
153
42c031184e8a
Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
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152
diff
changeset
|
424 cmp $0xA00000, %edi |
104
a0fdaa134964
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Mike Pavone <pavone@retrodev.com>
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95
diff
changeset
|
425 jb not_io_wb |
85
1db2a0b655d1
Fix Z80 BUSREQ/RESET implementation.
Mike Pavone <pavone@retrodev.com>
parents:
84
diff
changeset
|
426 cmp $0xA12000, %edi |
104
a0fdaa134964
Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp
Mike Pavone <pavone@retrodev.com>
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95
diff
changeset
|
427 jae not_io_wb |
66 | 428 jmp do_io_write |
429 not_io_wb: | |
64
2b1a65f4b85d
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
430 ret |
18
3e7bfde7606e
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17
diff
changeset
|
431 workram_wb: |
83
2c7267617d71
Implement Z80 reset and bus request registers.
Mike Pavone <pavone@retrodev.com>
parents:
82
diff
changeset
|
432 /* deal with byte swapping */ |
2c7267617d71
Implement Z80 reset and bus request registers.
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parents:
82
diff
changeset
|
433 xor $1, %edi |
18
3e7bfde7606e
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17
diff
changeset
|
434 and $0xFFFF, %rdi |
3e7bfde7606e
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17
diff
changeset
|
435 mov %cl, (%r9, %rdi) |
193
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176
diff
changeset
|
436 mov %edi, %ecx |
320
67b6d351df0e
Fix check for code writes
Mike Pavone <pavone@retrodev.com>
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317
diff
changeset
|
437 shr $11, %ecx |
193
c66e4636f991
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176
diff
changeset
|
438 bt %ecx, 160(%rsi) |
c66e4636f991
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diff
changeset
|
439 jnc not_code_b |
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176
diff
changeset
|
440 xor $1, %edi |
c66e4636f991
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changeset
|
441 call m68k_save_context |
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changeset
|
442 call m68k_handle_code_write |
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diff
changeset
|
443 mov %rax, %rsi |
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changeset
|
444 call m68k_load_context |
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diff
changeset
|
445 not_code_b: |
64
2b1a65f4b85d
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
446 ret |
18
3e7bfde7606e
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17
diff
changeset
|
447 cart_wb: |
83
2c7267617d71
Implement Z80 reset and bus request registers.
Mike Pavone <pavone@retrodev.com>
parents:
82
diff
changeset
|
448 /* deal with byte swapping */ |
2c7267617d71
Implement Z80 reset and bus request registers.
Mike Pavone <pavone@retrodev.com>
parents:
82
diff
changeset
|
449 xor $1, %edi |
18
3e7bfde7606e
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parents:
17
diff
changeset
|
450 mov %cl, (%r8, %rdi) |
64
2b1a65f4b85d
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
451 ret |
66 | 452 vdp_psg_wb: |
453 push %rdx | |
454 mov %cl, %dl | |
455 and $0xFF, %cx | |
456 shl $8, %dx | |
457 or %dx, %cx | |
458 pop %rdx | |
459 jmp vdp_psg_w | |
18
3e7bfde7606e
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17
diff
changeset
|
460 |
3e7bfde7606e
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diff
changeset
|
461 .global m68k_write_long_lowfirst |
3e7bfde7606e
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changeset
|
462 m68k_write_long_lowfirst: |
3e7bfde7606e
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17
diff
changeset
|
463 push %rdi |
86
3d3966c254b2
RTE doesn't crash the emulator anymore
Mike Pavone <pavone@retrodev.com>
parents:
85
diff
changeset
|
464 push %rcx |
18
3e7bfde7606e
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17
diff
changeset
|
465 add $2, %edi |
3e7bfde7606e
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17
diff
changeset
|
466 call m68k_write_word |
86
3d3966c254b2
RTE doesn't crash the emulator anymore
Mike Pavone <pavone@retrodev.com>
parents:
85
diff
changeset
|
467 pop %rcx |
3d3966c254b2
RTE doesn't crash the emulator anymore
Mike Pavone <pavone@retrodev.com>
parents:
85
diff
changeset
|
468 pop %rdi |
18
3e7bfde7606e
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17
diff
changeset
|
469 shr $16, %ecx |
3e7bfde7606e
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parents:
17
diff
changeset
|
470 jmp m68k_write_word |
3e7bfde7606e
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parents:
17
diff
changeset
|
471 |
3e7bfde7606e
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17
diff
changeset
|
472 .global m68k_write_long_highfirst |
3e7bfde7606e
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parents:
17
diff
changeset
|
473 m68k_write_long_highfirst: |
3e7bfde7606e
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parents:
17
diff
changeset
|
474 push %rdi |
3e7bfde7606e
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parents:
17
diff
changeset
|
475 push %rcx |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
476 shr $16, %ecx |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
477 call m68k_write_word |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
478 pop %rcx |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
479 pop %rdi |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
480 add $2, %rdi |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
481 jmp m68k_write_word |
64
2b1a65f4b85d
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
482 |
2b1a65f4b85d
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
483 inccycles: |
251
4a7ac10ac2d9
Fix target cycle count after 68K interrupt
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
484 cmp %ebp, %eax |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
485 jnb do_limit |
251
4a7ac10ac2d9
Fix target cycle count after 68K interrupt
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
486 add $4, %eax |
64
2b1a65f4b85d
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
487 ret |
344
b46771135442
Handle busack across frame boundary
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
488 do_limit: |
64
2b1a65f4b85d
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
489 call handle_cycle_limit |
251
4a7ac10ac2d9
Fix target cycle count after 68K interrupt
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
490 add $4, %eax |
64
2b1a65f4b85d
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
491 ret |
17
de0085d4ea40
Add asssembly runtime code stub
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
492 |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
493 .global m68k_read_word_scratch1 |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
494 m68k_read_word_scratch1: |
64
2b1a65f4b85d
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
495 call inccycles |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
496 and $0xFFFFFF, %rcx |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
497 cmp $0x400000, %ecx |
104
a0fdaa134964
Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
498 jbe cart |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
499 cmp $0xE00000, %ecx |
104
a0fdaa134964
Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
500 jae workram |
57
bc3bc7a60c4e
Code in runtime for checking for VDP reads was using the wrong register. This is now fixed.
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
501 cmp $0xC00000, %ecx |
104
a0fdaa134964
Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
502 jae vdp_psg |
153
42c031184e8a
Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
503 cmp $0xA00000, %ecx |
104
a0fdaa134964
Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
504 jb not_io |
85
1db2a0b655d1
Fix Z80 BUSREQ/RESET implementation.
Mike Pavone <pavone@retrodev.com>
parents:
84
diff
changeset
|
505 cmp $0xA12000, %ecx |
104
a0fdaa134964
Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
506 jae not_io |
83
2c7267617d71
Implement Z80 reset and bus request registers.
Mike Pavone <pavone@retrodev.com>
parents:
82
diff
changeset
|
507 call do_io_read_w |
72
7935cd64d5c8
Implement word wide access to IO area
Mike Pavone <pavone@retrodev.com>
parents:
66
diff
changeset
|
508 ret |
7935cd64d5c8
Implement word wide access to IO area
Mike Pavone <pavone@retrodev.com>
parents:
66
diff
changeset
|
509 not_io: |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
510 xor %cx, %cx |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
511 dec %cx |
64
2b1a65f4b85d
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
512 ret |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
513 workram: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
514 and $0xFFFF, %rcx |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
515 mov (%r9, %rcx), %cx |
64
2b1a65f4b85d
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
516 ret |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
517 vdp_psg: |
57
bc3bc7a60c4e
Code in runtime for checking for VDP reads was using the wrong register. This is now fixed.
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
518 test $0x2700E0, %ecx |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
519 jnz crash |
57
bc3bc7a60c4e
Code in runtime for checking for VDP reads was using the wrong register. This is now fixed.
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
520 and $0x1F, %ecx |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
521 jmp do_vdp_port_read |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
522 cart: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
523 mov (%r8, %rcx), %cx |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
524 ret |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
525 |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
526 .global m68k_read_long_scratch1 |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
527 m68k_read_long_scratch1: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
528 push %rcx |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
529 call m68k_read_word_scratch1 |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
530 mov %cx, %di |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
531 pop %rcx |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
532 add $2, %ecx |
84
2d1ae596db7a
Fix long reads from IO ports or long reads that trigger sync cycles by saving rdi. Possibly fix word wide IO reads.
Mike Pavone <pavone@retrodev.com>
parents:
83
diff
changeset
|
533 push %rdi |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
534 call m68k_read_word_scratch1 |
84
2d1ae596db7a
Fix long reads from IO ports or long reads that trigger sync cycles by saving rdi. Possibly fix word wide IO reads.
Mike Pavone <pavone@retrodev.com>
parents:
83
diff
changeset
|
535 pop %rdi |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
536 and $0xFFFF, %ecx |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
537 shl $16, %edi |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
538 or %edi, %ecx |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
539 ret |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
540 |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
541 .global m68k_read_byte_scratch1 |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
542 m68k_read_byte_scratch1: |
64
2b1a65f4b85d
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
543 call inccycles |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
544 and $0xFFFFFF, %rcx |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
545 cmp $0x400000, %ecx |
104
a0fdaa134964
Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
546 jbe cart_b |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
547 cmp $0xE00000, %ecx |
104
a0fdaa134964
Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
548 jae workram_b |
137 | 549 cmp $0xC00000, %ecx |
550 jae vdp_psg_b | |
153
42c031184e8a
Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
551 cmp $0xA00000, %ecx |
104
a0fdaa134964
Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
552 jb not_io_b |
85
1db2a0b655d1
Fix Z80 BUSREQ/RESET implementation.
Mike Pavone <pavone@retrodev.com>
parents:
84
diff
changeset
|
553 cmp $0xA12000, %ecx |
104
a0fdaa134964
Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
554 jae not_io_b |
66 | 555 jmp do_io_read |
556 not_io_b: | |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
557 xor %cl, %cl |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
558 dec %cl |
64
2b1a65f4b85d
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
559 ret |
137 | 560 vdp_psg_b: |
561 test $0x2700E0, %ecx | |
562 jnz crash | |
563 and $0x1F, %ecx | |
564 bt $0, %ecx | |
565 jnc vdp_swap | |
566 jmp do_vdp_port_read | |
567 vdp_swap: | |
568 call do_vdp_port_read | |
569 shr $8, %cx | |
570 ret | |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
571 workram_b: |
83
2c7267617d71
Implement Z80 reset and bus request registers.
Mike Pavone <pavone@retrodev.com>
parents:
82
diff
changeset
|
572 /* deal with byte swapping */ |
2c7267617d71
Implement Z80 reset and bus request registers.
Mike Pavone <pavone@retrodev.com>
parents:
82
diff
changeset
|
573 xor $1, %ecx |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
574 and $0xFFFF, %rcx |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
575 mov (%r9, %rcx), %cl |
64
2b1a65f4b85d
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
576 ret |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
577 cart_b: |
83
2c7267617d71
Implement Z80 reset and bus request registers.
Mike Pavone <pavone@retrodev.com>
parents:
82
diff
changeset
|
578 /* deal with byte swapping */ |
2c7267617d71
Implement Z80 reset and bus request registers.
Mike Pavone <pavone@retrodev.com>
parents:
82
diff
changeset
|
579 xor $1, %ecx |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
580 mov (%r8, %rcx), %cl |
64
2b1a65f4b85d
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
581 ret |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
582 |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
583 .global m68k_modified_ret_addr |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
584 m68k_modified_ret_addr: |
145
15b8dce19cf4
Implement m68k_modified_ret_addr
Mike Pavone <pavone@retrodev.com>
parents:
138
diff
changeset
|
585 add $16, %rsp |
15b8dce19cf4
Implement m68k_modified_ret_addr
Mike Pavone <pavone@retrodev.com>
parents:
138
diff
changeset
|
586 call m68k_native_addr |
15b8dce19cf4
Implement m68k_modified_ret_addr
Mike Pavone <pavone@retrodev.com>
parents:
138
diff
changeset
|
587 jmp *%rcx |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
588 |
53
44e661913a51
Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents:
18
diff
changeset
|
589 dyn_addr_msg: |
44e661913a51
Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents:
18
diff
changeset
|
590 .asciz "Program needs dynamically calculated native address\n" |
44e661913a51
Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents:
18
diff
changeset
|
591 |
86
3d3966c254b2
RTE doesn't crash the emulator anymore
Mike Pavone <pavone@retrodev.com>
parents:
85
diff
changeset
|
592 .global m68k_native_addr_and_sync |
3d3966c254b2
RTE doesn't crash the emulator anymore
Mike Pavone <pavone@retrodev.com>
parents:
85
diff
changeset
|
593 m68k_native_addr_and_sync: |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
594 call m68k_save_context |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
595 push %rcx |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
596 mov %rsi, %rdi |
198
209a37eed3e7
Add support for breaking into the debugger while game is running
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
597 xor %esi, %esi |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
598 call sync_components |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
599 pop %rsi |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
600 push %rax |
95
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
601 mov %rax, %rdi |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
602 call get_native_address_trans |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
603 mov %rax, %rcx |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
604 pop %rsi |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
605 call m68k_load_context |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
606 ret |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
607 |
86
3d3966c254b2
RTE doesn't crash the emulator anymore
Mike Pavone <pavone@retrodev.com>
parents:
85
diff
changeset
|
608 .global m68k_native_addr |
3d3966c254b2
RTE doesn't crash the emulator anymore
Mike Pavone <pavone@retrodev.com>
parents:
85
diff
changeset
|
609 m68k_native_addr: |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
610 call m68k_save_context |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
611 push %rsi |
95
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
612 mov %rsi, %rdi |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
613 mov %ecx, %esi |
95
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
614 call get_native_address_trans |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
615 mov %rax, %rcx |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
616 pop %rsi |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
617 call m68k_load_context |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
618 ret |
193
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
176
diff
changeset
|
619 |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
176
diff
changeset
|
620 .global m68k_retrans_stub |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
176
diff
changeset
|
621 m68k_retrans_stub: |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
176
diff
changeset
|
622 call m68k_save_context |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
176
diff
changeset
|
623 push %rsi |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
176
diff
changeset
|
624 call m68k_retranslate_inst |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
176
diff
changeset
|
625 pop %rsi |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
176
diff
changeset
|
626 mov %rax, %rcx |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
176
diff
changeset
|
627 call m68k_load_context |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
176
diff
changeset
|
628 jmp *%rcx |
53
44e661913a51
Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents:
18
diff
changeset
|
629 |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
630 .global m68k_save_context |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
631 m68k_save_context: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
632 mov %bl, 1(%rsi) /* N Flag */ |
207 | 633 mov %dl, 2(%rsi) /* Z flag */ |
634 mov %bh, 3(%rsi) /* V flag */ | |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
635 mov %dh, 4(%rsi) /* C flag */ |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
636 mov %r10d, 8(%rsi) /* d0 */ |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
637 mov %r11d, 12(%rsi) /* d1 */ |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
638 mov %r12d, 16(%rsi) /* d2 */ |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
639 mov %r13d, 40(%rsi) /* a0 */ |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
640 mov %r14d, 44(%rsi) /* a1 */ |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
641 mov %r15d, 68(%rsi) /* a7 */ |
72
7935cd64d5c8
Implement word wide access to IO area
Mike Pavone <pavone@retrodev.com>
parents:
66
diff
changeset
|
642 mov %eax, 80(%rsi) /* current cycle count */ |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
643 ret |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
644 |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
645 .global m68k_load_context |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
646 m68k_load_context: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
647 mov 1(%rsi), %bl /* N Flag */ |
207 | 648 mov 2(%rsi), %dl /* Z flag */ |
649 mov 3(%rsi), %bh /* V flag */ | |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
650 mov 4(%rsi), %dh /* C flag */ |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
651 mov 8(%rsi), %r10d /* d0 */ |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
652 mov 12(%rsi), %r11d /* d1 */ |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
653 mov 16(%rsi), %r12d /* d2 */ |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
654 mov 40(%rsi), %r13d /* a0 */ |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
655 mov 44(%rsi), %r14d /* a1 */ |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
656 mov 68(%rsi), %r15d /* a7 */ |
72
7935cd64d5c8
Implement word wide access to IO area
Mike Pavone <pavone@retrodev.com>
parents:
66
diff
changeset
|
657 mov 76(%rsi), %ebp /* target cycle count */ |
7935cd64d5c8
Implement word wide access to IO area
Mike Pavone <pavone@retrodev.com>
parents:
66
diff
changeset
|
658 mov 80(%rsi), %eax /* current cycle count */ |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
659 mov 96(%rsi), %r8d /* cartridge address */ |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
660 mov 104(%rsi), %r9d /* work ram address */ |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
661 ret |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
662 |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
663 .global m68k_start_context |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
664 m68k_start_context: |
208
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
207
diff
changeset
|
665 push %rbp |
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
207
diff
changeset
|
666 push %r12 |
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
207
diff
changeset
|
667 push %r13 |
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
207
diff
changeset
|
668 push %r14 |
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
207
diff
changeset
|
669 push %r15 |
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
207
diff
changeset
|
670 |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
671 call m68k_load_context |
208
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
207
diff
changeset
|
672 call *%rdi |
209
922b59c09259
Flag fixes for div, negx and not
Mike Pavone <pavone@retrodev.com>
parents:
208
diff
changeset
|
673 call m68k_save_context |
208
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
207
diff
changeset
|
674 |
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
207
diff
changeset
|
675 pop %r15 |
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
207
diff
changeset
|
676 pop %r14 |
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
207
diff
changeset
|
677 pop %r13 |
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
207
diff
changeset
|
678 pop %r12 |
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
207
diff
changeset
|
679 pop %rbp |
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
207
diff
changeset
|
680 |
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
207
diff
changeset
|
681 ret |