Mercurial > repos > blastem
annotate 68kinst.c @ 31:25016576b5f3
Make horizontal scrolling closer to correct, Comix Zone looks good, Sonic 2 slightly off
author | Mike Pavone <pavone@retrodev.com> |
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date | Sat, 08 Dec 2012 20:25:56 -0800 |
parents | 3e7bfde7606e |
children | f2aaaf36c875 |
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1 #include "68kinst.h" |
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2 #include <string.h> |
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3 #include <stdio.h> |
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4 |
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5 uint32_t sign_extend16(uint32_t val) |
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6 { |
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7 return (val & 0x8000) ? val | 0xFFFF0000 : val; |
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8 } |
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9 |
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10 uint32_t sign_extend8(uint32_t val) |
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11 { |
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12 return (val & 0x80) ? val | 0xFFFFFF00 : val; |
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13 } |
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14 |
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15 uint16_t *m68k_decode_op_ex(uint16_t *cur, uint8_t mode, uint8_t reg, uint8_t size, m68k_op_info *dst) |
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16 { |
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17 uint16_t ext; |
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18 dst->addr_mode = mode; |
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19 switch(mode) |
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20 { |
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21 case MODE_REG: |
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22 case MODE_AREG: |
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23 case MODE_AREG_INDIRECT: |
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24 case MODE_AREG_POSTINC: |
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25 case MODE_AREG_PREDEC: |
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26 dst->params.regs.pri = reg; |
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27 break; |
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28 case MODE_AREG_DISPLACE: |
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29 ext = *(++cur); |
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30 dst->params.regs.pri = reg; |
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31 dst->params.regs.displacement = sign_extend16(ext); |
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32 break; |
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33 case MODE_AREG_INDEX_MEM: |
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34 //TODO: implement me |
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35 break; |
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36 case MODE_PC_INDIRECT_ABS_IMMED: |
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37 switch(reg) |
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38 { |
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39 case 0: |
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40 dst->addr_mode = MODE_ABSOLUTE_SHORT; |
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41 ext = *(++cur); |
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42 dst->params.immed = sign_extend16(ext); |
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43 break; |
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44 case 1: |
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45 dst->addr_mode = MODE_ABSOLUTE; |
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46 ext = *(++cur); |
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47 dst->params.immed = ext << 16 | *(++cur); |
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48 break; |
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49 case 2: |
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50 dst->addr_mode = MODE_PC_DISPLACE; |
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51 ext = *(++cur); |
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52 dst->params.regs.displacement = sign_extend16(ext); |
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53 break; |
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54 case 4: |
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55 dst->addr_mode = MODE_IMMEDIATE; |
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56 ext = *(++cur); |
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57 switch (size) |
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58 { |
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59 case OPSIZE_BYTE: |
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60 dst->params.immed = ext & 0xFF; |
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61 break; |
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62 case OPSIZE_WORD: |
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63 dst->params.immed = ext; |
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64 break; |
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65 case OPSIZE_LONG: |
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66 dst->params.immed = ext << 16 | *(++cur); |
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67 break; |
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68 } |
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69 break; |
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70 //TODO: implement the rest of these |
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71 } |
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72 break; |
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73 } |
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74 return cur; |
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75 } |
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76 |
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77 uint16_t *m68k_decode_op(uint16_t *cur, uint8_t size, m68k_op_info *dst) |
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78 { |
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79 uint8_t mode = (*cur >> 3) & 0x7; |
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80 uint8_t reg = *cur & 0x7; |
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81 return m68k_decode_op_ex(cur, mode, reg, size, dst); |
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82 } |
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83 |
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84 void m68k_decode_cond(uint16_t op, m68kinst * decoded) |
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85 { |
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86 decoded->extra.cond = (op >> 0x8) & 0xF; |
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87 } |
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88 |
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89 uint8_t m68k_reg_quick_field(uint16_t op) |
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90 { |
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91 return (op >> 9) & 0x7; |
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92 } |
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93 |
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94 uint16_t * m68k_decode(uint16_t * istream, m68kinst * decoded, uint32_t address) |
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95 { |
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96 uint8_t optype = *istream >> 12; |
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97 uint8_t size; |
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98 uint8_t reg; |
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99 uint8_t opmode; |
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100 uint32_t immed; |
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101 decoded->op = M68K_INVALID; |
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102 decoded->src.addr_mode = decoded->dst.addr_mode = MODE_UNUSED; |
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103 decoded->variant = VAR_NORMAL; |
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104 decoded->address = address; |
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105 switch(optype) |
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106 { |
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107 case BIT_MOVEP_IMMED: |
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108 if (*istream & 0x100) { |
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109 //BTST, BCHG, BCLR, BSET |
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110 switch ((*istream >> 6) & 0x3) |
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111 { |
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112 case 0: |
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113 decoded->op = M68K_BTST; |
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114 break; |
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115 case 1: |
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116 decoded->op = M68K_BCHG; |
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117 break; |
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118 case 2: |
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119 decoded->op = M68K_BCLR; |
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120 break; |
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121 case 3: |
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122 decoded->op = M68K_BSET; |
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123 break; |
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124 } |
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125 decoded->src.addr_mode = MODE_REG; |
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126 decoded->src.params.regs.pri = m68k_reg_quick_field(*istream); |
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127 decoded->extra.size = OPSIZE_LONG; |
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128 istream = m68k_decode_op(istream, OPSIZE_LONG, &(decoded->dst)); |
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129 } else if ((*istream & 0xF00) == 0x800) { |
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130 //BTST, BCHG, BCLR, BSET |
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131 switch ((*istream >> 6) & 0x3) |
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132 { |
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133 case 0: |
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134 decoded->op = M68K_BTST; |
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135 break; |
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136 case 1: |
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137 decoded->op = M68K_BCHG; |
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138 break; |
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139 case 2: |
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140 decoded->op = M68K_BCLR; |
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141 break; |
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142 case 3: |
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143 decoded->op = M68K_BSET; |
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144 break; |
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145 } |
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146 opmode = (*istream >> 3) & 0x7; |
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147 reg = *istream & 0x7; |
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148 decoded->src.addr_mode = MODE_IMMEDIATE; |
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149 decoded->src.params.immed = *(++istream) & 0xFF; |
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150 decoded->extra.size = OPSIZE_BYTE; |
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151 istream = m68k_decode_op_ex(istream, opmode, reg, OPSIZE_BYTE, &(decoded->dst)); |
8
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152 } else if ((*istream & 0xC0) == 0xC0) { |
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153 #ifdef M68020 |
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154 //CMP2, CHK2, CAS, CAS2, RTM, CALLM |
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155 #endif |
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156 } else { |
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157 switch ((*istream >> 9) & 0x7) |
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158 { |
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159 case 0: |
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160 if ((*istream & 0xFF) == 0x3C) { |
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161 decoded->op = M68K_ORI_CCR; |
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162 decoded->extra.size = OPSIZE_BYTE; |
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163 decoded->src.addr_mode = MODE_IMMEDIATE; |
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164 decoded->src.params.immed = *(++istream) & 0xFF; |
4
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165 } else if((*istream & 0xFF) == 0x7C) { |
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166 decoded->op = M68K_ORI_SR; |
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167 decoded->extra.size = OPSIZE_WORD; |
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168 decoded->src.addr_mode = MODE_IMMEDIATE; |
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169 decoded->src.params.immed = *(++istream); |
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170 } else { |
8
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171 decoded->op = M68K_OR; |
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172 decoded->variant = VAR_IMMEDIATE; |
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173 decoded->src.addr_mode = MODE_IMMEDIATE; |
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174 decoded->extra.size = size = (*istream >> 6) & 3; |
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175 reg = *istream & 0x7; |
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176 opmode = (*istream >> 3) & 0x7; |
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177 switch (size) |
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178 { |
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179 case OPSIZE_BYTE: |
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180 decoded->src.params.immed = *(++istream) & 0xFF; |
8
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181 break; |
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182 case OPSIZE_WORD: |
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183 decoded->src.params.immed = *(++istream); |
8
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184 break; |
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185 case OPSIZE_LONG: |
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186 immed = *(++istream); |
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187 decoded->src.params.immed = immed << 16 | *(++istream); |
8
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188 break; |
4
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189 } |
8
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190 istream = m68k_decode_op_ex(istream, opmode, reg, size, &(decoded->dst)); |
4
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191 } |
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192 break; |
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193 case 1: |
8
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194 //ANDI, ANDI to CCR, ANDI to SR |
5
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195 if ((*istream & 0xFF) == 0x3C) { |
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196 decoded->op = M68K_ANDI_CCR; |
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197 decoded->extra.size = OPSIZE_BYTE; |
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198 decoded->src.addr_mode = MODE_IMMEDIATE; |
15
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199 decoded->src.params.immed = *(++istream) & 0xFF; |
5
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200 } else if((*istream & 0xFF) == 0x7C) { |
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201 decoded->op = M68K_ANDI_SR; |
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202 decoded->extra.size = OPSIZE_WORD; |
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203 decoded->src.addr_mode = MODE_IMMEDIATE; |
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204 decoded->src.params.immed = *(++istream); |
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205 } else { |
8
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206 decoded->op = M68K_AND; |
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207 decoded->variant = VAR_IMMEDIATE; |
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208 decoded->src.addr_mode = MODE_IMMEDIATE; |
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209 decoded->extra.size = size = (*istream >> 6) & 3; |
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210 reg = *istream & 0x7; |
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211 opmode = (*istream >> 3) & 0x7; |
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212 switch (size) |
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213 { |
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214 case OPSIZE_BYTE: |
15
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215 decoded->src.params.immed = *(++istream) & 0xFF; |
5
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216 break; |
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217 case OPSIZE_WORD: |
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218 decoded->src.params.immed = *(++istream); |
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219 break; |
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220 case OPSIZE_LONG: |
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221 immed = *(++istream); |
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222 decoded->src.params.immed = immed << 16 | *(++istream); |
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223 break; |
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224 } |
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225 istream = m68k_decode_op_ex(istream, opmode, reg, size, &(decoded->dst)); |
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226 } |
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227 break; |
8
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228 case 2: |
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229 decoded->op = M68K_SUB; |
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230 decoded->variant = VAR_IMMEDIATE; |
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|
231 decoded->src.addr_mode = MODE_IMMEDIATE; |
23b83d94c633
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|
232 decoded->extra.size = size = (*istream >> 6) & 3; |
23b83d94c633
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233 reg = *istream & 0x7; |
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|
234 opmode = (*istream >> 3) & 0x7; |
23b83d94c633
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|
235 switch (size) |
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5
diff
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|
236 { |
23b83d94c633
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5
diff
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|
237 case OPSIZE_BYTE: |
15
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13
diff
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|
238 decoded->src.params.immed = *(++istream) & 0xFF; |
8
23b83d94c633
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5
diff
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|
239 break; |
23b83d94c633
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5
diff
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|
240 case OPSIZE_WORD: |
15
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13
diff
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|
241 decoded->src.params.immed = *(++istream); |
8
23b83d94c633
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|
242 break; |
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|
243 case OPSIZE_LONG: |
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|
244 immed = *(++istream); |
15
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13
diff
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|
245 decoded->src.params.immed = immed << 16 | *(++istream); |
8
23b83d94c633
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|
246 break; |
23b83d94c633
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|
247 } |
23b83d94c633
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Mike Pavone <pavone@retrodev.com>
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|
248 istream = m68k_decode_op_ex(istream, opmode, reg, size, &(decoded->dst)); |
23b83d94c633
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|
249 break; |
4
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|
250 case 3: |
8
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|
251 decoded->op = M68K_ADD; |
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|
252 decoded->variant = VAR_IMMEDIATE; |
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|
253 decoded->src.addr_mode = MODE_IMMEDIATE; |
23b83d94c633
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|
254 decoded->extra.size = size = (*istream >> 6) & 3; |
23b83d94c633
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diff
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|
255 reg = *istream & 0x7; |
23b83d94c633
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|
256 opmode = (*istream >> 3) & 0x7; |
23b83d94c633
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|
257 switch (size) |
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diff
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|
258 { |
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Mike Pavone <pavone@retrodev.com>
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|
259 case OPSIZE_BYTE: |
15
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|
260 decoded->src.params.immed = *(++istream) & 0xFF; |
8
23b83d94c633
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5
diff
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|
261 break; |
23b83d94c633
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diff
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|
262 case OPSIZE_WORD: |
15
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13
diff
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|
263 decoded->src.params.immed = *(++istream); |
8
23b83d94c633
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5
diff
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|
264 break; |
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|
265 case OPSIZE_LONG: |
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|
266 immed = *(++istream); |
15
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13
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|
267 decoded->src.params.immed = immed << 16 | *(++istream); |
8
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|
268 break; |
5
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|
269 } |
8
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diff
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|
270 istream = m68k_decode_op_ex(istream, opmode, reg, size, &(decoded->dst)); |
4
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
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3
diff
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|
271 break; |
6f6a2d7cc889
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|
272 case 4: |
5
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|
273 //BTST, BCHG, BCLR, BSET |
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|
274 switch ((*istream >> 6) & 0x3) |
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|
275 { |
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|
276 case 0: |
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277 decoded->op = M68K_BTST; |
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|
278 break; |
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|
279 case 1: |
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280 decoded->op = M68K_BCHG; |
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|
281 break; |
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|
282 case 2: |
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|
283 decoded->op = M68K_BCLR; |
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|
284 break; |
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|
285 case 3: |
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|
286 decoded->op = M68K_BSET; |
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|
287 break; |
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diff
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|
288 } |
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|
289 decoded->src.addr_mode = MODE_IMMEDIATE; |
15
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13
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|
290 decoded->src.params.immed = *(++istream) & 0xFF; |
5
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diff
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|
291 istream = m68k_decode_op(istream, OPSIZE_BYTE, &(decoded->dst)); |
4
6f6a2d7cc889
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3
diff
changeset
|
292 break; |
6f6a2d7cc889
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diff
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|
293 case 5: |
5
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diff
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|
294 //EORI, EORI to CCR, EORI to SR |
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|
295 if ((*istream & 0xFF) == 0x3C) { |
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|
296 decoded->op = M68K_EORI_CCR; |
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diff
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|
297 decoded->extra.size = OPSIZE_BYTE; |
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changeset
|
298 decoded->src.addr_mode = MODE_IMMEDIATE; |
15
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13
diff
changeset
|
299 decoded->src.params.immed = *(++istream) & 0xFF; |
5
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|
300 } else if((*istream & 0xFF) == 0x7C) { |
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|
301 decoded->op = M68K_EORI_SR; |
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diff
changeset
|
302 decoded->extra.size = OPSIZE_WORD; |
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4
diff
changeset
|
303 decoded->src.addr_mode = MODE_IMMEDIATE; |
15
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13
diff
changeset
|
304 decoded->src.params.immed = *(++istream); |
5
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diff
changeset
|
305 } else { |
8
23b83d94c633
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diff
changeset
|
306 decoded->op = M68K_EOR; |
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diff
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|
307 decoded->variant = VAR_IMMEDIATE; |
23b83d94c633
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5
diff
changeset
|
308 decoded->src.addr_mode = MODE_IMMEDIATE; |
23b83d94c633
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diff
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|
309 decoded->extra.size = size = (*istream >> 6) & 3; |
23b83d94c633
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diff
changeset
|
310 reg = *istream & 0x7; |
23b83d94c633
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diff
changeset
|
311 opmode = (*istream >> 3) & 0x7; |
23b83d94c633
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diff
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|
312 switch (size) |
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5
diff
changeset
|
313 { |
23b83d94c633
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Mike Pavone <pavone@retrodev.com>
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5
diff
changeset
|
314 case OPSIZE_BYTE: |
15
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13
diff
changeset
|
315 decoded->src.params.immed = *(++istream) & 0xFF; |
8
23b83d94c633
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5
diff
changeset
|
316 break; |
23b83d94c633
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5
diff
changeset
|
317 case OPSIZE_WORD: |
15
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13
diff
changeset
|
318 decoded->src.params.immed = *(++istream); |
8
23b83d94c633
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5
diff
changeset
|
319 break; |
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5
diff
changeset
|
320 case OPSIZE_LONG: |
23b83d94c633
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5
diff
changeset
|
321 immed = *(++istream); |
15
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parents:
13
diff
changeset
|
322 decoded->src.params.immed = immed << 16 | *(++istream); |
8
23b83d94c633
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parents:
5
diff
changeset
|
323 break; |
5
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4
diff
changeset
|
324 } |
8
23b83d94c633
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Mike Pavone <pavone@retrodev.com>
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5
diff
changeset
|
325 istream = m68k_decode_op_ex(istream, opmode, reg, size, &(decoded->dst)); |
5
85699517043f
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4
diff
changeset
|
326 } |
4
6f6a2d7cc889
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Mike Pavone <pavone@retrodev.com>
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3
diff
changeset
|
327 break; |
6f6a2d7cc889
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3
diff
changeset
|
328 case 6: |
8
23b83d94c633
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5
diff
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|
329 decoded->op = M68K_CMP; |
23b83d94c633
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5
diff
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|
330 decoded->variant = VAR_IMMEDIATE; |
23b83d94c633
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Mike Pavone <pavone@retrodev.com>
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5
diff
changeset
|
331 decoded->extra.size = (*istream >> 6) & 0x3; |
23b83d94c633
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Mike Pavone <pavone@retrodev.com>
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5
diff
changeset
|
332 decoded->src.addr_mode = MODE_IMMEDIATE; |
23b83d94c633
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Mike Pavone <pavone@retrodev.com>
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5
diff
changeset
|
333 reg = *istream & 0x7; |
23b83d94c633
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Mike Pavone <pavone@retrodev.com>
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5
diff
changeset
|
334 opmode = (*istream >> 3) & 0x7; |
23b83d94c633
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Mike Pavone <pavone@retrodev.com>
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5
diff
changeset
|
335 switch (decoded->extra.size) |
23b83d94c633
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Mike Pavone <pavone@retrodev.com>
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5
diff
changeset
|
336 { |
23b83d94c633
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Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
337 case OPSIZE_BYTE: |
15
c0f339564819
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Mike Pavone <pavone@retrodev.com>
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13
diff
changeset
|
338 decoded->src.params.immed = *(++istream) & 0xFF; |
8
23b83d94c633
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5
diff
changeset
|
339 break; |
23b83d94c633
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Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
340 case OPSIZE_WORD: |
15
c0f339564819
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Mike Pavone <pavone@retrodev.com>
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13
diff
changeset
|
341 decoded->src.params.immed = *(++istream); |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
342 break; |
23b83d94c633
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Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
343 case OPSIZE_LONG: |
23b83d94c633
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Mike Pavone <pavone@retrodev.com>
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5
diff
changeset
|
344 immed = *(++istream); |
15
c0f339564819
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Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
345 decoded->src.params.immed = (immed << 16) | *(++istream); |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
346 break; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
347 } |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
348 istream = m68k_decode_op_ex(istream, opmode, reg, size, &(decoded->dst)); |
4
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
349 break; |
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
350 case 7: |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
351 //MOVEP |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
352 decoded->op = M68K_MOVEP; |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
353 decoded->extra.size = *istream & 0x40 ? OPSIZE_LONG : OPSIZE_WORD; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
354 if (*istream & 0x80) { |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
355 //memory dest |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
356 decoded->src.addr_mode = MODE_REG; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
357 decoded->src.params.regs.pri = m68k_reg_quick_field(*istream); |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
358 decoded->dst.addr_mode = MODE_AREG_DISPLACE; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
359 decoded->dst.params.regs.pri = *istream & 0x7; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
360 } else { |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
361 //memory source |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
362 decoded->dst.addr_mode = MODE_REG; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
363 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream); |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
364 decoded->src.addr_mode = MODE_AREG_DISPLACE; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
365 decoded->src.params.regs.pri = *istream & 0x7; |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
366 } |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
367 immed = *(++istream); |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
368 |
4
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
369 break; |
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
370 } |
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
371 } |
0
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
372 break; |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
373 case MOVE_BYTE: |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
374 case MOVE_LONG: |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
375 case MOVE_WORD: |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
376 decoded->op = M68K_MOVE; |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
377 decoded->extra.size = optype == MOVE_BYTE ? OPSIZE_BYTE : (optype == MOVE_WORD ? OPSIZE_WORD : OPSIZE_LONG); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
378 opmode = (*istream >> 6) & 0x7; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
379 reg = m68k_reg_quick_field(*istream); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
380 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src)); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
381 istream = m68k_decode_op_ex(istream, opmode, reg, decoded->extra.size, &(decoded->dst)); |
0
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
382 break; |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
383 case MISC: |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
384 |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
385 if ((*istream & 0x1C0) == 0x1C0) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
386 decoded->op = M68K_LEA; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
387 decoded->extra.size = OPSIZE_LONG; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
388 decoded->dst.addr_mode = MODE_AREG; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
389 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
390 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src)); |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
391 } else { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
392 if (*istream & 0x100) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
393 decoded->op = M68K_CHK; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
394 if ((*istream & 0x180) == 0x180) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
395 decoded->extra.size = OPSIZE_WORD; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
396 } else { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
397 //only on M68020+ |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
398 #ifdef M68020 |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
399 decoded->extra.size = OPSIZE_LONG; |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
400 #else |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
401 decoded->op = M68K_INVALID; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
402 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
403 #endif |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
404 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
405 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src)); |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
406 decoded->dst.addr_mode = MODE_REG; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
407 decoded->dst.addr_mode = m68k_reg_quick_field(*istream); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
408 } else { |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
409 opmode = (*istream >> 3) & 0x7; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
410 if ((*istream & 0xB80) == 0x880 && opmode != MODE_REG && opmode != MODE_AREG && opmode != MODE_AREG_POSTINC) { |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
411 decoded->op = M68K_MOVEM; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
412 decoded->extra.size = *istream & 0x40 ? OPSIZE_LONG : OPSIZE_WORD; |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
413 reg = *istream & 0x7; |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
414 immed = *(++istream); |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
415 if(*istream & 0x400) { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
416 decoded->dst.addr_mode = MODE_REG; |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
417 decoded->dst.params.immed = immed; |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
418 istream = m68k_decode_op_ex(istream, opmode, reg, decoded->extra.size, &(decoded->src)); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
419 } else { |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
420 decoded->src.addr_mode = MODE_REG; |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
421 decoded->src.params.immed = immed; |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
422 istream = m68k_decode_op_ex(istream, opmode, reg, decoded->extra.size, &(decoded->dst)); |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
423 } |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
424 } else { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
425 optype = (*istream >> 9) & 0x7; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
426 size = (*istream >> 6) & 0x3; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
427 switch(optype) |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
428 { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
429 case 0: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
430 //Move from SR or NEGX |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
431 if (size == OPSIZE_INVALID) { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
432 decoded->op = M68K_MOVE_FROM_SR; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
433 size = OPSIZE_WORD; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
434 } else { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
435 decoded->op = M68K_NEGX; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
436 } |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
437 decoded->extra.size = size; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
438 istream= m68k_decode_op(istream, size, &(decoded->dst)); |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
439 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
440 case 1: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
441 //MOVE from CCR or CLR |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
442 if (size == OPSIZE_INVALID) { |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
443 #ifdef M68010 |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
444 decoded->op = M68K_MOVE_FROM_CCR; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
445 size = OPSIZE_WORD; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
446 #else |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
447 return istream+1; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
448 #endif |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
449 } else { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
450 decoded->op = M68K_CLR; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
451 } |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
452 decoded->extra.size = size; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
453 istream= m68k_decode_op(istream, size, &(decoded->dst)); |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
454 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
455 case 2: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
456 //MOVE to CCR or NEG |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
457 if (size == OPSIZE_INVALID) { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
458 decoded->op = M68K_MOVE_CCR; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
459 size = OPSIZE_WORD; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
460 istream= m68k_decode_op(istream, size, &(decoded->src)); |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
461 } else { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
462 decoded->op = M68K_NEG; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
463 istream= m68k_decode_op(istream, size, &(decoded->dst)); |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
464 } |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
465 decoded->extra.size = size; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
466 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
467 case 3: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
468 //MOVE to SR or NOT |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
469 if (size == OPSIZE_INVALID) { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
470 decoded->op = M68K_MOVE_SR; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
471 size = OPSIZE_WORD; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
472 istream= m68k_decode_op(istream, size, &(decoded->src)); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
473 } else { |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
474 decoded->op = M68K_NOT; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
475 istream= m68k_decode_op(istream, size, &(decoded->dst)); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
476 } |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
477 decoded->extra.size = size; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
478 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
479 case 4: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
480 //EXT, EXTB, LINK.l, NBCD, SWAP, BKPT, PEA |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
481 switch((*istream >> 3) & 0x3F) |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
482 { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
483 case 1: |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
484 #ifdef M68020 |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
485 decoded->op = M68K_LINK; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
486 decoded->extra.size = OPSIZE_LONG; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
487 reg = *istream & 0x7; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
488 immed = *(++istream) << 16; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
489 immed |= *(++istream); |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
490 #endif |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
491 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
492 case 8: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
493 decoded->op = M68K_SWAP; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
494 decoded->src.addr_mode = MODE_REG; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
495 decoded->src.params.regs.pri = *istream & 0x7; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
496 decoded->extra.size = OPSIZE_WORD; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
497 break; |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
498 case 9: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
499 #ifdef M68010 |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
500 decoded->op = M68K_BKPT; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
501 decoded->src.addr_mode = MODE_IMMEDIATE; |
10
4553fc97b15e
Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special cases
Mike Pavone <pavone@retrodev.com>
parents:
9
diff
changeset
|
502 decoded->extra.size = OPSIZE_UNSIZED; |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
503 decoded->src.params.immed = *istream & 0x7; |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
504 #endif |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
505 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
506 case 0x10: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
507 decoded->op = M68K_EXT; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
508 decoded->src.addr_mode = MODE_REG; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
509 decoded->src.params.regs.pri = *istream & 0x7; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
510 decoded->extra.size = OPSIZE_WORD; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
511 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
512 case 0x18: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
513 decoded->op = M68K_EXT; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
514 decoded->src.addr_mode = MODE_REG; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
515 decoded->src.params.regs.pri = *istream & 0x7; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
516 decoded->extra.size = OPSIZE_LONG; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
517 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
518 case 0x38: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
519 #ifdef M68020 |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
520 #endif |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
521 break; |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
522 default: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
523 if (!(*istream & 0x1C0)) { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
524 decoded->op = M68K_NBCD; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
525 decoded->extra.size = OPSIZE_BYTE; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
526 istream = m68k_decode_op(istream, OPSIZE_BYTE, &(decoded->dst)); |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
527 } else if((*istream & 0x1C0) == 0x40) { |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
528 decoded->op = M68K_PEA; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
529 decoded->extra.size = OPSIZE_LONG; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
530 istream = m68k_decode_op(istream, OPSIZE_LONG, &(decoded->dst)); |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
531 } |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
532 } |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
533 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
534 case 5: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
535 //BGND, ILLEGAL, TAS, TST |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
536 optype = *istream & 0xFF; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
537 if (optype == 0xFA) { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
538 //BGND - CPU32 only |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
539 } else if (optype == 0xFC) { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
540 decoded->op = M68K_ILLEGAL; |
10
4553fc97b15e
Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special cases
Mike Pavone <pavone@retrodev.com>
parents:
9
diff
changeset
|
541 decoded->extra.size = OPSIZE_UNSIZED; |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
542 } else { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
543 if (size == OPSIZE_INVALID) { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
544 decoded->op = M68K_TAS; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
545 } else { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
546 decoded->op = M68K_TST; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
547 decoded->extra.size = size; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
548 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src)); |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
549 } |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
550 } |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
551 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
552 case 6: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
553 //MULU, MULS, DIVU, DIVUL, DIVS, DIVSL |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
554 #ifdef M68020 |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
555 //TODO: Implement these for 68020+ support |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
556 #endif |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
557 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
558 case 7: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
559 //TRAP, LINK.w, UNLNK, MOVE USP, RESET, NOP, STOP, RTE, RTD, RTS, TRAPV, RTR, MOVEC, JSR, JMP |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
560 if (*istream & 0x80) { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
561 //JSR, JMP |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
562 if (*istream & 0x40) { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
563 decoded->op = M68K_JMP; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
564 } else { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
565 decoded->op = M68K_JSR; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
566 } |
10
4553fc97b15e
Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special cases
Mike Pavone <pavone@retrodev.com>
parents:
9
diff
changeset
|
567 decoded->extra.size = OPSIZE_UNSIZED; |
4553fc97b15e
Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special cases
Mike Pavone <pavone@retrodev.com>
parents:
9
diff
changeset
|
568 istream = m68k_decode_op(istream, OPSIZE_UNSIZED, &(decoded->src)); |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
569 } else { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
570 //it would appear bit 6 needs to be set for it to be a valid instruction here |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
571 switch((*istream >> 3) & 0x7) |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
572 { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
573 case 0: |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
574 case 1: |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
575 //TRAP |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
576 decoded->op = M68K_TRAP; |
10
4553fc97b15e
Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special cases
Mike Pavone <pavone@retrodev.com>
parents:
9
diff
changeset
|
577 decoded->extra.size = OPSIZE_UNSIZED; |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
578 decoded->src.addr_mode = MODE_IMMEDIATE; |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
579 decoded->src.params.immed = *istream & 0xF; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
580 break; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
581 case 2: |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
582 //LINK.w |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
583 decoded->op = M68K_LINK; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
584 decoded->extra.size = OPSIZE_WORD; |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
585 decoded->src.addr_mode = MODE_AREG; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
586 decoded->src.params.regs.pri = *istream & 0x7; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
587 decoded->dst.addr_mode = MODE_IMMEDIATE; |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
588 decoded->dst.params.immed = *(++istream); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
589 break; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
590 case 3: |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
591 //UNLK |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
592 decoded->op = M68K_UNLK; |
10
4553fc97b15e
Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special cases
Mike Pavone <pavone@retrodev.com>
parents:
9
diff
changeset
|
593 decoded->extra.size = OPSIZE_UNSIZED; |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
594 decoded->dst.addr_mode = MODE_AREG; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
595 decoded->dst.params.regs.pri = *istream & 0x7; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
596 break; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
597 case 4: |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
598 case 5: |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
599 //MOVE USP |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
600 decoded->op = M68K_MOVE_USP; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
601 if (*istream & 0x8) { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
602 decoded->dst.addr_mode = MODE_AREG; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
603 decoded->dst.params.regs.pri = *istream & 0x7; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
604 } else { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
605 decoded->src.addr_mode = MODE_AREG; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
606 decoded->src.params.regs.pri = *istream & 0x7; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
607 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
608 break; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
609 case 6: |
10
4553fc97b15e
Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special cases
Mike Pavone <pavone@retrodev.com>
parents:
9
diff
changeset
|
610 decoded->extra.size = OPSIZE_UNSIZED; |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
611 switch(*istream & 0x7) |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
612 { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
613 case 0: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
614 decoded->op = M68K_RESET; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
615 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
616 case 1: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
617 decoded->op = M68K_NOP; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
618 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
619 case 2: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
620 decoded->op = M68K_STOP; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
621 decoded->src.addr_mode = MODE_IMMEDIATE; |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
622 decoded->src.params.immed =*(++istream); |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
623 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
624 case 3: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
625 decoded->op = M68K_RTE; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
626 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
627 case 4: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
628 #ifdef M68010 |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
629 decoded->op = M68K_RTD; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
630 decoded->src.addr_mode = MODE_IMMEDIATE; |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
631 decoded->src.params.immed =*(++istream); |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
632 #endif |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
633 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
634 case 5: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
635 decoded->op = M68K_RTS; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
636 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
637 case 6: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
638 decoded->op = M68K_TRAPV; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
639 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
640 case 7: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
641 decoded->op = M68K_RTR; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
642 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
643 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
644 break; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
645 case 7: |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
646 //MOVEC |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
647 #ifdef M68010 |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
648 #endif |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
649 break; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
650 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
651 } |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
652 break; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
653 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
654 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
655 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
656 } |
0
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
657 break; |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
658 case QUICK_ARITH_LOOP: |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
659 size = (*istream >> 6) & 3; |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
660 if (size == 0x3) { |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
661 //DBcc, TRAPcc or Scc |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
662 m68k_decode_cond(*istream, decoded); |
0
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
663 switch ((*istream >> 3) & 0x7) |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
664 { |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
665 case 1: //DBcc |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
666 decoded->op = M68K_DBCC; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
667 decoded->src.addr_mode = MODE_IMMEDIATE; |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
668 decoded->src.params.immed = *(++istream); |
0
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
669 decoded->dst.addr_mode = MODE_REG; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
670 decoded->dst.params.regs.pri = *istream & 0x7; |
0
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
671 break; |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
672 case 7: //TRAPcc |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
673 #ifdef M68020 |
0
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
674 decoded->op = M68K_TRAPCC; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
675 decoded->src.addr_mode = MODE_IMMEDIATE; |
0
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
676 //TODO: Figure out what to do with OPMODE and optional extention words |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
677 #endif |
0
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
678 break; |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
679 default: //Scc |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
680 decoded->op = M68K_SCC; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
681 istream = m68k_decode_op(istream, OPSIZE_BYTE, &(decoded->dst)); |
0
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
682 break; |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
683 } |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
684 } else { |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
685 //ADDQ, SUBQ |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
686 decoded->variant = VAR_QUICK; |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
687 decoded->extra.size = size; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
688 decoded->src.addr_mode = MODE_IMMEDIATE; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
689 istream = m68k_decode_op(istream, size, &(decoded->dst)); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
690 immed = m68k_reg_quick_field(*istream); |
0
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
691 if (!immed) { |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
692 immed = 8; |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
693 } |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
694 decoded->src.params.immed = immed; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
695 if (*istream & 0x100) { |
0
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
696 decoded->op = M68K_SUB; |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
697 } else { |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
698 decoded->op = M68K_ADD; |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
699 } |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
700 } |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
701 break; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
702 case BRANCH: |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
703 m68k_decode_cond(*istream, decoded); |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
704 decoded->op = decoded->extra.cond == COND_FALSE ? M68K_BSR : M68K_BCC; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
705 decoded->src.addr_mode = MODE_IMMEDIATE; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
706 immed = *istream & 0xFF; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
707 if (immed == 0) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
708 decoded->variant = VAR_WORD; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
709 immed = *(++istream); |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
710 immed = sign_extend16(immed); |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
711 } else if (immed == 0xFF) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
712 decoded->variant = VAR_LONG; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
713 immed = *(++istream) << 16; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
714 immed |= *(++istream); |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
715 } else { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
716 decoded->variant = VAR_BYTE; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
717 immed = sign_extend8(immed); |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
718 } |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
719 decoded->src.params.immed = immed; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
720 break; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
721 case MOVEQ: |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
722 decoded->op = M68K_MOVE; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
723 decoded->variant = VAR_QUICK; |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
724 decoded->extra.size = OPSIZE_LONG; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
725 decoded->src.addr_mode = MODE_IMMEDIATE; |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
726 decoded->src.params.immed = sign_extend8(*istream & 0xFF); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
727 decoded->dst.addr_mode = MODE_REG; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
728 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
729 immed = *istream & 0xFF; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
730 break; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
731 case OR_DIV_SBCD: |
11
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
732 //for OR, if opmode bit 2 is 1, then src = Dn, dst = <ea> |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
733 opmode = (*istream >> 6) & 0x7; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
734 size = opmode & 0x3; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
735 if (size == OPSIZE_INVALID || (opmode & 0x4 && !(*istream & 0x30))) { |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
736 switch(opmode) |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
737 { |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
738 case 3: |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
739 decoded->op = M68K_DIVU; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
740 decoded->extra.size = OPSIZE_WORD; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
741 decoded->dst.addr_mode = MODE_REG; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
742 decoded->dst.params.regs.pri = (*istream >> 9) & 0x7; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
743 istream = m68k_decode_op(istream, OPSIZE_WORD, &(decoded->src)); |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
744 break; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
745 case 4: |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
746 decoded->op = M68K_SBCD; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
747 decoded->dst.addr_mode = decoded->src.addr_mode = *istream & 0x8 ? MODE_AREG_PREDEC : MODE_REG; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
748 decoded->src.params.regs.pri = *istream & 0x7; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
749 decoded->dst.params.regs.pri = (*istream >> 9) & 0x7; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
750 break; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
751 case 5: |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
752 #ifdef M68020 |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
753 #endif |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
754 break; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
755 case 6: |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
756 #ifdef M68020 |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
757 #endif |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
758 break; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
759 case 7: |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
760 decoded->op = M68K_DIVS; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
761 decoded->extra.size = OPSIZE_WORD; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
762 decoded->dst.addr_mode = MODE_REG; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
763 decoded->dst.params.regs.pri = (*istream >> 9) & 0x7; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
764 istream = m68k_decode_op(istream, OPSIZE_WORD, &(decoded->src)); |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
765 break; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
766 } |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
767 } else { |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
768 decoded->op = M68K_OR; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
769 decoded->extra.size = size; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
770 if (opmode & 0x4) { |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
771 decoded->src.addr_mode = MODE_REG; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
772 decoded->src.params.regs.pri = (*istream >> 9) & 0x7; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
773 istream = m68k_decode_op(istream, size, &(decoded->dst)); |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
774 } else { |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
775 decoded->dst.addr_mode = MODE_REG; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
776 decoded->dst.params.regs.pri = (*istream >> 9) & 0x7; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
777 istream = m68k_decode_op(istream, size, &(decoded->src)); |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
778 } |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
779 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
780 break; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
781 case SUB_SUBX: |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
782 size = *istream >> 6 & 0x3; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
783 decoded->op = M68K_SUB; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
784 if (*istream & 0x100) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
785 //<ea> destination, SUBA.l or SUBX |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
786 if (*istream & 0x6) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
787 if (size == OPSIZE_INVALID) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
788 //SUBA.l |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
789 decoded->extra.size = OPSIZE_LONG; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
790 decoded->dst.addr_mode = MODE_AREG; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
791 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
792 istream = m68k_decode_op(istream, OPSIZE_LONG, &(decoded->src)); |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
793 } else { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
794 decoded->extra.size = size; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
795 decoded->src.addr_mode = MODE_REG; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
796 decoded->src.params.regs.pri = m68k_reg_quick_field(*istream); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
797 istream = m68k_decode_op(istream, size, &(decoded->dst)); |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
798 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
799 } else { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
800 //SUBX |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
801 decoded->op = M68K_SUBX; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
802 decoded->extra.size = size; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
803 istream = m68k_decode_op(istream, size, &(decoded->src)); |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
804 decoded->dst.addr_mode = decoded->src.addr_mode; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
805 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
806 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
807 } else { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
808 if (size == OPSIZE_INVALID) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
809 //SUBA.w |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
810 decoded->extra.size = OPSIZE_WORD; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
811 decoded->dst.addr_mode = MODE_AREG; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
812 } else { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
813 decoded->extra.size = size; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
814 decoded->dst.addr_mode = MODE_REG; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
815 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
816 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
817 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src)); |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
818 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
819 break; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
820 case RESERVED: |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
821 break; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
822 case CMP_XOR: |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
823 size = *istream >> 6 & 0x3; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
824 decoded->op = M68K_CMP; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
825 if (*istream & 0x100) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
826 //CMPM or EOR |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
827 istream = m68k_decode_op(istream, size, &(decoded->dst)); |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
828 if (decoded->src.addr_mode == MODE_AREG) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
829 //CMPM |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
830 decoded->src.addr_mode = decoded->dst.addr_mode = MODE_AREG_POSTINC; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
831 decoded->src.params.regs.pri = decoded->dst.params.regs.pri; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
832 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
833 } else { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
834 //EOR |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
835 decoded->op = M68K_EOR; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
836 decoded->extra.size = size; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
837 decoded->src.addr_mode = MODE_REG; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
838 decoded->src.params.regs.pri = m68k_reg_quick_field(*istream); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
839 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
840 } else { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
841 //CMP |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
842 decoded->extra.size = size; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
843 decoded->dst.addr_mode = MODE_REG; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
844 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
845 istream = m68k_decode_op(istream, size, &(decoded->src)); |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
846 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
847 break; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
848 case AND_MUL_ABCD_EXG: |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
849 //page 575 for summary |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
850 //EXG opmodes: |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
851 //01000 -data regs |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
852 //01001 -addr regs |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
853 //10001 -one of each |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
854 //AND opmodes: |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
855 //operand order bit + 2 size bits (00 - 10) |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
856 //no address register direct addressing |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
857 //data register direct not allowed when <ea> is the source (operand order bit of 1) |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
858 if (*istream & 0x100) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
859 if ((*istream & 0xC0) == 0xC0) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
860 decoded->op = M68K_MULS; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
861 decoded->extra.size = OPSIZE_WORD; |
3
a4ad0e3e3e0e
Finish mulu.w, muls.w and abcd parameter decoding
Mike Pavone <pavone@retrodev.com>
parents:
2
diff
changeset
|
862 decoded->dst.addr_mode = MODE_REG; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
863 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
864 istream = m68k_decode_op(istream, OPSIZE_WORD, &(decoded->src)); |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
865 } else if(!(*istream & 0xF0)) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
866 decoded->op = M68K_ABCD; |
3
a4ad0e3e3e0e
Finish mulu.w, muls.w and abcd parameter decoding
Mike Pavone <pavone@retrodev.com>
parents:
2
diff
changeset
|
867 decoded->extra.size = OPSIZE_BYTE; |
a4ad0e3e3e0e
Finish mulu.w, muls.w and abcd parameter decoding
Mike Pavone <pavone@retrodev.com>
parents:
2
diff
changeset
|
868 decoded->src.params.regs.pri = *istream & 0x7; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
869 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream); |
3
a4ad0e3e3e0e
Finish mulu.w, muls.w and abcd parameter decoding
Mike Pavone <pavone@retrodev.com>
parents:
2
diff
changeset
|
870 decoded->dst.addr_mode = decoded->src.addr_mode = (*istream & 8) ? MODE_AREG_PREDEC : MODE_REG; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
871 } else if(!(*istream & 0x30)) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
872 decoded->op = M68K_EXG; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
873 decoded->extra.size = OPSIZE_LONG; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
874 decoded->src.params.regs.pri = m68k_reg_quick_field(*istream); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
875 decoded->dst.params.regs.pri = *istream & 0x7; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
876 if (*istream & 0x8) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
877 if (*istream & 0x80) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
878 decoded->src.addr_mode = MODE_REG; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
879 decoded->dst.addr_mode = MODE_AREG; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
880 } else { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
881 decoded->src.addr_mode = decoded->dst.addr_mode = MODE_AREG; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
882 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
883 } else { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
884 decoded->src.addr_mode = decoded->dst.addr_mode = MODE_REG; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
885 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
886 } else { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
887 decoded->op = M68K_AND; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
888 decoded->extra.size = (*istream >> 6); |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
889 decoded->dst.addr_mode = MODE_REG; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
890 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
891 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src)); |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
892 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
893 } else { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
894 if ((*istream & 0xC0) == 0xC0) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
895 decoded->op = M68K_MULU; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
896 decoded->extra.size = OPSIZE_WORD; |
3
a4ad0e3e3e0e
Finish mulu.w, muls.w and abcd parameter decoding
Mike Pavone <pavone@retrodev.com>
parents:
2
diff
changeset
|
897 decoded->dst.addr_mode = MODE_REG; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
898 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
899 istream = m68k_decode_op(istream, OPSIZE_WORD, &(decoded->src)); |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
900 } else { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
901 decoded->op = M68K_AND; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
902 decoded->extra.size = (*istream >> 6); |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
903 decoded->src.addr_mode = MODE_REG; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
904 decoded->src.params.regs.pri = m68k_reg_quick_field(*istream); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
905 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->dst)); |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
906 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
907 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
908 break; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
909 case ADD_ADDX: |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
910 size = *istream >> 6 & 0x3; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
911 decoded->op = M68K_ADD; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
912 if (*istream & 0x100) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
913 //<ea> destination, ADDA.l or ADDX |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
914 if (*istream & 0x6) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
915 if (size == OPSIZE_INVALID) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
916 //ADDA.l |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
917 decoded->extra.size = OPSIZE_LONG; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
918 decoded->dst.addr_mode = MODE_AREG; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
919 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
920 istream = m68k_decode_op(istream, OPSIZE_LONG, &(decoded->src)); |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
921 } else { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
922 decoded->extra.size = size; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
923 decoded->src.addr_mode = MODE_REG; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
924 decoded->src.params.regs.pri = m68k_reg_quick_field(*istream); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
925 istream = m68k_decode_op(istream, size, &(decoded->dst)); |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
926 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
927 } else { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
928 //ADDX |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
929 decoded->op = M68K_ADDX; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
930 //FIXME: Size is not technically correct |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
931 decoded->extra.size = size; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
932 istream = m68k_decode_op(istream, size, &(decoded->src)); |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
933 decoded->dst.addr_mode = decoded->src.addr_mode; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
934 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
935 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
936 } else { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
937 if (size == OPSIZE_INVALID) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
938 //ADDA.w |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
939 decoded->extra.size = OPSIZE_WORD; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
940 decoded->dst.addr_mode = MODE_AREG; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
941 } else { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
942 decoded->extra.size = size; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
943 decoded->dst.addr_mode = MODE_REG; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
944 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
945 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
946 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src)); |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
947 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
948 break; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
949 case SHIFT_ROTATE: |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
950 if ((*istream & 0x8C0) == 0xC0) { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
951 switch((*istream >> 8) & 0x7) |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
952 { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
953 case 0: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
954 decoded->op = M68K_ASR; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
955 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
956 case 1: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
957 decoded->op = M68K_ASL; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
958 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
959 case 2: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
960 decoded->op = M68K_LSR; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
961 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
962 case 3: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
963 decoded->op = M68K_LSL; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
964 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
965 case 4: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
966 decoded->op = M68K_ROXR; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
967 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
968 case 5: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
969 decoded->op = M68K_ROXL; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
970 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
971 case 6: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
972 decoded->op = M68K_ROR; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
973 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
974 case 7: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
975 decoded->op = M68K_ROL; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
976 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
977 } |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
978 decoded->extra.size = OPSIZE_WORD; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
979 istream = m68k_decode_op(istream, OPSIZE_WORD, &(decoded->dst)); |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
980 } else if((*istream & 0xC0) != 0xC0) { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
981 switch(((*istream >> 2) & 0x6) | ((*istream >> 8) & 1)) |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
982 { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
983 case 0: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
984 decoded->op = M68K_ASR; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
985 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
986 case 1: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
987 decoded->op = M68K_ASL; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
988 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
989 case 2: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
990 decoded->op = M68K_LSR; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
991 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
992 case 3: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
993 decoded->op = M68K_LSL; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
994 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
995 case 4: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
996 decoded->op = M68K_ROXR; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
997 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
998 case 5: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
999 decoded->op = M68K_ROXL; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1000 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1001 case 6: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1002 decoded->op = M68K_ROR; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1003 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1004 case 7: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1005 decoded->op = M68K_ROL; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1006 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1007 } |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1008 decoded->extra.size = (*istream >> 6) & 0x3; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1009 immed = (*istream >> 9) & 0x7; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1010 if (*istream & 0x100) { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1011 decoded->src.addr_mode = MODE_IMMEDIATE; |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
1012 decoded->src.params.immed = immed; |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1013 } else { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1014 decoded->src.addr_mode = MODE_REG; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1015 decoded->src.params.regs.pri = immed; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1016 } |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1017 decoded->dst.addr_mode = MODE_REG; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1018 decoded->dst.params.regs.pri = *istream & 0x7; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1019 |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1020 } else { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1021 #ifdef M68020 |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1022 //TODO: Implement bitfield instructions for M68020+ support |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1023 #endif |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1024 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1025 break; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1026 case COPROC: |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1027 //TODO: Implement me |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1028 break; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1029 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1030 return istream+1; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1031 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1032 |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1033 char * mnemonics[] = { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1034 "abcd", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1035 "add", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1036 "addx", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1037 "and", |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1038 "andi",//ccr |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1039 "andi",//sr |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1040 "asl", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1041 "asr", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1042 "bcc", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1043 "bchg", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1044 "bclr", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1045 "bset", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1046 "bsr", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1047 "btst", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1048 "chk", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1049 "clr", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1050 "cmp", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1051 "dbcc", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1052 "divs", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1053 "divu", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1054 "eor", |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1055 "eori",//ccr |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1056 "eori",//sr |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1057 "exg", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1058 "ext", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1059 "illegal", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1060 "jmp", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1061 "jsr", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1062 "lea", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1063 "link", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1064 "lsl", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1065 "lsr", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1066 "move", |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1067 "move",//ccr |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1068 "move",//from_sr |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1069 "move",//sr |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1070 "move_usp", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1071 "movem", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1072 "movep", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1073 "muls", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1074 "mulu", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1075 "nbcd", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1076 "neg", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1077 "negx", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1078 "nop", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1079 "not", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1080 "or", |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1081 "ori",//ccr |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1082 "ori",//sr |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1083 "pea", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1084 "reset", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1085 "rol", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1086 "ror", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1087 "roxl", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1088 "roxr", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1089 "rte", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1090 "rtr", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1091 "rts", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1092 "sbcd", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1093 "scc", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1094 "stop", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1095 "sub", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1096 "subx", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1097 "swap", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1098 "tas", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1099 "trap", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1100 "trapv", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1101 "tst", |
12
db60ed283d8d
Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents:
11
diff
changeset
|
1102 "unlk", |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1103 "invalid" |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1104 }; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1105 |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1106 char * cond_mnem[] = { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1107 "ra", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1108 "f", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1109 "hi", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1110 "ls", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1111 "cc", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1112 "cs", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1113 "ne", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1114 "eq", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1115 "vc", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1116 "vs", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1117 "pl", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1118 "mi", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1119 "ge", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1120 "lt", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1121 "gt", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1122 "le" |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1123 }; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1124 |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
1125 int m68k_disasm_op(m68k_op_info *decoded, char *dst, int need_comma) |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1126 { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1127 char * c = need_comma ? "," : ""; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1128 switch(decoded->addr_mode) |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1129 { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1130 case MODE_REG: |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1131 return sprintf(dst, "%s d%d", c, decoded->params.regs.pri); |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1132 case MODE_AREG: |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1133 return sprintf(dst, "%s a%d", c, decoded->params.regs.pri); |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1134 case MODE_AREG_INDIRECT: |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
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|
1135 return sprintf(dst, "%s (a%d)", c, decoded->params.regs.pri); |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1136 case MODE_AREG_POSTINC: |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1137 return sprintf(dst, "%s (a%d)+", c, decoded->params.regs.pri); |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1138 case MODE_AREG_PREDEC: |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1139 return sprintf(dst, "%s -(a%d)", c, decoded->params.regs.pri); |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1140 case MODE_AREG_DISPLACE: |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1141 return sprintf(dst, "%s (a%d, %d)", c, decoded->params.regs.pri, decoded->params.regs.displacement); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1142 case MODE_IMMEDIATE: |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
1143 return sprintf(dst, "%s #%d", c, decoded->params.immed); |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1144 case MODE_ABSOLUTE_SHORT: |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
1145 return sprintf(dst, "%s $%X.w", c, decoded->params.immed); |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1146 case MODE_ABSOLUTE: |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
1147 return sprintf(dst, "%s $%X", c, decoded->params.immed); |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1148 case MODE_PC_DISPLACE: |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1149 return sprintf(dst, "%s (pc, %d)", c, decoded->params.regs.displacement); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1150 default: |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1151 return 0; |
0
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1152 } |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1153 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1154 |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
1155 int m68k_disasm_movem_op(m68k_op_info *decoded, m68k_op_info *other, char *dst, int need_comma) |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1156 { |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1157 int8_t dir, reg, bit, regnum, last=-1, lastreg, first=-1; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1158 char *rtype, *last_rtype; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1159 int oplen; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1160 if (decoded->addr_mode == MODE_REG) { |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1161 if (other->addr_mode == MODE_AREG_PREDEC) { |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1162 bit = 15; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1163 dir = -1; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1164 } else { |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1165 reg = 0; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1166 bit = 1; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1167 } |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1168 strcat(dst, " "); |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1169 for (oplen = 1, reg=0; bit < 16 && bit > -1; bit += dir, reg++) { |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
1170 if (decoded->params.immed & (1 << bit)) { |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1171 if (reg > 7) { |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1172 rtype = "a"; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1173 regnum = reg - 8; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1174 } else { |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1175 rtype = "d"; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1176 regnum = reg; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1177 } |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1178 if (last >= 0 && last == regnum - 1 && lastreg == reg - 1) { |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1179 last = regnum; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1180 lastreg = reg; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1181 } else if(last >= 0) { |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1182 if (first != last) { |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1183 oplen += sprintf(dst + oplen, "-%s%d/%s%d",last_rtype, last, rtype, regnum); |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1184 } else { |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1185 oplen += sprintf(dst + oplen, "/%s%d", rtype, regnum); |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1186 } |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1187 first = last = regnum; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1188 last_rtype = rtype; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1189 lastreg = reg; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1190 } else { |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1191 oplen += sprintf(dst + oplen, "%s%d", rtype, regnum); |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1192 first = last = regnum; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1193 last_rtype = rtype; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1194 lastreg = reg; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1195 } |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1196 } |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1197 } |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1198 if (last >= 0 && last != first) { |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1199 oplen += sprintf(dst + oplen, "-%s%d", last_rtype, last); |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1200 } |
168b1a873895
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Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1201 return oplen; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1202 } else { |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
1203 return m68k_disasm_op(decoded, dst, need_comma); |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1204 } |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1205 } |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1206 |
2
5df303bf72e6
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Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1207 int m68k_disasm(m68kinst * decoded, char * dst) |
5df303bf72e6
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Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1208 { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1209 int ret,op1len; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1210 uint8_t size; |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1211 char * special_op = "CCR"; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1212 switch (decoded->op) |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1213 { |
168b1a873895
Improve disassembly. FIx some decoding bugs.
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parents:
12
diff
changeset
|
1214 case M68K_BCC: |
168b1a873895
Improve disassembly. FIx some decoding bugs.
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parents:
12
diff
changeset
|
1215 case M68K_DBCC: |
168b1a873895
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Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1216 case M68K_SCC: |
2
5df303bf72e6
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Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1217 ret = strlen(mnemonics[decoded->op]) - 2; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
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1218 memcpy(dst, mnemonics[decoded->op], ret); |
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1219 dst[ret] = 0; |
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1220 strcat(dst, cond_mnem[decoded->extra.cond]); |
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1221 ret = strlen(dst); |
13
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1222 break; |
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1223 case M68K_BSR: |
2
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1224 ret = sprintf(dst, "bsr%s", decoded->variant == VAR_BYTE ? ".s" : ""); |
13
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1225 break; |
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1226 case M68K_MOVE_FROM_SR: |
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1227 ret = sprintf(dst, "%s", mnemonics[decoded->op]); |
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1228 ret += sprintf(dst + ret, " SR"); |
15
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1229 ret += m68k_disasm_op(&(decoded->dst), dst + ret, 1); |
13
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1230 return ret; |
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1231 case M68K_ANDI_SR: |
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1232 case M68K_EORI_SR: |
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1233 case M68K_MOVE_SR: |
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1234 case M68K_ORI_SR: |
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1235 special_op = "SR"; |
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1236 case M68K_ANDI_CCR: |
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1237 case M68K_EORI_CCR: |
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1238 case M68K_MOVE_CCR: |
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1239 case M68K_ORI_CCR: |
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1240 ret = sprintf(dst, "%s", mnemonics[decoded->op]); |
15
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1241 ret += m68k_disasm_op(&(decoded->src), dst + ret, 0); |
13
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1242 ret += sprintf(dst + ret, ", %s", special_op); |
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1243 return ret; |
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1244 default: |
2
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1245 size = decoded->extra.size; |
13
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1246 ret = sprintf(dst, "%s%s%s", |
2
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1247 mnemonics[decoded->op], |
8
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1248 decoded->variant == VAR_QUICK ? "q" : (decoded->variant == VAR_IMMEDIATE ? "i" : ""), |
13
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1249 size == OPSIZE_BYTE ? ".b" : (size == OPSIZE_WORD ? ".w" : (size == OPSIZE_LONG ? ".l" : ""))); |
2
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1250 } |
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1251 if (decoded->op == M68K_MOVEM) { |
15
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1252 op1len = m68k_disasm_movem_op(&(decoded->src), &(decoded->dst), dst + ret, 0); |
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1253 ret += op1len; |
15
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1254 ret += m68k_disasm_movem_op(&(decoded->dst), &(decoded->src), dst + ret, op1len); |
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1255 } else { |
15
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1256 op1len = m68k_disasm_op(&(decoded->src), dst + ret, 0); |
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1257 ret += op1len; |
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1258 ret += m68k_disasm_op(&(decoded->dst), dst + ret, op1len); |
13
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1259 } |
2
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1260 return ret; |
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1261 } |
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1262 |