repos/blastem: vdp.c annotate

annotate vdp.c @ 717:22dbdf50d33c

Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.

author	Michael Pavone <pavone@retrodev.com>
date	Tue, 19 May 2015 23:23:53 -0700
parents	e29bc2918f69
children	eaba6789f316

rev	line source
467 140af5509ce7 Added copyright notice to source files and added GPL license text in COPYING Mike Pavone <pavone@retrodev.com> parents: 462 diff changeset	1 /*
140af5509ce7 Added copyright notice to source files and added GPL license text in COPYING Mike Pavone <pavone@retrodev.com> parents: 462 diff changeset	2 Copyright 2013 Michael Pavone
470 541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM. Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	3 This file is part of BlastEm.
467 140af5509ce7 Added copyright notice to source files and added GPL license text in COPYING Mike Pavone <pavone@retrodev.com> parents: 462 diff changeset	4 BlastEm is free software distributed under the terms of the GNU General Public License version 3 or greater. See COPYING for full license text.
140af5509ce7 Added copyright notice to source files and added GPL license text in COPYING Mike Pavone <pavone@retrodev.com> parents: 462 diff changeset	5 */
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	6 #include "vdp.h"
75 108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	7 #include "blastem.h"
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	8 #include <stdlib.h>
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	9 #include <string.h>
426 add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	10 #include "render.h"
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	11
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	12 #define NTSC_INACTIVE_START 224
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	13 #define PAL_INACTIVE_START 240
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	14 #define BUF_BIT_PRIORITY 0x40
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	15 #define MAP_BIT_PRIORITY 0x8000
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	16 #define MAP_BIT_H_FLIP 0x800
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	17 #define MAP_BIT_V_FLIP 0x1000
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	18
39 3c69319269ef Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should Mike Pavone <pavone@retrodev.com> parents: 38 diff changeset	19 #define SCROLL_BUFFER_SIZE 32
436 e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	20 #define SCROLL_BUFFER_MASK (SCROLL_BUFFER_SIZE-1)
e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	21 #define SCROLL_BUFFER_DRAW (SCROLL_BUFFER_SIZE/2)
39 3c69319269ef Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should Mike Pavone <pavone@retrodev.com> parents: 38 diff changeset	22
328 bf7ed23efa40 Fewer magic numbers in the VDP core for the win Mike Pavone <pavone@retrodev.com> parents: 327 diff changeset	23 #define MCLKS_SLOT_H40 16
bf7ed23efa40 Fewer magic numbers in the VDP core for the win Mike Pavone <pavone@retrodev.com> parents: 327 diff changeset	24 #define MCLKS_SLOT_H32 20
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	25 #define VINT_SLOT_H40 4 //21 slots before HSYNC, 16 during, 10 after
711 3342548de036 Adjust H32 vint slot in response to latest test ROM data Michael Pavone <pavone@retrodev.com> parents: 710 diff changeset	26 #define VINT_SLOT_H32 4 //old value was 23, but recent tests suggest the actual value is close to the H40 one
697 7f96bd1cb1be Sync fixes and logging to fix more sync issues Michael Pavone <pavone@retrodev.com> parents: 680 diff changeset	27 #define HSYNC_SLOT_H40 234
7f96bd1cb1be Sync fixes and logging to fix more sync issues Michael Pavone <pavone@retrodev.com> parents: 680 diff changeset	28 #define HSYNC_END_H40 (HSYNC_SLOT_H40+17)
331 de17e0352f27 Fixup VINT cycle and HBLANK flag for the previous timing fixes Mike Pavone <pavone@retrodev.com> parents: 330 diff changeset	29 #define HSYNC_END_H32 (33 * MCLKS_SLOT_H32)
647 5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events Michael Pavone <pavone@retrodev.com> parents: 629 diff changeset	30 #define HBLANK_START_H40 178 //should be 179 according to Nemesis, but 178 seems to fit slightly better with my test ROM results
5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events Michael Pavone <pavone@retrodev.com> parents: 629 diff changeset	31 #define HBLANK_END_H40 0 //should be 5.5 according to Nemesis, but 0 seems to fit better with my test ROM results
5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events Michael Pavone <pavone@retrodev.com> parents: 629 diff changeset	32 #define HBLANK_START_H32 233 //should be 147 according to Nemesis which is very different from my test ROM result
5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events Michael Pavone <pavone@retrodev.com> parents: 629 diff changeset	33 #define HBLANK_END_H32 0 //should be 5 according to Nemesis, but 0 seems to fit better with my test ROM results
5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events Michael Pavone <pavone@retrodev.com> parents: 629 diff changeset	34 #define LINE_CHANGE_H40 165
5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events Michael Pavone <pavone@retrodev.com> parents: 629 diff changeset	35 #define LINE_CHANGE_H32 132
717 22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	36 #define VBLANK_START_H40 (LINE_CHANGE_H40+2)
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	37 #define VBLANK_START_H32 (LINE_CHANGE_H32+2)
460 788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	38 #define FIFO_LATENCY 3
328 bf7ed23efa40 Fewer magic numbers in the VDP core for the win Mike Pavone <pavone@retrodev.com> parents: 327 diff changeset	39
426 add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	40 int32_t color_map[1 << 12];
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	41 uint8_t levels[] = {0, 27, 49, 71, 87, 103, 119, 130, 146, 157, 174, 190, 206, 228, 255};
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	42
437 afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	43 uint8_t debug_base[][3] = {
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	44 {127, 127, 127}, //BG
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	45 {0, 0, 127}, //A
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	46 {127, 0, 0}, //Window
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	47 {0, 127, 0}, //B
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	48 {127, 0, 127} //Sprites
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	49 };
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	50
426 add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	51 uint8_t color_map_init_done;
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	52
623 66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	53 void init_vdp_context(vdp_context * context, uint8_t region_pal)
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	54 {
58 a6a19c45d358 Properly zero-init all VDP buffers. Comment out some debug printfs. Mike Pavone <pavone@retrodev.com> parents: 56 diff changeset	55 memset(context, 0, sizeof(*context));
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	56 context->vdpmem = malloc(VRAM_SIZE);
58 a6a19c45d358 Properly zero-init all VDP buffers. Comment out some debug printfs. Mike Pavone <pavone@retrodev.com> parents: 56 diff changeset	57 memset(context->vdpmem, 0, VRAM_SIZE);
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	58 /*
488 32f053ad9b02 Basic OpenGL rendering is working Mike Pavone <pavone@retrodev.com> parents: 481 diff changeset	59 */
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	60 if (headless) {
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	61 context->oddbuf = context->framebuf = malloc(FRAMEBUF_ENTRIES * (32 / 8));
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	62 memset(context->framebuf, 0, FRAMEBUF_ENTRIES * (32 / 8));
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	63 context->evenbuf = malloc(FRAMEBUF_ENTRIES * (32 / 8));
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	64 memset(context->evenbuf, 0, FRAMEBUF_ENTRIES * (32 / 8));
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	65 context->b32 = 1;
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	66 } else {
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	67 render_alloc_surfaces(context);
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	68 context->b32 = render_depth() == 32;
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	69 }
488 32f053ad9b02 Basic OpenGL rendering is working Mike Pavone <pavone@retrodev.com> parents: 481 diff changeset	70 context->framebuf = context->oddbuf;
39 3c69319269ef Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should Mike Pavone <pavone@retrodev.com> parents: 38 diff changeset	71 context->linebuf = malloc(LINEBUF_SIZE + SCROLL_BUFFER_SIZE*2);
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	72 memset(context->linebuf, 0, LINEBUF_SIZE + SCROLL_BUFFER_SIZE*2);
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	73 context->tmp_buf_a = context->linebuf + LINEBUF_SIZE;
39 3c69319269ef Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should Mike Pavone <pavone@retrodev.com> parents: 38 diff changeset	74 context->tmp_buf_b = context->tmp_buf_a + SCROLL_BUFFER_SIZE;
26 a7c2b92d8056 Fix management of context->sprite_draws so the sprite layer only draws when it should Mike Pavone <pavone@retrodev.com> parents: 25 diff changeset	75 context->sprite_draws = MAX_DRAWS;
471 f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	76 context->fifo_write = 0;
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	77 context->fifo_read = -1;
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	78
426 add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	79 if (!color_map_init_done) {
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	80 uint8_t b,g,r;
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	81 for (uint16_t color = 0; color < (1 << 12); color++) {
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	82 if (color & FBUF_SHADOW) {
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	83 b = levels[(color >> 9) & 0x7];
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	84 g = levels[(color >> 5) & 0x7];
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	85 r = levels[(color >> 1) & 0x7];
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	86 } else if(color & FBUF_HILIGHT) {
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	87 b = levels[((color >> 9) & 0x7) + 7];
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	88 g = levels[((color >> 5) & 0x7) + 7];
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	89 r = levels[((color >> 1) & 0x7) + 7];
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	90 } else {
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	91 b = levels[(color >> 8) & 0xE];
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	92 g = levels[(color >> 4) & 0xE];
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	93 r = levels[color & 0xE];
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	94 }
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	95 color_map[color] = render_map_color(r, g, b);
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	96 }
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	97 color_map_init_done = 1;
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	98 }
437 afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	99 for (uint8_t color = 0; color < (1 << (3 + 1 + 1 + 1)); color++)
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	100 {
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	101 uint8_t src = color & DBG_SRC_MASK;
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	102 if (src > DBG_SRC_S) {
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	103 context->debugcolors[color] = 0;
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	104 } else {
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	105 uint8_t r,g,b;
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	106 b = debug_base[src][0];
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	107 g = debug_base[src][1];
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	108 r = debug_base[src][2];
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	109 if (color & DBG_PRIORITY)
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	110 {
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	111 if (b) {
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	112 b += 48;
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	113 }
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	114 if (g) {
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	115 g += 48;
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	116 }
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	117 if (r) {
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	118 r += 48;
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	119 }
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	120 }
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	121 if (color & DBG_SHADOW) {
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	122 b /= 2;
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	123 g /= 2;
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	124 r /=2 ;
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	125 }
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	126 if (color & DBG_HILIGHT) {
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	127 if (b) {
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	128 b += 72;
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	129 }
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	130 if (g) {
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	131 g += 72;
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	132 }
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	133 if (r) {
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	134 r += 72;
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	135 }
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	136 }
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	137 context->debugcolors[color] = render_map_color(r, g, b);
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	138 }
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	139 }
623 66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	140 if (region_pal) {
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	141 context->flags2 \|= FLAG2_REGION_PAL;
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	142 }
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	143 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	144
460 788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	145 int is_refresh(vdp_context * context, uint32_t slot)
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	146 {
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	147 if (context->regs[REG_MODE_4] & BIT_H40) {
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	148 return slot == 250 \|\| slot == 26 \|\| slot == 59 \|\| slot == 90 \|\| slot == 122 \|\| slot == 154;
460 788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	149 } else {
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	150 //TODO: Figure out which slots are refresh when display is off in 32-cell mode
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	151 //These numbers are guesses based on H40 numbers
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	152 return slot == 243 \|\| slot == 19 \|\| slot == 51 \|\| slot == 83 \|\| slot == 115;
460 788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	153 //The numbers below are the refresh slots during active display
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	154 //return (slot == 29 \|\| slot == 61 \|\| slot == 93 \|\| slot == 125);
460 788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	155 }
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	156 }
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	157
21 72ce60cb1711 Sprites somewhat less broken Mike Pavone <pavone@retrodev.com> parents: 20 diff changeset	158 void render_sprite_cells(vdp_context * context)
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	159 {
21 72ce60cb1711 Sprites somewhat less broken Mike Pavone <pavone@retrodev.com> parents: 20 diff changeset	160 if (context->cur_slot >= context->sprite_draws) {
72ce60cb1711 Sprites somewhat less broken Mike Pavone <pavone@retrodev.com> parents: 20 diff changeset	161 sprite_draw * d = context->sprite_draw_list + context->cur_slot;
450 3758bcdae5de Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty Mike Pavone <pavone@retrodev.com> parents: 438 diff changeset	162
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	163 uint16_t dir;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	164 int16_t x;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	165 if (d->h_flip) {
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	166 x = d->x_pos + 7;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	167 dir = -1;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	168 } else {
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	169 x = d->x_pos;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	170 dir = 1;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	171 }
27 aa1c47fab3f1 Fix sprite transparency for overlapping sprites Mike Pavone <pavone@retrodev.com> parents: 26 diff changeset	172 //printf("Draw Slot %d of %d, Rendering sprite cell from %X to x: %d\n", context->cur_slot, context->sprite_draws, d->address, x);
26 a7c2b92d8056 Fix management of context->sprite_draws so the sprite layer only draws when it should Mike Pavone <pavone@retrodev.com> parents: 25 diff changeset	173 context->cur_slot--;
143 e5487ef04619 Fix infinite loop bug in sprite rendering Mike Pavone <pavone@retrodev.com> parents: 142 diff changeset	174 for (uint16_t address = d->address; address != ((d->address+4) & 0xFFFF); address++) {
27 aa1c47fab3f1 Fix sprite transparency for overlapping sprites Mike Pavone <pavone@retrodev.com> parents: 26 diff changeset	175 if (x >= 0 && x < 320 && !(context->linebuf[x] & 0xF)) {
494 8ac0eb05642c Initial implementation of sprite overflow and sprite collision status register flags Mike Pavone <pavone@retrodev.com> parents: 481 diff changeset	176 if (context->linebuf[x] && (context->vdpmem[address] >> 4)) {
8ac0eb05642c Initial implementation of sprite overflow and sprite collision status register flags Mike Pavone <pavone@retrodev.com> parents: 481 diff changeset	177 context->flags2 \|= FLAG2_SPRITE_COLLIDE;
8ac0eb05642c Initial implementation of sprite overflow and sprite collision status register flags Mike Pavone <pavone@retrodev.com> parents: 481 diff changeset	178 }
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	179 context->linebuf[x] = (context->vdpmem[address] >> 4) \| d->pal_priority;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	180 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	181 x += dir;
27 aa1c47fab3f1 Fix sprite transparency for overlapping sprites Mike Pavone <pavone@retrodev.com> parents: 26 diff changeset	182 if (x >= 0 && x < 320 && !(context->linebuf[x] & 0xF)) {
494 8ac0eb05642c Initial implementation of sprite overflow and sprite collision status register flags Mike Pavone <pavone@retrodev.com> parents: 481 diff changeset	183 if (context->linebuf[x] && (context->vdpmem[address] & 0xF)) {
8ac0eb05642c Initial implementation of sprite overflow and sprite collision status register flags Mike Pavone <pavone@retrodev.com> parents: 481 diff changeset	184 context->flags2 \|= FLAG2_SPRITE_COLLIDE;
8ac0eb05642c Initial implementation of sprite overflow and sprite collision status register flags Mike Pavone <pavone@retrodev.com> parents: 481 diff changeset	185 }
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	186 context->linebuf[x] = (context->vdpmem[address] & 0xF) \| d->pal_priority;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	187 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	188 x += dir;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	189 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	190 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	191 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	192
322 8e2fa485c0f2 Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview. Mike Pavone <pavone@retrodev.com> parents: 318 diff changeset	193 void vdp_print_sprite_table(vdp_context * context)
8e2fa485c0f2 Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview. Mike Pavone <pavone@retrodev.com> parents: 318 diff changeset	194 {
8e2fa485c0f2 Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview. Mike Pavone <pavone@retrodev.com> parents: 318 diff changeset	195 uint16_t sat_address = (context->regs[REG_SAT] & 0x7F) << 9;
8e2fa485c0f2 Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview. Mike Pavone <pavone@retrodev.com> parents: 318 diff changeset	196 uint16_t current_index = 0;
8e2fa485c0f2 Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview. Mike Pavone <pavone@retrodev.com> parents: 318 diff changeset	197 uint8_t count = 0;
8e2fa485c0f2 Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview. Mike Pavone <pavone@retrodev.com> parents: 318 diff changeset	198 do {
8e2fa485c0f2 Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview. Mike Pavone <pavone@retrodev.com> parents: 318 diff changeset	199 uint16_t address = current_index * 8 + sat_address;
8e2fa485c0f2 Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview. Mike Pavone <pavone@retrodev.com> parents: 318 diff changeset	200 uint8_t height = ((context->vdpmem[address+2] & 0x3) + 1) * 8;
8e2fa485c0f2 Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview. Mike Pavone <pavone@retrodev.com> parents: 318 diff changeset	201 uint8_t width = (((context->vdpmem[address+2] >> 2) & 0x3) + 1) * 8;
8e2fa485c0f2 Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview. Mike Pavone <pavone@retrodev.com> parents: 318 diff changeset	202 int16_t y = ((context->vdpmem[address] & 0x3) << 8 \| context->vdpmem[address+1]) & 0x1FF;
323 8c01b4154480 Properly mask sprite X and Y coordinates Mike Pavone <pavone@retrodev.com> parents: 322 diff changeset	203 int16_t x = ((context->vdpmem[address+ 6] & 0x3) << 8 \| context->vdpmem[address + 7]) & 0x1FF;
322 8e2fa485c0f2 Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview. Mike Pavone <pavone@retrodev.com> parents: 318 diff changeset	204 uint16_t link = context->vdpmem[address+3] & 0x7F;
323 8c01b4154480 Properly mask sprite X and Y coordinates Mike Pavone <pavone@retrodev.com> parents: 322 diff changeset	205 uint8_t pal = context->vdpmem[address + 4] >> 5 & 0x3;
8c01b4154480 Properly mask sprite X and Y coordinates Mike Pavone <pavone@retrodev.com> parents: 322 diff changeset	206 uint8_t pri = context->vdpmem[address + 4] >> 7;
450 3758bcdae5de Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty Mike Pavone <pavone@retrodev.com> parents: 438 diff changeset	207 uint16_t pattern = ((context->vdpmem[address + 4] << 8 \| context->vdpmem[address + 5]) & 0x7FF) << 5;
515 1495179d6737 Initial GDB remote debugging support. Lacks some features, but breakpoints and basic inspection of registers and memory work. Mike Pavone <pavone@retrodev.com> parents: 505 diff changeset	208 printf("Sprite %d: X=%d(%d), Y=%d(%d), Width=%u, Height=%u, Link=%u, Pal=%u, Pri=%u, Pat=%X\n", current_index, x, x-128, y, y-128, width, height, link, pal, pri, pattern);
322 8e2fa485c0f2 Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview. Mike Pavone <pavone@retrodev.com> parents: 318 diff changeset	209 current_index = link;
8e2fa485c0f2 Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview. Mike Pavone <pavone@retrodev.com> parents: 318 diff changeset	210 count++;
8e2fa485c0f2 Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview. Mike Pavone <pavone@retrodev.com> parents: 318 diff changeset	211 } while (current_index != 0 && count < 80);
8e2fa485c0f2 Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview. Mike Pavone <pavone@retrodev.com> parents: 318 diff changeset	212 }
8e2fa485c0f2 Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview. Mike Pavone <pavone@retrodev.com> parents: 318 diff changeset	213
705 ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	214 #define VRAM_READ 0 //0000
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	215 #define VRAM_WRITE 1 //0001
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	216 //2 would trigger register write 0010
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	217 #define CRAM_WRITE 3 //0011
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	218 #define VSRAM_READ 4 //0100
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	219 #define VSRAM_WRITE 5//0101
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	220 //6 would trigger regsiter write 0110
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	221 //7 is a mystery
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	222 #define CRAM_READ 8 //1000
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	223 //9 is also a mystery //1001
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	224 //A would trigger register write 1010
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	225 //B is a mystery 1011
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	226 #define VRAM_READ8 0xC //1100
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	227 //D is a mystery 1101
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	228 //E would trigger register write 1110
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	229 //F is a mystery 1111
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	230 #define DMA_START 0x20
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	231
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	232 const char * cd_name(uint8_t cd)
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	233 {
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	234 switch (cd & 0xF)
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	235 {
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	236 case VRAM_READ:
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	237 return "VRAM read";
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	238 case VRAM_WRITE:
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	239 return "VRAM write";
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	240 case CRAM_WRITE:
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	241 return "CRAM write";
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	242 case VSRAM_READ:
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	243 return "VSRAM read";
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	244 case VSRAM_WRITE:
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	245 return "VSRAM write";
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	246 case VRAM_READ8:
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	247 return "VRAM read (undocumented 8-bit mode)";
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	248 default:
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	249 return "invalid";
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	250 }
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	251 }
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	252
327 1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	253 void vdp_print_reg_explain(vdp_context * context)
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	254 {
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	255 char * hscroll[] = {"full", "7-line", "cell", "line"};
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	256 printf("Mode Group\n"
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	257 "00: %.2X \| H-ints %s, Pal Select %d, HVC latch %s, Display gen %s\n"
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	258 "01: %.2X \| Display %s, V-ints %s, Height: %d, Mode %d\n"
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	259 "0B: %.2X \| E-ints %s, V-Scroll: %s, H-Scroll: %s\n"
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	260 "0C: %.2X \| Width: %d, Shadow/Highlight: %s\n",
450 3758bcdae5de Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty Mike Pavone <pavone@retrodev.com> parents: 438 diff changeset	261 context->regs[REG_MODE_1], context->regs[REG_MODE_1] & BIT_HINT_EN ? "enabled" : "disabled", context->regs[REG_MODE_1] & BIT_PAL_SEL != 0,
327 1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	262 context->regs[REG_MODE_1] & BIT_HVC_LATCH ? "enabled" : "disabled", context->regs[REG_MODE_1] & BIT_DISP_DIS ? "disabled" : "enabled",
450 3758bcdae5de Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty Mike Pavone <pavone@retrodev.com> parents: 438 diff changeset	263 context->regs[REG_MODE_2], context->regs[REG_MODE_2] & BIT_DISP_EN ? "enabled" : "disabled", context->regs[REG_MODE_2] & BIT_VINT_EN ? "enabled" : "disabled",
327 1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	264 context->regs[REG_MODE_2] & BIT_PAL ? 30 : 28, context->regs[REG_MODE_2] & BIT_MODE_5 ? 5 : 4,
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	265 context->regs[REG_MODE_3], context->regs[REG_MODE_3] & BIT_EINT_EN ? "enabled" : "disabled", context->regs[REG_MODE_3] & BIT_VSCROLL ? "2 cell" : "full",
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	266 hscroll[context->regs[REG_MODE_3] & 0x3],
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	267 context->regs[REG_MODE_4], context->regs[REG_MODE_4] & BIT_H40 ? 40 : 32, context->regs[REG_MODE_4] & BIT_HILIGHT ? "enabled" : "disabled");
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	268 printf("\nTable Group\n"
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	269 "02: %.2X \| Scroll A Name Table: $%.4X\n"
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	270 "03: %.2X \| Window Name Table: $%.4X\n"
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	271 "04: %.2X \| Scroll B Name Table: $%.4X\n"
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	272 "05: %.2X \| Sprite Attribute Table: $%.4X\n"
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	273 "0D: %.2X \| HScroll Data Table: $%.4X\n",
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	274 context->regs[REG_SCROLL_A], (context->regs[REG_SCROLL_A] & 0x38) << 10,
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	275 context->regs[REG_WINDOW], (context->regs[REG_WINDOW] & (context->regs[REG_MODE_4] & BIT_H40 ? 0x3C : 0x3E)) << 10,
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	276 context->regs[REG_SCROLL_B], (context->regs[REG_SCROLL_B] & 0x7) << 13,
621 5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes. Michael Pavone <pavone@retrodev.com> parents: 515 diff changeset	277 context->regs[REG_SAT], (context->regs[REG_SAT] & (context->regs[REG_MODE_4] & BIT_H40 ? 0x7E : 0x7F)) << 9,
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes. Michael Pavone <pavone@retrodev.com> parents: 515 diff changeset	278 context->regs[REG_HSCROLL], (context->regs[REG_HSCROLL] & 0x3F) << 10);
327 1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	279 char * sizes[] = {"32", "64", "invalid", "128"};
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	280 printf("\nMisc Group\n"
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	281 "07: %.2X \| Backdrop Color: $%X\n"
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	282 "0A: %.2X \| H-Int Counter: %u\n"
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	283 "0F: %.2X \| Auto-increment: $%X\n"
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	284 "10: %.2X \| Scroll A/B Size: %sx%s\n",
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	285 context->regs[REG_BG_COLOR], context->regs[REG_BG_COLOR],
450 3758bcdae5de Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty Mike Pavone <pavone@retrodev.com> parents: 438 diff changeset	286 context->regs[REG_HINT], context->regs[REG_HINT],
327 1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	287 context->regs[REG_AUTOINC], context->regs[REG_AUTOINC],
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	288 context->regs[REG_SCROLL], sizes[context->regs[REG_SCROLL] & 0x3], sizes[context->regs[REG_SCROLL] >> 4 & 0x3]);
621 5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes. Michael Pavone <pavone@retrodev.com> parents: 515 diff changeset	289 char * src_types[] = {"68K", "68K", "Copy", "Fill"};
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes. Michael Pavone <pavone@retrodev.com> parents: 515 diff changeset	290 printf("\nDMA Group\n"
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes. Michael Pavone <pavone@retrodev.com> parents: 515 diff changeset	291 "13: %.2X \|\n"
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes. Michael Pavone <pavone@retrodev.com> parents: 515 diff changeset	292 "14: %.2X \| DMA Length: $%.4X words\n"
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes. Michael Pavone <pavone@retrodev.com> parents: 515 diff changeset	293 "15: %.2X \|\n"
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes. Michael Pavone <pavone@retrodev.com> parents: 515 diff changeset	294 "16: %.2X \|\n"
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes. Michael Pavone <pavone@retrodev.com> parents: 515 diff changeset	295 "17: %.2X \| DMA Source Address: $%.6X, Type: %s\n",
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes. Michael Pavone <pavone@retrodev.com> parents: 515 diff changeset	296 context->regs[REG_DMALEN_L],
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes. Michael Pavone <pavone@retrodev.com> parents: 515 diff changeset	297 context->regs[REG_DMALEN_H], context->regs[REG_DMALEN_H] << 8 \| context->regs[REG_DMALEN_L],
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes. Michael Pavone <pavone@retrodev.com> parents: 515 diff changeset	298 context->regs[REG_DMASRC_L],
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes. Michael Pavone <pavone@retrodev.com> parents: 515 diff changeset	299 context->regs[REG_DMASRC_M],
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes. Michael Pavone <pavone@retrodev.com> parents: 515 diff changeset	300 context->regs[REG_DMASRC_H],
629 9089951a1994 Small fix to display of DMA source address in vr debug command Michael Pavone <pavone@retrodev.com> parents: 624 diff changeset	301 context->regs[REG_DMASRC_H] << 17 \| context->regs[REG_DMASRC_M] << 9 \| context->regs[REG_DMASRC_L] << 1,
621 5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes. Michael Pavone <pavone@retrodev.com> parents: 515 diff changeset	302 src_types[context->regs[REG_DMASRC_H] >> 6 & 3]);
438 b3cee2fe690b Add address/cd registers to VDP debug message Mike Pavone <pavone@retrodev.com> parents: 437 diff changeset	303 printf("\nInternal Group\n"
b3cee2fe690b Add address/cd registers to VDP debug message Mike Pavone <pavone@retrodev.com> parents: 437 diff changeset	304 "Address: %X\n"
705 ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	305 "CD: %X - %s\n"
647 5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events Michael Pavone <pavone@retrodev.com> parents: 629 diff changeset	306 "Pending: %s\n"
5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events Michael Pavone <pavone@retrodev.com> parents: 629 diff changeset	307 "VCounter: %d\n"
5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events Michael Pavone <pavone@retrodev.com> parents: 629 diff changeset	308 "HCounter: %d\n",
705 ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	309 context->address, context->cd, cd_name(context->cd), (context->flags & FLAG_PENDING) ? "true" : "false",
647 5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events Michael Pavone <pavone@retrodev.com> parents: 629 diff changeset	310 context->vcounter, context->hslot*2);
450 3758bcdae5de Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty Mike Pavone <pavone@retrodev.com> parents: 438 diff changeset	311
3758bcdae5de Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty Mike Pavone <pavone@retrodev.com> parents: 438 diff changeset	312 //TODO: Window Group, DMA Group
327 1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	313 }
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	314
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	315 void scan_sprite_table(uint32_t line, vdp_context * context)
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	316 {
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	317 if (context->sprite_index && context->slot_counter) {
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	318 line += 1;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	319 line &= 0xFF;
413 36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	320 uint16_t ymask, ymin;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	321 uint8_t height_mult;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	322 if (context->double_res) {
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	323 line *= 2;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	324 if (context->framebuf != context->oddbuf) {
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	325 line++;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	326 }
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	327 ymask = 0x3FF;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	328 ymin = 256;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	329 height_mult = 16;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	330 } else {
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	331 ymask = 0x1FF;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	332 ymin = 128;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	333 height_mult = 8;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	334 }
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	335 context->sprite_index &= 0x7F;
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	336 if (context->regs[REG_MODE_4] & BIT_H40) {
38 898e3d035f42 Implement sprite index >= sprite limit triggers sprite limit behavior Mike Pavone <pavone@retrodev.com> parents: 37 diff changeset	337 if (context->sprite_index >= MAX_SPRITES_FRAME) {
898e3d035f42 Implement sprite index >= sprite limit triggers sprite limit behavior Mike Pavone <pavone@retrodev.com> parents: 37 diff changeset	338 context->sprite_index = 0;
898e3d035f42 Implement sprite index >= sprite limit triggers sprite limit behavior Mike Pavone <pavone@retrodev.com> parents: 37 diff changeset	339 return;
898e3d035f42 Implement sprite index >= sprite limit triggers sprite limit behavior Mike Pavone <pavone@retrodev.com> parents: 37 diff changeset	340 }
898e3d035f42 Implement sprite index >= sprite limit triggers sprite limit behavior Mike Pavone <pavone@retrodev.com> parents: 37 diff changeset	341 } else if(context->sprite_index >= MAX_SPRITES_FRAME_H32) {
898e3d035f42 Implement sprite index >= sprite limit triggers sprite limit behavior Mike Pavone <pavone@retrodev.com> parents: 37 diff changeset	342 context->sprite_index = 0;
898e3d035f42 Implement sprite index >= sprite limit triggers sprite limit behavior Mike Pavone <pavone@retrodev.com> parents: 37 diff changeset	343 return;
898e3d035f42 Implement sprite index >= sprite limit triggers sprite limit behavior Mike Pavone <pavone@retrodev.com> parents: 37 diff changeset	344 }
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	345 //TODO: Read from SAT cache rather than from VRAM
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	346 uint16_t sat_address = (context->regs[REG_SAT] & 0x7F) << 9;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	347 uint16_t address = context->sprite_index * 8 + sat_address;
413 36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	348 line += ymin;
415 8c60c8c09a0f Fix sprite y mask in interlace mode. Fix framebuffer selection when switching out of interlace mode. Mike Pavone <pavone@retrodev.com> parents: 414 diff changeset	349 uint16_t y = ((context->vdpmem[address] & 0x3) << 8 \| context->vdpmem[address+1]) & ymask;
413 36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	350 uint8_t height = ((context->vdpmem[address+2] & 0x3) + 1) * height_mult;
21 72ce60cb1711 Sprites somewhat less broken Mike Pavone <pavone@retrodev.com> parents: 20 diff changeset	351 //printf("Sprite %d \| y: %d, height: %d\n", context->sprite_index, y, height);
72ce60cb1711 Sprites somewhat less broken Mike Pavone <pavone@retrodev.com> parents: 20 diff changeset	352 if (y <= line && line < (y + height)) {
27 aa1c47fab3f1 Fix sprite transparency for overlapping sprites Mike Pavone <pavone@retrodev.com> parents: 26 diff changeset	353 //printf("Sprite %d at y: %d with height %d is on line %d\n", context->sprite_index, y, height, line);
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	354 context->sprite_info_list[--(context->slot_counter)].size = context->vdpmem[address+2];
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	355 context->sprite_info_list[context->slot_counter].index = context->sprite_index;
413 36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	356 context->sprite_info_list[context->slot_counter].y = y-ymin;
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	357 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	358 context->sprite_index = context->vdpmem[address+3] & 0x7F;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	359 if (context->sprite_index && context->slot_counter)
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	360 {
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	361 address = context->sprite_index * 8 + sat_address;
415 8c60c8c09a0f Fix sprite y mask in interlace mode. Fix framebuffer selection when switching out of interlace mode. Mike Pavone <pavone@retrodev.com> parents: 414 diff changeset	362 y = ((context->vdpmem[address] & 0x3) << 8 \| context->vdpmem[address+1]) & ymask;
413 36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	363 height = ((context->vdpmem[address+2] & 0x3) + 1) * height_mult;
323 8c01b4154480 Properly mask sprite X and Y coordinates Mike Pavone <pavone@retrodev.com> parents: 322 diff changeset	364 //printf("Sprite %d \| y: %d, height: %d\n", context->sprite_index, y, height);
21 72ce60cb1711 Sprites somewhat less broken Mike Pavone <pavone@retrodev.com> parents: 20 diff changeset	365 if (y <= line && line < (y + height)) {
27 aa1c47fab3f1 Fix sprite transparency for overlapping sprites Mike Pavone <pavone@retrodev.com> parents: 26 diff changeset	366 //printf("Sprite %d at y: %d with height %d is on line %d\n", context->sprite_index, y, height, line);
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	367 context->sprite_info_list[--(context->slot_counter)].size = context->vdpmem[address+2];
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	368 context->sprite_info_list[context->slot_counter].index = context->sprite_index;
413 36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	369 context->sprite_info_list[context->slot_counter].y = y-ymin;
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	370 }
21 72ce60cb1711 Sprites somewhat less broken Mike Pavone <pavone@retrodev.com> parents: 20 diff changeset	371 context->sprite_index = context->vdpmem[address+3] & 0x7F;
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	372 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	373 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	374 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	375
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	376 void read_sprite_x(uint32_t line, vdp_context * context)
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	377 {
34 0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	378 if (context->cur_slot >= context->slot_counter) {
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	379 if (context->sprite_draws) {
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	380 line += 1;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	381 line &= 0xFF;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	382 //in tiles
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	383 uint8_t width = ((context->sprite_info_list[context->cur_slot].size >> 2) & 0x3) + 1;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	384 //in pixels
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	385 uint8_t height = ((context->sprite_info_list[context->cur_slot].size & 0x3) + 1) * 8;
413 36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	386 if (context->double_res) {
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	387 line *= 2;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	388 if (context->framebuf != context->oddbuf) {
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	389 line++;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	390 }
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	391 height *= 2;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	392 }
34 0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	393 uint16_t att_addr = ((context->regs[REG_SAT] & 0x7F) << 9) + context->sprite_info_list[context->cur_slot].index * 8 + 4;
450 3758bcdae5de Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty Mike Pavone <pavone@retrodev.com> parents: 438 diff changeset	394 uint16_t tileinfo = (context->vdpmem[att_addr] << 8) \| context->vdpmem[att_addr+1];
34 0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	395 uint8_t pal_priority = (tileinfo >> 9) & 0x70;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	396 uint8_t row;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	397 if (tileinfo & MAP_BIT_V_FLIP) {
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	398 row = (context->sprite_info_list[context->cur_slot].y + height - 1) - line;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	399 } else {
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	400 row = line-context->sprite_info_list[context->cur_slot].y;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	401 }
413 36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	402 uint16_t address;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	403 if (context->double_res) {
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	404 address = ((tileinfo & 0x3FF) << 6) + row * 4;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	405 } else {
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	406 address = ((tileinfo & 0x7FF) << 5) + row * 4;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	407 }
323 8c01b4154480 Properly mask sprite X and Y coordinates Mike Pavone <pavone@retrodev.com> parents: 322 diff changeset	408 int16_t x = ((context->vdpmem[att_addr+ 2] & 0x3) << 8 \| context->vdpmem[att_addr + 3]) & 0x1FF;
36 04672c060062 Pass all sprite masking tests Mike Pavone <pavone@retrodev.com> parents: 35 diff changeset	409 if (x) {
04672c060062 Pass all sprite masking tests Mike Pavone <pavone@retrodev.com> parents: 35 diff changeset	410 context->flags \|= FLAG_CAN_MASK;
04672c060062 Pass all sprite masking tests Mike Pavone <pavone@retrodev.com> parents: 35 diff changeset	411 } else if(context->flags & (FLAG_CAN_MASK \| FLAG_DOT_OFLOW)) {
04672c060062 Pass all sprite masking tests Mike Pavone <pavone@retrodev.com> parents: 35 diff changeset	412 context->flags \|= FLAG_MASKED;
04672c060062 Pass all sprite masking tests Mike Pavone <pavone@retrodev.com> parents: 35 diff changeset	413 }
450 3758bcdae5de Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty Mike Pavone <pavone@retrodev.com> parents: 438 diff changeset	414
36 04672c060062 Pass all sprite masking tests Mike Pavone <pavone@retrodev.com> parents: 35 diff changeset	415 context->flags &= ~FLAG_DOT_OFLOW;
04672c060062 Pass all sprite masking tests Mike Pavone <pavone@retrodev.com> parents: 35 diff changeset	416 int16_t i;
04672c060062 Pass all sprite masking tests Mike Pavone <pavone@retrodev.com> parents: 35 diff changeset	417 if (context->flags & FLAG_MASKED) {
04672c060062 Pass all sprite masking tests Mike Pavone <pavone@retrodev.com> parents: 35 diff changeset	418 for (i=0; i < width && context->sprite_draws; i++) {
04672c060062 Pass all sprite masking tests Mike Pavone <pavone@retrodev.com> parents: 35 diff changeset	419 --context->sprite_draws;
04672c060062 Pass all sprite masking tests Mike Pavone <pavone@retrodev.com> parents: 35 diff changeset	420 context->sprite_draw_list[context->sprite_draws].x_pos = -128;
34 0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	421 }
36 04672c060062 Pass all sprite masking tests Mike Pavone <pavone@retrodev.com> parents: 35 diff changeset	422 } else {
34 0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	423 x -= 128;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	424 int16_t base_x = x;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	425 int16_t dir;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	426 if (tileinfo & MAP_BIT_H_FLIP) {
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	427 x += (width-1) * 8;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	428 dir = -8;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	429 } else {
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	430 dir = 8;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	431 }
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	432 //printf("Sprite %d \| x: %d, y: %d, width: %d, height: %d, pal_priority: %X, row: %d, tile addr: %X\n", context->sprite_info_list[context->cur_slot].index, x, context->sprite_info_list[context->cur_slot].y, width, height, pal_priority, row, address);
35 233c7737c152 Small fix to overflow flag Mike Pavone <pavone@retrodev.com> parents: 34 diff changeset	433 for (i=0; i < width && context->sprite_draws; i++, x += dir) {
34 0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	434 --context->sprite_draws;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	435 context->sprite_draw_list[context->sprite_draws].address = address + i * height * 4;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	436 context->sprite_draw_list[context->sprite_draws].x_pos = x;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	437 context->sprite_draw_list[context->sprite_draws].pal_priority = pal_priority;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	438 context->sprite_draw_list[context->sprite_draws].h_flip = (tileinfo & MAP_BIT_H_FLIP) ? 1 : 0;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	439 }
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	440 }
36 04672c060062 Pass all sprite masking tests Mike Pavone <pavone@retrodev.com> parents: 35 diff changeset	441 if (i < width) {
04672c060062 Pass all sprite masking tests Mike Pavone <pavone@retrodev.com> parents: 35 diff changeset	442 context->flags \|= FLAG_DOT_OFLOW;
04672c060062 Pass all sprite masking tests Mike Pavone <pavone@retrodev.com> parents: 35 diff changeset	443 }
04672c060062 Pass all sprite masking tests Mike Pavone <pavone@retrodev.com> parents: 35 diff changeset	444 context->cur_slot--;
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	445 } else {
34 0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	446 context->flags \|= FLAG_DOT_OFLOW;
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	447 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	448 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	449 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	450
427 2802318c14e1 Refactor duplicated CRAM writing code and fix a bug in the process Mike Pavone <pavone@retrodev.com> parents: 426 diff changeset	451 void write_cram(vdp_context * context, uint16_t address, uint16_t value)
2802318c14e1 Refactor duplicated CRAM writing code and fix a bug in the process Mike Pavone <pavone@retrodev.com> parents: 426 diff changeset	452 {
2802318c14e1 Refactor duplicated CRAM writing code and fix a bug in the process Mike Pavone <pavone@retrodev.com> parents: 426 diff changeset	453 uint16_t addr = (address/2) & (CRAM_SIZE-1);
2802318c14e1 Refactor duplicated CRAM writing code and fix a bug in the process Mike Pavone <pavone@retrodev.com> parents: 426 diff changeset	454 context->cram[addr] = value;
2802318c14e1 Refactor duplicated CRAM writing code and fix a bug in the process Mike Pavone <pavone@retrodev.com> parents: 426 diff changeset	455 context->colors[addr] = color_map[value & 0xEEE];
2802318c14e1 Refactor duplicated CRAM writing code and fix a bug in the process Mike Pavone <pavone@retrodev.com> parents: 426 diff changeset	456 context->colors[addr + CRAM_SIZE] = color_map[(value & 0xEEE) \| FBUF_SHADOW];
2802318c14e1 Refactor duplicated CRAM writing code and fix a bug in the process Mike Pavone <pavone@retrodev.com> parents: 426 diff changeset	457 context->colors[addr + CRAM_SIZE*2] = color_map[(value & 0xEEE) \| FBUF_HILIGHT];
2802318c14e1 Refactor duplicated CRAM writing code and fix a bug in the process Mike Pavone <pavone@retrodev.com> parents: 426 diff changeset	458 }
2802318c14e1 Refactor duplicated CRAM writing code and fix a bug in the process Mike Pavone <pavone@retrodev.com> parents: 426 diff changeset	459
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	460 void external_slot(vdp_context * context)
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	461 {
471 f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	462 fifo_entry * start = context->fifo + context->fifo_read;
474 e128e55710bd Remove read pending stuff, that had been added in an attempt to fix CRAM/VSRAM undefined bit results. Set number of bits actually saved in VSRAM to 11 Mike Pavone <pavone@retrodev.com> parents: 473 diff changeset	463 /*if (context->flags2 & FLAG2_READ_PENDING) {
470 541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM. Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	464 context->flags2 &= ~FLAG2_READ_PENDING;
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM. Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	465 context->flags \|= FLAG_UNUSED_SLOT;
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM. Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	466 return;
474 e128e55710bd Remove read pending stuff, that had been added in an attempt to fix CRAM/VSRAM undefined bit results. Set number of bits actually saved in VSRAM to 11 Mike Pavone <pavone@retrodev.com> parents: 473 diff changeset	467 }*/
471 f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	468 if (context->fifo_read >= 0 && start->cycle <= context->cycles) {
460 788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	469 switch (start->cd & 0xF)
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	470 {
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	471 case VRAM_WRITE:
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	472 if (start->partial) {
471 f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	473 //printf("VRAM Write: %X to %X at %d (line %d, slot %d)\n", start->value, start->address ^ 1, context->cycles, context->cycles/MCLKS_LINE, (context->cycles%MCLKS_LINE)/16);
478 2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all. Mike Pavone <pavone@retrodev.com> parents: 477 diff changeset	474 context->vdpmem[start->address ^ 1] = start->partial == 2 ? start->value >> 8 : start->value;
460 788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	475 } else {
471 f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	476 //printf("VRAM Write High: %X to %X at %d (line %d, slot %d)\n", start->value >> 8, start->address, context->cycles, context->cycles/MCLKS_LINE, (context->cycles%MCLKS_LINE)/16);
460 788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	477 context->vdpmem[start->address] = start->value >> 8;
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	478 start->partial = 1;
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	479 //skip auto-increment and removal of entry from fifo
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	480 return;
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	481 }
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	482 break;
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	483 case CRAM_WRITE: {
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	484 //printf("CRAM Write \| %X to %X\n", start->value, (start->address/2) & (CRAM_SIZE-1));
479 863e868752cf Implement funny behavior for DMA fill to CRAM and VSRAM. Return VSRAM address 0 for reads to VSRAM at >= 40 Mike Pavone <pavone@retrodev.com> parents: 478 diff changeset	485 write_cram(context, start->address, start->partial == 2 ? context->fifo[context->fifo_write].value : start->value);
460 788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	486 break;
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	487 }
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	488 case VSRAM_WRITE:
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	489 if (((start->address/2) & 63) < VSRAM_SIZE) {
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	490 //printf("VSRAM Write: %X to %X\n", start->value, context->address);
479 863e868752cf Implement funny behavior for DMA fill to CRAM and VSRAM. Return VSRAM address 0 for reads to VSRAM at >= 40 Mike Pavone <pavone@retrodev.com> parents: 478 diff changeset	491 context->vsram[(start->address/2) & 63] = start->partial == 2 ? context->fifo[context->fifo_write].value : start->value;
460 788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	492 }
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	493
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	494 break;
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	495 }
471 f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	496 context->fifo_read = (context->fifo_read+1) & (FIFO_SIZE-1);
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	497 if (context->fifo_read == context->fifo_write) {
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	498 context->fifo_read = -1;
460 788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	499 }
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	500 } else {
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	501 context->flags \|= FLAG_UNUSED_SLOT;
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	502 }
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	503 }
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	504
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	505 void run_dma_src(vdp_context * context, uint32_t slot)
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	506 {
75 108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	507 //TODO: Figure out what happens if CD bit 4 is not set in DMA copy mode
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	508 //TODO: Figure out what happens when CD:0-3 is not set to a write mode in DMA operations
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	509 //TODO: Figure out what happens if DMA gets disabled part way through a DMA fill or DMA copy
471 f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	510 if (context->fifo_write == context->fifo_read) {
460 788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	511 return;
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	512 }
478 2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all. Mike Pavone <pavone@retrodev.com> parents: 477 diff changeset	513 fifo_entry * cur = NULL;
460 788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	514 switch(context->regs[REG_DMASRC_H] & 0xC0)
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	515 {
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	516 //68K -> VDP
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	517 case 0:
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	518 case 0x40:
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	519 if (!slot \|\| !is_refresh(context, slot-1)) {
478 2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all. Mike Pavone <pavone@retrodev.com> parents: 477 diff changeset	520 cur = context->fifo + context->fifo_write;
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	521 cur->cycle = context->cycles + ((context->regs[REG_MODE_4] & BIT_H40) ? 16 : 20)*FIFO_LATENCY;
478 2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all. Mike Pavone <pavone@retrodev.com> parents: 477 diff changeset	522 cur->address = context->address;
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all. Mike Pavone <pavone@retrodev.com> parents: 477 diff changeset	523 cur->value = read_dma_value((context->regs[REG_DMASRC_H] << 16) \| (context->regs[REG_DMASRC_M] << 8) \| context->regs[REG_DMASRC_L]);
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all. Mike Pavone <pavone@retrodev.com> parents: 477 diff changeset	524 cur->cd = context->cd;
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all. Mike Pavone <pavone@retrodev.com> parents: 477 diff changeset	525 cur->partial = 0;
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all. Mike Pavone <pavone@retrodev.com> parents: 477 diff changeset	526 if (context->fifo_read < 0) {
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all. Mike Pavone <pavone@retrodev.com> parents: 477 diff changeset	527 context->fifo_read = context->fifo_write;
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all. Mike Pavone <pavone@retrodev.com> parents: 477 diff changeset	528 }
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all. Mike Pavone <pavone@retrodev.com> parents: 477 diff changeset	529 context->fifo_write = (context->fifo_write + 1) & (FIFO_SIZE-1);
460 788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	530 }
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	531 break;
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	532 //Copy
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	533 case 0xC0:
478 2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all. Mike Pavone <pavone@retrodev.com> parents: 477 diff changeset	534 if (context->flags & FLAG_UNUSED_SLOT && context->fifo_read < 0) {
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all. Mike Pavone <pavone@retrodev.com> parents: 477 diff changeset	535 //TODO: Fix this to not use the FIFO at all once read-caching is properly implemented
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all. Mike Pavone <pavone@retrodev.com> parents: 477 diff changeset	536 context->fifo_read = (context->fifo_write-1) & (FIFO_SIZE-1);
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all. Mike Pavone <pavone@retrodev.com> parents: 477 diff changeset	537 cur = context->fifo + context->fifo_read;
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all. Mike Pavone <pavone@retrodev.com> parents: 477 diff changeset	538 cur->cycle = context->cycles;
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all. Mike Pavone <pavone@retrodev.com> parents: 477 diff changeset	539 cur->address = context->address;
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all. Mike Pavone <pavone@retrodev.com> parents: 477 diff changeset	540 cur->partial = 1;
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all. Mike Pavone <pavone@retrodev.com> parents: 477 diff changeset	541 cur->value = context->vdpmem[(context->regs[REG_DMASRC_M] << 8) \| context->regs[REG_DMASRC_L] ^ 1] \| (cur->value & 0xFF00);
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all. Mike Pavone <pavone@retrodev.com> parents: 477 diff changeset	542 cur->cd = VRAM_WRITE;
460 788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	543 context->flags &= ~FLAG_UNUSED_SLOT;
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	544 }
460 788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	545 break;
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	546 case 0x80:
478 2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all. Mike Pavone <pavone@retrodev.com> parents: 477 diff changeset	547 if (context->fifo_read < 0) {
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all. Mike Pavone <pavone@retrodev.com> parents: 477 diff changeset	548 context->fifo_read = (context->fifo_write-1) & (FIFO_SIZE-1);
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all. Mike Pavone <pavone@retrodev.com> parents: 477 diff changeset	549 cur = context->fifo + context->fifo_read;
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all. Mike Pavone <pavone@retrodev.com> parents: 477 diff changeset	550 cur->cycle = context->cycles;
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all. Mike Pavone <pavone@retrodev.com> parents: 477 diff changeset	551 cur->address = context->address;
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all. Mike Pavone <pavone@retrodev.com> parents: 477 diff changeset	552 cur->partial = 2;
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all. Mike Pavone <pavone@retrodev.com> parents: 477 diff changeset	553 }
460 788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	554 break;
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	555 }
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	556
478 2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all. Mike Pavone <pavone@retrodev.com> parents: 477 diff changeset	557 if (cur) {
460 788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	558 context->regs[REG_DMASRC_L] += 1;
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	559 if (!context->regs[REG_DMASRC_L]) {
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	560 context->regs[REG_DMASRC_M] += 1;
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	561 }
460 788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	562 context->address += context->regs[REG_AUTOINC];
478 2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all. Mike Pavone <pavone@retrodev.com> parents: 477 diff changeset	563 uint16_t dma_len = ((context->regs[REG_DMALEN_H] << 8) \| context->regs[REG_DMALEN_L]) - 1;
460 788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	564 context->regs[REG_DMALEN_H] = dma_len >> 8;
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	565 context->regs[REG_DMALEN_L] = dma_len;
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	566 if (!dma_len) {
717 22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	567 //printf("DMA end at cycle %d, frame: %d, vcounter: %d, hslot: %d\n", context->cycles, context->frame, context->vcounter, context->hslot);
460 788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	568 context->flags &= ~FLAG_DMA_RUN;
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	569 context->cd &= 0xF;
75 108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	570 }
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	571 }
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	572 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	573
40 7368a7071908 Broken window support Mike Pavone <pavone@retrodev.com> parents: 39 diff changeset	574 #define WINDOW_RIGHT 0x80
7368a7071908 Broken window support Mike Pavone <pavone@retrodev.com> parents: 39 diff changeset	575 #define WINDOW_DOWN 0x80
7368a7071908 Broken window support Mike Pavone <pavone@retrodev.com> parents: 39 diff changeset	576
25 4d0c20ad815a Fix vertical scroll value for plane B Mike Pavone <pavone@retrodev.com> parents: 24 diff changeset	577 void read_map_scroll(uint16_t column, uint16_t vsram_off, uint32_t line, uint16_t address, uint16_t hscroll_val, vdp_context * context)
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	578 {
417 acdd6c5240fe Fix window layer in double res interlace mode Mike Pavone <pavone@retrodev.com> parents: 415 diff changeset	579 uint16_t window_line_shift, v_offset_mask, vscroll_shift;
414 51ee0f117365 Fix vscroll calculation in double resultion interlace mode Mike Pavone <pavone@retrodev.com> parents: 413 diff changeset	580 if (context->double_res) {
413 36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	581 line *= 2;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	582 if (context->framebuf != context->oddbuf) {
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	583 line++;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	584 }
417 acdd6c5240fe Fix window layer in double res interlace mode Mike Pavone <pavone@retrodev.com> parents: 415 diff changeset	585 window_line_shift = 4;
acdd6c5240fe Fix window layer in double res interlace mode Mike Pavone <pavone@retrodev.com> parents: 415 diff changeset	586 v_offset_mask = 0xF;
acdd6c5240fe Fix window layer in double res interlace mode Mike Pavone <pavone@retrodev.com> parents: 415 diff changeset	587 vscroll_shift = 4;
acdd6c5240fe Fix window layer in double res interlace mode Mike Pavone <pavone@retrodev.com> parents: 415 diff changeset	588 } else {
acdd6c5240fe Fix window layer in double res interlace mode Mike Pavone <pavone@retrodev.com> parents: 415 diff changeset	589 window_line_shift = 3;
acdd6c5240fe Fix window layer in double res interlace mode Mike Pavone <pavone@retrodev.com> parents: 415 diff changeset	590 v_offset_mask = 0x7;
acdd6c5240fe Fix window layer in double res interlace mode Mike Pavone <pavone@retrodev.com> parents: 415 diff changeset	591 vscroll_shift = 3;
414 51ee0f117365 Fix vscroll calculation in double resultion interlace mode Mike Pavone <pavone@retrodev.com> parents: 413 diff changeset	592 }
40 7368a7071908 Broken window support Mike Pavone <pavone@retrodev.com> parents: 39 diff changeset	593 if (!vsram_off) {
7368a7071908 Broken window support Mike Pavone <pavone@retrodev.com> parents: 39 diff changeset	594 uint16_t left_col, right_col;
7368a7071908 Broken window support Mike Pavone <pavone@retrodev.com> parents: 39 diff changeset	595 if (context->regs[REG_WINDOW_H] & WINDOW_RIGHT) {
41 e591004487bc More correct window support, maybe Mike Pavone <pavone@retrodev.com> parents: 40 diff changeset	596 left_col = (context->regs[REG_WINDOW_H] & 0x1F) * 2;
e591004487bc More correct window support, maybe Mike Pavone <pavone@retrodev.com> parents: 40 diff changeset	597 right_col = 42;
e591004487bc More correct window support, maybe Mike Pavone <pavone@retrodev.com> parents: 40 diff changeset	598 } else {
40 7368a7071908 Broken window support Mike Pavone <pavone@retrodev.com> parents: 39 diff changeset	599 left_col = 0;
7368a7071908 Broken window support Mike Pavone <pavone@retrodev.com> parents: 39 diff changeset	600 right_col = (context->regs[REG_WINDOW_H] & 0x1F) * 2;
7368a7071908 Broken window support Mike Pavone <pavone@retrodev.com> parents: 39 diff changeset	601 if (right_col) {
7368a7071908 Broken window support Mike Pavone <pavone@retrodev.com> parents: 39 diff changeset	602 right_col += 2;
7368a7071908 Broken window support Mike Pavone <pavone@retrodev.com> parents: 39 diff changeset	603 }
7368a7071908 Broken window support Mike Pavone <pavone@retrodev.com> parents: 39 diff changeset	604 }
41 e591004487bc More correct window support, maybe Mike Pavone <pavone@retrodev.com> parents: 40 diff changeset	605 uint16_t top_line, bottom_line;
e591004487bc More correct window support, maybe Mike Pavone <pavone@retrodev.com> parents: 40 diff changeset	606 if (context->regs[REG_WINDOW_V] & WINDOW_DOWN) {
417 acdd6c5240fe Fix window layer in double res interlace mode Mike Pavone <pavone@retrodev.com> parents: 415 diff changeset	607 top_line = (context->regs[REG_WINDOW_V] & 0x1F) << window_line_shift;
acdd6c5240fe Fix window layer in double res interlace mode Mike Pavone <pavone@retrodev.com> parents: 415 diff changeset	608 bottom_line = context->double_res ? 481 : 241;
41 e591004487bc More correct window support, maybe Mike Pavone <pavone@retrodev.com> parents: 40 diff changeset	609 } else {
e591004487bc More correct window support, maybe Mike Pavone <pavone@retrodev.com> parents: 40 diff changeset	610 top_line = 0;
417 acdd6c5240fe Fix window layer in double res interlace mode Mike Pavone <pavone@retrodev.com> parents: 415 diff changeset	611 bottom_line = (context->regs[REG_WINDOW_V] & 0x1F) << window_line_shift;
41 e591004487bc More correct window support, maybe Mike Pavone <pavone@retrodev.com> parents: 40 diff changeset	612 }
e591004487bc More correct window support, maybe Mike Pavone <pavone@retrodev.com> parents: 40 diff changeset	613 if ((column >= left_col && column < right_col) \|\| (line >= top_line && line < bottom_line)) {
e591004487bc More correct window support, maybe Mike Pavone <pavone@retrodev.com> parents: 40 diff changeset	614 uint16_t address = context->regs[REG_WINDOW] << 10;
e591004487bc More correct window support, maybe Mike Pavone <pavone@retrodev.com> parents: 40 diff changeset	615 uint16_t line_offset, offset, mask;
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	616 if (context->regs[REG_MODE_4] & BIT_H40) {
41 e591004487bc More correct window support, maybe Mike Pavone <pavone@retrodev.com> parents: 40 diff changeset	617 address &= 0xF000;
417 acdd6c5240fe Fix window layer in double res interlace mode Mike Pavone <pavone@retrodev.com> parents: 415 diff changeset	618 line_offset = (((line) >> vscroll_shift) * 64 * 2) & 0xFFF;
41 e591004487bc More correct window support, maybe Mike Pavone <pavone@retrodev.com> parents: 40 diff changeset	619 mask = 0x7F;
450 3758bcdae5de Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty Mike Pavone <pavone@retrodev.com> parents: 438 diff changeset	620
41 e591004487bc More correct window support, maybe Mike Pavone <pavone@retrodev.com> parents: 40 diff changeset	621 } else {
e591004487bc More correct window support, maybe Mike Pavone <pavone@retrodev.com> parents: 40 diff changeset	622 address &= 0xF800;
417 acdd6c5240fe Fix window layer in double res interlace mode Mike Pavone <pavone@retrodev.com> parents: 415 diff changeset	623 line_offset = (((line) >> vscroll_shift) * 32 * 2) & 0xFFF;
41 e591004487bc More correct window support, maybe Mike Pavone <pavone@retrodev.com> parents: 40 diff changeset	624 mask = 0x3F;
e591004487bc More correct window support, maybe Mike Pavone <pavone@retrodev.com> parents: 40 diff changeset	625 }
417 acdd6c5240fe Fix window layer in double res interlace mode Mike Pavone <pavone@retrodev.com> parents: 415 diff changeset	626 if (context->double_res) {
acdd6c5240fe Fix window layer in double res interlace mode Mike Pavone <pavone@retrodev.com> parents: 415 diff changeset	627 mask <<= 1;
acdd6c5240fe Fix window layer in double res interlace mode Mike Pavone <pavone@retrodev.com> parents: 415 diff changeset	628 mask \|= 1;
acdd6c5240fe Fix window layer in double res interlace mode Mike Pavone <pavone@retrodev.com> parents: 415 diff changeset	629 }
42 6653e67a6811 Fix bug in tile address masking. Remove some debug code from window plane. Mike Pavone <pavone@retrodev.com> parents: 41 diff changeset	630 offset = address + line_offset + (((column - 2) * 2) & mask);
41 e591004487bc More correct window support, maybe Mike Pavone <pavone@retrodev.com> parents: 40 diff changeset	631 context->col_1 = (context->vdpmem[offset] << 8) \| context->vdpmem[offset+1];
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	632 //printf("Window \| top: %d, bot: %d, left: %d, right: %d, base: %X, line: %X offset: %X, tile: %X, reg: %X\n", top_line, bottom_line, left_col, right_col, address, line_offset, offset, ((context->col_1 & 0x3FF) << 5), context->regs[REG_WINDOW]);
42 6653e67a6811 Fix bug in tile address masking. Remove some debug code from window plane. Mike Pavone <pavone@retrodev.com> parents: 41 diff changeset	633 offset = address + line_offset + (((column - 1) * 2) & mask);
41 e591004487bc More correct window support, maybe Mike Pavone <pavone@retrodev.com> parents: 40 diff changeset	634 context->col_2 = (context->vdpmem[offset] << 8) \| context->vdpmem[offset+1];
417 acdd6c5240fe Fix window layer in double res interlace mode Mike Pavone <pavone@retrodev.com> parents: 415 diff changeset	635 context->v_offset = (line) & v_offset_mask;
41 e591004487bc More correct window support, maybe Mike Pavone <pavone@retrodev.com> parents: 40 diff changeset	636 context->flags \|= FLAG_WINDOW;
e591004487bc More correct window support, maybe Mike Pavone <pavone@retrodev.com> parents: 40 diff changeset	637 return;
40 7368a7071908 Broken window support Mike Pavone <pavone@retrodev.com> parents: 39 diff changeset	638 }
7368a7071908 Broken window support Mike Pavone <pavone@retrodev.com> parents: 39 diff changeset	639 context->flags &= ~FLAG_WINDOW;
7368a7071908 Broken window support Mike Pavone <pavone@retrodev.com> parents: 39 diff changeset	640 }
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	641 uint16_t vscroll;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	642 switch(context->regs[REG_SCROLL] & 0x30)
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	643 {
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	644 case 0:
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	645 vscroll = 0xFF;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	646 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	647 case 0x10:
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	648 vscroll = 0x1FF;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	649 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	650 case 0x20:
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	651 //TODO: Verify this behavior
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	652 vscroll = 0;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	653 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	654 case 0x30:
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	655 vscroll = 0x3FF;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	656 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	657 }
414 51ee0f117365 Fix vscroll calculation in double resultion interlace mode Mike Pavone <pavone@retrodev.com> parents: 413 diff changeset	658 if (context->double_res) {
413 36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	659 vscroll <<= 1;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	660 vscroll \|= 1;
414 51ee0f117365 Fix vscroll calculation in double resultion interlace mode Mike Pavone <pavone@retrodev.com> parents: 413 diff changeset	661 }
710 4cd8823f79e3 First pass at emulating a vscroll latch. Titan's Overdrive demo seems to depend on the scroll value being latched early in the line before the HINT gets a chance to change it Michael Pavone <pavone@retrodev.com> parents: 708 diff changeset	662 //TODO: Further research on vscroll latch behavior and the "first column bug" seen in Gynoug
4cd8823f79e3 First pass at emulating a vscroll latch. Titan's Overdrive demo seems to depend on the scroll value being latched early in the line before the HINT gets a chance to change it Michael Pavone <pavone@retrodev.com> parents: 708 diff changeset	663 //this should be close, but won't match the exact behavior Eke-Eke has written about
4cd8823f79e3 First pass at emulating a vscroll latch. Titan's Overdrive demo seems to depend on the scroll value being latched early in the line before the HINT gets a chance to change it Michael Pavone <pavone@retrodev.com> parents: 708 diff changeset	664 if (column == 2 \|\| (column && (context->regs[REG_MODE_3] & BIT_VSCROLL))) {
4cd8823f79e3 First pass at emulating a vscroll latch. Titan's Overdrive demo seems to depend on the scroll value being latched early in the line before the HINT gets a chance to change it Michael Pavone <pavone@retrodev.com> parents: 708 diff changeset	665 context->vscroll_latch[vsram_off] = context->vsram[column - 2 + vsram_off];
4cd8823f79e3 First pass at emulating a vscroll latch. Titan's Overdrive demo seems to depend on the scroll value being latched early in the line before the HINT gets a chance to change it Michael Pavone <pavone@retrodev.com> parents: 708 diff changeset	666 }
4cd8823f79e3 First pass at emulating a vscroll latch. Titan's Overdrive demo seems to depend on the scroll value being latched early in the line before the HINT gets a chance to change it Michael Pavone <pavone@retrodev.com> parents: 708 diff changeset	667 vscroll &= context->vscroll_latch[vsram_off] + line;
414 51ee0f117365 Fix vscroll calculation in double resultion interlace mode Mike Pavone <pavone@retrodev.com> parents: 413 diff changeset	668 context->v_offset = vscroll & v_offset_mask;
26 a7c2b92d8056 Fix management of context->sprite_draws so the sprite layer only draws when it should Mike Pavone <pavone@retrodev.com> parents: 25 diff changeset	669 //printf("%s \| line %d, vsram: %d, vscroll: %d, v_offset: %d\n",(vsram_off ? "B" : "A"), line, context->vsram[context->regs[REG_MODE_3] & 0x4 ? column : 0], vscroll, context->v_offset);
414 51ee0f117365 Fix vscroll calculation in double resultion interlace mode Mike Pavone <pavone@retrodev.com> parents: 413 diff changeset	670 vscroll >>= vscroll_shift;
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	671 uint16_t hscroll_mask;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	672 uint16_t v_mul;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	673 switch(context->regs[REG_SCROLL] & 0x3)
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	674 {
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	675 case 0:
108 1a551a85cb06 Fix horizontal mask values for scroll plane map address calculation Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	676 hscroll_mask = 0x1F;
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	677 v_mul = 64;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	678 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	679 case 0x1:
39 3c69319269ef Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should Mike Pavone <pavone@retrodev.com> parents: 38 diff changeset	680 hscroll_mask = 0x3F;
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	681 v_mul = 128;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	682 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	683 case 0x2:
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	684 //TODO: Verify this behavior
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	685 hscroll_mask = 0;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	686 v_mul = 0;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	687 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	688 case 0x3:
108 1a551a85cb06 Fix horizontal mask values for scroll plane map address calculation Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	689 hscroll_mask = 0x7F;
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	690 v_mul = 256;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	691 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	692 }
28 037963b4c92d Fix BG plane B render bug Mike Pavone <pavone@retrodev.com> parents: 27 diff changeset	693 uint16_t hscroll, offset;
037963b4c92d Fix BG plane B render bug Mike Pavone <pavone@retrodev.com> parents: 27 diff changeset	694 for (int i = 0; i < 2; i++) {
39 3c69319269ef Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should Mike Pavone <pavone@retrodev.com> parents: 38 diff changeset	695 hscroll = (column - 2 + i - ((hscroll_val/8) & 0xFFFE)) & hscroll_mask;
3c69319269ef Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should Mike Pavone <pavone@retrodev.com> parents: 38 diff changeset	696 offset = address + ((vscroll * v_mul + hscroll*2) & 0x1FFF);
3c69319269ef Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should Mike Pavone <pavone@retrodev.com> parents: 38 diff changeset	697 //printf("%s \| line: %d, col: %d, x: %d, hs_mask %X, scr reg: %X, tbl addr: %X\n", (vsram_off ? "B" : "A"), line, (column-2+i), hscroll, hscroll_mask, context->regs[REG_SCROLL], offset);
28 037963b4c92d Fix BG plane B render bug Mike Pavone <pavone@retrodev.com> parents: 27 diff changeset	698 uint16_t col_val = (context->vdpmem[offset] << 8) \| context->vdpmem[offset+1];
037963b4c92d Fix BG plane B render bug Mike Pavone <pavone@retrodev.com> parents: 27 diff changeset	699 if (i) {
037963b4c92d Fix BG plane B render bug Mike Pavone <pavone@retrodev.com> parents: 27 diff changeset	700 context->col_2 = col_val;
037963b4c92d Fix BG plane B render bug Mike Pavone <pavone@retrodev.com> parents: 27 diff changeset	701 } else {
037963b4c92d Fix BG plane B render bug Mike Pavone <pavone@retrodev.com> parents: 27 diff changeset	702 context->col_1 = col_val;
037963b4c92d Fix BG plane B render bug Mike Pavone <pavone@retrodev.com> parents: 27 diff changeset	703 }
037963b4c92d Fix BG plane B render bug Mike Pavone <pavone@retrodev.com> parents: 27 diff changeset	704 }
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	705 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	706
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	707 void read_map_scroll_a(uint16_t column, uint32_t line, vdp_context * context)
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	708 {
25 4d0c20ad815a Fix vertical scroll value for plane B Mike Pavone <pavone@retrodev.com> parents: 24 diff changeset	709 read_map_scroll(column, 0, line, (context->regs[REG_SCROLL_A] & 0x38) << 10, context->hscroll_a, context);
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	710 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	711
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	712 void read_map_scroll_b(uint16_t column, uint32_t line, vdp_context * context)
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	713 {
25 4d0c20ad815a Fix vertical scroll value for plane B Mike Pavone <pavone@retrodev.com> parents: 24 diff changeset	714 read_map_scroll(column, 1, line, (context->regs[REG_SCROLL_B] & 0x7) << 13, context->hscroll_b, context);
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	715 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	716
436 e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	717 void render_map(uint16_t col, uint8_t * tmp_buf, uint8_t offset, vdp_context * context)
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	718 {
413 36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	719 uint16_t address;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	720 uint8_t shift, add;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	721 if (context->double_res) {
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	722 address = ((col & 0x3FF) << 6);
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	723 shift = 1;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	724 add = context->framebuf != context->oddbuf ? 1 : 0;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	725 } else {
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	726 address = ((col & 0x7FF) << 5);
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	727 shift = 0;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	728 add = 0;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	729 }
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	730 if (col & MAP_BIT_V_FLIP) {
414 51ee0f117365 Fix vscroll calculation in double resultion interlace mode Mike Pavone <pavone@retrodev.com> parents: 413 diff changeset	731 address += 28 - 4 * context->v_offset/((context->v_offset << shift) + add)/;
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	732 } else {
414 51ee0f117365 Fix vscroll calculation in double resultion interlace mode Mike Pavone <pavone@retrodev.com> parents: 413 diff changeset	733 address += 4 * context->v_offset/((context->v_offset << shift) + add)/;
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	734 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	735 uint16_t pal_priority = (col >> 9) & 0x70;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	736 int32_t dir;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	737 if (col & MAP_BIT_H_FLIP) {
436 e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	738 offset += 7;
e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	739 offset &= SCROLL_BUFFER_MASK;
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	740 dir = -1;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	741 } else {
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	742 dir = 1;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	743 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	744 for (uint32_t i=0; i < 4; i++, address++)
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	745 {
436 e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	746 tmp_buf[offset] = pal_priority \| (context->vdpmem[address] >> 4);
e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	747 offset += dir;
e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	748 offset &= SCROLL_BUFFER_MASK;
e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	749 tmp_buf[offset] = pal_priority \| (context->vdpmem[address] & 0xF);
e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	750 offset += dir;
e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	751 offset &= SCROLL_BUFFER_MASK;
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	752 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	753 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	754
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	755 void render_map_1(vdp_context * context)
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	756 {
436 e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	757 render_map(context->col_1, context->tmp_buf_a, context->buf_a_off, context);
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	758 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	759
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	760 void render_map_2(vdp_context * context)
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	761 {
436 e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	762 render_map(context->col_2, context->tmp_buf_a, context->buf_a_off+8, context);
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	763 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	764
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	765 void render_map_3(vdp_context * context)
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	766 {
436 e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	767 render_map(context->col_1, context->tmp_buf_b, context->buf_b_off, context);
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	768 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	769
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	770 void render_map_output(uint32_t line, int32_t col, vdp_context * context)
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	771 {
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	772 if (line >= 240) {
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	773 return;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	774 }
436 e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	775 render_map(context->col_2, context->tmp_buf_b, context->buf_b_off+8, context);
426 add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	776 uint16_t *dst;
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	777 uint32_t *dst32;
436 e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	778 uint8_t sprite_buf, plane_a, *plane_b;
e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	779 int plane_a_off, plane_b_off;
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	780 if (col)
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	781 {
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	782 col-=2;
426 add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	783 if (context->b32) {
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	784 dst32 = context->framebuf;
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	785 dst32 += line * 320 + col * 8;
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	786 } else {
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	787 dst = context->framebuf;
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	788 dst += line * 320 + col * 8;
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	789 }
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	790 sprite_buf = context->linebuf + col * 8;
437 afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	791 uint8_t a_src, src;
40 7368a7071908 Broken window support Mike Pavone <pavone@retrodev.com> parents: 39 diff changeset	792 if (context->flags & FLAG_WINDOW) {
436 e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	793 plane_a_off = context->buf_a_off;
437 afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	794 a_src = DBG_SRC_W;
40 7368a7071908 Broken window support Mike Pavone <pavone@retrodev.com> parents: 39 diff changeset	795 } else {
436 e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	796 plane_a_off = context->buf_a_off - (context->hscroll_a & 0xF);
437 afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	797 a_src = DBG_SRC_A;
40 7368a7071908 Broken window support Mike Pavone <pavone@retrodev.com> parents: 39 diff changeset	798 }
436 e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	799 plane_b_off = context->buf_b_off - (context->hscroll_b & 0xF);
30 03f9bb57cc54 Small cleanup Mike Pavone <pavone@retrodev.com> parents: 29 diff changeset	800 //printf("A \| tmp_buf offset: %d\n", 8 - (context->hscroll_a & 0x7));
450 3758bcdae5de Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty Mike Pavone <pavone@retrodev.com> parents: 438 diff changeset	801
230 d3266cee02c9 Implemented shadow hilight mode. Mike Pavone <pavone@retrodev.com> parents: 191 diff changeset	802 if (context->regs[REG_MODE_4] & BIT_HILIGHT) {
436 e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	803 for (int i = 0; i < 16; ++plane_a_off, ++plane_b_off, ++sprite_buf, ++i) {
230 d3266cee02c9 Implemented shadow hilight mode. Mike Pavone <pavone@retrodev.com> parents: 191 diff changeset	804 uint8_t pixel;
436 e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	805 plane_a = context->tmp_buf_a + (plane_a_off & SCROLL_BUFFER_MASK);
e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	806 plane_b = context->tmp_buf_b + (plane_b_off & SCROLL_BUFFER_MASK);
437 afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	807 uint32_t * colors = context->colors;
230 d3266cee02c9 Implemented shadow hilight mode. Mike Pavone <pavone@retrodev.com> parents: 191 diff changeset	808 src = 0;
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	809 pixel = context->regs[REG_BG_COLOR];
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	810 src = DBG_SRC_BG;
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	811 if (*plane_b & 0xF) {
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	812 pixel = *plane_b;
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	813 src = DBG_SRC_B;
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	814 }
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	815 if (plane_a & 0xF && (plane_a & BUF_BIT_PRIORITY) >= (pixel & BUF_BIT_PRIORITY)) {
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	816 pixel = *plane_a;
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	817 src = DBG_SRC_A;
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	818 }
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	819 if (*sprite_buf & 0xF) {
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	820 uint8_t sprite_color = *sprite_buf & 0x3F;
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	821 if (sprite_color == 0x3E) {
437 afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	822 colors += CRAM_SIZE*2;
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	823 src \|= DBG_HILIGHT;
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	824 } else if (sprite_color == 0x3F) {
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	825 colors += CRAM_SIZE;
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	826 src \|= DBG_SHADOW;
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	827 } else if ((*sprite_buf & BUF_BIT_PRIORITY) >= (pixel & BUF_BIT_PRIORITY)) {
230 d3266cee02c9 Implemented shadow hilight mode. Mike Pavone <pavone@retrodev.com> parents: 191 diff changeset	828 pixel = *sprite_buf;
437 afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	829 src = DBG_SRC_S;
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	830 if ((pixel & 0xF) == 0xE) {
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	831 src \|= DBG_SHADOW;
437 afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	832 colors += CRAM_SIZE;
230 d3266cee02c9 Implemented shadow hilight mode. Mike Pavone <pavone@retrodev.com> parents: 191 diff changeset	833 }
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	834
230 d3266cee02c9 Implemented shadow hilight mode. Mike Pavone <pavone@retrodev.com> parents: 191 diff changeset	835 }
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	836 } else if (!((plane_a \| plane_b) & BUF_BIT_PRIORITY)) {
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	837 colors += CRAM_SIZE;
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	838 src \|= DBG_SHADOW;
230 d3266cee02c9 Implemented shadow hilight mode. Mike Pavone <pavone@retrodev.com> parents: 191 diff changeset	839 }
426 add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	840 pixel &= 0x3F;
437 afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	841 uint32_t outpixel;
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	842 if (context->debug) {
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	843 outpixel = context->debugcolors[src];
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	844 } else {
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	845 outpixel = colors[pixel];
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	846 }
426 add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	847 if (context->b32) {
437 afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	848 *(dst32++) = outpixel;
426 add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	849 } else {
437 afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	850 *(dst++) = outpixel;
426 add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	851 }
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	852 //*dst = (context->cram[pixel & 0x3F] & 0xEEE) \| ((pixel & BUF_BIT_PRIORITY) ? FBUF_BIT_PRIORITY : 0) \| src;
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	853 }
230 d3266cee02c9 Implemented shadow hilight mode. Mike Pavone <pavone@retrodev.com> parents: 191 diff changeset	854 } else {
436 e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	855 for (int i = 0; i < 16; ++plane_a_off, ++plane_b_off, ++sprite_buf, ++i) {
e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	856 plane_a = context->tmp_buf_a + (plane_a_off & SCROLL_BUFFER_MASK);
e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	857 plane_b = context->tmp_buf_b + (plane_b_off & SCROLL_BUFFER_MASK);
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	858 uint8_t pixel = context->regs[REG_BG_COLOR];
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	859 src = DBG_SRC_BG;
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	860 if (*plane_b & 0xF) {
230 d3266cee02c9 Implemented shadow hilight mode. Mike Pavone <pavone@retrodev.com> parents: 191 diff changeset	861 pixel = *plane_b;
437 afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	862 src = DBG_SRC_B;
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	863 }
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	864 if (plane_a & 0xF && (plane_a & BUF_BIT_PRIORITY) >= (pixel & BUF_BIT_PRIORITY)) {
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	865 pixel = *plane_a;
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	866 src = DBG_SRC_A;
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	867 }
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	868 if (sprite_buf & 0xF && (sprite_buf & BUF_BIT_PRIORITY) >= (pixel & BUF_BIT_PRIORITY)) {
230 d3266cee02c9 Implemented shadow hilight mode. Mike Pavone <pavone@retrodev.com> parents: 191 diff changeset	869 pixel = *sprite_buf;
437 afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	870 src = DBG_SRC_S;
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	871 }
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	872 uint32_t outpixel;
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	873 if (context->debug) {
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	874 outpixel = context->debugcolors[src];
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	875 } else {
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	876 outpixel = context->colors[pixel & 0x3F];
230 d3266cee02c9 Implemented shadow hilight mode. Mike Pavone <pavone@retrodev.com> parents: 191 diff changeset	877 }
426 add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	878 if (context->b32) {
437 afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	879 *(dst32++) = outpixel;
426 add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	880 } else {
437 afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	881 *(dst++) = outpixel;
426 add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	882 }
230 d3266cee02c9 Implemented shadow hilight mode. Mike Pavone <pavone@retrodev.com> parents: 191 diff changeset	883 }
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	884 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	885 }
436 e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	886 context->buf_a_off = (context->buf_a_off + SCROLL_BUFFER_DRAW) & SCROLL_BUFFER_MASK;
e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	887 context->buf_b_off = (context->buf_b_off + SCROLL_BUFFER_DRAW) & SCROLL_BUFFER_MASK;
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	888 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	889
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	890 #define COLUMN_RENDER_BLOCK(column, startcyc) \
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	891 case startcyc:\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	892 read_map_scroll_a(column, line, context);\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	893 break;\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	894 case (startcyc+1):\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	895 external_slot(context);\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	896 break;\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	897 case (startcyc+2):\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	898 render_map_1(context);\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	899 break;\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	900 case (startcyc+3):\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	901 render_map_2(context);\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	902 break;\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	903 case (startcyc+4):\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	904 read_map_scroll_b(column, line, context);\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	905 break;\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	906 case (startcyc+5):\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	907 read_sprite_x(line, context);\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	908 break;\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	909 case (startcyc+6):\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	910 render_map_3(context);\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	911 break;\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	912 case (startcyc+7):\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	913 render_map_output(line, column, context);\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	914 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	915
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	916 #define COLUMN_RENDER_BLOCK_REFRESH(column, startcyc) \
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	917 case startcyc:\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	918 read_map_scroll_a(column, line, context);\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	919 break;\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	920 case (startcyc+1):\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	921 break;\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	922 case (startcyc+2):\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	923 render_map_1(context);\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	924 break;\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	925 case (startcyc+3):\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	926 render_map_2(context);\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	927 break;\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	928 case (startcyc+4):\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	929 read_map_scroll_b(column, line, context);\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	930 break;\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	931 case (startcyc+5):\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	932 read_sprite_x(line, context);\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	933 break;\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	934 case (startcyc+6):\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	935 render_map_3(context);\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	936 break;\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	937 case (startcyc+7):\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	938 render_map_output(line, column, context);\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	939 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	940
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	941 void vdp_h40(uint32_t line, uint32_t linecyc, vdp_context * context)
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	942 {
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	943 uint16_t address;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	944 uint32_t mask;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	945 switch(linecyc)
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	946 {
647 5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events Michael Pavone <pavone@retrodev.com> parents: 629 diff changeset	947 case 165:
5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events Michael Pavone <pavone@retrodev.com> parents: 629 diff changeset	948 case 166:
5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events Michael Pavone <pavone@retrodev.com> parents: 629 diff changeset	949 external_slot(context);
5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events Michael Pavone <pavone@retrodev.com> parents: 629 diff changeset	950 break;
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	951 //sprite render to line buffer starts
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	952 case 167:
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	953 case 168:
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	954 case 169:
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	955 case 170:
329 fd5f6577db9b Implement first line/last line weirdness in VDP Mike Pavone <pavone@retrodev.com> parents: 328 diff changeset	956 if (line == 0xFF) {
fd5f6577db9b Implement first line/last line weirdness in VDP Mike Pavone <pavone@retrodev.com> parents: 328 diff changeset	957 external_slot(context);
fd5f6577db9b Implement first line/last line weirdness in VDP Mike Pavone <pavone@retrodev.com> parents: 328 diff changeset	958 } else {
fd5f6577db9b Implement first line/last line weirdness in VDP Mike Pavone <pavone@retrodev.com> parents: 328 diff changeset	959 render_sprite_cells(context);
fd5f6577db9b Implement first line/last line weirdness in VDP Mike Pavone <pavone@retrodev.com> parents: 328 diff changeset	960 }
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	961 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	962 //sprite attribute table scan starts
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	963 case 171:
21 72ce60cb1711 Sprites somewhat less broken Mike Pavone <pavone@retrodev.com> parents: 20 diff changeset	964 render_sprite_cells( context);
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	965 scan_sprite_table(line, context);
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	966 break;
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	967 case 172:
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	968 case 173:
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	969 case 174:
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	970 case 175:
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	971 case 176:
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	972 case 177:
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	973 case 178:
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	974 case 179:
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	975 case 180:
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	976 case 181:
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	977 case 182:
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	978 case 229:
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	979 case 230:
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	980 case 231:
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	981 case 232:
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	982 case 233:
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	983 //!HSYNC asserted
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	984 case 234:
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	985 case 235:
21 72ce60cb1711 Sprites somewhat less broken Mike Pavone <pavone@retrodev.com> parents: 20 diff changeset	986 render_sprite_cells(context);
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	987 scan_sprite_table(line, context);
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	988 break;
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	989 case 236:
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	990 external_slot(context);
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	991 break;
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	992 case 237:
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	993 case 238:
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	994 case 239:
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	995 case 240:
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	996 case 241:
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	997 case 242:
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	998 case 243:
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	999 case 244:
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1000 case 245:
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1001 case 246:
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1002 case 247:
21 72ce60cb1711 Sprites somewhat less broken Mike Pavone <pavone@retrodev.com> parents: 20 diff changeset	1003 render_sprite_cells(context);
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1004 scan_sprite_table(line, context);
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1005 break;
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1006 case 248:
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1007 address = (context->regs[REG_HSCROLL] & 0x3F) << 10;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1008 mask = 0;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1009 if (context->regs[REG_MODE_3] & 0x2) {
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1010 mask \|= 0xF8;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1011 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1012 if (context->regs[REG_MODE_3] & 0x1) {
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1013 mask \|= 0x7;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1014 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1015 line &= mask;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1016 address += line * 4;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1017 context->hscroll_a = context->vdpmem[address] << 8 \| context->vdpmem[address+1];
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1018 context->hscroll_b = context->vdpmem[address+2] << 8 \| context->vdpmem[address+3];
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1019 //printf("%d: HScroll A: %d, HScroll B: %d\n", line, context->hscroll_a, context->hscroll_b);
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1020 break;
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1021 case 249:
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1022 //!HSYNC high
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1023 case 250:
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1024 case 251:
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1025 case 252:
21 72ce60cb1711 Sprites somewhat less broken Mike Pavone <pavone@retrodev.com> parents: 20 diff changeset	1026 render_sprite_cells(context);
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1027 scan_sprite_table(line, context);
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1028 break;
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1029 case 253:
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1030 read_map_scroll_a(0, line, context);
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1031 break;
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1032 case 254:
21 72ce60cb1711 Sprites somewhat less broken Mike Pavone <pavone@retrodev.com> parents: 20 diff changeset	1033 render_sprite_cells(context);
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1034 scan_sprite_table(line, context);
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1035 break;
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1036 case 255:
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1037 render_map_1(context);
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1038 scan_sprite_table(line, context);//Just a guess
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1039 break;
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1040 case 0:
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1041 render_map_2(context);
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1042 scan_sprite_table(line, context);//Just a guess
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1043 break;
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1044 case 1:
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1045 read_map_scroll_b(0, line, context);
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1046 break;
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1047 case 2:
21 72ce60cb1711 Sprites somewhat less broken Mike Pavone <pavone@retrodev.com> parents: 20 diff changeset	1048 render_sprite_cells(context);
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1049 scan_sprite_table(line, context);
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1050 break;
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1051 case 3:
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1052 render_map_3(context);
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1053 scan_sprite_table(line, context);//Just a guess
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1054 break;
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1055 case 4:
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1056 render_map_output(line, 0, context);
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1057 scan_sprite_table(line, context);//Just a guess
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1058 //reverse context slot counter so it counts the number of sprite slots
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1059 //filled rather than the number of available slots
21 72ce60cb1711 Sprites somewhat less broken Mike Pavone <pavone@retrodev.com> parents: 20 diff changeset	1060 //context->slot_counter = MAX_SPRITES_LINE - context->slot_counter;
72ce60cb1711 Sprites somewhat less broken Mike Pavone <pavone@retrodev.com> parents: 20 diff changeset	1061 context->cur_slot = MAX_SPRITES_LINE-1;
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1062 context->sprite_draws = MAX_DRAWS;
36 04672c060062 Pass all sprite masking tests Mike Pavone <pavone@retrodev.com> parents: 35 diff changeset	1063 context->flags &= (~FLAG_CAN_MASK & ~FLAG_MASKED);
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1064 break;
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1065 COLUMN_RENDER_BLOCK(2, 5)
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1066 COLUMN_RENDER_BLOCK(4, 13)
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1067 COLUMN_RENDER_BLOCK(6, 21)
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1068 COLUMN_RENDER_BLOCK_REFRESH(8, 29)
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1069 COLUMN_RENDER_BLOCK(10, 37)
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1070 COLUMN_RENDER_BLOCK(12, 45)
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1071 COLUMN_RENDER_BLOCK(14, 53)
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1072 COLUMN_RENDER_BLOCK_REFRESH(16, 61)
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1073 COLUMN_RENDER_BLOCK(18, 69)
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1074 COLUMN_RENDER_BLOCK(20, 77)
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1075 COLUMN_RENDER_BLOCK(22, 85)
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1076 COLUMN_RENDER_BLOCK_REFRESH(24, 93)
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1077 COLUMN_RENDER_BLOCK(26, 101)
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1078 COLUMN_RENDER_BLOCK(28, 109)
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1079 COLUMN_RENDER_BLOCK(30, 117)
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1080 COLUMN_RENDER_BLOCK_REFRESH(32, 125)
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1081 COLUMN_RENDER_BLOCK(34, 133)
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1082 COLUMN_RENDER_BLOCK(36, 141)
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1083 COLUMN_RENDER_BLOCK(38, 149)
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1084 COLUMN_RENDER_BLOCK_REFRESH(40, 157)
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1085 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1086 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1087
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1088 void vdp_h32(uint32_t line, uint32_t linecyc, vdp_context * context)
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1089 {
37 cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1090 uint16_t address;
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1091 uint32_t mask;
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1092 switch(linecyc)
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1093 {
647 5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events Michael Pavone <pavone@retrodev.com> parents: 629 diff changeset	1094 case 132:
5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events Michael Pavone <pavone@retrodev.com> parents: 629 diff changeset	1095 case 133:
5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events Michael Pavone <pavone@retrodev.com> parents: 629 diff changeset	1096 external_slot(context);
5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events Michael Pavone <pavone@retrodev.com> parents: 629 diff changeset	1097 break;
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1098 //sprite render to line buffer starts
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1099 case 134:
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1100 case 135:
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1101 case 136:
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1102 case 137:
329 fd5f6577db9b Implement first line/last line weirdness in VDP Mike Pavone <pavone@retrodev.com> parents: 328 diff changeset	1103 if (line == 0xFF) {
fd5f6577db9b Implement first line/last line weirdness in VDP Mike Pavone <pavone@retrodev.com> parents: 328 diff changeset	1104 external_slot(context);
fd5f6577db9b Implement first line/last line weirdness in VDP Mike Pavone <pavone@retrodev.com> parents: 328 diff changeset	1105 } else {
fd5f6577db9b Implement first line/last line weirdness in VDP Mike Pavone <pavone@retrodev.com> parents: 328 diff changeset	1106 render_sprite_cells(context);
fd5f6577db9b Implement first line/last line weirdness in VDP Mike Pavone <pavone@retrodev.com> parents: 328 diff changeset	1107 }
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1108 break;
37 cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1109 //sprite attribute table scan starts
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1110 case 138:
37 cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1111 render_sprite_cells( context);
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1112 scan_sprite_table(line, context);
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1113 break;
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1114 case 139:
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1115 case 140:
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1116 case 141:
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1117 case 142:
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1118 case 143:
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1119 case 144:
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1120 case 145:
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1121 case 146:
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1122 case 147:
37 cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1123 render_sprite_cells(context);
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1124 scan_sprite_table(line, context);
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1125 case 233:
37 cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1126 external_slot(context);
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1127 break;
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1128 case 234:
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1129 case 235:
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1130 case 236:
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1131 case 237:
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1132 case 238:
37 cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1133 //HSYNC start
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1134 case 239:
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1135 case 240:
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1136 case 241:
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1137 case 242:
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1138 case 243:
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1139 case 244:
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1140 case 245:
37 cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1141 render_sprite_cells(context);
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1142 scan_sprite_table(line, context);
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1143 break;
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1144 case 246:
37 cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1145 external_slot(context);
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1146 break;
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1147 case 247:
37 cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1148 address = (context->regs[REG_HSCROLL] & 0x3F) << 10;
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1149 mask = 0;
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1150 if (context->regs[REG_MODE_3] & 0x2) {
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1151 mask \|= 0xF8;
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1152 }
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1153 if (context->regs[REG_MODE_3] & 0x1) {
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1154 mask \|= 0x7;
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1155 }
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1156 line &= mask;
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1157 address += line * 4;
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1158 context->hscroll_a = context->vdpmem[address] << 8 \| context->vdpmem[address+1];
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1159 context->hscroll_b = context->vdpmem[address+2] << 8 \| context->vdpmem[address+3];
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1160 //printf("%d: HScroll A: %d, HScroll B: %d\n", line, context->hscroll_a, context->hscroll_b);
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1161 break;
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1162 case 248:
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1163 case 249:
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1164 case 250:
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1165 case 251:
37 cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1166 render_sprite_cells(context);
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1167 scan_sprite_table(line, context);
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1168 break;
37 cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1169 //!HSYNC high
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1170 case 252:
37 cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1171 read_map_scroll_a(0, line, context);
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1172 break;
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1173 case 253:
37 cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1174 render_sprite_cells(context);
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1175 scan_sprite_table(line, context);
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1176 break;
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1177 case 254:
37 cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1178 render_map_1(context);
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1179 scan_sprite_table(line, context);//Just a guess
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1180 break;
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1181 case 255:
37 cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1182 render_map_2(context);
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1183 scan_sprite_table(line, context);//Just a guess
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1184 break;
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1185 case 0:
37 cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1186 read_map_scroll_b(0, line, context);
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1187 break;
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1188 case 1:
37 cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1189 render_sprite_cells(context);
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1190 scan_sprite_table(line, context);
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1191 break;
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1192 case 2:
37 cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1193 render_map_3(context);
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1194 scan_sprite_table(line, context);//Just a guess
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1195 break;
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1196 case 3:
37 cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1197 render_map_output(line, 0, context);
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1198 scan_sprite_table(line, context);//Just a guess
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1199 //reverse context slot counter so it counts the number of sprite slots
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1200 //filled rather than the number of available slots
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1201 //context->slot_counter = MAX_SPRITES_LINE - context->slot_counter;
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1202 context->cur_slot = MAX_SPRITES_LINE_H32-1;
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1203 context->sprite_draws = MAX_DRAWS_H32;
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1204 context->flags &= (~FLAG_CAN_MASK & ~FLAG_MASKED);
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1205 break;
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1206 COLUMN_RENDER_BLOCK(2, 4)
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1207 COLUMN_RENDER_BLOCK(4, 12)
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1208 COLUMN_RENDER_BLOCK(6, 20)
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1209 COLUMN_RENDER_BLOCK_REFRESH(8, 28)
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1210 COLUMN_RENDER_BLOCK(10, 36)
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1211 COLUMN_RENDER_BLOCK(12, 44)
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1212 COLUMN_RENDER_BLOCK(14, 52)
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1213 COLUMN_RENDER_BLOCK_REFRESH(16, 60)
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1214 COLUMN_RENDER_BLOCK(18, 68)
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1215 COLUMN_RENDER_BLOCK(20, 76)
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1216 COLUMN_RENDER_BLOCK(22, 84)
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1217 COLUMN_RENDER_BLOCK_REFRESH(24, 92)
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1218 COLUMN_RENDER_BLOCK(26, 100)
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1219 COLUMN_RENDER_BLOCK(28, 108)
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1220 COLUMN_RENDER_BLOCK(30, 116)
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1221 COLUMN_RENDER_BLOCK_REFRESH(32, 124)
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1222 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1223 }
503 eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1224
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1225 void vdp_h40_line(uint32_t line, vdp_context * context)
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1226 {
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1227 context->cur_slot = MAX_DRAWS-1;
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1228 memset(context->linebuf, 0, LINEBUF_SIZE);
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1229 if (line == 0xFF) {
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1230 external_slot(context);
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1231 if (context->flags & FLAG_DMA_RUN) {
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1232 run_dma_src(context, 0);
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1233 }
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1234 external_slot(context);
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1235 if (context->flags & FLAG_DMA_RUN) {
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1236 run_dma_src(context, 0);
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1237 }
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1238 external_slot(context);
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1239 if (context->flags & FLAG_DMA_RUN) {
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1240 run_dma_src(context, 0);
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1241 }
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1242 external_slot(context);
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1243 if (context->flags & FLAG_DMA_RUN) {
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1244 run_dma_src(context, 0);
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1245 }
647 5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events Michael Pavone <pavone@retrodev.com> parents: 629 diff changeset	1246 external_slot(context);
5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events Michael Pavone <pavone@retrodev.com> parents: 629 diff changeset	1247 if (context->flags & FLAG_DMA_RUN) {
5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events Michael Pavone <pavone@retrodev.com> parents: 629 diff changeset	1248 run_dma_src(context, 0);
5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events Michael Pavone <pavone@retrodev.com> parents: 629 diff changeset	1249 }
5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events Michael Pavone <pavone@retrodev.com> parents: 629 diff changeset	1250 external_slot(context);
5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events Michael Pavone <pavone@retrodev.com> parents: 629 diff changeset	1251 if (context->flags & FLAG_DMA_RUN) {
5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events Michael Pavone <pavone@retrodev.com> parents: 629 diff changeset	1252 run_dma_src(context, 0);
5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events Michael Pavone <pavone@retrodev.com> parents: 629 diff changeset	1253 }
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	1254 for (int i = 0; i < 19; i++)
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	1255 {
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	1256 scan_sprite_table(line, context);
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	1257 }
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	1258 external_slot(context);
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	1259 for (int i = 0; i < 21; i++)
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	1260 {
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	1261 scan_sprite_table(line, context);
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	1262 }
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	1263 //reverse context slot counter so it counts the number of sprite slots
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	1264 //filled rather than the number of available slots
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	1265 //context->slot_counter = MAX_SPRITES_LINE - context->slot_counter;
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	1266 context->cur_slot = MAX_SPRITES_LINE-1;
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	1267 context->sprite_draws = MAX_DRAWS;
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	1268 context->flags &= (~FLAG_CAN_MASK & ~FLAG_MASKED);
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	1269 for (int column = 2; column < 42; column += 8)
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	1270 {
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	1271 external_slot(context);
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	1272 if (context->flags & FLAG_DMA_RUN) {
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	1273 run_dma_src(context, 0);
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	1274 }
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	1275 read_sprite_x(line, context);
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	1276
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	1277 external_slot(context);
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	1278 if (context->flags & FLAG_DMA_RUN) {
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	1279 run_dma_src(context, 0);
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	1280 }
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	1281 read_sprite_x(line, context);
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	1282
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	1283 external_slot(context);
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	1284 if (context->flags & FLAG_DMA_RUN) {
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	1285 run_dma_src(context, 0);
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	1286 }
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	1287 read_sprite_x(line, context);
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	1288
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	1289 read_sprite_x(line, context);
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	1290 }
647 5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events Michael Pavone <pavone@retrodev.com> parents: 629 diff changeset	1291
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	1292 return;
503 eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1293 }
647 5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events Michael Pavone <pavone@retrodev.com> parents: 629 diff changeset	1294 external_slot(context);
5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events Michael Pavone <pavone@retrodev.com> parents: 629 diff changeset	1295 if (context->flags & FLAG_DMA_RUN) {
5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events Michael Pavone <pavone@retrodev.com> parents: 629 diff changeset	1296 run_dma_src(context, 0);
5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events Michael Pavone <pavone@retrodev.com> parents: 629 diff changeset	1297 }
5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events Michael Pavone <pavone@retrodev.com> parents: 629 diff changeset	1298 external_slot(context);
5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events Michael Pavone <pavone@retrodev.com> parents: 629 diff changeset	1299 if (context->flags & FLAG_DMA_RUN) {
5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events Michael Pavone <pavone@retrodev.com> parents: 629 diff changeset	1300 run_dma_src(context, 0);
5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events Michael Pavone <pavone@retrodev.com> parents: 629 diff changeset	1301 }
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	1302
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	1303 render_sprite_cells(context);
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	1304 render_sprite_cells(context);
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	1305 render_sprite_cells(context);
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	1306 render_sprite_cells(context);
503 eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1307 context->sprite_index = 0x80;
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1308 context->slot_counter = MAX_SPRITES_LINE;
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1309 for (int i = 0; i < 19; i++)
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1310 {
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1311 render_sprite_cells(context);
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1312 scan_sprite_table(line, context);
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1313 }
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1314 external_slot(context);
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1315 for (int i = 0; i < 11; i++)
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1316 {
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1317 render_sprite_cells(context);
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1318 scan_sprite_table(line, context);
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1319 }
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1320 uint16_t address;
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1321 uint32_t mask;
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1322 address = (context->regs[REG_HSCROLL] & 0x3F) << 10;
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1323 mask = 0;
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1324 if (context->regs[REG_MODE_3] & 0x2) {
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1325 mask \|= 0xF8;
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1326 }
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1327 if (context->regs[REG_MODE_3] & 0x1) {
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1328 mask \|= 0x7;
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1329 }
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1330 address += (line & mask) * 4;
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1331 context->hscroll_a = context->vdpmem[address] << 8 \| context->vdpmem[address+1];
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1332 context->hscroll_b = context->vdpmem[address+2] << 8 \| context->vdpmem[address+3];
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1333 render_sprite_cells(context);
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1334 scan_sprite_table(line, context);
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1335 render_sprite_cells(context);
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1336 scan_sprite_table(line, context);
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1337 render_sprite_cells(context);
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1338 scan_sprite_table(line, context);
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1339 render_sprite_cells(context);
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1340 scan_sprite_table(line, context);
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1341
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1342 read_map_scroll_a(0, line, context);
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1343 render_sprite_cells(context);
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1344 scan_sprite_table(line, context);
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1345 render_map_1(context);
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1346 scan_sprite_table(line, context);//Just a guess
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1347 render_map_2(context);
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1348 scan_sprite_table(line, context);//Just a guess
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1349 read_map_scroll_b(0, line, context);
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1350 render_sprite_cells(context);
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1351 scan_sprite_table(line, context);
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1352 render_map_3(context);
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1353 scan_sprite_table(line, context);//Just a guess
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1354 render_map_output(line, 0, context);
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1355 scan_sprite_table(line, context);//Just a guess
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1356 //reverse context slot counter so it counts the number of sprite slots
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1357 //filled rather than the number of available slots
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1358 //context->slot_counter = MAX_SPRITES_LINE - context->slot_counter;
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1359 context->cur_slot = MAX_SPRITES_LINE-1;
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1360 context->sprite_draws = MAX_DRAWS;
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1361 context->flags &= (~FLAG_CAN_MASK & ~FLAG_MASKED);
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1362 for (int column = 2; column < 42; column += 2)
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1363 {
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1364 read_map_scroll_a(column, line, context);
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1365 external_slot(context);
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1366 if (context->flags & FLAG_DMA_RUN) {
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1367 run_dma_src(context, 0);
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1368 }
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1369 render_map_1(context);
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1370 render_map_2(context);
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1371 read_map_scroll_b(column, line, context);
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1372 read_sprite_x(line, context);
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1373 render_map_3(context);
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1374 render_map_output(line, column, context);
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1375
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1376 column += 2;
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1377 read_map_scroll_a(column, line, context);
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1378 external_slot(context);
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1379 if (context->flags & FLAG_DMA_RUN) {
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1380 run_dma_src(context, 0);
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1381 }
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1382 render_map_1(context);
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1383 render_map_2(context);
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1384 read_map_scroll_b(column, line, context);
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1385 read_sprite_x(line, context);
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1386 render_map_3(context);
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1387 render_map_output(line, column, context);
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1388
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1389 column += 2;
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1390 read_map_scroll_a(column, line, context);
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1391 external_slot(context);
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1392 if (context->flags & FLAG_DMA_RUN) {
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1393 run_dma_src(context, 0);
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1394 }
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1395 render_map_1(context);
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1396 render_map_2(context);
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1397 read_map_scroll_b(column, line, context);
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1398 read_sprite_x(line, context);
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1399 render_map_3(context);
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1400 render_map_output(line, column, context);
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1401
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1402 column += 2;
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1403 read_map_scroll_a(column, line, context);
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1404 render_map_1(context);
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1405 render_map_2(context);
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1406 read_map_scroll_b(column, line, context);
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1407 read_sprite_x(line, context);
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1408 render_map_3(context);
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1409 render_map_output(line, column, context);
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1410 }
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1411 }
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1412
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1413 void latch_mode(vdp_context * context)
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1414 {
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1415 context->latched_mode = context->regs[REG_MODE_2] & BIT_PAL;
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1416 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1417
330 57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1418 void check_render_bg(vdp_context * context, int32_t line, uint32_t slot)
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1419 {
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1420 int starti = -1;
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1421 if (context->regs[REG_MODE_4] & BIT_H40) {
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1422 if (slot >= 12 && slot < 172) {
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1423 uint32_t x = (slot-12)*2;
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1424 starti = line * 320 + x;
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1425 }
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1426 } else {
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1427 if (slot >= 11 && slot < 139) {
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1428 uint32_t x = (slot-11)*2;
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1429 starti = line * 320 + x;
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1430 }
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1431 }
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1432 if (starti >= 0) {
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1433 if (context->b32) {
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1434 uint32_t color = context->colors[context->regs[REG_BG_COLOR]];
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1435 uint32_t * start = context->framebuf;
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1436 start += starti;
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1437 for (int i = 0; i < 2; i++) {
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1438 *(start++) = color;
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1439 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1440 } else {
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1441 uint16_t color = context->colors[context->regs[REG_BG_COLOR]];
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1442 uint16_t * start = context->framebuf;
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1443 start += starti;
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1444 for (int i = 0; i < 2; i++) {
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1445 *(start++) = color;
426 add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	1446 }
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1447 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1448 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1449 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1450
697 7f96bd1cb1be Sync fixes and logging to fix more sync issues Michael Pavone <pavone@retrodev.com> parents: 680 diff changeset	1451 uint32_t const h40_hsync_cycles[] = {19, 20, 20, 20, 18, 20, 20, 20, 18, 20, 20, 20, 18, 20, 20, 20, 19};
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1452
717 22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	1453 void vdp_advance_line(vdp_context *context)
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	1454 {
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	1455 context->vcounter++;
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	1456 if (context->vcounter > (context->latched_mode & BIT_PAL ? PAL_INACTIVE_START : NTSC_INACTIVE_START)) {
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	1457 context->hint_counter = context->regs[REG_HINT];
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	1458 } else if (context->hint_counter) {
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	1459 context->hint_counter--;
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	1460 } else {
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	1461 context->flags2 \|= FLAG2_HINT_PENDING;
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	1462 context->pending_hint_start = context->cycles;
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	1463 context->hint_counter = context->regs[REG_HINT];
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	1464 }
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	1465 }
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	1466
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1467 void vdp_run_context(vdp_context * context, uint32_t target_cycles)
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1468 {
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1469 while(context->cycles < target_cycles)
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1470 {
460 788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	1471 context->flags &= ~FLAG_UNUSED_SLOT;
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1472 uint32_t line = context->vcounter;
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1473 uint32_t slot = context->hslot;
697 7f96bd1cb1be Sync fixes and logging to fix more sync issues Michael Pavone <pavone@retrodev.com> parents: 680 diff changeset	1474
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1475 if (!line && !slot) {
697 7f96bd1cb1be Sync fixes and logging to fix more sync issues Michael Pavone <pavone@retrodev.com> parents: 680 diff changeset	1476 //TODO: Figure out when this actually happens
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1477 latch_mode(context);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1478 }
697 7f96bd1cb1be Sync fixes and logging to fix more sync issues Michael Pavone <pavone@retrodev.com> parents: 680 diff changeset	1479 uint32_t inactive_start = context->latched_mode & BIT_PAL ? PAL_INACTIVE_START : NTSC_INACTIVE_START;
647 5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events Michael Pavone <pavone@retrodev.com> parents: 629 diff changeset	1480
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1481 uint8_t is_h40 = context->regs[REG_MODE_4] & BIT_H40;
647 5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events Michael Pavone <pavone@retrodev.com> parents: 629 diff changeset	1482 if (is_h40) {
5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events Michael Pavone <pavone@retrodev.com> parents: 629 diff changeset	1483 if (slot == 167) {
5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events Michael Pavone <pavone@retrodev.com> parents: 629 diff changeset	1484 context->cur_slot = MAX_DRAWS-1;
5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events Michael Pavone <pavone@retrodev.com> parents: 629 diff changeset	1485 memset(context->linebuf, 0, LINEBUF_SIZE);
5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events Michael Pavone <pavone@retrodev.com> parents: 629 diff changeset	1486 } else if (slot == 171) {
5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events Michael Pavone <pavone@retrodev.com> parents: 629 diff changeset	1487 context->sprite_index = 0x80;
5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events Michael Pavone <pavone@retrodev.com> parents: 629 diff changeset	1488 context->slot_counter = MAX_SPRITES_LINE;
5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events Michael Pavone <pavone@retrodev.com> parents: 629 diff changeset	1489 }
5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events Michael Pavone <pavone@retrodev.com> parents: 629 diff changeset	1490 } else {
5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events Michael Pavone <pavone@retrodev.com> parents: 629 diff changeset	1491 if (slot == 134) {
5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events Michael Pavone <pavone@retrodev.com> parents: 629 diff changeset	1492 context->cur_slot = MAX_DRAWS_H32-1;
5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events Michael Pavone <pavone@retrodev.com> parents: 629 diff changeset	1493 memset(context->linebuf, 0, LINEBUF_SIZE);
5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events Michael Pavone <pavone@retrodev.com> parents: 629 diff changeset	1494 } else if (slot == 138) {
5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events Michael Pavone <pavone@retrodev.com> parents: 629 diff changeset	1495 context->sprite_index = 0x80;
5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events Michael Pavone <pavone@retrodev.com> parents: 629 diff changeset	1496 context->slot_counter = MAX_SPRITES_LINE_H32;
5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events Michael Pavone <pavone@retrodev.com> parents: 629 diff changeset	1497 }
5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events Michael Pavone <pavone@retrodev.com> parents: 629 diff changeset	1498 }
717 22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	1499 if(line == inactive_start) {
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1500 uint32_t intslot = context->regs[REG_MODE_4] & BIT_H40 ? VINT_SLOT_H40 : VINT_SLOT_H32;
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1501 if (slot == intslot) {
317 e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	1502 context->flags2 \|= FLAG2_VINT_PENDING;
717 22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	1503 context->pending_vint_start = context->cycles;
317 e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	1504 }
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	1505 }
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1506 uint32_t inccycles;
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1507 //line 0x1FF is basically active even though it's not displayed
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1508 uint8_t active_slot = line < inactive_start \|\| line == 0x1FF;
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1509 if (is_h40) {
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1510 if (slot < HSYNC_SLOT_H40 \|\| slot >= HSYNC_END_H40) {
330 57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1511 inccycles = MCLKS_SLOT_H40;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1512 } else {
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1513 inccycles = h40_hsync_cycles[slot-HSYNC_SLOT_H40];
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1514 }
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1515 //the first inactive line behaves as an active one for the first 4 slots
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1516 if (line == inactive_start && slot > 166 && slot < 171) {
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1517 active_slot = 1;
330 57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1518 }
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1519 } else {
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1520 inccycles = MCLKS_SLOT_H32;
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1521 //the first inactive line behaves as an active one for the first 4 slots
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1522 if (line == inactive_start && slot > 166 && slot < 171) {
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1523 active_slot = 1;
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1524 }
330 57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1525 }
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1526 uint8_t inc_slot = 1;
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1527 if (context->regs[REG_MODE_2] & DISPLAY_ENABLE && active_slot) {
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1528 //run VDP rendering for a slot or a line
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1529 if (is_h40) {
647 5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events Michael Pavone <pavone@retrodev.com> parents: 629 diff changeset	1530 if (slot == LINE_CHANGE_H40 && line < inactive_start && (target_cycles - context->cycles) >= MCLKS_LINE) {
503 eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1531 vdp_h40_line(line, context);
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1532 inccycles = MCLKS_LINE;
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1533 inc_slot = 0;
503 eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1534 } else {
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1535 vdp_h40(line, slot, context);
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	1536 }
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1537 } else {
330 57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1538 vdp_h32(line, slot, context);
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1539 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1540 } else {
330 57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1541 if (!is_refresh(context, slot)) {
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1542 external_slot(context);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1543 }
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1544 if (line < inactive_start) {
330 57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1545 check_render_bg(context, line, slot);
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1546 }
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1547 }
460 788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	1548 if (context->flags & FLAG_DMA_RUN && !is_refresh(context, slot)) {
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	1549 run_dma_src(context, slot);
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	1550 }
717 22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	1551 context->cycles += inccycles;
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1552 if (inc_slot) {
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1553 context->hslot++;
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1554 context->hslot &= 0xFF;
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1555 if (is_h40) {
647 5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events Michael Pavone <pavone@retrodev.com> parents: 629 diff changeset	1556 if (context->hslot == LINE_CHANGE_H40) {
717 22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	1557 vdp_advance_line(context);
699 d8a1fdec68fc Fix frame counter increment and VINT cycle time calculation Michael Pavone <pavone@retrodev.com> parents: 697 diff changeset	1558 if (context->vcounter == (inactive_start + 8)) {
d8a1fdec68fc Fix frame counter increment and VINT cycle time calculation Michael Pavone <pavone@retrodev.com> parents: 697 diff changeset	1559 context->frame++;
d8a1fdec68fc Fix frame counter increment and VINT cycle time calculation Michael Pavone <pavone@retrodev.com> parents: 697 diff changeset	1560 }
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1561 } else if (context->hslot == 183) {
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1562 context->hslot = 229;
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1563 }
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1564 } else {
647 5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events Michael Pavone <pavone@retrodev.com> parents: 629 diff changeset	1565 if (context->hslot == LINE_CHANGE_H32) {
717 22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	1566 vdp_advance_line(context);
699 d8a1fdec68fc Fix frame counter increment and VINT cycle time calculation Michael Pavone <pavone@retrodev.com> parents: 697 diff changeset	1567 if (context->vcounter == (inactive_start + 8)) {
d8a1fdec68fc Fix frame counter increment and VINT cycle time calculation Michael Pavone <pavone@retrodev.com> parents: 697 diff changeset	1568 context->frame++;
d8a1fdec68fc Fix frame counter increment and VINT cycle time calculation Michael Pavone <pavone@retrodev.com> parents: 697 diff changeset	1569 }
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1570 } else if (context->hslot == 148) {
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1571 context->hslot = 233;
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1572 }
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1573 }
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1574
717 22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	1575 } else {
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	1576 vdp_advance_line(context);
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1577 }
623 66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	1578 context->vcounter &= 0x1FF;
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	1579 if (context->flags2 & FLAG2_REGION_PAL) {
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	1580 if (context->latched_mode & BIT_PAL) {
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	1581 if (context->vcounter == 0x10B) {
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	1582 context->vcounter = 0x1D2;
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	1583 }
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	1584 } else if (context->vcounter == 0x103){
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	1585 context->vcounter = 0x1CA;
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	1586 }
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	1587 } else if (!(context->latched_mode & BIT_PAL) && context->vcounter == 0xEB) {
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	1588 context->vcounter = 0x1E5;
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1589 }
717 22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	1590
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1591 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1592 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1593
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1594 uint32_t vdp_run_to_vblank(vdp_context * context)
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1595 {
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1596 uint32_t target_cycles = ((context->latched_mode & BIT_PAL) ? PAL_INACTIVE_START : NTSC_INACTIVE_START) * MCLKS_LINE;
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1597 vdp_run_context(context, target_cycles);
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1598 return context->cycles;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1599 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1600
75 108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	1601 void vdp_run_dma_done(vdp_context * context, uint32_t target_cycles)
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	1602 {
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	1603 for(;;) {
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	1604 uint32_t dmalen = (context->regs[REG_DMALEN_H] << 8) \| context->regs[REG_DMALEN_L];
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	1605 if (!dmalen) {
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	1606 dmalen = 0x10000;
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	1607 }
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1608 uint32_t min_dma_complete = dmalen * (context->regs[REG_MODE_4] & BIT_H40 ? 16 : 20);
75 108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	1609 if ((context->regs[REG_DMASRC_H] & 0xC0) == 0xC0 \|\| (context->cd & 0xF) == VRAM_WRITE) {
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	1610 //DMA copies take twice as long to complete since they require a read and a write
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	1611 //DMA Fills and transfers to VRAM also take twice as long as it requires 2 writes for a single word
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	1612 min_dma_complete *= 2;
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	1613 }
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	1614 min_dma_complete += context->cycles;
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	1615 if (target_cycles < min_dma_complete) {
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	1616 vdp_run_context(context, target_cycles);
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	1617 return;
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	1618 } else {
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	1619 vdp_run_context(context, min_dma_complete);
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	1620 if (!(context->flags & FLAG_DMA_RUN)) {
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	1621 return;
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	1622 }
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	1623 }
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	1624 }
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	1625 }
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	1626
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	1627 int vdp_control_port_write(vdp_context * context, uint16_t value)
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1628 {
471 f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	1629 //printf("control port write: %X at %d\n", value, context->cycles);
149 139e5dcd6aa3 Make writes to control and data port block when DMA is in progress Mike Pavone <pavone@retrodev.com> parents: 143 diff changeset	1630 if (context->flags & FLAG_DMA_RUN) {
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress Mike Pavone <pavone@retrodev.com> parents: 143 diff changeset	1631 return -1;
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress Mike Pavone <pavone@retrodev.com> parents: 143 diff changeset	1632 }
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1633 if (context->flags & FLAG_PENDING) {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1634 context->address = (context->address & 0x3FFF) \| (value << 14);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1635 context->cd = (context->cd & 0x3) \| ((value >> 2) & 0x3C);
75 108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	1636 context->flags &= ~FLAG_PENDING;
453 b491df8bdbc0 Adjust VBLANK flag and refresh timing to be in line with logic analyzer and visual observations of direct color DMA demos. Remove debug print statements. Mike Pavone <pavone@retrodev.com> parents: 452 diff changeset	1637 //printf("New Address: %X, New CD: %X\n", context->address, context->cd);
327 1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	1638 if (context->cd & 0x20 && (context->regs[REG_MODE_2] & BIT_DMA_ENABLE)) {
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	1639 //
75 108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	1640 if((context->regs[REG_DMASRC_H] & 0xC0) != 0x80) {
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	1641 //DMA copy or 68K -> VDP, transfer starts immediately
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	1642 context->flags \|= FLAG_DMA_RUN;
131 8fc8e46be691 Fix bug that was causing DMA fills to lock up under certain circumstances Mike Pavone <pavone@retrodev.com> parents: 109 diff changeset	1643 context->dma_cd = context->cd;
717 22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	1644 //printf("DMA start (length: %X) at cycle %d, frame: %d, vcounter: %d, hslot: %d\n", (context->regs[REG_DMALEN_H] << 8) \| context->regs[REG_DMALEN_L], context->cycles, context->frame, context->vcounter, context->hslot);
75 108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	1645 if (!(context->regs[REG_DMASRC_H] & 0x80)) {
327 1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	1646 //printf("DMA Address: %X, New CD: %X, Source: %X, Length: %X\n", context->address, context->cd, (context->regs[REG_DMASRC_H] << 17) \| (context->regs[REG_DMASRC_M] << 9) \| (context->regs[REG_DMASRC_L] << 1), context->regs[REG_DMALEN_H] << 8 \| context->regs[REG_DMALEN_L]);
75 108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	1647 return 1;
327 1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	1648 } else {
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	1649 //printf("DMA Copy Address: %X, New CD: %X, Source: %X\n", context->address, context->cd, (context->regs[REG_DMASRC_M] << 8) \| context->regs[REG_DMASRC_L]);
75 108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	1650 }
327 1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	1651 } else {
453 b491df8bdbc0 Adjust VBLANK flag and refresh timing to be in line with logic analyzer and visual observations of direct color DMA demos. Remove debug print statements. Mike Pavone <pavone@retrodev.com> parents: 452 diff changeset	1652 //printf("DMA Fill Address: %X, New CD: %X\n", context->address, context->cd);
75 108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	1653 }
63 a6dd5b7a971b Add FPS counter to console output Mike Pavone <pavone@retrodev.com> parents: 58 diff changeset	1654 }
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1655 } else {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1656 if ((value & 0xC000) == 0x8000) {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1657 //Register write
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1658 uint8_t reg = (value >> 8) & 0x1F;
475 50e0cb475294 Don't allow register writes to regs above when in Mode 4 Mike Pavone <pavone@retrodev.com> parents: 474 diff changeset	1659 if (reg < (context->regs[REG_MODE_2] & BIT_MODE_5 ? VDP_REGS : 0xA)) {
453 b491df8bdbc0 Adjust VBLANK flag and refresh timing to be in line with logic analyzer and visual observations of direct color DMA demos. Remove debug print statements. Mike Pavone <pavone@retrodev.com> parents: 452 diff changeset	1660 //printf("register %d set to %X\n", reg, value & 0xFF);
480 0737953132ad Implement HV counter latch Mike Pavone <pavone@retrodev.com> parents: 479 diff changeset	1661 if (reg == REG_MODE_1 && (value & BIT_HVC_LATCH) && !(context->regs[reg] & BIT_HVC_LATCH)) {
0737953132ad Implement HV counter latch Mike Pavone <pavone@retrodev.com> parents: 479 diff changeset	1662 context->hv_latch = vdp_hv_counter_read(context);
0737953132ad Implement HV counter latch Mike Pavone <pavone@retrodev.com> parents: 479 diff changeset	1663 }
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	1664 if (reg == REG_BG_COLOR) {
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	1665 value &= 0x3F;
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	1666 }
717 22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	1667 if (reg == REG_MODE_4 && ((value ^ context->regs[reg]) & BIT_H40)) {
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	1668 printf("Mode changed from H%d to H%d @ %d, frame: %d\n", context->regs[reg] & BIT_H40 ? 40 : 32, value & BIT_H40 ? 40 : 32, context->cycles, context->frame);
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	1669 }
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1670 context->regs[reg] = value;
413 36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	1671 if (reg == REG_MODE_4) {
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	1672 context->double_res = (value & (BIT_INTERLACE \| BIT_DOUBLE_RES)) == (BIT_INTERLACE \| BIT_DOUBLE_RES);
415 8c60c8c09a0f Fix sprite y mask in interlace mode. Fix framebuffer selection when switching out of interlace mode. Mike Pavone <pavone@retrodev.com> parents: 414 diff changeset	1673 if (!context->double_res) {
8c60c8c09a0f Fix sprite y mask in interlace mode. Fix framebuffer selection when switching out of interlace mode. Mike Pavone <pavone@retrodev.com> parents: 414 diff changeset	1674 context->framebuf = context->oddbuf;
8c60c8c09a0f Fix sprite y mask in interlace mode. Fix framebuffer selection when switching out of interlace mode. Mike Pavone <pavone@retrodev.com> parents: 414 diff changeset	1675 }
680 4996369f1463 Some small synchronization improvements that do not seem to fix anything Michael Pavone <pavone@retrodev.com> parents: 678 diff changeset	1676 }
476 5d7bc113653b Clear the low 2 bits of CD when a register is written to Mike Pavone <pavone@retrodev.com> parents: 475 diff changeset	1677 context->cd &= 0x3C;
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1678 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1679 } else {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1680 context->flags \|= FLAG_PENDING;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1681 context->address = (context->address &0xC000) \| (value & 0x3FFF);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1682 context->cd = (context->cd &0x3C) \| (value >> 14);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1683 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1684 }
75 108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	1685 return 0;
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1686 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1687
149 139e5dcd6aa3 Make writes to control and data port block when DMA is in progress Mike Pavone <pavone@retrodev.com> parents: 143 diff changeset	1688 int vdp_data_port_write(vdp_context * context, uint16_t value)
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1689 {
471 f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	1690 //printf("data port write: %X at %d\n", value, context->cycles);
460 788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	1691 if (context->flags & FLAG_DMA_RUN && (context->regs[REG_DMASRC_H] & 0xC0) != 0x80) {
149 139e5dcd6aa3 Make writes to control and data port block when DMA is in progress Mike Pavone <pavone@retrodev.com> parents: 143 diff changeset	1692 return -1;
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress Mike Pavone <pavone@retrodev.com> parents: 143 diff changeset	1693 }
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1694 context->flags &= ~FLAG_PENDING;
109 004dd46e0a97 COmment out fifo full debug printf Mike Pavone <pavone@retrodev.com> parents: 108 diff changeset	1695 /*if (context->fifo_cur == context->fifo_end) {
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1696 printf("FIFO full, waiting for space before next write at cycle %X\n", context->cycles);
109 004dd46e0a97 COmment out fifo full debug printf Mike Pavone <pavone@retrodev.com> parents: 108 diff changeset	1697 }*/
460 788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	1698 if (context->cd & 0x20 && (context->regs[REG_DMASRC_H] & 0xC0) == 0x80) {
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	1699 context->flags &= ~FLAG_DMA_RUN;
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	1700 }
471 f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	1701 while (context->fifo_write == context->fifo_read) {
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1702 vdp_run_context(context, context->cycles + ((context->regs[REG_MODE_4] & BIT_H40) ? 16 : 20));
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1703 }
471 f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	1704 fifo_entry * cur = context->fifo + context->fifo_write;
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1705 cur->cycle = context->cycles + ((context->regs[REG_MODE_4] & BIT_H40) ? 16 : 20)*FIFO_LATENCY;
471 f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	1706 cur->address = context->address;
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	1707 cur->value = value;
460 788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	1708 if (context->cd & 0x20 && (context->regs[REG_DMASRC_H] & 0xC0) == 0x80) {
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	1709 context->flags \|= FLAG_DMA_RUN;
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	1710 }
471 f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	1711 cur->cd = context->cd;
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	1712 cur->partial = 0;
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	1713 if (context->fifo_read < 0) {
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	1714 context->fifo_read = context->fifo_write;
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	1715 }
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	1716 context->fifo_write = (context->fifo_write + 1) & (FIFO_SIZE-1);
138 aa3e1bb338c9 Fix VDP reads Mike Pavone <pavone@retrodev.com> parents: 137 diff changeset	1717 context->address += context->regs[REG_AUTOINC];
149 139e5dcd6aa3 Make writes to control and data port block when DMA is in progress Mike Pavone <pavone@retrodev.com> parents: 143 diff changeset	1718 return 0;
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1719 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1720
470 541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM. Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1721 void vdp_test_port_write(vdp_context * context, uint16_t value)
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM. Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1722 {
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM. Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1723 //TODO: implement test register
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM. Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1724 }
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM. Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1725
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1726 uint16_t vdp_control_port_read(vdp_context * context)
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1727 {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1728 context->flags &= ~FLAG_PENDING;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1729 uint16_t value = 0x3400;
471 f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	1730 if (context->fifo_read < 0) {
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1731 value \|= 0x200;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1732 }
471 f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	1733 if (context->fifo_read == context->fifo_write) {
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1734 value \|= 0x100;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1735 }
317 e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	1736 if (context->flags2 & FLAG2_VINT_PENDING) {
413 36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	1737 value \|= 0x80;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	1738 }
494 8ac0eb05642c Initial implementation of sprite overflow and sprite collision status register flags Mike Pavone <pavone@retrodev.com> parents: 481 diff changeset	1739 if (context->flags & FLAG_DOT_OFLOW) {
8ac0eb05642c Initial implementation of sprite overflow and sprite collision status register flags Mike Pavone <pavone@retrodev.com> parents: 481 diff changeset	1740 value \|= 0x40;
8ac0eb05642c Initial implementation of sprite overflow and sprite collision status register flags Mike Pavone <pavone@retrodev.com> parents: 481 diff changeset	1741 }
8ac0eb05642c Initial implementation of sprite overflow and sprite collision status register flags Mike Pavone <pavone@retrodev.com> parents: 481 diff changeset	1742 if (context->flags2 & FLAG2_SPRITE_COLLIDE) {
8ac0eb05642c Initial implementation of sprite overflow and sprite collision status register flags Mike Pavone <pavone@retrodev.com> parents: 481 diff changeset	1743 value \|= 0x20;
8ac0eb05642c Initial implementation of sprite overflow and sprite collision status register flags Mike Pavone <pavone@retrodev.com> parents: 481 diff changeset	1744 //TODO: Test when this is actually cleared
8ac0eb05642c Initial implementation of sprite overflow and sprite collision status register flags Mike Pavone <pavone@retrodev.com> parents: 481 diff changeset	1745 context->flags2 &= ~FLAG2_SPRITE_COLLIDE;
8ac0eb05642c Initial implementation of sprite overflow and sprite collision status register flags Mike Pavone <pavone@retrodev.com> parents: 481 diff changeset	1746 }
413 36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	1747 if ((context->regs[REG_MODE_4] & BIT_INTERLACE) && context->framebuf == context->oddbuf) {
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	1748 value \|= 0x10;
317 e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	1749 }
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1750 uint32_t line= context->vcounter;
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1751 uint32_t slot = context->hslot;
717 22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	1752 uint32_t inactive_start = (context->latched_mode & BIT_PAL ? PAL_INACTIVE_START : NTSC_INACTIVE_START);
647 5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events Michael Pavone <pavone@retrodev.com> parents: 629 diff changeset	1753 if (
5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events Michael Pavone <pavone@retrodev.com> parents: 629 diff changeset	1754 (
717 22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	1755 line > inactive_start
647 5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events Michael Pavone <pavone@retrodev.com> parents: 629 diff changeset	1756 && line < 0x1FF
5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events Michael Pavone <pavone@retrodev.com> parents: 629 diff changeset	1757 )
717 22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	1758 \|\| (line == inactive_start
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	1759 && (
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	1760 slot >= (context->regs[REG_MODE_4] & BIT_H40 ? VBLANK_START_H40 : VBLANK_START_H32)
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	1761 \|\| slot < (context->regs[REG_MODE_4] & BIT_H40 ? LINE_CHANGE_H40 : LINE_CHANGE_H32)
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	1762 )
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	1763 )
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	1764 \|\| (line == 0x1FF
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	1765 && slot < (context->regs[REG_MODE_4] & BIT_H40 ? VBLANK_START_H40 : VBLANK_START_H32))
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	1766 && slot >= (context->regs[REG_MODE_4] & BIT_H40 ? LINE_CHANGE_H40 : LINE_CHANGE_H32)
647 5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events Michael Pavone <pavone@retrodev.com> parents: 629 diff changeset	1767 \|\| !(context->regs[REG_MODE_2] & BIT_DISP_EN)
5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events Michael Pavone <pavone@retrodev.com> parents: 629 diff changeset	1768 ) {
318 789f2f5f2277 Implement hblank flag in status register Mike Pavone <pavone@retrodev.com> parents: 317 diff changeset	1769 value \|= 0x8;
789f2f5f2277 Implement hblank flag in status register Mike Pavone <pavone@retrodev.com> parents: 317 diff changeset	1770 }
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1771 if (context->regs[REG_MODE_4] & BIT_H40) {
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1772 if (slot < HBLANK_END_H40 \|\| slot > HBLANK_START_H40) {
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1773 value \|= 0x4;
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1774 }
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1775 } else {
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1776 if (slot < HBLANK_END_H32 \|\| slot > HBLANK_START_H32) {
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1777 value \|= 0x4;
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1778 }
318 789f2f5f2277 Implement hblank flag in status register Mike Pavone <pavone@retrodev.com> parents: 317 diff changeset	1779 }
149 139e5dcd6aa3 Make writes to control and data port block when DMA is in progress Mike Pavone <pavone@retrodev.com> parents: 143 diff changeset	1780 if (context->flags & FLAG_DMA_RUN) {
141 576f55711d8d Fix DMA in progress flag in VDP status register Mike Pavone <pavone@retrodev.com> parents: 138 diff changeset	1781 value \|= 0x2;
75 108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	1782 }
714 e29bc2918f69 Fix VDP status register PAL bit based on observations of the Titan Overdrive demo Michael Pavone <pavone@retrodev.com> parents: 711 diff changeset	1783 if (context->flags2 & FLAG2_REGION_PAL) {
317 e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	1784 value \|= 0x1;
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	1785 }
459 c49ecf575784 Revert change to VBLANK flag timing based on new direct color DMA test Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	1786 //printf("status read at cycle %d returned %X\n", context->cycles, value);
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1787 return value;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1788 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1789
470 541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM. Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1790 #define CRAM_BITS 0xEEE
474 e128e55710bd Remove read pending stuff, that had been added in an attempt to fix CRAM/VSRAM undefined bit results. Set number of bits actually saved in VSRAM to 11 Mike Pavone <pavone@retrodev.com> parents: 473 diff changeset	1791 #define VSRAM_BITS 0x7FF
471 f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	1792 #define VSRAM_DIRTY_BITS 0xF800
470 541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM. Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1793
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1794 uint16_t vdp_data_port_read(vdp_context * context)
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1795 {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1796 context->flags &= ~FLAG_PENDING;
138 aa3e1bb338c9 Fix VDP reads Mike Pavone <pavone@retrodev.com> parents: 137 diff changeset	1797 if (context->cd & 1) {
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1798 return 0;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1799 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1800 //Not sure if the FIFO should be drained before processing a read or not, but it would make sense
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1801 context->flags &= ~FLAG_UNUSED_SLOT;
474 e128e55710bd Remove read pending stuff, that had been added in an attempt to fix CRAM/VSRAM undefined bit results. Set number of bits actually saved in VSRAM to 11 Mike Pavone <pavone@retrodev.com> parents: 473 diff changeset	1802 //context->flags2 \|= FLAG2_READ_PENDING;
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1803 while (!(context->flags & FLAG_UNUSED_SLOT)) {
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1804 vdp_run_context(context, context->cycles + ((context->regs[REG_MODE_4] & BIT_H40) ? 16 : 20));
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1805 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1806 uint16_t value = 0;
138 aa3e1bb338c9 Fix VDP reads Mike Pavone <pavone@retrodev.com> parents: 137 diff changeset	1807 switch (context->cd & 0xF)
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1808 {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1809 case VRAM_READ:
472 93dc0382fd70 Fix VSRAM reads Mike Pavone <pavone@retrodev.com> parents: 471 diff changeset	1810 value = context->vdpmem[context->address & 0xFFFE] << 8;
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1811 context->flags &= ~FLAG_UNUSED_SLOT;
470 541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM. Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1812 context->flags2 \|= FLAG2_READ_PENDING;
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1813 while (!(context->flags & FLAG_UNUSED_SLOT)) {
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1814 vdp_run_context(context, context->cycles + ((context->regs[REG_MODE_4] & BIT_H40) ? 16 : 20));
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1815 }
472 93dc0382fd70 Fix VSRAM reads Mike Pavone <pavone@retrodev.com> parents: 471 diff changeset	1816 value \|= context->vdpmem[context->address \| 1];
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1817 break;
473 1358045c0bdd Implement undocumented 8-bit VRAM read Mike Pavone <pavone@retrodev.com> parents: 472 diff changeset	1818 case VRAM_READ8:
1358045c0bdd Implement undocumented 8-bit VRAM read Mike Pavone <pavone@retrodev.com> parents: 472 diff changeset	1819 value = context->vdpmem[context->address ^ 1];
1358045c0bdd Implement undocumented 8-bit VRAM read Mike Pavone <pavone@retrodev.com> parents: 472 diff changeset	1820 value \|= context->fifo[context->fifo_write].value & 0xFF00;
1358045c0bdd Implement undocumented 8-bit VRAM read Mike Pavone <pavone@retrodev.com> parents: 472 diff changeset	1821 break;
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1822 case CRAM_READ:
470 541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM. Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1823 value = context->cram[(context->address/2) & (CRAM_SIZE-1)] & CRAM_BITS;
471 f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	1824 value \|= context->fifo[context->fifo_write].value & ~CRAM_BITS;
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1825 break;
479 863e868752cf Implement funny behavior for DMA fill to CRAM and VSRAM. Return VSRAM address 0 for reads to VSRAM at >= 40 Mike Pavone <pavone@retrodev.com> parents: 478 diff changeset	1826 case VSRAM_READ: {
863e868752cf Implement funny behavior for DMA fill to CRAM and VSRAM. Return VSRAM address 0 for reads to VSRAM at >= 40 Mike Pavone <pavone@retrodev.com> parents: 478 diff changeset	1827 uint16_t address = (context->address /2) & 63;
863e868752cf Implement funny behavior for DMA fill to CRAM and VSRAM. Return VSRAM address 0 for reads to VSRAM at >= 40 Mike Pavone <pavone@retrodev.com> parents: 478 diff changeset	1828 if (address >= VSRAM_SIZE) {
863e868752cf Implement funny behavior for DMA fill to CRAM and VSRAM. Return VSRAM address 0 for reads to VSRAM at >= 40 Mike Pavone <pavone@retrodev.com> parents: 478 diff changeset	1829 address = 0;
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1830 }
479 863e868752cf Implement funny behavior for DMA fill to CRAM and VSRAM. Return VSRAM address 0 for reads to VSRAM at >= 40 Mike Pavone <pavone@retrodev.com> parents: 478 diff changeset	1831 value = context->vsram[address] & VSRAM_BITS;
863e868752cf Implement funny behavior for DMA fill to CRAM and VSRAM. Return VSRAM address 0 for reads to VSRAM at >= 40 Mike Pavone <pavone@retrodev.com> parents: 478 diff changeset	1832 value \|= context->fifo[context->fifo_write].value & VSRAM_DIRTY_BITS;
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1833 break;
479 863e868752cf Implement funny behavior for DMA fill to CRAM and VSRAM. Return VSRAM address 0 for reads to VSRAM at >= 40 Mike Pavone <pavone@retrodev.com> parents: 478 diff changeset	1834 }
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1835 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1836 context->address += context->regs[REG_AUTOINC];
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1837 return value;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1838 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1839
137 0e7e1ccc0a81 Implemented HV counter Mike Pavone <pavone@retrodev.com> parents: 135 diff changeset	1840 uint16_t vdp_hv_counter_read(vdp_context * context)
0e7e1ccc0a81 Implemented HV counter Mike Pavone <pavone@retrodev.com> parents: 135 diff changeset	1841 {
480 0737953132ad Implement HV counter latch Mike Pavone <pavone@retrodev.com> parents: 479 diff changeset	1842 if (context->regs[REG_MODE_1] & BIT_HVC_LATCH) {
0737953132ad Implement HV counter latch Mike Pavone <pavone@retrodev.com> parents: 479 diff changeset	1843 return context->hv_latch;
0737953132ad Implement HV counter latch Mike Pavone <pavone@retrodev.com> parents: 479 diff changeset	1844 }
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1845 uint32_t line= context->vcounter & 0xFF;
647 5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events Michael Pavone <pavone@retrodev.com> parents: 629 diff changeset	1846 uint32_t linecyc = context->hslot;
137 0e7e1ccc0a81 Implemented HV counter Mike Pavone <pavone@retrodev.com> parents: 135 diff changeset	1847 linecyc &= 0xFF;
413 36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	1848 if (context->double_res) {
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	1849 line <<= 1;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	1850 if (line & 0x100) {
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	1851 line \|= 1;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	1852 }
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	1853 }
137 0e7e1ccc0a81 Implemented HV counter Mike Pavone <pavone@retrodev.com> parents: 135 diff changeset	1854 return (line << 8) \| linecyc;
0e7e1ccc0a81 Implemented HV counter Mike Pavone <pavone@retrodev.com> parents: 135 diff changeset	1855 }
0e7e1ccc0a81 Implemented HV counter Mike Pavone <pavone@retrodev.com> parents: 135 diff changeset	1856
470 541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM. Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1857 uint16_t vdp_test_port_read(vdp_context * context)
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM. Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1858 {
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM. Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1859 //TODO: Find out what actually gets returned here
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM. Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1860 return 0xFFFF;
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM. Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1861 }
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM. Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1862
65 aef6302770c2 Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame. Mike Pavone <pavone@retrodev.com> parents: 63 diff changeset	1863 void vdp_adjust_cycles(vdp_context * context, uint32_t deduction)
aef6302770c2 Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame. Mike Pavone <pavone@retrodev.com> parents: 63 diff changeset	1864 {
aef6302770c2 Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame. Mike Pavone <pavone@retrodev.com> parents: 63 diff changeset	1865 context->cycles -= deduction;
717 22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	1866 if (context->pending_vint_start >= deduction) {
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	1867 context->pending_vint_start -= deduction;
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	1868 } else {
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	1869 context->pending_vint_start = 0;
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	1870 }
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	1871 if (context->pending_hint_start >= deduction) {
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	1872 context->pending_hint_start -= deduction;
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	1873 } else {
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	1874 context->pending_hint_start = 0;
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	1875 }
471 f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	1876 if (context->fifo_read >= 0) {
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	1877 int32_t idx = context->fifo_read;
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	1878 do {
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	1879 if (context->fifo[idx].cycle >= deduction) {
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	1880 context->fifo[idx].cycle -= deduction;
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	1881 } else {
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	1882 context->fifo[idx].cycle = 0;
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	1883 }
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	1884 idx = (idx+1) & (FIFO_SIZE-1);
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	1885 } while(idx != context->fifo_write);
65 aef6302770c2 Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame. Mike Pavone <pavone@retrodev.com> parents: 63 diff changeset	1886 }
aef6302770c2 Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame. Mike Pavone <pavone@retrodev.com> parents: 63 diff changeset	1887 }
aef6302770c2 Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame. Mike Pavone <pavone@retrodev.com> parents: 63 diff changeset	1888
717 22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	1889 uint32_t vdp_cycles_hslot_wrap_h40(vdp_context * context)
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	1890 {
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	1891 if (context->hslot < 183) {
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	1892 return MCLKS_LINE - context->hslot * MCLKS_SLOT_H40;
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	1893 } else if (context->hslot < HSYNC_END_H40) {
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	1894 uint32_t before_hsync = context->hslot < HSYNC_SLOT_H40 ? (HSYNC_SLOT_H40 - context->hslot) * MCLKS_SLOT_H40 : 0;
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	1895 uint32_t hsync = 0;
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	1896 for (int i = context->hslot <= HSYNC_SLOT_H40 ? 0 : context->hslot - HSYNC_SLOT_H40; i < sizeof(h40_hsync_cycles)/sizeof(uint32_t); i++)
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	1897 {
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	1898 hsync += h40_hsync_cycles[i];
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	1899 }
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	1900 uint32_t after_hsync = (256- HSYNC_END_H40) * MCLKS_SLOT_H40;
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	1901 return before_hsync + hsync + after_hsync;
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	1902 } else {
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	1903 return (256-context->hslot) * MCLKS_SLOT_H40;
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	1904 }
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	1905 }
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	1906
623 66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	1907 uint32_t vdp_cycles_next_line(vdp_context * context)
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	1908 {
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	1909 if (context->regs[REG_MODE_4] & BIT_H40) {
647 5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events Michael Pavone <pavone@retrodev.com> parents: 629 diff changeset	1910 if (context->hslot < LINE_CHANGE_H40) {
697 7f96bd1cb1be Sync fixes and logging to fix more sync issues Michael Pavone <pavone@retrodev.com> parents: 680 diff changeset	1911 return (LINE_CHANGE_H40 - context->hslot) * MCLKS_SLOT_H40;
623 66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	1912 } else {
717 22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	1913 return vdp_cycles_hslot_wrap_h40(context) + LINE_CHANGE_H40 * MCLKS_SLOT_H40;
623 66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	1914 }
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	1915 } else {
647 5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events Michael Pavone <pavone@retrodev.com> parents: 629 diff changeset	1916 if (context->hslot < LINE_CHANGE_H32) {
5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events Michael Pavone <pavone@retrodev.com> parents: 629 diff changeset	1917 return (LINE_CHANGE_H32 - context->hslot) * MCLKS_SLOT_H32;
623 66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	1918 } else if (context->hslot < 148) {
647 5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events Michael Pavone <pavone@retrodev.com> parents: 629 diff changeset	1919 return MCLKS_LINE - (context->hslot - LINE_CHANGE_H32) * MCLKS_SLOT_H32;
623 66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	1920 } else {
647 5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events Michael Pavone <pavone@retrodev.com> parents: 629 diff changeset	1921 return (256-context->hslot + LINE_CHANGE_H32) * MCLKS_SLOT_H32;
623 66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	1922 }
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	1923 }
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	1924 }
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	1925
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	1926 uint32_t vdp_cycles_to_line(vdp_context * context, uint32_t target)
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	1927 {
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	1928 uint32_t jump_start, jump_dst;
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	1929 if (context->flags2 & FLAG2_REGION_PAL) {
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	1930 if (context->latched_mode & BIT_PAL) {
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	1931 jump_start = 0x10B;
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	1932 jump_dst = 0x1D2;
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	1933 } else {
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	1934 jump_start = 0x103;
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	1935 jump_dst = 0x1CA;
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	1936 }
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	1937 } else {
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	1938 if (context->latched_mode & BIT_PAL) {
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	1939 jump_start = 0;
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	1940 jump_dst = 0;
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	1941 } else {
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	1942 jump_start = 0xEB;
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	1943 jump_dst = 0x1E5;
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	1944 }
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	1945 }
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	1946 uint32_t lines;
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	1947 if (context->vcounter < target) {
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	1948 if (target < jump_start) {
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	1949 lines = target - context->vcounter;
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	1950 } else {
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	1951 lines = jump_start - context->vcounter + target - jump_dst;
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	1952 }
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	1953 } else {
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	1954 if (context->vcounter < jump_start) {
717 22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	1955 lines = jump_start - context->vcounter + 512 - jump_dst + 1;
623 66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	1956 } else {
717 22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	1957 lines = 512 - context->vcounter + 1;
623 66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	1958 }
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	1959 if (target < jump_start) {
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	1960 lines += target;
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	1961 } else {
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	1962 lines += jump_start + target - jump_dst;
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	1963 }
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	1964 }
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	1965 return MCLKS_LINE * (lines - 1) + vdp_cycles_next_line(context);
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	1966 }
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	1967
680 4996369f1463 Some small synchronization improvements that do not seem to fix anything Michael Pavone <pavone@retrodev.com> parents: 678 diff changeset	1968 uint32_t vdp_frame_end_line(vdp_context * context)
623 66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	1969 {
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	1970 uint32_t frame_end;
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	1971 if (context->flags2 & FLAG2_REGION_PAL) {
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	1972 if (context->latched_mode & BIT_PAL) {
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	1973 frame_end = PAL_INACTIVE_START + 8;
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	1974 } else {
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	1975 frame_end = NTSC_INACTIVE_START + 8;
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	1976 }
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	1977 } else {
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	1978 if (context->latched_mode & BIT_PAL) {
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	1979 frame_end = 512;
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	1980 } else {
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	1981 frame_end = NTSC_INACTIVE_START + 8;
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	1982 }
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	1983 }
680 4996369f1463 Some small synchronization improvements that do not seem to fix anything Michael Pavone <pavone@retrodev.com> parents: 678 diff changeset	1984 return frame_end;
4996369f1463 Some small synchronization improvements that do not seem to fix anything Michael Pavone <pavone@retrodev.com> parents: 678 diff changeset	1985 }
4996369f1463 Some small synchronization improvements that do not seem to fix anything Michael Pavone <pavone@retrodev.com> parents: 678 diff changeset	1986
4996369f1463 Some small synchronization improvements that do not seem to fix anything Michael Pavone <pavone@retrodev.com> parents: 678 diff changeset	1987 uint32_t vdp_cycles_to_frame_end(vdp_context * context)
4996369f1463 Some small synchronization improvements that do not seem to fix anything Michael Pavone <pavone@retrodev.com> parents: 678 diff changeset	1988 {
4996369f1463 Some small synchronization improvements that do not seem to fix anything Michael Pavone <pavone@retrodev.com> parents: 678 diff changeset	1989 return context->cycles + vdp_cycles_to_line(context, vdp_frame_end_line(context));
4996369f1463 Some small synchronization improvements that do not seem to fix anything Michael Pavone <pavone@retrodev.com> parents: 678 diff changeset	1990 }
4996369f1463 Some small synchronization improvements that do not seem to fix anything Michael Pavone <pavone@retrodev.com> parents: 678 diff changeset	1991
317 e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	1992 uint32_t vdp_next_hint(vdp_context * context)
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	1993 {
327 1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	1994 if (!(context->regs[REG_MODE_1] & BIT_HINT_EN)) {
317 e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	1995 return 0xFFFFFFFF;
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	1996 }
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	1997 if (context->flags2 & FLAG2_HINT_PENDING) {
717 22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	1998 return context->pending_hint_start;
317 e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	1999 }
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	2000 uint32_t inactive_start = context->latched_mode & BIT_PAL ? PAL_INACTIVE_START : NTSC_INACTIVE_START;
623 66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2001 uint32_t hint_line;
708 61faa298af07 Small horizontal interrupt fixes Michael Pavone <pavone@retrodev.com> parents: 705 diff changeset	2002 if (context->vcounter + context->hint_counter >= inactive_start) {
623 66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2003 hint_line = context->regs[REG_HINT];
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2004 } else {
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2005 hint_line = context->vcounter + context->hint_counter + 1;
317 e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	2006 }
623 66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2007
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2008 return context->cycles + vdp_cycles_to_line(context, hint_line);
317 e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	2009 }
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	2010
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	2011 uint32_t vdp_next_vint(vdp_context * context)
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	2012 {
327 1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	2013 if (!(context->regs[REG_MODE_2] & BIT_VINT_EN)) {
317 e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	2014 return 0xFFFFFFFF;
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	2015 }
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	2016 if (context->flags2 & FLAG2_VINT_PENDING) {
717 22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	2017 return context->pending_vint_start;
317 e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	2018 }
623 66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2019
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2020
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2021 return vdp_next_vint_z80(context);
317 e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	2022 }
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	2023
333 f16136a3835d Update Z80 vint timing Mike Pavone <pavone@retrodev.com> parents: 332 diff changeset	2024 uint32_t vdp_next_vint_z80(vdp_context * context)
f16136a3835d Update Z80 vint timing Mike Pavone <pavone@retrodev.com> parents: 332 diff changeset	2025 {
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	2026 uint32_t inactive_start = context->latched_mode & BIT_PAL ? PAL_INACTIVE_START : NTSC_INACTIVE_START;
623 66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2027 if (context->vcounter == inactive_start) {
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2028 if (context->regs[REG_MODE_4] & BIT_H40) {
699 d8a1fdec68fc Fix frame counter increment and VINT cycle time calculation Michael Pavone <pavone@retrodev.com> parents: 697 diff changeset	2029 if (context->hslot >= LINE_CHANGE_H40) {
717 22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	2030 return context->cycles + vdp_cycles_hslot_wrap_h40(context) + VINT_SLOT_H40 * MCLKS_SLOT_H40;
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	2031 } else if (context->hslot <= VINT_SLOT_H40) {
623 66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2032 return context->cycles + (VINT_SLOT_H40 - context->hslot) * MCLKS_SLOT_H40;
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2033 }
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2034 } else {
699 d8a1fdec68fc Fix frame counter increment and VINT cycle time calculation Michael Pavone <pavone@retrodev.com> parents: 697 diff changeset	2035 if (context->hslot >= LINE_CHANGE_H32) {
623 66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2036 if (context->hslot < 148) {
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2037 return context->cycles + (VINT_SLOT_H32 + 148 - context->hslot + 256 - 233) * MCLKS_SLOT_H32;
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2038 } else {
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2039 return context->cycles + (VINT_SLOT_H32 + 256 - context->hslot) * MCLKS_SLOT_H32;
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2040 }
717 22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	2041 } else if (context->hslot <= VINT_SLOT_H32) {
623 66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2042 return context->cycles + (VINT_SLOT_H32 - context->hslot) * MCLKS_SLOT_H32;
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2043 }
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2044 }
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2045 }
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2046 int32_t cycles_to_vint = vdp_cycles_to_line(context, inactive_start);
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	2047 if (context->regs[REG_MODE_4] & BIT_H40) {
717 22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	2048 cycles_to_vint += MCLKS_LINE - (LINE_CHANGE_H40 - VINT_SLOT_H40) * MCLKS_SLOT_H40;
333 f16136a3835d Update Z80 vint timing Mike Pavone <pavone@retrodev.com> parents: 332 diff changeset	2049 } else {
699 d8a1fdec68fc Fix frame counter increment and VINT cycle time calculation Michael Pavone <pavone@retrodev.com> parents: 697 diff changeset	2050 cycles_to_vint += (VINT_SLOT_H32 + 148 - LINE_CHANGE_H32 + 256 - 233) * MCLKS_SLOT_H32;
333 f16136a3835d Update Z80 vint timing Mike Pavone <pavone@retrodev.com> parents: 332 diff changeset	2051 }
623 66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2052 return context->cycles + cycles_to_vint;
333 f16136a3835d Update Z80 vint timing Mike Pavone <pavone@retrodev.com> parents: 332 diff changeset	2053 }
f16136a3835d Update Z80 vint timing Mike Pavone <pavone@retrodev.com> parents: 332 diff changeset	2054
317 e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	2055 void vdp_int_ack(vdp_context * context, uint16_t int_num)
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	2056 {
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	2057 if (int_num == 6) {
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	2058 context->flags2 &= ~FLAG2_VINT_PENDING;
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	2059 } else if(int_num ==4) {
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	2060 context->flags2 &= ~FLAG2_HINT_PENDING;
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	2061 }
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	2062 }
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	2063

Mercurial > repos > blastem

annotate vdp.c @ 717:22dbdf50d33c