Mercurial > repos > blastem
annotate z80.cpu @ 1733:1f0a86f5e055
Implemented LDI in new Z80 core
author | Michael Pavone <pavone@retrodev.com> |
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date | Sat, 02 Feb 2019 23:02:19 -0800 |
parents | 3b286be82ea5 |
children | 88fbc4e711fd |
rev | line source |
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1706
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Initial checkin of new WIP Z80 core using CPU DSL
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1 info |
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2 prefix z80_ |
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3 opcode_size 8 |
1721
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4 extra_tables cb ed dded fded ddcb fdcb dd fd |
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5 body z80_run_op |
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6 include z80_util.c |
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7 header z80.h |
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8 |
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9 regs |
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10 main 8 b c d e h l f a |
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11 alt 8 b' c' d' e' h' l' f' a' |
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12 i 8 |
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13 r 8 |
1732
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14 rhigh 8 |
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15 iff1 8 |
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16 iff2 8 |
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17 imode 8 |
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18 sp 16 |
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19 ix 16 |
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20 iy 16 |
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21 pc 16 |
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22 wz 16 |
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23 nflag 8 |
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24 last_flag_result 8 |
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25 pvflag 8 |
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26 chflags 8 |
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27 zflag 8 |
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28 scratch1 16 |
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29 scratch2 16 |
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30 |
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31 flags |
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32 register f |
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33 S 7 sign last_flag_result.7 |
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34 Z 6 zero zflag |
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35 Y 5 bit-5 last_flag_result.5 |
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36 H 4 half-carry chflags.3 |
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37 P 2 parity pvflag |
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38 V 2 overflow pvflag |
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39 X 3 bit-3 last_flag_result.3 |
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40 N 1 none nflag |
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41 C 0 carry chflags.7 |
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42 |
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43 |
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44 z80_op_fetch |
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45 cycles 1 |
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46 add 1 r r |
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47 mov pc scratch1 |
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48 ocall read_8 |
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49 add 1 pc pc |
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50 |
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51 z80_run_op |
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52 z80_op_fetch |
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53 dispatch scratch1 |
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54 |
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55 11001011 cb_prefix |
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56 z80_op_fetch |
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57 dispatch scratch1 cb |
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58 |
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59 11011101 dd_prefix |
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60 z80_op_fetch |
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61 dispatch scratch1 dd |
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62 |
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63 11101101 ed_prefix |
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64 z80_op_fetch |
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65 dispatch scratch1 ed |
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66 |
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67 11111101 fd_prefix |
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68 z80_op_fetch |
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69 dispatch scratch1 fd |
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70 |
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71 dd 11001011 ddcb_prefix |
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72 z80_calc_index ix |
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73 cycles 2 |
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74 mov pc scratch1 |
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75 ocall read_8 |
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76 add 1 pc pc |
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77 dispatch scratch1 ddcb |
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78 |
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79 fd 11001011 fdcb_prefix |
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80 z80_calc_index iy |
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81 cycles 2 |
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82 mov pc scratch1 |
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83 ocall read_8 |
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84 add 1 pc pc |
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85 dispatch scratch1 fdcb |
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86 |
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87 z80_check_cond |
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88 arg cond 8 |
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89 local invert 8 |
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90 switch cond |
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91 case 0 |
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92 meta istrue invert |
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93 lnot zflag invert |
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94 |
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95 case 1 |
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96 meta istrue zflag |
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97 |
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98 case 2 |
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99 meta istrue invert |
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100 not chflags invert |
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101 and 0x80 invert invert |
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102 |
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103 case 3 |
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104 meta istrue invert |
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105 and 0x80 chflags invert |
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106 |
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107 case 4 |
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108 meta istrue invert |
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109 lnot pvflag invert |
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110 |
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111 case 5 |
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112 meta istrue pvflag |
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113 |
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114 case 6 |
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115 meta istrue invert |
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116 not last_flag_result invert |
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117 and 0x80 invert invert |
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118 |
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119 case 7 |
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120 meta istrue invert |
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121 and 0x80 last_flag_result invert |
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122 |
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123 end |
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124 |
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125 z80_fetch_hl |
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diff
changeset
|
126 lsl h 8 scratch1 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
127 or l scratch1 scratch1 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
128 ocall read_8 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
129 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
130 z80_store_hl |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
131 lsl h 8 scratch2 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
132 or l scratch2 scratch2 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
133 ocall write_8 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
134 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
135 z80_fetch_immed |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
136 mov pc scratch1 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
137 ocall read_8 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
138 add 1 pc pc |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
139 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
140 z80_fetch_immed16 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
141 mov pc scratch1 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
142 ocall read_8 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
143 mov scratch1 wz |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
144 add 1 pc pc |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
145 mov pc scratch1 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
146 ocall read_8 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
147 add 1 pc pc |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
148 lsl scratch1 8 scratch1 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
149 or scratch1 wz wz |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
150 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
151 z80_fetch_immed_reg16 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
152 mov pc scratch1 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
153 ocall read_8 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
154 mov scratch1 low |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
155 add 1 pc pc |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
156 mov pc scratch1 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
157 ocall read_8 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
158 mov scratch1 high |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
159 add 1 pc pc |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
160 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
161 z80_fetch_immed_to_reg16 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
162 mov pc scratch1 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
163 ocall read_8 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
164 mov scratch1 reg |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
165 add 1 pc pc |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
166 mov pc scratch1 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
167 ocall read_8 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
168 add 1 pc pc |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
169 lsl scratch1 8 scratch1 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
170 or scratch1 reg reg |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
171 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
172 01RRR110 ld_from_hl |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
173 z80_fetch_hl |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
174 mov scratch1 main.R |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
175 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
176 01DDDSSS ld_from_reg |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
177 mov main.S main.D |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
178 |
1730
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
179 dd 01DDD100 ld_from_ixh |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
180 invalid D 6 |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
181 lsr ix 8 main.D |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
182 |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
183 dd 01100SSS ld_to_ixh |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
184 invalid S 6 |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
185 local tmp 16 |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
186 and 0xFF ix ix |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
187 lsl main.S 8 tmp |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
188 or tmp ix ix |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
189 |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
190 dd 0110D10S ld_ixb_to_ixb |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
191 |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
192 dd 01DDD101 ld_from_ixl |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
193 invalid D 6 |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
194 mov ix main.D |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
195 |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
196 dd 01101SSS ld_to_ixl |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
197 invalid S 6 |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
198 and 0xFF00 ix ix |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
199 or main.S ix ix |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
200 |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
201 dd 01100101 ld_ixl_to_ixh |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
202 local tmp 16 |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
203 lsl ix 8 tmp |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
204 and 0xFF ix ix |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
205 or tmp ix ix |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
206 |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
207 dd 01101100 ld_ixh_to_ixl |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
208 local tmp 16 |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
209 lsr ix 8 tmp |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
210 and 0xFF00 ix ix |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
211 or tmp ix ix |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
212 |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
213 fd 01DDD100 ld_from_iyh |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
214 invalid D 6 |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
215 lsr iy 8 main.D |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
216 |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
217 fd 01100SSS ld_to_iyh |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
218 invalid S 6 |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
219 local tmp 16 |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
220 and 0xFF iy iy |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
221 lsl main.S 8 tmp |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
222 or tmp iy iy |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
223 |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
224 fd 0110D10S ld_iyb_to_iyb |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
225 |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
226 fd 01DDD101 ld_from_iyl |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
227 invalid D 6 |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
228 mov iy main.D |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
229 |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
230 fd 01101SSS ld_to_iyl |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
231 invalid S 6 |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
232 and 0xFF00 iy iy |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
233 or main.S iy iy |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
234 |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
235 fd 01100101 ld_iyl_to_iyh |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
236 local tmp 16 |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
237 lsl iy 8 tmp |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
238 and 0xFF iy iy |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
239 or tmp iy iy |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
240 |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
241 fd 01101100 ld_iyh_to_iyl |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
242 local tmp 16 |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
243 lsr iy 8 tmp |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
244 and 0xFF00 iy iy |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
245 or tmp iy iy |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
246 |
1717
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
247 z80_calc_index |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
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|
248 arg index 16 |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
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parents:
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|
249 mov index wz |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
250 z80_fetch_immed |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
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changeset
|
251 sext 16 scratch1 scratch1 |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
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changeset
|
252 add scratch1 wz wz |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
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parents:
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changeset
|
253 |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
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changeset
|
254 z80_fetch_index |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
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parents:
1715
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changeset
|
255 arg index 16 |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
256 z80_calc_index index |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
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changeset
|
257 mov wz scratch1 |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
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parents:
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changeset
|
258 cycles 5 |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
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changeset
|
259 ocall read_8 |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
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changeset
|
260 |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
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diff
changeset
|
261 z80_store_index |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
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changeset
|
262 mov wz scratch2 |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
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parents:
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changeset
|
263 ocall write_8 |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
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changeset
|
264 |
1706
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
265 dd 01RRR110 ld_from_ix |
1717
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
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changeset
|
266 z80_fetch_index ix |
1706
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
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parents:
diff
changeset
|
267 mov scratch1 main.R |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
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parents:
diff
changeset
|
268 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
269 fd 01RRR110 ld_from_iy |
1717
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
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changeset
|
270 z80_fetch_index iy |
1706
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
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parents:
diff
changeset
|
271 mov scratch1 main.R |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
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parents:
diff
changeset
|
272 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
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parents:
diff
changeset
|
273 00RRR110 ld_immed |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
274 z80_fetch_immed |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
275 mov scratch1 main.R |
1730
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
276 |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
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changeset
|
277 dd 00100110 ld_immed_ixh |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
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diff
changeset
|
278 z80_fetch_immed |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
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parents:
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changeset
|
279 lsl scratch1 8 scratch1 |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
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changeset
|
280 and 0xFF ix ix |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
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diff
changeset
|
281 or scratch1 ix ix |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
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diff
changeset
|
282 |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
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changeset
|
283 dd 00101110 ld_immed_ixl |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
284 z80_fetch_immed |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
285 and 0xFF00 ix ix |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
286 or scratch1 ix ix |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
287 |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
288 fd 00100110 ld_immed_iyh |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
289 z80_fetch_immed |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
290 lsl scratch1 8 scratch1 |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
291 and 0xFF iy iy |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
292 or scratch1 iy iy |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
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diff
changeset
|
293 |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
294 fd 00101110 ld_immed_iyl |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
295 z80_fetch_immed |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
296 and 0xFF00 iy iy |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
297 or scratch1 iy iy |
1706
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
298 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
299 01110RRR ld_to_hl |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
300 mov main.R scratch1 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
301 z80_store_hl |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
302 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
303 dd 01110RRR ld_to_ix |
1717
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
304 z80_calc_index ix |
1706
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
305 mov wz scratch2 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
306 mov main.R scratch1 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
307 ocall write_8 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
308 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
309 fd 01110RRR ld_to_iy |
1717
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
310 z80_calc_index iy |
1706
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
311 mov wz scratch2 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
312 mov main.R scratch1 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
313 ocall write_8 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
314 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
315 00110110 ld_to_hl_immed |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
316 z80_fetch_immed |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
317 z80_store_hl |
1730
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
318 |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
319 dd 00110110 ld_to_ixd_immed |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
320 z80_calc_index ix |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
321 z80_fetch_immed |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
322 cycles 2 |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
323 mov wz scratch2 |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
324 ocall write_8 |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
325 |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
326 fd 00110110 ld_to_iyd_immed |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
327 z80_calc_index iy |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
328 z80_fetch_immed |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
329 cycles 2 |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
330 mov wz scratch2 |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
331 ocall write_8 |
1706
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
332 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
333 00001010 ld_a_from_bc |
1727
9ea0b4cc8f02
Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents:
1726
diff
changeset
|
334 lsl b 8 wz |
9ea0b4cc8f02
Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents:
1726
diff
changeset
|
335 or c wz wz |
9ea0b4cc8f02
Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents:
1726
diff
changeset
|
336 mov wz scratch1 |
9ea0b4cc8f02
Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents:
1726
diff
changeset
|
337 add 1 wz wz |
1706
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
338 ocall read_8 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
339 mov scratch1 a |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
340 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
341 00011010 ld_a_from_de |
1727
9ea0b4cc8f02
Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents:
1726
diff
changeset
|
342 lsl d 8 wz |
9ea0b4cc8f02
Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents:
1726
diff
changeset
|
343 or e wz wz |
9ea0b4cc8f02
Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents:
1726
diff
changeset
|
344 mov wz scratch1 |
9ea0b4cc8f02
Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents:
1726
diff
changeset
|
345 add 1 wz wz |
1724
9a74c2d05672
Fixed a few ld instructions in the new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1723
diff
changeset
|
346 ocall read_8 |
1706
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
347 mov scratch1 a |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
348 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
349 00111010 ld_a_from_immed |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
350 z80_fetch_immed16 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
351 mov wz scratch1 |
1727
9ea0b4cc8f02
Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents:
1726
diff
changeset
|
352 add 1 wz wz |
1706
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
353 ocall read_8 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
354 mov scratch1 a |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
355 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
356 00000010 ld_a_to_bc |
1727
9ea0b4cc8f02
Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents:
1726
diff
changeset
|
357 local tmp 8 |
1706
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
358 lsl b 8 scratch2 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
359 or c scratch2 scratch2 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
360 mov a scratch1 |
1727
9ea0b4cc8f02
Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents:
1726
diff
changeset
|
361 add c 1 tmp |
9ea0b4cc8f02
Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents:
1726
diff
changeset
|
362 lsl a 8 wz |
9ea0b4cc8f02
Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents:
1726
diff
changeset
|
363 or tmp wz wz |
1706
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
364 ocall write_8 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
365 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
366 00010010 ld_a_to_de |
1727
9ea0b4cc8f02
Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents:
1726
diff
changeset
|
367 local tmp 8 |
1706
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
368 lsl d 8 scratch2 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
369 or e scratch2 scratch2 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
370 mov a scratch1 |
1727
9ea0b4cc8f02
Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents:
1726
diff
changeset
|
371 add e 1 tmp |
9ea0b4cc8f02
Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents:
1726
diff
changeset
|
372 lsl a 8 wz |
9ea0b4cc8f02
Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents:
1726
diff
changeset
|
373 or tmp wz wz |
1706
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
374 ocall write_8 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
375 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
376 00110010 ld_a_to_immed |
1727
9ea0b4cc8f02
Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents:
1726
diff
changeset
|
377 local tmp 16 |
1706
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
378 z80_fetch_immed16 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
379 mov wz scratch2 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
380 mov a scratch1 |
1727
9ea0b4cc8f02
Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents:
1726
diff
changeset
|
381 add 1 wz wz |
1706
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
382 ocall write_8 |
1727
9ea0b4cc8f02
Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents:
1726
diff
changeset
|
383 and 0xFF wz wz |
9ea0b4cc8f02
Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents:
1726
diff
changeset
|
384 lsl a 8 tmp |
9ea0b4cc8f02
Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents:
1726
diff
changeset
|
385 or tmp wz wz |
1706
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
386 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
387 ed 01000111 ld_i_a |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
388 mov a i |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
389 cycles 1 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
390 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
391 ed 01001111 ld_r_a |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
392 mov a r |
1732
3b286be82ea5
Implemented ld a,r and ld a,i in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1731
diff
changeset
|
393 and 0x80 a rhigh |
1706
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
394 cycles 1 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
395 |
1732
3b286be82ea5
Implemented ld a,r and ld a,i in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1731
diff
changeset
|
396 ed 01011111 ld_a_r |
3b286be82ea5
Implemented ld a,r and ld a,i in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1731
diff
changeset
|
397 cycles 1 |
3b286be82ea5
Implemented ld a,r and ld a,i in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1731
diff
changeset
|
398 and 0x7F r a |
3b286be82ea5
Implemented ld a,r and ld a,i in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1731
diff
changeset
|
399 or rhigh a a |
3b286be82ea5
Implemented ld a,r and ld a,i in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1731
diff
changeset
|
400 update_flags SZYH0XN0 |
3b286be82ea5
Implemented ld a,r and ld a,i in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1731
diff
changeset
|
401 mov iff2 pvflag |
3b286be82ea5
Implemented ld a,r and ld a,i in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1731
diff
changeset
|
402 |
3b286be82ea5
Implemented ld a,r and ld a,i in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1731
diff
changeset
|
403 ed 01010111 ld_a_i |
3b286be82ea5
Implemented ld a,r and ld a,i in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1731
diff
changeset
|
404 cycles 1 |
3b286be82ea5
Implemented ld a,r and ld a,i in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1731
diff
changeset
|
405 mov i a |
3b286be82ea5
Implemented ld a,r and ld a,i in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1731
diff
changeset
|
406 update_flags SZYH0XN0 |
3b286be82ea5
Implemented ld a,r and ld a,i in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1731
diff
changeset
|
407 mov iff2 pvflag |
3b286be82ea5
Implemented ld a,r and ld a,i in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1731
diff
changeset
|
408 |
1706
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
409 00000001 ld_bc_immed |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
410 meta high b |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
411 meta low c |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
412 z80_fetch_immed_reg16 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
413 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
414 00010001 ld_de_immed |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
415 meta high d |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
416 meta low e |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
417 z80_fetch_immed_reg16 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
418 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
419 00100001 ld_hl_immed |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
420 meta high h |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
421 meta low l |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
422 z80_fetch_immed_reg16 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
423 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
424 00110001 ld_sp_immed |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
425 meta reg sp |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
426 z80_fetch_immed_to_reg16 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
427 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
428 dd 00100001 ld_ix_immed |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
429 meta reg ix |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
430 z80_fetch_immed_to_reg16 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
431 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
432 fd 00100001 ld_iy_immed |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
433 meta reg iy |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
434 z80_fetch_immed_to_reg16 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
435 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
436 z80_fetch16_from_immed |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
437 z80_fetch_immed16 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
438 mov wz scratch1 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
439 ocall read_8 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
440 mov scratch1 low |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
441 add 1 wz wz |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
442 mov wz scratch1 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
443 ocall read_8 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
444 mov scratch1 high |
1727
9ea0b4cc8f02
Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents:
1726
diff
changeset
|
445 add 1 wz wz |
1706
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
446 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
447 00101010 ld_hl_from_immed |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
448 meta low l |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
449 meta high h |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
450 z80_fetch16_from_immed |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
451 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
452 ed 01001011 ld_bc_from_immed |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
453 meta low c |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
454 meta high b |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
455 z80_fetch16_from_immed |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
456 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
457 ed 01011011 ld_de_from_immed |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
458 meta low e |
1724
9a74c2d05672
Fixed a few ld instructions in the new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1723
diff
changeset
|
459 meta high d |
1706
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
460 z80_fetch16_from_immed |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
461 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
462 ed 01101011 ld_hl_from_immed_slow |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
463 meta low l |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
464 meta high h |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
465 z80_fetch16_from_immed |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
466 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
467 z80_fetch_reg16_from_immed |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
468 z80_fetch_immed16 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
469 mov wz scratch1 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
470 ocall read_8 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
471 mov scratch1 reg |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
472 add 1 wz wz |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
473 mov wz scratch1 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
474 ocall read_8 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
475 lsl scratch1 8 scratch1 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
476 or scratch1 reg reg |
1727
9ea0b4cc8f02
Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents:
1726
diff
changeset
|
477 add 1 wz wz |
1706
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
478 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
479 ed 01111011 ld_sp_from_immed |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
480 meta reg sp |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
481 z80_fetch_reg16_from_immed |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
482 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
483 dd 00101010 ld_ix_from_immed |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
484 meta reg ix |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
485 z80_fetch_reg16_from_immed |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
486 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
487 fd 00101010 ld_iy_from_immed |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
488 meta reg iy |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
489 z80_fetch_reg16_from_immed |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
490 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
491 00100010 ld_hl_to_immed |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
492 z80_fetch_immed16 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
493 mov wz scratch2 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
494 mov l scratch1 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
495 ocall write_8 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
496 add 1 wz wz |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
497 mov wz scratch2 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
498 mov h scratch1 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
499 ocall write_8 |
1727
9ea0b4cc8f02
Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents:
1726
diff
changeset
|
500 add 1 wz wz |
1706
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
501 |
1730
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
502 dd 00100010 ld_ix_to_immed |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
503 z80_fetch_immed16 |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
504 mov wz scratch2 |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
505 mov ix scratch1 |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
506 ocall write_8 |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
507 add 1 wz wz |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
508 mov wz scratch2 |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
509 lsr ix 8 scratch1 |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
510 ocall write_8 |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
511 add 1 wz wz |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
512 |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
513 fd 00100010 ld_iy_to_immed |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
514 z80_fetch_immed16 |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
515 mov wz scratch2 |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
516 mov iy scratch1 |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
517 ocall write_8 |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
518 add 1 wz wz |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
519 mov wz scratch2 |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
520 lsr iy 8 scratch1 |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
521 ocall write_8 |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
522 add 1 wz wz |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
523 |
1706
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
524 z80_regpair_to_immed |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
525 z80_fetch_immed16 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
526 mov wz scratch2 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
527 mov low scratch1 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
528 ocall write_8 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
529 add 1 wz wz |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
530 mov high scratch1 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
531 mov wz scratch2 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
532 ocall write_8 |
1727
9ea0b4cc8f02
Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents:
1726
diff
changeset
|
533 add 1 wz wz |
1706
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
534 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
535 ed 01000011 ld_bc_to_immed |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
536 meta low c |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
537 meta high b |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
538 z80_regpair_to_immed |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
539 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
540 ed 01010011 ld_de_to_immed |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
541 meta low e |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
542 meta high d |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
543 z80_regpair_to_immed |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
544 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
545 ed 01100011 ld_hl_to_immed_slow |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
546 meta low l |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
547 meta high h |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
548 z80_regpair_to_immed |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
549 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
550 ed 01110011 ld_sp_to_immed |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
551 meta low sp |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
552 local sph 8 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
553 lsr sp 8 sph |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
554 meta high sph |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
555 z80_regpair_to_immed |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
556 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
557 11111001 ld_sp_hl |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
558 cycles 2 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
559 lsl h 8 sp |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
560 or l sp sp |
1730
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
561 |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
562 dd 11111001 ld_sp_ix |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
563 cycles 2 |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
564 mov ix sp |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
565 |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
566 fd 11111001 ld_sp_iy |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
567 cycles 2 |
71f7827ff30a
Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1729
diff
changeset
|
568 mov iy sp |
1706
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
569 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
570 z80_push |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
571 cycles 1 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
572 sub 1 sp sp |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
573 mov sp scratch2 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
574 mov high scratch1 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
575 ocall write_8 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
576 sub 1 sp sp |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
577 mov sp scratch2 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
578 mov low scratch1 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
579 ocall write_8 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
580 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
581 11000101 push_bc |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
582 meta high b |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
583 meta low c |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
584 z80_push |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
585 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
586 11010101 push_de |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
587 meta high d |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
588 meta low e |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
589 z80_push |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
590 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
591 11100101 push_hl |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
592 meta high h |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
593 meta low l |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
594 z80_push |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
595 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
596 11110101 push_af |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
597 meta high a |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
598 meta low f |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
599 z80_push |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
600 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
601 dd 11100101 push_ix |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
602 local ixh 8 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
603 lsr ix 8 ixh |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
604 meta high ixh |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
605 meta low ix |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
606 z80_push |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
607 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
608 fd 11100101 push_iy |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
609 local iyh 8 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
610 lsr iy 8 iyh |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
611 meta high iyh |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
612 meta low iy |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
613 z80_push |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
614 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
615 z80_pop |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
616 mov sp scratch1 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
617 ocall read_8 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
618 add 1 sp sp |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
619 mov scratch1 low |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
620 mov sp scratch1 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
621 ocall read_8 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
622 add 1 sp sp |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
623 mov scratch1 high |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
624 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
625 11000001 pop_bc |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
626 meta high b |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
627 meta low c |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
628 z80_pop |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
629 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
630 11010001 pop_de |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
631 meta high d |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
632 meta low e |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
633 z80_pop |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
634 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
635 11100001 pop_hl |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
636 meta high h |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
637 meta low l |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
638 z80_pop |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
639 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
640 11110001 pop_af |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
641 meta high a |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
642 meta low f |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
643 z80_pop |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
644 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
645 dd 11100001 pop_ix |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
646 local ixh 16 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
647 meta high ixh |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
648 meta low ix |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
649 z80_pop |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
650 lsl ixh 8 ixh |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
651 or ixh ix ix |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
652 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
653 fd 11100001 pop_iy |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
654 local iyh 16 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
655 meta high iyh |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
656 meta low iy |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
657 z80_pop |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
658 lsl iyh 8 iyh |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
659 or iyh iy iy |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
660 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
661 11101011 ex_de_hl |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
662 xchg e l |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
663 xchg d h |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
664 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
665 00001000 ex_af_af |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
666 xchg a a' |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
667 xchg f f' |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
668 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
669 11011001 exx |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
670 xchg b b' |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
671 xchg c c' |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
672 xchg d d' |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
673 xchg e e' |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
674 xchg h h' |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
675 xchg l l' |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
676 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
677 11100011 ex_sp_hl |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
678 mov sp scratch1 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
679 ocall read_8 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
680 xchg l scratch1 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
681 cycles 1 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
682 mov sp scratch2 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
683 ocall write_8 |
1731
366b65d91614
Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1730
diff
changeset
|
684 add 1 sp scratch1 |
1706
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
685 ocall read_8 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
686 xchg h scratch1 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
687 cycles 2 |
1731
366b65d91614
Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1730
diff
changeset
|
688 add 1 sp scratch2 |
366b65d91614
Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1730
diff
changeset
|
689 ocall write_8 |
366b65d91614
Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1730
diff
changeset
|
690 lsl h 8 wz |
366b65d91614
Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1730
diff
changeset
|
691 or l wz wz |
366b65d91614
Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1730
diff
changeset
|
692 |
366b65d91614
Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1730
diff
changeset
|
693 dd 11100011 ex_sp_ix |
366b65d91614
Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1730
diff
changeset
|
694 mov sp scratch1 |
366b65d91614
Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1730
diff
changeset
|
695 ocall read_8 |
366b65d91614
Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1730
diff
changeset
|
696 mov scratch1 wz |
366b65d91614
Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1730
diff
changeset
|
697 mov ix scratch1 |
366b65d91614
Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1730
diff
changeset
|
698 cycles 1 |
366b65d91614
Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1730
diff
changeset
|
699 mov sp scratch2 |
1706
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
700 ocall write_8 |
1731
366b65d91614
Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1730
diff
changeset
|
701 add 1 sp scratch1 |
366b65d91614
Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1730
diff
changeset
|
702 ocall read_8 |
366b65d91614
Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1730
diff
changeset
|
703 lsl scratch1 8 scratch1 |
366b65d91614
Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1730
diff
changeset
|
704 or scratch1 wz wz |
366b65d91614
Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1730
diff
changeset
|
705 lsr ix 8 scratch1 |
366b65d91614
Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1730
diff
changeset
|
706 cycles 2 |
366b65d91614
Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1730
diff
changeset
|
707 add 1 sp scratch2 |
366b65d91614
Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1730
diff
changeset
|
708 ocall write_8 |
366b65d91614
Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1730
diff
changeset
|
709 mov wz ix |
366b65d91614
Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1730
diff
changeset
|
710 |
366b65d91614
Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1730
diff
changeset
|
711 fd 11100011 ex_sp_iy |
366b65d91614
Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1730
diff
changeset
|
712 mov sp scratch1 |
366b65d91614
Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1730
diff
changeset
|
713 ocall read_8 |
366b65d91614
Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1730
diff
changeset
|
714 mov scratch1 wz |
366b65d91614
Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1730
diff
changeset
|
715 mov iy scratch1 |
366b65d91614
Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1730
diff
changeset
|
716 cycles 1 |
366b65d91614
Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1730
diff
changeset
|
717 mov sp scratch2 |
366b65d91614
Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1730
diff
changeset
|
718 ocall write_8 |
366b65d91614
Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1730
diff
changeset
|
719 add 1 sp scratch1 |
366b65d91614
Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1730
diff
changeset
|
720 ocall read_8 |
366b65d91614
Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1730
diff
changeset
|
721 lsl scratch1 8 scratch1 |
366b65d91614
Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1730
diff
changeset
|
722 or scratch1 wz wz |
366b65d91614
Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1730
diff
changeset
|
723 lsr iy 8 scratch1 |
366b65d91614
Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1730
diff
changeset
|
724 cycles 2 |
366b65d91614
Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1730
diff
changeset
|
725 add 1 sp scratch2 |
366b65d91614
Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1730
diff
changeset
|
726 ocall write_8 |
366b65d91614
Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1730
diff
changeset
|
727 mov wz iy |
1706
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
728 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
729 10000RRR add_reg |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
730 add a main.R a |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
731 update_flags SZYHVXN0C |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
732 |
1718
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
733 dd 10000100 add_ixh |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
734 lsr ix 8 scratch1 |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
735 add a scratch1 a |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
736 update_flags SZYHVXN0C |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
737 |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
738 dd 10000101 add_ixl |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
739 and ix 0xFF scratch1 |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
740 add a scratch1 a |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
741 update_flags SZYHVXN0C |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
742 |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
743 fd 10000100 add_iyh |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
744 lsr iy 8 scratch1 |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
745 add a scratch1 a |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
746 update_flags SZYHVXN0C |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
747 |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
748 fd 10000101 add_iyl |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
749 and iy 0xFF scratch1 |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
750 add a scratch1 a |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
751 update_flags SZYHVXN0C |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
752 |
1706
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
753 10000110 add_hl |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
754 z80_fetch_hl |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
755 add a scratch1 a |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
756 update_flags SZYHVXN0C |
1717
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
757 |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
758 dd 10000110 add_ixd |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
759 z80_fetch_index ix |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
760 add a scratch1 a |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
761 update_flags SZYHVXN0C |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
762 |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
763 fd 10000110 add_iyd |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
764 z80_fetch_index iy |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
765 add a scratch1 a |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
766 update_flags SZYHVXN0C |
1706
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
767 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
768 11000110 add_immed |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
769 z80_fetch_immed |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
770 add a scratch1 a |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
771 update_flags SZYHVXN0C |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
772 |
1715
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1714
diff
changeset
|
773 z80_add16_hl |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1714
diff
changeset
|
774 arg src 16 |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1714
diff
changeset
|
775 lsl h 8 hlt |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1714
diff
changeset
|
776 or l hlt hlt |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1714
diff
changeset
|
777 add 1 hlt wz |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1714
diff
changeset
|
778 add src hlt hlt |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1714
diff
changeset
|
779 update_flags YHXN0C |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1714
diff
changeset
|
780 mov hlt l |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1714
diff
changeset
|
781 lsr hlt 8 h |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1714
diff
changeset
|
782 |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1714
diff
changeset
|
783 00001001 add_hl_bc |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1714
diff
changeset
|
784 local hlw 16 |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1714
diff
changeset
|
785 local bcw 16 |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1714
diff
changeset
|
786 meta hlt hlw |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1714
diff
changeset
|
787 lsl b 8 bcw |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1714
diff
changeset
|
788 or c bcw bcw |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1714
diff
changeset
|
789 z80_add16_hl bcw |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1714
diff
changeset
|
790 |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1714
diff
changeset
|
791 00011001 add_hl_de |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1714
diff
changeset
|
792 local hlw 16 |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1714
diff
changeset
|
793 local dew 16 |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1714
diff
changeset
|
794 meta hlt hlw |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1714
diff
changeset
|
795 lsl d 8 dew |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1714
diff
changeset
|
796 or e dew dew |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1714
diff
changeset
|
797 z80_add16_hl dew |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1714
diff
changeset
|
798 |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1714
diff
changeset
|
799 00101001 add_hl_hl |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1714
diff
changeset
|
800 local hlw 16 |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1714
diff
changeset
|
801 meta hlt hlw |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1714
diff
changeset
|
802 z80_add16_hl hlw |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1714
diff
changeset
|
803 |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1714
diff
changeset
|
804 00111001 add_hl_sp |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1714
diff
changeset
|
805 local hlw 16 |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1714
diff
changeset
|
806 meta hlt hlw |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1714
diff
changeset
|
807 z80_add16_hl sp |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1714
diff
changeset
|
808 |
1718
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
809 dd 00001001 add_ix_bc |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
810 lsl b 8 scratch1 |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
811 or c scratch1 scratch1 |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
812 add scratch1 ix ix |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
813 update_flags YHXN0C |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
814 |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
815 dd 00011001 add_ix_de |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
816 lsl d 8 scratch1 |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
817 or e scratch1 scratch1 |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
818 add scratch1 ix ix |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
819 update_flags YHXN0C |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
820 |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
821 dd 00101001 add_ix_ix |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
822 add ix ix ix |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
823 update_flags YHXN0C |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
824 |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
825 dd 00111001 add_ix_sp |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
826 add sp ix ix |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
827 update_flags YHXN0C |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
828 |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
829 fd 00001001 add_iy_bc |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
830 lsl b 8 scratch1 |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
831 or c scratch1 scratch1 |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
832 add scratch1 iy iy |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
833 update_flags YHXN0C |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
834 |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
835 fd 00011001 add_iy_de |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
836 lsl d 8 scratch1 |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
837 or e scratch1 scratch1 |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
838 add scratch1 iy iy |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
839 update_flags YHXN0C |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
840 |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
841 fd 00101001 add_iy_iy |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
842 add iy iy iy |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
843 update_flags YHXN0C |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
844 |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
845 fd 00111001 add_iy_sp |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
846 add sp iy iy |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
847 update_flags YHXN0C |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
848 |
1706
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
849 10001RRR adc_reg |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
850 adc a main.R a |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
851 update_flags SZYHVXN0C |
1718
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
852 |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
853 dd 10001100 adc_ixh |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
854 lsr ix 8 scratch1 |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
855 adc a scratch1 a |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
856 update_flags SZYHVXN0C |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
857 |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
858 dd 10001101 adc_ixl |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
859 and ix 0xFF scratch1 |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
860 adc a scratch1 a |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
861 update_flags SZYHVXN0C |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
862 |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
863 fd 10001100 adc_iyh |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
864 lsr iy 8 scratch1 |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
865 adc a scratch1 a |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
866 update_flags SZYHVXN0C |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
867 |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
868 fd 10001101 adc_iyl |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
869 and iy 0xFF scratch1 |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
870 adc a scratch1 a |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
871 update_flags SZYHVXN0C |
1706
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
872 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
873 10001110 adc_hl |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
874 z80_fetch_hl |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
875 adc a scratch1 a |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
876 update_flags SZYHVXN0C |
1718
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
877 |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
878 dd 10001110 adc_ixd |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
879 z80_fetch_index ix |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
880 adc a scratch1 a |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
881 update_flags SZYHVXN0C |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
882 |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
883 fd 10001110 adc_iyd |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
884 z80_fetch_index iy |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
885 adc a scratch1 a |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
886 update_flags SZYHVXN0C |
1706
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
887 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
888 11001110 adc_immed |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
889 z80_fetch_immed |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
890 adc a scratch1 a |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
891 update_flags SZYHVXN0C |
1715
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1714
diff
changeset
|
892 |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1714
diff
changeset
|
893 z80_adc16_hl |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1714
diff
changeset
|
894 arg src 16 |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1714
diff
changeset
|
895 lsl h 8 hlt |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1714
diff
changeset
|
896 or l hlt hlt |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1714
diff
changeset
|
897 add 1 hlt wz |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1714
diff
changeset
|
898 adc src hlt hlt |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1714
diff
changeset
|
899 update_flags SZYHVXN0C |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1714
diff
changeset
|
900 mov hlt l |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1714
diff
changeset
|
901 lsr hlt 8 h |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1714
diff
changeset
|
902 |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1714
diff
changeset
|
903 ed 01001010 adc_hl_bc |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1714
diff
changeset
|
904 local hlw 16 |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1714
diff
changeset
|
905 local bcw 16 |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1714
diff
changeset
|
906 meta hlt hlw |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1714
diff
changeset
|
907 lsl b 8 bcw |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1714
diff
changeset
|
908 or c bcw bcw |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1714
diff
changeset
|
909 z80_adc16_hl bcw |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1714
diff
changeset
|
910 |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1714
diff
changeset
|
911 ed 01011010 adc_hl_de |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1714
diff
changeset
|
912 local hlw 16 |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1714
diff
changeset
|
913 local dew 16 |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1714
diff
changeset
|
914 meta hlt hlw |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1714
diff
changeset
|
915 lsl d 8 dew |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1714
diff
changeset
|
916 or e dew dew |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1714
diff
changeset
|
917 z80_adc16_hl dew |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1714
diff
changeset
|
918 |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1714
diff
changeset
|
919 ed 01101010 adc_hl_hl |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1714
diff
changeset
|
920 local hlw 16 |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1714
diff
changeset
|
921 meta hlt hlw |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1714
diff
changeset
|
922 z80_adc16_hl hlw |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1714
diff
changeset
|
923 |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1714
diff
changeset
|
924 |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1714
diff
changeset
|
925 ed 01111010 adc_hl_sp |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1714
diff
changeset
|
926 local hlw 16 |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1714
diff
changeset
|
927 meta hlt hlw |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1714
diff
changeset
|
928 z80_adc16_hl sp |
1706
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
929 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
930 10010RRR sub_reg |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
931 sub main.R a a |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
932 update_flags SZYHVXN1C |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
933 |
1718
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
934 dd 10010100 sub_ixh |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
935 lsr ix 8 scratch1 |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
936 sub scratch1 a a |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
937 update_flags SZYHVXN1C |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
938 |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
939 dd 10010101 sub_ixl |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
940 and ix 0xFF scratch1 |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
941 sub scratch1 a a |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
942 update_flags SZYHVXN1C |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
943 |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
944 fd 10010100 sub_iyh |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
945 lsr iy 8 scratch1 |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
946 sub scratch1 a a |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
947 update_flags SZYHVXN1C |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
948 |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
949 fd 10010101 sub_iyl |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
950 and iy 0xFF scratch1 |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
951 sub scratch1 a a |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
952 update_flags SZYHVXN1C |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
953 |
1706
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
954 10010110 sub_hl |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
955 z80_fetch_hl |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
956 sub scratch1 a a |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
957 update_flags SZYHVXN1C |
1718
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
958 |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
959 dd 10010110 sub_ixd |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
960 z80_fetch_index ix |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
961 sub scratch1 a a |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
962 update_flags SZYHVXN1C |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
963 |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
964 fd 10010110 sub_iyd |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
965 z80_fetch_index iy |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
966 sub scratch1 a a |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
967 update_flags SZYHVXN1C |
1706
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
968 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
969 11010110 sub_immed |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
970 z80_fetch_immed |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
971 sub scratch1 a a |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
972 update_flags SZYHVXN1C |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
973 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
974 10011RRR sbc_reg |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
975 sbc main.R a a |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
976 update_flags SZYHVXN1C |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
977 |
1718
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
978 dd 10011100 sbc_ixh |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
979 lsr ix 8 scratch1 |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
980 sbc scratch1 a a |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
981 update_flags SZYHVXN1C |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
982 |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
983 dd 10011101 sbc_ixl |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
984 and ix 0xFF scratch1 |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
985 sbc scratch1 a a |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
986 update_flags SZYHVXN1C |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
987 |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
988 fd 10011100 sbc_iyh |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
989 lsr iy 8 scratch1 |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
990 sbc scratch1 a a |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
991 update_flags SZYHVXN1C |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
992 |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
993 fd 10011101 sbc_iyl |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
994 and iy 0xFF scratch1 |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
995 sbc scratch1 a a |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
996 update_flags SZYHVXN1C |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
997 |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
998 |
1706
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
999 10011110 sbc_hl |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1000 z80_fetch_hl |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1001 sbc scratch1 a a |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1002 update_flags SZYHVXN1C |
1718
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
1003 |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
1004 dd 10011110 sbc_ixd |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
1005 z80_fetch_index ix |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
1006 sbc scratch1 a a |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
1007 update_flags SZYHVXN1C |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
1008 |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
1009 fd 10011110 sbc_iyd |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
1010 z80_fetch_index iy |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
1011 sbc scratch1 a a |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
1012 update_flags SZYHVXN1C |
1706
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1013 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1014 11011110 sbc_immed |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1015 z80_fetch_immed |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1016 sbc scratch1 a a |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1017 update_flags SZYHVXN1C |
1717
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1018 |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1019 z80_sbc16_hl |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1020 arg src 16 |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1021 lsl h 8 hlt |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1022 or l hlt hlt |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1023 add 1 hlt wz |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1024 sbc src hlt hlt |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1025 update_flags SZYHVXN1C |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1026 mov hlt l |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1027 lsr hlt 8 h |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1028 |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1029 ed 01000010 sbc_hl_bc |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1030 local hlw 16 |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1031 local bcw 16 |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1032 meta hlt hlw |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1033 lsl b 8 bcw |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1034 or c bcw bcw |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1035 z80_sbc16_hl bcw |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1036 |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1037 ed 01010010 sbc_hl_de |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1038 local hlw 16 |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1039 local dew 16 |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1040 meta hlt hlw |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1041 lsl d 8 dew |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1042 or e dew dew |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1043 z80_sbc16_hl dew |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1044 |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1045 ed 01100010 sbc_hl_hl |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1046 local hlw 16 |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1047 meta hlt hlw |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1048 z80_sbc16_hl hlw |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1049 |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1050 |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1051 ed 01110010 sbc_hl_sp |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1052 local hlw 16 |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1053 meta hlt hlw |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1054 z80_sbc16_hl sp |
1706
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1055 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1056 10100RRR and_reg |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1057 and a main.R a |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1058 update_flags SZYH1PXN0C0 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1059 |
1720
1648c685083a
Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1060 dd 10100100 and_ixh |
1648c685083a
Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1061 lsr ix 8 scratch1 |
1648c685083a
Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1062 and scratch1 a a |
1648c685083a
Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1063 update_flags SZYH1PXN0C0 |
1648c685083a
Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1064 |
1648c685083a
Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1065 dd 10100101 and_ixl |
1648c685083a
Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1066 and ix a a |
1648c685083a
Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1067 update_flags SZYH1PXN0C0 |
1648c685083a
Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1068 |
1648c685083a
Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1069 fd 10100100 and_iyh |
1648c685083a
Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1070 lsr iy 8 scratch1 |
1648c685083a
Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1071 and scratch1 a a |
1648c685083a
Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1072 update_flags SZYH1PXN0C0 |
1648c685083a
Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1073 |
1648c685083a
Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1074 fd 10100101 and_iyl |
1648c685083a
Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1075 and iy a a |
1648c685083a
Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1076 update_flags SZYH1PXN0C0 |
1648c685083a
Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1077 |
1706
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1078 10100110 and_hl |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1079 z80_fetch_hl |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1080 and a scratch1 a |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1081 update_flags SZYH1PXN0C0 |
1720
1648c685083a
Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1082 |
1648c685083a
Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1083 dd 10100110 and_ixd |
1648c685083a
Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1084 z80_fetch_index ix |
1648c685083a
Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1085 and a scratch1 a |
1648c685083a
Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1086 update_flags SZYH1PXN0C0 |
1648c685083a
Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1087 |
1648c685083a
Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1088 fd 10100110 and_iyd |
1648c685083a
Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1089 z80_fetch_index iy |
1648c685083a
Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1090 and a scratch1 a |
1648c685083a
Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1091 update_flags SZYH1PXN0C0 |
1706
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1092 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1093 11100110 and_immed |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1094 z80_fetch_immed |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1095 and a scratch1 a |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1096 update_flags SZYH1PXN0C0 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1097 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1098 10110RRR or_reg |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1099 or a main.R a |
1714
e170a0f75c4f
fix half-carry for or and xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1712
diff
changeset
|
1100 update_flags SZYH0PXN0C0 |
1706
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1101 |
1720
1648c685083a
Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1102 dd 10110100 or_ixh |
1648c685083a
Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1103 lsr ix 8 scratch1 |
1648c685083a
Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1104 or scratch1 a a |
1648c685083a
Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1105 update_flags SZYH0PXN0C0 |
1648c685083a
Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1106 |
1648c685083a
Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1107 dd 10110101 or_ixl |
1648c685083a
Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1108 or ix a a |
1648c685083a
Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1109 update_flags SZYH0PXN0C0 |
1648c685083a
Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1110 |
1648c685083a
Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1111 fd 10110100 or_iyh |
1648c685083a
Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1112 lsr iy 8 scratch1 |
1648c685083a
Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1113 or scratch1 a a |
1648c685083a
Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1114 update_flags SZYH0PXN0C0 |
1648c685083a
Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1115 |
1648c685083a
Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1116 fd 10110101 or_iyl |
1648c685083a
Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1117 or iy a a |
1648c685083a
Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1118 update_flags SZYH0PXN0C0 |
1648c685083a
Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1119 |
1706
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1120 10110110 or_hl |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1121 z80_fetch_hl |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1122 or a scratch1 a |
1714
e170a0f75c4f
fix half-carry for or and xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1712
diff
changeset
|
1123 update_flags SZYH0PXN0C0 |
1720
1648c685083a
Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1124 |
1648c685083a
Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1125 dd 10110110 or_ixd |
1648c685083a
Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1126 z80_fetch_index ix |
1648c685083a
Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1127 or a scratch1 a |
1648c685083a
Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1128 update_flags SZYH0PXN0C0 |
1648c685083a
Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1129 |
1648c685083a
Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1130 fd 10110110 or_iyd |
1648c685083a
Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1131 z80_fetch_index iy |
1648c685083a
Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1132 or a scratch1 a |
1648c685083a
Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1133 update_flags SZYH0PXN0C0 |
1706
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1134 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1135 11110110 or_immed |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1136 z80_fetch_immed |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1137 or a scratch1 a |
1714
e170a0f75c4f
fix half-carry for or and xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1712
diff
changeset
|
1138 update_flags SZYH0PXN0C0 |
1706
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1139 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1140 10101RRR xor_reg |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1141 xor a main.R a |
1714
e170a0f75c4f
fix half-carry for or and xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1712
diff
changeset
|
1142 update_flags SZYH0PXN0C0 |
1706
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1143 |
1720
1648c685083a
Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1144 dd 10101100 xor_ixh |
1648c685083a
Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1145 lsr ix 8 scratch1 |
1648c685083a
Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1146 xor scratch1 a a |
1648c685083a
Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1147 update_flags SZYH0PXN0C0 |
1648c685083a
Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1148 |
1648c685083a
Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1149 dd 10101101 xor_ixl |
1648c685083a
Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1150 xor ix a a |
1648c685083a
Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1151 update_flags SZYH0PXN0C0 |
1648c685083a
Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1152 |
1648c685083a
Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1153 fd 10101100 xor_iyh |
1648c685083a
Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1154 lsr iy 8 scratch1 |
1648c685083a
Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1155 xor scratch1 a a |
1648c685083a
Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1156 update_flags SZYH0PXN0C0 |
1648c685083a
Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1157 |
1648c685083a
Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1158 fd 10101101 xor_iyl |
1648c685083a
Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1159 xor iy a a |
1648c685083a
Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1160 update_flags SZYH0PXN0C0 |
1648c685083a
Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1161 |
1706
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1162 10101110 xor_hl |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1163 z80_fetch_hl |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1164 xor a scratch1 a |
1714
e170a0f75c4f
fix half-carry for or and xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1712
diff
changeset
|
1165 update_flags SZYH0PXN0C0 |
1720
1648c685083a
Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1166 |
1648c685083a
Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1167 dd 10101110 xor_ixd |
1648c685083a
Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1168 z80_fetch_index ix |
1648c685083a
Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1169 xor a scratch1 a |
1648c685083a
Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1170 update_flags SZYH0PXN0C0 |
1648c685083a
Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1171 |
1648c685083a
Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1172 fd 10101110 xor_iyd |
1648c685083a
Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1173 z80_fetch_index iy |
1648c685083a
Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1174 xor a scratch1 a |
1648c685083a
Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1175 update_flags SZYH0PXN0C0 |
1706
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1176 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1177 11101110 xor_immed |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1178 z80_fetch_immed |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1179 xor a scratch1 a |
1714
e170a0f75c4f
fix half-carry for or and xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1712
diff
changeset
|
1180 update_flags SZYH0PXN0C0 |
1706
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1181 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1182 10111RRR cp_reg |
1719
fb5ae8c20b85
Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1718
diff
changeset
|
1183 mov main.R last_flag_result |
1706
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1184 cmp main.R a |
1719
fb5ae8c20b85
Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1718
diff
changeset
|
1185 update_flags SZHVN1C |
fb5ae8c20b85
Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1718
diff
changeset
|
1186 |
fb5ae8c20b85
Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1718
diff
changeset
|
1187 dd 10111100 cp_ixh |
1725
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1724
diff
changeset
|
1188 local tmp 8 |
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1724
diff
changeset
|
1189 lsr ix 8 tmp |
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1724
diff
changeset
|
1190 mov tmp last_flag_result |
1719
fb5ae8c20b85
Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1718
diff
changeset
|
1191 cmp last_flag_result a |
fb5ae8c20b85
Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1718
diff
changeset
|
1192 update_flags SZHVN1C |
fb5ae8c20b85
Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1718
diff
changeset
|
1193 |
fb5ae8c20b85
Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1718
diff
changeset
|
1194 dd 10111101 cp_ixl |
1725
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1724
diff
changeset
|
1195 local tmp 8 |
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1724
diff
changeset
|
1196 mov ix tmp |
1719
fb5ae8c20b85
Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1718
diff
changeset
|
1197 mov ix last_flag_result |
1725
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1724
diff
changeset
|
1198 cmp tmp a |
1719
fb5ae8c20b85
Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1718
diff
changeset
|
1199 update_flags SZHVN1C |
fb5ae8c20b85
Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1718
diff
changeset
|
1200 |
fb5ae8c20b85
Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1718
diff
changeset
|
1201 fd 10111100 cp_iyh |
1725
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1724
diff
changeset
|
1202 local tmp 8 |
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1724
diff
changeset
|
1203 lsr iy 8 tmp |
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1724
diff
changeset
|
1204 mov tmp last_flag_result |
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1724
diff
changeset
|
1205 cmp tmp a |
1719
fb5ae8c20b85
Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1718
diff
changeset
|
1206 update_flags SZHVN1C |
fb5ae8c20b85
Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1718
diff
changeset
|
1207 |
fb5ae8c20b85
Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1718
diff
changeset
|
1208 fd 10111101 cp_iyl |
1725
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1724
diff
changeset
|
1209 local tmp 8 |
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1724
diff
changeset
|
1210 mov iy tmp |
1719
fb5ae8c20b85
Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1718
diff
changeset
|
1211 mov iy last_flag_result |
1725
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1724
diff
changeset
|
1212 cmp tmp a |
1719
fb5ae8c20b85
Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1718
diff
changeset
|
1213 update_flags SZHVN1C |
1706
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1214 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1215 10111110 cp_hl |
1725
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1724
diff
changeset
|
1216 local tmp 8 |
1706
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1217 z80_fetch_hl |
1725
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1724
diff
changeset
|
1218 mov scratch1 tmp |
1719
fb5ae8c20b85
Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1718
diff
changeset
|
1219 mov scratch1 last_flag_result |
1725
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1724
diff
changeset
|
1220 cmp tmp a |
1719
fb5ae8c20b85
Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1718
diff
changeset
|
1221 update_flags SZHVN1C |
fb5ae8c20b85
Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1718
diff
changeset
|
1222 |
fb5ae8c20b85
Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1718
diff
changeset
|
1223 dd 10111110 cp_ixd |
1725
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1724
diff
changeset
|
1224 local tmp 8 |
1719
fb5ae8c20b85
Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1718
diff
changeset
|
1225 z80_fetch_index ix |
1725
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1724
diff
changeset
|
1226 mov scratch1 tmp |
1719
fb5ae8c20b85
Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1718
diff
changeset
|
1227 mov scratch1 last_flag_result |
1725
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1724
diff
changeset
|
1228 cmp tmp a |
1719
fb5ae8c20b85
Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1718
diff
changeset
|
1229 update_flags SZHVN1C |
fb5ae8c20b85
Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1718
diff
changeset
|
1230 |
fb5ae8c20b85
Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1718
diff
changeset
|
1231 fd 10111110 cp_iyd |
1725
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1724
diff
changeset
|
1232 local tmp 8 |
1719
fb5ae8c20b85
Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1718
diff
changeset
|
1233 z80_fetch_index iy |
1725
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1724
diff
changeset
|
1234 mov scratch1 tmp |
1719
fb5ae8c20b85
Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1718
diff
changeset
|
1235 mov scratch1 last_flag_result |
1725
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1724
diff
changeset
|
1236 cmp tmp a |
1719
fb5ae8c20b85
Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1718
diff
changeset
|
1237 update_flags SZHVN1C |
1706
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1238 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1239 11111110 cp_immed |
1725
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1724
diff
changeset
|
1240 local tmp 8 |
1706
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1241 z80_fetch_immed |
1725
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1724
diff
changeset
|
1242 mov scratch1 tmp |
1719
fb5ae8c20b85
Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1718
diff
changeset
|
1243 mov scratch1 last_flag_result |
1725
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1724
diff
changeset
|
1244 cmp tmp a |
1719
fb5ae8c20b85
Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1718
diff
changeset
|
1245 update_flags SZHVN1C |
1706
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1246 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1247 00RRR100 inc_reg |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1248 add 1 main.R main.R |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1249 update_flags SZYHVXN0 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1250 |
1718
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
1251 dd 00100100 inc_ixh |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
1252 add 0x100 ix ix |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
1253 update_flags SZYHVXN0 |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
1254 |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
1255 dd 00101100 inc_ixl |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
1256 local tmp 8 |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
1257 mov ix tmp |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
1258 add 1 tmp tmp |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
1259 update_flags SZYHVXN0 |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
1260 and 0xFF00 ix ix |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
1261 or tmp ix ix |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
1262 |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
1263 fd 00100100 inc_iyh |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
1264 add 0x100 iy iy |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
1265 update_flags SZYHVXN0 |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
1266 |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
1267 fd 00101100 inc_iyl |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
1268 local tmp 8 |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
1269 mov iy tmp |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
1270 add 1 tmp tmp |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
1271 update_flags SZYHVXN0 |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
1272 and 0xFF00 iy iy |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
1273 or tmp iy iy |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
1274 |
1706
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1275 00110100 inc_hl |
1717
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1276 local tmp 8 |
1706
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1277 z80_fetch_hl |
1717
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1278 #TODO: Either make DSL compiler smart enough to optimize these unnecessary moves out |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1279 #or add some syntax to force a certain size on an operation so they are unnecessary |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1280 mov scratch1 tmp |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1281 add 1 tmp tmp |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1282 update_flags SZYHVXN0 |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1283 mov tmp scratch1 |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1284 z80_store_hl |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1285 |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1286 dd 00110100 inc_ixd |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1287 local tmp 8 |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1288 z80_fetch_index ix |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1289 #TODO: Either make DSL compiler smart enough to optimize these unnecessary moves out |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1290 #or add some syntax to force a certain size on an operation so they are unnecessary |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1291 mov scratch1 tmp |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1292 add 1 tmp tmp |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1293 update_flags SZYHVXN0 |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1294 mov tmp scratch1 |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1295 cycles 1 |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1296 z80_store_index |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1297 |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1298 fd 00110100 inc_iyd |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1299 local tmp 8 |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1300 z80_fetch_index iy |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1301 #TODO: Either make DSL compiler smart enough to optimize these unnecessary moves out |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1302 #or add some syntax to force a certain size on an operation so they are unnecessary |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1303 mov scratch1 tmp |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1304 add 1 tmp tmp |
1706
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1305 update_flags SZYHVXN0 |
1717
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1306 mov tmp scratch1 |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1307 cycles 1 |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1308 z80_store_index |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1309 |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1310 z80_inc_pair |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1311 arg high 8 |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1312 arg low 8 |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1313 local word 16 |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1314 lsl high 8 word |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1315 or low word word |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1316 add 1 word word |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1317 mov word low |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1318 lsr word 8 high |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1319 |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1320 00000011 inc_bc |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1321 z80_inc_pair b c |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1322 |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1323 00010011 inc_de |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1324 z80_inc_pair d e |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1325 |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1326 00100011 inc16_hl |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1327 z80_inc_pair h l |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1328 |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1329 00110011 inc_sp |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1330 add 1 sp sp |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1331 |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1332 dd 00100011 inc_ix |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1333 add 1 ix ix |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1334 |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1335 fd 00100011 inc_iy |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1336 add 1 iy iy |
1706
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1337 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1338 00RRR101 dec_reg |
1717
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1339 sub 1 main.R main.R |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1340 update_flags SZYHVXN1 |
1706
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1341 |
1718
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
1342 dd 00100101 dec_ixh |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
1343 sub 0x100 ix ix |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
1344 update_flags SZYHVXN1 |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
1345 |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
1346 dd 00101101 dec_ixl |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
1347 local tmp 8 |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
1348 mov ix tmp |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
1349 sub 1 tmp tmp |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
1350 update_flags SZYHVXN1 |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
1351 and 0xFF00 ix ix |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
1352 or tmp ix ix |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
1353 |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
1354 fd 00100101 dec_iyh |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
1355 sub 0x100 iy iy |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
1356 update_flags SZYHVXN1 |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
1357 |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
1358 fd 00101101 dec_iyl |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
1359 local tmp 8 |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
1360 mov iy tmp |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
1361 sub 1 tmp tmp |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
1362 update_flags SZYHVXN1 |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
1363 and 0xFF00 iy iy |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
1364 or tmp iy iy |
c7d18b8ec29a
Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1717
diff
changeset
|
1365 |
1706
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1366 00110101 dec_hl |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1367 z80_fetch_hl |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1368 #TODO: fix size |
1717
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1369 sub 1 scratch1 scratch1 |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1370 update_flags SZYHVXN1 |
1706
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1371 z80_store_hl |
1717
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1372 |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1373 dd 00110101 dec_ixd |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1374 local tmp 8 |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1375 z80_fetch_index ix |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1376 #TODO: Either make DSL compiler smart enough to optimize these unnecessary moves out |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1377 #or add some syntax to force a certain size on an operation so they are unnecessary |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1378 mov scratch1 tmp |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1379 sub 1 tmp tmp |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1380 update_flags SZYHVXN1 |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1381 mov tmp scratch1 |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1382 cycles 1 |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1383 z80_store_index |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1384 |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1385 fd 00110101 dec_iyd |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1386 local tmp 8 |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1387 z80_fetch_index iy |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1388 #TODO: Either make DSL compiler smart enough to optimize these unnecessary moves out |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1389 #or add some syntax to force a certain size on an operation so they are unnecessary |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1390 mov scratch1 tmp |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1391 sub 1 tmp tmp |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1392 update_flags SZYHVXN1 |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1393 mov tmp scratch1 |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1394 cycles 1 |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1395 z80_store_index |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1396 |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1397 z80_dec_pair |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1398 arg high 8 |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1399 arg low 8 |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1400 local word 16 |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1401 lsl high 8 word |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1402 or low word word |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1403 sub 1 word word |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1404 mov word low |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1405 lsr word 8 high |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1406 |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1407 00001011 dec_bc |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1408 z80_dec_pair b c |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1409 |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1410 00011011 dec_de |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1411 z80_dec_pair d e |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1412 |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1413 00101011 dec16_hl |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1414 z80_dec_pair h l |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1415 |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1416 00111011 dec_sp |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1417 sub 1 sp sp |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1418 |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1419 dd 00101011 dec_ix |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1420 sub 1 ix ix |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1421 |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1422 fd 00101011 dec_iy |
b11cfa655c61
Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
1423 sub 1 iy iy |
1706
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1424 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1425 00101111 cpl |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1426 not a a |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1427 update_flags YH1XN1 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1428 |
1725
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1724
diff
changeset
|
1429 ed 01DDD100 neg |
1706
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1430 neg a a |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1431 update_flags SZYHVXN1C |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1432 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1433 00111111 ccf |
1725
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1724
diff
changeset
|
1434 local tmp 8 |
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1724
diff
changeset
|
1435 and 0x80 chflags chflags |
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1724
diff
changeset
|
1436 lsr chflags 4 tmp |
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1724
diff
changeset
|
1437 or tmp chflags chflags |
1706
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1438 xor 0x80 chflags chflags |
1725
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1724
diff
changeset
|
1439 update_flags N0 |
1706
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1440 |
1725
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1724
diff
changeset
|
1441 00110111 scf |
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1724
diff
changeset
|
1442 update_flags H0N0C1 |
1706
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1443 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1444 00000000 nop |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1445 |
1725
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1724
diff
changeset
|
1446 01110110 halt |
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1724
diff
changeset
|
1447 sub 1 pc pc |
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1724
diff
changeset
|
1448 |
1706
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1449 11110011 di |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1450 mov 0 iff1 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1451 mov 0 iff2 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1452 #TODO: update interrupt/sync cycle |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1453 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1454 11111011 ei |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1455 mov 1 iff1 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1456 mov 1 iff2 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1457 #TODO: update interrupt/sync cycle |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1458 |
1725
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1724
diff
changeset
|
1459 ed 01D00110 im0 |
1706
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1460 mov 0 imode |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1461 |
1725
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1724
diff
changeset
|
1462 ed 01D10110 im1 |
1706
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1463 mov 1 imode |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1464 |
1725
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1724
diff
changeset
|
1465 ed 01D11110 im2 |
1706
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1466 mov 2 imode |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1467 |
1725
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1724
diff
changeset
|
1468 ed 01D01110 im3 |
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1724
diff
changeset
|
1469 mov 3 imode |
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1724
diff
changeset
|
1470 |
1706
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1471 11000011 jp |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1472 z80_fetch_immed16 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1473 mov wz pc |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1474 |
1726
4f064b575e57
Implemented jp (hl), jp (ix) and jp (iy) in the new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1725
diff
changeset
|
1475 11101001 jp_hl |
4f064b575e57
Implemented jp (hl), jp (ix) and jp (iy) in the new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1725
diff
changeset
|
1476 lsl h 8 pc |
4f064b575e57
Implemented jp (hl), jp (ix) and jp (iy) in the new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1725
diff
changeset
|
1477 or l pc pc |
4f064b575e57
Implemented jp (hl), jp (ix) and jp (iy) in the new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1725
diff
changeset
|
1478 |
4f064b575e57
Implemented jp (hl), jp (ix) and jp (iy) in the new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1725
diff
changeset
|
1479 dd 11101001 jp_ix |
4f064b575e57
Implemented jp (hl), jp (ix) and jp (iy) in the new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1725
diff
changeset
|
1480 mov ix pc |
4f064b575e57
Implemented jp (hl), jp (ix) and jp (iy) in the new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1725
diff
changeset
|
1481 |
4f064b575e57
Implemented jp (hl), jp (ix) and jp (iy) in the new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1725
diff
changeset
|
1482 fd 11101001 jp_iy |
4f064b575e57
Implemented jp (hl), jp (ix) and jp (iy) in the new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1725
diff
changeset
|
1483 mov iy pc |
4f064b575e57
Implemented jp (hl), jp (ix) and jp (iy) in the new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1725
diff
changeset
|
1484 |
1706
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1485 11CCC010 jp_cc |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1486 z80_check_cond C |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1487 z80_fetch_immed16 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1488 if istrue |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1489 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1490 mov wz pc |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1491 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1492 end |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1493 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1494 00011000 jr |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1495 z80_fetch_immed |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1496 #TODO: determine if this updates wz |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1497 sext 16 scratch1 scratch1 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1498 add scratch1 pc pc |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1499 cycles 5 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1500 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1501 001CC000 jr_cc |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1502 z80_check_cond C |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1503 z80_fetch_immed |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1504 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1505 if istrue |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1506 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1507 sext 16 scratch1 scratch1 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1508 add scratch1 pc pc |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1509 cycles 5 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1510 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1511 end |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1512 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1513 00010000 djnz |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1514 cycles 1 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1515 z80_fetch_immed |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1516 sub 1 b b |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1517 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1518 if b |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1519 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1520 sext 16 scratch1 scratch1 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1521 add scratch1 pc pc |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1522 cycles 5 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1523 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1524 end |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1525 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1526 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1527 11001101 call_uncond |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1528 z80_fetch_immed16 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1529 local pch 8 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1530 lsr pc 8 pch |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1531 meta high pch |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1532 meta low pc |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1533 z80_push |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1534 mov wz pc |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1535 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1536 11TTT111 rst |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1537 local pch 8 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1538 lsr pc 8 pch |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1539 meta high pch |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1540 meta low pc |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1541 z80_push |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1542 lsl T 3 scratch1 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1543 mov scratch1 pc |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1544 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1545 11001001 ret |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1546 #TODO: confirm this goes through wz |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1547 local wzh 16 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1548 meta high wzh |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1549 meta low wz |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1550 z80_pop |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1551 lsl wzh 8 wzh |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1552 or wzh wz wz |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1553 mov wz pc |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1554 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1555 11011011 in_abs |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1556 z80_fetch_immed |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1557 ocall io_read8 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1558 mov scratch1 a |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1559 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1560 ed 01RRR000 in_bc |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1561 lsl b 8 scratch1 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1562 or c scratch1 scratch1 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1563 ocall io_read8 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1564 mov scratch1 main.R |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1565 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1566 11010011 out_abs |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1567 z80_fetch_immed |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1568 mov scratch1 scratch2 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1569 mov a scratch1 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1570 ocall io_write8 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1571 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1572 ed 01RRR001 out_bc |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1573 lsl b 8 scratch2 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1574 or c scratch2 scratch2 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1575 mov main.R scratch1 |
c2324849a5e5
Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1576 ocall io_write8 |
1721
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1720
diff
changeset
|
1577 |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1720
diff
changeset
|
1578 00000111 rlca |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1720
diff
changeset
|
1579 rol a 1 a |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1720
diff
changeset
|
1580 update_flags YH0XN0C |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1720
diff
changeset
|
1581 |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1720
diff
changeset
|
1582 00010111 rla |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1720
diff
changeset
|
1583 rlc a 1 a |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1720
diff
changeset
|
1584 update_flags YH0XN0C |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1720
diff
changeset
|
1585 |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1720
diff
changeset
|
1586 00001111 rrca |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1720
diff
changeset
|
1587 ror a 1 a |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1720
diff
changeset
|
1588 update_flags YH0XN0C |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1720
diff
changeset
|
1589 |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1720
diff
changeset
|
1590 00011111 rra |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1720
diff
changeset
|
1591 rrc a 1 a |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1720
diff
changeset
|
1592 update_flags YH0XN0C |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1720
diff
changeset
|
1593 |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1720
diff
changeset
|
1594 cb 00000RRR rlc |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1720
diff
changeset
|
1595 rol main.R 1 main.R |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1720
diff
changeset
|
1596 update_flags SZYH0PXN0C |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1720
diff
changeset
|
1597 |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1720
diff
changeset
|
1598 cb 00000110 rlc_hl |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1720
diff
changeset
|
1599 local tmp 8 |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1720
diff
changeset
|
1600 z80_fetch_hl |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1720
diff
changeset
|
1601 mov scratch1 tmp |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1720
diff
changeset
|
1602 rol tmp 1 tmp |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1720
diff
changeset
|
1603 update_flags SZYH0PXN0C |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1720
diff
changeset
|
1604 mov tmp scratch1 |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1720
diff
changeset
|
1605 z80_store_hl |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1720
diff
changeset
|
1606 |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1720
diff
changeset
|
1607 z80_rlc_index |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1720
diff
changeset
|
1608 arg tmp 8 |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1720
diff
changeset
|
1609 mov wz scratch1 |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1720
diff
changeset
|
1610 ocall read_8 |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1720
diff
changeset
|
1611 cycles 1 |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1720
diff
changeset
|
1612 mov scratch1 tmp |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1720
diff
changeset
|
1613 rol tmp 1 tmp |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1720
diff
changeset
|
1614 update_flags SZYH0PXN0C |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1720
diff
changeset
|
1615 mov tmp scratch1 |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1720
diff
changeset
|
1616 z80_store_index |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1720
diff
changeset
|
1617 |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1720
diff
changeset
|
1618 ddcb 00000110 rlc_ixd |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1720
diff
changeset
|
1619 local tmp 8 |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1720
diff
changeset
|
1620 z80_rlc_index tmp |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1720
diff
changeset
|
1621 |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1720
diff
changeset
|
1622 ddcb 00000RRR rlc_ixd_reg |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1720
diff
changeset
|
1623 z80_rlc_index main.R |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1720
diff
changeset
|
1624 |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1720
diff
changeset
|
1625 fdcb 00000110 rlc_iyd |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1720
diff
changeset
|
1626 local tmp 8 |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1720
diff
changeset
|
1627 z80_rlc_index tmp |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1720
diff
changeset
|
1628 |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1720
diff
changeset
|
1629 fdcb 00000RRR rlc_iyd_reg |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1720
diff
changeset
|
1630 z80_rlc_index main.R |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1720
diff
changeset
|
1631 |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1720
diff
changeset
|
1632 cb 00010RRR rl |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1720
diff
changeset
|
1633 rlc main.R 1 main.R |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1720
diff
changeset
|
1634 update_flags SZYH0PXN0C |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1720
diff
changeset
|
1635 |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1720
diff
changeset
|
1636 cb 00010110 rl_hl |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1720
diff
changeset
|
1637 local tmp 8 |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1720
diff
changeset
|
1638 z80_fetch_hl |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1720
diff
changeset
|
1639 mov scratch1 tmp |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1720
diff
changeset
|
1640 rlc tmp 1 tmp |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1720
diff
changeset
|
1641 update_flags SZYH0PXN0C |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1720
diff
changeset
|
1642 mov tmp scratch1 |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1720
diff
changeset
|
1643 z80_store_hl |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1720
diff
changeset
|
1644 |
1722
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
1645 z80_rl_index |
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
1646 arg tmp 8 |
1721
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1720
diff
changeset
|
1647 mov wz scratch1 |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1720
diff
changeset
|
1648 ocall read_8 |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1720
diff
changeset
|
1649 cycles 1 |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1720
diff
changeset
|
1650 mov scratch1 tmp |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1720
diff
changeset
|
1651 rlc tmp 1 tmp |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1720
diff
changeset
|
1652 update_flags SZYH0PXN0C |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1720
diff
changeset
|
1653 mov tmp scratch1 |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1720
diff
changeset
|
1654 z80_store_index |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1720
diff
changeset
|
1655 |
1722
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
1656 ddcb 00010110 rl_ixd |
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
1657 local tmp 8 |
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
1658 z80_rl_index tmp |
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
1659 |
1721
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1720
diff
changeset
|
1660 fdcb 00010110 rl_iyd |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1720
diff
changeset
|
1661 local tmp 8 |
1722
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
1662 z80_rl_index tmp |
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
1663 |
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
1664 |
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
1665 ddcb 00010RRR rl_ixd_reg |
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
1666 z80_rl_index main.R |
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
1667 |
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
1668 fdcb 00010RRR rl_iyd_reg |
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
1669 z80_rl_index main.R |
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
1670 |
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
1671 cb 00001RRR rrc |
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
1672 ror main.R 1 main.R |
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
1673 update_flags SZYH0PXN0C |
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
1674 |
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
1675 cb 00001110 rrc_hl |
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
1676 local tmp 8 |
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
1677 z80_fetch_hl |
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
1678 mov scratch1 tmp |
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
1679 ror tmp 1 tmp |
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
1680 update_flags SZYH0PXN0C |
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
1681 mov tmp scratch1 |
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
1682 z80_store_hl |
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
1683 |
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
1684 z80_rrc_index |
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
1685 arg tmp 8 |
1721
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1720
diff
changeset
|
1686 mov wz scratch1 |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1720
diff
changeset
|
1687 ocall read_8 |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1720
diff
changeset
|
1688 cycles 1 |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1720
diff
changeset
|
1689 mov scratch1 tmp |
1722
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
1690 ror tmp 1 tmp |
1721
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1720
diff
changeset
|
1691 update_flags SZYH0PXN0C |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1720
diff
changeset
|
1692 mov tmp scratch1 |
1722
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
1693 z80_store_index |
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
1694 |
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
1695 ddcb 00001110 rrc_ixd |
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
1696 local tmp 8 |
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
1697 z80_rrc_index tmp |
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
1698 |
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
1699 ddcb 00001RRR rrc_ixd_reg |
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
1700 z80_rrc_index main.R |
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
1701 |
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
1702 fdcb 00001110 rrc_iyd |
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
1703 local tmp 8 |
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
1704 z80_rrc_index tmp |
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
1705 |
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
1706 fdcb 00001RRR rrc_iyd_reg |
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
1707 z80_rrc_index main.R |
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
1708 |
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
1709 cb 00011RRR rr |
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
1710 rrc main.R 1 main.R |
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
1711 update_flags SZYH0PXN0C |
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
1712 |
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
1713 cb 00011110 rr_hl |
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
1714 local tmp 8 |
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
1715 z80_fetch_hl |
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
1716 mov scratch1 tmp |
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
1717 rrc tmp 1 tmp |
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
1718 update_flags SZYH0PXN0C |
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
1719 mov tmp scratch1 |
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
1720 z80_store_hl |
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
1721 |
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
1722 z80_rr_index |
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
1723 arg tmp 8 |
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
1724 mov wz scratch1 |
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
1725 ocall read_8 |
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
1726 cycles 1 |
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
1727 mov scratch1 tmp |
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
1728 rrc tmp 1 tmp |
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
1729 update_flags SZYH0PXN0C |
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
1730 mov tmp scratch1 |
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
1731 z80_store_index |
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
1732 |
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
1733 ddcb 00011110 rr_ixd |
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
1734 local tmp 8 |
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
1735 z80_rr_index tmp |
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
1736 |
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
1737 ddcb 00011RRR rr_ixd_reg |
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
1738 z80_rr_index main.R |
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
1739 |
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
1740 fdcb 00011110 rr_iyd |
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
1741 local tmp 8 |
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
1742 z80_rr_index tmp |
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
1743 |
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
1744 fdcb 00011RRR rr_iyd_reg |
1723
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1745 z80_rr_index main.R |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1746 |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1747 cb 00100RRR sla |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1748 lsl main.R 1 main.R |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1749 update_flags SZYH0PXN0C |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1750 |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1751 cb 00100110 sla_hl |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1752 local tmp 8 |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1753 z80_fetch_hl |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1754 mov scratch1 tmp |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1755 lsl tmp 1 tmp |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1756 update_flags SZYH0PXN0C |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1757 mov tmp scratch1 |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1758 z80_store_hl |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1759 |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1760 z80_sla_index |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1761 arg tmp 8 |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1762 mov wz scratch1 |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1763 ocall read_8 |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1764 cycles 1 |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1765 mov scratch1 tmp |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1766 lsl tmp 1 tmp |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1767 update_flags SZYH0PXN0C |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1768 mov tmp scratch1 |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1769 z80_store_index |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1770 |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1771 ddcb 00100110 sla_ixd |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1772 local tmp 8 |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1773 z80_sla_index tmp |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1774 |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1775 ddcb 00100RRR sla_ixd_reg |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1776 z80_sla_index main.R |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1777 |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1778 fdcb 00100110 sla_iyd |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1779 local tmp 8 |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1780 z80_sla_index tmp |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1781 |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1782 fdcb 00100RRR sla_iyd_reg |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1783 z80_sla_index main.R |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1784 |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1785 cb 00101RRR sra |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1786 asr main.R 1 main.R |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1787 update_flags SZYH0PXN0C |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1788 |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1789 cb 00101110 sra_hl |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1790 local tmp 8 |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1791 z80_fetch_hl |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1792 mov scratch1 tmp |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1793 asr tmp 1 tmp |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1794 update_flags SZYH0PXN0C |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1795 mov tmp scratch1 |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1796 z80_store_hl |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1797 |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1798 z80_sra_index |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1799 arg tmp 8 |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1800 mov wz scratch1 |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1801 ocall read_8 |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1802 cycles 1 |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1803 mov scratch1 tmp |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1804 asr tmp 1 tmp |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1805 update_flags SZYH0PXN0C |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1806 mov tmp scratch1 |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1807 z80_store_index |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1808 |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1809 ddcb 00101110 sra_ixd |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1810 local tmp 8 |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1811 z80_sra_index tmp |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1812 |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1813 ddcb 00101RRR sra_ixd_reg |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1814 z80_sra_index main.R |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1815 |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1816 fdcb 00101110 sra_iyd |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1817 local tmp 8 |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1818 z80_sra_index tmp |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1819 |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1820 fdcb 00101RRR sra_iyd_reg |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1821 z80_sra_index main.R |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1822 |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1823 cb 00110RRR sll |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1824 lsl main.R 1 main.R |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1825 update_flags SZ0YH0XN0C |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1826 or 1 main.R main.R |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1827 update_flags P |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1828 |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1829 cb 00110110 sll_hl |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1830 local tmp 8 |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1831 z80_fetch_hl |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1832 mov scratch1 tmp |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1833 lsl tmp 1 tmp |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1834 update_flags SZ0YH0XN0C |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1835 or 1 tmp tmp |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1836 update_flags P |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1837 mov tmp scratch1 |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1838 z80_store_hl |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1839 |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1840 z80_sll_index |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1841 arg tmp 8 |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1842 mov wz scratch1 |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1843 ocall read_8 |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1844 cycles 1 |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1845 mov scratch1 tmp |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1846 lsl tmp 1 tmp |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1847 update_flags SZ0YH0XN0C |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1848 or 1 tmp tmp |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1849 update_flags P |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1850 mov tmp scratch1 |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1851 z80_store_index |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1852 |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1853 ddcb 00110110 sll_ixd |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1854 local tmp 8 |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1855 z80_sll_index tmp |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1856 |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1857 ddcb 00110RRR sll_ixd_reg |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1858 z80_sll_index main.R |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1859 |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1860 fdcb 00110110 sll_iyd |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1861 local tmp 8 |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1862 z80_sll_index tmp |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1863 |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1864 fdcb 00110RRR sll_iyd_reg |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1865 z80_sll_index main.R |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1866 |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1867 cb 00111RRR srl |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1868 lsr main.R 1 main.R |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1869 update_flags SZYH0PXN0C |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1870 |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1871 cb 00111110 srl_hl |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1872 local tmp 8 |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1873 z80_fetch_hl |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1874 mov scratch1 tmp |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1875 lsr tmp 1 tmp |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1876 update_flags SZYH0PXN0C |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1877 mov tmp scratch1 |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1878 z80_store_hl |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1879 |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1880 z80_srl_index |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1881 arg tmp 8 |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1882 mov wz scratch1 |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1883 ocall read_8 |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1884 cycles 1 |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1885 mov scratch1 tmp |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1886 lsr tmp 1 tmp |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1887 update_flags SZYH0PXN0C |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1888 mov tmp scratch1 |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1889 z80_store_index |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1890 |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1891 ddcb 00111110 srl_ixd |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1892 local tmp 8 |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1893 z80_srl_index tmp |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1894 |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1895 ddcb 00111RRR srl_ixd_reg |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1896 z80_srl_index main.R |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1897 |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1898 fdcb 00111110 srl_iyd |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1899 local tmp 8 |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1900 z80_srl_index tmp |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1901 |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
1902 fdcb 00111RRR srl_iyd_reg |
1727
9ea0b4cc8f02
Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents:
1726
diff
changeset
|
1903 z80_srl_index main.R |
9ea0b4cc8f02
Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents:
1726
diff
changeset
|
1904 |
9ea0b4cc8f02
Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents:
1726
diff
changeset
|
1905 cb 01BBBRRR bit_reg |
9ea0b4cc8f02
Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents:
1726
diff
changeset
|
1906 local tmp 8 |
9ea0b4cc8f02
Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents:
1726
diff
changeset
|
1907 lsl 1 B tmp |
9ea0b4cc8f02
Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents:
1726
diff
changeset
|
1908 mov main.R last_flag_result |
9ea0b4cc8f02
Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents:
1726
diff
changeset
|
1909 and main.R tmp tmp |
9ea0b4cc8f02
Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents:
1726
diff
changeset
|
1910 update_flags SZH1PN0 |
9ea0b4cc8f02
Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents:
1726
diff
changeset
|
1911 |
9ea0b4cc8f02
Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents:
1726
diff
changeset
|
1912 cb 01BBB110 bit_hl |
9ea0b4cc8f02
Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents:
1726
diff
changeset
|
1913 local tmp 8 |
9ea0b4cc8f02
Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents:
1726
diff
changeset
|
1914 z80_fetch_hl |
9ea0b4cc8f02
Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents:
1726
diff
changeset
|
1915 lsl 1 B tmp |
9ea0b4cc8f02
Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents:
1726
diff
changeset
|
1916 lsr wz 8 last_flag_result |
9ea0b4cc8f02
Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents:
1726
diff
changeset
|
1917 and scratch1 tmp tmp |
9ea0b4cc8f02
Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents:
1726
diff
changeset
|
1918 update_flags SZH1PN0 |
9ea0b4cc8f02
Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents:
1726
diff
changeset
|
1919 |
9ea0b4cc8f02
Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents:
1726
diff
changeset
|
1920 |
9ea0b4cc8f02
Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents:
1726
diff
changeset
|
1921 ddcb 01BBBRRR bit_ixd |
9ea0b4cc8f02
Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents:
1726
diff
changeset
|
1922 local tmp 8 |
9ea0b4cc8f02
Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents:
1726
diff
changeset
|
1923 mov wz scratch1 |
9ea0b4cc8f02
Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents:
1726
diff
changeset
|
1924 ocall read_8 |
9ea0b4cc8f02
Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents:
1726
diff
changeset
|
1925 cycles 1 |
9ea0b4cc8f02
Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents:
1726
diff
changeset
|
1926 lsl 1 B tmp |
9ea0b4cc8f02
Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents:
1726
diff
changeset
|
1927 lsr wz 8 last_flag_result |
9ea0b4cc8f02
Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents:
1726
diff
changeset
|
1928 and scratch1 tmp tmp |
9ea0b4cc8f02
Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents:
1726
diff
changeset
|
1929 update_flags SZH1PN0 |
9ea0b4cc8f02
Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents:
1726
diff
changeset
|
1930 |
9ea0b4cc8f02
Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents:
1726
diff
changeset
|
1931 fdcb 01BBBRRR bit_iyd |
9ea0b4cc8f02
Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents:
1726
diff
changeset
|
1932 local tmp 8 |
9ea0b4cc8f02
Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents:
1726
diff
changeset
|
1933 mov wz scratch1 |
9ea0b4cc8f02
Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents:
1726
diff
changeset
|
1934 ocall read_8 |
9ea0b4cc8f02
Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents:
1726
diff
changeset
|
1935 cycles 1 |
9ea0b4cc8f02
Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents:
1726
diff
changeset
|
1936 lsl 1 B tmp |
9ea0b4cc8f02
Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents:
1726
diff
changeset
|
1937 lsr wz 8 last_flag_result |
9ea0b4cc8f02
Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents:
1726
diff
changeset
|
1938 and scratch1 tmp tmp |
1728
b0e01e64d76d
Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1727
diff
changeset
|
1939 update_flags SZH1PN0 |
b0e01e64d76d
Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1727
diff
changeset
|
1940 |
b0e01e64d76d
Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1727
diff
changeset
|
1941 cb 10BBBRRR res_reg |
b0e01e64d76d
Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1727
diff
changeset
|
1942 local tmp 8 |
b0e01e64d76d
Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1727
diff
changeset
|
1943 lsl 1 B tmp |
b0e01e64d76d
Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1727
diff
changeset
|
1944 not tmp tmp |
b0e01e64d76d
Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1727
diff
changeset
|
1945 and main.R tmp main.R |
b0e01e64d76d
Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1727
diff
changeset
|
1946 |
b0e01e64d76d
Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1727
diff
changeset
|
1947 cb 10BBB110 res_hl |
b0e01e64d76d
Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1727
diff
changeset
|
1948 z80_fetch_hl |
b0e01e64d76d
Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1727
diff
changeset
|
1949 cycles 1 |
b0e01e64d76d
Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1727
diff
changeset
|
1950 local tmp 8 |
b0e01e64d76d
Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1727
diff
changeset
|
1951 lsl 1 B tmp |
b0e01e64d76d
Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1727
diff
changeset
|
1952 not tmp tmp |
b0e01e64d76d
Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1727
diff
changeset
|
1953 and scratch1 tmp scratch1 |
b0e01e64d76d
Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1727
diff
changeset
|
1954 z80_store_hl |
b0e01e64d76d
Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1727
diff
changeset
|
1955 |
b0e01e64d76d
Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1727
diff
changeset
|
1956 z80_res_index |
b0e01e64d76d
Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1727
diff
changeset
|
1957 arg bit 8 |
b0e01e64d76d
Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1727
diff
changeset
|
1958 arg tmp 8 |
b0e01e64d76d
Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1727
diff
changeset
|
1959 lsl 1 bit tmp |
b0e01e64d76d
Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1727
diff
changeset
|
1960 not tmp tmp |
b0e01e64d76d
Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1727
diff
changeset
|
1961 mov wz scratch1 |
b0e01e64d76d
Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1727
diff
changeset
|
1962 ocall read_8 |
b0e01e64d76d
Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1727
diff
changeset
|
1963 cycles 1 |
b0e01e64d76d
Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1727
diff
changeset
|
1964 and scratch1 tmp tmp |
b0e01e64d76d
Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1727
diff
changeset
|
1965 mov tmp scratch1 |
b0e01e64d76d
Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1727
diff
changeset
|
1966 z80_store_index |
b0e01e64d76d
Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1727
diff
changeset
|
1967 |
b0e01e64d76d
Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1727
diff
changeset
|
1968 ddcb 10BBB110 res_ixd |
b0e01e64d76d
Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1727
diff
changeset
|
1969 local tmp 8 |
b0e01e64d76d
Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1727
diff
changeset
|
1970 z80_res_index B tmp |
b0e01e64d76d
Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1727
diff
changeset
|
1971 |
b0e01e64d76d
Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1727
diff
changeset
|
1972 ddcb 10BBBRRR res_ixd_reg |
b0e01e64d76d
Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1727
diff
changeset
|
1973 z80_res_index B main.R |
b0e01e64d76d
Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1727
diff
changeset
|
1974 |
b0e01e64d76d
Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1727
diff
changeset
|
1975 fdcb 10BBB110 res_iyd |
b0e01e64d76d
Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1727
diff
changeset
|
1976 local tmp 8 |
b0e01e64d76d
Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1727
diff
changeset
|
1977 z80_res_index B tmp |
b0e01e64d76d
Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1727
diff
changeset
|
1978 |
b0e01e64d76d
Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1727
diff
changeset
|
1979 fdcb 10BBBRRR res_iyd_reg |
1729
bd13d017f16f
Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1728
diff
changeset
|
1980 z80_res_index B main.R |
bd13d017f16f
Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1728
diff
changeset
|
1981 |
bd13d017f16f
Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1728
diff
changeset
|
1982 cb 11BBBRRR set_reg |
bd13d017f16f
Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1728
diff
changeset
|
1983 local tmp 8 |
bd13d017f16f
Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1728
diff
changeset
|
1984 lsl 1 B tmp |
bd13d017f16f
Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1728
diff
changeset
|
1985 or main.R tmp main.R |
bd13d017f16f
Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1728
diff
changeset
|
1986 |
bd13d017f16f
Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1728
diff
changeset
|
1987 cb 11BBB110 set_hl |
bd13d017f16f
Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1728
diff
changeset
|
1988 z80_fetch_hl |
bd13d017f16f
Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1728
diff
changeset
|
1989 cycles 1 |
bd13d017f16f
Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1728
diff
changeset
|
1990 local tmp 8 |
bd13d017f16f
Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1728
diff
changeset
|
1991 lsl 1 B tmp |
bd13d017f16f
Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1728
diff
changeset
|
1992 or scratch1 tmp scratch1 |
bd13d017f16f
Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1728
diff
changeset
|
1993 z80_store_hl |
bd13d017f16f
Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1728
diff
changeset
|
1994 |
bd13d017f16f
Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1728
diff
changeset
|
1995 z80_set_index |
bd13d017f16f
Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1728
diff
changeset
|
1996 arg bit 8 |
bd13d017f16f
Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1728
diff
changeset
|
1997 arg tmp 8 |
bd13d017f16f
Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1728
diff
changeset
|
1998 lsl 1 bit tmp |
bd13d017f16f
Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1728
diff
changeset
|
1999 mov wz scratch1 |
bd13d017f16f
Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1728
diff
changeset
|
2000 ocall read_8 |
bd13d017f16f
Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1728
diff
changeset
|
2001 cycles 1 |
bd13d017f16f
Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1728
diff
changeset
|
2002 or scratch1 tmp tmp |
bd13d017f16f
Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1728
diff
changeset
|
2003 mov tmp scratch1 |
bd13d017f16f
Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1728
diff
changeset
|
2004 z80_store_index |
bd13d017f16f
Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1728
diff
changeset
|
2005 |
bd13d017f16f
Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1728
diff
changeset
|
2006 ddcb 11BBB110 set_ixd |
bd13d017f16f
Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1728
diff
changeset
|
2007 local tmp 8 |
bd13d017f16f
Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1728
diff
changeset
|
2008 z80_set_index B tmp |
bd13d017f16f
Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1728
diff
changeset
|
2009 |
bd13d017f16f
Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1728
diff
changeset
|
2010 ddcb 11BBBRRR set_ixd_reg |
bd13d017f16f
Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1728
diff
changeset
|
2011 z80_set_index B main.R |
bd13d017f16f
Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1728
diff
changeset
|
2012 |
bd13d017f16f
Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1728
diff
changeset
|
2013 fdcb 11BBB110 set_iyd |
bd13d017f16f
Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1728
diff
changeset
|
2014 local tmp 8 |
bd13d017f16f
Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1728
diff
changeset
|
2015 z80_set_index B tmp |
bd13d017f16f
Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1728
diff
changeset
|
2016 |
bd13d017f16f
Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1728
diff
changeset
|
2017 fdcb 11BBBRRR set_iyd_reg |
1733
1f0a86f5e055
Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1732
diff
changeset
|
2018 z80_set_index B main.R |
1f0a86f5e055
Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1732
diff
changeset
|
2019 |
1f0a86f5e055
Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1732
diff
changeset
|
2020 ed 10100000 ldi |
1f0a86f5e055
Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1732
diff
changeset
|
2021 local tmp 16 |
1f0a86f5e055
Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1732
diff
changeset
|
2022 local tmp8 8 |
1f0a86f5e055
Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1732
diff
changeset
|
2023 lsl h 8 tmp |
1f0a86f5e055
Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1732
diff
changeset
|
2024 or l tmp tmp |
1f0a86f5e055
Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1732
diff
changeset
|
2025 mov tmp scratch1 |
1f0a86f5e055
Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1732
diff
changeset
|
2026 add 1 tmp tmp |
1f0a86f5e055
Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1732
diff
changeset
|
2027 mov tmp l |
1f0a86f5e055
Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1732
diff
changeset
|
2028 lsr tmp 8 h |
1f0a86f5e055
Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1732
diff
changeset
|
2029 ocall read_8 |
1f0a86f5e055
Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1732
diff
changeset
|
2030 cycles 1 |
1f0a86f5e055
Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1732
diff
changeset
|
2031 |
1f0a86f5e055
Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1732
diff
changeset
|
2032 add a scratch1 tmp8 |
1f0a86f5e055
Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1732
diff
changeset
|
2033 update_flags H0XN0 |
1f0a86f5e055
Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1732
diff
changeset
|
2034 |
1f0a86f5e055
Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1732
diff
changeset
|
2035 and 0x2 tmp8 tmp8 |
1f0a86f5e055
Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1732
diff
changeset
|
2036 lsl 4 tmp8 tmp8 |
1f0a86f5e055
Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1732
diff
changeset
|
2037 and 0x88 last_flag_result last_flag_result |
1f0a86f5e055
Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1732
diff
changeset
|
2038 or tmp8 last_flag_result last_flag_result |
1f0a86f5e055
Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1732
diff
changeset
|
2039 |
1f0a86f5e055
Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1732
diff
changeset
|
2040 lsl d 8 tmp |
1f0a86f5e055
Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1732
diff
changeset
|
2041 or e tmp tmp |
1f0a86f5e055
Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1732
diff
changeset
|
2042 mov tmp scratch2 |
1f0a86f5e055
Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1732
diff
changeset
|
2043 add 1 tmp tmp |
1f0a86f5e055
Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1732
diff
changeset
|
2044 mov tmp e |
1f0a86f5e055
Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1732
diff
changeset
|
2045 lsr tmp 8 d |
1f0a86f5e055
Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1732
diff
changeset
|
2046 ocall write_8 |
1f0a86f5e055
Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1732
diff
changeset
|
2047 |
1f0a86f5e055
Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1732
diff
changeset
|
2048 lsl b 8 tmp |
1f0a86f5e055
Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1732
diff
changeset
|
2049 or c tmp tmp |
1f0a86f5e055
Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1732
diff
changeset
|
2050 sub 1 tmp tmp |
1f0a86f5e055
Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1732
diff
changeset
|
2051 |
1f0a86f5e055
Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1732
diff
changeset
|
2052 mov tmp c |
1f0a86f5e055
Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1732
diff
changeset
|
2053 lsr tmp 8 b |
1f0a86f5e055
Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1732
diff
changeset
|
2054 mov c pvflag |
1f0a86f5e055
Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1732
diff
changeset
|
2055 or b pvflag pvflag |
1f0a86f5e055
Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1732
diff
changeset
|
2056 |
1f0a86f5e055
Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1732
diff
changeset
|
2057 |
1f0a86f5e055
Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1732
diff
changeset
|
2058 |
1f0a86f5e055
Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1732
diff
changeset
|
2059 cycles 5 |
1f0a86f5e055
Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1732
diff
changeset
|
2060 |